source: rtos_arduino/trunk/arduino_lib/hardware/tools/CMSIS/Device/ATMEL/samd21/include/component/ac.h@ 136

Last change on this file since 136 was 136, checked in by ertl-honda, 8 years ago

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1/**
2 * \file
3 *
4 * \brief Component description for AC
5 *
6 * Copyright (c) 2014 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 *
42 */
43
44#ifndef _SAMD21_AC_COMPONENT_
45#define _SAMD21_AC_COMPONENT_
46
47/* ========================================================================== */
48/** SOFTWARE API DEFINITION FOR AC */
49/* ========================================================================== */
50/** \addtogroup SAMD21_AC Analog Comparators */
51/*@{*/
52
53#define AC_U2205
54#define REV_AC 0x111
55
56/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */
57#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
58typedef union {
59 struct {
60 uint8_t SWRST:1; /*!< bit: 0 Software Reset */
61 uint8_t ENABLE:1; /*!< bit: 1 Enable */
62 uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
63 uint8_t :4; /*!< bit: 3.. 6 Reserved */
64 uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */
65 } bit; /*!< Structure used for bit access */
66 uint8_t reg; /*!< Type used for register access */
67} AC_CTRLA_Type;
68#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
69
70#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */
71#define AC_CTRLA_RESETVALUE 0x00 /**< \brief (AC_CTRLA reset_value) Control A */
72
73#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */
74#define AC_CTRLA_SWRST (0x1u << AC_CTRLA_SWRST_Pos)
75#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */
76#define AC_CTRLA_ENABLE (0x1u << AC_CTRLA_ENABLE_Pos)
77#define AC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (AC_CTRLA) Run in Standby */
78#define AC_CTRLA_RUNSTDBY_Msk (0x1u << AC_CTRLA_RUNSTDBY_Pos)
79#define AC_CTRLA_RUNSTDBY(value) ((AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos)))
80#define AC_CTRLA_LPMUX_Pos 7 /**< \brief (AC_CTRLA) Low-Power Mux */
81#define AC_CTRLA_LPMUX (0x1u << AC_CTRLA_LPMUX_Pos)
82#define AC_CTRLA_MASK 0x87u /**< \brief (AC_CTRLA) MASK Register */
83
84/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */
85#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
86typedef union {
87 struct {
88 uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
89 uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
90 uint8_t :6; /*!< bit: 2.. 7 Reserved */
91 } bit; /*!< Structure used for bit access */
92 struct {
93 uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
94 uint8_t :6; /*!< bit: 2.. 7 Reserved */
95 } vec; /*!< Structure used for vec access */
96 uint8_t reg; /*!< Type used for register access */
97} AC_CTRLB_Type;
98#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
99
100#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */
101#define AC_CTRLB_RESETVALUE 0x00 /**< \brief (AC_CTRLB reset_value) Control B */
102
103#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */
104#define AC_CTRLB_START0 (1 << AC_CTRLB_START0_Pos)
105#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */
106#define AC_CTRLB_START1 (1 << AC_CTRLB_START1_Pos)
107#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */
108#define AC_CTRLB_START_Msk (0x3u << AC_CTRLB_START_Pos)
109#define AC_CTRLB_START(value) ((AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)))
110#define AC_CTRLB_MASK 0x03u /**< \brief (AC_CTRLB) MASK Register */
111
112/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
113#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
114typedef union {
115 struct {
116 uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
117 uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
118 uint16_t :2; /*!< bit: 2.. 3 Reserved */
119 uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
120 uint16_t :3; /*!< bit: 5.. 7 Reserved */
121 uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */
122 uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */
123 uint16_t :6; /*!< bit: 10..15 Reserved */
124 } bit; /*!< Structure used for bit access */
125 struct {
126 uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
127 uint16_t :2; /*!< bit: 2.. 3 Reserved */
128 uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
129 uint16_t :3; /*!< bit: 5.. 7 Reserved */
130 uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */
131 uint16_t :6; /*!< bit: 10..15 Reserved */
132 } vec; /*!< Structure used for vec access */
133 uint16_t reg; /*!< Type used for register access */
134} AC_EVCTRL_Type;
135#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
136
137#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */
138#define AC_EVCTRL_RESETVALUE 0x0000 /**< \brief (AC_EVCTRL reset_value) Event Control */
139
140#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */
141#define AC_EVCTRL_COMPEO0 (1 << AC_EVCTRL_COMPEO0_Pos)
142#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */
143#define AC_EVCTRL_COMPEO1 (1 << AC_EVCTRL_COMPEO1_Pos)
144#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
145#define AC_EVCTRL_COMPEO_Msk (0x3u << AC_EVCTRL_COMPEO_Pos)
146#define AC_EVCTRL_COMPEO(value) ((AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)))
147#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
148#define AC_EVCTRL_WINEO0 (1 << AC_EVCTRL_WINEO0_Pos)
149#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */
150#define AC_EVCTRL_WINEO_Msk (0x1u << AC_EVCTRL_WINEO_Pos)
151#define AC_EVCTRL_WINEO(value) ((AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)))
152#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input */
153#define AC_EVCTRL_COMPEI0 (1 << AC_EVCTRL_COMPEI0_Pos)
154#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input */
155#define AC_EVCTRL_COMPEI1 (1 << AC_EVCTRL_COMPEI1_Pos)
156#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input */
157#define AC_EVCTRL_COMPEI_Msk (0x3u << AC_EVCTRL_COMPEI_Pos)
158#define AC_EVCTRL_COMPEI(value) ((AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)))
159#define AC_EVCTRL_MASK 0x0313u /**< \brief (AC_EVCTRL) MASK Register */
160
161/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
162#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
163typedef union {
164 struct {
165 uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
166 uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
167 uint8_t :2; /*!< bit: 2.. 3 Reserved */
168 uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
169 uint8_t :3; /*!< bit: 5.. 7 Reserved */
170 } bit; /*!< Structure used for bit access */
171 struct {
172 uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
173 uint8_t :2; /*!< bit: 2.. 3 Reserved */
174 uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
175 uint8_t :3; /*!< bit: 5.. 7 Reserved */
176 } vec; /*!< Structure used for vec access */
177 uint8_t reg; /*!< Type used for register access */
178} AC_INTENCLR_Type;
179#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
180
181#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */
182#define AC_INTENCLR_RESETVALUE 0x00 /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */
183
184#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */
185#define AC_INTENCLR_COMP0 (1 << AC_INTENCLR_COMP0_Pos)
186#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */
187#define AC_INTENCLR_COMP1 (1 << AC_INTENCLR_COMP1_Pos)
188#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
189#define AC_INTENCLR_COMP_Msk (0x3u << AC_INTENCLR_COMP_Pos)
190#define AC_INTENCLR_COMP(value) ((AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)))
191#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
192#define AC_INTENCLR_WIN0 (1 << AC_INTENCLR_WIN0_Pos)
193#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
194#define AC_INTENCLR_WIN_Msk (0x1u << AC_INTENCLR_WIN_Pos)
195#define AC_INTENCLR_WIN(value) ((AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)))
196#define AC_INTENCLR_MASK 0x13u /**< \brief (AC_INTENCLR) MASK Register */
197
198/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
199#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
200typedef union {
201 struct {
202 uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
203 uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
204 uint8_t :2; /*!< bit: 2.. 3 Reserved */
205 uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
206 uint8_t :3; /*!< bit: 5.. 7 Reserved */
207 } bit; /*!< Structure used for bit access */
208 struct {
209 uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
210 uint8_t :2; /*!< bit: 2.. 3 Reserved */
211 uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
212 uint8_t :3; /*!< bit: 5.. 7 Reserved */
213 } vec; /*!< Structure used for vec access */
214 uint8_t reg; /*!< Type used for register access */
215} AC_INTENSET_Type;
216#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
217
218#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */
219#define AC_INTENSET_RESETVALUE 0x00 /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */
220
221#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */
222#define AC_INTENSET_COMP0 (1 << AC_INTENSET_COMP0_Pos)
223#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */
224#define AC_INTENSET_COMP1 (1 << AC_INTENSET_COMP1_Pos)
225#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
226#define AC_INTENSET_COMP_Msk (0x3u << AC_INTENSET_COMP_Pos)
227#define AC_INTENSET_COMP(value) ((AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)))
228#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
229#define AC_INTENSET_WIN0 (1 << AC_INTENSET_WIN0_Pos)
230#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */
231#define AC_INTENSET_WIN_Msk (0x1u << AC_INTENSET_WIN_Pos)
232#define AC_INTENSET_WIN(value) ((AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)))
233#define AC_INTENSET_MASK 0x13u /**< \brief (AC_INTENSET) MASK Register */
234
235/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
236#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
237typedef union {
238 struct {
239 uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
240 uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
241 uint8_t :2; /*!< bit: 2.. 3 Reserved */
242 uint8_t WIN0:1; /*!< bit: 4 Window 0 */
243 uint8_t :3; /*!< bit: 5.. 7 Reserved */
244 } bit; /*!< Structure used for bit access */
245 struct {
246 uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
247 uint8_t :2; /*!< bit: 2.. 3 Reserved */
248 uint8_t WIN:1; /*!< bit: 4 Window x */
249 uint8_t :3; /*!< bit: 5.. 7 Reserved */
250 } vec; /*!< Structure used for vec access */
251 uint8_t reg; /*!< Type used for register access */
252} AC_INTFLAG_Type;
253#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
254
255#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */
256#define AC_INTFLAG_RESETVALUE 0x00 /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */
257
258#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */
259#define AC_INTFLAG_COMP0 (1 << AC_INTFLAG_COMP0_Pos)
260#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */
261#define AC_INTFLAG_COMP1 (1 << AC_INTFLAG_COMP1_Pos)
262#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */
263#define AC_INTFLAG_COMP_Msk (0x3u << AC_INTFLAG_COMP_Pos)
264#define AC_INTFLAG_COMP(value) ((AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)))
265#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */
266#define AC_INTFLAG_WIN0 (1 << AC_INTFLAG_WIN0_Pos)
267#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */
268#define AC_INTFLAG_WIN_Msk (0x1u << AC_INTFLAG_WIN_Pos)
269#define AC_INTFLAG_WIN(value) ((AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)))
270#define AC_INTFLAG_MASK 0x13u /**< \brief (AC_INTFLAG) MASK Register */
271
272/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */
273#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
274typedef union {
275 struct {
276 uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
277 uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
278 uint8_t :2; /*!< bit: 2.. 3 Reserved */
279 uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
280 uint8_t :2; /*!< bit: 6.. 7 Reserved */
281 } bit; /*!< Structure used for bit access */
282 struct {
283 uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
284 uint8_t :6; /*!< bit: 2.. 7 Reserved */
285 } vec; /*!< Structure used for vec access */
286 uint8_t reg; /*!< Type used for register access */
287} AC_STATUSA_Type;
288#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
289
290#define AC_STATUSA_OFFSET 0x08 /**< \brief (AC_STATUSA offset) Status A */
291#define AC_STATUSA_RESETVALUE 0x00 /**< \brief (AC_STATUSA reset_value) Status A */
292
293#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */
294#define AC_STATUSA_STATE0 (1 << AC_STATUSA_STATE0_Pos)
295#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */
296#define AC_STATUSA_STATE1 (1 << AC_STATUSA_STATE1_Pos)
297#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */
298#define AC_STATUSA_STATE_Msk (0x3u << AC_STATUSA_STATE_Pos)
299#define AC_STATUSA_STATE(value) ((AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)))
300#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */
301#define AC_STATUSA_WSTATE0_Msk (0x3u << AC_STATUSA_WSTATE0_Pos)
302#define AC_STATUSA_WSTATE0(value) ((AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)))
303#define AC_STATUSA_WSTATE0_ABOVE_Val 0x0u /**< \brief (AC_STATUSA) Signal is above window */
304#define AC_STATUSA_WSTATE0_INSIDE_Val 0x1u /**< \brief (AC_STATUSA) Signal is inside window */
305#define AC_STATUSA_WSTATE0_BELOW_Val 0x2u /**< \brief (AC_STATUSA) Signal is below window */
306#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos)
307#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos)
308#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos)
309#define AC_STATUSA_MASK 0x33u /**< \brief (AC_STATUSA) MASK Register */
310
311/* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */
312#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
313typedef union {
314 struct {
315 uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
316 uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
317 uint8_t :5; /*!< bit: 2.. 6 Reserved */
318 uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
319 } bit; /*!< Structure used for bit access */
320 struct {
321 uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
322 uint8_t :6; /*!< bit: 2.. 7 Reserved */
323 } vec; /*!< Structure used for vec access */
324 uint8_t reg; /*!< Type used for register access */
325} AC_STATUSB_Type;
326#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
327
328#define AC_STATUSB_OFFSET 0x09 /**< \brief (AC_STATUSB offset) Status B */
329#define AC_STATUSB_RESETVALUE 0x00 /**< \brief (AC_STATUSB reset_value) Status B */
330
331#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */
332#define AC_STATUSB_READY0 (1 << AC_STATUSB_READY0_Pos)
333#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */
334#define AC_STATUSB_READY1 (1 << AC_STATUSB_READY1_Pos)
335#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */
336#define AC_STATUSB_READY_Msk (0x3u << AC_STATUSB_READY_Pos)
337#define AC_STATUSB_READY(value) ((AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)))
338#define AC_STATUSB_SYNCBUSY_Pos 7 /**< \brief (AC_STATUSB) Synchronization Busy */
339#define AC_STATUSB_SYNCBUSY (0x1u << AC_STATUSB_SYNCBUSY_Pos)
340#define AC_STATUSB_MASK 0x83u /**< \brief (AC_STATUSB) MASK Register */
341
342/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */
343#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
344typedef union {
345 struct {
346 uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
347 uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
348 uint8_t :2; /*!< bit: 2.. 3 Reserved */
349 uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
350 uint8_t :2; /*!< bit: 6.. 7 Reserved */
351 } bit; /*!< Structure used for bit access */
352 struct {
353 uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
354 uint8_t :6; /*!< bit: 2.. 7 Reserved */
355 } vec; /*!< Structure used for vec access */
356 uint8_t reg; /*!< Type used for register access */
357} AC_STATUSC_Type;
358#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
359
360#define AC_STATUSC_OFFSET 0x0A /**< \brief (AC_STATUSC offset) Status C */
361#define AC_STATUSC_RESETVALUE 0x00 /**< \brief (AC_STATUSC reset_value) Status C */
362
363#define AC_STATUSC_STATE0_Pos 0 /**< \brief (AC_STATUSC) Comparator 0 Current State */
364#define AC_STATUSC_STATE0 (1 << AC_STATUSC_STATE0_Pos)
365#define AC_STATUSC_STATE1_Pos 1 /**< \brief (AC_STATUSC) Comparator 1 Current State */
366#define AC_STATUSC_STATE1 (1 << AC_STATUSC_STATE1_Pos)
367#define AC_STATUSC_STATE_Pos 0 /**< \brief (AC_STATUSC) Comparator x Current State */
368#define AC_STATUSC_STATE_Msk (0x3u << AC_STATUSC_STATE_Pos)
369#define AC_STATUSC_STATE(value) ((AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos)))
370#define AC_STATUSC_WSTATE0_Pos 4 /**< \brief (AC_STATUSC) Window 0 Current State */
371#define AC_STATUSC_WSTATE0_Msk (0x3u << AC_STATUSC_WSTATE0_Pos)
372#define AC_STATUSC_WSTATE0(value) ((AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos)))
373#define AC_STATUSC_WSTATE0_ABOVE_Val 0x0u /**< \brief (AC_STATUSC) Signal is above window */
374#define AC_STATUSC_WSTATE0_INSIDE_Val 0x1u /**< \brief (AC_STATUSC) Signal is inside window */
375#define AC_STATUSC_WSTATE0_BELOW_Val 0x2u /**< \brief (AC_STATUSC) Signal is below window */
376#define AC_STATUSC_WSTATE0_ABOVE (AC_STATUSC_WSTATE0_ABOVE_Val << AC_STATUSC_WSTATE0_Pos)
377#define AC_STATUSC_WSTATE0_INSIDE (AC_STATUSC_WSTATE0_INSIDE_Val << AC_STATUSC_WSTATE0_Pos)
378#define AC_STATUSC_WSTATE0_BELOW (AC_STATUSC_WSTATE0_BELOW_Val << AC_STATUSC_WSTATE0_Pos)
379#define AC_STATUSC_MASK 0x33u /**< \brief (AC_STATUSC) MASK Register */
380
381/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */
382#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
383typedef union {
384 struct {
385 uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
386 uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
387 uint8_t :5; /*!< bit: 3.. 7 Reserved */
388 } bit; /*!< Structure used for bit access */
389 uint8_t reg; /*!< Type used for register access */
390} AC_WINCTRL_Type;
391#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
392
393#define AC_WINCTRL_OFFSET 0x0C /**< \brief (AC_WINCTRL offset) Window Control */
394#define AC_WINCTRL_RESETVALUE 0x00 /**< \brief (AC_WINCTRL reset_value) Window Control */
395
396#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */
397#define AC_WINCTRL_WEN0 (0x1u << AC_WINCTRL_WEN0_Pos)
398#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
399#define AC_WINCTRL_WINTSEL0_Msk (0x3u << AC_WINCTRL_WINTSEL0_Pos)
400#define AC_WINCTRL_WINTSEL0(value) ((AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)))
401#define AC_WINCTRL_WINTSEL0_ABOVE_Val 0x0u /**< \brief (AC_WINCTRL) Interrupt on signal above window */
402#define AC_WINCTRL_WINTSEL0_INSIDE_Val 0x1u /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
403#define AC_WINCTRL_WINTSEL0_BELOW_Val 0x2u /**< \brief (AC_WINCTRL) Interrupt on signal below window */
404#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val 0x3u /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
405#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos)
406#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
407#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos)
408#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
409#define AC_WINCTRL_MASK 0x07u /**< \brief (AC_WINCTRL) MASK Register */
410
411/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
412#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
413typedef union {
414 struct {
415 uint32_t ENABLE:1; /*!< bit: 0 Enable */
416 uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */
417 uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */
418 uint32_t :1; /*!< bit: 4 Reserved */
419 uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */
420 uint32_t :1; /*!< bit: 7 Reserved */
421 uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
422 uint32_t :1; /*!< bit: 11 Reserved */
423 uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */
424 uint32_t :1; /*!< bit: 14 Reserved */
425 uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
426 uint32_t OUT:2; /*!< bit: 16..17 Output */
427 uint32_t :1; /*!< bit: 18 Reserved */
428 uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */
429 uint32_t :4; /*!< bit: 20..23 Reserved */
430 uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
431 uint32_t :5; /*!< bit: 27..31 Reserved */
432 } bit; /*!< Structure used for bit access */
433 uint32_t reg; /*!< Type used for register access */
434} AC_COMPCTRL_Type;
435#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
436
437#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */
438#define AC_COMPCTRL_RESETVALUE 0x00000000 /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */
439
440#define AC_COMPCTRL_ENABLE_Pos 0 /**< \brief (AC_COMPCTRL) Enable */
441#define AC_COMPCTRL_ENABLE (0x1u << AC_COMPCTRL_ENABLE_Pos)
442#define AC_COMPCTRL_SINGLE_Pos 1 /**< \brief (AC_COMPCTRL) Single-Shot Mode */
443#define AC_COMPCTRL_SINGLE (0x1u << AC_COMPCTRL_SINGLE_Pos)
444#define AC_COMPCTRL_SPEED_Pos 2 /**< \brief (AC_COMPCTRL) Speed Selection */
445#define AC_COMPCTRL_SPEED_Msk (0x3u << AC_COMPCTRL_SPEED_Pos)
446#define AC_COMPCTRL_SPEED(value) ((AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)))
447#define AC_COMPCTRL_SPEED_LOW_Val 0x0u /**< \brief (AC_COMPCTRL) Low speed */
448#define AC_COMPCTRL_SPEED_HIGH_Val 0x1u /**< \brief (AC_COMPCTRL) High speed */
449#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos)
450#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos)
451#define AC_COMPCTRL_INTSEL_Pos 5 /**< \brief (AC_COMPCTRL) Interrupt Selection */
452#define AC_COMPCTRL_INTSEL_Msk (0x3u << AC_COMPCTRL_INTSEL_Pos)
453#define AC_COMPCTRL_INTSEL(value) ((AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)))
454#define AC_COMPCTRL_INTSEL_TOGGLE_Val 0x0u /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
455#define AC_COMPCTRL_INTSEL_RISING_Val 0x1u /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
456#define AC_COMPCTRL_INTSEL_FALLING_Val 0x2u /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
457#define AC_COMPCTRL_INTSEL_EOC_Val 0x3u /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
458#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos)
459#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos)
460#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos)
461#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos)
462#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
463#define AC_COMPCTRL_MUXNEG_Msk (0x7u << AC_COMPCTRL_MUXNEG_Pos)
464#define AC_COMPCTRL_MUXNEG(value) ((AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)))
465#define AC_COMPCTRL_MUXNEG_PIN0_Val 0x0u /**< \brief (AC_COMPCTRL) I/O pin 0 */
466#define AC_COMPCTRL_MUXNEG_PIN1_Val 0x1u /**< \brief (AC_COMPCTRL) I/O pin 1 */
467#define AC_COMPCTRL_MUXNEG_PIN2_Val 0x2u /**< \brief (AC_COMPCTRL) I/O pin 2 */
468#define AC_COMPCTRL_MUXNEG_PIN3_Val 0x3u /**< \brief (AC_COMPCTRL) I/O pin 3 */
469#define AC_COMPCTRL_MUXNEG_GND_Val 0x4u /**< \brief (AC_COMPCTRL) Ground */
470#define AC_COMPCTRL_MUXNEG_VSCALE_Val 0x5u /**< \brief (AC_COMPCTRL) VDD scaler */
471#define AC_COMPCTRL_MUXNEG_BANDGAP_Val 0x6u /**< \brief (AC_COMPCTRL) Internal bandgap voltage */
472#define AC_COMPCTRL_MUXNEG_DAC_Val 0x7u /**< \brief (AC_COMPCTRL) DAC output */
473#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos)
474#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos)
475#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos)
476#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos)
477#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos)
478#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos)
479#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos)
480#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos)
481#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
482#define AC_COMPCTRL_MUXPOS_Msk (0x3u << AC_COMPCTRL_MUXPOS_Pos)
483#define AC_COMPCTRL_MUXPOS(value) ((AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)))
484#define AC_COMPCTRL_MUXPOS_PIN0_Val 0x0u /**< \brief (AC_COMPCTRL) I/O pin 0 */
485#define AC_COMPCTRL_MUXPOS_PIN1_Val 0x1u /**< \brief (AC_COMPCTRL) I/O pin 1 */
486#define AC_COMPCTRL_MUXPOS_PIN2_Val 0x2u /**< \brief (AC_COMPCTRL) I/O pin 2 */
487#define AC_COMPCTRL_MUXPOS_PIN3_Val 0x3u /**< \brief (AC_COMPCTRL) I/O pin 3 */
488#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos)
489#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos)
490#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos)
491#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos)
492#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */
493#define AC_COMPCTRL_SWAP (0x1u << AC_COMPCTRL_SWAP_Pos)
494#define AC_COMPCTRL_OUT_Pos 16 /**< \brief (AC_COMPCTRL) Output */
495#define AC_COMPCTRL_OUT_Msk (0x3u << AC_COMPCTRL_OUT_Pos)
496#define AC_COMPCTRL_OUT(value) ((AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)))
497#define AC_COMPCTRL_OUT_OFF_Val 0x0u /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
498#define AC_COMPCTRL_OUT_ASYNC_Val 0x1u /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
499#define AC_COMPCTRL_OUT_SYNC_Val 0x2u /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
500#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos)
501#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos)
502#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos)
503#define AC_COMPCTRL_HYST_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */
504#define AC_COMPCTRL_HYST (0x1u << AC_COMPCTRL_HYST_Pos)
505#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */
506#define AC_COMPCTRL_FLEN_Msk (0x7u << AC_COMPCTRL_FLEN_Pos)
507#define AC_COMPCTRL_FLEN(value) ((AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)))
508#define AC_COMPCTRL_FLEN_OFF_Val 0x0u /**< \brief (AC_COMPCTRL) No filtering */
509#define AC_COMPCTRL_FLEN_MAJ3_Val 0x1u /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
510#define AC_COMPCTRL_FLEN_MAJ5_Val 0x2u /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
511#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos)
512#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos)
513#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos)
514#define AC_COMPCTRL_MASK 0x070BB76Fu /**< \brief (AC_COMPCTRL) MASK Register */
515
516/* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */
517#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
518typedef union {
519 struct {
520 uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
521 uint8_t :2; /*!< bit: 6.. 7 Reserved */
522 } bit; /*!< Structure used for bit access */
523 uint8_t reg; /*!< Type used for register access */
524} AC_SCALER_Type;
525#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
526
527#define AC_SCALER_OFFSET 0x20 /**< \brief (AC_SCALER offset) Scaler n */
528#define AC_SCALER_RESETVALUE 0x00 /**< \brief (AC_SCALER reset_value) Scaler n */
529
530#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */
531#define AC_SCALER_VALUE_Msk (0x3Fu << AC_SCALER_VALUE_Pos)
532#define AC_SCALER_VALUE(value) ((AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)))
533#define AC_SCALER_MASK 0x3Fu /**< \brief (AC_SCALER) MASK Register */
534
535/** \brief AC hardware registers */
536#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
537typedef struct {
538 __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
539 __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
540 __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
541 __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
542 __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
543 __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
544 RoReg8 Reserved1[0x1];
545 __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */
546 __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */
547 __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */
548 RoReg8 Reserved2[0x1];
549 __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */
550 RoReg8 Reserved3[0x3];
551 __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
552 RoReg8 Reserved4[0x8];
553 __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */
554} Ac;
555#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
556
557/*@}*/
558
559#endif /* _SAMD21_AC_COMPONENT_ */
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