[457] | 1 | /*
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| 2 | *
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| 3 | * STM32F746-Discovery SDRAM設定
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| 4 | *
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| 5 | */
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| 6 | #include "kernel_impl.h"
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| 7 | #include <t_syslog.h>
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| 8 | #include <t_stdlib.h>
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| 9 | #include <sil.h>
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| 10 | #include <target_syssvc.h>
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| 11 | #include "device.h"
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| 12 |
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| 13 | /*
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| 14 | * SIL関数のマクロ定義
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| 15 | */
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| 16 | #define sil_orw_mem(a, b) sil_wrw_mem((a), sil_rew_mem(a) | (b))
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| 17 | #define sil_andw_mem(a, b) sil_wrw_mem((a), sil_rew_mem(a) & ~(b))
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| 18 | #define sil_modw_mem(a, b, c) sil_wrw_mem((a), (sil_rew_mem(a) & (~b)) | (c))
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| 19 |
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| 20 | /*
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| 21 | * AF 12セクション定義
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| 22 | */
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| 23 | #define GPIO_AF12_FMC 0x0C /* FMC Alternate Function mapping */
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| 24 | #define GPIO_AF12_OTG_HS_FS 0x0C /* OTG HS configured in FS, Alternate Function mapping */
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| 25 | #define GPIO_AF12_SDMMC1 0x0C /* SDMMC1 Alternate Function mapping */
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| 26 |
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| 27 | /*
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| 28 | * SDRAM設定タイムアウト定義(μsec)
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| 29 | */
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| 30 | #define SDRAM_TIMEOUT (0xFFFF*1000)
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| 31 |
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| 32 | /*
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| 33 | * FMC SDRAMモードコマンド定義
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| 34 | */
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| 35 | #define FMC_SDRAM_CMD_NORMAL_MODE 0x00000000
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| 36 | #define FMC_SDRAM_CMD_CLK_ENABLE 0x00000001
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| 37 | #define FMC_SDRAM_CMD_PALL 0x00000002
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| 38 | #define FMC_SDRAM_CMD_AUTOREFRESH_MODE 0x00000003
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| 39 | #define FMC_SDRAM_CMD_LOAD_MODE 0x00000004
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| 40 | #define FMC_SDRAM_CMD_SELFREFRESH_MODE 0x00000005
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| 41 | #define FMC_SDRAM_CMD_POWERDOWN_MODE 0x00000006
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| 42 |
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| 43 | /*
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| 44 | * FMC SDRAM カラムビット番号
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| 45 | */
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| 46 | #define FMC_SDRAM_COLUMN_BITS_NUM_8 0x00000000
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| 47 | #define FMC_SDRAM_COLUMN_BITS_NUM_9 0x00000001
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| 48 | #define FMC_SDRAM_COLUMN_BITS_NUM_10 0x00000002
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| 49 | #define FMC_SDRAM_COLUMN_BITS_NUM_11 0x00000003
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| 50 |
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| 51 | /*
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| 52 | * FMC SDRAM ロービット番号
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| 53 | */
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| 54 | #define FMC_SDRAM_ROW_BITS_NUM_11 0x00000000
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| 55 | #define FMC_SDRAM_ROW_BITS_NUM_12 0x00000004
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| 56 | #define FMC_SDRAM_ROW_BITS_NUM_13 0x00000008
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| 57 |
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| 58 | /*
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| 59 | * FMC SDRAM メモリビット幅
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| 60 | */
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| 61 | #define FMC_SDRAM_MEM_BUS_WIDTH_8 0x00000000
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| 62 | #define FMC_SDRAM_MEM_BUS_WIDTH_16 0x00000010
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| 63 | #define FMC_SDRAM_MEM_BUS_WIDTH_32 0x00000020
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| 64 |
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| 65 | /*
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| 66 | * FMC SDRAM インターナルバンク番号
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| 67 | */
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| 68 | #define FMC_SDRAM_INTERN_BANKS_NUM_2 0x00000000
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| 69 | #define FMC_SDRAM_INTERN_BANKS_NUM_4 0x00000040
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| 70 |
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| 71 | /*
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| 72 | * FMC SDRAM CAS レーテンシィ
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| 73 | */
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| 74 | #define FMC_SDRAM_CAS_LATENCY_1 0x00000080
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| 75 | #define FMC_SDRAM_CAS_LATENCY_2 0x00000100
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| 76 | #define FMC_SDRAM_CAS_LATENCY_3 0x00000180
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| 77 |
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| 78 | /*
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| 79 | * FMC SDRAM ライトプロテクション
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| 80 | */
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| 81 | #define FMC_SDRAM_WRITE_PROTECTION_DISABLE 0x00000000
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| 82 | #define FMC_SDRAM_WRITE_PROTECTION_ENABLE 0x00000200
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| 83 |
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| 84 | /*
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| 85 | * FMC SDRAM リードブースト
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| 86 | */
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| 87 | #define FMC_SDRAM_RBURST_DISABLE 0x00000000
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| 88 | #define FMC_SDRAM_RBURST_ENABLE 0x00001000
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| 89 |
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| 90 | /*
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| 91 | * FMC SDRAM リードパイプデレィ
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| 92 | */
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| 93 | #define FMC_SDRAM_RPIPE_DELAY_0 0x00000000
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| 94 | #define FMC_SDRAM_RPIPE_DELAY_1 0x00002000
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| 95 | #define FMC_SDRAM_RPIPE_DELAY_2 0x00004000
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| 96 |
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| 97 | /*
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| 98 | * FMC SDRAM Clock Period
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| 99 | */
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| 100 | #define FMC_SDRAM_CLOCK_DISABLE 0x00000000
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| 101 | #define FMC_SDRAM_CLOCK_PERIOD_2 0x00000800
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| 102 | #define FMC_SDRAM_CLOCK_PERIOD_3 0x00000C00
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| 103 |
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| 104 |
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| 105 | #define SDRAM_MODEREG_BURST_LENGTH_1 0x0000
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| 106 | #define SDRAM_MODEREG_BURST_LENGTH_2 0x0001
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| 107 | #define SDRAM_MODEREG_BURST_LENGTH_4 0x0002
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| 108 | #define SDRAM_MODEREG_BURST_LENGTH_8 0x0004
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| 109 | #define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL 0x0000
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| 110 | #define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED 0x0008
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| 111 | #define SDRAM_MODEREG_CAS_LATENCY_2 0x0020
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| 112 | #define SDRAM_MODEREG_CAS_LATENCY_3 0x0030
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| 113 | #define SDRAM_MODEREG_OPERATING_MODE_STANDARD 0x0000
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| 114 | #define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED 0x0000
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| 115 | #define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE 0x0200
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| 116 |
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| 117 |
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| 118 | /*
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| 119 | * FMC SDRAM コンフィギュレーション定義
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| 120 | */
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| 121 | typedef struct {
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| 122 | uint32_t ColumnBitsNumber; /* Defines the number of bits of column address. FMC_NORSRAM_Bank */
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| 123 | uint32_t RowBitsNumber; /* Defines the number of bits of column address. FMC_SDRAM_Row_Bits_number. */
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| 124 | uint32_t MemoryDataWidth; /* Defines the memory device width. FMC_SDRAM_Memory_Bus_Width. */
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| 125 | uint32_t InternalBankNumber; /* Defines the number of the device's internal banks. FMC_SDRAM_Internal_Banks_Number. */
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| 126 | uint32_t CASLatency; /* Defines the SDRAM CAS latency in number of memory clock cycles. FMC_SDRAM_CAS_Latency. */
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| 127 | uint32_t WriteProtection; /* Enables the SDRAM device to be accessed in write mode. FMC_SDRAM_Write_Protection. */
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| 128 | uint32_t SDClockPeriod; /* Define the SDRAM Clock Period for both SDRAM devices and they allow
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| 129 | to disable the clock before changing frequency. FMC_SDRAM_Clock_Period. */
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| 130 | uint32_t ReadBurst; /* This bit enable the SDRAM controller to anticipate the next read
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| 131 | commands during the CAS latency and stores data in the Read FIFO. FMC_SDRAM_Read_Burst. */
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| 132 | uint32_t ReadPipeDelay; /* Define the delay in system clock cycles on read data path. FMC_SDRAM_Read_Pipe_Delay. */
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| 133 | }FMC_SDRAM_Init_t;
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| 134 |
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| 135 | /*
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| 136 | * FMC SDRAM タイミング パラメータ
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| 137 | */
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| 138 | typedef struct {
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| 139 | uint32_t LoadToActiveDelay; /* Defines the delay between a Load Mode Register command and
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| 140 | an active or Refresh command in number of memory clock cycles. */
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| 141 | uint32_t ExitSelfRefreshDelay; /* Defines the delay from releasing the self refresh command to
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| 142 | issuing the Activate command in number of memory clock cycles. */
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| 143 | uint32_t SelfRefreshTime; /* Defines the minimum Self Refresh period in number of memory clock cycles.*/
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| 144 | uint32_t RowCycleDelay; /* Defines the delay between the Refresh command and the Activate command
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| 145 | and the delay between two consecutive Refresh commands in number of memory clock cycles. */
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| 146 | uint32_t WriteRecoveryTime; /* Defines the Write recovery Time in number of memory clock cycles. */
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| 147 | uint32_t RPDelay; /* Defines the delay between a Precharge Command and an other command
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| 148 | in number of memory clock cycles. */
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| 149 | uint32_t RCDDelay; /* Defines the delay between the Activate Command and a Read/Write
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| 150 | command in number of memory clock cycles. */
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| 151 | }FMC_SDRAM_Timing_t;
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| 152 |
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| 153 | #if defined(TOPPERS_STM32F769_DISCOVERY)
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| 154 | #define SDRAM_AHB1ENR (RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | \
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| 155 | RCC_AHB1ENR_GPIOFEN | RCC_AHB1ENR_GPIOGEN | \
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| 156 | RCC_AHB1ENR_GPIOHEN | RCC_AHB1ENR_GPIOIEN)
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| 157 | #define SDRAM_MODEREG_CAS_LATENCY SDRAM_MODEREG_CAS_LATENCY_3
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| 158 | #define REFLESH_RATE 1539
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| 159 | static const GPIO_Init_Table sdram_gpio_table[] = {
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| 160 | {TADR_GPIOD_BASE, (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15) },
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| 161 | {TADR_GPIOE_BASE, (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | \
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| 162 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15) },
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| 163 | {TADR_GPIOF_BASE, (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | \
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| 164 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15) },
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| 165 | {TADR_GPIOG_BASE, (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15) },
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| 166 | {TADR_GPIOH_BASE, (GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | \
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| 167 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15) },
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| 168 | {TADR_GPIOI_BASE, (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | \
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| 169 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_9 | GPIO_PIN_10) }
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| 170 | };
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| 171 |
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| 172 | static const FMC_SDRAM_Init_t sdinit = {
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| 173 | FMC_SDRAM_COLUMN_BITS_NUM_8, /* ColumnBitsNumber */
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| 174 | FMC_SDRAM_ROW_BITS_NUM_12, /* RowBitsNumber */
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| 175 | FMC_SDRAM_MEM_BUS_WIDTH_32, /* MemoryDataWidth */
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| 176 | FMC_SDRAM_INTERN_BANKS_NUM_4, /* InternalBankNumber */
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| 177 | FMC_SDRAM_CAS_LATENCY_3, /* CASLatency */
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| 178 | FMC_SDRAM_WRITE_PROTECTION_DISABLE, /* WriteProtection */
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| 179 | FMC_SDRAM_CLOCK_PERIOD_2, /* SDClockPeriod */
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| 180 | FMC_SDRAM_RBURST_ENABLE, /* ReadBurst */
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| 181 | FMC_SDRAM_RPIPE_DELAY_1 /* ReadPipeDelay */
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| 182 | };
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| 183 | static const FMC_SDRAM_Timing_t sdtiming = {
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| 184 | 2, /* LoadToActiveDelay */
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| 185 | 7, /* ExitSelfRefreshDelay */
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| 186 | 4, /* SelfRefreshTime */
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| 187 | 7, /* RowCycleDelay */
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| 188 | 2, /* WriteRecoveryTime */
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| 189 | 2, /* RPDelay */
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| 190 | 2 /* RCDDelay */
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| 191 | };
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| 192 |
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| 193 | #else
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| 194 | #define SDRAM_AHB1ENR (RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \
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| 195 | RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | \
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| 196 | RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN)
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| 197 | #define SDRAM_MODEREG_CAS_LATENCY SDRAM_MODEREG_CAS_LATENCY_2
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| 198 | #define REFLESH_RATE 1292
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| 199 | static const GPIO_Init_Table sdram_gpio_table[] = {
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| 200 | {TADR_GPIOC_BASE, (GPIO_PIN_3) },
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| 201 | {TADR_GPIOD_BASE, (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15) },
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| 202 | {TADR_GPIOE_BASE, (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | \
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| 203 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15) },
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| 204 | {TADR_GPIOF_BASE, (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | \
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| 205 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15) },
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| 206 | {TADR_GPIOG_BASE, (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15) },
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| 207 | {TADR_GPIOH_BASE, (GPIO_PIN_3 | GPIO_PIN_5) }
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| 208 | };
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| 209 |
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| 210 | static const FMC_SDRAM_Init_t sdinit = {
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| 211 | FMC_SDRAM_COLUMN_BITS_NUM_8, /* ColumnBitsNumber */
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| 212 | FMC_SDRAM_ROW_BITS_NUM_12, /* RowBitsNumber */
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| 213 | FMC_SDRAM_MEM_BUS_WIDTH_16, /* MemoryDataWidth */
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| 214 | FMC_SDRAM_INTERN_BANKS_NUM_4, /* InternalBankNumber */
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| 215 | FMC_SDRAM_CAS_LATENCY_2, /* CASLatency */
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| 216 | FMC_SDRAM_WRITE_PROTECTION_DISABLE, /* WriteProtection */
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| 217 | FMC_SDRAM_CLOCK_PERIOD_2, /* SDClockPeriod */
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| 218 | FMC_SDRAM_RBURST_ENABLE, /* ReadBurst */
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| 219 | FMC_SDRAM_RPIPE_DELAY_1 /* ReadPipeDelay */
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| 220 | };
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| 221 | static const FMC_SDRAM_Timing_t sdtiming = {
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| 222 | 2, /* LoadToActiveDelay */
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| 223 | 7, /* ExitSelfRefreshDelay */
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| 224 | 4, /* SelfRefreshTime */
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| 225 | 7, /* RowCycleDelay */
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| 226 | 2, /* WriteRecoveryTime */
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| 227 | 2, /* RPDelay */
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| 228 | 2 /* RCDDelay */
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| 229 | };
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| 230 |
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| 231 | #endif
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| 232 |
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| 233 | #define NUM_SDRAM_GPIO_ITEM (sizeof(sdram_gpio_table)/sizeof(GPIO_Init_Table))
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| 234 |
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| 235 | /*
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| 236 | * SDRAM GPIO初期化
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| 237 | */
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| 238 | static void
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| 239 | sdram_gpio_init(void)
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| 240 | {
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| 241 | GPIO_Init_t GPIO_Init_Data;
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| 242 | int i, pin;
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| 243 | volatile uint32_t tmp;
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| 244 |
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| 245 | /*
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| 246 | * GPIOクロック設定
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| 247 | */
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| 248 | sil_orw_mem((uint32_t *)(TADR_RCC_BASE+TOFF_RCC_AHB1ENR), SDRAM_AHB1ENR);
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| 249 | tmp = sil_rew_mem((uint32_t *)(TADR_RCC_BASE+TOFF_RCC_AHB1ENR));
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| 250 |
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| 251 | /*
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| 252 | * FMCクロック設定
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| 253 | */
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| 254 | sil_orw_mem((uint32_t *)(TADR_RCC_BASE+TOFF_RCC_AHB3ENR), RCC_AHB3ENR_FSMCEN);
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| 255 | tmp = sil_rew_mem((uint32_t *)(TADR_RCC_BASE+TOFF_RCC_AHB3ENR));
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| 256 | (void)(tmp);
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| 257 |
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| 258 | /*
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| 259 | * GPIO設定
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| 260 | */
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| 261 | GPIO_Init_Data.mode = GPIO_MODE_AF;
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| 262 | GPIO_Init_Data.pull = GPIO_PULLUP;
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| 263 | GPIO_Init_Data.otype = GPIO_OTYPE_PP;
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| 264 | #if defined(TOPPERS_STM32F769_DISCOVERY)
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| 265 | GPIO_Init_Data.speed = GPIO_SPEED_HIGH;
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| 266 | #else
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| 267 | GPIO_Init_Data.speed = GPIO_SPEED_FAST;
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| 268 | #endif
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| 269 | GPIO_Init_Data.alternate = GPIO_AF12_FMC;
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| 270 |
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| 271 | for(i = 0 ; i < NUM_SDRAM_GPIO_ITEM ; i++){
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| 272 | for(pin = 0 ; pin < 16 ; pin++){
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| 273 | if((sdram_gpio_table[i].pinmap & 1<<pin) != 0)
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| 274 | gpio_setup(sdram_gpio_table[i].base, &GPIO_Init_Data, pin);
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| 275 | }
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| 276 | }
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| 277 | }
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| 278 |
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| 279 | /*
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| 280 | * FMC SDRAMバンクへのコマンド送信
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| 281 | * patameter1 mode コマンド値
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| 282 | * parameter2 target ターゲット番号
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| 283 | * parameter3 num バンク番号
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| 284 | * parameter4 moder モード
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| 285 | * parameter5 timeout タイムアウト値
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| 286 | * return 正常終了でtrue
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| 287 | */
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| 288 | static bool_t
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| 289 | FMC_SDRAM_SendCommand(uint32_t cmd, uint32_t target, uint32_t num, uint32_t moder, uint32_t Timeout)
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| 290 | {
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| 291 | uint32_t tickstart = 0;
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| 292 |
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| 293 | /*
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| 294 | * コマンドレジスタ設定
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| 295 | */
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| 296 | sil_wrw_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDCMR), (cmd | target | ((num-1) << 5) | (moder << 9)));
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| 297 |
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| 298 | /*
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| 299 | * コマンド送信待ち
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| 300 | */
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| 301 | tickstart = 0;
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| 302 | while((sil_rew_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDSR)) & FMC_SDSR_BUSY) != 0){
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| 303 | if(tickstart > Timeout){
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| 304 | return false;
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| 305 | }
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| 306 | sil_dly_nse(1000);
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| 307 | tickstart++;
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| 308 | }
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| 309 | return true;
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| 310 | }
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| 311 |
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| 312 | /*
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| 313 | * 拡張SDRAMの初期化
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| 314 | */
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| 315 | void
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| 316 | sdram_init(intptr_t exinf)
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| 317 | {
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| 318 | uint32_t Bank = (uint32_t)exinf;
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| 319 | volatile uint32_t tmpr1 = 0;
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| 320 | volatile uint32_t tmpr2 = 0;
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| 321 |
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| 322 | /*
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| 323 | * GPIO,クロック設定
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| 324 | */
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| 325 | sdram_gpio_init();
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| 326 |
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| 327 | /*
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| 328 | * SDRAM制御タイミング設定
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| 329 | */
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| 330 | if (Bank != FMC_SDRAM_BANK2){ /* Bank1 */
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| 331 | tmpr1 = sil_rew_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDCR0));
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| 332 |
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| 333 | /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
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| 334 | tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
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| 335 | FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
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| 336 | FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
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| 337 |
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| 338 | tmpr1 |= (uint32_t)(sdinit.ColumnBitsNumber |
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| 339 | sdinit.RowBitsNumber |
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| 340 | sdinit.MemoryDataWidth |
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| 341 | sdinit.InternalBankNumber |
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| 342 | sdinit.CASLatency |
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| 343 | sdinit.WriteProtection |
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| 344 | sdinit.SDClockPeriod |
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| 345 | sdinit.ReadBurst |
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| 346 | sdinit.ReadPipeDelay );
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| 347 | sil_wrw_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDCR0), tmpr1);
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| 348 |
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| 349 | tmpr1 = sil_rew_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDTR0));
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| 350 | /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
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| 351 | tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS |
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| 352 | FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | FMC_SDTR1_TRCD));
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| 353 |
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| 354 | tmpr1 |= (uint32_t)(((sdtiming.LoadToActiveDelay)-1) |
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| 355 | (((sdtiming.ExitSelfRefreshDelay)-1) << 4) |
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| 356 | (((sdtiming.SelfRefreshTime)-1) << 8) |
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| 357 | (((sdtiming.RowCycleDelay)-1) << 12) |
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| 358 | (((sdtiming.WriteRecoveryTime)-1) <<16) |
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| 359 | (((sdtiming.RPDelay)-1) << 20) |
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| 360 | (((sdtiming.RCDDelay)-1) << 24));
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| 361 | sil_wrw_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDTR0), tmpr1);
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| 362 | }
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| 363 | else{ /* Bank 2 */
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| 364 | tmpr1 = sil_rew_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDCR0));
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| 365 |
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| 366 | /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
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| 367 | tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID |
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| 368 | FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP |
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| 369 | FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
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| 370 |
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| 371 | tmpr1 |= (uint32_t)(sdinit.SDClockPeriod |
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| 372 | sdinit.ReadBurst |
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| 373 | sdinit.ReadPipeDelay);
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| 374 |
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| 375 | tmpr2 = sil_rew_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDCR1));
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| 376 | /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
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| 377 | tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID |
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| 378 | FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP |
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| 379 | FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
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| 380 |
|
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| 381 | tmpr2 |= (uint32_t)(sdinit.ColumnBitsNumber |
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| 382 | sdinit.RowBitsNumber |
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| 383 | sdinit.MemoryDataWidth |
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| 384 | sdinit.InternalBankNumber |
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| 385 | sdinit.CASLatency |
|
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| 386 | sdinit.WriteProtection);
|
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| 387 |
|
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| 388 | sil_wrw_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDCR0), tmpr1);
|
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| 389 | sil_wrw_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDCR1), tmpr2);
|
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| 390 |
|
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| 391 | tmpr1 = sil_rew_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDTR1));
|
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| 392 | /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
|
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| 393 | tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS |
|
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| 394 | FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | FMC_SDTR1_TRCD));
|
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| 395 |
|
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| 396 | tmpr1 |= (uint32_t)(((sdtiming.LoadToActiveDelay)-1) |
|
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| 397 | (((sdtiming.ExitSelfRefreshDelay)-1) << 4) |
|
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| 398 | (((sdtiming.SelfRefreshTime)-1) << 8) |
|
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| 399 | (((sdtiming.WriteRecoveryTime)-1) <<16) |
|
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| 400 | (((sdtiming.RCDDelay)-1) << 24));
|
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| 401 |
|
---|
| 402 | tmpr2 = sil_rew_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDTR0));
|
---|
| 403 |
|
---|
| 404 | /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
|
---|
| 405 | tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS |
|
---|
| 406 | FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | FMC_SDTR1_TRCD));
|
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| 407 | tmpr2 |= (uint32_t)((((sdtiming.RowCycleDelay)-1) << 12) |
|
---|
| 408 | (((sdtiming.RPDelay)-1) << 20));
|
---|
| 409 |
|
---|
| 410 | sil_wrw_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDTR1), tmpr1);
|
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| 411 | sil_wrw_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDTR0), tmpr2);
|
---|
| 412 | }
|
---|
| 413 |
|
---|
| 414 | /*
|
---|
| 415 | * SDRAM外部デバイス設定
|
---|
| 416 | */
|
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| 417 | /* クロックコンフィギュレーション許可コマンド */
|
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| 418 | FMC_SDRAM_SendCommand(FMC_SDRAM_CMD_CLK_ENABLE, FMC_SDCMR_CTB1, 1, 0, SDRAM_TIMEOUT);
|
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| 419 |
|
---|
| 420 | /* 300us待ち */
|
---|
| 421 | sil_dly_nse(300*1000);
|
---|
| 422 |
|
---|
| 423 | /* PALLコンフィギュレーションコマンド */
|
---|
| 424 | FMC_SDRAM_SendCommand(FMC_SDRAM_CMD_PALL, FMC_SDCMR_CTB1, 1, 0, SDRAM_TIMEOUT);
|
---|
| 425 |
|
---|
| 426 | /* オートリフレッシュ設定コマンド */
|
---|
| 427 | FMC_SDRAM_SendCommand(FMC_SDRAM_CMD_AUTOREFRESH_MODE, FMC_SDCMR_CTB1, 8, 0, SDRAM_TIMEOUT);
|
---|
| 428 |
|
---|
| 429 | /* 外部メモリプログラミングレジスタ設定 */
|
---|
| 430 | tmpr1 = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |
|
---|
| 431 | SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
|
---|
| 432 | SDRAM_MODEREG_CAS_LATENCY |
|
---|
| 433 | SDRAM_MODEREG_OPERATING_MODE_STANDARD |
|
---|
| 434 | SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
|
---|
| 435 |
|
---|
| 436 | FMC_SDRAM_SendCommand(FMC_SDRAM_CMD_LOAD_MODE, FMC_SDCMR_CTB1, 1, tmpr1, SDRAM_TIMEOUT);
|
---|
| 437 |
|
---|
| 438 | /* リフレッシュレート設定: (15.62 us x Freq) - 20 */
|
---|
| 439 | sil_wrw_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDRTR), (REFLESH_RATE)<< 1);
|
---|
| 440 |
|
---|
| 441 | sil_orw_mem((uint32_t *)(TADR_RCC_BASE+TOFF_RCC_AHB1ENR), RCC_AHB1ENR_CRCEN);
|
---|
| 442 | tmpr1 = sil_rew_mem((uint32_t *)(TADR_RCC_BASE+TOFF_RCC_AHB1ENR));
|
---|
| 443 | }
|
---|
| 444 |
|
---|