source: azure_iot_hub_f767zi/trunk/asp_baseplatform/pdic/stm32f7xx/sdram.c@ 457

Last change on this file since 457 was 457, checked in by coas-nagasima, 4 years ago

ファイルを追加
  • Property svn:eol-style set to native
  • Property svn:mime-type set to text/x-csrc;charset=UTF-8
File size: 17.1 KB
Line 
1/*
2 *
3 * STM32F746-Discovery SDRAM設定
4 *
5 */
6#include "kernel_impl.h"
7#include <t_syslog.h>
8#include <t_stdlib.h>
9#include <sil.h>
10#include <target_syssvc.h>
11#include "device.h"
12
13/*
14 * SIL関数のマクロ定義
15 */
16#define sil_orw_mem(a, b) sil_wrw_mem((a), sil_rew_mem(a) | (b))
17#define sil_andw_mem(a, b) sil_wrw_mem((a), sil_rew_mem(a) & ~(b))
18#define sil_modw_mem(a, b, c) sil_wrw_mem((a), (sil_rew_mem(a) & (~b)) | (c))
19
20/*
21 * AF 12セクション定義
22 */
23#define GPIO_AF12_FMC 0x0C /* FMC Alternate Function mapping */
24#define GPIO_AF12_OTG_HS_FS 0x0C /* OTG HS configured in FS, Alternate Function mapping */
25#define GPIO_AF12_SDMMC1 0x0C /* SDMMC1 Alternate Function mapping */
26
27/*
28 * SDRAM設定タイムアウト定義(μsec)
29 */
30#define SDRAM_TIMEOUT (0xFFFF*1000)
31
32/*
33 * FMC SDRAMモードコマンド定義
34 */
35#define FMC_SDRAM_CMD_NORMAL_MODE 0x00000000
36#define FMC_SDRAM_CMD_CLK_ENABLE 0x00000001
37#define FMC_SDRAM_CMD_PALL 0x00000002
38#define FMC_SDRAM_CMD_AUTOREFRESH_MODE 0x00000003
39#define FMC_SDRAM_CMD_LOAD_MODE 0x00000004
40#define FMC_SDRAM_CMD_SELFREFRESH_MODE 0x00000005
41#define FMC_SDRAM_CMD_POWERDOWN_MODE 0x00000006
42
43/*
44 * FMC SDRAM カラムビット番号
45 */
46#define FMC_SDRAM_COLUMN_BITS_NUM_8 0x00000000
47#define FMC_SDRAM_COLUMN_BITS_NUM_9 0x00000001
48#define FMC_SDRAM_COLUMN_BITS_NUM_10 0x00000002
49#define FMC_SDRAM_COLUMN_BITS_NUM_11 0x00000003
50
51/*
52 * FMC SDRAM ロービット番号
53 */
54#define FMC_SDRAM_ROW_BITS_NUM_11 0x00000000
55#define FMC_SDRAM_ROW_BITS_NUM_12 0x00000004
56#define FMC_SDRAM_ROW_BITS_NUM_13 0x00000008
57
58/*
59 * FMC SDRAM メモリビット幅
60 */
61#define FMC_SDRAM_MEM_BUS_WIDTH_8 0x00000000
62#define FMC_SDRAM_MEM_BUS_WIDTH_16 0x00000010
63#define FMC_SDRAM_MEM_BUS_WIDTH_32 0x00000020
64
65/*
66 * FMC SDRAM インターナルバンク番号
67 */
68#define FMC_SDRAM_INTERN_BANKS_NUM_2 0x00000000
69#define FMC_SDRAM_INTERN_BANKS_NUM_4 0x00000040
70
71/*
72 * FMC SDRAM CAS レーテンシィ
73 */
74#define FMC_SDRAM_CAS_LATENCY_1 0x00000080
75#define FMC_SDRAM_CAS_LATENCY_2 0x00000100
76#define FMC_SDRAM_CAS_LATENCY_3 0x00000180
77
78/*
79 * FMC SDRAM ライトプロテクション
80 */
81#define FMC_SDRAM_WRITE_PROTECTION_DISABLE 0x00000000
82#define FMC_SDRAM_WRITE_PROTECTION_ENABLE 0x00000200
83
84/*
85 * FMC SDRAM リードブースト
86 */
87#define FMC_SDRAM_RBURST_DISABLE 0x00000000
88#define FMC_SDRAM_RBURST_ENABLE 0x00001000
89
90/*
91 * FMC SDRAM リードパイプデレィ
92 */
93#define FMC_SDRAM_RPIPE_DELAY_0 0x00000000
94#define FMC_SDRAM_RPIPE_DELAY_1 0x00002000
95#define FMC_SDRAM_RPIPE_DELAY_2 0x00004000
96
97/*
98 * FMC SDRAM Clock Period
99 */
100#define FMC_SDRAM_CLOCK_DISABLE 0x00000000
101#define FMC_SDRAM_CLOCK_PERIOD_2 0x00000800
102#define FMC_SDRAM_CLOCK_PERIOD_3 0x00000C00
103
104
105#define SDRAM_MODEREG_BURST_LENGTH_1 0x0000
106#define SDRAM_MODEREG_BURST_LENGTH_2 0x0001
107#define SDRAM_MODEREG_BURST_LENGTH_4 0x0002
108#define SDRAM_MODEREG_BURST_LENGTH_8 0x0004
109#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL 0x0000
110#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED 0x0008
111#define SDRAM_MODEREG_CAS_LATENCY_2 0x0020
112#define SDRAM_MODEREG_CAS_LATENCY_3 0x0030
113#define SDRAM_MODEREG_OPERATING_MODE_STANDARD 0x0000
114#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED 0x0000
115#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE 0x0200
116
117
118/*
119 * FMC SDRAM コンフィギュレーション定義
120 */
121typedef struct {
122 uint32_t ColumnBitsNumber; /* Defines the number of bits of column address. FMC_NORSRAM_Bank */
123 uint32_t RowBitsNumber; /* Defines the number of bits of column address. FMC_SDRAM_Row_Bits_number. */
124 uint32_t MemoryDataWidth; /* Defines the memory device width. FMC_SDRAM_Memory_Bus_Width. */
125 uint32_t InternalBankNumber; /* Defines the number of the device's internal banks. FMC_SDRAM_Internal_Banks_Number. */
126 uint32_t CASLatency; /* Defines the SDRAM CAS latency in number of memory clock cycles. FMC_SDRAM_CAS_Latency. */
127 uint32_t WriteProtection; /* Enables the SDRAM device to be accessed in write mode. FMC_SDRAM_Write_Protection. */
128 uint32_t SDClockPeriod; /* Define the SDRAM Clock Period for both SDRAM devices and they allow
129 to disable the clock before changing frequency. FMC_SDRAM_Clock_Period. */
130 uint32_t ReadBurst; /* This bit enable the SDRAM controller to anticipate the next read
131 commands during the CAS latency and stores data in the Read FIFO. FMC_SDRAM_Read_Burst. */
132 uint32_t ReadPipeDelay; /* Define the delay in system clock cycles on read data path. FMC_SDRAM_Read_Pipe_Delay. */
133}FMC_SDRAM_Init_t;
134
135/*
136 * FMC SDRAM タイミング パラメータ
137 */
138typedef struct {
139 uint32_t LoadToActiveDelay; /* Defines the delay between a Load Mode Register command and
140 an active or Refresh command in number of memory clock cycles. */
141 uint32_t ExitSelfRefreshDelay; /* Defines the delay from releasing the self refresh command to
142 issuing the Activate command in number of memory clock cycles. */
143 uint32_t SelfRefreshTime; /* Defines the minimum Self Refresh period in number of memory clock cycles.*/
144 uint32_t RowCycleDelay; /* Defines the delay between the Refresh command and the Activate command
145 and the delay between two consecutive Refresh commands in number of memory clock cycles. */
146 uint32_t WriteRecoveryTime; /* Defines the Write recovery Time in number of memory clock cycles. */
147 uint32_t RPDelay; /* Defines the delay between a Precharge Command and an other command
148 in number of memory clock cycles. */
149 uint32_t RCDDelay; /* Defines the delay between the Activate Command and a Read/Write
150 command in number of memory clock cycles. */
151}FMC_SDRAM_Timing_t;
152
153#if defined(TOPPERS_STM32F769_DISCOVERY)
154#define SDRAM_AHB1ENR (RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | \
155 RCC_AHB1ENR_GPIOFEN | RCC_AHB1ENR_GPIOGEN | \
156 RCC_AHB1ENR_GPIOHEN | RCC_AHB1ENR_GPIOIEN)
157#define SDRAM_MODEREG_CAS_LATENCY SDRAM_MODEREG_CAS_LATENCY_3
158#define REFLESH_RATE 1539
159static const GPIO_Init_Table sdram_gpio_table[] = {
160 {TADR_GPIOD_BASE, (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15) },
161 {TADR_GPIOE_BASE, (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | \
162 GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15) },
163 {TADR_GPIOF_BASE, (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | \
164 GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15) },
165 {TADR_GPIOG_BASE, (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15) },
166 {TADR_GPIOH_BASE, (GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | \
167 GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15) },
168 {TADR_GPIOI_BASE, (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | \
169 GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_9 | GPIO_PIN_10) }
170};
171
172static const FMC_SDRAM_Init_t sdinit = {
173 FMC_SDRAM_COLUMN_BITS_NUM_8, /* ColumnBitsNumber */
174 FMC_SDRAM_ROW_BITS_NUM_12, /* RowBitsNumber */
175 FMC_SDRAM_MEM_BUS_WIDTH_32, /* MemoryDataWidth */
176 FMC_SDRAM_INTERN_BANKS_NUM_4, /* InternalBankNumber */
177 FMC_SDRAM_CAS_LATENCY_3, /* CASLatency */
178 FMC_SDRAM_WRITE_PROTECTION_DISABLE, /* WriteProtection */
179 FMC_SDRAM_CLOCK_PERIOD_2, /* SDClockPeriod */
180 FMC_SDRAM_RBURST_ENABLE, /* ReadBurst */
181 FMC_SDRAM_RPIPE_DELAY_1 /* ReadPipeDelay */
182};
183static const FMC_SDRAM_Timing_t sdtiming = {
184 2, /* LoadToActiveDelay */
185 7, /* ExitSelfRefreshDelay */
186 4, /* SelfRefreshTime */
187 7, /* RowCycleDelay */
188 2, /* WriteRecoveryTime */
189 2, /* RPDelay */
190 2 /* RCDDelay */
191};
192
193#else
194#define SDRAM_AHB1ENR (RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \
195 RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | \
196 RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN)
197#define SDRAM_MODEREG_CAS_LATENCY SDRAM_MODEREG_CAS_LATENCY_2
198#define REFLESH_RATE 1292
199static const GPIO_Init_Table sdram_gpio_table[] = {
200 {TADR_GPIOC_BASE, (GPIO_PIN_3) },
201 {TADR_GPIOD_BASE, (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15) },
202 {TADR_GPIOE_BASE, (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | \
203 GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15) },
204 {TADR_GPIOF_BASE, (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | \
205 GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15) },
206 {TADR_GPIOG_BASE, (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15) },
207 {TADR_GPIOH_BASE, (GPIO_PIN_3 | GPIO_PIN_5) }
208};
209
210static const FMC_SDRAM_Init_t sdinit = {
211 FMC_SDRAM_COLUMN_BITS_NUM_8, /* ColumnBitsNumber */
212 FMC_SDRAM_ROW_BITS_NUM_12, /* RowBitsNumber */
213 FMC_SDRAM_MEM_BUS_WIDTH_16, /* MemoryDataWidth */
214 FMC_SDRAM_INTERN_BANKS_NUM_4, /* InternalBankNumber */
215 FMC_SDRAM_CAS_LATENCY_2, /* CASLatency */
216 FMC_SDRAM_WRITE_PROTECTION_DISABLE, /* WriteProtection */
217 FMC_SDRAM_CLOCK_PERIOD_2, /* SDClockPeriod */
218 FMC_SDRAM_RBURST_ENABLE, /* ReadBurst */
219 FMC_SDRAM_RPIPE_DELAY_1 /* ReadPipeDelay */
220};
221static const FMC_SDRAM_Timing_t sdtiming = {
222 2, /* LoadToActiveDelay */
223 7, /* ExitSelfRefreshDelay */
224 4, /* SelfRefreshTime */
225 7, /* RowCycleDelay */
226 2, /* WriteRecoveryTime */
227 2, /* RPDelay */
228 2 /* RCDDelay */
229};
230
231#endif
232
233#define NUM_SDRAM_GPIO_ITEM (sizeof(sdram_gpio_table)/sizeof(GPIO_Init_Table))
234
235/*
236 * SDRAM GPIO初期化
237 */
238static void
239sdram_gpio_init(void)
240{
241 GPIO_Init_t GPIO_Init_Data;
242 int i, pin;
243 volatile uint32_t tmp;
244
245 /*
246 * GPIOクロック設定
247 */
248 sil_orw_mem((uint32_t *)(TADR_RCC_BASE+TOFF_RCC_AHB1ENR), SDRAM_AHB1ENR);
249 tmp = sil_rew_mem((uint32_t *)(TADR_RCC_BASE+TOFF_RCC_AHB1ENR));
250
251 /*
252 * FMCクロック設定
253 */
254 sil_orw_mem((uint32_t *)(TADR_RCC_BASE+TOFF_RCC_AHB3ENR), RCC_AHB3ENR_FSMCEN);
255 tmp = sil_rew_mem((uint32_t *)(TADR_RCC_BASE+TOFF_RCC_AHB3ENR));
256 (void)(tmp);
257
258 /*
259 * GPIO設定
260 */
261 GPIO_Init_Data.mode = GPIO_MODE_AF;
262 GPIO_Init_Data.pull = GPIO_PULLUP;
263 GPIO_Init_Data.otype = GPIO_OTYPE_PP;
264#if defined(TOPPERS_STM32F769_DISCOVERY)
265 GPIO_Init_Data.speed = GPIO_SPEED_HIGH;
266#else
267 GPIO_Init_Data.speed = GPIO_SPEED_FAST;
268#endif
269 GPIO_Init_Data.alternate = GPIO_AF12_FMC;
270
271 for(i = 0 ; i < NUM_SDRAM_GPIO_ITEM ; i++){
272 for(pin = 0 ; pin < 16 ; pin++){
273 if((sdram_gpio_table[i].pinmap & 1<<pin) != 0)
274 gpio_setup(sdram_gpio_table[i].base, &GPIO_Init_Data, pin);
275 }
276 }
277}
278
279/*
280 * FMC SDRAMバンクへのコマンド送信
281 * patameter1 mode コマンド値
282 * parameter2 target ターゲット番号
283 * parameter3 num バンク番号
284 * parameter4 moder モード
285 * parameter5 timeout タイムアウト値
286 * return 正常終了でtrue
287 */
288static bool_t
289FMC_SDRAM_SendCommand(uint32_t cmd, uint32_t target, uint32_t num, uint32_t moder, uint32_t Timeout)
290{
291 uint32_t tickstart = 0;
292
293 /*
294 * コマンドレジスタ設定
295 */
296 sil_wrw_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDCMR), (cmd | target | ((num-1) << 5) | (moder << 9)));
297
298 /*
299 * コマンド送信待ち
300 */
301 tickstart = 0;
302 while((sil_rew_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDSR)) & FMC_SDSR_BUSY) != 0){
303 if(tickstart > Timeout){
304 return false;
305 }
306 sil_dly_nse(1000);
307 tickstart++;
308 }
309 return true;
310}
311
312/*
313 * 拡張SDRAMの初期化
314 */
315void
316sdram_init(intptr_t exinf)
317{
318 uint32_t Bank = (uint32_t)exinf;
319 volatile uint32_t tmpr1 = 0;
320 volatile uint32_t tmpr2 = 0;
321
322 /*
323 * GPIO,クロック設定
324 */
325 sdram_gpio_init();
326
327 /*
328 * SDRAM制御タイミング設定
329 */
330 if (Bank != FMC_SDRAM_BANK2){ /* Bank1 */
331 tmpr1 = sil_rew_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDCR0));
332
333 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
334 tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
335 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
336 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
337
338 tmpr1 |= (uint32_t)(sdinit.ColumnBitsNumber |
339 sdinit.RowBitsNumber |
340 sdinit.MemoryDataWidth |
341 sdinit.InternalBankNumber |
342 sdinit.CASLatency |
343 sdinit.WriteProtection |
344 sdinit.SDClockPeriod |
345 sdinit.ReadBurst |
346 sdinit.ReadPipeDelay );
347 sil_wrw_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDCR0), tmpr1);
348
349 tmpr1 = sil_rew_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDTR0));
350 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
351 tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS |
352 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | FMC_SDTR1_TRCD));
353
354 tmpr1 |= (uint32_t)(((sdtiming.LoadToActiveDelay)-1) |
355 (((sdtiming.ExitSelfRefreshDelay)-1) << 4) |
356 (((sdtiming.SelfRefreshTime)-1) << 8) |
357 (((sdtiming.RowCycleDelay)-1) << 12) |
358 (((sdtiming.WriteRecoveryTime)-1) <<16) |
359 (((sdtiming.RPDelay)-1) << 20) |
360 (((sdtiming.RCDDelay)-1) << 24));
361 sil_wrw_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDTR0), tmpr1);
362 }
363 else{ /* Bank 2 */
364 tmpr1 = sil_rew_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDCR0));
365
366 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
367 tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID |
368 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP |
369 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
370
371 tmpr1 |= (uint32_t)(sdinit.SDClockPeriod |
372 sdinit.ReadBurst |
373 sdinit.ReadPipeDelay);
374
375 tmpr2 = sil_rew_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDCR1));
376 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
377 tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID |
378 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP |
379 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
380
381 tmpr2 |= (uint32_t)(sdinit.ColumnBitsNumber |
382 sdinit.RowBitsNumber |
383 sdinit.MemoryDataWidth |
384 sdinit.InternalBankNumber |
385 sdinit.CASLatency |
386 sdinit.WriteProtection);
387
388 sil_wrw_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDCR0), tmpr1);
389 sil_wrw_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDCR1), tmpr2);
390
391 tmpr1 = sil_rew_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDTR1));
392 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
393 tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS |
394 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | FMC_SDTR1_TRCD));
395
396 tmpr1 |= (uint32_t)(((sdtiming.LoadToActiveDelay)-1) |
397 (((sdtiming.ExitSelfRefreshDelay)-1) << 4) |
398 (((sdtiming.SelfRefreshTime)-1) << 8) |
399 (((sdtiming.WriteRecoveryTime)-1) <<16) |
400 (((sdtiming.RCDDelay)-1) << 24));
401
402 tmpr2 = sil_rew_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDTR0));
403
404 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
405 tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS |
406 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | FMC_SDTR1_TRCD));
407 tmpr2 |= (uint32_t)((((sdtiming.RowCycleDelay)-1) << 12) |
408 (((sdtiming.RPDelay)-1) << 20));
409
410 sil_wrw_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDTR1), tmpr1);
411 sil_wrw_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDTR0), tmpr2);
412 }
413
414 /*
415 * SDRAM外部デバイス設定
416 */
417 /* クロックコンフィギュレーション許可コマンド */
418 FMC_SDRAM_SendCommand(FMC_SDRAM_CMD_CLK_ENABLE, FMC_SDCMR_CTB1, 1, 0, SDRAM_TIMEOUT);
419
420 /* 300us待ち */
421 sil_dly_nse(300*1000);
422
423 /* PALLコンフィギュレーションコマンド */
424 FMC_SDRAM_SendCommand(FMC_SDRAM_CMD_PALL, FMC_SDCMR_CTB1, 1, 0, SDRAM_TIMEOUT);
425
426 /* オートリフレッシュ設定コマンド */
427 FMC_SDRAM_SendCommand(FMC_SDRAM_CMD_AUTOREFRESH_MODE, FMC_SDCMR_CTB1, 8, 0, SDRAM_TIMEOUT);
428
429 /* 外部メモリプログラミングレジスタ設定 */
430 tmpr1 = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |
431 SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
432 SDRAM_MODEREG_CAS_LATENCY |
433 SDRAM_MODEREG_OPERATING_MODE_STANDARD |
434 SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
435
436 FMC_SDRAM_SendCommand(FMC_SDRAM_CMD_LOAD_MODE, FMC_SDCMR_CTB1, 1, tmpr1, SDRAM_TIMEOUT);
437
438 /* リフレッシュレート設定: (15.62 us x Freq) - 20 */
439 sil_wrw_mem((uint32_t *)(TADR_FMC_R_BASE+TOFF_FMC_R_SDRTR), (REFLESH_RATE)<< 1);
440
441 sil_orw_mem((uint32_t *)(TADR_RCC_BASE+TOFF_RCC_AHB1ENR), RCC_AHB1ENR_CRCEN);
442 tmpr1 = sil_rew_mem((uint32_t *)(TADR_RCC_BASE+TOFF_RCC_AHB1ENR));
443}
444
Note: See TracBrowser for help on using the repository browser.