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prc_mpu.c

Last change on this file was 172, checked in by ertl-ishikawa, 8 years ago
ATK2-SC3 1.4.0 RH850依存部非信頼C2ISR対応を追加
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File size: 10.8 KB

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1	/*
2	* TOPPERS ATK2
3	* Toyohashi Open Platform for Embedded Real-Time Systems
4	* Automotive Kernel Version 2
5	*
6	* Copyright (C) 2013-2015 by Embedded and Real-Time Systems Laboratory
7	* Graduate School of Information Science, Nagoya Univ., JAPAN
8	*
9	* ä¸è¨èä½æ¨©è
10	ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
11	* ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
12	* å¤ã»åé
13	å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
14	* (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
15	* æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
16	* ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
17	* (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
18	* ç¨ã§ããå½¢ã§åé
19	å¸ããå ´åã«ã¯ï¼åé
20	å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
21	* è
22	ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
23	* ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
24	* (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
25	* ç¨ã§ããªãå½¢ã§åé
26	å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
27	* ã¨ï¼
28	* (a) åé
29	å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
30	ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
31	* ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
32	* (b) åé
33	å¸ã®å½¢æ
34	ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
35	* å ±åãããã¨ï¼
36	* (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
37	* å®³ãããï¼ä¸è¨èä½æ¨©è
38	ããã³TOPPERSããã¸ã§ã¯ããå
39	è²¬ãããã¨ï¼
40	* ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
41	* ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
42	ããã³TOPPERSããã¸ã§ã¯ãã
43	* å
44	è²¬ãããã¨ï¼
45	*
46	* æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
47	ã
48	* ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
49	* ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
50	* ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
51	* ã®è²¬ä»»ãè² ããªãï¼
52	*
53	* $Id$
54	*/
55
56	/*
57	* MPUãã©ã¤ã
58	*/
59
60	#include "kernel_impl.h"
61	#include "task.h"
62	#include "memory.h"
63	#include "prc_sil.h"
64	#include "Os_Lcfg.h"
65	#include <t_syslog.h>
66
67	void *p_ctxosap;
68
69	void
70	target_mpu_initialize(void)
71	{
72	#ifdef __v850e2v3__
73	uint8 *ipal;
74	uint8 *ipau;
75
76	/*
77	* bselãä¿è·è¨å®ç¨ã«
78	*/
79	ipal = (uint8 *)0x00001001;
80	LDSR_REG(BSEL, (uint32)ipal);
81
82	/*
83	* IPA2: å
84	±æãªã¼ãé å
85	*/
86	ipal = shared_meminib_table[0];
87	ipau = shared_meminib_table[1];
88	IPA_WRITE(2, ipal, ipau);
89
90	/*
91	* IPA3: å
92	±ærosdata
93	*/
94	ipal = shared_meminib_table[2];
95	ipau = shared_meminib_table[3];
96	IPA_WRITE(3, ipal, ipau);
97
98	/*
99	* DPA5: å
100	±æãªã¼ãã©ã¤ãé å
101	*/
102	ipal = shared_meminib_table[4];
103	ipau = shared_meminib_table[5];
104	DPA_WRITE(5, ipal, ipau);
105
106	/*
107	* MPUæå¹
108	* ç¹æ¨©ã¢ã¼ãã§ã¯ããã©ã«ãã®ã¡ã¢ãªããã
109	* ãã³ãã©å
110	ã§ã¯MPUç¡å¹
111	*/
112	ipal = (uint8 *)0x07;
113	LDSR_REG(MPM, (uint32)ipal);
114
115	/*
116	* bselãåºæ¬è¨å®ç¨ã«æ»ã
117	*/
118	LDSR_REG(BSEL, (0U));
119
120	#elif defined(__v850e3v5__)
121	uint32 mpm = 0x0U;
122
123	/*
124	* MPU0: ã¦ã¼ã¶ã¹ã¿ãã¯MPUé åã®è¨å®
125	*/
126	LDSR_REG(2, 6, (uint32)(MPAT_E \| MPAT_G \| MPAT_UX \| MPAT_UW \| MPAT_UR))
127
128	mpu_shared_area_initialize();
129
130	/*
131	* MPUæå¹
132	* DW = 0 ããã¯ã°ã©ã¦ã³ãã®æ¸è¾¼ã¿ã¯ç¦æ¢
133	* SVP = 0 ç¹æ¨©ã§ã®ã¢ã¯ã»ã¹å¶éã¯ããªã
134	* MPE = 1 MPUæå¹
135	*/
136	/*
137	* RH850/F1Lç¨ã®è¨å®
138	* DR = 1 ããã¯ã°ã©ã¦ã³ãã®æ¸è¾¼ã¿ã¯ç¦æ¢
139	* DW = 0 ããã¯ã°ã©ã¦ã³ãã®æ¸è¾¼ã¿ã¯ç¦æ¢
140	* DX = 1 ããã¯ã°ã©ã¦ã³ãã®æ¸è¾¼ã¿ã¯ç¦æ¢
141	* RH850/F1Hç¨ã®è¨å®
142	* DR = 0 ããã¯ã°ã©ã¦ã³ãã®ã¢ã¯ã»ã¹ã¯ç¦æ¢
143	* DW = 0 ããã¯ã°ã©ã¦ã³ãã®ã¢ã¯ã»ã¹ã¯ç¦æ¢
144	* DX = 0 ããã¯ã°ã©ã¦ã³ãã®ã¢ã¯ã»ã¹ã¯ç¦æ¢
145	*/
146	LDSR_REG(0, 5, (uint32)TARGET_MPM_CONFIG);
147
148
149	#else /* __v850e3v5__ */
150	#error please define ether __v850e2v3__ or __v850e3v5__
151	#endif /* __v850e2v3__ */
152
153	}
154
155	void
156	target_impu_exc_handler(void *p_excinf)
157	{
158	uint32 sreg;
159	uint32 vmtid;
160
161	#if defined(__v850e2v3__)
162	sreg = 0x00001000; /* ããã»ããµä¿è·éåãã³ã¯ */
163	LDSR_REG(BSEL, sreg);
164	STSR_REG(VMTID, vmtid);
165	STSR_REG(VMADR, sreg);
166	LDSR_REG(BSEL, (0U));
167
168	#elif defined(__v850e3v5__)
169	vmtid = (uint32)p_runosap;
170	STSR_REG(2, 0, (sreg));
171
172	#else /* __v850e3v5__ */
173	#error please define ether __v850e2v3__ or __v850e3v5__
174	#endif /* __v850e2v3__ */
175
176	syslog(LOG_EMERG, "MPU EXCEPTION (RX) at 0x%x OCCURED!!", sreg);
177	syslog(LOG_EMERG, "p_dominib = 0x%x", vmtid);
178	while(1);
179	}
180
181	void
182	target_dmpu_exc_handler(void *p_excinf)
183	{
184	uint32 sreg;
185	uint32 vmtid;
186
187	#if defined(__v850e2v3__)
188	sreg = 0x00001000; /* ããã»ããµä¿è·éåãã³ã¯ */
189	LDSR_REG(BSEL, (sreg));
190	STSR_REG(VMTID, (vmtid));
191	STSR_REG(VMADR, (sreg));
192	LDSR_REG(BSEL, (0U));
193	#elif defined(__v850e3v5__)
194	vmtid = (uint32)p_runosap;
195	STSR_REG(2, 0, (sreg));
196
197	#else /* __v850e3v5__ */
198	#error please define ether __v850e2v3__ or __v850e3v5__
199	#endif /* __v850e2v3__ */
200
201	syslog(LOG_EMERG, "MPU EXCEPTION (RWX) at 0x%x OCCURED!!", sreg);
202	syslog(LOG_EMERG, "p_dominib = 0x%x", vmtid);
203	while(1);
204	}
205
206	/*
207	* ä¿è·éåFEã¬ãã«ä¾å¤ãã³ãã©
208	*/
209	void
210	target_protection_handler(void *p_excinf)
211	{
212	uint32 feic = 0;
213
214	/*
215	* FEã¬ãã«ä¾å¤è¦å ã®èªåºã
216	*/
217	#if defined(__v850e2v3__)
218	LDSR_REG(BSEL, 0U);
219	STSR_REG(FEIC, feic);
220
221	#elif defined(__v850e3v5__)
222	STSR_REG(FEIC, 0, feic);
223
224	#else /* __v850e3v5__ */
225	#error please define ether __v850e2v3__ or __v850e3v5__
226	#endif /* __v850e2v3__ */
227
228	switch(feic){
229	case FE_MIP: /* å®è¡ä¿è·éåä¾å¤ */
230	target_impu_exc_handler(NULL);
231	break;
232	case FE_MDP: /* ãã¼ã¿ä¿è·éåä¾å¤ */
233	target_dmpu_exc_handler(NULL);
234	break;
235	default:
236	break;
237	}
238	}
239
240	#if 1
241	/*
242	* æå®ãããã¢ãã¬ã¹ãã¦ã¼ã¶ã¢ã¼ãæã«æ¸è¾¼ã¿å¯è½ãããã§ãã¯ãã
243	*/
244	#ifdef OMIT_PROBE_MEM_WRITE
245	boolean
246	probe_mem_write(const MemoryStartAddressType base, MemorySizeType size)
247	{
248	uint32 sreg;
249	boolean ret;
250
251	/*
252	* ä¿¡é ¼OSAPãªãã°ä»»æã®ã¢ãã¬ã¹ã«ã¢ã¯ã»ã¹å¯è½
253	*/
254	if(run_trusted != FALSE){
255	return TRUE;
256	}
257
258	#ifdef __v850e2v3__
259	sreg = 0x00001000; /* ããã»ããµä¿è·éåãã³ã¯ */
260	/*
261	* ãã³ã¯ãã»ãã
262	*/
263	LDSR_REG(BSEL, (sreg));
264	/*
265	* å
266	é ã¢ãã¬ã¹ãMCAã«ã»ãã
267	*/
268	LDSR_REG(MCA, (uint32)base);
269
270	/*
271	* ãµã¤ãºãMCSã«ã»ãã
272	*/
273	LDSR_REG(MCS, (uint32)size);
274
275	/*
276	* ã¡ã¢ãªä¿è·è¨å®ãã§ãã¯éå§
277	*/
278	LDSR_REG(MCC, 0U);
279
280	/*
281	* ã¡ã¢ãªä¿è·è¨å®ãã§ãã¯çµæãèªã¿åºã
282	*/
283	STSR_REG(MCR, sreg);
284	#elif __v850e3v5__
285	/*
286	* å
287	é ã¢ãã¬ã¹ãMCAã«ã»ãã
288	*/
289	LDSR_REG(8, 5, (uint32)base);
290	/*
291	* ãµã¤ãºãMCSã«ã»ãã
292	*/
293	LDSR_REG(9, 5, (uint32)size);
294	/*
295	* ã¡ã¢ãªä¿è·è¨å®ãã§ãã¯éå§
296	*/
297	LDSR_REG(10, 5, 0U);
298	/*
299	* ã¡ã¢ãªä¿è·è¨å®ãã§ãã¯çµæãèªã¿åºã
300	*/
301	STSR_REG(11, 5, sreg);
302	#else
303	#error hoge!
304	#endif
305
306	if(sreg & 0x00000100){
307	/* ãªã¼ãããã¼ã®å ´å */
308	ret = FALSE;
309	} else if(sreg & 0x00000004){
310	/* ã©ã¤ãè¨±å¯ã®å ´å */
311	ret = TRUE;
312	} else {
313	ret = FALSE;
314	}
315
316	#ifdef __v850e2v3__
317	/*
318	* ãã³ã¯ãæ»ã
319	*/
320	LDSR_REG(BSEL, 0U);
321	#endif /* __v850e2v3__ */
322
323	return ret;
324	}
325	#endif /* OMIT_PROBE_MEM_WRITE */
326
327	#ifdef __v850e2v3__
328	/*
329	* æå®ãããã¢ãã¬ã¹ãã¦ã¼ã¶ã¢ã¼ãæã«èªè¾¼ã¿å¯è½ãããã§ãã¯ãã
330	*/
331	#ifdef OMIT_PROBE_MEM_READ
332	boolean
333	probe_mem_read(const MemoryStartAddressType base, MemorySizeType size)
334	{
335	uint32 sreg;
336	boolean ret;
337
338	/*
339	* ä¿¡é ¼OSAPãªãã°ä»»æã®ã¢ãã¬ã¹ã«ã¢ã¯ã»ã¹å¯è½
340	*/
341	if(run_trusted != FALSE){
342	return TRUE;
343	}
344
345	sreg = 0x00001000; /* ããã»ããµä¿è·éåãã³ã¯ */
346	/*
347	* ãã³ã¯ãã»ãã
348	*/
349	LDSR_REG(BSEL, sreg);
350
351	/*
352	* å
353	é ã¢ãã¬ã¹ãMCAã«ã»ãã
354	*/
355	LDSR_REG(MCA, (uint32)base);
356
357	/*
358	* ãµã¤ãºãMCSã«ã»ãã
359	*/
360	LDSR_REG(MCS, (uint32)size);
361
362	/*
363	* ã¡ã¢ãªä¿è·è¨å®ãã§ãã¯éå§
364	*/
365	LDSR_REG(MCC, (uint32)size);
366
367	/*
368	* ã¡ã¢ãªä¿è·è¨å®ãã§ãã¯çµæãèªã¿åºã
369	*/
370	STSR_REG(MCR, sreg);
371
372	if(sreg & 0x00000100){
373	/* ãªã¼ãããã¼ã®å ´å */
374	ret = FALSE;
375	} else if(sreg & 0x00000002){
376	/* ãªã¼ãè¨±å¯ã®å ´å */
377	ret = TRUE;
378	} else {
379	ret = FALSE;
380	}
381
382	/*
383	* ãã³ã¯ãæ»ã
384	*/
385	LDSR_REG(BSEL, 0U);
386
387	return ret;
388	}
389	#endif /* OMIT_PROBE_MEM_READ */
390
391	/*
392	* æå®ãããé åãã¦ã¼ã¶ã¹ã¿ãã¯é åã«åã¾ã£ã¦ãããããã§ãã¯ãã
393	*/
394	#ifdef OMIT_PROBE_STACK
395
396	boolean
397	probe_stack(const void *base, MemorySizeType size)
398	{
399	uint32 sreg;
400	boolean ret;
401
402	sreg = 0x00001000; /* ããã»ããµä¿è·éåãã³ã¯ */
403	/*
404	* ãã³ã¯ãã»ãã
405	*/
406	LDSR_REG(BSEL, sreg);
407
408	/*
409	* å
410	é ã¢ãã¬ã¹ãMCAã«ã»ãã
411	*/
412	LDSR_REG(MCA, (uint32)base);
413
414	/*
415	* ãµã¤ãºãMCSã«ã»ãã
416	*/
417	LDSR_REG(MCS, (uint32)size);
418
419	/*
420	* ã¡ã¢ãªä¿è·è¨å®ãã§ãã¯éå§
421	*/
422	LDSR_REG(MCC, 0U);
423
424	/*
425	* ã¡ã¢ãªä¿è·è¨å®ãã§ãã¯çµæãèªã¿åºã
426	*/
427	STSR_REG(MCR, sreg);
428
429	if(sreg & 0x00000100){
430	/* ãªã¼ãããã¼ã®å ´å */
431	ret = FALSE;
432	} else if(sreg & 0x00000010){
433	/* ã¹ã¿ãã¯ã®å ´å */
434	ret = TRUE;
435	} else {
436	ret = FALSE;
437	}
438
439	/*
440	* ãã³ã¯ãæ»ã
441	*/
442	LDSR_REG(BSEL, 0U);
443
444
445	return ret;
446	}
447	#endif /* OMIT_PROBE_STACK */
448	#endif /* __v850e2v3__ */
449	#endif
450
451	AccessType
452	probe_trusted_osap_mem(const MemoryStartAddressType sadr, const MemoryStartAddressType eadr)
453	{
454	/*
455	* ä¿¡é ¼OSAPãªãã°ä»»æã®ã¢ãã¬ã¹ã«ã¢ã¯ã»ã¹å¯è½
456	*/
457	return(AP_Executable\|AP_Readable\|AP_Writable);
458	}
459

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source: atk2-sc3-1.4.0-ntisr/arch/v850_gcc/prc_mpu.c

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