[129] | 1 | /*
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| 2 | * TOPPERS/ASP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Advanced Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2008-2011 by Embedded and Real-Time Systems Laboratory
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| 7 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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| 8 | *
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| 9 | * ãLì ÒÍCȺÌ(1)`(4)Ìðð½·êÉÀèC{\tgEF
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| 10 | * Ai{\tgEFAðüϵ½àÌðÜÞDȺ¯¶jðgpE¡»Eü
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| 11 | * ÏEÄzziȺCpÆÄÔj·é±Æð³Åø·éD
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| 12 | * (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
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| 13 | * \¦C±Ìpð¨æѺL̳ÛØKèªC»ÌÜÜÌ`Å\[
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| 14 | * XR[hÉÜÜêÄ¢é±ÆD
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| 15 | * (2) {\tgEFAðCCu`®ÈÇC¼Ì\tgEFAJÉg
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| 16 | * pÅ«é`ÅÄzz·éêÉÍCÄzzɺ¤hL
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| 17 | gip
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| 18 | * Ò}j
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| 19 | AÈÇjÉCãLÌì \¦C±Ìpð¨æѺL
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| 20 | * ̳ÛØKèðfÚ·é±ÆD
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| 21 | * (3) {\tgEFAðC@íÉgÝÞÈÇC¼Ì\tgEFAJÉg
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| 22 | * pÅ«È¢`ÅÄzz·éêÉÍCÌ¢¸ê©Ìðð½·±
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| 23 | * ÆD
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| 24 | * (a) Äzzɺ¤hL
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| 25 | gipÒ}j
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| 26 | AÈÇjÉCãLÌ
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| 27 | * ì \¦C±Ìpð¨æѺL̳ÛØKèðfÚ·é±ÆD
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| 28 | * (b) ÄzzÌ`ÔðCÊÉèßéû@ÉæÁÄCTOPPERSvWFNgÉ
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| 29 | * ñ·é±ÆD
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| 30 | * (4) {\tgEFAÌpÉæè¼ÚIܽÍÔÚIɶ¶é¢©Èé¹
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| 31 | * Q©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆD
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| 32 | * ܽC{\tgEFAÌ[UܽÍGh[U©çÌ¢©Èé
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| 33 | * RÉîÿ©çàCãLì Ò¨æÑTOPPERSvWFNgð
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| 34 | * ÆÓ·é±ÆD
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| 35 | *
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| 36 | * {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì Ò¨
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| 37 | * æÑTOPPERSvWFNgÍC{\tgEFAÉÖµÄCÁèÌgpÚI
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| 38 | * ÉηéK«àÜßÄC¢©ÈéÛØàsíÈ¢DܽC{\tgEF
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| 39 | * AÌpÉæè¼ÚIܽÍÔÚIɶ¶½¢©Èé¹QÉÖµÄàC»
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| 40 | * ÌÓCðíÈ¢D
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| 41 | *
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| 42 | */
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| 43 |
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| 44 | /*
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| 45 | * VAI/OfoCXiSIOjhCo
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| 46 | */
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| 47 |
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| 48 | #include <kernel.h>
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| 49 | #include <t_syslog.h>
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| 50 | #include "target_serial.h"
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| 51 | #include "target_syssvc.h"
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| 52 |
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| 53 | /*
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| 54 | * WX^Ýèl
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| 55 | */
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| 56 | #define PORT2SIOPID(x) ((x) + 1)
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| 57 | #define INDEX_PORT(x) ((x) - 1)
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| 58 | #define GET_SIOPCB(x) (&siopcb_table[INDEX_PORT(x)])
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| 59 |
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| 60 | /*
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| 61 | * UARTWX^è`
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| 62 | */
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| 63 | #define UART_SMR(x) (x + 0x00)
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| 64 | #define UART_SCR(x) (x + 0x01)
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| 65 | #define UART_ESCR(x) (x + 0x04)
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| 66 | #define UART_SSR(x) (x + 0x05)
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| 67 | #define UART_RDR(x) (x + 0x08)
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| 68 | #define UART_TDR(x) (x + 0x08)
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| 69 | #define UART_BGR(x) (x + 0x0c)
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| 70 | #define UART_BGR0(x) (x + 0x0c)
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| 71 | #define UART_BGR1(x) (x + 0x0d)
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| 72 | #define UART_ISBA(x) (x + 0x10)
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| 73 | #define UART_ISMK(x) (x + 0x11)
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| 74 | #define UART_FCR0(x) (x + 0x14)
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| 75 | #define UART_FCR1(x) (x + 0x15)
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| 76 | #define UART_FBYTE1(x) (x + 0x18)
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| 77 | #define UART_FBYTE2(x) (x + 0x19)
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| 78 |
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| 79 | /*
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| 80 | * VAI/O|[gú»ubNÌè`
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| 81 | */
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[150] | 82 | typedef struct sio_port_initialization_block {
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[129] | 83 | uint32_t base;
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| 84 | INTNO intno_rx;
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| 85 | INTNO intno_tx;
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| 86 | uint16_t bps_setting; /* {[[gÌÝèl */
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| 87 | } SIOPINIB;
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| 88 |
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| 89 | /*
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| 90 | * pGPIO|[gú»ubNÌè`
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| 91 | */
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| 92 | typedef struct gpio_port_initialization_block {
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| 93 | uint32_t pfr; /* PFRxWX^AhX */
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| 94 | uint32_t pfr_set; /* PFRxWX^ðZbg·érbg */
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| 95 | uint32_t pcr; /* PCRxWX^AhX */
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| 96 | uint32_t pcr_set; /* PCRxWX^ðZbg·érbg */
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| 97 | uint32_t epfr; /* EPFRxxWX^AhX */
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| 98 | uint32_t epfr_clr; /* EPFRxxWX^ðNA·érbg */
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| 99 | uint32_t epfr_set; /* EPFRxxWX^ðZbg·érbg */
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| 100 | uint32_t ade; /* ADEWX^AhX */
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| 101 | uint32_t ade_clr; /* ADEWX^ðNA·érbg */
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| 102 | } GPIOINIB;
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| 103 |
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| 104 | /*
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| 105 | * VAI/O|[gÇubNÌè`
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| 106 | */
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| 107 | struct sio_port_control_block {
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| 108 | const SIOPINIB *p_siopinib; /* VAI/O|[gú»ubN */
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| 109 | const GPIOINIB *p_gpioinib; /* pGPIO|[gú»ubN */
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| 110 | intptr_t exinf; /* g£îñ */
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| 111 | bool_t opnflg; /* I[vÏÝtO */
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| 112 | };
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| 113 |
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[150] | 114 | /*
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| 115 | * VAI/O|[gú»ubN
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| 116 | */
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[129] | 117 | const SIOPINIB siopinib_table[TNUM_SIOP] = {
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| 118 | {(uint32_t)FM3_MFS4_UART_BASE, (INTNO)IRQ_VECTOR_MFS4RX, (INTNO)IRQ_VECTOR_MFS4TX, MFS4_BPS_SETTING},
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| 119 | {(uint32_t)FM3_MFS0_UART_BASE, (INTNO)IRQ_VECTOR_MFS0RX, (INTNO)IRQ_VECTOR_MFS0TX, MFS0_BPS_SETTING},
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| 120 | {(uint32_t)FM3_MFS3_UART_BASE, (INTNO)IRQ_VECTOR_MFS3RX, (INTNO)IRQ_VECTOR_MFS3TX, MFS3_BPS_SETTING},
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| 121 | };
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| 122 |
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[150] | 123 | /*
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[129] | 124 | * pGPIO|[gú»ubN
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| 125 | */
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| 126 | const GPIOINIB gpioinib_table[TNUM_SIOP] = {
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| 127 | {(uint32_t)FM3_GPIO_PFR0, (uint32_t)((1 << 5) | (1 << 6)), (uint32_t)FM3_GPIO_PCR0, (uint32_t)(1<<5), (uint32_t)FM3_GPIO_EPFR08, (uint32_t)~0x000000f0, (uint32_t)0x000000f0, (uint32_t)FM3_GPIO_ADE, (uint32_t)0},
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| 128 | {(uint32_t)FM3_GPIO_PFR2, (uint32_t)((1 << 1) | (1 << 2)), (uint32_t)FM3_GPIO_PCR2, (uint32_t)(1<<1), (uint32_t)FM3_GPIO_EPFR07, (uint32_t)~0x000000f0, (uint32_t)0x00000050, (uint32_t)FM3_GPIO_ADE, (uint32_t)(1 << 31)},
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| 129 | {(uint32_t)FM3_GPIO_PFR4, (uint32_t)((1 << 8) | (1 << 9)), (uint32_t)FM3_GPIO_PCR4, (uint32_t)(1<<8), (uint32_t)FM3_GPIO_EPFR07, (uint32_t)~0x03c00000, (uint32_t)0x03c00000, (uint32_t)FM3_GPIO_ADE, (uint32_t)0},
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| 130 | };
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| 131 |
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| 132 | /*
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| 133 | * VAI/O|[gÇubNÌGA
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| 134 | */
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| 135 | SIOPCB siopcb_table[TNUM_SIOP];
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| 136 |
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| 137 | /*
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| 138 | * VAI/O|[gID©çÇubNðæèo·½ßÌ}N
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| 139 | */
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| 140 | #define INDEX_SIOP(siopid) ((uint_t)((siopid) - 1))
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| 141 | #define get_siopcb(siopid) (&(siopcb_table[INDEX_SIOP(siopid)]))
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| 142 |
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| 143 | /*
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| 144 | * SIOhCoÌú»
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| 145 | */
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| 146 | void
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| 147 | sio_initialize(intptr_t exinf)
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| 148 | {
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| 149 | SIOPCB *p_siopcb;
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| 150 | uint_t i;
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| 151 |
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| 152 | /*
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| 153 | * VAI/O|[gÇubNÌú»
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| 154 | */
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| 155 | for (p_siopcb = siopcb_table, i = 0; i < TNUM_SIOP; p_siopcb++, i++) {
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| 156 | p_siopcb->p_siopinib = &(siopinib_table[i]);
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| 157 | p_siopcb->p_gpioinib = &(gpioinib_table[i]);
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| 158 | p_siopcb->opnflg = false;
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| 159 | }
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| 160 | }
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| 161 |
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| 162 |
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| 163 | /*
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| 164 | * VAI/O|[gÌI[v
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| 165 | */
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| 166 | SIOPCB *
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| 167 | sio_opn_por(ID siopid, intptr_t exinf)
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| 168 | {
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| 169 | SIOPCB *p_siopcb;
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| 170 | const SIOPINIB *p_siopinib;
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| 171 | const GPIOINIB *p_gpioinib;
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| 172 | bool_t opnflg;
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| 173 | ER ercd;
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| 174 |
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| 175 | p_siopcb = get_siopcb(siopid);
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| 176 | p_siopinib = p_siopcb->p_siopinib;
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| 177 | p_gpioinib = p_siopcb->p_gpioinib;
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| 178 |
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| 179 | /*
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| 180 | * I[vµ½|[gª é©ðopnflgÉÇñŨD
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| 181 | */
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| 182 | opnflg = p_siopcb->opnflg;
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| 183 |
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| 184 | p_siopcb->exinf = exinf;
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| 185 |
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| 186 | /*
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| 187 | * n[hEFAÌú»
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| 188 | */
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| 189 | sil_wrw_mem((uint32_t *)p_gpioinib->pfr, sil_rew_mem((uint32_t *)p_gpioinib->pfr) | p_gpioinib->pfr_set);
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| 190 | sil_wrw_mem((uint32_t *)p_gpioinib->pcr, sil_rew_mem((uint32_t *)p_gpioinib->pcr) | p_gpioinib->pcr_set);
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| 191 | sil_wrw_mem((uint32_t *)p_gpioinib->epfr, (sil_rew_mem((uint32_t *)p_gpioinib->epfr) & p_gpioinib->epfr_clr) | p_gpioinib->epfr_set);
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| 192 | sil_wrw_mem((uint32_t *)p_gpioinib->ade, sil_rew_mem((uint32_t *)p_gpioinib->ade) & ~p_gpioinib->ade_clr);
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| 193 |
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[150] | 194 | uint32_t base = p_siopinib->base;
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[129] | 195 |
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| 196 | sil_wrb_mem((uint8_t *)UART_SCR(base), 0);
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| 197 | sil_wrb_mem((uint8_t *)UART_SMR(base), SMR_MD_UART | SMR_SOE);
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| 198 | sil_wrh_mem((uint16_t *)UART_BGR(base), p_siopinib->bps_setting);
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| 199 | sil_wrb_mem((uint8_t *)UART_ESCR(base), ESCR_DATABITS_8);
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| 200 | sil_wrb_mem((uint8_t *)UART_SCR(base), SCR_RXE | SCR_TXE);
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| 201 |
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| 202 | /*
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| 203 | * VAI/OÝÌ}XNðð·éD
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| 204 | */
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| 205 | if (!opnflg) {
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| 206 | ercd = ena_int(p_siopinib->intno_rx);
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| 207 | assert(ercd == E_OK);
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| 208 | ercd = ena_int(p_siopinib->intno_tx);
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| 209 | assert(ercd == E_OK);
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| 210 | }
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| 211 |
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| 212 | return(p_siopcb);
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| 213 | }
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| 214 |
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| 215 | /*
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| 216 | * VAI/O|[gÌN[Y
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| 217 | */
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| 218 | void
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| 219 | sio_cls_por(SIOPCB *p_siopcb)
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| 220 | {
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| 221 | /*
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| 222 | * VAI/OÝð}XN·éD
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| 223 | */
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| 224 | if (!(p_siopcb->opnflg)) {
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| 225 | dis_int(p_siopcb->p_siopinib->intno_rx);
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| 226 | dis_int(p_siopcb->p_siopinib->intno_tx);
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| 227 | }
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| 228 | }
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| 229 |
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| 230 | /*
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| 231 | * SIOÌÝT[rX[`
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| 232 | */
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| 233 |
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| 234 | Inline bool_t
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| 235 | sio_putready(SIOPCB* p_siopcb)
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| 236 | {
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| 237 | return (sil_reb_mem((uint8_t *)UART_SSR(p_siopcb->p_siopinib->base)) & SSR_TDRE) != 0;
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| 238 | }
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| 239 |
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| 240 | Inline bool_t
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| 241 | sio_getready(SIOPCB* p_siopcb)
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| 242 | {
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| 243 | char ssr = sil_reb_mem((uint8_t *)UART_SSR(p_siopcb->p_siopinib->base));
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| 244 |
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| 245 | if ((ssr & (SSR_ORE | SSR_FRE | SSR_PE)) != 0)
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| 246 | {
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| 247 | sil_wrb_mem((uint8_t *)UART_SSR(p_siopcb->p_siopinib->base), ssr | SSR_REC);
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| 248 | return 0;
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| 249 | }
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| 250 | if ((ssr & SSR_RDRF) != 0)
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| 251 | {
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| 252 | return 1;
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| 253 | }
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| 254 | return 0;
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| 255 | }
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| 256 |
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| 257 | void
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| 258 | sio_tx_isr(intptr_t exinf)
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| 259 | {
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| 260 | SIOPCB *p_siopcb;
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| 261 |
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| 262 | p_siopcb = get_siopcb(exinf);
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| 263 |
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| 264 | if (sio_putready(p_siopcb)) {
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| 265 | sio_irdy_snd(p_siopcb->exinf);
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| 266 | }
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| 267 | }
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| 268 |
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| 269 | void
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| 270 | sio_rx_isr(intptr_t exinf)
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| 271 | {
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| 272 | SIOPCB *p_siopcb;
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| 273 |
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| 274 | p_siopcb = get_siopcb(exinf);
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| 275 |
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| 276 | if (sio_getready(p_siopcb)) {
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| 277 | sio_irdy_rcv(p_siopcb->exinf);
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| 278 | }
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| 279 | }
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| 280 |
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| 281 | /*
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| 282 | * VAI/O|[gÖ̶M
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| 283 | */
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| 284 | bool_t
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| 285 | sio_snd_chr(SIOPCB *p_siopcb, char c)
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| 286 | {
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| 287 | if (sio_putready(p_siopcb)) {
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| 288 | sil_wrh_mem((uint16_t *)UART_TDR(p_siopcb->p_siopinib->base), (uint16_t)c);
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| 289 |
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| 290 | return true;
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| 291 | }
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| 292 |
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| 293 | return false;
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| 294 | }
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| 295 |
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| 296 | /*
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| 297 | * VAI/O|[g©ç̶óM
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| 298 | */
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| 299 | int_t
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| 300 | sio_rcv_chr(SIOPCB *p_siopcb)
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| 301 | {
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| 302 | int_t c = -1;
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| 303 |
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| 304 | if (sio_getready(p_siopcb)) {
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| 305 | c = sil_reh_mem((uint16_t *)UART_RDR(p_siopcb->p_siopinib->base)) & 0xFF;
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| 306 | }
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| 307 |
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| 308 | return c;
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| 309 | }
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| 310 |
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| 311 | /*
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| 312 | * VAI/O|[g©çÌR[obNÌÂ
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| 313 | */
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| 314 | void
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| 315 | sio_ena_cbr(SIOPCB *p_siopcb, uint_t cbrtn)
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| 316 | {
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| 317 | switch (cbrtn) {
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| 318 | case SIO_RDY_SND:
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| 319 | sil_wrb_mem((uint8_t *)UART_SCR(p_siopcb->p_siopinib->base), sil_reb_mem((uint8_t *)UART_SCR(p_siopcb->p_siopinib->base)) | SCR_TIE);
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| 320 | break;
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| 321 | case SIO_RDY_RCV:
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| 322 | sil_wrb_mem((uint8_t *)UART_SCR(p_siopcb->p_siopinib->base), sil_reb_mem((uint8_t *)UART_SCR(p_siopcb->p_siopinib->base)) | SCR_RIE);
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| 323 | break;
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| 324 | }
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| 325 | }
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| 326 |
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| 327 | /*
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| 328 | * VAI/O|[g©çÌR[obNÌÖ~
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| 329 | */
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| 330 | void
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| 331 | sio_dis_cbr(SIOPCB *p_siopcb, uint_t cbrtn)
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| 332 | {
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| 333 | switch (cbrtn) {
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| 334 | case SIO_RDY_SND:
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| 335 | sil_wrb_mem((uint8_t *)UART_SCR(p_siopcb->p_siopinib->base), sil_reb_mem((uint8_t *)UART_SCR(p_siopcb->p_siopinib->base)) & ~SCR_TIE);
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| 336 | break;
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| 337 | case SIO_RDY_RCV:
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| 338 | sil_wrb_mem((uint8_t *)UART_SCR(p_siopcb->p_siopinib->base), sil_reb_mem((uint8_t *)UART_SCR(p_siopcb->p_siopinib->base)) & ~SCR_RIE);
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| 339 | break;
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| 340 | }
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| 341 | }
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| 342 |
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| 343 | /*
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| 344 | * 1¶oÍi|[OÅÌoÍj
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| 345 | */
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| 346 | void sio_pol_snd_chr(char c, ID siopid)
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| 347 | {
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| 348 | uint32_t base = siopinib_table[INDEX_PORT(siopid)].base;
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| 349 |
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| 350 | sil_wrh_mem((uint16_t *)UART_TDR(base), (uint16_t)c);
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| 351 | while(0 == (sil_reb_mem((uint8_t *)UART_SSR(base)) & (1 << 1)));
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| 352 |
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| 353 | /*
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| 354 | * oͪ®SÉIíéÜÅÒÂ
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| 355 | */
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| 356 | volatile int n = 300000000/BPS_SETTING;
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| 357 | while(n--);
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| 358 | }
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| 359 |
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| 360 | /*
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[150] | 361 | * ^[QbgÌVAú»
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[129] | 362 | */
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| 363 | void target_uart_init(ID siopid)
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| 364 | {
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| 365 | const SIOPINIB *p_siopinib = &siopinib_table[INDEX_PORT(siopid)];
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| 366 | const GPIOINIB *p_gpioinib = &gpioinib_table[INDEX_PORT(siopid)];
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| 367 |
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| 368 | sil_wrw_mem((uint32_t *)p_gpioinib->pfr, sil_rew_mem((uint32_t *)p_gpioinib->pfr) | p_gpioinib->pfr_set);
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| 369 | sil_wrw_mem((uint32_t *)p_gpioinib->pcr, sil_rew_mem((uint32_t *)p_gpioinib->pcr) | p_gpioinib->pcr_set);
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| 370 | sil_wrw_mem((uint32_t *)p_gpioinib->epfr, (sil_rew_mem((uint32_t *)p_gpioinib->epfr) & p_gpioinib->epfr_clr) | p_gpioinib->epfr_set);
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| 371 | sil_wrw_mem((uint32_t *)p_gpioinib->ade, sil_rew_mem((uint32_t *)p_gpioinib->ade) & ~p_gpioinib->ade_clr);
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| 372 |
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[150] | 373 | uint32_t base = siopinib_table[INDEX_PORT(siopid)].base;
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[129] | 374 |
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| 375 | sil_wrb_mem((uint8_t *)UART_SCR(base), 0);
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| 376 | sil_wrb_mem((uint8_t *)UART_SMR(base), SMR_MD_UART | SMR_SOE);
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| 377 | sil_wrh_mem((uint16_t *)UART_BGR(base), p_siopinib->bps_setting);
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| 378 | sil_wrb_mem((uint8_t *)UART_ESCR(base), ESCR_DATABITS_8);
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| 379 | sil_wrb_mem((uint8_t *)UART_SCR(base), SCR_TXE);
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| 380 | }
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