[302] | 1 | /*
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| 2 | * TOPPERS/ASP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Advanced Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2007-2015 by Embedded and Real-Time Systems Laboratory
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| 7 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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| 8 | *
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| 9 | * ä¸è¨èä½æ¨©è
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| 10 | ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
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| 11 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
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| 12 | * å¤ã»åé
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| 13 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 14 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 15 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 16 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 17 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 18 | * ç¨ã§ããå½¢ã§åé
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| 19 | å¸ããå ´åã«ã¯ï¼åé
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| 20 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 21 | * è
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| 22 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 23 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 24 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 25 | * ç¨ã§ããªãå½¢ã§åé
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| 26 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 27 | * ã¨ï¼
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| 28 | * (a) åé
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| 29 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 30 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 31 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 32 | * (b) åé
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| 33 | å¸ã®å½¢æ
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| 34 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 35 | * å ±åãããã¨ï¼
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| 36 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 37 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 38 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 39 | 責ãããã¨ï¼
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| 40 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
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| 41 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
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| 42 | ããã³TOPPERSããã¸ã§ã¯ãã
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| 43 | * å
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| 44 | 責ãããã¨ï¼
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| 45 | *
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| 46 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 47 | ã
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| 48 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
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| 49 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
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| 50 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
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| 51 | * ã®è²¬ä»»ãè² ããªãï¼
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| 52 | *
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| 53 | * $Id: target_kernel_impl.c 365 2015-07-26 13:18:44Z ertl-hiro $
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| 54 | */
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| 55 |
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| 56 | /*
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| 57 | * ã«ã¼ãã«ã®ã¿ã¼ã²ããä¾åé¨ï¼CT11MPCoreç¨ï¼
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| 58 | */
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| 59 |
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| 60 | #include "kernel_impl.h"
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| 61 | #include <sil.h>
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| 62 | #include "arm.h"
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| 63 | #include "uart_pl011.h"
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| 64 |
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| 65 | /*
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| 66 | * ã«ã¼ãã«åä½æã®ã¡ã¢ãªãããã¨é¢é£ããå®ç¾©
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| 67 | *
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| 68 | * 0x00000000 - 0x00100000ï¼ãã¯ã¿ã¼é åï¼1MBï¼
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| 69 | * 0x00100000 - 0x0FFFFFFFï¼DRAMï¼255MBï¼
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| 70 | * 0x10000000 - 0x100FFFFFï¼Emulation Baseboardä¸ã®ãªã½ã¼ã¹ï¼1MBï¼
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| 71 | * 0x10100000 - 0x101FFFFFï¼Private Memory Regionï¼1MBï¼(*)
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| 72 | * 0x48000000 - 0x4BFFFFFFï¼SRAMï¼4MBï¼
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| 73 | *
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| 74 | * (*) Private Memory Regionã®å
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| 75 | é çªå°ã¯ï¼ãã¼ãã®è¨å®ã§å¤æ´ã§ããï¼
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| 76 | */
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| 77 |
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| 78 | /*
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| 79 | * MMUã¸ã®è¨å®å±æ§ï¼ç¬¬1ã¬ãã«ãã£ã¹ã¯ãªãã¿ï¼
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| 80 | */
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| 81 | #define MMU_ATTR_RAM (ARM_MMU_DSCR1_SHARED|ARMV6_MMU_DSCR1_APX0 \
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| 82 | |ARM_MMU_DSCR1_TEX001|ARM_MMU_DSCR1_AP11 \
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| 83 | |ARM_MMU_DSCR1_CB11)
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| 84 | #define MMU_ATTR_IODEV (ARM_MMU_DSCR1_SHARED|ARMV6_MMU_DSCR1_APX0 \
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| 85 | |ARM_MMU_DSCR1_TEX000|ARM_MMU_DSCR1_AP11 \
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| 86 | |ARM_MMU_DSCR1_CB01|ARMV6_MMU_DSCR1_NOEXEC)
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| 87 | #define MMU_ATTR_VECTOR (ARMV6_MMU_DSCR1_APX0 \
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| 88 | |ARM_MMU_DSCR1_TEX001|ARM_MMU_DSCR1_AP11 \
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| 89 | |ARM_MMU_DSCR1_CB11)
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| 90 |
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| 91 | /*
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| 92 | * ã¡ã¢ãªé åã®å
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| 93 | é çªå°ã¨ãµã¤ãº
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| 94 | */
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| 95 | #define SDRAM_ADDR 0x00100000
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| 96 | #define SDRAM_SIZE 0x0ff00000 /* 255MB */
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| 97 | #define SDRAM_ATTR MMU_ATTR_RAM
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| 98 |
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| 99 | #define SRAM_ADDR 0x48000000
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| 100 | #define SRAM_SIZE 0x04000000 /* 16MB */
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| 101 | #define SRAM_ATTR MMU_ATTR_RAM
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| 102 |
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| 103 | /*
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| 104 | * ããã¤ã¹ã¬ã¸ã¹ã¿é åã®å
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| 105 | é çªå°ã¨ãµã¤ãº
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| 106 | */
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| 107 | #define EB_SYS_ADDR EB_SYS_BASE
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| 108 | #define EB_SYS_SIZE 0x00100000 /* 1MB */
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| 109 | #define EB_SYS_ATTR MMU_ATTR_IODEV
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| 110 |
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| 111 | #define PMR_ADDR MPCORE_PMR_BASE
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| 112 | #define PMR_SIZE 0x00100000 /* 1MB */
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| 113 | #define PMR_ATTR MMU_ATTR_IODEV
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| 114 |
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| 115 | /*
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| 116 | * ãã¯ã¿ãã¼ãã«ãç½®ãã¡ã¢ãªé å
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| 117 | */
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| 118 | #if defined(CORE0)
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| 119 | #define VECTOR_ADDR 0x01000000
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| 120 | #elif defined(CORE1)
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| 121 | #define VECTOR_ADDR 0x02000000
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| 122 | #elif defined(CORE2)
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| 123 | #define VECTOR_ADDR 0x03000000
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| 124 | #elif defined(CORE3)
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| 125 | #define VECTOR_ADDR 0x04000000
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| 126 | #endif
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| 127 | #define VECTOR_SIZE 0x00100000 /* 1MB */
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| 128 | #define VECTOR_ATTR MMU_ATTR_VECTOR
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| 129 |
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| 130 | /*
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| 131 | * MMUã®è¨å®æ
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| 132 | å ±ï¼ã¡ã¢ãªã¨ãªã¢ã®æ
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| 133 | å ±ï¼
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| 134 | */
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| 135 | ARM_MMU_CONFIG arm_memory_area[] = {
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| 136 | { 0x00000000, VECTOR_ADDR, VECTOR_SIZE, VECTOR_ATTR },
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| 137 | { SRAM_ADDR, SRAM_ADDR, SRAM_SIZE, SRAM_ATTR },
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| 138 | { EB_SYS_ADDR, EB_SYS_ADDR, EB_SYS_SIZE, EB_SYS_ATTR },
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| 139 | { PMR_ADDR, PMR_ADDR, PMR_SIZE, PMR_ATTR },
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| 140 | { SDRAM_ADDR, SDRAM_ADDR, SDRAM_SIZE, SDRAM_ATTR }
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| 141 | };
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| 142 |
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| 143 | /*
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| 144 | * MMUã®è¨å®æ
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| 145 | å ±ã®æ°ï¼ã¡ã¢ãªã¨ãªã¢ã®æ°ï¼
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| 146 | */
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| 147 | const uint_t arm_tnum_memory_area
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| 148 | = sizeof(arm_memory_area) / sizeof(ARM_MMU_CONFIG);
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| 149 |
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| 150 | /*
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| 151 | * UARTããã®ãã¼ãªã³ã°åºå
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| 152 | */
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| 153 | static void
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| 154 | ct11mpcore_uart_fput(char c)
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| 155 | {
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| 156 | /*
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| 157 | * éä¿¡ãããã¡ã空ãã¾ã§ãã¼ãªã³ã°
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| 158 | */
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| 159 | while (!(uart_pl011_putready(FPUT_UART_BASE))) ;
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| 160 |
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| 161 | /*
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| 162 | * éä¿¡ããæåã®æ¸è¾¼ã¿
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| 163 | */
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| 164 | uart_pl011_putchar(FPUT_UART_BASE, c);
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| 165 | }
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| 166 |
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| 167 | /*
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| 168 | * ã·ã¹ãã ãã°ã®ä½ã¬ãã«åºåã®ããã®æååºå
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| 169 | */
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| 170 | void
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| 171 | target_fput_log(char c)
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| 172 | {
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| 173 | if (c == '\n') {
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| 174 | ct11mpcore_uart_fput('\r');
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| 175 | }
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| 176 | ct11mpcore_uart_fput(c);
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| 177 | }
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| 178 |
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| 179 | /*
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| 180 | * UARPããã®ãã¼ãªã³ã°åºåã®ããã®åæå
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| 181 | */
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| 182 | static void
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| 183 | ct11mpcore_uart_initialize(void)
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| 184 | {
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| 185 | /*
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| 186 | * UARTããã£ã¹ã¨ã¼ãã«
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| 187 | */
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| 188 | sil_wrw_mem(UART_CR(FPUT_UART_BASE), 0U);
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| 189 |
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| 190 | /*
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| 191 | * ã¨ã©ã¼ãã©ã°ãã¯ãªã¢
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| 192 | */
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| 193 | sil_wrw_mem(UART_ECR(FPUT_UART_BASE), 0U);
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| 194 |
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| 195 | /*
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| 196 | * FIFOã空ã«ãã
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| 197 | */
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| 198 | while (uart_pl011_getready(FPUT_UART_BASE)) {
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| 199 | (void) uart_pl011_getchar(FPUT_UART_BASE);
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| 200 | }
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| 201 |
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| 202 | /*
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| 203 | * ãã¼ã¬ã¼ãã¨éä¿¡è¦æ ¼ãè¨å®
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| 204 | */
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| 205 | sil_wrw_mem(UART_IBRD(FPUT_UART_BASE), EB_UART_IBRD_38400);
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| 206 | sil_wrw_mem(UART_FBRD(FPUT_UART_BASE), EB_UART_FBRD_38400);
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| 207 | sil_wrw_mem(UART_LCR_H(FPUT_UART_BASE), UART_LCR_H_WLEN8);
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| 208 |
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| 209 | /*
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| 210 | * UARTãã¤ãã¼ãã«
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| 211 | */
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| 212 | sil_wrw_mem(UART_CR(FPUT_UART_BASE),
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| 213 | UART_CR_UARTEN|UART_CR_TXE|UART_CR_RXE);
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| 214 | }
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| 215 |
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| 216 | /*
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| 217 | * ã¿ã¼ã²ããä¾åã®åæå
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| 218 | */
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| 219 | void
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| 220 | target_initialize(void)
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| 221 | {
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| 222 | uint32_t reg;
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| 223 |
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| 224 | /*
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| 225 | * ãããä¾åã®åæå
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| 226 | */
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| 227 | chip_initialize();
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| 228 |
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| 229 | /*
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| 230 | * Emulation Baseboardã®å²è¾¼ã¿ã¢ã¼ãã®è¨å®
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| 231 | */
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| 232 | sil_wrw_mem(EB_SYS_LOCK, EB_SYS_LOCK_UNLOCK); /* ããã¯è§£é¤ */
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| 233 |
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| 234 | reg = sil_rew_mem(EB_SYS_PLD_CTRL1);
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| 235 | reg &= ~EB_SYS_PLD_CTRL1_INTMODE_MASK;
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| 236 | reg |= EB_SYS_PLD_CTRL1_INTMODE_NEW_NODCC;
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| 237 | sil_wrw_mem(EB_SYS_PLD_CTRL1, reg);
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| 238 |
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| 239 | sil_wrw_mem(EB_SYS_LOCK, EB_SYS_LOCK_LOCK); /* ãã㯠*/
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| 240 |
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| 241 | /*
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| 242 | * UARTãåæå
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| 243 | */
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| 244 | ct11mpcore_uart_initialize();
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| 245 | }
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| 246 |
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| 247 | /*
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| 248 | * ã¿ã¼ã²ããä¾åã®çµäºå¦ç
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| 249 | */
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| 250 | void
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| 251 | target_exit(void)
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| 252 | {
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| 253 | /*
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| 254 | * ãããä¾åã®çµäºå¦ç
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| 255 | */
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| 256 | chip_terminate();
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| 257 |
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| 258 | /*
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| 259 | * ã¿ã¼ã²ããä¾åã®çµäºå¦ç
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| 260 | */
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| 261 | #if defined(TOPPERS_USE_QEMU) && !defined(TOPPERS_OMIT_QEMU_SEMIHOSTING)
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| 262 | /*
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| 263 | * QEMUãçµäºãããï¼
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| 264 | */
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| 265 | Asm("mov r0, #24\n\t"
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| 266 | "svc 0x00123456");
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| 267 | #endif
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| 268 | while (true) ;
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| 269 | }
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