[303] | 1 | /**
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| 2 | ******************************************************************************
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| 3 | * @file stm32f4xx_ll_fsmc.c
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| 4 | * @author MCD Application Team
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| 5 | * @version V1.4.1
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| 6 | * @date 09-October-2015
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| 7 | * @brief FSMC Low Layer HAL module driver.
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| 8 | *
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| 9 | * This file provides firmware functions to manage the following
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| 10 | * functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories:
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| 11 | * + Initialization/de-initialization functions
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| 12 | * + Peripheral Control functions
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| 13 | * + Peripheral State functions
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| 14 | *
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| 15 | @verbatim
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| 16 | ==============================================================================
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| 17 | ##### FSMC peripheral features #####
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| 18 | ==============================================================================
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| 19 | [..] The Flexible static memory controller (FSMC) includes two memory controllers:
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| 20 | (+) The NOR/PSRAM memory controller
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| 21 | (+) The NAND/PC Card memory controller
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| 22 |
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| 23 | [..] The FSMC functional block makes the interface with synchronous and asynchronous static
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| 24 | memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
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| 25 | (+) to translate AHB transactions into the appropriate external device protocol.
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| 26 | (+) to meet the access time requirements of the external memory devices.
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| 27 |
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| 28 | [..] All external memories share the addresses, data and control signals with the controller.
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| 29 | Each external device is accessed by means of a unique Chip Select. The FSMC performs
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| 30 | only one access at a time to an external device.
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| 31 | The main features of the FSMC controller are the following:
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| 32 | (+) Interface with static-memory mapped devices including:
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| 33 | (++) Static random access memory (SRAM).
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| 34 | (++) Read-only memory (ROM).
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| 35 | (++) NOR Flash memory/OneNAND Flash memory.
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| 36 | (++) PSRAM (4 memory banks).
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| 37 | (++) 16-bit PC Card compatible devices.
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| 38 | (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
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| 39 | data.
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| 40 | (+) Independent Chip Select control for each memory bank.
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| 41 | (+) Independent configuration for each memory bank.
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| 42 |
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| 43 | @endverbatim
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| 44 | ******************************************************************************
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| 45 | * @attention
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| 46 | *
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| 47 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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| 48 | *
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| 49 | * Redistribution and use in source and binary forms, with or without modification,
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| 50 | * are permitted provided that the following conditions are met:
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| 51 | * 1. Redistributions of source code must retain the above copyright notice,
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| 52 | * this list of conditions and the following disclaimer.
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| 53 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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| 54 | * this list of conditions and the following disclaimer in the documentation
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| 55 | * and/or other materials provided with the distribution.
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| 56 | * 3. Neither the name of STMicroelectronics nor the names of its contributors
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| 57 | * may be used to endorse or promote products derived from this software
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| 58 | * without specific prior written permission.
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| 59 | *
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| 60 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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| 61 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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| 62 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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| 63 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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| 64 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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| 65 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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| 66 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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| 67 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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| 68 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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| 69 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 70 | *
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| 71 | ******************************************************************************
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| 72 | */
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| 73 |
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| 74 | /* Includes ------------------------------------------------------------------*/
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| 75 | #include "stm32f4xx_hal.h"
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| 76 |
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| 77 | /** @addtogroup STM32F4xx_HAL_Driver
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| 78 | * @{
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| 79 | */
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| 80 |
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| 81 | /** @defgroup FSMC_LL FSMC Low Layer
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| 82 | * @brief FSMC driver modules
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| 83 | * @{
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| 84 | */
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| 85 |
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| 86 | #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
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| 87 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
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| 88 | /* Private typedef -----------------------------------------------------------*/
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| 89 | /* Private define ------------------------------------------------------------*/
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| 90 | /* Private macro -------------------------------------------------------------*/
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| 91 | /* Private variables ---------------------------------------------------------*/
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| 92 | /* Private function prototypes -----------------------------------------------*/
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| 93 | /* Private functions ---------------------------------------------------------*/
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| 94 | /** @addtogroup FSMC_LL_Private_Functions
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| 95 | * @{
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| 96 | */
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| 97 |
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| 98 | /** @addtogroup FSMC_LL_NORSRAM
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| 99 | * @brief NORSRAM Controller functions
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| 100 | *
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| 101 | @verbatim
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| 102 | ==============================================================================
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| 103 | ##### How to use NORSRAM device driver #####
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| 104 | ==============================================================================
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| 105 |
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| 106 | [..]
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| 107 | This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
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| 108 | to run the NORSRAM external devices.
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| 109 |
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| 110 | (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
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| 111 | (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
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| 112 | (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
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| 113 | (+) FSMC NORSRAM bank extended timing configuration using the function
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| 114 | FSMC_NORSRAM_Extended_Timing_Init()
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| 115 | (+) FSMC NORSRAM bank enable/disable write operation using the functions
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| 116 | FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
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| 117 |
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| 118 | @endverbatim
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| 119 | * @{
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| 120 | */
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| 121 |
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| 122 | /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1
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| 123 | * @brief Initialization and Configuration functions
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| 124 | *
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| 125 | @verbatim
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| 126 | ==============================================================================
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| 127 | ##### Initialization and de_initialization functions #####
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| 128 | ==============================================================================
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| 129 | [..]
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| 130 | This section provides functions allowing to:
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| 131 | (+) Initialize and configure the FSMC NORSRAM interface
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| 132 | (+) De-initialize the FSMC NORSRAM interface
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| 133 | (+) Configure the FSMC clock and associated GPIOs
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| 134 |
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| 135 | @endverbatim
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| 136 | * @{
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| 137 | */
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| 138 |
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| 139 | /**
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| 140 | * @brief Initialize the FSMC_NORSRAM device according to the specified
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| 141 | * control parameters in the FSMC_NORSRAM_InitTypeDef
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| 142 | * @param Device: Pointer to NORSRAM device instance
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| 143 | * @param Init: Pointer to NORSRAM Initialization structure
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| 144 | * @retval HAL status
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| 145 | */
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| 146 | HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init)
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| 147 | {
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| 148 | uint32_t tmpr = 0;
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| 149 |
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| 150 | /* Check the parameters */
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| 151 | assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
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| 152 | assert_param(IS_FSMC_MUX(Init->DataAddressMux));
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| 153 | assert_param(IS_FSMC_MEMORY(Init->MemoryType));
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| 154 | assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
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| 155 | assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
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| 156 | assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
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| 157 | assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
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| 158 | assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
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| 159 | assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
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| 160 | assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
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| 161 | assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
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| 162 | assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
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| 163 | assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
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| 164 |
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| 165 | /* Get the BTCR register value */
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| 166 | tmpr = Device->BTCR[Init->NSBank];
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| 167 |
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| 168 | /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
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| 169 | WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */
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| 170 | tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \
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| 171 | FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \
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| 172 | FSMC_BCR1_WAITPOL | FSMC_BCR1_WRAPMOD | FSMC_BCR1_WAITCFG | \
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| 173 | FSMC_BCR1_WREN | FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | \
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| 174 | FSMC_BCR1_ASYNCWAIT | FSMC_BCR1_CBURSTRW));
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| 175 | /* Set NORSRAM device control parameters */
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| 176 | tmpr |= (uint32_t)(Init->DataAddressMux |\
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| 177 | Init->MemoryType |\
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| 178 | Init->MemoryDataWidth |\
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| 179 | Init->BurstAccessMode |\
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| 180 | Init->WaitSignalPolarity |\
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| 181 | Init->WrapMode |\
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| 182 | Init->WaitSignalActive |\
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| 183 | Init->WriteOperation |\
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| 184 | Init->WaitSignal |\
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| 185 | Init->ExtendedMode |\
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| 186 | Init->AsynchronousWait |\
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| 187 | Init->WriteBurst
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| 188 | );
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| 189 |
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| 190 | if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
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| 191 | {
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| 192 | tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
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| 193 | }
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| 194 |
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| 195 | Device->BTCR[Init->NSBank] = tmpr;
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| 196 |
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| 197 | return HAL_OK;
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| 198 | }
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| 199 |
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| 200 | /**
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| 201 | * @brief DeInitialize the FSMC_NORSRAM peripheral
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| 202 | * @param Device: Pointer to NORSRAM device instance
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| 203 | * @param ExDevice: Pointer to NORSRAM extended mode device instance
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| 204 | * @param Bank: NORSRAM bank number
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| 205 | * @retval HAL status
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| 206 | */
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| 207 | HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
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| 208 | {
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| 209 | /* Check the parameters */
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| 210 | assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
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| 211 | assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
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| 212 |
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| 213 | /* Disable the FSMC_NORSRAM device */
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| 214 | __FSMC_NORSRAM_DISABLE(Device, Bank);
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| 215 |
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| 216 | /* De-initialize the FSMC_NORSRAM device */
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| 217 | /* FSMC_NORSRAM_BANK1 */
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| 218 | if(Bank == FSMC_NORSRAM_BANK1)
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| 219 | {
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| 220 | Device->BTCR[Bank] = 0x000030DB;
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| 221 | }
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| 222 | /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
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| 223 | else
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| 224 | {
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| 225 | Device->BTCR[Bank] = 0x000030D2;
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| 226 | }
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| 227 |
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| 228 | Device->BTCR[Bank + 1] = 0x0FFFFFFF;
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| 229 | ExDevice->BWTR[Bank] = 0x0FFFFFFF;
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| 230 |
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| 231 | return HAL_OK;
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| 232 | }
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| 233 |
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| 234 |
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| 235 | /**
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| 236 | * @brief Initialize the FSMC_NORSRAM Timing according to the specified
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| 237 | * parameters in the FSMC_NORSRAM_TimingTypeDef
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| 238 | * @param Device: Pointer to NORSRAM device instance
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| 239 | * @param Timing: Pointer to NORSRAM Timing structure
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| 240 | * @param Bank: NORSRAM bank number
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| 241 | * @retval HAL status
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| 242 | */
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| 243 | HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
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| 244 | {
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| 245 | uint32_t tmpr = 0;
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| 246 |
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| 247 | /* Check the parameters */
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| 248 | assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
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| 249 | assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
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| 250 | assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
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| 251 | assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
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| 252 | assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
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| 253 | assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
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| 254 | assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
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| 255 |
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| 256 | /* Get the BTCR register value */
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| 257 | tmpr = Device->BTCR[Bank + 1];
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| 258 |
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| 259 | /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
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| 260 | tmpr &= ((uint32_t)~(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD | FSMC_BTR1_DATAST | \
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| 261 | FSMC_BTR1_BUSTURN | FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT | \
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| 262 | FSMC_BTR1_ACCMOD));
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| 263 |
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| 264 | /* Set FSMC_NORSRAM device timing parameters */
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| 265 | tmpr |= (uint32_t)(Timing->AddressSetupTime |\
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| 266 | ((Timing->AddressHoldTime) << 4) |\
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| 267 | ((Timing->DataSetupTime) << 8) |\
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| 268 | ((Timing->BusTurnAroundDuration) << 16) |\
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| 269 | (((Timing->CLKDivision)-1) << 20) |\
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| 270 | (((Timing->DataLatency)-2) << 24) |\
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| 271 | (Timing->AccessMode));
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| 272 |
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| 273 | Device->BTCR[Bank + 1] = tmpr;
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| 274 |
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| 275 | return HAL_OK;
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| 276 | }
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| 277 |
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| 278 | /**
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| 279 | * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
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| 280 | * parameters in the FSMC_NORSRAM_TimingTypeDef
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| 281 | * @param Device: Pointer to NORSRAM device instance
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| 282 | * @param Timing: Pointer to NORSRAM Timing structure
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| 283 | * @param Bank: NORSRAM bank number
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| 284 | * @retval HAL status
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| 285 | */
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| 286 | HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
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| 287 | {
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| 288 | uint32_t tmpr = 0;
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| 289 |
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| 290 | /* Set NORSRAM device timing register for write configuration, if extended mode is used */
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| 291 | if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
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| 292 | {
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| 293 | /* Check the parameters */
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| 294 | assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
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| 295 | assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
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| 296 | assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
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| 297 | assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
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| 298 | assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
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| 299 | assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
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| 300 | assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
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| 301 |
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| 302 | /* Get the BWTR register value */
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| 303 | tmpr = Device->BWTR[Bank];
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| 304 |
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| 305 | /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
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| 306 | tmpr &= ((uint32_t)~(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD | FSMC_BWTR1_DATAST | \
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| 307 | FSMC_BWTR1_BUSTURN | FSMC_BWTR1_CLKDIV | FSMC_BWTR1_DATLAT | \
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| 308 | FSMC_BWTR1_ACCMOD));
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| 309 |
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| 310 | tmpr |= (uint32_t)(Timing->AddressSetupTime |\
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| 311 | ((Timing->AddressHoldTime) << 4) |\
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| 312 | ((Timing->DataSetupTime) << 8) |\
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| 313 | ((Timing->BusTurnAroundDuration) << 16) |\
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| 314 | (((Timing->CLKDivision)-1) << 20) |\
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| 315 | (((Timing->DataLatency)-2) << 24) |\
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| 316 | (Timing->AccessMode));
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| 317 |
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| 318 | Device->BWTR[Bank] = tmpr;
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| 319 | }
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| 320 | else
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| 321 | {
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| 322 | Device->BWTR[Bank] = 0x0FFFFFFF;
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| 323 | }
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| 324 |
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| 325 | return HAL_OK;
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| 326 | }
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| 327 | /**
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| 328 | * @}
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| 329 | */
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| 330 |
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| 331 | /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
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| 332 | * @brief management functions
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| 333 | *
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| 334 | @verbatim
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| 335 | ==============================================================================
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| 336 | ##### FSMC_NORSRAM Control functions #####
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| 337 | ==============================================================================
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| 338 | [..]
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| 339 | This subsection provides a set of functions allowing to control dynamically
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| 340 | the FSMC NORSRAM interface.
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| 341 |
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| 342 | @endverbatim
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| 343 | * @{
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| 344 | */
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| 345 |
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| 346 | /**
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| 347 | * @brief Enables dynamically FSMC_NORSRAM write operation.
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| 348 | * @param Device: Pointer to NORSRAM device instance
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| 349 | * @param Bank: NORSRAM bank number
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| 350 | * @retval HAL status
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| 351 | */
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| 352 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
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| 353 | {
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| 354 | /* Enable write operation */
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| 355 | Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE;
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| 356 |
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| 357 | return HAL_OK;
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| 358 | }
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| 359 |
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| 360 | /**
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| 361 | * @brief Disables dynamically FSMC_NORSRAM write operation.
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| 362 | * @param Device: Pointer to NORSRAM device instance
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| 363 | * @param Bank: NORSRAM bank number
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| 364 | * @retval HAL status
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| 365 | */
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| 366 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
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| 367 | {
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| 368 | /* Disable write operation */
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| 369 | Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE;
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| 370 |
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| 371 | return HAL_OK;
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| 372 | }
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| 373 | /**
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| 374 | * @}
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| 375 | */
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| 376 |
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| 377 | /**
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| 378 | * @}
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| 379 | */
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| 380 |
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| 381 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
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| 382 | /** @addtogroup FSMC_LL_NAND
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| 383 | * @brief NAND Controller functions
|
---|
| 384 | *
|
---|
| 385 | @verbatim
|
---|
| 386 | ==============================================================================
|
---|
| 387 | ##### How to use NAND device driver #####
|
---|
| 388 | ==============================================================================
|
---|
| 389 | [..]
|
---|
| 390 | This driver contains a set of APIs to interface with the FSMC NAND banks in order
|
---|
| 391 | to run the NAND external devices.
|
---|
| 392 |
|
---|
| 393 | (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
|
---|
| 394 | (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
|
---|
| 395 | (+) FSMC NAND bank common space timing configuration using the function
|
---|
| 396 | FSMC_NAND_CommonSpace_Timing_Init()
|
---|
| 397 | (+) FSMC NAND bank attribute space timing configuration using the function
|
---|
| 398 | FSMC_NAND_AttributeSpace_Timing_Init()
|
---|
| 399 | (+) FSMC NAND bank enable/disable ECC correction feature using the functions
|
---|
| 400 | FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
|
---|
| 401 | (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
|
---|
| 402 |
|
---|
| 403 | @endverbatim
|
---|
| 404 | * @{
|
---|
| 405 | */
|
---|
| 406 |
|
---|
| 407 | /** @addtogroup FSMC_LL_NAND_Private_Functions_Group1
|
---|
| 408 | * @brief Initialization and Configuration functions
|
---|
| 409 | *
|
---|
| 410 | @verbatim
|
---|
| 411 | ==============================================================================
|
---|
| 412 | ##### Initialization and de_initialization functions #####
|
---|
| 413 | ==============================================================================
|
---|
| 414 | [..]
|
---|
| 415 | This section provides functions allowing to:
|
---|
| 416 | (+) Initialize and configure the FSMC NAND interface
|
---|
| 417 | (+) De-initialize the FSMC NAND interface
|
---|
| 418 | (+) Configure the FSMC clock and associated GPIOs
|
---|
| 419 |
|
---|
| 420 | @endverbatim
|
---|
| 421 | * @{
|
---|
| 422 | */
|
---|
| 423 |
|
---|
| 424 | /**
|
---|
| 425 | * @brief Initializes the FSMC_NAND device according to the specified
|
---|
| 426 | * control parameters in the FSMC_NAND_HandleTypeDef
|
---|
| 427 | * @param Device: Pointer to NAND device instance
|
---|
| 428 | * @param Init: Pointer to NAND Initialization structure
|
---|
| 429 | * @retval HAL status
|
---|
| 430 | */
|
---|
| 431 | HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
|
---|
| 432 | {
|
---|
| 433 | uint32_t tmpr = 0;
|
---|
| 434 |
|
---|
| 435 | /* Check the parameters */
|
---|
| 436 | assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
|
---|
| 437 | assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
|
---|
| 438 | assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
|
---|
| 439 | assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
|
---|
| 440 | assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
|
---|
| 441 | assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
|
---|
| 442 | assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
|
---|
| 443 |
|
---|
| 444 | if(Init->NandBank == FSMC_NAND_BANK2)
|
---|
| 445 | {
|
---|
| 446 | /* Get the NAND bank 2 register value */
|
---|
| 447 | tmpr = Device->PCR2;
|
---|
| 448 | }
|
---|
| 449 | else
|
---|
| 450 | {
|
---|
| 451 | /* Get the NAND bank 3 register value */
|
---|
| 452 | tmpr = Device->PCR3;
|
---|
| 453 | }
|
---|
| 454 |
|
---|
| 455 | /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
|
---|
| 456 | tmpr &= ((uint32_t)~(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | FSMC_PCR2_PTYP | \
|
---|
| 457 | FSMC_PCR2_PWID | FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \
|
---|
| 458 | FSMC_PCR2_TAR | FSMC_PCR2_ECCPS));
|
---|
| 459 |
|
---|
| 460 | /* Set NAND device control parameters */
|
---|
| 461 | tmpr |= (uint32_t)(Init->Waitfeature |\
|
---|
| 462 | FSMC_PCR_MEMORY_TYPE_NAND |\
|
---|
| 463 | Init->MemoryDataWidth |\
|
---|
| 464 | Init->EccComputation |\
|
---|
| 465 | Init->ECCPageSize |\
|
---|
| 466 | ((Init->TCLRSetupTime) << 9) |\
|
---|
| 467 | ((Init->TARSetupTime) << 13));
|
---|
| 468 |
|
---|
| 469 | if(Init->NandBank == FSMC_NAND_BANK2)
|
---|
| 470 | {
|
---|
| 471 | /* NAND bank 2 registers configuration */
|
---|
| 472 | Device->PCR2 = tmpr;
|
---|
| 473 | }
|
---|
| 474 | else
|
---|
| 475 | {
|
---|
| 476 | /* NAND bank 3 registers configuration */
|
---|
| 477 | Device->PCR3 = tmpr;
|
---|
| 478 | }
|
---|
| 479 |
|
---|
| 480 | return HAL_OK;
|
---|
| 481 | }
|
---|
| 482 |
|
---|
| 483 | /**
|
---|
| 484 | * @brief Initializes the FSMC_NAND Common space Timing according to the specified
|
---|
| 485 | * parameters in the FSMC_NAND_PCC_TimingTypeDef
|
---|
| 486 | * @param Device: Pointer to NAND device instance
|
---|
| 487 | * @param Timing: Pointer to NAND timing structure
|
---|
| 488 | * @param Bank: NAND bank number
|
---|
| 489 | * @retval HAL status
|
---|
| 490 | */
|
---|
| 491 | HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
|
---|
| 492 | {
|
---|
| 493 | uint32_t tmpr = 0;
|
---|
| 494 |
|
---|
| 495 | /* Check the parameters */
|
---|
| 496 | assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
|
---|
| 497 | assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
|
---|
| 498 | assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
|
---|
| 499 | assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
|
---|
| 500 |
|
---|
| 501 | if(Bank == FSMC_NAND_BANK2)
|
---|
| 502 | {
|
---|
| 503 | /* Get the NAND bank 2 register value */
|
---|
| 504 | tmpr = Device->PMEM2;
|
---|
| 505 | }
|
---|
| 506 | else
|
---|
| 507 | {
|
---|
| 508 | /* Get the NAND bank 3 register value */
|
---|
| 509 | tmpr = Device->PMEM3;
|
---|
| 510 | }
|
---|
| 511 |
|
---|
| 512 | /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
|
---|
| 513 | tmpr &= ((uint32_t)~(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 | FSMC_PMEM2_MEMHOLD2 | \
|
---|
| 514 | FSMC_PMEM2_MEMHIZ2));
|
---|
| 515 |
|
---|
| 516 | /* Set FSMC_NAND device timing parameters */
|
---|
| 517 | tmpr |= (uint32_t)(Timing->SetupTime |\
|
---|
| 518 | ((Timing->WaitSetupTime) << 8) |\
|
---|
| 519 | ((Timing->HoldSetupTime) << 16) |\
|
---|
| 520 | ((Timing->HiZSetupTime) << 24)
|
---|
| 521 | );
|
---|
| 522 |
|
---|
| 523 | if(Bank == FSMC_NAND_BANK2)
|
---|
| 524 | {
|
---|
| 525 | /* NAND bank 2 registers configuration */
|
---|
| 526 | Device->PMEM2 = tmpr;
|
---|
| 527 | }
|
---|
| 528 | else
|
---|
| 529 | {
|
---|
| 530 | /* NAND bank 3 registers configuration */
|
---|
| 531 | Device->PMEM3 = tmpr;
|
---|
| 532 | }
|
---|
| 533 |
|
---|
| 534 | return HAL_OK;
|
---|
| 535 | }
|
---|
| 536 |
|
---|
| 537 | /**
|
---|
| 538 | * @brief Initializes the FSMC_NAND Attribute space Timing according to the specified
|
---|
| 539 | * parameters in the FSMC_NAND_PCC_TimingTypeDef
|
---|
| 540 | * @param Device: Pointer to NAND device instance
|
---|
| 541 | * @param Timing: Pointer to NAND timing structure
|
---|
| 542 | * @param Bank: NAND bank number
|
---|
| 543 | * @retval HAL status
|
---|
| 544 | */
|
---|
| 545 | HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
|
---|
| 546 | {
|
---|
| 547 | uint32_t tmpr = 0;
|
---|
| 548 |
|
---|
| 549 | /* Check the parameters */
|
---|
| 550 | assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
|
---|
| 551 | assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
|
---|
| 552 | assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
|
---|
| 553 | assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
|
---|
| 554 |
|
---|
| 555 | if(Bank == FSMC_NAND_BANK2)
|
---|
| 556 | {
|
---|
| 557 | /* Get the NAND bank 2 register value */
|
---|
| 558 | tmpr = Device->PATT2;
|
---|
| 559 | }
|
---|
| 560 | else
|
---|
| 561 | {
|
---|
| 562 | /* Get the NAND bank 3 register value */
|
---|
| 563 | tmpr = Device->PATT3;
|
---|
| 564 | }
|
---|
| 565 |
|
---|
| 566 | /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
|
---|
| 567 | tmpr &= ((uint32_t)~(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 | FSMC_PATT2_ATTHOLD2 | \
|
---|
| 568 | FSMC_PATT2_ATTHIZ2));
|
---|
| 569 |
|
---|
| 570 | /* Set FSMC_NAND device timing parameters */
|
---|
| 571 | tmpr |= (uint32_t)(Timing->SetupTime |\
|
---|
| 572 | ((Timing->WaitSetupTime) << 8) |\
|
---|
| 573 | ((Timing->HoldSetupTime) << 16) |\
|
---|
| 574 | ((Timing->HiZSetupTime) << 24)
|
---|
| 575 | );
|
---|
| 576 |
|
---|
| 577 | if(Bank == FSMC_NAND_BANK2)
|
---|
| 578 | {
|
---|
| 579 | /* NAND bank 2 registers configuration */
|
---|
| 580 | Device->PATT2 = tmpr;
|
---|
| 581 | }
|
---|
| 582 | else
|
---|
| 583 | {
|
---|
| 584 | /* NAND bank 3 registers configuration */
|
---|
| 585 | Device->PATT3 = tmpr;
|
---|
| 586 | }
|
---|
| 587 |
|
---|
| 588 | return HAL_OK;
|
---|
| 589 | }
|
---|
| 590 |
|
---|
| 591 | /**
|
---|
| 592 | * @brief DeInitializes the FSMC_NAND device
|
---|
| 593 | * @param Device: Pointer to NAND device instance
|
---|
| 594 | * @param Bank: NAND bank number
|
---|
| 595 | * @retval HAL status
|
---|
| 596 | */
|
---|
| 597 | HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
|
---|
| 598 | {
|
---|
| 599 | /* Disable the NAND Bank */
|
---|
| 600 | __FSMC_NAND_DISABLE(Device, Bank);
|
---|
| 601 |
|
---|
| 602 | /* De-initialize the NAND Bank */
|
---|
| 603 | if(Bank == FSMC_NAND_BANK2)
|
---|
| 604 | {
|
---|
| 605 | /* Set the FSMC_NAND_BANK2 registers to their reset values */
|
---|
| 606 | Device->PCR2 = 0x00000018;
|
---|
| 607 | Device->SR2 = 0x00000040;
|
---|
| 608 | Device->PMEM2 = 0xFCFCFCFC;
|
---|
| 609 | Device->PATT2 = 0xFCFCFCFC;
|
---|
| 610 | }
|
---|
| 611 | /* FSMC_Bank3_NAND */
|
---|
| 612 | else
|
---|
| 613 | {
|
---|
| 614 | /* Set the FSMC_NAND_BANK3 registers to their reset values */
|
---|
| 615 | Device->PCR3 = 0x00000018;
|
---|
| 616 | Device->SR3 = 0x00000040;
|
---|
| 617 | Device->PMEM3 = 0xFCFCFCFC;
|
---|
| 618 | Device->PATT3 = 0xFCFCFCFC;
|
---|
| 619 | }
|
---|
| 620 |
|
---|
| 621 | return HAL_OK;
|
---|
| 622 | }
|
---|
| 623 | /**
|
---|
| 624 | * @}
|
---|
| 625 | */
|
---|
| 626 |
|
---|
| 627 | /** @addtogroup FSMC_LL_NAND_Private_Functions_Group2
|
---|
| 628 | * @brief management functions
|
---|
| 629 | *
|
---|
| 630 | @verbatim
|
---|
| 631 | ==============================================================================
|
---|
| 632 | ##### FSMC_NAND Control functions #####
|
---|
| 633 | ==============================================================================
|
---|
| 634 | [..]
|
---|
| 635 | This subsection provides a set of functions allowing to control dynamically
|
---|
| 636 | the FSMC NAND interface.
|
---|
| 637 |
|
---|
| 638 | @endverbatim
|
---|
| 639 | * @{
|
---|
| 640 | */
|
---|
| 641 |
|
---|
| 642 | /**
|
---|
| 643 | * @brief Enables dynamically FSMC_NAND ECC feature.
|
---|
| 644 | * @param Device: Pointer to NAND device instance
|
---|
| 645 | * @param Bank: NAND bank number
|
---|
| 646 | * @retval HAL status
|
---|
| 647 | */
|
---|
| 648 | HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
|
---|
| 649 | {
|
---|
| 650 | /* Enable ECC feature */
|
---|
| 651 | if(Bank == FSMC_NAND_BANK2)
|
---|
| 652 | {
|
---|
| 653 | Device->PCR2 |= FSMC_PCR2_ECCEN;
|
---|
| 654 | }
|
---|
| 655 | else
|
---|
| 656 | {
|
---|
| 657 | Device->PCR3 |= FSMC_PCR3_ECCEN;
|
---|
| 658 | }
|
---|
| 659 |
|
---|
| 660 | return HAL_OK;
|
---|
| 661 | }
|
---|
| 662 |
|
---|
| 663 | /**
|
---|
| 664 | * @brief Disables dynamically FSMC_NAND ECC feature.
|
---|
| 665 | * @param Device: Pointer to NAND device instance
|
---|
| 666 | * @param Bank: NAND bank number
|
---|
| 667 | * @retval HAL status
|
---|
| 668 | */
|
---|
| 669 | HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
|
---|
| 670 | {
|
---|
| 671 | /* Disable ECC feature */
|
---|
| 672 | if(Bank == FSMC_NAND_BANK2)
|
---|
| 673 | {
|
---|
| 674 | Device->PCR2 &= ~FSMC_PCR2_ECCEN;
|
---|
| 675 | }
|
---|
| 676 | else
|
---|
| 677 | {
|
---|
| 678 | Device->PCR3 &= ~FSMC_PCR3_ECCEN;
|
---|
| 679 | }
|
---|
| 680 |
|
---|
| 681 | return HAL_OK;
|
---|
| 682 | }
|
---|
| 683 |
|
---|
| 684 | /**
|
---|
| 685 | * @brief Disables dynamically FSMC_NAND ECC feature.
|
---|
| 686 | * @param Device: Pointer to NAND device instance
|
---|
| 687 | * @param ECCval: Pointer to ECC value
|
---|
| 688 | * @param Bank: NAND bank number
|
---|
| 689 | * @param Timeout: Timeout wait value
|
---|
| 690 | * @retval HAL status
|
---|
| 691 | */
|
---|
| 692 | HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
|
---|
| 693 | {
|
---|
| 694 | uint32_t tickstart = 0;
|
---|
| 695 |
|
---|
| 696 | /* Check the parameters */
|
---|
| 697 | assert_param(IS_FSMC_NAND_DEVICE(Device));
|
---|
| 698 | assert_param(IS_FSMC_NAND_BANK(Bank));
|
---|
| 699 |
|
---|
| 700 | /* Get tick */
|
---|
| 701 | tickstart = HAL_GetTick();
|
---|
| 702 |
|
---|
| 703 | /* Wait until FIFO is empty */
|
---|
| 704 | while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
|
---|
| 705 | {
|
---|
| 706 | /* Check for the Timeout */
|
---|
| 707 | if(Timeout != HAL_MAX_DELAY)
|
---|
| 708 | {
|
---|
| 709 | if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
|
---|
| 710 | {
|
---|
| 711 | return HAL_TIMEOUT;
|
---|
| 712 | }
|
---|
| 713 | }
|
---|
| 714 | }
|
---|
| 715 |
|
---|
| 716 | if(Bank == FSMC_NAND_BANK2)
|
---|
| 717 | {
|
---|
| 718 | /* Get the ECCR2 register value */
|
---|
| 719 | *ECCval = (uint32_t)Device->ECCR2;
|
---|
| 720 | }
|
---|
| 721 | else
|
---|
| 722 | {
|
---|
| 723 | /* Get the ECCR3 register value */
|
---|
| 724 | *ECCval = (uint32_t)Device->ECCR3;
|
---|
| 725 | }
|
---|
| 726 |
|
---|
| 727 | return HAL_OK;
|
---|
| 728 | }
|
---|
| 729 |
|
---|
| 730 | /**
|
---|
| 731 | * @}
|
---|
| 732 | */
|
---|
| 733 |
|
---|
| 734 | /**
|
---|
| 735 | * @}
|
---|
| 736 | */
|
---|
| 737 |
|
---|
| 738 | /** @addtogroup FSMC_LL_PCCARD
|
---|
| 739 | * @brief PCCARD Controller functions
|
---|
| 740 | *
|
---|
| 741 | @verbatim
|
---|
| 742 | ==============================================================================
|
---|
| 743 | ##### How to use PCCARD device driver #####
|
---|
| 744 | ==============================================================================
|
---|
| 745 | [..]
|
---|
| 746 | This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
|
---|
| 747 | to run the PCCARD/compact flash external devices.
|
---|
| 748 |
|
---|
| 749 | (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
|
---|
| 750 | (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
|
---|
| 751 | (+) FSMC PCCARD bank common space timing configuration using the function
|
---|
| 752 | FSMC_PCCARD_CommonSpace_Timing_Init()
|
---|
| 753 | (+) FSMC PCCARD bank attribute space timing configuration using the function
|
---|
| 754 | FSMC_PCCARD_AttributeSpace_Timing_Init()
|
---|
| 755 | (+) FSMC PCCARD bank IO space timing configuration using the function
|
---|
| 756 | FSMC_PCCARD_IOSpace_Timing_Init()
|
---|
| 757 |
|
---|
| 758 | @endverbatim
|
---|
| 759 | * @{
|
---|
| 760 | */
|
---|
| 761 |
|
---|
| 762 | /** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1
|
---|
| 763 | * @brief Initialization and Configuration functions
|
---|
| 764 | *
|
---|
| 765 | @verbatim
|
---|
| 766 | ==============================================================================
|
---|
| 767 | ##### Initialization and de_initialization functions #####
|
---|
| 768 | ==============================================================================
|
---|
| 769 | [..]
|
---|
| 770 | This section provides functions allowing to:
|
---|
| 771 | (+) Initialize and configure the FSMC PCCARD interface
|
---|
| 772 | (+) De-initialize the FSMC PCCARD interface
|
---|
| 773 | (+) Configure the FSMC clock and associated GPIOs
|
---|
| 774 |
|
---|
| 775 | @endverbatim
|
---|
| 776 | * @{
|
---|
| 777 | */
|
---|
| 778 |
|
---|
| 779 | /**
|
---|
| 780 | * @brief Initializes the FSMC_PCCARD device according to the specified
|
---|
| 781 | * control parameters in the FSMC_PCCARD_HandleTypeDef
|
---|
| 782 | * @param Device: Pointer to PCCARD device instance
|
---|
| 783 | * @param Init: Pointer to PCCARD Initialization structure
|
---|
| 784 | * @retval HAL status
|
---|
| 785 | */
|
---|
| 786 | HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
|
---|
| 787 | {
|
---|
| 788 | uint32_t tmpr = 0;
|
---|
| 789 |
|
---|
| 790 | /* Check the parameters */
|
---|
| 791 | assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
|
---|
| 792 | assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
|
---|
| 793 | assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
|
---|
| 794 |
|
---|
| 795 | /* Get PCCARD control register value */
|
---|
| 796 | tmpr = Device->PCR4;
|
---|
| 797 |
|
---|
| 798 | /* Clear TAR, TCLR, PWAITEN and PWID bits */
|
---|
| 799 | tmpr &= ((uint32_t)~(FSMC_PCR4_TAR | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \
|
---|
| 800 | FSMC_PCR4_PWID));
|
---|
| 801 |
|
---|
| 802 | /* Set FSMC_PCCARD device control parameters */
|
---|
| 803 | tmpr |= (uint32_t)(Init->Waitfeature |\
|
---|
| 804 | FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
|
---|
| 805 | (Init->TCLRSetupTime << 9) |\
|
---|
| 806 | (Init->TARSetupTime << 13));
|
---|
| 807 |
|
---|
| 808 | Device->PCR4 = tmpr;
|
---|
| 809 |
|
---|
| 810 | return HAL_OK;
|
---|
| 811 | }
|
---|
| 812 |
|
---|
| 813 | /**
|
---|
| 814 | * @brief Initializes the FSMC_PCCARD Common space Timing according to the specified
|
---|
| 815 | * parameters in the FSMC_NAND_PCC_TimingTypeDef
|
---|
| 816 | * @param Device: Pointer to PCCARD device instance
|
---|
| 817 | * @param Timing: Pointer to PCCARD timing structure
|
---|
| 818 | * @retval HAL status
|
---|
| 819 | */
|
---|
| 820 | HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
|
---|
| 821 | {
|
---|
| 822 | uint32_t tmpr = 0;
|
---|
| 823 |
|
---|
| 824 | /* Check the parameters */
|
---|
| 825 | assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
|
---|
| 826 | assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
|
---|
| 827 | assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
|
---|
| 828 | assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
|
---|
| 829 |
|
---|
| 830 | /* Get PCCARD common space timing register value */
|
---|
| 831 | tmpr = Device->PMEM4;
|
---|
| 832 |
|
---|
| 833 | /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
|
---|
| 834 | tmpr &= ((uint32_t)~(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 | FSMC_PMEM4_MEMHOLD4 | \
|
---|
| 835 | FSMC_PMEM4_MEMHIZ4));
|
---|
| 836 | /* Set PCCARD timing parameters */
|
---|
| 837 | tmpr |= (uint32_t)((Timing->SetupTime |\
|
---|
| 838 | ((Timing->WaitSetupTime) << 8) |\
|
---|
| 839 | (Timing->HoldSetupTime) << 16) |\
|
---|
| 840 | ((Timing->HiZSetupTime) << 24));
|
---|
| 841 |
|
---|
| 842 | Device->PMEM4 = tmpr;
|
---|
| 843 |
|
---|
| 844 | return HAL_OK;
|
---|
| 845 | }
|
---|
| 846 |
|
---|
| 847 | /**
|
---|
| 848 | * @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified
|
---|
| 849 | * parameters in the FSMC_NAND_PCC_TimingTypeDef
|
---|
| 850 | * @param Device: Pointer to PCCARD device instance
|
---|
| 851 | * @param Timing: Pointer to PCCARD timing structure
|
---|
| 852 | * @retval HAL status
|
---|
| 853 | */
|
---|
| 854 | HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
|
---|
| 855 | {
|
---|
| 856 | uint32_t tmpr = 0;
|
---|
| 857 |
|
---|
| 858 | /* Check the parameters */
|
---|
| 859 | assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
|
---|
| 860 | assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
|
---|
| 861 | assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
|
---|
| 862 | assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
|
---|
| 863 |
|
---|
| 864 | /* Get PCCARD timing parameters */
|
---|
| 865 | tmpr = Device->PATT4;
|
---|
| 866 |
|
---|
| 867 | /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
|
---|
| 868 | tmpr &= ((uint32_t)~(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 | FSMC_PATT4_ATTHOLD4 | \
|
---|
| 869 | FSMC_PATT4_ATTHIZ4));
|
---|
| 870 |
|
---|
| 871 | /* Set PCCARD timing parameters */
|
---|
| 872 | tmpr |= (uint32_t)(Timing->SetupTime |\
|
---|
| 873 | ((Timing->WaitSetupTime) << 8) |\
|
---|
| 874 | ((Timing->HoldSetupTime) << 16) |\
|
---|
| 875 | ((Timing->HiZSetupTime) << 24));
|
---|
| 876 | Device->PATT4 = tmpr;
|
---|
| 877 |
|
---|
| 878 | return HAL_OK;
|
---|
| 879 | }
|
---|
| 880 |
|
---|
| 881 | /**
|
---|
| 882 | * @brief Initializes the FSMC_PCCARD IO space Timing according to the specified
|
---|
| 883 | * parameters in the FSMC_NAND_PCC_TimingTypeDef
|
---|
| 884 | * @param Device: Pointer to PCCARD device instance
|
---|
| 885 | * @param Timing: Pointer to PCCARD timing structure
|
---|
| 886 | * @retval HAL status
|
---|
| 887 | */
|
---|
| 888 | HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
|
---|
| 889 | {
|
---|
| 890 | uint32_t tmpr = 0;
|
---|
| 891 |
|
---|
| 892 | /* Check the parameters */
|
---|
| 893 | assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
|
---|
| 894 | assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
|
---|
| 895 | assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
|
---|
| 896 | assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
|
---|
| 897 |
|
---|
| 898 | /* Get FSMC_PCCARD device timing parameters */
|
---|
| 899 | tmpr = Device->PIO4;
|
---|
| 900 |
|
---|
| 901 | /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
|
---|
| 902 | tmpr &= ((uint32_t)~(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | FSMC_PIO4_IOHOLD4 | \
|
---|
| 903 | FSMC_PIO4_IOHIZ4));
|
---|
| 904 |
|
---|
| 905 | /* Set FSMC_PCCARD device timing parameters */
|
---|
| 906 | tmpr |= (uint32_t)(Timing->SetupTime |\
|
---|
| 907 | ((Timing->WaitSetupTime) << 8) |\
|
---|
| 908 | ((Timing->HoldSetupTime) << 16) |\
|
---|
| 909 | ((Timing->HiZSetupTime) << 24));
|
---|
| 910 |
|
---|
| 911 | Device->PIO4 = tmpr;
|
---|
| 912 |
|
---|
| 913 | return HAL_OK;
|
---|
| 914 | }
|
---|
| 915 |
|
---|
| 916 | /**
|
---|
| 917 | * @brief DeInitializes the FSMC_PCCARD device
|
---|
| 918 | * @param Device: Pointer to PCCARD device instance
|
---|
| 919 | * @retval HAL status
|
---|
| 920 | */
|
---|
| 921 | HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
|
---|
| 922 | {
|
---|
| 923 | /* Disable the FSMC_PCCARD device */
|
---|
| 924 | __FSMC_PCCARD_DISABLE(Device);
|
---|
| 925 |
|
---|
| 926 | /* De-initialize the FSMC_PCCARD device */
|
---|
| 927 | Device->PCR4 = 0x00000018;
|
---|
| 928 | Device->SR4 = 0x00000000;
|
---|
| 929 | Device->PMEM4 = 0xFCFCFCFC;
|
---|
| 930 | Device->PATT4 = 0xFCFCFCFC;
|
---|
| 931 | Device->PIO4 = 0xFCFCFCFC;
|
---|
| 932 |
|
---|
| 933 | return HAL_OK;
|
---|
| 934 | }
|
---|
| 935 | /**
|
---|
| 936 | * @}
|
---|
| 937 | */
|
---|
| 938 |
|
---|
| 939 | /**
|
---|
| 940 | * @}
|
---|
| 941 | */
|
---|
| 942 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
|
---|
| 943 |
|
---|
| 944 | /**
|
---|
| 945 | * @}
|
---|
| 946 | */
|
---|
| 947 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
|
---|
| 948 | #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */
|
---|
| 949 |
|
---|
| 950 | /**
|
---|
| 951 | * @}
|
---|
| 952 | */
|
---|
| 953 |
|
---|
| 954 | /**
|
---|
| 955 | * @}
|
---|
| 956 | */
|
---|
| 957 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
---|