source: asp3_wo_tecs/trunk/arch/arm_m_gcc/stm32f4xx_stm32cube/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c@ 303

Last change on this file since 303 was 303, checked in by ertl-honda, 7 years ago

nucleo_f401re依存部の追加
File size: 33.3 KB
Line 
1/**
2 ******************************************************************************
3 * @file stm32f4xx_ll_fsmc.c
4 * @author MCD Application Team
5 * @version V1.4.1
6 * @date 09-October-2015
7 * @brief FSMC Low Layer HAL module driver.
8 *
9 * This file provides firmware functions to manage the following
10 * functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories:
11 * + Initialization/de-initialization functions
12 * + Peripheral Control functions
13 * + Peripheral State functions
14 *
15 @verbatim
16 ==============================================================================
17 ##### FSMC peripheral features #####
18 ==============================================================================
19 [..] The Flexible static memory controller (FSMC) includes two memory controllers:
20 (+) The NOR/PSRAM memory controller
21 (+) The NAND/PC Card memory controller
22
23 [..] The FSMC functional block makes the interface with synchronous and asynchronous static
24 memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
25 (+) to translate AHB transactions into the appropriate external device protocol.
26 (+) to meet the access time requirements of the external memory devices.
27
28 [..] All external memories share the addresses, data and control signals with the controller.
29 Each external device is accessed by means of a unique Chip Select. The FSMC performs
30 only one access at a time to an external device.
31 The main features of the FSMC controller are the following:
32 (+) Interface with static-memory mapped devices including:
33 (++) Static random access memory (SRAM).
34 (++) Read-only memory (ROM).
35 (++) NOR Flash memory/OneNAND Flash memory.
36 (++) PSRAM (4 memory banks).
37 (++) 16-bit PC Card compatible devices.
38 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
39 data.
40 (+) Independent Chip Select control for each memory bank.
41 (+) Independent configuration for each memory bank.
42
43 @endverbatim
44 ******************************************************************************
45 * @attention
46 *
47 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
48 *
49 * Redistribution and use in source and binary forms, with or without modification,
50 * are permitted provided that the following conditions are met:
51 * 1. Redistributions of source code must retain the above copyright notice,
52 * this list of conditions and the following disclaimer.
53 * 2. Redistributions in binary form must reproduce the above copyright notice,
54 * this list of conditions and the following disclaimer in the documentation
55 * and/or other materials provided with the distribution.
56 * 3. Neither the name of STMicroelectronics nor the names of its contributors
57 * may be used to endorse or promote products derived from this software
58 * without specific prior written permission.
59 *
60 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
61 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
63 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
66 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
67 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
68 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
69 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
70 *
71 ******************************************************************************
72 */
73
74/* Includes ------------------------------------------------------------------*/
75#include "stm32f4xx_hal.h"
76
77/** @addtogroup STM32F4xx_HAL_Driver
78 * @{
79 */
80
81/** @defgroup FSMC_LL FSMC Low Layer
82 * @brief FSMC driver modules
83 * @{
84 */
85
86#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
87#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
88/* Private typedef -----------------------------------------------------------*/
89/* Private define ------------------------------------------------------------*/
90/* Private macro -------------------------------------------------------------*/
91/* Private variables ---------------------------------------------------------*/
92/* Private function prototypes -----------------------------------------------*/
93/* Private functions ---------------------------------------------------------*/
94/** @addtogroup FSMC_LL_Private_Functions
95 * @{
96 */
97
98/** @addtogroup FSMC_LL_NORSRAM
99 * @brief NORSRAM Controller functions
100 *
101 @verbatim
102 ==============================================================================
103 ##### How to use NORSRAM device driver #####
104 ==============================================================================
105
106 [..]
107 This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
108 to run the NORSRAM external devices.
109
110 (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
111 (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
112 (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
113 (+) FSMC NORSRAM bank extended timing configuration using the function
114 FSMC_NORSRAM_Extended_Timing_Init()
115 (+) FSMC NORSRAM bank enable/disable write operation using the functions
116 FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
117
118@endverbatim
119 * @{
120 */
121
122/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1
123 * @brief Initialization and Configuration functions
124 *
125 @verbatim
126 ==============================================================================
127 ##### Initialization and de_initialization functions #####
128 ==============================================================================
129 [..]
130 This section provides functions allowing to:
131 (+) Initialize and configure the FSMC NORSRAM interface
132 (+) De-initialize the FSMC NORSRAM interface
133 (+) Configure the FSMC clock and associated GPIOs
134
135@endverbatim
136 * @{
137 */
138
139/**
140 * @brief Initialize the FSMC_NORSRAM device according to the specified
141 * control parameters in the FSMC_NORSRAM_InitTypeDef
142 * @param Device: Pointer to NORSRAM device instance
143 * @param Init: Pointer to NORSRAM Initialization structure
144 * @retval HAL status
145 */
146HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init)
147{
148 uint32_t tmpr = 0;
149
150 /* Check the parameters */
151 assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
152 assert_param(IS_FSMC_MUX(Init->DataAddressMux));
153 assert_param(IS_FSMC_MEMORY(Init->MemoryType));
154 assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
155 assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
156 assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
157 assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
158 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
159 assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
160 assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
161 assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
162 assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
163 assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
164
165 /* Get the BTCR register value */
166 tmpr = Device->BTCR[Init->NSBank];
167
168 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
169 WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */
170 tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \
171 FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \
172 FSMC_BCR1_WAITPOL | FSMC_BCR1_WRAPMOD | FSMC_BCR1_WAITCFG | \
173 FSMC_BCR1_WREN | FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | \
174 FSMC_BCR1_ASYNCWAIT | FSMC_BCR1_CBURSTRW));
175 /* Set NORSRAM device control parameters */
176 tmpr |= (uint32_t)(Init->DataAddressMux |\
177 Init->MemoryType |\
178 Init->MemoryDataWidth |\
179 Init->BurstAccessMode |\
180 Init->WaitSignalPolarity |\
181 Init->WrapMode |\
182 Init->WaitSignalActive |\
183 Init->WriteOperation |\
184 Init->WaitSignal |\
185 Init->ExtendedMode |\
186 Init->AsynchronousWait |\
187 Init->WriteBurst
188 );
189
190 if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
191 {
192 tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
193 }
194
195 Device->BTCR[Init->NSBank] = tmpr;
196
197 return HAL_OK;
198}
199
200/**
201 * @brief DeInitialize the FSMC_NORSRAM peripheral
202 * @param Device: Pointer to NORSRAM device instance
203 * @param ExDevice: Pointer to NORSRAM extended mode device instance
204 * @param Bank: NORSRAM bank number
205 * @retval HAL status
206 */
207HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
208{
209 /* Check the parameters */
210 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
211 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
212
213 /* Disable the FSMC_NORSRAM device */
214 __FSMC_NORSRAM_DISABLE(Device, Bank);
215
216 /* De-initialize the FSMC_NORSRAM device */
217 /* FSMC_NORSRAM_BANK1 */
218 if(Bank == FSMC_NORSRAM_BANK1)
219 {
220 Device->BTCR[Bank] = 0x000030DB;
221 }
222 /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
223 else
224 {
225 Device->BTCR[Bank] = 0x000030D2;
226 }
227
228 Device->BTCR[Bank + 1] = 0x0FFFFFFF;
229 ExDevice->BWTR[Bank] = 0x0FFFFFFF;
230
231 return HAL_OK;
232}
233
234
235/**
236 * @brief Initialize the FSMC_NORSRAM Timing according to the specified
237 * parameters in the FSMC_NORSRAM_TimingTypeDef
238 * @param Device: Pointer to NORSRAM device instance
239 * @param Timing: Pointer to NORSRAM Timing structure
240 * @param Bank: NORSRAM bank number
241 * @retval HAL status
242 */
243HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
244{
245 uint32_t tmpr = 0;
246
247 /* Check the parameters */
248 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
249 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
250 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
251 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
252 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
253 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
254 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
255
256 /* Get the BTCR register value */
257 tmpr = Device->BTCR[Bank + 1];
258
259 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
260 tmpr &= ((uint32_t)~(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD | FSMC_BTR1_DATAST | \
261 FSMC_BTR1_BUSTURN | FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT | \
262 FSMC_BTR1_ACCMOD));
263
264 /* Set FSMC_NORSRAM device timing parameters */
265 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
266 ((Timing->AddressHoldTime) << 4) |\
267 ((Timing->DataSetupTime) << 8) |\
268 ((Timing->BusTurnAroundDuration) << 16) |\
269 (((Timing->CLKDivision)-1) << 20) |\
270 (((Timing->DataLatency)-2) << 24) |\
271 (Timing->AccessMode));
272
273 Device->BTCR[Bank + 1] = tmpr;
274
275 return HAL_OK;
276}
277
278/**
279 * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
280 * parameters in the FSMC_NORSRAM_TimingTypeDef
281 * @param Device: Pointer to NORSRAM device instance
282 * @param Timing: Pointer to NORSRAM Timing structure
283 * @param Bank: NORSRAM bank number
284 * @retval HAL status
285 */
286HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
287{
288 uint32_t tmpr = 0;
289
290 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
291 if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
292 {
293 /* Check the parameters */
294 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
295 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
296 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
297 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
298 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
299 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
300 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
301
302 /* Get the BWTR register value */
303 tmpr = Device->BWTR[Bank];
304
305 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
306 tmpr &= ((uint32_t)~(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD | FSMC_BWTR1_DATAST | \
307 FSMC_BWTR1_BUSTURN | FSMC_BWTR1_CLKDIV | FSMC_BWTR1_DATLAT | \
308 FSMC_BWTR1_ACCMOD));
309
310 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
311 ((Timing->AddressHoldTime) << 4) |\
312 ((Timing->DataSetupTime) << 8) |\
313 ((Timing->BusTurnAroundDuration) << 16) |\
314 (((Timing->CLKDivision)-1) << 20) |\
315 (((Timing->DataLatency)-2) << 24) |\
316 (Timing->AccessMode));
317
318 Device->BWTR[Bank] = tmpr;
319 }
320 else
321 {
322 Device->BWTR[Bank] = 0x0FFFFFFF;
323 }
324
325 return HAL_OK;
326}
327/**
328 * @}
329 */
330
331/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
332 * @brief management functions
333 *
334@verbatim
335 ==============================================================================
336 ##### FSMC_NORSRAM Control functions #####
337 ==============================================================================
338 [..]
339 This subsection provides a set of functions allowing to control dynamically
340 the FSMC NORSRAM interface.
341
342@endverbatim
343 * @{
344 */
345
346/**
347 * @brief Enables dynamically FSMC_NORSRAM write operation.
348 * @param Device: Pointer to NORSRAM device instance
349 * @param Bank: NORSRAM bank number
350 * @retval HAL status
351 */
352HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
353{
354 /* Enable write operation */
355 Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE;
356
357 return HAL_OK;
358}
359
360/**
361 * @brief Disables dynamically FSMC_NORSRAM write operation.
362 * @param Device: Pointer to NORSRAM device instance
363 * @param Bank: NORSRAM bank number
364 * @retval HAL status
365 */
366HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
367{
368 /* Disable write operation */
369 Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE;
370
371 return HAL_OK;
372}
373/**
374 * @}
375 */
376
377/**
378 * @}
379 */
380
381#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
382/** @addtogroup FSMC_LL_NAND
383 * @brief NAND Controller functions
384 *
385 @verbatim
386 ==============================================================================
387 ##### How to use NAND device driver #####
388 ==============================================================================
389 [..]
390 This driver contains a set of APIs to interface with the FSMC NAND banks in order
391 to run the NAND external devices.
392
393 (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
394 (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
395 (+) FSMC NAND bank common space timing configuration using the function
396 FSMC_NAND_CommonSpace_Timing_Init()
397 (+) FSMC NAND bank attribute space timing configuration using the function
398 FSMC_NAND_AttributeSpace_Timing_Init()
399 (+) FSMC NAND bank enable/disable ECC correction feature using the functions
400 FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
401 (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
402
403@endverbatim
404 * @{
405 */
406
407/** @addtogroup FSMC_LL_NAND_Private_Functions_Group1
408 * @brief Initialization and Configuration functions
409 *
410@verbatim
411 ==============================================================================
412 ##### Initialization and de_initialization functions #####
413 ==============================================================================
414 [..]
415 This section provides functions allowing to:
416 (+) Initialize and configure the FSMC NAND interface
417 (+) De-initialize the FSMC NAND interface
418 (+) Configure the FSMC clock and associated GPIOs
419
420@endverbatim
421 * @{
422 */
423
424/**
425 * @brief Initializes the FSMC_NAND device according to the specified
426 * control parameters in the FSMC_NAND_HandleTypeDef
427 * @param Device: Pointer to NAND device instance
428 * @param Init: Pointer to NAND Initialization structure
429 * @retval HAL status
430 */
431HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
432{
433 uint32_t tmpr = 0;
434
435 /* Check the parameters */
436 assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
437 assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
438 assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
439 assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
440 assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
441 assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
442 assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
443
444 if(Init->NandBank == FSMC_NAND_BANK2)
445 {
446 /* Get the NAND bank 2 register value */
447 tmpr = Device->PCR2;
448 }
449 else
450 {
451 /* Get the NAND bank 3 register value */
452 tmpr = Device->PCR3;
453 }
454
455 /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
456 tmpr &= ((uint32_t)~(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | FSMC_PCR2_PTYP | \
457 FSMC_PCR2_PWID | FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \
458 FSMC_PCR2_TAR | FSMC_PCR2_ECCPS));
459
460 /* Set NAND device control parameters */
461 tmpr |= (uint32_t)(Init->Waitfeature |\
462 FSMC_PCR_MEMORY_TYPE_NAND |\
463 Init->MemoryDataWidth |\
464 Init->EccComputation |\
465 Init->ECCPageSize |\
466 ((Init->TCLRSetupTime) << 9) |\
467 ((Init->TARSetupTime) << 13));
468
469 if(Init->NandBank == FSMC_NAND_BANK2)
470 {
471 /* NAND bank 2 registers configuration */
472 Device->PCR2 = tmpr;
473 }
474 else
475 {
476 /* NAND bank 3 registers configuration */
477 Device->PCR3 = tmpr;
478 }
479
480 return HAL_OK;
481}
482
483/**
484 * @brief Initializes the FSMC_NAND Common space Timing according to the specified
485 * parameters in the FSMC_NAND_PCC_TimingTypeDef
486 * @param Device: Pointer to NAND device instance
487 * @param Timing: Pointer to NAND timing structure
488 * @param Bank: NAND bank number
489 * @retval HAL status
490 */
491HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
492{
493 uint32_t tmpr = 0;
494
495 /* Check the parameters */
496 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
497 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
498 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
499 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
500
501 if(Bank == FSMC_NAND_BANK2)
502 {
503 /* Get the NAND bank 2 register value */
504 tmpr = Device->PMEM2;
505 }
506 else
507 {
508 /* Get the NAND bank 3 register value */
509 tmpr = Device->PMEM3;
510 }
511
512 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
513 tmpr &= ((uint32_t)~(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 | FSMC_PMEM2_MEMHOLD2 | \
514 FSMC_PMEM2_MEMHIZ2));
515
516 /* Set FSMC_NAND device timing parameters */
517 tmpr |= (uint32_t)(Timing->SetupTime |\
518 ((Timing->WaitSetupTime) << 8) |\
519 ((Timing->HoldSetupTime) << 16) |\
520 ((Timing->HiZSetupTime) << 24)
521 );
522
523 if(Bank == FSMC_NAND_BANK2)
524 {
525 /* NAND bank 2 registers configuration */
526 Device->PMEM2 = tmpr;
527 }
528 else
529 {
530 /* NAND bank 3 registers configuration */
531 Device->PMEM3 = tmpr;
532 }
533
534 return HAL_OK;
535}
536
537/**
538 * @brief Initializes the FSMC_NAND Attribute space Timing according to the specified
539 * parameters in the FSMC_NAND_PCC_TimingTypeDef
540 * @param Device: Pointer to NAND device instance
541 * @param Timing: Pointer to NAND timing structure
542 * @param Bank: NAND bank number
543 * @retval HAL status
544 */
545HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
546{
547 uint32_t tmpr = 0;
548
549 /* Check the parameters */
550 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
551 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
552 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
553 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
554
555 if(Bank == FSMC_NAND_BANK2)
556 {
557 /* Get the NAND bank 2 register value */
558 tmpr = Device->PATT2;
559 }
560 else
561 {
562 /* Get the NAND bank 3 register value */
563 tmpr = Device->PATT3;
564 }
565
566 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
567 tmpr &= ((uint32_t)~(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 | FSMC_PATT2_ATTHOLD2 | \
568 FSMC_PATT2_ATTHIZ2));
569
570 /* Set FSMC_NAND device timing parameters */
571 tmpr |= (uint32_t)(Timing->SetupTime |\
572 ((Timing->WaitSetupTime) << 8) |\
573 ((Timing->HoldSetupTime) << 16) |\
574 ((Timing->HiZSetupTime) << 24)
575 );
576
577 if(Bank == FSMC_NAND_BANK2)
578 {
579 /* NAND bank 2 registers configuration */
580 Device->PATT2 = tmpr;
581 }
582 else
583 {
584 /* NAND bank 3 registers configuration */
585 Device->PATT3 = tmpr;
586 }
587
588 return HAL_OK;
589}
590
591/**
592 * @brief DeInitializes the FSMC_NAND device
593 * @param Device: Pointer to NAND device instance
594 * @param Bank: NAND bank number
595 * @retval HAL status
596 */
597HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
598{
599 /* Disable the NAND Bank */
600 __FSMC_NAND_DISABLE(Device, Bank);
601
602 /* De-initialize the NAND Bank */
603 if(Bank == FSMC_NAND_BANK2)
604 {
605 /* Set the FSMC_NAND_BANK2 registers to their reset values */
606 Device->PCR2 = 0x00000018;
607 Device->SR2 = 0x00000040;
608 Device->PMEM2 = 0xFCFCFCFC;
609 Device->PATT2 = 0xFCFCFCFC;
610 }
611 /* FSMC_Bank3_NAND */
612 else
613 {
614 /* Set the FSMC_NAND_BANK3 registers to their reset values */
615 Device->PCR3 = 0x00000018;
616 Device->SR3 = 0x00000040;
617 Device->PMEM3 = 0xFCFCFCFC;
618 Device->PATT3 = 0xFCFCFCFC;
619 }
620
621 return HAL_OK;
622}
623/**
624 * @}
625 */
626
627/** @addtogroup FSMC_LL_NAND_Private_Functions_Group2
628 * @brief management functions
629 *
630@verbatim
631 ==============================================================================
632 ##### FSMC_NAND Control functions #####
633 ==============================================================================
634 [..]
635 This subsection provides a set of functions allowing to control dynamically
636 the FSMC NAND interface.
637
638@endverbatim
639 * @{
640 */
641
642/**
643 * @brief Enables dynamically FSMC_NAND ECC feature.
644 * @param Device: Pointer to NAND device instance
645 * @param Bank: NAND bank number
646 * @retval HAL status
647 */
648HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
649{
650 /* Enable ECC feature */
651 if(Bank == FSMC_NAND_BANK2)
652 {
653 Device->PCR2 |= FSMC_PCR2_ECCEN;
654 }
655 else
656 {
657 Device->PCR3 |= FSMC_PCR3_ECCEN;
658 }
659
660 return HAL_OK;
661}
662
663/**
664 * @brief Disables dynamically FSMC_NAND ECC feature.
665 * @param Device: Pointer to NAND device instance
666 * @param Bank: NAND bank number
667 * @retval HAL status
668 */
669HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
670{
671 /* Disable ECC feature */
672 if(Bank == FSMC_NAND_BANK2)
673 {
674 Device->PCR2 &= ~FSMC_PCR2_ECCEN;
675 }
676 else
677 {
678 Device->PCR3 &= ~FSMC_PCR3_ECCEN;
679 }
680
681 return HAL_OK;
682}
683
684/**
685 * @brief Disables dynamically FSMC_NAND ECC feature.
686 * @param Device: Pointer to NAND device instance
687 * @param ECCval: Pointer to ECC value
688 * @param Bank: NAND bank number
689 * @param Timeout: Timeout wait value
690 * @retval HAL status
691 */
692HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
693{
694 uint32_t tickstart = 0;
695
696 /* Check the parameters */
697 assert_param(IS_FSMC_NAND_DEVICE(Device));
698 assert_param(IS_FSMC_NAND_BANK(Bank));
699
700 /* Get tick */
701 tickstart = HAL_GetTick();
702
703 /* Wait until FIFO is empty */
704 while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
705 {
706 /* Check for the Timeout */
707 if(Timeout != HAL_MAX_DELAY)
708 {
709 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
710 {
711 return HAL_TIMEOUT;
712 }
713 }
714 }
715
716 if(Bank == FSMC_NAND_BANK2)
717 {
718 /* Get the ECCR2 register value */
719 *ECCval = (uint32_t)Device->ECCR2;
720 }
721 else
722 {
723 /* Get the ECCR3 register value */
724 *ECCval = (uint32_t)Device->ECCR3;
725 }
726
727 return HAL_OK;
728}
729
730/**
731 * @}
732 */
733
734/**
735 * @}
736 */
737
738/** @addtogroup FSMC_LL_PCCARD
739 * @brief PCCARD Controller functions
740 *
741 @verbatim
742 ==============================================================================
743 ##### How to use PCCARD device driver #####
744 ==============================================================================
745 [..]
746 This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
747 to run the PCCARD/compact flash external devices.
748
749 (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
750 (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
751 (+) FSMC PCCARD bank common space timing configuration using the function
752 FSMC_PCCARD_CommonSpace_Timing_Init()
753 (+) FSMC PCCARD bank attribute space timing configuration using the function
754 FSMC_PCCARD_AttributeSpace_Timing_Init()
755 (+) FSMC PCCARD bank IO space timing configuration using the function
756 FSMC_PCCARD_IOSpace_Timing_Init()
757
758@endverbatim
759 * @{
760 */
761
762/** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1
763 * @brief Initialization and Configuration functions
764 *
765@verbatim
766 ==============================================================================
767 ##### Initialization and de_initialization functions #####
768 ==============================================================================
769 [..]
770 This section provides functions allowing to:
771 (+) Initialize and configure the FSMC PCCARD interface
772 (+) De-initialize the FSMC PCCARD interface
773 (+) Configure the FSMC clock and associated GPIOs
774
775@endverbatim
776 * @{
777 */
778
779/**
780 * @brief Initializes the FSMC_PCCARD device according to the specified
781 * control parameters in the FSMC_PCCARD_HandleTypeDef
782 * @param Device: Pointer to PCCARD device instance
783 * @param Init: Pointer to PCCARD Initialization structure
784 * @retval HAL status
785 */
786HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
787{
788 uint32_t tmpr = 0;
789
790 /* Check the parameters */
791 assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
792 assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
793 assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
794
795 /* Get PCCARD control register value */
796 tmpr = Device->PCR4;
797
798 /* Clear TAR, TCLR, PWAITEN and PWID bits */
799 tmpr &= ((uint32_t)~(FSMC_PCR4_TAR | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \
800 FSMC_PCR4_PWID));
801
802 /* Set FSMC_PCCARD device control parameters */
803 tmpr |= (uint32_t)(Init->Waitfeature |\
804 FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
805 (Init->TCLRSetupTime << 9) |\
806 (Init->TARSetupTime << 13));
807
808 Device->PCR4 = tmpr;
809
810 return HAL_OK;
811}
812
813/**
814 * @brief Initializes the FSMC_PCCARD Common space Timing according to the specified
815 * parameters in the FSMC_NAND_PCC_TimingTypeDef
816 * @param Device: Pointer to PCCARD device instance
817 * @param Timing: Pointer to PCCARD timing structure
818 * @retval HAL status
819 */
820HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
821{
822 uint32_t tmpr = 0;
823
824 /* Check the parameters */
825 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
826 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
827 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
828 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
829
830 /* Get PCCARD common space timing register value */
831 tmpr = Device->PMEM4;
832
833 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
834 tmpr &= ((uint32_t)~(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 | FSMC_PMEM4_MEMHOLD4 | \
835 FSMC_PMEM4_MEMHIZ4));
836 /* Set PCCARD timing parameters */
837 tmpr |= (uint32_t)((Timing->SetupTime |\
838 ((Timing->WaitSetupTime) << 8) |\
839 (Timing->HoldSetupTime) << 16) |\
840 ((Timing->HiZSetupTime) << 24));
841
842 Device->PMEM4 = tmpr;
843
844 return HAL_OK;
845}
846
847/**
848 * @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified
849 * parameters in the FSMC_NAND_PCC_TimingTypeDef
850 * @param Device: Pointer to PCCARD device instance
851 * @param Timing: Pointer to PCCARD timing structure
852 * @retval HAL status
853 */
854HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
855{
856 uint32_t tmpr = 0;
857
858 /* Check the parameters */
859 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
860 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
861 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
862 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
863
864 /* Get PCCARD timing parameters */
865 tmpr = Device->PATT4;
866
867 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
868 tmpr &= ((uint32_t)~(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 | FSMC_PATT4_ATTHOLD4 | \
869 FSMC_PATT4_ATTHIZ4));
870
871 /* Set PCCARD timing parameters */
872 tmpr |= (uint32_t)(Timing->SetupTime |\
873 ((Timing->WaitSetupTime) << 8) |\
874 ((Timing->HoldSetupTime) << 16) |\
875 ((Timing->HiZSetupTime) << 24));
876 Device->PATT4 = tmpr;
877
878 return HAL_OK;
879}
880
881/**
882 * @brief Initializes the FSMC_PCCARD IO space Timing according to the specified
883 * parameters in the FSMC_NAND_PCC_TimingTypeDef
884 * @param Device: Pointer to PCCARD device instance
885 * @param Timing: Pointer to PCCARD timing structure
886 * @retval HAL status
887 */
888HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
889{
890 uint32_t tmpr = 0;
891
892 /* Check the parameters */
893 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
894 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
895 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
896 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
897
898 /* Get FSMC_PCCARD device timing parameters */
899 tmpr = Device->PIO4;
900
901 /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
902 tmpr &= ((uint32_t)~(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | FSMC_PIO4_IOHOLD4 | \
903 FSMC_PIO4_IOHIZ4));
904
905 /* Set FSMC_PCCARD device timing parameters */
906 tmpr |= (uint32_t)(Timing->SetupTime |\
907 ((Timing->WaitSetupTime) << 8) |\
908 ((Timing->HoldSetupTime) << 16) |\
909 ((Timing->HiZSetupTime) << 24));
910
911 Device->PIO4 = tmpr;
912
913 return HAL_OK;
914}
915
916/**
917 * @brief DeInitializes the FSMC_PCCARD device
918 * @param Device: Pointer to PCCARD device instance
919 * @retval HAL status
920 */
921HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
922{
923 /* Disable the FSMC_PCCARD device */
924 __FSMC_PCCARD_DISABLE(Device);
925
926 /* De-initialize the FSMC_PCCARD device */
927 Device->PCR4 = 0x00000018;
928 Device->SR4 = 0x00000000;
929 Device->PMEM4 = 0xFCFCFCFC;
930 Device->PATT4 = 0xFCFCFCFC;
931 Device->PIO4 = 0xFCFCFCFC;
932
933 return HAL_OK;
934}
935/**
936 * @}
937 */
938
939/**
940 * @}
941 */
942#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
943
944/**
945 * @}
946 */
947#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
948#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */
949
950/**
951 * @}
952 */
953
954/**
955 * @}
956 */
957/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Note: See TracBrowser for help on using the repository browser.