[302] | 1 | /*
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| 2 | * TOPPERS/ASP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Advanced Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
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| 7 | * Toyohashi Univ. of Technology, JAPAN
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| 8 | * Copyright (C) 2005-2014 by Embedded and Real-Time Systems Laboratory
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| 9 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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| 10 | *
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| 11 | * ä¸è¨èä½æ¨©è
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| 12 | ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
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| 13 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
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| 14 | * å¤ã»åé
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| 15 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 16 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 17 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 18 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 19 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 20 | * ç¨ã§ããå½¢ã§åé
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| 21 | å¸ããå ´åã«ã¯ï¼åé
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| 22 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 23 | * è
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| 24 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 25 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 26 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 27 | * ç¨ã§ããªãå½¢ã§åé
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| 28 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 29 | * ã¨ï¼
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| 30 | * (a) åé
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| 31 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 32 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 33 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 34 | * (b) åé
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| 35 | å¸ã®å½¢æ
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| 36 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 37 | * å ±åãããã¨ï¼
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| 38 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 39 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 40 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 41 | 責ãããã¨ï¼
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| 42 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
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| 43 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
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| 44 | ããã³TOPPERSããã¸ã§ã¯ãã
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| 45 | * å
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| 46 | 責ãããã¨ï¼
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| 47 | *
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| 48 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 49 | ã
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| 50 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
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| 51 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
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| 52 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
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| 53 | * ã®è²¬ä»»ãè² ããªãï¼
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| 54 | *
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| 55 | * @(#) $Id: core_insn.h 301 2015-01-07 04:57:01Z ertl-ishikawa $
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| 56 | */
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| 57 |
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| 58 |
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| 59 | /*
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| 60 | * ã³ã¢ä¾åã®ç¹æ®å½ä»¤ã®ã¤ã³ã©ã¤ã³é¢æ°å®ç¾©ï¼ARM-Mç¨ï¼
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| 61 | */
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| 62 |
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| 63 | #ifndef CORE_INSN_H
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| 64 | #define CORE_INSN_H
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| 65 |
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| 66 | #include <arm_m.h>
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| 67 |
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| 68 | /*
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| 69 | * ã¡ã¢ãªãå¤æ´ããããã¨ãã³ã³ãã¤ã©ã«ä¼ããããã®ãã¯ã
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| 70 | */
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| 71 | #define ARM_MEMORY_CHANGED Asm("":::"memory")
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| 72 |
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| 73 | /*
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| 74 | * FAULTMASKã®ã»ãã
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| 75 | */
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| 76 | Inline void
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| 77 | set_faultmask(void){
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| 78 | Asm("cpsid f":::"memory");
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| 79 | }
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| 80 |
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| 81 | /*
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| 82 | * FAULTMASKã®ã¯ãªã¢
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| 83 | */
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| 84 | Inline void
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| 85 | clear_faultmask(void){
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| 86 | Asm("cpsie f":::"memory");
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| 87 | }
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| 88 |
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| 89 | /*
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| 90 | * PRIMASKã®ã»ãã
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| 91 | */
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| 92 | Inline void
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| 93 | set_primask(void){
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| 94 | Asm("cpsid i":::"memory");
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| 95 | }
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| 96 |
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| 97 | /*
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| 98 | * PRIMASKã®ã¯ãªã¢
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| 99 | */
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| 100 | Inline void
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| 101 | clear_primask(void){
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| 102 | Asm("cpsie i":::"memory");
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| 103 | }
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| 104 |
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| 105 | /*
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| 106 | * BASEPRIã®ã»ãã
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| 107 | */
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| 108 | Inline void
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| 109 | set_basepri(uint32_t val){
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| 110 | Asm("msr BASEPRI, %0" : : "r"(val) : "memory");
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| 111 | }
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| 112 |
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| 113 | /*
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| 114 | * BASEPRIã®åå¾
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| 115 | */
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| 116 | Inline uint32_t
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| 117 | get_basepri(void){
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| 118 | uint32_t val;
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| 119 | Asm("mrs %0, BASEPRI" : "=r"(val));
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| 120 | return(val);
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| 121 | }
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| 122 |
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| 123 | /*
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| 124 | * CONTROLã®ã»ãã
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| 125 | */
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| 126 | Inline void
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| 127 | set_control(uint32_t val){
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| 128 | /*
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| 129 | * controlã¬ã¸ã¹ã¿ã»ããå¾ã«ã¯isbãå¿
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| 130 | é
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| 131 | * [ARMv7-M Architecture Reference Manaual(DDI0403B) A3-37]
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| 132 | */
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| 133 | Asm("msr control, %0 \n"
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| 134 | " isb"
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| 135 | : : "r"(val) : "memory");
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| 136 | }
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| 137 |
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| 138 | /*
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| 139 | * CONTROLã®åå¾
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| 140 | */
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| 141 | Inline uint32_t
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| 142 | get_control(void){
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| 143 | uint32_t val;
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| 144 | Asm("mrs %0, CONTROL" : "=r"(val));
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| 145 | return(val);
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| 146 | }
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| 147 |
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| 148 | /*
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| 149 | * ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿ï¼CPSRï¼ã®ç¾å¨å¤ã®èªåºã
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| 150 | */
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| 151 | Inline uint32_t
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| 152 | get_ipsr(void)
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| 153 | {
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| 154 | uint32_t sr;
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| 155 | Asm("mrs %0, ipsr" : "=r"(sr));
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| 156 | return(sr);
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| 157 | }
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| 158 |
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| 159 | Inline void
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| 160 | delay_for_interrupt(void)
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| 161 | {
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| 162 | Asm("nop" : : : "memory");
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| 163 | }
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| 164 |
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| 165 | /*
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| 166 | * SCS(NVICç)ãæä½å¾ã«æä½ã®å½±é¿ãåæ ããã¦ãã次ã®å½ä»¤ãå®è¡ããããã®åæ
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| 167 | */
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| 168 | #if defined(TOPPERS_CORTEX_M4) || defined(TOPPERS_CORTEX_M3) || defined(TOPPERS_CORTEX_M0) || defined(TOPPERS_CORTEX_M0PLUS)
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| 169 | #define SCS_SYNC Asm("isb")
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| 170 | #else /* !defined(TOPPERS_CORTEX_M4) || defined(TOPPERS_CORTEX_M3) || defined(TOPPERS_CORTEX_M0) || defined(TOPPERS_CORTEX_M0PLUS) */
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| 171 | #define SCS_SYNC Asm("isb \n dsb \n")
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| 172 | #endif /* defined(TOPPERS_CORTEX_M4) || defined(TOPPERS_CORTEX_M3) || defined(TOPPERS_CORTEX_M0) || defined(TOPPERS_CORTEX_M0PLUS) */
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| 173 |
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| 174 | #endif /* CORE_INSN_H */
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