1 | /*
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2 | * TOPPERS/ASP Kernel
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3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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4 | * Advanced Standard Profile Kernel
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5 | *
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6 | * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
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7 | * Toyohashi Univ. of Technology, JAPAN
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8 | * Copyright (C) 2005-2014 by Embedded and Real-Time Systems Laboratory
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9 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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10 | *
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11 | * ä¸è¨èä½æ¨©è
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12 | ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
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13 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
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14 | * å¤ã»åé
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15 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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16 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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17 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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18 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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19 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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20 | * ç¨ã§ããå½¢ã§åé
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21 | å¸ããå ´åã«ã¯ï¼åé
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22 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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23 | * è
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24 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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25 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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26 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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27 | * ç¨ã§ããªãå½¢ã§åé
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28 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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29 | * ã¨ï¼
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30 | * (a) åé
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31 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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32 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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33 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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34 | * (b) åé
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35 | å¸ã®å½¢æ
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36 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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37 | * å ±åãããã¨ï¼
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38 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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39 | * 害ãããï¼ä¸è¨èä½æ¨©è
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40 | ããã³TOPPERSããã¸ã§ã¯ããå
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41 | 責ãããã¨ï¼
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42 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
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43 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
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44 | ããã³TOPPERSããã¸ã§ã¯ãã
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45 | * å
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46 | 責ãããã¨ï¼
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47 | *
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48 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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49 | ã
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50 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
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51 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
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52 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
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53 | * ã®è²¬ä»»ãè² ããªãï¼
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54 | *
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55 | * @(#) $Id: arm_m.h 301 2015-01-07 04:57:01Z ertl-ishikawa $
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56 | */
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57 |
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58 | /*
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59 | * ARMVx-Mã®ãã¼ãã¦ã§ã¢è³æºã®å®ç¾©
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60 | */
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61 |
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62 | #ifndef ARM_M_H
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63 | #define ARM_M_H
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64 |
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65 | /*
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66 | * EPSRã®Tããã
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67 | */
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68 | #define EPSR_T 0x01000000
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69 |
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70 | /*
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71 | * IPSRã® ISR NUMBER
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72 | */
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73 | #define IPSR_ISR_NUMBER 0x1ff
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74 |
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75 | /*
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76 | * ä¾å¤ã»å²è¾¼ã¿çºçæã«LRã«è¨å®ãããEXC_RETURNã®å¤
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77 | */
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78 | #define EXC_RETURN_HANDLER 0x0
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79 | #define EXC_RETURN_THREAD 0x8
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80 | #define EXC_RETURN_MSP 0x0
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81 | #define EXC_RETURN_PSP 0x4
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82 |
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83 | /*
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84 | * CONTROLã¬ã¸ã¹ã¿
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85 | */
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86 | #define CONTROL_PSP 0x02
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87 | #define CONTROL_MSP 0x00
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88 |
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89 | /*
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90 | * ä¾å¤çªå·
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91 | */
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92 | #define EXCNO_NMI 2
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93 | #define EXCNO_HARD 3
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94 | #define EXCNO_MPU 4
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95 | #define EXCNO_BUS 5
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96 | #define EXCNO_USAGE 6
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97 | #define EXCNO_SVCALL 11
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98 | #define EXCNO_DEBUG 12
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99 | #define EXCNO_PENDSV 14
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100 |
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101 | /*
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102 | * ä¾å¤çªå·ã®æå°å¤ã¨æ大å¤
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103 | */
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104 | #define TMIN_EXCNO 2
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105 | #define TMAX_EXCNO 14
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106 |
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107 | /*
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108 | * å²è¾¼ã¿çªå·
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109 | */
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110 | #define IRQNO_SYSTICK 15
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111 |
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112 | /*
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113 | * å²è¾¼ã¿çªå·ã®æå°å¤
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114 | */
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115 | #define TMIN_INTNO 15
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116 |
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117 | /*
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118 | * ä¾å¤ãã¬ã¼ã ã®ãªãã»ãã
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119 | */
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120 | #define P_EXCINF_OFFSET_EXC_RETURN 0x00
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121 | #define P_EXCINF_OFFSET_BASEPRI 0x01
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122 | #define P_EXCINF_OFFSET_XPSR 0x09
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123 | #define P_EXCINF_OFFSET_PC 0x08
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124 |
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125 | /*
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126 | * NVICé¢é£
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127 | */
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128 |
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129 | /*
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130 | * ã³ã³ããã¼ã«ã¬ã¸ã¹ã¿
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131 | */
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132 | #define NVIC_INT_CTRL 0xe000ed04
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133 |
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134 | #define NVIC_PENDSVSET 0x10000000
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135 |
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136 | /*
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137 | * ã·ã¹ãã ãã³ãã©ã¼ã³ã³ããã¼ã«ã¬ã¸ã¹ã¿
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138 | */
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139 | #define NVIC_SYS_HND_CTRL 0xE000ED24
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140 |
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141 | /*
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142 | * åä¾å¤ã®è¨±å¯ããã
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143 | */
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144 | #define NVIC_SYS_HND_CTRL_USAGE 0x00040000
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145 | #define NVIC_SYS_HND_CTRL_BUS 0x00020000
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146 | #define NVIC_SYS_HND_CTRL_MEM 0x00010000
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147 |
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148 | /*
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149 | * åªå
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150 | 度è¨å®ã¬ã¸ã¹ã¿
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151 | */
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152 | #define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority
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153 | #define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority
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154 | #define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority
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155 | #define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register
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156 |
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157 | /*
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158 | * å²è¾¼ã¿è¨±å¯ã¬ã¸ã¹ã¿
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159 | */
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160 | #define NVIC_SETENA0 0xE000E100 // IRQ 0 to 31 Set Enable Register
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161 |
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162 | /*
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163 | * å²è¾¼ã¿ç¦æ¢ã¬ã¸ã¹ã¿
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164 | */
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165 | #define NVIC_CLRENA0 0xE000E180 // IRQ 0 to 31 Set Disable Register
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166 |
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167 | /*
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168 | * å²è¾¼ã¿ã»ãããã³ãã£ã³ã°ã¬ã¸ã¹ã¿
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169 | */
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170 | #define NVIC_ISER0 0xE000E200 // IRQ 0 to 31 Set-Pending Register
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171 |
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172 | /*
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173 | * å²è¾¼ã¿ã¯ãªã¢ãã³ãã£ã³ã°ã¬ã¸ã¹ã¿
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174 | */
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175 | #define NVIC_ICER0 0xE000E280 // IRQ 0 to 31 Clear-Pending Register
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176 |
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177 | /*
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178 | * ãã¯ã¿ãã¼ãã«ãªãã»ããã¬ã¸ã¹ã¿
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179 | */
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180 | #define NVIC_VECTTBL 0xE000ED08
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181 |
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182 |
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183 | /*
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184 | * SYSTICé¢é£ã¬ã¸ã¹ã¿
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185 | */
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186 | #define SYSTIC_CONTROL_STATUS 0xE000E010
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187 | #define SYSTIC_RELOAD_VALUE 0xE000E014
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188 | #define SYSTIC_CURRENT_VALUE 0xE000E018
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189 | #define SYSTIC_CALIBRATION 0xE000E01C
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190 |
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191 | #define SYSTIC_ENABLE 0x01
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192 | #define SYSTIC_TICINT 0x02
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193 | #define SYSTIC_CLKSOURCE 0x04
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194 | #define SYSTIC_COUNTFLAG 0x10000
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195 |
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196 | #define SYSTIC_SKEW 0x40000000
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197 | #define SYSTIC_NOREF 0x80000000
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198 | #define SYSTIC_TENMS 0x00ffffff
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199 |
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200 | /*
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201 | * Configuration Control Register
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202 | */
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203 | #define CCR_BASE 0xE000ED14
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204 | #define CCR_STKALIGN 0x00000200
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205 | #define CPACR_BASE 0xE000ED88U /*!< System Control Space Base Address */
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206 |
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207 | #endif /* ARM_M_H */
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