source: asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/sdfs.c@ 374

Last change on this file since 374 was 374, checked in by coas-nagasima, 5 years ago

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
ファイルディスクリプタの処理を更新
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1/* mbed Microcontroller Library
2 * Copyright (c) 2006-2012 ARM Limited
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23/* Introduction
24 * ------------
25 * SD and MMC cards support a number of interfaces, but common to them all
26 * is one based on SPI. This is the one I'm implmenting because it means
27 * it is much more portable even though not so performant, and we already
28 * have the mbed SPI Interface!
29 *
30 * The main reference I'm using is Chapter 7, "SPI Mode" of:
31 * http://www.sdcard.org/developers/tech/sdcard/pls/Simplified_Physical_Layer_Spec.pdf
32 *
33 * SPI Startup
34 * -----------
35 * The SD card powers up in SD mode. The SPI interface mode is selected by
36 * asserting CS low and sending the reset command (CMD0). The card will
37 * respond with a (R1) response.
38 *
39 * CMD8 is optionally sent to determine the voltage range supported, and
40 * indirectly determine whether it is a version 1.x SD/non-SD card or
41 * version 2.x. I'll just ignore this for now.
42 *
43 * ACMD41 is repeatedly issued to initialise the card, until "in idle"
44 * (bit 0) of the R1 response goes to '0', indicating it is initialised.
45 *
46 * You should also indicate whether the host supports High Capicity cards,
47 * and check whether the card is high capacity - i'll also ignore this
48 *
49 * SPI Protocol
50 * ------------
51 * The SD SPI protocol is based on transactions made up of 8-bit words, with
52 * the host starting every bus transaction by asserting the CS signal low. The
53 * card always responds to commands, data blocks and errors.
54 *
55 * The protocol supports a CRC, but by default it is off (except for the
56 * first reset CMD0, where the CRC can just be pre-calculated, and CMD8)
57 * I'll leave the CRC off I think!
58 *
59 * Standard capacity cards have variable data block sizes, whereas High
60 * Capacity cards fix the size of data block to 512 bytes. I'll therefore
61 * just always use the Standard Capacity cards with a block size of 512 bytes.
62 * This is set with CMD16.
63 *
64 * You can read and write single blocks (CMD17, CMD25) or multiple blocks
65 * (CMD18, CMD25). For simplicity, I'll just use single block accesses. When
66 * the card gets a read command, it responds with a response token, and then
67 * a data token or an error.
68 *
69 * SPI Command Format
70 * ------------------
71 * Commands are 6-bytes long, containing the command, 32-bit argument, and CRC.
72 *
73 * +---------------+------------+------------+-----------+----------+--------------+
74 * | 01 | cmd[5:0] | arg[31:24] | arg[23:16] | arg[15:8] | arg[7:0] | crc[6:0] | 1 |
75 * +---------------+------------+------------+-----------+----------+--------------+
76 *
77 * As I'm not using CRC, I can fix that byte to what is needed for CMD0 (0x95)
78 *
79 * All Application Specific commands shall be preceded with APP_CMD (CMD55).
80 *
81 * SPI Response Format
82 * -------------------
83 * The main response format (R1) is a status byte (normally zero). Key flags:
84 * idle - 1 if the card is in an idle state/initialising
85 * cmd - 1 if an illegal command code was detected
86 *
87 * +-------------------------------------------------+
88 * R1 | 0 | arg | addr | seq | crc | cmd | erase | idle |
89 * +-------------------------------------------------+
90 *
91 * R1b is the same, except it is followed by a busy signal (zeros) until
92 * the first non-zero byte when it is ready again.
93 *
94 * Data Response Token
95 * -------------------
96 * Every data block written to the card is acknowledged by a byte
97 * response token
98 *
99 * +----------------------+
100 * | xxx | 0 | status | 1 |
101 * +----------------------+
102 * 010 - OK!
103 * 101 - CRC Error
104 * 110 - Write Error
105 *
106 * Single Block Read and Write
107 * ---------------------------
108 *
109 * Block transfers have a byte header, followed by the data, followed
110 * by a 16-bit CRC. In our case, the data will always be 512 bytes.
111 *
112 * +------+---------+---------+- - - -+---------+-----------+----------+
113 * | 0xFE | data[0] | data[1] | | data[n] | crc[15:8] | crc[7:0] |
114 * +------+---------+---------+- - - -+---------+-----------+----------+
115 */
116#include "sdfs.h"
117#include "diskio.h"
118//#include "mbed_debug.h"
119#include "mbed_wait_api.h"
120#include <stdio.h>
121
122#define debug(...) printf(__VA_ARGS__)
123#define debug_if(cond, ...) if(cond){ printf(__VA_ARGS__); }
124
125static int sdfs_initialise_card_v1(sdfs_t *obj);
126static int sdfs_initialise_card_v2(sdfs_t *obj);
127static int sdfs__cmd(sdfs_t *obj, int cmd, int arg);
128static int sdfs__cmd8(sdfs_t *obj);
129static int sdfs__cmd58(sdfs_t *obj);
130static uint64_t sdfs__sd_sectors(sdfs_t *obj);
131static int sdfs__write(sdfs_t *obj, const uint8_t*buffer, uint32_t length);
132static int sdfs__read(sdfs_t *obj, uint8_t *buffer, uint32_t length);
133
134#define SD_COMMAND_TIMEOUT 5000
135
136#define SD_DBG 0
137
138void sdfs_init(sdfs_t *obj, PinName mosi, PinName miso, PinName sclk, PinName cs, const char* name)
139{
140 obj->name = name;
141 spi_init(&obj->_spi, mosi, miso, sclk, NC);
142 gpio_init_out(&obj->_cs, cs);
143 gpio_write(&obj->_cs, 1);
144
145 // Set default to 100kHz for initialisation and 1MHz for data transfer
146 obj->_init_sck = 100000;
147 obj->_transfer_sck = 1000000;
148 obj->_is_initialized = STA_NOINIT;
149}
150
151#define R1_IDLE_STATE (1 << 0)
152#define R1_ERASE_RESET (1 << 1)
153#define R1_ILLEGAL_COMMAND (1 << 2)
154#define R1_COM_CRC_ERROR (1 << 3)
155#define R1_ERASE_SEQUENCE_ERROR (1 << 4)
156#define R1_ADDRESS_ERROR (1 << 5)
157#define R1_PARAMETER_ERROR (1 << 6)
158
159int sdfs_initialise_card(sdfs_t *obj)
160{
161 spi_format(&obj->_spi, 8, 0, 0);
162 // Set to 100kHz for initialisation, and clock card with cs = 1
163 spi_frequency(&obj->_spi, obj->_init_sck);
164 gpio_write(&obj->_cs, 1);
165 for (int i = 0; i < 16; i++) {
166 spi_master_write(&obj->_spi, 0xFF);
167 }
168
169 // send CMD0, should return with all zeros except IDLE STATE set (bit 0)
170 if (sdfs__cmd(obj, 0, 0) != R1_IDLE_STATE) {
171 debug("No disk, or could not put SD card in to SPI idle state\n");
172 return CT_FAIL;
173 }
174
175 // send CMD8 to determine whther it is ver 2.x
176 int r = sdfs__cmd8(obj);
177 if (r == R1_IDLE_STATE) {
178 return sdfs_initialise_card_v2(obj);
179 }
180 else if (r == (R1_IDLE_STATE | R1_ILLEGAL_COMMAND)) {
181 return sdfs_initialise_card_v1(obj);
182 }
183 else {
184 debug("Not in idle state after sending CMD8 (not an SD card?)\n");
185 return CT_FAIL;
186 }
187}
188
189static int sdfs_initialise_card_v1(sdfs_t *obj)
190{
191 sdfs__cmd(obj, 55, 0);
192 if (sdfs__cmd(obj, 41, 0) <= 1) {
193 obj->cdv = 512;
194 debug_if(SD_DBG, "\n\rInit: SEDCARD_V1\n\r");
195 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
196 sdfs__cmd(obj, 55, 0);
197 if (sdfs__cmd(obj, 41, 0) == 0) {
198 break;
199 }
200 }
201 return CT_SD1;
202 }
203 else {
204 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
205 if (sdfs__cmd(obj, 1, 0) == 0)
206 break;
207 }
208 return CT_MMC;
209 }
210 //if (!Timer1 || sdfs__cmd(obj, 16, 512) != 0) /* Set block length: 512 */
211 // ty = 0;
212
213 debug("Timeout waiting for v1.x card\n");
214 return CT_FAIL;
215}
216
217static int sdfs_initialise_card_v2(sdfs_t *obj)
218{
219 int n;
220 uint8_t ocr[4];
221
222 /* Get 32 bit return value of R7 resp */
223 for (n = 0; n < 4; n++) ocr[n] = spi_master_write(&obj->_spi, 0xFF);
224 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
225 sdfs__cmd(obj, 55, 0);
226 if (sdfs__cmd(obj, 41, 0x40000000) == 0) {
227 if (sdfs__cmd58(obj) == 0) {
228 for (n = 0; n < 4; n++) ocr[n] = spi_master_write(&obj->_spi, 0xFF);
229 debug_if(SD_DBG, "\n\rInit: SDCARD_V2\n\r");
230 obj->cdv = 1;
231 return (ocr[0] & 0x40) ? CT_SD2 | CT_BLOCK : CT_SD2;
232 }
233 }
234 wait_ms(50);
235 }
236
237 debug("Timeout waiting for v2.x card\n");
238 return CT_FAIL;
239}
240
241int sdfs_initialize(sdfs_t *obj)
242{
243 obj->_is_initialized |= STA_NOINIT;
244
245 obj->_card_type = sdfs_initialise_card(obj);
246 if (obj->_card_type == 0) {
247 debug("Fail to initialize card\n");
248 return 1;
249 }
250 debug_if(SD_DBG, "init card = %x\n", obj->_is_initialized);
251
252 obj->_sectors = sdfs__sd_sectors(obj);
253
254 if (sdfs__cmdx(obj, 10, 0) != 0 /* READ_CID */
255 || sdfs__read(obj, obj->_cid, 16) != 0) {
256 obj->_card_type = CT_FAIL;
257 debug("Fail to read cid\n");
258 return 1;
259 }
260
261 // Set block length to 512 (CMD16)
262 if (sdfs__cmd(obj, 16, 512) != 0) {
263 obj->_card_type = CT_FAIL;
264 debug("Set 512-byte block timed out\n");
265 return 1;
266 }
267
268 obj->_is_initialized &= ~STA_NOINIT;
269
270 // Set SCK for data transfer
271 spi_frequency(&obj->_spi, obj->_transfer_sck);
272 return 0;
273}
274
275int sdfs_write(sdfs_t *obj, const uint8_t *buffer, uint32_t block_number, uint32_t count)
276{
277 if (obj->_is_initialized & (STA_NOINIT | STA_PROTECT)) {
278 return -1;
279 }
280
281 for (uint32_t b = block_number; b < block_number + count; b++) {
282 // set write address for single block (CMD24)
283 if (sdfs__cmd(obj, 24, b * obj->cdv) != 0) {
284 return 1;
285 }
286
287 // send the data block
288 sdfs__write(obj, buffer, 512);
289 buffer += 512;
290 }
291
292 return 0;
293}
294
295int sdfs_read(sdfs_t *obj, uint8_t *buffer, uint32_t block_number, uint32_t count)
296{
297 if (obj->_is_initialized & STA_NOINIT) {
298 return -1;
299 }
300
301 for (uint32_t b = block_number; b < block_number + count; b++) {
302 // set read address for single block (CMD17)
303 if (sdfs__cmd(obj, 17, b * obj->cdv) != 0) {
304 return 1;
305 }
306
307 // receive the data
308 sdfs__read(obj, buffer, 512);
309 buffer += 512;
310 }
311
312 return 0;
313}
314
315int sdfs_status(sdfs_t *obj)
316{
317 // FATFileSystem::disk_status() returns 0 when initialized
318 if ((obj->_is_initialized & STA_NOINIT) == 0) {
319 return 0;
320 }
321 else {
322 return 1;
323 }
324}
325
326uint64_t sdfs_sectors(sdfs_t *obj) { return obj->_sectors; }
327
328
329// PRIVATE FUNCTIONS
330static int sdfs__cmd(sdfs_t *obj, int cmd, int arg)
331{
332 gpio_write(&obj->_cs, 0);
333
334 // send a command
335 spi_master_write(&obj->_spi, 0x40 | cmd);
336 spi_master_write(&obj->_spi, arg >> 24);
337 spi_master_write(&obj->_spi, arg >> 16);
338 spi_master_write(&obj->_spi, arg >> 8);
339 spi_master_write(&obj->_spi, arg >> 0);
340 spi_master_write(&obj->_spi, 0x95);
341
342 // wait for the repsonse (response[7] == 0)
343 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
344 int response = spi_master_write(&obj->_spi, 0xFF);
345 if (!(response & 0x80)) {
346 gpio_write(&obj->_cs, 1);
347 spi_master_write(&obj->_spi, 0xFF);
348 return response;
349 }
350 }
351 gpio_write(&obj->_cs, 1);
352 spi_master_write(&obj->_spi, 0xFF);
353 return -1; // timeout
354}
355
356int sdfs__cmdx(sdfs_t *obj, int cmd, int arg)
357{
358 gpio_write(&obj->_cs, 0);
359
360 // send a command
361 spi_master_write(&obj->_spi, 0x40 | cmd);
362 spi_master_write(&obj->_spi, arg >> 24);
363 spi_master_write(&obj->_spi, arg >> 16);
364 spi_master_write(&obj->_spi, arg >> 8);
365 spi_master_write(&obj->_spi, arg >> 0);
366 spi_master_write(&obj->_spi, 0x95);
367
368 // wait for the repsonse (response[7] == 0)
369 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
370 int response = spi_master_write(&obj->_spi, 0xFF);
371 if (!(response & 0x80)) {
372 return response;
373 }
374 }
375 gpio_write(&obj->_cs, 1);
376 spi_master_write(&obj->_spi, 0xFF);
377 return -1; // timeout
378}
379
380static int sdfs__cmd58(sdfs_t *obj)
381{
382 gpio_write(&obj->_cs, 0);
383 int arg = 0;
384
385 // send a command
386 spi_master_write(&obj->_spi, 0x40 | 58);
387 spi_master_write(&obj->_spi, arg >> 24);
388 spi_master_write(&obj->_spi, arg >> 16);
389 spi_master_write(&obj->_spi, arg >> 8);
390 spi_master_write(&obj->_spi, arg >> 0);
391 spi_master_write(&obj->_spi, 0x95);
392
393 // wait for the repsonse (response[7] == 0)
394 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
395 int response = spi_master_write(&obj->_spi, 0xFF);
396 if (!(response & 0x80)) {
397 int ocr = spi_master_write(&obj->_spi, 0xFF) << 24;
398 ocr |= spi_master_write(&obj->_spi, 0xFF) << 16;
399 ocr |= spi_master_write(&obj->_spi, 0xFF) << 8;
400 ocr |= spi_master_write(&obj->_spi, 0xFF) << 0;
401 gpio_write(&obj->_cs, 1);
402 spi_master_write(&obj->_spi, 0xFF);
403 return response;
404 }
405 }
406 gpio_write(&obj->_cs, 1);
407 spi_master_write(&obj->_spi, 0xFF);
408 return -1; // timeout
409}
410
411static int sdfs__cmd8(sdfs_t *obj)
412{
413 gpio_write(&obj->_cs, 0);
414
415 // send a command
416 spi_master_write(&obj->_spi, 0x40 | 8); // CMD8
417 spi_master_write(&obj->_spi, 0x00); // reserved
418 spi_master_write(&obj->_spi, 0x00); // reserved
419 spi_master_write(&obj->_spi, 0x01); // 3.3v
420 spi_master_write(&obj->_spi, 0xAA); // check pattern
421 spi_master_write(&obj->_spi, 0x87); // crc
422
423 // wait for the repsonse (response[7] == 0)
424 for (int i = 0; i < SD_COMMAND_TIMEOUT * 1000; i++) {
425 char response[5];
426 response[0] = spi_master_write(&obj->_spi, 0xFF);
427 if (!(response[0] & 0x80)) {
428 for (int j = 1; j < 5; j++) {
429 response[i] = spi_master_write(&obj->_spi, 0xFF);
430 }
431 gpio_write(&obj->_cs, 1);
432 spi_master_write(&obj->_spi, 0xFF);
433 return response[0];
434 }
435 }
436 gpio_write(&obj->_cs, 1);
437 spi_master_write(&obj->_spi, 0xFF);
438 return -1; // timeout
439}
440
441static int sdfs__read(sdfs_t *obj, uint8_t *buffer, uint32_t length)
442{
443 gpio_write(&obj->_cs, 0);
444
445 // read until start byte (0xFF)
446 while (spi_master_write(&obj->_spi, 0xFF) != 0xFE);
447
448 // read data
449 for (int i = 0; i < length; i++) {
450 buffer[i] = spi_master_write(&obj->_spi, 0xFF);
451 }
452 spi_master_write(&obj->_spi, 0xFF); // checksum
453 spi_master_write(&obj->_spi, 0xFF);
454
455 gpio_write(&obj->_cs, 1);
456 spi_master_write(&obj->_spi, 0xFF);
457 return 0;
458}
459
460static int sdfs__write(sdfs_t *obj, const uint8_t*buffer, uint32_t length)
461{
462 gpio_write(&obj->_cs, 0);
463
464 // indicate start of block
465 spi_master_write(&obj->_spi, 0xFE);
466
467 // write the data
468 for (int i = 0; i < length; i++) {
469 spi_master_write(&obj->_spi, buffer[i]);
470 }
471
472 // write the checksum
473 spi_master_write(&obj->_spi, 0xFF);
474 spi_master_write(&obj->_spi, 0xFF);
475
476 // check the response token
477 if ((spi_master_write(&obj->_spi, 0xFF) & 0x1F) != 0x05) {
478 gpio_write(&obj->_cs, 1);
479 spi_master_write(&obj->_spi, 0xFF);
480 return 1;
481 }
482
483 // wait for write to finish
484 while (spi_master_write(&obj->_spi, 0xFF) == 0);
485
486 gpio_write(&obj->_cs, 1);
487 spi_master_write(&obj->_spi, 0xFF);
488 return 0;
489}
490
491static uint32_t sdfs_ext_bits(sdfs_t *obj, unsigned char *data, int msb, int lsb)
492{
493 uint32_t bits = 0;
494 uint32_t size = 1 + msb - lsb;
495 for (uint32_t i = 0; i < size; i++) {
496 uint32_t position = lsb + i;
497 uint32_t byte = 15 - (position >> 3);
498 uint32_t bit = position & 0x7;
499 uint32_t value = (data[byte] >> bit) & 1;
500 bits |= value << i;
501 }
502 return bits;
503}
504
505static uint64_t sdfs__sd_sectors(sdfs_t *obj)
506{
507 uint32_t c_size, c_size_mult, read_bl_len;
508 uint32_t mult, blocknr;
509 uint32_t hc_c_size;
510 uint64_t blocks;
511
512 // CMD9, Response R2 (R1 byte + 16-byte block read)
513 if (sdfs__cmdx(obj, 9, 0) != 0) {
514 debug("Didn't get a response from the disk\n");
515 return 0;
516 }
517
518 if (sdfs__read(obj, obj->_csd, 16) != 0) {
519 debug("Couldn't read csd response from disk\n");
520 return 0;
521 }
522
523 // csd_structure : csd[127:126]
524 // c_size : csd[73:62]
525 // c_size_mult : csd[49:47]
526 // read_bl_len : csd[83:80] - the *maximum* read block length
527
528 int csd_structure = sdfs_ext_bits(obj, obj->_csd, 127, 126);
529
530 switch (csd_structure) {
531 case 0:
532 obj->cdv = 512;
533 c_size = sdfs_ext_bits(obj, obj->_csd, 73, 62);
534 c_size_mult = sdfs_ext_bits(obj, obj->_csd, 49, 47);
535 read_bl_len = sdfs_ext_bits(obj, obj->_csd, 83, 80);
536
537 obj->_block_len = 1 << read_bl_len;
538 mult = 1 << (c_size_mult + 2);
539 blocknr = (c_size + 1) * mult;
540 obj->_capacity = blocknr * obj->_block_len;
541 blocks = obj->_capacity / 512;
542 debug_if(SD_DBG, "\n\rSDCard\n\rc_size: %d \n\rcapacity: %ld \n\rsectors: %lld\n\r", c_size, obj->_capacity, blocks);
543 break;
544
545 case 1:
546 obj->cdv = 1;
547 hc_c_size = sdfs_ext_bits(obj, obj->_csd, 63, 48);
548 blocks = (hc_c_size + 1) * 1024;
549 debug_if(SD_DBG, "\n\rSDHC Card \n\rhc_c_size: %d\n\rcapacity: %lld \n\rsectors: %lld\n\r", hc_c_size, blocks * 512, blocks);
550 break;
551
552 default:
553 debug("CSD struct unsupported\r\n");
554 return 0;
555 };
556 return blocks;
557}
558
559static
560int wait_ready(sdfs_t *obj, uint32_t wt)
561{
562 /* Wait until card goes ready or timeout */
563 for (int i = 0; i < wt; i++) {
564 if (spi_master_write(&obj->_spi, 0xFF) == 0xFF)
565 /* Card goes ready */
566 return 1;
567 }
568
569 /* Timeout occured */
570 return 0;
571}
572
573static
574void deselect(sdfs_t *obj)
575{
576 /* Set CS# high */
577 gpio_write(&obj->_cs, 0);
578
579 /* Dummy clock (force DO hi-z for multiple slave SPI) */
580 spi_master_write(&obj->_spi, 0xFF);
581}
582
583static
584int select(sdfs_t *obj)
585{
586 /* Set CS# low */
587 gpio_write(&obj->_cs, 1);
588
589 /* Dummy clock (force DO enabled) */
590 spi_master_write(&obj->_spi, 0xFF);
591
592 /* Wait for card ready */
593 if (wait_ready(obj, 500))
594 return 0;
595
596 deselect(obj);
597
598 /* Failed to select the card due to timeout */
599 return -1;
600}
601
602int sdfs_sync(sdfs_t *obj)
603{
604 int ret = select(obj);
605 deselect(obj);
606 return ret;
607}
608
609int sdfs_trim(sdfs_t *obj, uint32_t st, uint32_t ed)
610{
611 int res = -1;
612
613 for(;;) {
614 /* Check if the card is SDC */
615 if (!(obj->_card_type & CT_SDC))
616 break;
617 /* Check if sector erase can be applied to the card */
618 if (!(obj->_csd[0] >> 6) && !(obj->_csd[10] & 0x40))
619 break;
620 /* Load sector block */
621 if (!(obj->_card_type & CT_BLOCK)) {
622 st *= 512; ed *= 512;
623 }
624 /* Erase sector block */
625 if ((sdfs__cmd(obj, 32, st) == 0)
626 && (sdfs__cmd(obj, 33, ed) == 0)
627 && (sdfs__cmd(obj, 38, 0) == 0)
628 && wait_ready(obj, 30000))
629 res = 0;
630 }
631
632 return res;
633}
634
635int sdfs_get_ocr(sdfs_t *obj, uint8_t buff[4])
636{
637 int res = -1, n;
638
639 /* READ_OCR */
640 if (sdfs__cmd58(obj) == 0) {
641 for (n = 4; n; n--) {
642 *buff++ = spi_master_write(&obj->_spi, 0xFF);
643 }
644 res = 0;
645 }
646
647 deselect(obj);
648
649 return res;
650}
651
652int sdfs_get_sdstat(sdfs_t *obj, uint8_t buff[64])
653{
654 int res = -1;
655
656 sdfs__cmd(obj, 55, 0);
657
658 /* SD_STATUS */
659 if (sdfs__cmd(obj, 13, 0) == 0) {
660 spi_master_write(&obj->_spi, 0xFF);
661 if (sdfs__read(obj, buff, 64) == 0)
662 return 0;
663 }
664
665 deselect(obj);
666
667 return res;
668}
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