source: asp3_tinet_ecnl_arm/trunk/ntshell/fatfs/sdfs.c@ 359

Last change on this file since 359 was 359, checked in by coas-nagasima, 6 years ago

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1/* mbed Microcontroller Library
2 * Copyright (c) 2006-2012 ARM Limited
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23/* Introduction
24 * ------------
25 * SD and MMC cards support a number of interfaces, but common to them all
26 * is one based on SPI. This is the one I'm implmenting because it means
27 * it is much more portable even though not so performant, and we already
28 * have the mbed SPI Interface!
29 *
30 * The main reference I'm using is Chapter 7, "SPI Mode" of:
31 * http://www.sdcard.org/developers/tech/sdcard/pls/Simplified_Physical_Layer_Spec.pdf
32 *
33 * SPI Startup
34 * -----------
35 * The SD card powers up in SD mode. The SPI interface mode is selected by
36 * asserting CS low and sending the reset command (CMD0). The card will
37 * respond with a (R1) response.
38 *
39 * CMD8 is optionally sent to determine the voltage range supported, and
40 * indirectly determine whether it is a version 1.x SD/non-SD card or
41 * version 2.x. I'll just ignore this for now.
42 *
43 * ACMD41 is repeatedly issued to initialise the card, until "in idle"
44 * (bit 0) of the R1 response goes to '0', indicating it is initialised.
45 *
46 * You should also indicate whether the host supports High Capicity cards,
47 * and check whether the card is high capacity - i'll also ignore this
48 *
49 * SPI Protocol
50 * ------------
51 * The SD SPI protocol is based on transactions made up of 8-bit words, with
52 * the host starting every bus transaction by asserting the CS signal low. The
53 * card always responds to commands, data blocks and errors.
54 *
55 * The protocol supports a CRC, but by default it is off (except for the
56 * first reset CMD0, where the CRC can just be pre-calculated, and CMD8)
57 * I'll leave the CRC off I think!
58 *
59 * Standard capacity cards have variable data block sizes, whereas High
60 * Capacity cards fix the size of data block to 512 bytes. I'll therefore
61 * just always use the Standard Capacity cards with a block size of 512 bytes.
62 * This is set with CMD16.
63 *
64 * You can read and write single blocks (CMD17, CMD25) or multiple blocks
65 * (CMD18, CMD25). For simplicity, I'll just use single block accesses. When
66 * the card gets a read command, it responds with a response token, and then
67 * a data token or an error.
68 *
69 * SPI Command Format
70 * ------------------
71 * Commands are 6-bytes long, containing the command, 32-bit argument, and CRC.
72 *
73 * +---------------+------------+------------+-----------+----------+--------------+
74 * | 01 | cmd[5:0] | arg[31:24] | arg[23:16] | arg[15:8] | arg[7:0] | crc[6:0] | 1 |
75 * +---------------+------------+------------+-----------+----------+--------------+
76 *
77 * As I'm not using CRC, I can fix that byte to what is needed for CMD0 (0x95)
78 *
79 * All Application Specific commands shall be preceded with APP_CMD (CMD55).
80 *
81 * SPI Response Format
82 * -------------------
83 * The main response format (R1) is a status byte (normally zero). Key flags:
84 * idle - 1 if the card is in an idle state/initialising
85 * cmd - 1 if an illegal command code was detected
86 *
87 * +-------------------------------------------------+
88 * R1 | 0 | arg | addr | seq | crc | cmd | erase | idle |
89 * +-------------------------------------------------+
90 *
91 * R1b is the same, except it is followed by a busy signal (zeros) until
92 * the first non-zero byte when it is ready again.
93 *
94 * Data Response Token
95 * -------------------
96 * Every data block written to the card is acknowledged by a byte
97 * response token
98 *
99 * +----------------------+
100 * | xxx | 0 | status | 1 |
101 * +----------------------+
102 * 010 - OK!
103 * 101 - CRC Error
104 * 110 - Write Error
105 *
106 * Single Block Read and Write
107 * ---------------------------
108 *
109 * Block transfers have a byte header, followed by the data, followed
110 * by a 16-bit CRC. In our case, the data will always be 512 bytes.
111 *
112 * +------+---------+---------+- - - -+---------+-----------+----------+
113 * | 0xFE | data[0] | data[1] | | data[n] | crc[15:8] | crc[7:0] |
114 * +------+---------+---------+- - - -+---------+-----------+----------+
115 */
116#include "sdfs.h"
117#include "diskio.h"
118//#include "mbed_debug.h"
119#include "mbed_wait_api.h"
120#include "util/ntstdio.h"
121
122extern ntstdio_t ntstdio;
123#define debug(...) ntstdio_printf(&ntstdio, __VA_ARGS__)
124#define debug_if(cond, ...) if(cond){ ntstdio_printf(&ntstdio, __VA_ARGS__); }
125
126static int sdfs_initialise_card_v1(sdfs_t *obj);
127static int sdfs_initialise_card_v2(sdfs_t *obj);
128static int sdfs__cmd(sdfs_t *obj, int cmd, int arg);
129static int sdfs__cmd8(sdfs_t *obj);
130static int sdfs__cmd58(sdfs_t *obj);
131static uint64_t sdfs__sd_sectors(sdfs_t *obj);
132static int sdfs__write(sdfs_t *obj, const uint8_t*buffer, uint32_t length);
133static int sdfs__read(sdfs_t *obj, uint8_t *buffer, uint32_t length);
134
135#define SD_COMMAND_TIMEOUT 5000
136
137#define SD_DBG 0
138
139sdfs_init(sdfs_t *obj, PinName mosi, PinName miso, PinName sclk, PinName cs, const char* name)
140{
141 obj->name = name;
142 spi_init(&obj->_spi, mosi, miso, sclk, NC);
143 gpio_init_out(&obj->_cs, cs);
144 gpio_write(&obj->_cs, 1);
145
146 // Set default to 100kHz for initialisation and 1MHz for data transfer
147 obj->_init_sck = 100000;
148 obj->_transfer_sck = 1000000;
149 obj->_is_initialized = STA_NOINIT;
150}
151
152#define R1_IDLE_STATE (1 << 0)
153#define R1_ERASE_RESET (1 << 1)
154#define R1_ILLEGAL_COMMAND (1 << 2)
155#define R1_COM_CRC_ERROR (1 << 3)
156#define R1_ERASE_SEQUENCE_ERROR (1 << 4)
157#define R1_ADDRESS_ERROR (1 << 5)
158#define R1_PARAMETER_ERROR (1 << 6)
159
160int sdfs_initialise_card(sdfs_t *obj)
161{
162 spi_format(&obj->_spi, 8, 0, 0);
163 // Set to 100kHz for initialisation, and clock card with cs = 1
164 spi_frequency(&obj->_spi, obj->_init_sck);
165 gpio_write(&obj->_cs, 1);
166 for (int i = 0; i < 16; i++) {
167 spi_master_write(&obj->_spi, 0xFF);
168 }
169
170 // send CMD0, should return with all zeros except IDLE STATE set (bit 0)
171 if (sdfs__cmd(obj, 0, 0) != R1_IDLE_STATE) {
172 debug("No disk, or could not put SD card in to SPI idle state\n");
173 return CT_FAIL;
174 }
175
176 // send CMD8 to determine whther it is ver 2.x
177 int r = sdfs__cmd8(obj);
178 if (r == R1_IDLE_STATE) {
179 return sdfs_initialise_card_v2(obj);
180 }
181 else if (r == (R1_IDLE_STATE | R1_ILLEGAL_COMMAND)) {
182 return sdfs_initialise_card_v1(obj);
183 }
184 else {
185 debug("Not in idle state after sending CMD8 (not an SD card?)\n");
186 return CT_FAIL;
187 }
188}
189
190static int sdfs_initialise_card_v1(sdfs_t *obj)
191{
192 sdfs__cmd(obj, 55, 0);
193 if (sdfs__cmd(obj, 41, 0) <= 1) {
194 obj->cdv = 512;
195 debug_if(SD_DBG, "\n\rInit: SEDCARD_V1\n\r");
196 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
197 sdfs__cmd(obj, 55, 0);
198 if (sdfs__cmd(obj, 41, 0) == 0) {
199 break;
200 }
201 }
202 return CT_SD1;
203 }
204 else {
205 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
206 if (sdfs__cmd(obj, 1, 0) == 0)
207 break;
208 }
209 return CT_MMC;
210 }
211 //if (!Timer1 || sdfs__cmd(obj, 16, 512) != 0) /* Set block length: 512 */
212 // ty = 0;
213
214 debug("Timeout waiting for v1.x card\n");
215 return CT_FAIL;
216}
217
218static int sdfs_initialise_card_v2(sdfs_t *obj)
219{
220 int n;
221 uint8_t ocr[4];
222
223 /* Get 32 bit return value of R7 resp */
224 for (n = 0; n < 4; n++) ocr[n] = spi_master_write(&obj->_spi, 0xFF);
225 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
226 sdfs__cmd(obj, 55, 0);
227 if (sdfs__cmd(obj, 41, 0x40000000) == 0) {
228 if (sdfs__cmd58(obj) == 0) {
229 for (n = 0; n < 4; n++) ocr[n] = spi_master_write(&obj->_spi, 0xFF);
230 debug_if(SD_DBG, "\n\rInit: SDCARD_V2\n\r");
231 obj->cdv = 1;
232 return (ocr[0] & 0x40) ? CT_SD2 | CT_BLOCK : CT_SD2;
233 }
234 }
235 wait_ms(50);
236 }
237
238 debug("Timeout waiting for v2.x card\n");
239 return CT_FAIL;
240}
241
242int sdfs_initialize(sdfs_t *obj)
243{
244 obj->_is_initialized |= STA_NOINIT;
245
246 obj->_card_type = sdfs_initialise_card(obj);
247 if (obj->_card_type == 0) {
248 debug("Fail to initialize card\n");
249 return 1;
250 }
251 debug_if(SD_DBG, "init card = %x\n", obj->_is_initialized);
252
253 obj->_sectors = sdfs__sd_sectors(obj);
254
255 if (sdfs__cmdx(obj, 10, 0) != 0 /* READ_CID */
256 || sdfs__read(obj, obj->_cid, 16) != 0) {
257 obj->_card_type = CT_FAIL;
258 debug("Fail to read cid\n");
259 return 1;
260 }
261
262 // Set block length to 512 (CMD16)
263 if (sdfs__cmd(obj, 16, 512) != 0) {
264 obj->_card_type = CT_FAIL;
265 debug("Set 512-byte block timed out\n");
266 return 1;
267 }
268
269 obj->_is_initialized &= ~STA_NOINIT;
270
271 // Set SCK for data transfer
272 spi_frequency(&obj->_spi, obj->_transfer_sck);
273 return 0;
274}
275
276int sdfs_write(sdfs_t *obj, const uint8_t *buffer, uint32_t block_number, uint32_t count)
277{
278 if (obj->_is_initialized & (STA_NOINIT | STA_PROTECT)) {
279 return -1;
280 }
281
282 for (uint32_t b = block_number; b < block_number + count; b++) {
283 // set write address for single block (CMD24)
284 if (sdfs__cmd(obj, 24, b * obj->cdv) != 0) {
285 return 1;
286 }
287
288 // send the data block
289 sdfs__write(obj, buffer, 512);
290 buffer += 512;
291 }
292
293 return 0;
294}
295
296int sdfs_read(sdfs_t *obj, uint8_t *buffer, uint32_t block_number, uint32_t count)
297{
298 if (obj->_is_initialized & STA_NOINIT) {
299 return -1;
300 }
301
302 for (uint32_t b = block_number; b < block_number + count; b++) {
303 // set read address for single block (CMD17)
304 if (sdfs__cmd(obj, 17, b * obj->cdv) != 0) {
305 return 1;
306 }
307
308 // receive the data
309 sdfs__read(obj, buffer, 512);
310 buffer += 512;
311 }
312
313 return 0;
314}
315
316int sdfs_status(sdfs_t *obj)
317{
318 // FATFileSystem::disk_status() returns 0 when initialized
319 if ((obj->_is_initialized & STA_NOINIT) == 0) {
320 return 0;
321 }
322 else {
323 return 1;
324 }
325}
326
327uint64_t sdfs_sectors(sdfs_t *obj) { return obj->_sectors; }
328
329
330// PRIVATE FUNCTIONS
331static int sdfs__cmd(sdfs_t *obj, int cmd, int arg)
332{
333 gpio_write(&obj->_cs, 0);
334
335 // send a command
336 spi_master_write(&obj->_spi, 0x40 | cmd);
337 spi_master_write(&obj->_spi, arg >> 24);
338 spi_master_write(&obj->_spi, arg >> 16);
339 spi_master_write(&obj->_spi, arg >> 8);
340 spi_master_write(&obj->_spi, arg >> 0);
341 spi_master_write(&obj->_spi, 0x95);
342
343 // wait for the repsonse (response[7] == 0)
344 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
345 int response = spi_master_write(&obj->_spi, 0xFF);
346 if (!(response & 0x80)) {
347 gpio_write(&obj->_cs, 1);
348 spi_master_write(&obj->_spi, 0xFF);
349 return response;
350 }
351 }
352 gpio_write(&obj->_cs, 1);
353 spi_master_write(&obj->_spi, 0xFF);
354 return -1; // timeout
355}
356
357int sdfs__cmdx(sdfs_t *obj, int cmd, int arg)
358{
359 gpio_write(&obj->_cs, 0);
360
361 // send a command
362 spi_master_write(&obj->_spi, 0x40 | cmd);
363 spi_master_write(&obj->_spi, arg >> 24);
364 spi_master_write(&obj->_spi, arg >> 16);
365 spi_master_write(&obj->_spi, arg >> 8);
366 spi_master_write(&obj->_spi, arg >> 0);
367 spi_master_write(&obj->_spi, 0x95);
368
369 // wait for the repsonse (response[7] == 0)
370 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
371 int response = spi_master_write(&obj->_spi, 0xFF);
372 if (!(response & 0x80)) {
373 return response;
374 }
375 }
376 gpio_write(&obj->_cs, 1);
377 spi_master_write(&obj->_spi, 0xFF);
378 return -1; // timeout
379}
380
381static int sdfs__cmd58(sdfs_t *obj)
382{
383 gpio_write(&obj->_cs, 0);
384 int arg = 0;
385
386 // send a command
387 spi_master_write(&obj->_spi, 0x40 | 58);
388 spi_master_write(&obj->_spi, arg >> 24);
389 spi_master_write(&obj->_spi, arg >> 16);
390 spi_master_write(&obj->_spi, arg >> 8);
391 spi_master_write(&obj->_spi, arg >> 0);
392 spi_master_write(&obj->_spi, 0x95);
393
394 // wait for the repsonse (response[7] == 0)
395 for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
396 int response = spi_master_write(&obj->_spi, 0xFF);
397 if (!(response & 0x80)) {
398 int ocr = spi_master_write(&obj->_spi, 0xFF) << 24;
399 ocr |= spi_master_write(&obj->_spi, 0xFF) << 16;
400 ocr |= spi_master_write(&obj->_spi, 0xFF) << 8;
401 ocr |= spi_master_write(&obj->_spi, 0xFF) << 0;
402 gpio_write(&obj->_cs, 1);
403 spi_master_write(&obj->_spi, 0xFF);
404 return response;
405 }
406 }
407 gpio_write(&obj->_cs, 1);
408 spi_master_write(&obj->_spi, 0xFF);
409 return -1; // timeout
410}
411
412static int sdfs__cmd8(sdfs_t *obj)
413{
414 gpio_write(&obj->_cs, 0);
415
416 // send a command
417 spi_master_write(&obj->_spi, 0x40 | 8); // CMD8
418 spi_master_write(&obj->_spi, 0x00); // reserved
419 spi_master_write(&obj->_spi, 0x00); // reserved
420 spi_master_write(&obj->_spi, 0x01); // 3.3v
421 spi_master_write(&obj->_spi, 0xAA); // check pattern
422 spi_master_write(&obj->_spi, 0x87); // crc
423
424 // wait for the repsonse (response[7] == 0)
425 for (int i = 0; i < SD_COMMAND_TIMEOUT * 1000; i++) {
426 char response[5];
427 response[0] = spi_master_write(&obj->_spi, 0xFF);
428 if (!(response[0] & 0x80)) {
429 for (int j = 1; j < 5; j++) {
430 response[i] = spi_master_write(&obj->_spi, 0xFF);
431 }
432 gpio_write(&obj->_cs, 1);
433 spi_master_write(&obj->_spi, 0xFF);
434 return response[0];
435 }
436 }
437 gpio_write(&obj->_cs, 1);
438 spi_master_write(&obj->_spi, 0xFF);
439 return -1; // timeout
440}
441
442static int sdfs__read(sdfs_t *obj, uint8_t *buffer, uint32_t length)
443{
444 gpio_write(&obj->_cs, 0);
445
446 // read until start byte (0xFF)
447 while (spi_master_write(&obj->_spi, 0xFF) != 0xFE);
448
449 // read data
450 for (int i = 0; i < length; i++) {
451 buffer[i] = spi_master_write(&obj->_spi, 0xFF);
452 }
453 spi_master_write(&obj->_spi, 0xFF); // checksum
454 spi_master_write(&obj->_spi, 0xFF);
455
456 gpio_write(&obj->_cs, 1);
457 spi_master_write(&obj->_spi, 0xFF);
458 return 0;
459}
460
461static int sdfs__write(sdfs_t *obj, const uint8_t*buffer, uint32_t length)
462{
463 gpio_write(&obj->_cs, 0);
464
465 // indicate start of block
466 spi_master_write(&obj->_spi, 0xFE);
467
468 // write the data
469 for (int i = 0; i < length; i++) {
470 spi_master_write(&obj->_spi, buffer[i]);
471 }
472
473 // write the checksum
474 spi_master_write(&obj->_spi, 0xFF);
475 spi_master_write(&obj->_spi, 0xFF);
476
477 // check the response token
478 if ((spi_master_write(&obj->_spi, 0xFF) & 0x1F) != 0x05) {
479 gpio_write(&obj->_cs, 1);
480 spi_master_write(&obj->_spi, 0xFF);
481 return 1;
482 }
483
484 // wait for write to finish
485 while (spi_master_write(&obj->_spi, 0xFF) == 0);
486
487 gpio_write(&obj->_cs, 1);
488 spi_master_write(&obj->_spi, 0xFF);
489 return 0;
490}
491
492static uint32_t sdfs_ext_bits(sdfs_t *obj, unsigned char *data, int msb, int lsb)
493{
494 uint32_t bits = 0;
495 uint32_t size = 1 + msb - lsb;
496 for (uint32_t i = 0; i < size; i++) {
497 uint32_t position = lsb + i;
498 uint32_t byte = 15 - (position >> 3);
499 uint32_t bit = position & 0x7;
500 uint32_t value = (data[byte] >> bit) & 1;
501 bits |= value << i;
502 }
503 return bits;
504}
505
506static uint64_t sdfs__sd_sectors(sdfs_t *obj)
507{
508 uint32_t c_size, c_size_mult, read_bl_len;
509 uint32_t mult, blocknr;
510 uint32_t hc_c_size;
511 uint64_t blocks;
512
513 // CMD9, Response R2 (R1 byte + 16-byte block read)
514 if (sdfs__cmdx(obj, 9, 0) != 0) {
515 debug("Didn't get a response from the disk\n");
516 return 0;
517 }
518
519 if (sdfs__read(obj, obj->_csd, 16) != 0) {
520 debug("Couldn't read csd response from disk\n");
521 return 0;
522 }
523
524 // csd_structure : csd[127:126]
525 // c_size : csd[73:62]
526 // c_size_mult : csd[49:47]
527 // read_bl_len : csd[83:80] - the *maximum* read block length
528
529 int csd_structure = sdfs_ext_bits(obj, obj->_csd, 127, 126);
530
531 switch (csd_structure) {
532 case 0:
533 obj->cdv = 512;
534 c_size = sdfs_ext_bits(obj, obj->_csd, 73, 62);
535 c_size_mult = sdfs_ext_bits(obj, obj->_csd, 49, 47);
536 read_bl_len = sdfs_ext_bits(obj, obj->_csd, 83, 80);
537
538 obj->_block_len = 1 << read_bl_len;
539 mult = 1 << (c_size_mult + 2);
540 blocknr = (c_size + 1) * mult;
541 obj->_capacity = blocknr * obj->_block_len;
542 blocks = obj->_capacity / 512;
543 debug_if(SD_DBG, "\n\rSDCard\n\rc_size: %d \n\rcapacity: %ld \n\rsectors: %lld\n\r", c_size, obj->_capacity, blocks);
544 break;
545
546 case 1:
547 obj->cdv = 1;
548 hc_c_size = sdfs_ext_bits(obj, obj->_csd, 63, 48);
549 blocks = (hc_c_size + 1) * 1024;
550 debug_if(SD_DBG, "\n\rSDHC Card \n\rhc_c_size: %d\n\rcapacity: %lld \n\rsectors: %lld\n\r", hc_c_size, blocks * 512, blocks);
551 break;
552
553 default:
554 debug("CSD struct unsupported\r\n");
555 return 0;
556 };
557 return blocks;
558}
559
560static
561int wait_ready(sdfs_t *obj, uint32_t wt)
562{
563 /* Wait until card goes ready or timeout */
564 for (int i = 0; i < wt; i++) {
565 if (spi_master_write(&obj->_spi, 0xFF) == 0xFF)
566 /* Card goes ready */
567 return 1;
568 }
569
570 /* Timeout occured */
571 return 0;
572}
573
574static
575void deselect(sdfs_t *obj)
576{
577 /* Set CS# high */
578 gpio_write(&obj->_cs, 0);
579
580 /* Dummy clock (force DO hi-z for multiple slave SPI) */
581 spi_master_write(&obj->_spi, 0xFF);
582}
583
584static
585int select(sdfs_t *obj)
586{
587 /* Set CS# low */
588 gpio_write(&obj->_cs, 1);
589
590 /* Dummy clock (force DO enabled) */
591 spi_master_write(&obj->_spi, 0xFF);
592
593 /* Wait for card ready */
594 if (wait_ready(obj, 500))
595 return 0;
596
597 deselect(obj);
598
599 /* Failed to select the card due to timeout */
600 return -1;
601}
602
603int sdfs_sync(sdfs_t *obj)
604{
605 int ret = select(obj);
606 deselect(obj);
607 return ret;
608}
609
610int sdfs_trim(sdfs_t *obj, uint32_t st, uint32_t ed)
611{
612 int res = -1;
613
614 for(;;) {
615 /* Check if the card is SDC */
616 if (!(obj->_card_type & CT_SDC))
617 break;
618 /* Check if sector erase can be applied to the card */
619 if (!(obj->_csd[0] >> 6) && !(obj->_csd[10] & 0x40))
620 break;
621 /* Load sector block */
622 if (!(obj->_card_type & CT_BLOCK)) {
623 st *= 512; ed *= 512;
624 }
625 /* Erase sector block */
626 if ((sdfs__cmd(obj, 32, st) == 0)
627 && (sdfs__cmd(obj, 33, ed) == 0)
628 && (sdfs__cmd(obj, 38, 0) == 0)
629 && wait_ready(obj, 30000))
630 res = 0;
631 }
632
633 return res;
634}
635
636int sdfs_get_ocr(sdfs_t *obj, uint8_t buff[4])
637{
638 int res = -1, n;
639
640 /* READ_OCR */
641 if (sdfs__cmd58(obj) == 0) {
642 for (n = 4; n; n--) {
643 *buff++ = spi_master_write(&obj->_spi, 0xFF);
644 }
645 res = 0;
646 }
647
648 deselect(obj);
649
650 return res;
651}
652
653int sdfs_get_sdstat(sdfs_t *obj, uint8_t buff[64])
654{
655 int res = -1;
656
657 sdfs__cmd(obj, 55, 0);
658
659 /* SD_STATUS */
660 if (sdfs__cmd(obj, 13, 0) == 0) {
661 spi_master_write(&obj->_spi, 0xFF);
662 if (sdfs__read(obj, buff, 64) == 0)
663 return 0;
664 }
665
666 deselect(obj);
667
668 return res;
669}
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