[352] | 1 | /* mbed Microcontroller Library
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| 2 | * Copyright (c) 2006-2015 ARM Limited
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| 3 | *
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| 4 | * Licensed under the Apache License, Version 2.0 (the "License");
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| 5 | * you may not use this file except in compliance with the License.
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| 6 | * You may obtain a copy of the License at
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| 7 | *
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| 8 | * http://www.apache.org/licenses/LICENSE-2.0
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| 9 | *
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| 10 | * Unless required by applicable law or agreed to in writing, software
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| 11 | * distributed under the License is distributed on an "AS IS" BASIS,
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| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 13 | * See the License for the specific language governing permissions and
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| 14 | * limitations under the License.
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| 15 | */
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| 16 | // math.h required for floating point operations for baud rate calculation
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| 17 | #include "mbed_assert.h"
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| 18 | #include <math.h>
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| 19 | #include <string.h>
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| 20 | #include <stdlib.h>
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| 21 |
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| 22 | #include "serial_api.h"
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| 23 | #include "cmsis.h"
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| 24 | #include "pinmap.h"
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| 25 | #include "gpio_api.h"
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| 26 |
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| 27 | #include "scif_iodefine.h"
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| 28 | #include "cpg_iodefine.h"
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| 29 |
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| 30 | /******************************************************************************
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| 31 | * INITIALIZATION
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| 32 | ******************************************************************************/
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| 33 | #define PCLK (66666666) // Define the peripheral clock P1 frequency.
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| 34 |
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| 35 | #define UART_NUM 8
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| 36 | #define IRQ_NUM 4
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| 37 |
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| 38 | static void uart0_tx_irq(void);
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| 39 | static void uart1_tx_irq(void);
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| 40 | static void uart2_tx_irq(void);
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| 41 | static void uart3_tx_irq(void);
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| 42 | static void uart4_tx_irq(void);
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| 43 | static void uart5_tx_irq(void);
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| 44 | static void uart6_tx_irq(void);
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| 45 | static void uart7_tx_irq(void);
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| 46 | static void uart0_rx_irq(void);
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| 47 | static void uart1_rx_irq(void);
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| 48 | static void uart2_rx_irq(void);
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| 49 | static void uart3_rx_irq(void);
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| 50 | static void uart4_rx_irq(void);
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| 51 | static void uart5_rx_irq(void);
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| 52 | static void uart6_rx_irq(void);
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| 53 | static void uart7_rx_irq(void);
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| 54 | static void uart0_er_irq(void);
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| 55 | static void uart1_er_irq(void);
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| 56 | static void uart2_er_irq(void);
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| 57 | static void uart3_er_irq(void);
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| 58 | static void uart4_er_irq(void);
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| 59 | static void uart5_er_irq(void);
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| 60 | static void uart6_er_irq(void);
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| 61 | static void uart7_er_irq(void);
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| 62 |
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| 63 | static void serial_put_done(serial_t *obj);
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| 64 | static uint8_t serial_available_buffer(serial_t *obj);
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| 65 | static void serial_irq_err_set(serial_t *obj, uint32_t enable);
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| 66 |
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| 67 | static const PinMap PinMap_UART_TX[] = {
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| 68 | {P2_14 , UART0, 6},
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| 69 | {P2_5 , UART1, 6},
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| 70 | {P4_12 , UART1, 7},
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| 71 | {P6_3 , UART2, 7},
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| 72 | {P4_14 , UART2, 7},
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| 73 | {P5_3 , UART3, 5},
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| 74 | {P8_8 , UART3, 7},
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| 75 | {P5_0 , UART4, 5},
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| 76 | {P8_14 , UART4, 7},
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| 77 | {P8_13 , UART5, 5},
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| 78 | {P11_10, UART5, 3},
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| 79 | {P6_6 , UART5, 5},
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| 80 | {P5_6 , UART6, 5},
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| 81 | {P11_1 , UART6, 4},
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| 82 | {P7_4 , UART7, 4},
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| 83 | {NC , NC , 0}
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| 84 | };
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| 85 |
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| 86 | static const PinMap PinMap_UART_RX[] = {
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| 87 | {P2_15 , UART0, 6},
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| 88 | {P2_6 , UART1, 6},
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| 89 | {P4_13 , UART1, 7},
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| 90 | {P6_2 , UART2, 7},
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| 91 | {P4_15 , UART2, 7},
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| 92 | {P5_4 , UART3, 5},
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| 93 | {P8_9 , UART3, 7},
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| 94 | {P5_1 , UART4, 5},
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| 95 | {P8_15 , UART4, 7},
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| 96 | {P8_11 , UART5, 5},
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| 97 | {P11_11, UART5, 3},
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| 98 | {P6_7 , UART5, 5},
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| 99 | {P5_7 , UART6, 5},
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| 100 | {P11_2 , UART6, 4},
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| 101 | {P7_5 , UART7, 4},
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| 102 | {NC , NC , 0}
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| 103 | };
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| 104 |
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| 105 | static const PinMap PinMap_UART_CTS[] = {
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| 106 | {P2_3 , UART1, 6},
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| 107 | {P11_7 , UART5, 3},
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| 108 | {P7_6 , UART7, 4},
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| 109 | {NC , NC , 0}
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| 110 | };
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| 111 | static const PinMap PinMap_UART_RTS[] = {
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| 112 | {P2_7 , UART1, 6},
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| 113 | {P11_8 , UART5, 3},
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| 114 | {P7_7 , UART7, 4},
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| 115 | {NC , NC , 0}
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| 116 | };
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| 117 |
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| 118 |
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| 119 |
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| 120 | static const struct st_scif *SCIF[] = SCIF_ADDRESS_LIST;
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| 121 | static uart_irq_handler irq_handler;
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| 122 |
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| 123 | int stdio_uart_inited = 0;
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| 124 | serial_t stdio_uart;
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| 125 |
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| 126 | struct serial_global_data_s {
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| 127 | uint32_t serial_irq_id;
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| 128 | gpio_t sw_rts, sw_cts;
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| 129 | uint8_t rx_irq_set_flow, rx_irq_set_api;
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| 130 | serial_t *tranferring_obj, *receiving_obj;
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| 131 | uint32_t async_tx_callback, async_rx_callback;
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| 132 | int event, wanted_rx_events;
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| 133 | };
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| 134 |
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| 135 | static struct serial_global_data_s uart_data[UART_NUM];
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| 136 |
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| 137 | static const IRQn_Type irq_set_tbl[UART_NUM][IRQ_NUM] = {
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| 138 | {SCIFRXI0_IRQn, SCIFTXI0_IRQn, SCIFBRI0_IRQn, SCIFERI0_IRQn},
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| 139 | {SCIFRXI1_IRQn, SCIFTXI1_IRQn, SCIFBRI1_IRQn, SCIFERI1_IRQn},
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| 140 | {SCIFRXI2_IRQn, SCIFTXI2_IRQn, SCIFBRI2_IRQn, SCIFERI2_IRQn},
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| 141 | {SCIFRXI3_IRQn, SCIFTXI3_IRQn, SCIFBRI3_IRQn, SCIFERI3_IRQn},
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| 142 | {SCIFRXI4_IRQn, SCIFTXI4_IRQn, SCIFBRI4_IRQn, SCIFERI4_IRQn},
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| 143 | {SCIFRXI5_IRQn, SCIFTXI5_IRQn, SCIFBRI5_IRQn, SCIFERI5_IRQn},
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| 144 | {SCIFRXI6_IRQn, SCIFTXI6_IRQn, SCIFBRI6_IRQn, SCIFERI6_IRQn},
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| 145 | {SCIFRXI7_IRQn, SCIFTXI7_IRQn, SCIFBRI7_IRQn, SCIFERI7_IRQn}
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| 146 | };
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| 147 |
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| 148 | static const IRQHandler hander_set_tbl[UART_NUM][IRQ_NUM] = {
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| 149 | {uart0_rx_irq, uart0_tx_irq, uart0_er_irq, uart0_er_irq},
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| 150 | {uart1_rx_irq, uart1_tx_irq, uart1_er_irq, uart1_er_irq},
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| 151 | {uart2_rx_irq, uart2_tx_irq, uart2_er_irq, uart2_er_irq},
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| 152 | {uart3_rx_irq, uart3_tx_irq, uart3_er_irq, uart3_er_irq},
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| 153 | {uart4_rx_irq, uart4_tx_irq, uart4_er_irq, uart4_er_irq},
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| 154 | {uart5_rx_irq, uart5_tx_irq, uart5_er_irq, uart5_er_irq},
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| 155 | {uart6_rx_irq, uart6_tx_irq, uart6_er_irq, uart6_er_irq},
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| 156 | {uart7_rx_irq, uart7_tx_irq, uart7_er_irq, uart7_er_irq}
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| 157 | };
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| 158 |
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| 159 | static __IO uint16_t *SCSCR_MATCH[] = {
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| 160 | &SCSCR_0,
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| 161 | &SCSCR_1,
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| 162 | &SCSCR_2,
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| 163 | &SCSCR_3,
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| 164 | &SCSCR_4,
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| 165 | &SCSCR_5,
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| 166 | &SCSCR_6,
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| 167 | &SCSCR_7,
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| 168 | };
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| 169 |
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| 170 | static __IO uint16_t *SCFSR_MATCH[] = {
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| 171 | &SCFSR_0,
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| 172 | &SCFSR_1,
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| 173 | &SCFSR_2,
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| 174 | &SCFSR_3,
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| 175 | &SCFSR_4,
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| 176 | &SCFSR_5,
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| 177 | &SCFSR_6,
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| 178 | &SCFSR_7,
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| 179 | };
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| 180 |
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| 181 |
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| 182 | void serial_init(serial_t *obj, PinName tx, PinName rx) {
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| 183 | volatile uint8_t dummy ;
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| 184 | int is_stdio_uart = 0;
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| 185 | // determine the UART to use
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| 186 | uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
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| 187 | uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
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| 188 | uint32_t uart = pinmap_merge(uart_tx, uart_rx);
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| 189 |
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| 190 | MBED_ASSERT((int)uart != NC);
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| 191 |
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| 192 | obj->serial.uart = (struct st_scif *)SCIF[uart];
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| 193 | // enable power
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| 194 | switch (uart) {
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| 195 | case UART0:
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| 196 | CPG.STBCR4 &= ~(1 << 7);
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| 197 | break;
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| 198 | case UART1:
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| 199 | CPG.STBCR4 &= ~(1 << 6);
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| 200 | break;
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| 201 | case UART2:
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| 202 | CPG.STBCR4 &= ~(1 << 5);
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| 203 | break;
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| 204 | case UART3:
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| 205 | CPG.STBCR4 &= ~(1 << 4);
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| 206 | break;
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| 207 | case UART4:
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| 208 | CPG.STBCR4 &= ~(1 << 3);
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| 209 | break;
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| 210 | case UART5:
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| 211 | CPG.STBCR4 &= ~(1 << 2);
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| 212 | break;
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| 213 | case UART6:
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| 214 | CPG.STBCR4 &= ~(1 << 1);
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| 215 | break;
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| 216 | case UART7:
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| 217 | CPG.STBCR4 &= ~(1 << 0);
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| 218 | break;
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| 219 | }
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| 220 | dummy = CPG.STBCR4;
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| 221 |
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| 222 | /* ==== SCIF initial setting ==== */
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| 223 | /* ---- Serial control register (SCSCR) setting ---- */
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| 224 | /* B'00 : Internal CLK */
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| 225 | obj->serial.uart->SCSCR = 0x0000u; /* SCIF transmitting and receiving operations stop */
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| 226 |
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| 227 | /* ---- FIFO control register (SCFCR) setting ---- */
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| 228 | /* Transmit FIFO reset & Receive FIFO data register reset */
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| 229 | obj->serial.uart->SCFCR = 0x0006;
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| 230 |
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| 231 | /* ---- Serial status register (SCFSR) setting ---- */
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| 232 | dummy = obj->serial.uart->SCFSR;
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| 233 | obj->serial.uart->SCFSR = (dummy & 0xFF6Cu); /* ER,BRK,DR bit clear */
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| 234 |
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| 235 | /* ---- Line status register (SCLSR) setting ---- */
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| 236 | /* ORER bit clear */
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| 237 | obj->serial.uart->SCLSR = 0;
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| 238 |
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| 239 | /* ---- Serial extension mode register (SCEMR) setting ----
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| 240 | b7 BGDM - Baud rate generator double-speed mode : Normal mode
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| 241 | b0 ABCS - Base clock select in asynchronous mode : Base clock is 16 times the bit rate */
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| 242 | obj->serial.uart->SCEMR = 0x0000u;
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| 243 |
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| 244 | /* ---- Bit rate register (SCBRR) setting ---- */
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| 245 | serial_baud (obj, 9600);
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| 246 | serial_format(obj, 8, ParityNone, 1);
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| 247 |
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| 248 | /* ---- FIFO control register (SCFCR) setting ---- */
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| 249 | obj->serial.uart->SCFCR = 0x0030u;
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| 250 |
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| 251 | /* ---- Serial port register (SCSPTR) setting ----
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| 252 | b1 SPB2IO - Serial port break output : disabled
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| 253 | b0 SPB2DT - Serial port break data : High-level */
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| 254 | obj->serial.uart->SCSPTR = 0x0003u; // SPB2IO = 1, SPB2DT = 1
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| 255 |
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| 256 | /* ---- Line status register (SCLSR) setting ----
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| 257 | b0 ORER - Overrun error detect : clear */
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| 258 |
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| 259 | if (obj->serial.uart->SCLSR & 0x0001) {
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| 260 | obj->serial.uart->SCLSR = 0u; // ORER clear
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| 261 | }
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| 262 |
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| 263 | // pinout the chosen uart
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| 264 | pinmap_pinout(tx, PinMap_UART_TX);
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| 265 | pinmap_pinout(rx, PinMap_UART_RX);
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| 266 |
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| 267 | switch (uart) {
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| 268 | case UART0:
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| 269 | obj->serial.index = 0;
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| 270 | break;
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| 271 | case UART1:
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| 272 | obj->serial.index = 1;
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| 273 | break;
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| 274 | case UART2:
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| 275 | obj->serial.index = 2;
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| 276 | break;
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| 277 | case UART3:
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| 278 | obj->serial.index = 3;
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| 279 | break;
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| 280 | case UART4:
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| 281 | obj->serial.index = 4;
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| 282 | break;
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| 283 | case UART5:
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| 284 | obj->serial.index = 5;
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| 285 | break;
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| 286 | case UART6:
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| 287 | obj->serial.index = 6;
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| 288 | break;
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| 289 | case UART7:
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| 290 | obj->serial.index = 7;
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| 291 | break;
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| 292 | }
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| 293 | uart_data[obj->serial.index].sw_rts.pin = NC;
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| 294 | uart_data[obj->serial.index].sw_cts.pin = NC;
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| 295 |
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| 296 | /* ---- Serial control register (SCSCR) setting ---- */
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| 297 | /* Setting the TE and RE bits enables the TxD and RxD pins to be used. */
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| 298 | obj->serial.uart->SCSCR = 0x0070;
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| 299 |
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| 300 | is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
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| 301 |
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| 302 | if (is_stdio_uart) {
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| 303 | stdio_uart_inited = 1;
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| 304 | memcpy(&stdio_uart, obj, sizeof(serial_t));
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| 305 | }
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| 306 | }
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| 307 |
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| 308 | void serial_free(serial_t *obj) {
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| 309 | uart_data[obj->serial.index].serial_irq_id = 0;
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| 310 | }
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| 311 |
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| 312 | // serial_baud
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| 313 | // set the baud rate, taking in to account the current SystemFrequency
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| 314 | void serial_baud(serial_t *obj, int baudrate) {
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| 315 | uint16_t DL;
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| 316 |
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| 317 | obj->serial.uart->SCSMR &= ~0x0003;
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| 318 |
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| 319 | if (baudrate > 32552) {
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| 320 | obj->serial.uart->SCEMR = 0x0081; // BGDM = 1, ABCS = 1
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| 321 | DL = PCLK / (8 * baudrate);
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| 322 | if (DL > 0) {
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| 323 | DL--;
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| 324 | }
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| 325 | obj->serial.uart->SCBRR = (uint8_t)DL;
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| 326 | } else if (baudrate > 16276) {
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| 327 | obj->serial.uart->SCEMR = 0x0080; // BGDM = 1
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| 328 | obj->serial.uart->SCBRR = PCLK / (16 * baudrate) - 1;
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| 329 | } else if (baudrate > 8138) {
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| 330 | obj->serial.uart->SCEMR = 0x0000;
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| 331 | obj->serial.uart->SCBRR = PCLK / (32 * baudrate) - 1;
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| 332 | } else if (baudrate > 4169) {
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| 333 | obj->serial.uart->SCSMR |= 0x0001;
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| 334 | obj->serial.uart->SCEMR = 0x0080; // BGDM = 1
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| 335 | obj->serial.uart->SCBRR = PCLK / (64 * baudrate) - 1;
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| 336 | } else if (baudrate > 2034) {
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| 337 | obj->serial.uart->SCSMR |= 0x0001;
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| 338 | obj->serial.uart->SCEMR = 0x0000;
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| 339 | obj->serial.uart->SCBRR = PCLK / (128 * baudrate) - 1;
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| 340 | } else if (baudrate > 1017) {
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| 341 | obj->serial.uart->SCSMR |= 0x0002;
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| 342 | obj->serial.uart->SCEMR = 0x0080; // BGDM = 1
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| 343 | obj->serial.uart->SCBRR = PCLK / (256 * baudrate) - 1;
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| 344 | } else if (baudrate > 508) {
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| 345 | obj->serial.uart->SCSMR |= 0x0002;
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| 346 | obj->serial.uart->SCEMR = 0x0000;
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| 347 | obj->serial.uart->SCBRR = PCLK / (512 * baudrate) - 1;
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| 348 | } else if (baudrate > 254) {
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| 349 | obj->serial.uart->SCSMR |= 0x0003;
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| 350 | obj->serial.uart->SCEMR = 0x0080; // BGDM = 1
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| 351 | obj->serial.uart->SCBRR = PCLK / (1024 * baudrate) - 1;
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| 352 | } else if (baudrate > 127) {
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| 353 | obj->serial.uart->SCSMR |= 0x0003;
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| 354 | obj->serial.uart->SCEMR = 0x0000;
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| 355 | obj->serial.uart->SCBRR = PCLK / (2048 * baudrate) - 1;
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| 356 | } else {
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| 357 | obj->serial.uart->SCSMR |= 0x0003;
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| 358 | obj->serial.uart->SCEMR = 0x0000;
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| 359 | obj->serial.uart->SCBRR = 0xFFu;
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| 360 | }
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| 361 | }
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| 362 |
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| 363 | void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
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| 364 | int parity_enable;
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| 365 | int parity_select;
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| 366 |
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| 367 | MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
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| 368 | MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 5: 5 data bits ... 3: 8 data bits
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| 369 | MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
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| 370 | (parity == ParityForced1) || (parity == ParityForced0));
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| 371 |
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| 372 | stop_bits = (stop_bits == 1)? 0:
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| 373 | (stop_bits == 2)? 1:
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| 374 | 0; // must not to be
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| 375 |
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| 376 | data_bits = (data_bits == 8)? 0:
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| 377 | (data_bits == 7)? 1:
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| 378 | 0; // must not to be
|
---|
| 379 |
|
---|
| 380 | switch (parity) {
|
---|
| 381 | case ParityNone:
|
---|
| 382 | parity_enable = 0;
|
---|
| 383 | parity_select = 0;
|
---|
| 384 | break;
|
---|
| 385 | case ParityOdd:
|
---|
| 386 | parity_enable = 1;
|
---|
| 387 | parity_select = 1;
|
---|
| 388 | break;
|
---|
| 389 | case ParityEven:
|
---|
| 390 | parity_enable = 1;
|
---|
| 391 | parity_select = 0;
|
---|
| 392 | break;
|
---|
| 393 | case ParityForced1:
|
---|
| 394 | case ParityForced0:
|
---|
| 395 | default:
|
---|
| 396 | parity_enable = 0;
|
---|
| 397 | parity_select = 0;
|
---|
| 398 | break;
|
---|
| 399 | }
|
---|
| 400 |
|
---|
| 401 | obj->serial.uart->SCSMR = (obj->serial.uart->SCSMR & ~0x0078)
|
---|
| 402 | | (data_bits << 6)
|
---|
| 403 | | (parity_enable << 5)
|
---|
| 404 | | (parity_select << 4)
|
---|
| 405 | | (stop_bits << 3);
|
---|
| 406 | }
|
---|
| 407 |
|
---|
| 408 | /******************************************************************************
|
---|
| 409 | * INTERRUPTS HANDLING
|
---|
| 410 | ******************************************************************************/
|
---|
| 411 |
|
---|
| 412 | static void uart_tx_irq(IRQn_Type irq_num, uint32_t index) {
|
---|
| 413 | __IO uint16_t *dmy_rd_scscr;
|
---|
| 414 | __IO uint16_t *dmy_rd_scfsr;
|
---|
| 415 | serial_t *obj;
|
---|
| 416 | int i;
|
---|
| 417 |
|
---|
| 418 | dmy_rd_scscr = SCSCR_MATCH[index];
|
---|
| 419 | *dmy_rd_scscr &= 0x007B; // Clear TIE and Write to bit15~8,2 is always 0
|
---|
| 420 | dmy_rd_scfsr = SCFSR_MATCH[index];
|
---|
| 421 | *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0020); // Set TEND
|
---|
| 422 |
|
---|
| 423 | obj = uart_data[index].tranferring_obj;
|
---|
| 424 | if (obj) {
|
---|
| 425 | i = obj->tx_buff.length - obj->tx_buff.pos;
|
---|
| 426 | if (0 < i) {
|
---|
| 427 | if (serial_available_buffer(obj) < i) {
|
---|
| 428 | i = serial_available_buffer(obj);
|
---|
| 429 | }
|
---|
| 430 | do {
|
---|
| 431 | uint8_t c = *(uint8_t *)obj->tx_buff.buffer;
|
---|
| 432 | obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + 1;
|
---|
| 433 | ++obj->tx_buff.pos;
|
---|
| 434 | obj->serial.uart->SCFTDR = c;
|
---|
| 435 | } while (--i);
|
---|
| 436 | serial_put_done(obj);
|
---|
| 437 | } else {
|
---|
| 438 | uart_data[index].tranferring_obj = NULL;
|
---|
| 439 | uart_data[index].event = SERIAL_EVENT_TX_COMPLETE;
|
---|
| 440 | ((void (*)())uart_data[index].async_tx_callback)();
|
---|
| 441 | }
|
---|
| 442 | }
|
---|
| 443 |
|
---|
| 444 | irq_handler(uart_data[index].serial_irq_id, TxIrq);
|
---|
| 445 | }
|
---|
| 446 |
|
---|
| 447 | static void uart_rx_irq(IRQn_Type irq_num, uint32_t index) {
|
---|
| 448 | __IO uint16_t *dmy_rd_scscr;
|
---|
| 449 | __IO uint16_t *dmy_rd_scfsr;
|
---|
| 450 | serial_t *obj;
|
---|
| 451 | int c;
|
---|
| 452 |
|
---|
| 453 | dmy_rd_scscr = SCSCR_MATCH[index];
|
---|
| 454 | *dmy_rd_scscr &= 0x00B3; // Clear RIE,REIE and Write to bit15~8,2 is always 0
|
---|
| 455 | dmy_rd_scfsr = SCFSR_MATCH[index];
|
---|
| 456 | *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0003); // Clear RDF,DR
|
---|
| 457 |
|
---|
| 458 | obj = uart_data[index].receiving_obj;
|
---|
| 459 | if (obj) {
|
---|
| 460 | if (obj->serial.uart->SCLSR & 1) {
|
---|
| 461 | if (uart_data[index].wanted_rx_events & SERIAL_EVENT_RX_OVERRUN_ERROR) {
|
---|
| 462 | serial_rx_abort_asynch(obj);
|
---|
| 463 | uart_data[index].event = SERIAL_EVENT_RX_OVERRUN_ERROR;
|
---|
| 464 | ((void (*)())uart_data[index].async_rx_callback)();
|
---|
| 465 | }
|
---|
| 466 | return;
|
---|
| 467 | }
|
---|
| 468 | c = serial_getc(obj);
|
---|
| 469 | if (c != -1) {
|
---|
| 470 | ((uint8_t *)obj->rx_buff.buffer)[obj->rx_buff.pos] = c;
|
---|
| 471 | ++obj->rx_buff.pos;
|
---|
| 472 | if (c == obj->char_match && ! obj->char_found) {
|
---|
| 473 | obj->char_found = 1;
|
---|
| 474 | if (obj->rx_buff.pos == obj->rx_buff.length) {
|
---|
| 475 | if (uart_data[index].wanted_rx_events & SERIAL_EVENT_RX_COMPLETE) {
|
---|
| 476 | uart_data[index].event = SERIAL_EVENT_RX_COMPLETE;
|
---|
| 477 | }
|
---|
| 478 | }
|
---|
| 479 | if (uart_data[index].wanted_rx_events & SERIAL_EVENT_RX_CHARACTER_MATCH) {
|
---|
| 480 | uart_data[index].event |= SERIAL_EVENT_RX_CHARACTER_MATCH;
|
---|
| 481 | }
|
---|
| 482 | if (uart_data[index].event) {
|
---|
| 483 | uart_data[index].receiving_obj = NULL;
|
---|
| 484 | ((void (*)())uart_data[index].async_rx_callback)();
|
---|
| 485 | }
|
---|
| 486 | } else if (obj->rx_buff.pos == obj->rx_buff.length) {
|
---|
| 487 | uart_data[index].receiving_obj = NULL;
|
---|
| 488 | if (uart_data[index].wanted_rx_events & SERIAL_EVENT_RX_COMPLETE) {
|
---|
| 489 | uart_data[index].event = SERIAL_EVENT_RX_COMPLETE;
|
---|
| 490 | ((void (*)())uart_data[index].async_rx_callback)();
|
---|
| 491 | }
|
---|
| 492 | }
|
---|
| 493 | } else {
|
---|
| 494 | serial_rx_abort_asynch(obj);
|
---|
| 495 | if (uart_data[index].wanted_rx_events & (SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR)) {
|
---|
| 496 | uart_data[index].event = SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR;
|
---|
| 497 | if (obj->serial.uart->SCFSR & 1 << 2) {
|
---|
| 498 | uart_data[index].event = SERIAL_EVENT_RX_PARITY_ERROR;
|
---|
| 499 | } else if (obj->serial.uart->SCFSR & 1 << 3) {
|
---|
| 500 | uart_data[index].event = SERIAL_EVENT_RX_FRAMING_ERROR;
|
---|
| 501 | }
|
---|
| 502 | ((void (*)())uart_data[index].async_rx_callback)();
|
---|
| 503 | }
|
---|
| 504 | return;
|
---|
| 505 | }
|
---|
| 506 | }
|
---|
| 507 |
|
---|
| 508 | irq_handler(uart_data[index].serial_irq_id, RxIrq);
|
---|
| 509 | }
|
---|
| 510 |
|
---|
| 511 | static void uart_err_irq(IRQn_Type irq_num, uint32_t index) {
|
---|
| 512 | serial_t *obj = uart_data[index].receiving_obj;
|
---|
| 513 | int was_masked, err_read;
|
---|
| 514 |
|
---|
| 515 | if (obj) {
|
---|
| 516 | serial_irq_err_set(obj, 0);
|
---|
| 517 | if (uart_data[index].wanted_rx_events & (SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR)) {
|
---|
| 518 | uart_data[index].event = SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR;
|
---|
| 519 | if (obj->serial.uart->SCFSR & 1 << 2) {
|
---|
| 520 | uart_data[index].event = SERIAL_EVENT_RX_PARITY_ERROR;
|
---|
| 521 | } else if (obj->serial.uart->SCFSR & 1 << 3) {
|
---|
| 522 | uart_data[index].event = SERIAL_EVENT_RX_FRAMING_ERROR;
|
---|
| 523 | }
|
---|
| 524 | ((void (*)())uart_data[index].async_rx_callback)();
|
---|
| 525 | }
|
---|
| 526 | serial_rx_abort_asynch(obj);
|
---|
| 527 |
|
---|
| 528 | #if defined ( __ICCARM__ )
|
---|
| 529 | was_masked = __disable_irq_iar();
|
---|
| 530 | #else
|
---|
| 531 | was_masked = __disable_irq();
|
---|
| 532 | #endif /* __ICCARM__ */
|
---|
| 533 | if (obj->serial.uart->SCFSR & 0x93) {
|
---|
| 534 | err_read = obj->serial.uart->SCFSR;
|
---|
| 535 | obj->serial.uart->SCFSR = (err_read & ~0x93);
|
---|
| 536 | }
|
---|
| 537 | if (obj->serial.uart->SCLSR & 1) {
|
---|
| 538 | obj->serial.uart->SCLSR = 0;
|
---|
| 539 | }
|
---|
| 540 | if (!was_masked) {
|
---|
| 541 | __enable_irq();
|
---|
| 542 | }
|
---|
| 543 | }
|
---|
| 544 | }
|
---|
| 545 |
|
---|
| 546 | /* TX handler */
|
---|
| 547 | static void uart0_tx_irq(void) {
|
---|
| 548 | uart_tx_irq(SCIFTXI0_IRQn, 0);
|
---|
| 549 | }
|
---|
| 550 | static void uart1_tx_irq(void) {
|
---|
| 551 | uart_tx_irq(SCIFTXI1_IRQn, 1);
|
---|
| 552 | }
|
---|
| 553 | static void uart2_tx_irq(void) {
|
---|
| 554 | uart_tx_irq(SCIFTXI2_IRQn, 2);
|
---|
| 555 | }
|
---|
| 556 | static void uart3_tx_irq(void) {
|
---|
| 557 | uart_tx_irq(SCIFTXI3_IRQn, 3);
|
---|
| 558 | }
|
---|
| 559 | static void uart4_tx_irq(void) {
|
---|
| 560 | uart_tx_irq(SCIFTXI4_IRQn, 4);
|
---|
| 561 | }
|
---|
| 562 | static void uart5_tx_irq(void) {
|
---|
| 563 | uart_tx_irq(SCIFTXI5_IRQn, 5);
|
---|
| 564 | }
|
---|
| 565 | static void uart6_tx_irq(void) {
|
---|
| 566 | uart_tx_irq(SCIFTXI6_IRQn, 6);
|
---|
| 567 | }
|
---|
| 568 | static void uart7_tx_irq(void) {
|
---|
| 569 | uart_tx_irq(SCIFTXI7_IRQn, 7);
|
---|
| 570 | }
|
---|
| 571 | /* RX handler */
|
---|
| 572 | static void uart0_rx_irq(void) {
|
---|
| 573 | uart_rx_irq(SCIFRXI0_IRQn, 0);
|
---|
| 574 | }
|
---|
| 575 | static void uart1_rx_irq(void) {
|
---|
| 576 | uart_rx_irq(SCIFRXI1_IRQn, 1);
|
---|
| 577 | }
|
---|
| 578 | static void uart2_rx_irq(void) {
|
---|
| 579 | uart_rx_irq(SCIFRXI2_IRQn, 2);
|
---|
| 580 | }
|
---|
| 581 | static void uart3_rx_irq(void) {
|
---|
| 582 | uart_rx_irq(SCIFRXI3_IRQn, 3);
|
---|
| 583 | }
|
---|
| 584 | static void uart4_rx_irq(void) {
|
---|
| 585 | uart_rx_irq(SCIFRXI4_IRQn, 4);
|
---|
| 586 | }
|
---|
| 587 | static void uart5_rx_irq(void) {
|
---|
| 588 | uart_rx_irq(SCIFRXI5_IRQn, 5);
|
---|
| 589 | }
|
---|
| 590 | static void uart6_rx_irq(void) {
|
---|
| 591 | uart_rx_irq(SCIFRXI6_IRQn, 6);
|
---|
| 592 | }
|
---|
| 593 | static void uart7_rx_irq(void) {
|
---|
| 594 | uart_rx_irq(SCIFRXI7_IRQn, 7);
|
---|
| 595 | }
|
---|
| 596 | /* Error handler */
|
---|
| 597 | static void uart0_er_irq(void)
|
---|
| 598 | {
|
---|
| 599 | uart_err_irq(SCIFERI0_IRQn, 0);
|
---|
| 600 | }
|
---|
| 601 | static void uart1_er_irq(void)
|
---|
| 602 | {
|
---|
| 603 | uart_err_irq(SCIFERI0_IRQn, 1);
|
---|
| 604 | }
|
---|
| 605 | static void uart2_er_irq(void)
|
---|
| 606 | {
|
---|
| 607 | uart_err_irq(SCIFERI0_IRQn, 2);
|
---|
| 608 | }
|
---|
| 609 | static void uart3_er_irq(void)
|
---|
| 610 | {
|
---|
| 611 | uart_err_irq(SCIFERI0_IRQn, 3);
|
---|
| 612 | }
|
---|
| 613 | static void uart4_er_irq(void)
|
---|
| 614 | {
|
---|
| 615 | uart_err_irq(SCIFERI0_IRQn, 4);
|
---|
| 616 | }
|
---|
| 617 | static void uart5_er_irq(void)
|
---|
| 618 | {
|
---|
| 619 | uart_err_irq(SCIFERI0_IRQn, 5);
|
---|
| 620 | }
|
---|
| 621 | static void uart6_er_irq(void)
|
---|
| 622 | {
|
---|
| 623 | uart_err_irq(SCIFERI0_IRQn, 6);
|
---|
| 624 | }
|
---|
| 625 | static void uart7_er_irq(void)
|
---|
| 626 | {
|
---|
| 627 | uart_err_irq(SCIFERI0_IRQn, 7);
|
---|
| 628 | }
|
---|
| 629 |
|
---|
| 630 | void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
|
---|
| 631 | irq_handler = handler;
|
---|
| 632 | uart_data[obj->serial.index].serial_irq_id = id;
|
---|
| 633 | }
|
---|
| 634 |
|
---|
| 635 | static void serial_irq_set_irq(IRQn_Type IRQn, IRQHandler handler, uint32_t enable)
|
---|
| 636 | {
|
---|
| 637 | if (enable) {
|
---|
| 638 | InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler);
|
---|
| 639 | GIC_SetPriority(IRQn, 5);
|
---|
| 640 | GIC_EnableIRQ(IRQn);
|
---|
| 641 | } else {
|
---|
| 642 | GIC_DisableIRQ(IRQn);
|
---|
| 643 | }
|
---|
| 644 | }
|
---|
| 645 |
|
---|
| 646 | static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) {
|
---|
| 647 | IRQn_Type IRQn;
|
---|
| 648 | IRQHandler handler;
|
---|
| 649 |
|
---|
| 650 | IRQn = irq_set_tbl[obj->serial.index][irq];
|
---|
| 651 | handler = hander_set_tbl[obj->serial.index][irq];
|
---|
| 652 |
|
---|
| 653 | if ((obj->serial.index >= 0) && (obj->serial.index <= 7)) {
|
---|
| 654 | serial_irq_set_irq(IRQn, handler, enable);
|
---|
| 655 | }
|
---|
| 656 | }
|
---|
| 657 |
|
---|
| 658 | static void serial_irq_err_set(serial_t *obj, uint32_t enable)
|
---|
| 659 | {
|
---|
| 660 | serial_irq_set_irq(irq_set_tbl[obj->serial.index][2], hander_set_tbl[obj->serial.index][2], enable);
|
---|
| 661 | serial_irq_set_irq(irq_set_tbl[obj->serial.index][3], hander_set_tbl[obj->serial.index][3], enable);
|
---|
| 662 | }
|
---|
| 663 |
|
---|
| 664 | void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
|
---|
| 665 | if (RxIrq == irq) {
|
---|
| 666 | uart_data[obj->serial.index].rx_irq_set_api = enable;
|
---|
| 667 | }
|
---|
| 668 | serial_irq_set_internal(obj, irq, enable);
|
---|
| 669 | }
|
---|
| 670 |
|
---|
| 671 | static void serial_flow_irq_set(serial_t *obj, uint32_t enable) {
|
---|
| 672 | uart_data[obj->serial.index].rx_irq_set_flow = enable;
|
---|
| 673 | serial_irq_set_internal(obj, RxIrq, enable);
|
---|
| 674 | }
|
---|
| 675 |
|
---|
| 676 | /******************************************************************************
|
---|
| 677 | * READ/WRITE
|
---|
| 678 | ******************************************************************************/
|
---|
| 679 | int serial_getc(serial_t *obj) {
|
---|
| 680 | uint16_t err_read;
|
---|
| 681 | int data;
|
---|
| 682 | int was_masked;
|
---|
| 683 |
|
---|
| 684 | #if defined ( __ICCARM__ )
|
---|
| 685 | was_masked = __disable_irq_iar();
|
---|
| 686 | #else
|
---|
| 687 | was_masked = __disable_irq();
|
---|
| 688 | #endif /* __ICCARM__ */
|
---|
| 689 | if (obj->serial.uart->SCFSR & 0x93) {
|
---|
| 690 | err_read = obj->serial.uart->SCFSR;
|
---|
| 691 | obj->serial.uart->SCFSR = (err_read & ~0x93);
|
---|
| 692 | }
|
---|
| 693 | obj->serial.uart->SCSCR |= 0x0040; // Set RIE
|
---|
| 694 | if (!was_masked) {
|
---|
| 695 | __enable_irq();
|
---|
| 696 | }
|
---|
| 697 |
|
---|
| 698 | if (obj->serial.uart->SCLSR & 0x0001) {
|
---|
| 699 | obj->serial.uart->SCLSR = 0u; // ORER clear
|
---|
| 700 | }
|
---|
| 701 |
|
---|
| 702 | while (!serial_readable(obj));
|
---|
| 703 | data = obj->serial.uart->SCFRDR & 0xff;
|
---|
| 704 |
|
---|
| 705 | #if defined ( __ICCARM__ )
|
---|
| 706 | was_masked = __disable_irq_iar();
|
---|
| 707 | #else
|
---|
| 708 | was_masked = __disable_irq();
|
---|
| 709 | #endif /* __ICCARM__ */
|
---|
| 710 | err_read = obj->serial.uart->SCFSR;
|
---|
| 711 | obj->serial.uart->SCFSR = (err_read & 0xfffD); // Clear RDF
|
---|
| 712 | if (!was_masked) {
|
---|
| 713 | __enable_irq();
|
---|
| 714 | }
|
---|
| 715 |
|
---|
| 716 | if (err_read & 0x80) {
|
---|
| 717 | data = -1; //err
|
---|
| 718 | }
|
---|
| 719 | return data;
|
---|
| 720 | }
|
---|
| 721 |
|
---|
| 722 | void serial_putc(serial_t *obj, int c) {
|
---|
| 723 | while (!serial_writable(obj));
|
---|
| 724 | obj->serial.uart->SCFTDR = c;
|
---|
| 725 | serial_put_done(obj);
|
---|
| 726 | }
|
---|
| 727 |
|
---|
| 728 | static void serial_put_done(serial_t *obj)
|
---|
| 729 | {
|
---|
| 730 | int was_masked;
|
---|
| 731 | volatile uint16_t dummy_read;
|
---|
| 732 |
|
---|
| 733 | #if defined ( __ICCARM__ )
|
---|
| 734 | was_masked = __disable_irq_iar();
|
---|
| 735 | #else
|
---|
| 736 | was_masked = __disable_irq();
|
---|
| 737 | #endif /* __ICCARM__ */
|
---|
| 738 | dummy_read = obj->serial.uart->SCFSR;
|
---|
| 739 | obj->serial.uart->SCFSR = (dummy_read & 0xff9f); // Clear TEND/TDFE
|
---|
| 740 | obj->serial.uart->SCSCR |= 0x0080; // Set TIE
|
---|
| 741 | if (!was_masked) {
|
---|
| 742 | __enable_irq();
|
---|
| 743 | }
|
---|
| 744 | }
|
---|
| 745 |
|
---|
| 746 | int serial_readable(serial_t *obj) {
|
---|
| 747 | return ((obj->serial.uart->SCFSR & 0x02) != 0); // RDF
|
---|
| 748 | }
|
---|
| 749 |
|
---|
| 750 | int serial_writable(serial_t *obj) {
|
---|
| 751 | return ((obj->serial.uart->SCFSR & 0x20) != 0); // TDFE
|
---|
| 752 | }
|
---|
| 753 |
|
---|
| 754 | void serial_clear(serial_t *obj) {
|
---|
| 755 | int was_masked;
|
---|
| 756 | #if defined ( __ICCARM__ )
|
---|
| 757 | was_masked = __disable_irq_iar();
|
---|
| 758 | #else
|
---|
| 759 | was_masked = __disable_irq();
|
---|
| 760 | #endif /* __ICCARM__ */
|
---|
| 761 |
|
---|
| 762 | obj->serial.uart->SCFCR |= 0x06; // TFRST = 1, RFRST = 1
|
---|
| 763 | obj->serial.uart->SCFCR &= ~0x06; // TFRST = 0, RFRST = 0
|
---|
| 764 | obj->serial.uart->SCFSR &= ~0x0093u; // ER, BRK, RDF, DR = 0
|
---|
| 765 |
|
---|
| 766 | if (!was_masked) {
|
---|
| 767 | __enable_irq();
|
---|
| 768 | }
|
---|
| 769 | }
|
---|
| 770 |
|
---|
| 771 | void serial_pinout_tx(PinName tx) {
|
---|
| 772 | pinmap_pinout(tx, PinMap_UART_TX);
|
---|
| 773 | }
|
---|
| 774 |
|
---|
| 775 | void serial_break_set(serial_t *obj) {
|
---|
| 776 | int was_masked;
|
---|
| 777 | #if defined ( __ICCARM__ )
|
---|
| 778 | was_masked = __disable_irq_iar();
|
---|
| 779 | #else
|
---|
| 780 | was_masked = __disable_irq();
|
---|
| 781 | #endif /* __ICCARM__ */
|
---|
| 782 | // TxD Output(L)
|
---|
| 783 | obj->serial.uart->SCSPTR &= ~0x0001u; // SPB2DT = 0
|
---|
| 784 | obj->serial.uart->SCSCR &= ~0x0020u; // TE = 0 (Output disable)
|
---|
| 785 | if (!was_masked) {
|
---|
| 786 | __enable_irq();
|
---|
| 787 | }
|
---|
| 788 | }
|
---|
| 789 |
|
---|
| 790 | void serial_break_clear(serial_t *obj) {
|
---|
| 791 | int was_masked;
|
---|
| 792 | #if defined ( __ICCARM__ )
|
---|
| 793 | was_masked = __disable_irq_iar();
|
---|
| 794 | #else
|
---|
| 795 | was_masked = __disable_irq();
|
---|
| 796 | #endif /* __ICCARM__ */
|
---|
| 797 | obj->serial.uart->SCSCR |= 0x0020u; // TE = 1 (Output enable)
|
---|
| 798 | obj->serial.uart->SCSPTR |= 0x0001u; // SPB2DT = 1
|
---|
| 799 | if (!was_masked) {
|
---|
| 800 | __enable_irq();
|
---|
| 801 | }
|
---|
| 802 | }
|
---|
| 803 |
|
---|
| 804 | void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
|
---|
| 805 | // determine the UART to use
|
---|
| 806 | int was_masked;
|
---|
| 807 |
|
---|
| 808 | serial_flow_irq_set(obj, 0);
|
---|
| 809 |
|
---|
| 810 | if (type == FlowControlRTSCTS) {
|
---|
| 811 | #if defined ( __ICCARM__ )
|
---|
| 812 | was_masked = __disable_irq_iar();
|
---|
| 813 | #else
|
---|
| 814 | was_masked = __disable_irq();
|
---|
| 815 | #endif /* __ICCARM__ */
|
---|
| 816 | obj->serial.uart->SCFCR = 0x0008u; // CTS/RTS enable
|
---|
| 817 | if (!was_masked) {
|
---|
| 818 | __enable_irq();
|
---|
| 819 | }
|
---|
| 820 | pinmap_pinout(rxflow, PinMap_UART_RTS);
|
---|
| 821 | pinmap_pinout(txflow, PinMap_UART_CTS);
|
---|
| 822 | } else {
|
---|
| 823 | #if defined ( __ICCARM__ )
|
---|
| 824 | was_masked = __disable_irq_iar();
|
---|
| 825 | #else
|
---|
| 826 | was_masked = __disable_irq();
|
---|
| 827 | #endif /* __ICCARM__ */
|
---|
| 828 | obj->serial.uart->SCFCR = 0x0000u; // CTS/RTS diable
|
---|
| 829 | if (!was_masked) {
|
---|
| 830 | __enable_irq();
|
---|
| 831 | }
|
---|
| 832 | }
|
---|
| 833 | }
|
---|
| 834 |
|
---|
| 835 | static uint8_t serial_available_buffer(serial_t *obj)
|
---|
| 836 | {
|
---|
| 837 | return 1;
|
---|
| 838 | /* Faster but unstable way */
|
---|
| 839 | /*
|
---|
| 840 | uint16_t ret = 16 - ((obj->serial.uart->SCFDR >> 8) & 0x1F);
|
---|
| 841 | while (ret == 0) {
|
---|
| 842 | ret = 16 - ((obj->serial.uart->SCFDR >> 8) & 0x1F);
|
---|
| 843 | }
|
---|
| 844 | MBED_ASSERT(0 < ret && ret <= 16);
|
---|
| 845 | return ret;
|
---|
| 846 | */
|
---|
| 847 | }
|
---|
| 848 |
|
---|
| 849 | #if DEVICE_SERIAL_ASYNCH
|
---|
| 850 |
|
---|
| 851 | /******************************************************************************
|
---|
| 852 | * ASYNCHRONOUS HAL
|
---|
| 853 | ******************************************************************************/
|
---|
| 854 |
|
---|
| 855 | int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
|
---|
| 856 | {
|
---|
| 857 | int i;
|
---|
| 858 | buffer_t *buf = &obj->tx_buff;
|
---|
| 859 | struct serial_global_data_s *data = uart_data + obj->serial.index;
|
---|
| 860 |
|
---|
| 861 | if (tx_length == 0) {
|
---|
| 862 | return 0;
|
---|
| 863 | }
|
---|
| 864 |
|
---|
| 865 | buf->buffer = (void *)tx;
|
---|
| 866 | buf->length = tx_length * tx_width / 8;
|
---|
| 867 | buf->pos = 0;
|
---|
| 868 | buf->width = tx_width;
|
---|
| 869 | data->tranferring_obj = obj;
|
---|
| 870 | data->async_tx_callback = handler;
|
---|
| 871 | serial_irq_set(obj, TxIrq, 1);
|
---|
| 872 |
|
---|
| 873 | while (!serial_writable(obj));
|
---|
| 874 | i = buf->length;
|
---|
| 875 | if (serial_available_buffer(obj) < i) {
|
---|
| 876 | i = serial_available_buffer(obj);
|
---|
| 877 | }
|
---|
| 878 | do {
|
---|
| 879 | uint8_t c = *(uint8_t *)buf->buffer;
|
---|
| 880 | obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + 1;
|
---|
| 881 | ++buf->pos;
|
---|
| 882 | obj->serial.uart->SCFTDR = c;
|
---|
| 883 | } while (--i);
|
---|
| 884 | serial_put_done(obj);
|
---|
| 885 |
|
---|
| 886 | return buf->length;
|
---|
| 887 | }
|
---|
| 888 |
|
---|
| 889 | void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
|
---|
| 890 | {
|
---|
| 891 | buffer_t *buf = &obj->rx_buff;
|
---|
| 892 | struct serial_global_data_s *data = uart_data + obj->serial.index;
|
---|
| 893 |
|
---|
| 894 | if (rx_length == 0) {
|
---|
| 895 | return;
|
---|
| 896 | }
|
---|
| 897 |
|
---|
| 898 | buf->buffer = rx;
|
---|
| 899 | buf->length = rx_length * rx_width / 8;
|
---|
| 900 | buf->pos = 0;
|
---|
| 901 | buf->width = rx_width;
|
---|
| 902 | obj->char_match = char_match;
|
---|
| 903 | obj->char_found = 0;
|
---|
| 904 | data->receiving_obj = obj;
|
---|
| 905 | data->async_rx_callback = handler;
|
---|
| 906 | data->event = 0;
|
---|
| 907 | data->wanted_rx_events = event;
|
---|
| 908 |
|
---|
| 909 | serial_irq_set(obj, RxIrq, 1);
|
---|
| 910 | serial_irq_err_set(obj, 1);
|
---|
| 911 | }
|
---|
| 912 |
|
---|
| 913 | uint8_t serial_tx_active(serial_t *obj)
|
---|
| 914 | {
|
---|
| 915 | return uart_data[obj->serial.index].tranferring_obj != NULL;
|
---|
| 916 | }
|
---|
| 917 |
|
---|
| 918 | uint8_t serial_rx_active(serial_t *obj)
|
---|
| 919 | {
|
---|
| 920 | return uart_data[obj->serial.index].receiving_obj != NULL;
|
---|
| 921 | }
|
---|
| 922 |
|
---|
| 923 | int serial_irq_handler_asynch(serial_t *obj)
|
---|
| 924 | {
|
---|
| 925 | return uart_data[obj->serial.index].event;
|
---|
| 926 | }
|
---|
| 927 |
|
---|
| 928 | void serial_tx_abort_asynch(serial_t *obj)
|
---|
| 929 | {
|
---|
| 930 | uart_data[obj->serial.index].tranferring_obj = NULL;
|
---|
| 931 | obj->serial.uart->SCFCR |= 1 << 2;
|
---|
| 932 | obj->serial.uart->SCFCR &= ~(1 << 2);
|
---|
| 933 | }
|
---|
| 934 |
|
---|
| 935 | void serial_rx_abort_asynch(serial_t *obj)
|
---|
| 936 | {
|
---|
| 937 | uart_data[obj->serial.index].receiving_obj = NULL;
|
---|
| 938 | obj->serial.uart->SCFCR |= 1 << 1;
|
---|
| 939 | obj->serial.uart->SCFCR &= ~(1 << 1);
|
---|
| 940 | }
|
---|
| 941 |
|
---|
| 942 | #endif
|
---|