1 | /* mbed Microcontroller Library
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2 | * Copyright (c) 2006-2015 ARM Limited
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3 | *
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4 | * Licensed under the Apache License, Version 2.0 (the "License");
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5 | * you may not use this file except in compliance with the License.
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6 | * You may obtain a copy of the License at
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7 | *
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8 | * http://www.apache.org/licenses/LICENSE-2.0
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9 | *
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10 | * Unless required by applicable law or agreed to in writing, software
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11 | * distributed under the License is distributed on an "AS IS" BASIS,
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12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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13 | * See the License for the specific language governing permissions and
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14 | * limitations under the License.
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15 | */
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16 | // math.h required for floating point operations for baud rate calculation
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17 | #include "mbed_assert.h"
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18 | #include <math.h>
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19 | #include <string.h>
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20 | #include <stdlib.h>
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21 |
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22 | #include "serial_api.h"
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23 | #include "cmsis.h"
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24 | #include "PeripheralPins.h"
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25 | #include "gpio_api.h"
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26 | #include "RZ_A1_Init.h"
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27 |
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28 | #include "iodefine.h"
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29 | #include "mbed_drv_cfg.h"
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30 | #include "mbed_critical.h"
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31 |
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32 | /******************************************************************************
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33 | * INITIALIZATION
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34 | ******************************************************************************/
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35 | #if defined(TARGET_RZA1H)
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36 | #define UART_NUM 8
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37 | #else
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38 | #define UART_NUM 5
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39 | #endif
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40 | #define IRQ_NUM 4
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41 |
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42 | static void uart0_tx_irq(void);
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43 | static void uart0_rx_irq(void);
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44 | static void uart0_er_irq(void);
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45 | static void uart1_tx_irq(void);
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46 | static void uart1_rx_irq(void);
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47 | static void uart1_er_irq(void);
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48 | static void uart2_tx_irq(void);
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49 | static void uart2_rx_irq(void);
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50 | static void uart2_er_irq(void);
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51 | static void uart3_tx_irq(void);
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52 | static void uart3_rx_irq(void);
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53 | static void uart3_er_irq(void);
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54 | static void uart4_tx_irq(void);
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55 | static void uart4_rx_irq(void);
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56 | static void uart4_er_irq(void);
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57 | #if defined(TARGET_RZA1H)
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58 | static void uart5_tx_irq(void);
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59 | static void uart5_rx_irq(void);
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60 | static void uart5_er_irq(void);
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61 | static void uart6_tx_irq(void);
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62 | static void uart6_rx_irq(void);
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63 | static void uart6_er_irq(void);
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64 | static void uart7_tx_irq(void);
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65 | static void uart7_rx_irq(void);
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66 | static void uart7_er_irq(void);
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67 | #endif
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68 |
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69 | static void serial_put_done(serial_t *obj);
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70 | static uint8_t serial_available_buffer(serial_t *obj);
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71 | static void serial_irq_err_set(serial_t *obj, uint32_t enable);
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72 |
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73 | static const struct st_scif *SCIF[] = SCIF_ADDRESS_LIST;
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74 | //static uart_irq_handler irq_handler;
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75 |
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76 | int stdio_uart_inited = 0;
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77 | serial_t stdio_uart;
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78 |
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79 | struct serial_global_data_s {
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80 | /*add*/uart_irq_handler irq_handler;
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81 | uint32_t serial_irq_id;
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82 | gpio_t sw_rts, sw_cts;
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83 | serial_t *tranferring_obj, *receiving_obj;
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84 | uint32_t async_tx_callback, async_rx_callback;
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85 | int event, wanted_rx_events;
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86 | };
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87 |
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88 | static struct serial_global_data_s uart_data[UART_NUM];
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89 |
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90 | static const IRQn_Type irq_set_tbl[UART_NUM][IRQ_NUM] = {
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91 | {SCIFRXI0_IRQn, SCIFTXI0_IRQn, SCIFBRI0_IRQn, SCIFERI0_IRQn},
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92 | {SCIFRXI1_IRQn, SCIFTXI1_IRQn, SCIFBRI1_IRQn, SCIFERI1_IRQn},
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93 | {SCIFRXI2_IRQn, SCIFTXI2_IRQn, SCIFBRI2_IRQn, SCIFERI2_IRQn},
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94 | {SCIFRXI3_IRQn, SCIFTXI3_IRQn, SCIFBRI3_IRQn, SCIFERI3_IRQn},
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95 | {SCIFRXI4_IRQn, SCIFTXI4_IRQn, SCIFBRI4_IRQn, SCIFERI4_IRQn},
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96 | #if defined(TARGET_RZA1H)
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97 | {SCIFRXI5_IRQn, SCIFTXI5_IRQn, SCIFBRI5_IRQn, SCIFERI5_IRQn},
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98 | {SCIFRXI6_IRQn, SCIFTXI6_IRQn, SCIFBRI6_IRQn, SCIFERI6_IRQn},
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99 | {SCIFRXI7_IRQn, SCIFTXI7_IRQn, SCIFBRI7_IRQn, SCIFERI7_IRQn},
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100 | #endif
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101 | };
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102 |
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103 | static const IRQHandler hander_set_tbl[UART_NUM][IRQ_NUM] = {
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104 | {uart0_rx_irq, uart0_tx_irq, uart0_er_irq, uart0_er_irq},
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105 | {uart1_rx_irq, uart1_tx_irq, uart1_er_irq, uart1_er_irq},
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106 | {uart2_rx_irq, uart2_tx_irq, uart2_er_irq, uart2_er_irq},
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107 | {uart3_rx_irq, uart3_tx_irq, uart3_er_irq, uart3_er_irq},
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108 | {uart4_rx_irq, uart4_tx_irq, uart4_er_irq, uart4_er_irq},
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109 | #if defined(TARGET_RZA1H)
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110 | {uart5_rx_irq, uart5_tx_irq, uart5_er_irq, uart5_er_irq},
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111 | {uart6_rx_irq, uart6_tx_irq, uart6_er_irq, uart6_er_irq},
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112 | {uart7_rx_irq, uart7_tx_irq, uart7_er_irq, uart7_er_irq},
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113 | #endif
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114 | };
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115 |
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116 | static __IO uint16_t *SCSCR_MATCH[] = {
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117 | &SCSCR_0,
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118 | &SCSCR_1,
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119 | &SCSCR_2,
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120 | &SCSCR_3,
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121 | &SCSCR_4,
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122 | #if defined(TARGET_RZA1H)
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123 | &SCSCR_5,
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124 | &SCSCR_6,
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125 | &SCSCR_7,
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126 | #endif
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127 | };
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128 |
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129 | static __IO uint16_t *SCFSR_MATCH[] = {
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130 | &SCFSR_0,
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131 | &SCFSR_1,
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132 | &SCFSR_2,
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133 | &SCFSR_3,
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134 | &SCFSR_4,
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135 | #if defined(TARGET_RZA1H)
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136 | &SCFSR_5,
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137 | &SCFSR_6,
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138 | &SCFSR_7,
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139 | #endif
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140 | };
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141 |
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142 |
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143 | void serial_init(serial_t *obj, PinName tx, PinName rx) {
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144 | volatile uint8_t dummy ;
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145 | int is_stdio_uart = 0;
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146 | // determine the UART to use
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147 | uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
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148 | uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
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149 | uint32_t uart = pinmap_merge(uart_tx, uart_rx);
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150 |
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151 | MBED_ASSERT((int)uart != NC);
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152 |
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153 | obj->serial.uart = (struct st_scif *)SCIF[uart];
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154 | // enable power
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155 | CPG.STBCR4 &= ~(1 << (7 - uart));
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156 | dummy = CPG.STBCR4;
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157 |
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158 | /* ==== SCIF initial setting ==== */
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159 | /* ---- Serial control register (SCSCR) setting ---- */
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160 | /* B'00 : Internal CLK */
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161 | obj->serial.uart->SCSCR = 0x0000u; /* SCIF transmitting and receiving operations stop */
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162 |
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163 | /* ---- FIFO control register (SCFCR) setting ---- */
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164 | /* Transmit FIFO reset & Receive FIFO data register reset */
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165 | obj->serial.uart->SCFCR = 0x0006u;
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166 |
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167 | /* ---- Serial status register (SCFSR) setting ---- */
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168 | dummy = obj->serial.uart->SCFSR;
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169 | obj->serial.uart->SCFSR = (dummy & 0xFF6Cu); /* ER,BRK,DR bit clear */
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170 |
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171 | /* ---- Line status register (SCLSR) setting ---- */
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172 | /* ORER bit clear */
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173 | obj->serial.uart->SCLSR = 0;
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174 |
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175 | /* ---- Serial extension mode register (SCEMR) setting ----
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176 | b7 BGDM - Baud rate generator double-speed mode : Normal mode
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177 | b0 ABCS - Base clock select in asynchronous mode : Base clock is 16 times the bit rate */
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178 | obj->serial.uart->SCEMR = 0x0000u;
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179 |
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180 | /* ---- Bit rate register (SCBRR) setting ---- */
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181 | serial_baud (obj, 9600);
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182 | serial_format(obj, 8, ParityNone, 1);
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183 |
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184 | /* ---- FIFO control register (SCFCR) setting ---- */
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185 | obj->serial.uart->SCFCR = 0x0030u;
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186 |
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187 | /* ---- Serial port register (SCSPTR) setting ----
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188 | b1 SPB2IO - Serial port break output : disabled
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189 | b0 SPB2DT - Serial port break data : High-level */
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190 | obj->serial.uart->SCSPTR = 0x0003u; // SPB2IO = 1, SPB2DT = 1
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191 |
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192 | /* ---- Line status register (SCLSR) setting ----
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193 | b0 ORER - Overrun error detect : clear */
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194 |
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195 | if (obj->serial.uart->SCLSR & 0x0001) {
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196 | obj->serial.uart->SCLSR = 0u; // ORER clear
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197 | }
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198 |
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199 | // pinout the chosen uart
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200 | pinmap_pinout(tx, PinMap_UART_TX);
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201 | pinmap_pinout(rx, PinMap_UART_RX);
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202 |
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203 | obj->serial.index = uart;
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204 |
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205 | uart_data[obj->serial.index].sw_rts.pin = NC;
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206 | uart_data[obj->serial.index].sw_cts.pin = NC;
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207 |
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208 | /* ---- Serial control register (SCSCR) setting ---- */
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209 | /* Setting the TE and RE bits enables the TxD and RxD pins to be used. */
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210 | obj->serial.uart->SCSCR = 0x0070;
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211 |
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212 | is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
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213 |
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214 | if (is_stdio_uart) {
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215 | stdio_uart_inited = 1;
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216 | memcpy(&stdio_uart, obj, sizeof(serial_t));
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217 | }
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218 | }
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219 |
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220 | void serial_free(serial_t *obj) {
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221 | uart_data[obj->serial.index].serial_irq_id = 0;
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222 | }
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223 |
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224 | // serial_baud
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225 | // set the baud rate, taking in to account the current SystemFrequency
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226 | void serial_baud(serial_t *obj, int baudrate) {
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227 | uint32_t pclk_base;
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228 | uint32_t bgdm = 1;
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229 | uint32_t cks = 0;
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230 | uint32_t DL;
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231 |
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232 | if (RZ_A1_IsClockMode0() == false) {
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233 | pclk_base = CM1_RENESAS_RZ_A1_P1_CLK;
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234 | } else {
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235 | pclk_base = CM0_RENESAS_RZ_A1_P1_CLK;
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236 | }
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237 |
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238 | if (baudrate > (int)(pclk_base / 0x800)) {
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239 | obj->serial.uart->SCSMR &= ~0x0003;
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240 | obj->serial.uart->SCEMR = 0x0081; // BGDM = 1, ABCS = 1
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241 | DL = (pclk_base + (4 * baudrate)) / (8 * baudrate); // Rounding
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242 | if (DL > 0) {
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243 | DL--;
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244 | }
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245 | obj->serial.uart->SCBRR = (uint8_t)DL;
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246 | } else if (baudrate < (int)(pclk_base / 0x80000)) {
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247 | obj->serial.uart->SCSMR |= 0x0003;
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248 | obj->serial.uart->SCEMR = 0x0000;
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249 | obj->serial.uart->SCBRR = 0xFFu;
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250 | } else {
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251 | DL = (pclk_base + (8 * baudrate)) / (16 * baudrate); // Rounding
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252 | while (DL > 256) {
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253 | DL >>= 1;
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254 | if (bgdm == 1) {
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255 | bgdm = 0;
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256 | } else {
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257 | bgdm = 1;
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258 | cks++;
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259 | }
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260 | }
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261 | obj->serial.uart->SCSMR = (obj->serial.uart->SCSMR & ~0x0003) | (uint8_t)cks;
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262 | obj->serial.uart->SCEMR = (uint8_t)(bgdm << 7);
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263 | obj->serial.uart->SCBRR = (uint8_t)(DL - 1);
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264 | }
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265 | }
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266 |
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267 | void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
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268 | int parity_enable;
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269 | int parity_select;
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270 |
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271 | MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
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272 | MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 5: 5 data bits ... 3: 8 data bits
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273 | MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
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274 | (parity == ParityForced1) || (parity == ParityForced0));
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275 |
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276 | stop_bits = (stop_bits == 1)? 0:
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277 | (stop_bits == 2)? 1:
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278 | 0; // must not to be
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279 |
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280 | data_bits = (data_bits == 8)? 0:
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281 | (data_bits == 7)? 1:
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282 | 0; // must not to be
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283 |
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284 | switch (parity) {
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285 | case ParityNone:
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286 | parity_enable = 0;
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287 | parity_select = 0;
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288 | break;
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289 | case ParityOdd:
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290 | parity_enable = 1;
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291 | parity_select = 1;
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292 | break;
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293 | case ParityEven:
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294 | parity_enable = 1;
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295 | parity_select = 0;
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296 | break;
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297 | case ParityForced1:
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298 | case ParityForced0:
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299 | default:
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300 | parity_enable = 0;
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301 | parity_select = 0;
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302 | break;
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303 | }
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304 |
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305 | obj->serial.uart->SCSMR = data_bits << 6
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306 | | parity_enable << 5
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307 | | parity_select << 4
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308 | | stop_bits << 3;
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309 | }
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310 |
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311 | /******************************************************************************
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312 | * INTERRUPTS HANDLING
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313 | ******************************************************************************/
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314 |
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315 | static void uart_tx_irq(IRQn_Type irq_num, uint32_t index) {
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316 | __IO uint16_t *dmy_rd_scscr;
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317 | __IO uint16_t *dmy_rd_scfsr;
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318 | serial_t *obj;
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319 | int i;
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320 |
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321 | dmy_rd_scscr = SCSCR_MATCH[index];
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322 | *dmy_rd_scscr &= 0x007B; // Clear TIE and Write to bit15~8,2 is always 0
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323 | dmy_rd_scfsr = SCFSR_MATCH[index];
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324 | *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0020); // Set TEND
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325 |
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326 | obj = uart_data[index].tranferring_obj;
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327 | if (obj) {
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328 | i = obj->tx_buff.length - obj->tx_buff.pos;
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329 | if (0 < i) {
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330 | if (serial_available_buffer(obj) < i) {
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331 | i = serial_available_buffer(obj);
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332 | }
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333 | do {
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334 | uint8_t c = *(uint8_t *)obj->tx_buff.buffer;
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335 | obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + 1;
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336 | ++obj->tx_buff.pos;
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337 | obj->serial.uart->SCFTDR = c;
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338 | } while (--i);
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339 | serial_put_done(obj);
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340 | } else {
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341 | uart_data[index].tranferring_obj = NULL;
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342 | uart_data[index].event = SERIAL_EVENT_TX_COMPLETE;
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343 | ((void (*)())uart_data[index].async_tx_callback)();
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344 | }
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345 | }
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346 |
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347 | if (uart_data[index].irq_handler != NULL)
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348 | uart_data[index].irq_handler(uart_data[index].serial_irq_id, TxIrq);
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349 | }
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350 |
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351 | static void uart_rx_irq(IRQn_Type irq_num, uint32_t index) {
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352 | __IO uint16_t *dmy_rd_scscr;
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353 | __IO uint16_t *dmy_rd_scfsr;
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354 | serial_t *obj;
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355 | int c;
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356 |
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357 | dmy_rd_scscr = SCSCR_MATCH[index];
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358 | *dmy_rd_scscr &= 0x00B3; // Clear RIE,REIE and Write to bit15~8,2 is always 0
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359 | dmy_rd_scfsr = SCFSR_MATCH[index];
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360 | *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0003); // Clear RDF,DR
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361 |
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362 | obj = uart_data[index].receiving_obj;
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363 | if (obj) {
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364 | if (obj->serial.uart->SCLSR & 1) {
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365 | if (uart_data[index].wanted_rx_events & SERIAL_EVENT_RX_OVERRUN_ERROR) {
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366 | serial_rx_abort_asynch(obj);
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367 | uart_data[index].event = SERIAL_EVENT_RX_OVERRUN_ERROR;
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368 | ((void (*)())uart_data[index].async_rx_callback)();
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369 | }
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370 | return;
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371 | }
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372 | c = serial_getc(obj);
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373 | if (c != -1) {
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374 | ((uint8_t *)obj->rx_buff.buffer)[obj->rx_buff.pos] = c;
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375 | ++obj->rx_buff.pos;
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376 | if (c == obj->char_match && ! obj->char_found) {
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377 | obj->char_found = 1;
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378 | if (obj->rx_buff.pos == obj->rx_buff.length) {
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379 | if (uart_data[index].wanted_rx_events & SERIAL_EVENT_RX_COMPLETE) {
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380 | uart_data[index].event = SERIAL_EVENT_RX_COMPLETE;
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381 | }
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382 | }
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383 | if (uart_data[index].wanted_rx_events & SERIAL_EVENT_RX_CHARACTER_MATCH) {
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384 | uart_data[index].event |= SERIAL_EVENT_RX_CHARACTER_MATCH;
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385 | }
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386 | if (uart_data[index].event) {
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387 | uart_data[index].receiving_obj = NULL;
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388 | ((void (*)())uart_data[index].async_rx_callback)();
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389 | }
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390 | } else if (obj->rx_buff.pos == obj->rx_buff.length) {
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391 | uart_data[index].receiving_obj = NULL;
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392 | if (uart_data[index].wanted_rx_events & SERIAL_EVENT_RX_COMPLETE) {
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393 | uart_data[index].event = SERIAL_EVENT_RX_COMPLETE;
|
---|
394 | ((void (*)())uart_data[index].async_rx_callback)();
|
---|
395 | }
|
---|
396 | }
|
---|
397 | } else {
|
---|
398 | serial_rx_abort_asynch(obj);
|
---|
399 | if (uart_data[index].wanted_rx_events & (SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR)) {
|
---|
400 | uart_data[index].event = SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR;
|
---|
401 | if (obj->serial.uart->SCFSR & 1 << 2) {
|
---|
402 | uart_data[index].event = SERIAL_EVENT_RX_PARITY_ERROR;
|
---|
403 | } else if (obj->serial.uart->SCFSR & 1 << 3) {
|
---|
404 | uart_data[index].event = SERIAL_EVENT_RX_FRAMING_ERROR;
|
---|
405 | }
|
---|
406 | ((void (*)())uart_data[index].async_rx_callback)();
|
---|
407 | }
|
---|
408 | return;
|
---|
409 | }
|
---|
410 | }
|
---|
411 |
|
---|
412 | if (uart_data[index].irq_handler != NULL)
|
---|
413 | uart_data[index].irq_handler(uart_data[index].serial_irq_id, RxIrq);
|
---|
414 | }
|
---|
415 |
|
---|
416 | static void uart_err_irq(IRQn_Type irq_num, uint32_t index) {
|
---|
417 | serial_t *obj = uart_data[index].receiving_obj;
|
---|
418 | int err_read;
|
---|
419 |
|
---|
420 | if (obj) {
|
---|
421 | serial_irq_err_set(obj, 0);
|
---|
422 | if (uart_data[index].wanted_rx_events & (SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR)) {
|
---|
423 | uart_data[index].event = SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR;
|
---|
424 | if (obj->serial.uart->SCFSR & 1 << 2) {
|
---|
425 | uart_data[index].event = SERIAL_EVENT_RX_PARITY_ERROR;
|
---|
426 | } else if (obj->serial.uart->SCFSR & 1 << 3) {
|
---|
427 | uart_data[index].event = SERIAL_EVENT_RX_FRAMING_ERROR;
|
---|
428 | }
|
---|
429 | ((void (*)())uart_data[index].async_rx_callback)();
|
---|
430 | }
|
---|
431 | serial_rx_abort_asynch(obj);
|
---|
432 |
|
---|
433 | core_util_critical_section_enter();
|
---|
434 | if (obj->serial.uart->SCFSR & 0x93) {
|
---|
435 | err_read = obj->serial.uart->SCFSR;
|
---|
436 | obj->serial.uart->SCFSR = (err_read & ~0x93);
|
---|
437 | }
|
---|
438 | if (obj->serial.uart->SCLSR & 1) {
|
---|
439 | obj->serial.uart->SCLSR = 0;
|
---|
440 | }
|
---|
441 | core_util_critical_section_exit();
|
---|
442 | }
|
---|
443 | }
|
---|
444 |
|
---|
445 | static void uart0_tx_irq(void) {
|
---|
446 | uart_tx_irq(SCIFTXI0_IRQn, 0);
|
---|
447 | }
|
---|
448 | static void uart0_rx_irq(void) {
|
---|
449 | uart_rx_irq(SCIFRXI0_IRQn, 0);
|
---|
450 | }
|
---|
451 | static void uart0_er_irq(void) {
|
---|
452 | uart_err_irq(SCIFERI0_IRQn, 0);
|
---|
453 | }
|
---|
454 |
|
---|
455 | static void uart1_tx_irq(void) {
|
---|
456 | uart_tx_irq(SCIFTXI1_IRQn, 1);
|
---|
457 | }
|
---|
458 | static void uart1_rx_irq(void) {
|
---|
459 | uart_rx_irq(SCIFRXI1_IRQn, 1);
|
---|
460 | }
|
---|
461 | static void uart1_er_irq(void) {
|
---|
462 | uart_err_irq(SCIFERI1_IRQn, 1);
|
---|
463 | }
|
---|
464 |
|
---|
465 | static void uart2_tx_irq(void) {
|
---|
466 | uart_tx_irq(SCIFTXI2_IRQn, 2);
|
---|
467 | }
|
---|
468 | static void uart2_rx_irq(void) {
|
---|
469 | uart_rx_irq(SCIFRXI2_IRQn, 2);
|
---|
470 | }
|
---|
471 | static void uart2_er_irq(void) {
|
---|
472 | uart_err_irq(SCIFERI2_IRQn, 2);
|
---|
473 | }
|
---|
474 |
|
---|
475 | static void uart3_tx_irq(void) {
|
---|
476 | uart_tx_irq(SCIFTXI3_IRQn, 3);
|
---|
477 | }
|
---|
478 | static void uart3_rx_irq(void) {
|
---|
479 | uart_rx_irq(SCIFRXI3_IRQn, 3);
|
---|
480 | }
|
---|
481 | static void uart3_er_irq(void) {
|
---|
482 | uart_err_irq(SCIFERI3_IRQn, 3);
|
---|
483 | }
|
---|
484 |
|
---|
485 | static void uart4_tx_irq(void) {
|
---|
486 | uart_tx_irq(SCIFTXI4_IRQn, 4);
|
---|
487 | }
|
---|
488 | static void uart4_rx_irq(void) {
|
---|
489 | uart_rx_irq(SCIFRXI4_IRQn, 4);
|
---|
490 | }
|
---|
491 | static void uart4_er_irq(void) {
|
---|
492 | uart_err_irq(SCIFERI4_IRQn, 4);
|
---|
493 | }
|
---|
494 |
|
---|
495 | #if defined(TARGET_RZA1H)
|
---|
496 | static void uart5_tx_irq(void) {
|
---|
497 | uart_tx_irq(SCIFTXI5_IRQn, 5);
|
---|
498 | }
|
---|
499 | static void uart5_rx_irq(void) {
|
---|
500 | uart_rx_irq(SCIFRXI5_IRQn, 5);
|
---|
501 | }
|
---|
502 | static void uart5_er_irq(void) {
|
---|
503 | uart_err_irq(SCIFERI5_IRQn, 5);
|
---|
504 | }
|
---|
505 |
|
---|
506 | static void uart6_tx_irq(void) {
|
---|
507 | uart_tx_irq(SCIFTXI6_IRQn, 6);
|
---|
508 | }
|
---|
509 | static void uart6_rx_irq(void) {
|
---|
510 | uart_rx_irq(SCIFRXI6_IRQn, 6);
|
---|
511 | }
|
---|
512 | static void uart6_er_irq(void) {
|
---|
513 | uart_err_irq(SCIFERI6_IRQn, 6);
|
---|
514 | }
|
---|
515 |
|
---|
516 | static void uart7_tx_irq(void) {
|
---|
517 | uart_tx_irq(SCIFTXI7_IRQn, 7);
|
---|
518 | }
|
---|
519 | static void uart7_rx_irq(void) {
|
---|
520 | uart_rx_irq(SCIFRXI7_IRQn, 7);
|
---|
521 | }
|
---|
522 | static void uart7_er_irq(void) {
|
---|
523 | uart_err_irq(SCIFERI7_IRQn, 7);
|
---|
524 | }
|
---|
525 | #endif
|
---|
526 |
|
---|
527 | void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
|
---|
528 | uart_data[obj->serial.index].irq_handler = handler;
|
---|
529 | uart_data[obj->serial.index].serial_irq_id = id;
|
---|
530 | }
|
---|
531 |
|
---|
532 | static void serial_irq_set_irq(IRQn_Type IRQn, IRQHandler handler, uint32_t enable)
|
---|
533 | {
|
---|
534 | if (enable) {
|
---|
535 | InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler);
|
---|
536 | GIC_SetPriority(IRQn, 5);
|
---|
537 | GIC_EnableIRQ(IRQn);
|
---|
538 | } else {
|
---|
539 | GIC_DisableIRQ(IRQn);
|
---|
540 | }
|
---|
541 | }
|
---|
542 |
|
---|
543 | static void serial_irq_err_set(serial_t *obj, uint32_t enable)
|
---|
544 | {
|
---|
545 | serial_irq_set_irq(irq_set_tbl[obj->serial.index][2], hander_set_tbl[obj->serial.index][2], enable);
|
---|
546 | serial_irq_set_irq(irq_set_tbl[obj->serial.index][3], hander_set_tbl[obj->serial.index][3], enable);
|
---|
547 | }
|
---|
548 |
|
---|
549 | void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
|
---|
550 | IRQn_Type IRQn;
|
---|
551 | IRQHandler handler;
|
---|
552 |
|
---|
553 | IRQn = irq_set_tbl[obj->serial.index][irq];
|
---|
554 | handler = hander_set_tbl[obj->serial.index][irq];
|
---|
555 |
|
---|
556 | if ((obj->serial.index >= 0) && (obj->serial.index <= 7)) {
|
---|
557 | serial_irq_set_irq(IRQn, handler, enable);
|
---|
558 | }
|
---|
559 | }
|
---|
560 |
|
---|
561 | /******************************************************************************
|
---|
562 | * READ/WRITE
|
---|
563 | ******************************************************************************/
|
---|
564 | int serial_getc(serial_t *obj) {
|
---|
565 | uint16_t err_read;
|
---|
566 | int data;
|
---|
567 |
|
---|
568 | core_util_critical_section_enter();
|
---|
569 | if (obj->serial.uart->SCFSR & 0x93) {
|
---|
570 | err_read = obj->serial.uart->SCFSR;
|
---|
571 | obj->serial.uart->SCFSR = (err_read & ~0x93);
|
---|
572 | }
|
---|
573 | obj->serial.uart->SCSCR |= 0x0040; // Set RIE
|
---|
574 | core_util_critical_section_exit();
|
---|
575 |
|
---|
576 | if (obj->serial.uart->SCLSR & 0x0001) {
|
---|
577 | obj->serial.uart->SCLSR = 0u; // ORER clear
|
---|
578 | }
|
---|
579 |
|
---|
580 | while (!serial_readable(obj));
|
---|
581 | data = obj->serial.uart->SCFRDR & 0xff;
|
---|
582 |
|
---|
583 | core_util_critical_section_enter();
|
---|
584 | err_read = obj->serial.uart->SCFSR;
|
---|
585 | obj->serial.uart->SCFSR = (err_read & 0xfffD); // Clear RDF
|
---|
586 | core_util_critical_section_exit();
|
---|
587 |
|
---|
588 | if (err_read & 0x80) {
|
---|
589 | data = -1; //err
|
---|
590 | }
|
---|
591 | return data;
|
---|
592 | }
|
---|
593 |
|
---|
594 | void serial_putc(serial_t *obj, int c) {
|
---|
595 | while (!serial_writable(obj));
|
---|
596 | obj->serial.uart->SCFTDR = c;
|
---|
597 | serial_put_done(obj);
|
---|
598 | }
|
---|
599 |
|
---|
600 | static void serial_put_done(serial_t *obj)
|
---|
601 | {
|
---|
602 | volatile uint16_t dummy_read;
|
---|
603 |
|
---|
604 | core_util_critical_section_enter();
|
---|
605 | dummy_read = obj->serial.uart->SCFSR;
|
---|
606 | obj->serial.uart->SCFSR = (dummy_read & 0xff9f); // Clear TEND/TDFE
|
---|
607 | obj->serial.uart->SCSCR |= 0x0080; // Set TIE
|
---|
608 | core_util_critical_section_exit();
|
---|
609 | }
|
---|
610 |
|
---|
611 | int serial_readable(serial_t *obj) {
|
---|
612 | return ((obj->serial.uart->SCFSR & 0x02) != 0); // RDF
|
---|
613 | }
|
---|
614 |
|
---|
615 | int serial_writable(serial_t *obj) {
|
---|
616 | return ((obj->serial.uart->SCFSR & 0x20) != 0); // TDFE
|
---|
617 | }
|
---|
618 |
|
---|
619 | void serial_clear(serial_t *obj) {
|
---|
620 | core_util_critical_section_enter();
|
---|
621 |
|
---|
622 | obj->serial.uart->SCFCR |= 0x0006u; // TFRST = 1, RFRST = 1
|
---|
623 | obj->serial.uart->SCFCR &= ~0x0006u; // TFRST = 0, RFRST = 0
|
---|
624 | obj->serial.uart->SCFSR &= ~0x0093u; // ER, BRK, RDF, DR = 0
|
---|
625 |
|
---|
626 | core_util_critical_section_exit();
|
---|
627 | }
|
---|
628 |
|
---|
629 | void serial_pinout_tx(PinName tx) {
|
---|
630 | pinmap_pinout(tx, PinMap_UART_TX);
|
---|
631 | }
|
---|
632 |
|
---|
633 | void serial_break_set(serial_t *obj) {
|
---|
634 | core_util_critical_section_enter();
|
---|
635 | // TxD Output(L)
|
---|
636 | obj->serial.uart->SCSPTR &= ~0x0001u; // SPB2DT = 0
|
---|
637 | obj->serial.uart->SCSCR &= ~0x0020u; // TE = 0 (Output disable)
|
---|
638 | core_util_critical_section_exit();
|
---|
639 | }
|
---|
640 |
|
---|
641 | void serial_break_clear(serial_t *obj) {
|
---|
642 | core_util_critical_section_enter();
|
---|
643 | obj->serial.uart->SCSCR |= 0x0020u; // TE = 1 (Output enable)
|
---|
644 | obj->serial.uart->SCSPTR |= 0x0001u; // SPB2DT = 1
|
---|
645 | core_util_critical_section_exit();
|
---|
646 | }
|
---|
647 |
|
---|
648 | #if DEVICE_SERIAL_FC
|
---|
649 | void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
|
---|
650 | // determine the UART to use
|
---|
651 |
|
---|
652 | if (type == FlowControlRTSCTS) {
|
---|
653 | core_util_critical_section_enter();
|
---|
654 | obj->serial.uart->SCFCR |= 0x0008u; // CTS/RTS enable
|
---|
655 | core_util_critical_section_exit();
|
---|
656 | pinmap_pinout(rxflow, PinMap_UART_RTS);
|
---|
657 | pinmap_pinout(txflow, PinMap_UART_CTS);
|
---|
658 | } else {
|
---|
659 | core_util_critical_section_enter();
|
---|
660 | obj->serial.uart->SCFCR &= ~0x0008u; // CTS/RTS diable
|
---|
661 | core_util_critical_section_exit();
|
---|
662 | }
|
---|
663 | }
|
---|
664 | #endif
|
---|
665 |
|
---|
666 | static uint8_t serial_available_buffer(serial_t *obj)
|
---|
667 | {
|
---|
668 | return 1;
|
---|
669 | /* Faster but unstable way */
|
---|
670 | /*
|
---|
671 | uint16_t ret = 16 - ((obj->serial.uart->SCFDR >> 8) & 0x1F);
|
---|
672 | while (ret == 0) {
|
---|
673 | ret = 16 - ((obj->serial.uart->SCFDR >> 8) & 0x1F);
|
---|
674 | }
|
---|
675 | MBED_ASSERT(0 < ret && ret <= 16);
|
---|
676 | return ret;
|
---|
677 | */
|
---|
678 | }
|
---|
679 |
|
---|
680 | #if DEVICE_SERIAL_ASYNCH
|
---|
681 |
|
---|
682 | /******************************************************************************
|
---|
683 | * ASYNCHRONOUS HAL
|
---|
684 | ******************************************************************************/
|
---|
685 |
|
---|
686 | int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
|
---|
687 | {
|
---|
688 | int i;
|
---|
689 | buffer_t *buf = &obj->tx_buff;
|
---|
690 | struct serial_global_data_s *data = uart_data + obj->serial.index;
|
---|
691 |
|
---|
692 | if (tx_length == 0) {
|
---|
693 | return 0;
|
---|
694 | }
|
---|
695 |
|
---|
696 | buf->buffer = (void *)tx;
|
---|
697 | buf->length = tx_length * tx_width / 8;
|
---|
698 | buf->pos = 0;
|
---|
699 | buf->width = tx_width;
|
---|
700 | data->tranferring_obj = obj;
|
---|
701 | data->async_tx_callback = handler;
|
---|
702 | serial_irq_set(obj, TxIrq, 1);
|
---|
703 |
|
---|
704 | while (!serial_writable(obj));
|
---|
705 | i = buf->length;
|
---|
706 | if (serial_available_buffer(obj) < i) {
|
---|
707 | i = serial_available_buffer(obj);
|
---|
708 | }
|
---|
709 | do {
|
---|
710 | uint8_t c = *(uint8_t *)buf->buffer;
|
---|
711 | obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + 1;
|
---|
712 | ++buf->pos;
|
---|
713 | obj->serial.uart->SCFTDR = c;
|
---|
714 | } while (--i);
|
---|
715 | serial_put_done(obj);
|
---|
716 |
|
---|
717 | return buf->length;
|
---|
718 | }
|
---|
719 |
|
---|
720 | void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
|
---|
721 | {
|
---|
722 | buffer_t *buf = &obj->rx_buff;
|
---|
723 | struct serial_global_data_s *data = uart_data + obj->serial.index;
|
---|
724 |
|
---|
725 | if (rx_length == 0) {
|
---|
726 | return;
|
---|
727 | }
|
---|
728 |
|
---|
729 | buf->buffer = rx;
|
---|
730 | buf->length = rx_length * rx_width / 8;
|
---|
731 | buf->pos = 0;
|
---|
732 | buf->width = rx_width;
|
---|
733 | obj->char_match = char_match;
|
---|
734 | obj->char_found = 0;
|
---|
735 | data->receiving_obj = obj;
|
---|
736 | data->async_rx_callback = handler;
|
---|
737 | data->event = 0;
|
---|
738 | data->wanted_rx_events = event;
|
---|
739 |
|
---|
740 | serial_irq_set(obj, RxIrq, 1);
|
---|
741 | serial_irq_err_set(obj, 1);
|
---|
742 | }
|
---|
743 |
|
---|
744 | uint8_t serial_tx_active(serial_t *obj)
|
---|
745 | {
|
---|
746 | return uart_data[obj->serial.index].tranferring_obj != NULL;
|
---|
747 | }
|
---|
748 |
|
---|
749 | uint8_t serial_rx_active(serial_t *obj)
|
---|
750 | {
|
---|
751 | return uart_data[obj->serial.index].receiving_obj != NULL;
|
---|
752 | }
|
---|
753 |
|
---|
754 | int serial_irq_handler_asynch(serial_t *obj)
|
---|
755 | {
|
---|
756 | return uart_data[obj->serial.index].event;
|
---|
757 | }
|
---|
758 |
|
---|
759 | void serial_tx_abort_asynch(serial_t *obj)
|
---|
760 | {
|
---|
761 | uart_data[obj->serial.index].tranferring_obj = NULL;
|
---|
762 | obj->serial.uart->SCFCR |= 1 << 2;
|
---|
763 | obj->serial.uart->SCFCR &= ~(1 << 2);
|
---|
764 | }
|
---|
765 |
|
---|
766 | void serial_rx_abort_asynch(serial_t *obj)
|
---|
767 | {
|
---|
768 | uart_data[obj->serial.index].receiving_obj = NULL;
|
---|
769 | obj->serial.uart->SCFCR |= 1 << 1;
|
---|
770 | obj->serial.uart->SCFCR &= ~(1 << 1);
|
---|
771 | }
|
---|
772 |
|
---|
773 | #endif
|
---|