[26] | 1 | /*
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| 2 | * TOPPERS/JSP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Just Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
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| 7 | * Toyohashi Univ. of Technology, JAPAN
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| 8 | * Copyright (C) 2000-2003 by Industrial Technology Institute,
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| 9 | * Miyagi Prefectural Government, JAPAN
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| 10 | *
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| 11 | * ä¸è¨èä½æ¨©è
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| 12 | ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
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| 13 | * ã«ãã£ã¦å
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| 14 | ¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
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| 15 | * è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
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| 16 | * ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
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| 17 | å¸ï¼ä»¥ä¸ï¼
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| 18 | * å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 19 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 20 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 21 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 22 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 23 | * ç¨ã§ããå½¢ã§åé
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| 24 | å¸ããå ´åã«ã¯ï¼åé
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| 25 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 26 | * è
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| 27 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 28 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 29 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 30 | * ç¨ã§ããªãå½¢ã§åé
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| 31 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 32 | * ã¨ï¼
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| 33 | * (a) åé
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| 34 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 35 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 36 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 37 | * (b) åé
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| 38 | å¸ã®å½¢æ
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| 39 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 40 | * å ±åãããã¨ï¼
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| 41 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 42 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 43 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 44 | 責ãããã¨ï¼
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| 45 | *
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| 46 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 47 | ã
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| 48 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
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| 49 | * å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
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| 50 | * æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
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| 51 | */
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| 52 |
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| 53 | #ifndef _MIPS3_H_
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| 54 | #define _MIPS3_H_
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| 55 |
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| 56 | #include <util.h>
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| 57 |
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| 58 | /*
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| 59 | * MIPS3 ç¨å®ç¾©
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| 60 | */
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| 61 |
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| 62 | /* CPUã³ã¢ã®å
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| 63 | é¨ã¬ã¸ã¹ã¿ã®å称 */
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| 64 | #define zero $0 /* 常æã¼ã */
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| 65 | #define at $1 /* ã¢ã»ã³ãã©ã®ãã³ãã©ãª */
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| 66 | #define v0 $2 /* é¢æ°ã®æ»ãå¤ */
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| 67 | #define v1 $3
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| 68 | #define a0 $4 /* é¢æ°ã®å¼æ° */
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| 69 | #define a1 $5
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| 70 | #define a2 $6
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| 71 | #define a3 $7
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| 72 | #define t0 $8 /* ãã³ãã©ãªã¬ã¸ã¹ã¿ tx (x=0-9)ï¼é¢æ°å¼ã³åºãã§ç ´å£ */
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| 73 | #define t1 $9
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| 74 | #define t2 $10
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| 75 | #define t3 $11
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| 76 | #define t4 $12
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| 77 | #define t5 $13
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| 78 | #define t6 $14
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| 79 | #define t7 $15
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| 80 | #define s0 $16 /* sx (x=0-7) : é¢æ°å¼ã³åºãã§ä¸å¤ãªã¬ã¸ã¹ã¿ */
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| 81 | #define s1 $17
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| 82 | #define s2 $18
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| 83 | #define s3 $19
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| 84 | #define s4 $20
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| 85 | #define s5 $21
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| 86 | #define s6 $22
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| 87 | #define s7 $23
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| 88 | #define t8 $24 /* ãã³ãã©ãªã¬ã¸ã¹ã¿ tx (x=0-9)ï¼é¢æ°å¼ã³åºãã§ç ´å£ */
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| 89 | #define t9 $25
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| 90 | #define k0 $26 /* OSç¨ã«äºç´æ¸ã¿ */
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| 91 | #define kt0 $26
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| 92 | #define k1 $27
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| 93 | #define kt1 $27
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| 94 | #define gp $28 /* 大åå¤æ°é åã®ãã¼ã¹ã¢ãã¬ã¹ */
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| 95 | #define sp $29 /* ã¹ã¿ãã¯ãã¤ã³ã¿ */
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| 96 | #define fp $30 /* ãã¬ã¼ã ãã¤ã³ã¿ */
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| 97 | /* ããã㯠*/
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| 98 | #define s8 $30 /* s8 : é¢æ°å¼ã³åºãã§ä¸å¤ãªã¬ã¸ã¹ã¿ */
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| 99 | #define ra $31 /* é¢æ°ããã®æ»ãã¢ãã¬ã¹ */
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| 100 |
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| 101 | /* CP0ã®å
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| 102 | é¨ã¬ã¸ã¹ã¿ã®å称 */
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| 103 | #define Index $0
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| 104 | #define Random $1
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| 105 | #define EntryLo0 $2
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| 106 | #define EntryLo1 $3
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| 107 | #define Context $4
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| 108 | #define PageMask $5
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| 109 | #define Wired $6
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| 110 | #define Error $7
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| 111 | #define BadVAddr $8
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| 112 | #define Count $9
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| 113 | #define EntryHi $10
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| 114 | #define Compare $11
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| 115 | #define Status $12
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| 116 | #define Cause $13
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| 117 | #define EPC $14
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| 118 | #define PRId $15
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| 119 | #define Config $16
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| 120 | #define LLAddr $17
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| 121 | #define WatchLo $18
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| 122 | #define WatchHi $19
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| 123 | #define XContext $20
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| 124 | /* $21-$24 - äºç´ */
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| 125 | #define Performance $25
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| 126 | #define ParityErr $26
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| 127 | #define CacheErr $27
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| 128 | #define TagLo $28
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| 129 | #define TagHi $29
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| 130 | #define ErrorEPC $30
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| 131 | /* $31 - äºç´ */
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| 132 |
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| 133 | /* ã¤ã³ã©ã¤ã³ã¢ã»ã³ãã©å
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| 134 | ã§ä½¿ãå ´åã®å®ç¾© */
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| 135 | #define str_k0 "$26"
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| 136 | #define str_Status "$12"
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| 137 |
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| 138 | /* ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿é¢ä¿ */
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| 139 | #define SR_IE BIT0 /* IEããã */
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| 140 | #define SR_EXL BIT1 /* EXLããã */
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| 141 | #define SR_ERL BIT2 /* ERLããã */
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| 142 |
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| 143 | #define SR_EXL_IE (SR_EXL | SR_IE) /* EXL,IEããã */
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| 144 | #define SR_ERL_EXL (SR_ERL | SR_EXL) /* ERL,EXLããã */
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| 145 | #define SR_ERL_EXL_IE (SR_ERL_EXL | SR_IE) /* ERL,EXL,IEããã */
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| 146 | #define SR_IM 0xff00 /* IMããããåãåºããã¹ã¯ */
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| 147 |
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| 148 | #define SR_UX BIT5 /* UXããã */
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| 149 | #define SR_SX BIT6 /* SXããã */
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| 150 | #define SR_KX BIT7 /* SXããã */
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| 151 | #define SR_DE BIT16 /* DEããã */
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| 152 | #define SR_SR BIT20 /* SRããã */
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| 153 | #define SR_BEV BIT22 /* BEVããã */
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| 154 | #define SR_RE BIT25 /* REããã */
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| 155 | #define SR_CU0 BIT28 /* CU0ããã */
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| 156 | #define SR_CU1 BIT29 /* CU1ããã */
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| 157 | #define SR_CU2 BIT30 /* CU2ããã */
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| 158 | #define SR_XX BIT31 /* XXããã */
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| 159 |
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| 160 | /* åå ã¬ã¸ã¹ã¿é¢ä¿ */
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| 161 | #define Cause_IP0 BIT8 /* IP0ããã */
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| 162 | #define Cause_IP1 BIT9 /* IP1ããã */
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| 163 | #define Cause_IP2 BIT10 /* IP2ããã */
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| 164 | #define Cause_IP3 BIT11 /* IP3ããã */
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| 165 | #define Cause_IP4 BIT12 /* IP4ããã */
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| 166 | #define Cause_IP5 BIT13 /* IP5ããã */
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| 167 | #define Cause_IP6 BIT14 /* IP6ããã */
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| 168 | #define Cause_IP7 BIT15 /* IP7ããã */
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| 169 |
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| 170 | /* å¤é¨å²ãè¾¼ã¿ã«å¯¾ããIPãããã®å¥å */
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| 171 | #define Cause_Int0 Cause_IP2 /* Int0è¦æ±ããã */
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| 172 | #define Cause_Int1 Cause_IP3 /* Int1è¦æ±ããã */
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| 173 | #define Cause_Int2 Cause_IP4 /* Int2è¦æ±ããã */
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| 174 | #define Cause_Int3 Cause_IP5 /* Int3è¦æ±ããã */
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| 175 | #define Cause_Int4 Cause_IP6 /* Int4è¦æ±ããã */
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| 176 |
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| 177 | /* åå ã¬ã¸ã¹ã¿ããåå ã³ã¼ããåãåºããã¹ã¯ */
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| 178 | #define ExcCode_mask 0x7c
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| 179 |
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| 180 | /* ä¾å¤ã³ã¼ã */
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| 181 | #define Int 0 /* å²ãè¾¼ã¿ä¾å¤ */
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| 182 | #define Mod 1 /* TLBå¤æ´ä¾å¤ */
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| 183 | #define TLBL 2 /* TLBä¸ä¸è´ä¾å¤ (ãã¼ãã¾ãã¯å½ä»¤ãã§ãã) */
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| 184 | #define TLBS 3 /* TLBä¸ä¸è´ä¾å¤ (ã¹ãã¢) */
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| 185 | #define AdEL 4 /* ã¢ãã¬ã¹ã¨ã©ã¼ä¾å¤ (ãã¼ãã¾ãã¯å½ä»¤ãã§ãã) */
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| 186 | #define AdES 5 /* ã¢ãã¬ã¹ã¨ã©ã¼ä¾å¤ (ã¹ãã¢) */
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| 187 | #define IBE 6 /* ãã¹ã¨ã©ã¼ä¾å¤ (å½ä»¤ãã§ãã) */
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| 188 | #define DBE 7 /* ãã¹ã¨ã©ã¼ä¾å¤ (ãã¼ã¿ã®ãã¼ãã¾ãã¯ã¹ãã¢) */
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| 189 | #define Sys 8 /* ã·ã¹ãã ã³ã¼ã«ä¾å¤ */
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| 190 | #define Bp 9 /* ãã¬ã¤ã¯ãã¤ã³ãä¾å¤ */
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| 191 | #define RI 10 /* äºç´å½ä»¤ä¾å¤ */
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| 192 | #define CpU 11 /* ã³ããã»ããµä½¿ç¨ä¸å¯ä¾å¤ */
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| 193 | #define Ov 12 /* æ¼ç®ãªã¼ãã¼ããã¼ä¾å¤ */
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| 194 | #define Tr 13 /* ãã©ããä¾å¤ */
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| 195 | /* 14 - äºç´ */
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| 196 | #define FPE 15 /* æµ®åå°æ°ç¹ä¾å¤ */
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| 197 | /* 16-22 - äºç´ */
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| 198 | #define WATCH 23 /* ã¦ã©ããä¾å¤ */
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| 199 | /* 24-31 - äºç´ */
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| 200 |
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| 201 | /* å²è¾¼ã¿è¦å çªå· */
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| 202 | #define INTNO_IP0 0
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| 203 | #define INTNO_IP1 1
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| 204 | #define INTNO_IP2 2
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| 205 | #define INTNO_IP3 3
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| 206 | #define INTNO_IP4 4
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| 207 | #define INTNO_IP5 5
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| 208 | #define INTNO_IP6 6
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| 209 | #define INTNO_IP7 7
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| 210 |
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| 211 | /* ã³ã¢ã®å²è¾¼ã¿ã®æ¬æ°ï¼ã½ããã¦ã§ã¢å²è¾¼ã¿ãå«ãï¼ */
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| 212 | #define TMAX_CORE_INTNO 8
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| 213 |
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| 214 | /*
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| 215 | * MIPS3ã³ã¢ã®ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿ã«è¨å®å¯è½ãªæé«å²è¾¼ã¿è¨±å¯ããããã¿ã¼ã³
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| 216 | */
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| 217 | #define MAX_IPM 0xff
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| 218 |
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| 219 | /*
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| 220 | * MIPS3ã³ã¢ã«è¨å®ããå²è¾¼ã¿ãã¹ã¯ã®ãã§ãã¯
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| 221 | */
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| 222 | #define CHECK_CORE_IPM(ipm) CHECK_PAR(0 <= (ipm) && (ipm) <= MAX_IPM)
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| 223 |
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| 224 | /*
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| 225 | * CPUä¾å¤ã®ç¨®é¡æ°
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| 226 | */
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| 227 | #define TMAX_CORE_EXCNO 32u
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| 228 |
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| 229 | /*
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| 230 | * ãã°åºåæã®ã¹ã¿ãã¯æ§é ã®å®ç¾©
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| 231 | * cpu_config.hã«ãããcpu_experré¢æ°ãcpu_support.Sãåç
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| 232 | §ã®ãã¨ã
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| 233 | */
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| 234 | #ifndef _MACRO_ONLY
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| 235 |
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| 236 | typedef struct exc_stack {
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| 237 |
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| 238 | /* ã¬ã¸ã¹ã¿ç¾¤ã®å®ç¾© */
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| 239 | UW sp;
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| 240 | UW at;
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| 241 | UW v0;
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| 242 | UW v1;
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| 243 | UW a0;
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| 244 | UW a1;
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| 245 | UW a2;
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| 246 | UW a3;
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| 247 | UW t0;
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| 248 | UW t1;
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| 249 | UW t2;
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| 250 | UW t3;
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| 251 | UW t4;
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| 252 | UW t5;
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| 253 | UW t6;
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| 254 | UW t7;
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| 255 | UW t8;
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| 256 | UW t9;
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| 257 | UW gp;
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| 258 | UW fp;
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| 259 | UW ra;
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| 260 |
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| 261 | UW CP0_Status;
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| 262 | UW CP0_EPC;
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| 263 |
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| 264 | UW hi;
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| 265 | UW lo;
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| 266 |
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| 267 | } EXCSTACK;
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| 268 |
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| 269 | #endif /* _MACRO_ONLY */
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| 270 |
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| 271 | #endif /* _MIPS3_H_ */
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