[26] | 1 | /*
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| 2 | * TOPPERS/JSP Kernel
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| 3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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| 4 | * Just Standard Profile Kernel
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| 5 | *
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| 6 | * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
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| 7 | * Toyohashi Univ. of Technology, JAPAN
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| 8 | *
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| 9 | * ä¸è¨èä½æ¨©è
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| 10 | ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
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| 11 | * ã«ãã£ã¦å
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| 12 | ¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
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| 13 | * è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
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| 14 | * ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹å¤ã»åé
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| 15 | å¸ï¼ä»¥ä¸ï¼
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| 16 | * å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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| 17 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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| 18 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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| 19 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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| 20 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 21 | * ç¨ã§ããå½¢ã§åé
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| 22 | å¸ããå ´åã«ã¯ï¼åé
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| 23 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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| 24 | * è
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| 25 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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| 26 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 27 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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| 28 | * ç¨ã§ããªãå½¢ã§åé
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| 29 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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| 30 | * ã¨ï¼
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| 31 | * (a) åé
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| 32 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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| 33 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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| 34 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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| 35 | * (b) åé
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| 36 | å¸ã®å½¢æ
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| 37 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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| 38 | * å ±åãããã¨ï¼
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| 39 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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| 40 | * 害ãããï¼ä¸è¨èä½æ¨©è
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| 41 | ããã³TOPPERSããã¸ã§ã¯ããå
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| 42 | 責ãããã¨ï¼
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| 43 | *
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| 44 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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| 45 | ã
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| 46 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
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| 47 | * å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
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| 48 | * æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
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| 49 | *
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| 50 | * @(#) $Id: cpu_support.S,v 1.14 2007/07/27 11:28:44 honda Exp $
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| 51 | */
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| 52 |
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| 53 | #define _MACRO_ONLY
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| 54 | #include "offset.h"
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| 55 | #include "jsp_kernel.h"
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| 56 |
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| 57 | .text
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| 58 | .globl dispatch
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| 59 | .globl exit_and_dispatch
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| 60 |
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| 61 | dispatch:
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| 62 | addi sp, sp, -120
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| 63 | sw (sp+4), r1
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| 64 | sw (sp+8), r2
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| 65 | sw (sp+12), r3
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| 66 | sw (sp+16), r4
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| 67 | sw (sp+20), r5
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| 68 | sw (sp+24), r6
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| 69 | sw (sp+28), r7
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| 70 | sw (sp+32), r8
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| 71 | sw (sp+36), r9
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| 72 | sw (sp+40), r10
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| 73 | sw (sp+44), r11
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| 74 | sw (sp+48), r12
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| 75 | sw (sp+52), r13
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| 76 | sw (sp+56), r14
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| 77 | sw (sp+60), r15
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| 78 | sw (sp+64), r16
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| 79 | sw (sp+68), r17
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| 80 | sw (sp+72), r18
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| 81 | sw (sp+76), r19
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| 82 | sw (sp+80), r20
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| 83 | sw (sp+84), r21
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| 84 | sw (sp+88), r22
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| 85 | sw (sp+92), r23
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| 86 | sw (sp+96), r24
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| 87 | sw (sp+100), r25
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| 88 | sw (sp+104), r26
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| 89 | sw (sp+108), r27
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| 90 | sw (sp+112), ra
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| 91 | sw (sp+116), ea
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| 92 | sw (sp+120), ba
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| 93 |
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| 94 | mvhi r1, hi(runtsk)
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| 95 | ori r1, r1, lo(runtsk)
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| 96 | lw r1, (r1+0)
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| 97 | mvhi r2, hi(dispatch_r)
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| 98 | ori r2, r2, lo(dispatch_r)
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| 99 | sw (r1+TCB_sp), sp
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| 100 | sw (r1+TCB_pc), r2
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| 101 | bi dispatcher
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| 102 |
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| 103 | exit_and_dispatch:
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| 104 | mvhi r1, hi(exception_count)
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| 105 | ori r1, r1, lo(exception_count)
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| 106 | sw (r1+0), r0
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| 107 |
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| 108 | rcsr r1, ie
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| 109 | andi r1, r1, 0x6
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| 110 | wcsr ie, r1
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| 111 |
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| 112 | dispatcher:
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| 113 | mvhi r1, hi(schedtsk)
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| 114 | ori r1, r1, lo(schedtsk)
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| 115 | lw r1, (r1+0)
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| 116 |
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| 117 | mvhi r2, hi(runtsk)
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| 118 | ori r2, r2, lo(runtsk)
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| 119 |
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| 120 | sw (r2+0), r1
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| 121 |
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| 122 | be r1, r0, dispatcher_2
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| 123 | nop
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| 124 |
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| 125 | dispatcher_1:
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| 126 | lw sp, (r1+TCB_sp)
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| 127 | lw r1, (r1+TCB_pc)
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| 128 | b r1
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| 129 | nop
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| 130 |
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| 131 | dispatcher_2:
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| 132 |
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| 133 | mvhi r2, hi(exception_count)
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| 134 | ori r2, r2, lo(exception_count)
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| 135 | ori r3, r0, 1
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| 136 | sw (r2+0), r3
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| 137 |
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| 138 | mvhi r3, hi(_fstack)
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| 139 | ori r3, r3, lo(_fstack)
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| 140 | mv sp, r3
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| 141 |
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| 142 | rcsr r1, ie
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| 143 | ori r1, r1, 0x1
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| 144 | wcsr ie, r1
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| 145 |
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| 146 | nop
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| 147 |
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| 148 | rcsr r1, ie
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| 149 | andi r1, r1, 0x6
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| 150 | wcsr ie, r1
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| 151 |
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| 152 | mvhi r1, hi(exception_count)
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| 153 | ori r1, r1, lo(exception_count)
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| 154 | sw (r1+0), r0
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| 155 |
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| 156 | bi dispatcher
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| 157 |
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| 158 | dispatch_r:
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| 159 | lw r1, (sp+4)
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| 160 | lw r2, (sp+8)
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| 161 | lw r3, (sp+12)
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| 162 | lw r4, (sp+16)
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| 163 | lw r5, (sp+20)
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| 164 | lw r6, (sp+24)
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| 165 | lw r7, (sp+28)
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| 166 | lw r8, (sp+32)
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| 167 | lw r9, (sp+36)
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| 168 | lw r10, (sp+40)
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| 169 | lw r11, (sp+44)
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| 170 | lw r12, (sp+48)
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| 171 | lw r13, (sp+52)
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| 172 | lw r14, (sp+56)
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| 173 | lw r15, (sp+60)
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| 174 | lw r16, (sp+64)
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| 175 | lw r17, (sp+68)
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| 176 | lw r18, (sp+72)
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| 177 | lw r19, (sp+76)
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| 178 | lw r20, (sp+80)
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| 179 | lw r21, (sp+84)
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| 180 | lw r22, (sp+88)
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| 181 | lw r23, (sp+92)
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| 182 | lw r24, (sp+96)
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| 183 | lw r25, (sp+100)
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| 184 | lw r26, (sp+104)
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| 185 | lw r27, (sp+108)
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| 186 | lw ra, (sp+112)
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| 187 | lw ea, (sp+116)
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| 188 | lw ba, (sp+120)
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| 189 | addi sp, sp, 120
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| 190 |
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| 191 | mvhi r1, hi(runtsk)
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| 192 | ori r1, r1, lo(runtsk)
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| 193 | lw r1, (r1+0)
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| 194 |
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| 195 | lw r2, (r1+TCB_enatex)
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| 196 | andi r2, r2, TCB_enatex_mask
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| 197 | be r2, r0, dispatcher_r_1
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| 198 | nop
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| 199 | lw r2, (r1+TCB_texptn)
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| 200 | be r2, r0, dispatcher_r_1
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| 201 | nop
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| 202 | bi call_texrtn
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| 203 | nop
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| 204 |
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| 205 | dispatcher_r_1:
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| 206 | ret
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| 207 | nop
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| 208 |
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| 209 | .globl activate_r
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| 210 | activate_r:
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| 211 |
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| 212 | mvhi r2, hi(runtsk)
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| 213 | ori r2, r2, lo(runtsk)
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| 214 | lw r2, (r2+0)
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| 215 |
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| 216 | lw r2, (r2+TCB_tinib)
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| 217 | lw r3, (r2+TINIB_task)
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| 218 | lw r1, (r2+TINIB_exinf)
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| 219 |
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| 220 | rcsr r2, ie
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| 221 | ori r2, r2, 0x1
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| 222 | wcsr ie, r2
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| 223 |
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| 224 | mvhi ra, hi(ext_tsk)
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| 225 | ori ra, ra, lo(ext_tsk)
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| 226 |
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| 227 | b r3
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| 228 | nop
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| 229 |
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| 230 | .text
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| 231 | .globl ret_int
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| 232 | .globl ret_exc
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| 233 | ret_int:
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| 234 | ret_exc:
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| 235 | mvhi r1, hi(enadsp)
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| 236 | ori r1, r1, lo(enadsp)
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| 237 | lw r1, (r1+0)
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| 238 | be r1, r0, ret_int_1
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| 239 |
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| 240 | mvhi r1, hi(runtsk)
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| 241 | ori r1, r1, lo(runtsk)
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| 242 | lw r1, (r1+0)
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| 243 |
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| 244 | mvhi r2, hi(schedtsk)
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| 245 | ori r2, r2, lo(schedtsk)
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| 246 | lw r2, (r2+0)
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| 247 | be r1, r2, ret_int_1
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| 248 |
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| 249 | addi sp, sp, -120
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| 250 | sw (sp+4), r1
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| 251 | sw (sp+8), r2
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| 252 | sw (sp+12), r3
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| 253 | sw (sp+16), r4
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| 254 | sw (sp+20), r5
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| 255 | sw (sp+24), r6
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| 256 | sw (sp+28), r7
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| 257 | sw (sp+32), r8
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| 258 | sw (sp+36), r9
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| 259 | sw (sp+40), r10
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| 260 | sw (sp+44), r11
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| 261 | sw (sp+48), r12
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| 262 | sw (sp+52), r13
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| 263 | sw (sp+56), r14
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| 264 | sw (sp+60), r15
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| 265 | sw (sp+64), r16
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| 266 | sw (sp+68), r17
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| 267 | sw (sp+72), r18
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| 268 | sw (sp+76), r19
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| 269 | sw (sp+80), r20
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| 270 | sw (sp+84), r21
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| 271 | sw (sp+88), r22
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| 272 | sw (sp+92), r23
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| 273 | sw (sp+96), r24
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| 274 | sw (sp+100), r25
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| 275 | sw (sp+104), r26
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| 276 | sw (sp+108), r27
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| 277 | sw (sp+112), ra
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| 278 | sw (sp+116), ea
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| 279 | sw (sp+120), ba
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| 280 |
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| 281 | sw (r1+TCB_sp), sp
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| 282 | mvhi r2, hi(ret_int_r)
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| 283 | ori r2, r2, lo(ret_int_r)
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| 284 | sw (r1+TCB_pc), r2
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| 285 |
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| 286 | bi dispatcher
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| 287 |
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| 288 | ret_int_r:
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| 289 | lw r1, (sp+4)
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| 290 | lw r2, (sp+8)
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| 291 | lw r3, (sp+12)
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| 292 | lw r4, (sp+16)
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| 293 | lw r5, (sp+20)
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| 294 | lw r6, (sp+24)
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| 295 | lw r7, (sp+28)
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| 296 | lw r8, (sp+32)
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| 297 | lw r9, (sp+36)
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| 298 | lw r10, (sp+40)
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| 299 | lw r11, (sp+44)
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| 300 | lw r12, (sp+48)
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| 301 | lw r13, (sp+52)
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| 302 | lw r14, (sp+56)
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| 303 | lw r15, (sp+60)
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| 304 | lw r16, (sp+64)
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| 305 | lw r17, (sp+68)
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| 306 | lw r18, (sp+72)
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| 307 | lw r19, (sp+76)
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| 308 | lw r20, (sp+80)
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| 309 | lw r21, (sp+84)
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| 310 | lw r22, (sp+88)
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| 311 | lw r23, (sp+92)
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| 312 | lw r24, (sp+96)
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| 313 | lw r25, (sp+100)
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| 314 | lw r26, (sp+104)
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| 315 | lw r27, (sp+108)
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| 316 | lw ra, (sp+112)
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| 317 | lw ea, (sp+116)
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| 318 | lw ba, (sp+120)
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| 319 | addi sp, sp, 120
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| 320 |
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| 321 | ret_int_1:
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| 322 | mvhi r1, hi(runtsk)
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| 323 | ori r1, r1, lo(runtsk)
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| 324 | lw r1, (r1+0)
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| 325 |
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| 326 | lw r2, (r1+TCB_enatex)
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| 327 | mvhi r3, hi(TCB_enatex_mask)
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| 328 | ori r3, r3, lo(TCB_enatex_mask)
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| 329 | be r2, r3, ret_int_2
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| 330 |
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| 331 | lw r2, (r1+TCB_texptn)
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| 332 | be r2, r0, ret_int_2
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| 333 |
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| 334 | calli call_texrtn
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| 335 |
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| 336 | ret_int_2:
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| 337 | addi sp, sp, 4
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| 338 | lw ra, (sp+0)
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| 339 | ret
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| 340 |
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| 341 |
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