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cpu_support.S@ 363

Last change on this file since 363 was 363, checked in by ykominami, 5 years ago
add tags/jsp-1.4.4-full-UTF8
Property svn:executable set to ``*
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1	/*
2	* TOPPERS/JSP Kernel
3	* Toyohashi Open Platform for Embedded Real-Time Systems/
4	* Just Standard Profile Kernel
5	*
6	* Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
7	* Toyohashi Univ. of Technology, JAPAN
8	*
9	* ä¸è¨èä½æ¨©è
10	ã¯ï¼ä»¥ä¸ã® (1)ã(4) ã®æ¡ä»¶ãï¼Free Software Foundation
11	* ã«ãã£ã¦å
12	¬è¡¨ããã¦ãã GNU General Public License ã® Version 2 ã«è¨
13	* è¿°ããã¦ããæ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§ã¢ï¼æ¬ã½ããã¦ã§ã¢
14	* ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹å¤ã»åé
15	å¸ï¼ä»¥ä¸ï¼
16	* å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
17	* (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
18	* æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
19	* ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
20	* (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
21	* ç¨ã§ããå½¢ã§åé
22	å¸ããå ´åã«ã¯ï¼åé
23	å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
24	* è
25	ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
26	* ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
27	* (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
28	* ç¨ã§ããªãå½¢ã§åé
29	å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
30	* ã¨ï¼
31	* (a) åé
32	å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
33	ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
34	* ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
35	* (b) åé
36	å¸ã®å½¢æ
37	ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
38	* å ±åãããã¨ï¼
39	* (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
40	* å®³ãããï¼ä¸è¨èä½æ¨©è
41	ããã³TOPPERSããã¸ã§ã¯ããå
42	è²¬ãããã¨ï¼
43	*
44	* æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
45	ã
46	* ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ãã®é©ç¨å¯è½æ§ã
47	* å«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´
48	* æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ãã®è²¬ä»»ãè² ããªãï¼
49	*
50	* @(#) $Id: cpu_support.S,v 1.14 2007/07/27 11:28:44 honda Exp $
51	*/
52
53	#define _MACRO_ONLY
54	#include "offset.h"
55	#include "jsp_kernel.h"
56
57	.text
58	.globl dispatch
59	.globl exit_and_dispatch
60
61	dispatch:
62	addi sp, sp, -120
63	sw (sp+4), r1
64	sw (sp+8), r2
65	sw (sp+12), r3
66	sw (sp+16), r4
67	sw (sp+20), r5
68	sw (sp+24), r6
69	sw (sp+28), r7
70	sw (sp+32), r8
71	sw (sp+36), r9
72	sw (sp+40), r10
73	sw (sp+44), r11
74	sw (sp+48), r12
75	sw (sp+52), r13
76	sw (sp+56), r14
77	sw (sp+60), r15
78	sw (sp+64), r16
79	sw (sp+68), r17
80	sw (sp+72), r18
81	sw (sp+76), r19
82	sw (sp+80), r20
83	sw (sp+84), r21
84	sw (sp+88), r22
85	sw (sp+92), r23
86	sw (sp+96), r24
87	sw (sp+100), r25
88	sw (sp+104), r26
89	sw (sp+108), r27
90	sw (sp+112), ra
91	sw (sp+116), ea
92	sw (sp+120), ba
93
94	mvhi r1, hi(runtsk)
95	ori r1, r1, lo(runtsk)
96	lw r1, (r1+0)
97	mvhi r2, hi(dispatch_r)
98	ori r2, r2, lo(dispatch_r)
99	sw (r1+TCB_sp), sp
100	sw (r1+TCB_pc), r2
101	bi dispatcher
102
103	exit_and_dispatch:
104	mvhi r1, hi(exception_count)
105	ori r1, r1, lo(exception_count)
106	sw (r1+0), r0
107
108	rcsr r1, ie
109	andi r1, r1, 0x6
110	wcsr ie, r1
111
112	dispatcher:
113	mvhi r1, hi(schedtsk)
114	ori r1, r1, lo(schedtsk)
115	lw r1, (r1+0)
116
117	mvhi r2, hi(runtsk)
118	ori r2, r2, lo(runtsk)
119
120	sw (r2+0), r1
121
122	be r1, r0, dispatcher_2
123	nop
124
125	dispatcher_1:
126	lw sp, (r1+TCB_sp)
127	lw r1, (r1+TCB_pc)
128	b r1
129	nop
130
131	dispatcher_2:
132
133	mvhi r2, hi(exception_count)
134	ori r2, r2, lo(exception_count)
135	ori r3, r0, 1
136	sw (r2+0), r3
137
138	mvhi r3, hi(_fstack)
139	ori r3, r3, lo(_fstack)
140	mv sp, r3
141
142	rcsr r1, ie
143	ori r1, r1, 0x1
144	wcsr ie, r1
145
146	nop
147
148	rcsr r1, ie
149	andi r1, r1, 0x6
150	wcsr ie, r1
151
152	mvhi r1, hi(exception_count)
153	ori r1, r1, lo(exception_count)
154	sw (r1+0), r0
155
156	bi dispatcher
157
158	dispatch_r:
159	lw r1, (sp+4)
160	lw r2, (sp+8)
161	lw r3, (sp+12)
162	lw r4, (sp+16)
163	lw r5, (sp+20)
164	lw r6, (sp+24)
165	lw r7, (sp+28)
166	lw r8, (sp+32)
167	lw r9, (sp+36)
168	lw r10, (sp+40)
169	lw r11, (sp+44)
170	lw r12, (sp+48)
171	lw r13, (sp+52)
172	lw r14, (sp+56)
173	lw r15, (sp+60)
174	lw r16, (sp+64)
175	lw r17, (sp+68)
176	lw r18, (sp+72)
177	lw r19, (sp+76)
178	lw r20, (sp+80)
179	lw r21, (sp+84)
180	lw r22, (sp+88)
181	lw r23, (sp+92)
182	lw r24, (sp+96)
183	lw r25, (sp+100)
184	lw r26, (sp+104)
185	lw r27, (sp+108)
186	lw ra, (sp+112)
187	lw ea, (sp+116)
188	lw ba, (sp+120)
189	addi sp, sp, 120
190
191	mvhi r1, hi(runtsk)
192	ori r1, r1, lo(runtsk)
193	lw r1, (r1+0)
194
195	lw r2, (r1+TCB_enatex)
196	andi r2, r2, TCB_enatex_mask
197	be r2, r0, dispatcher_r_1
198	nop
199	lw r2, (r1+TCB_texptn)
200	be r2, r0, dispatcher_r_1
201	nop
202	bi call_texrtn
203	nop
204
205	dispatcher_r_1:
206	ret
207	nop
208
209	.globl activate_r
210	activate_r:
211
212	mvhi r2, hi(runtsk)
213	ori r2, r2, lo(runtsk)
214	lw r2, (r2+0)
215
216	lw r2, (r2+TCB_tinib)
217	lw r3, (r2+TINIB_task)
218	lw r1, (r2+TINIB_exinf)
219
220	rcsr r2, ie
221	ori r2, r2, 0x1
222	wcsr ie, r2
223
224	mvhi ra, hi(ext_tsk)
225	ori ra, ra, lo(ext_tsk)
226
227	b r3
228	nop
229
230	.text
231	.globl ret_int
232	.globl ret_exc
233	ret_int:
234	ret_exc:
235	mvhi r1, hi(enadsp)
236	ori r1, r1, lo(enadsp)
237	lw r1, (r1+0)
238	be r1, r0, ret_int_1
239
240	mvhi r1, hi(runtsk)
241	ori r1, r1, lo(runtsk)
242	lw r1, (r1+0)
243
244	mvhi r2, hi(schedtsk)
245	ori r2, r2, lo(schedtsk)
246	lw r2, (r2+0)
247	be r1, r2, ret_int_1
248
249	addi sp, sp, -120
250	sw (sp+4), r1
251	sw (sp+8), r2
252	sw (sp+12), r3
253	sw (sp+16), r4
254	sw (sp+20), r5
255	sw (sp+24), r6
256	sw (sp+28), r7
257	sw (sp+32), r8
258	sw (sp+36), r9
259	sw (sp+40), r10
260	sw (sp+44), r11
261	sw (sp+48), r12
262	sw (sp+52), r13
263	sw (sp+56), r14
264	sw (sp+60), r15
265	sw (sp+64), r16
266	sw (sp+68), r17
267	sw (sp+72), r18
268	sw (sp+76), r19
269	sw (sp+80), r20
270	sw (sp+84), r21
271	sw (sp+88), r22
272	sw (sp+92), r23
273	sw (sp+96), r24
274	sw (sp+100), r25
275	sw (sp+104), r26
276	sw (sp+108), r27
277	sw (sp+112), ra
278	sw (sp+116), ea
279	sw (sp+120), ba
280
281	sw (r1+TCB_sp), sp
282	mvhi r2, hi(ret_int_r)
283	ori r2, r2, lo(ret_int_r)
284	sw (r1+TCB_pc), r2
285
286	bi dispatcher
287
288	ret_int_r:
289	lw r1, (sp+4)
290	lw r2, (sp+8)
291	lw r3, (sp+12)
292	lw r4, (sp+16)
293	lw r5, (sp+20)
294	lw r6, (sp+24)
295	lw r7, (sp+28)
296	lw r8, (sp+32)
297	lw r9, (sp+36)
298	lw r10, (sp+40)
299	lw r11, (sp+44)
300	lw r12, (sp+48)
301	lw r13, (sp+52)
302	lw r14, (sp+56)
303	lw r15, (sp+60)
304	lw r16, (sp+64)
305	lw r17, (sp+68)
306	lw r18, (sp+72)
307	lw r19, (sp+76)
308	lw r20, (sp+80)
309	lw r21, (sp+84)
310	lw r22, (sp+88)
311	lw r23, (sp+92)
312	lw r24, (sp+96)
313	lw r25, (sp+100)
314	lw r26, (sp+104)
315	lw r27, (sp+108)
316	lw ra, (sp+112)
317	lw ea, (sp+116)
318	lw ba, (sp+120)
319	addi sp, sp, 120
320
321	ret_int_1:
322	mvhi r1, hi(runtsk)
323	ori r1, r1, lo(runtsk)
324	lw r1, (r1+0)
325
326	lw r2, (r1+TCB_enatex)
327	mvhi r3, hi(TCB_enatex_mask)
328	ori r3, r3, lo(TCB_enatex_mask)
329	be r2, r3, ret_int_2
330
331	lw r2, (r1+TCB_texptn)
332	be r2, r0, ret_int_2
333
334	calli call_texrtn
335
336	ret_int_2:
337	addi sp, sp, 4
338	lw ra, (sp+0)
339	ret
340
341

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