[270] | 1 | /*******************************************************************************
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| 2 | * DISCLAIMER
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| 3 | * This software is supplied by Renesas Electronics Corporation and is only
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| 4 | * intended for use with Renesas products. No other uses are authorized. This
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| 5 | * software is owned by Renesas Electronics Corporation and is protected under
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| 6 | * all applicable laws, including copyright laws.
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| 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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| 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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| 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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| 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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| 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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| 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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| 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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| 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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| 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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| 16 | * Renesas reserves the right, without notice, to make changes to this software
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| 17 | * and to discontinue the availability of this software. By using this software,
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| 18 | * you agree to the additional terms and conditions found by accessing the
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| 19 | * following link:
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| 20 | * http://www.renesas.com/disclaimer*
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| 21 | * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
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| 22 | *******************************************************************************/
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| 23 | /*******************************************************************************
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| 24 | * File Name : scux_iodefine.h
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| 25 | * $Rev: $
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| 26 | * $Date:: $
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| 27 | * Description : Definition of I/O Register (V1.00a)
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| 28 | ******************************************************************************/
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| 29 | #ifndef SCUX_IODEFINE_H
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| 30 | #define SCUX_IODEFINE_H
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| 31 | /* ->QAC 0639 : Over 127 members (C90) */
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| 32 | /* ->SEC M1.10.1 : Not magic number */
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| 33 |
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| 34 | struct st_scux
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| 35 | { /* SCUX */
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| 36 | /* start of struct st_scux_from_ipcir_ipc0_n */
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| 37 | volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */
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| 38 | volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */
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| 39 | volatile uint8_t dummy259[248]; /* */
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| 40 | /* end of struct st_scux_from_ipcir_ipc0_n */
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| 41 | /* start of struct st_scux_from_ipcir_ipc0_n */
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| 42 | volatile uint32_t IPCIR_IPC0_1; /* IPCIR_IPC0_1 */
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| 43 | volatile uint32_t IPSLR_IPC0_1; /* IPSLR_IPC0_1 */
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| 44 | volatile uint8_t dummy260[248]; /* */
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| 45 | /* end of struct st_scux_from_ipcir_ipc0_n */
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| 46 | /* start of struct st_scux_from_ipcir_ipc0_n */
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| 47 | volatile uint32_t IPCIR_IPC0_2; /* IPCIR_IPC0_2 */
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| 48 | volatile uint32_t IPSLR_IPC0_2; /* IPSLR_IPC0_2 */
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| 49 | volatile uint8_t dummy261[248]; /* */
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| 50 | /* end of struct st_scux_from_ipcir_ipc0_n */
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| 51 | /* start of struct st_scux_from_ipcir_ipc0_n */
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| 52 | volatile uint32_t IPCIR_IPC0_3; /* IPCIR_IPC0_3 */
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| 53 | volatile uint32_t IPSLR_IPC0_3; /* IPSLR_IPC0_3 */
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| 54 | volatile uint8_t dummy262[248]; /* */
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| 55 | /* end of struct st_scux_from_ipcir_ipc0_n */
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| 56 | /* start of struct st_scux_from_opcir_opc0_n */
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| 57 | volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */
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| 58 | volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */
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| 59 | volatile uint8_t dummy263[248]; /* */
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| 60 | /* end of struct st_scux_from_opcir_opc0_n */
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| 61 | /* start of struct st_scux_from_opcir_opc0_n */
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| 62 | volatile uint32_t OPCIR_OPC0_1; /* OPCIR_OPC0_1 */
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| 63 | volatile uint32_t OPSLR_OPC0_1; /* OPSLR_OPC0_1 */
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| 64 | volatile uint8_t dummy264[248]; /* */
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| 65 | /* end of struct st_scux_from_opcir_opc0_n */
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| 66 | /* start of struct st_scux_from_opcir_opc0_n */
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| 67 | volatile uint32_t OPCIR_OPC0_2; /* OPCIR_OPC0_2 */
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| 68 | volatile uint32_t OPSLR_OPC0_2; /* OPSLR_OPC0_2 */
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| 69 | volatile uint8_t dummy265[248]; /* */
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| 70 | /* end of struct st_scux_from_opcir_opc0_n */
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| 71 | /* start of struct st_scux_from_opcir_opc0_n */
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| 72 | volatile uint32_t OPCIR_OPC0_3; /* OPCIR_OPC0_3 */
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| 73 | volatile uint32_t OPSLR_OPC0_3; /* OPSLR_OPC0_3 */
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| 74 | volatile uint8_t dummy266[248]; /* */
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| 75 | /* end of struct st_scux_from_opcir_opc0_n */
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| 76 | /* start of struct st_scux_from_ffdir_ffd0_n */
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| 77 | volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */
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| 78 | volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */
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| 79 | volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */
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| 80 | volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */
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| 81 | volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */
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| 82 | volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */
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| 83 | volatile uint8_t dummy267[4]; /* */
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| 84 | volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */
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| 85 | /* end of struct st_scux_from_ffdir_ffd0_n */
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| 86 | volatile uint8_t dummy268[224]; /* */
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| 87 | /* start of struct st_scux_from_ffdir_ffd0_n */
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| 88 | volatile uint32_t FFDIR_FFD0_1; /* FFDIR_FFD0_1 */
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| 89 | volatile uint32_t FDAIR_FFD0_1; /* FDAIR_FFD0_1 */
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| 90 | volatile uint32_t DRQSR_FFD0_1; /* DRQSR_FFD0_1 */
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| 91 | volatile uint32_t FFDPR_FFD0_1; /* FFDPR_FFD0_1 */
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| 92 | volatile uint32_t FFDBR_FFD0_1; /* FFDBR_FFD0_1 */
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| 93 | volatile uint32_t DEVMR_FFD0_1; /* DEVMR_FFD0_1 */
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| 94 | volatile uint8_t dummy269[4]; /* */
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| 95 | volatile uint32_t DEVCR_FFD0_1; /* DEVCR_FFD0_1 */
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| 96 | /* end of struct st_scux_from_ffdir_ffd0_n */
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| 97 | volatile uint8_t dummy270[224]; /* */
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| 98 | /* start of struct st_scux_from_ffdir_ffd0_n */
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| 99 | volatile uint32_t FFDIR_FFD0_2; /* FFDIR_FFD0_2 */
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| 100 | volatile uint32_t FDAIR_FFD0_2; /* FDAIR_FFD0_2 */
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| 101 | volatile uint32_t DRQSR_FFD0_2; /* DRQSR_FFD0_2 */
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| 102 | volatile uint32_t FFDPR_FFD0_2; /* FFDPR_FFD0_2 */
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| 103 | volatile uint32_t FFDBR_FFD0_2; /* FFDBR_FFD0_2 */
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| 104 | volatile uint32_t DEVMR_FFD0_2; /* DEVMR_FFD0_2 */
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| 105 | volatile uint8_t dummy271[4]; /* */
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| 106 | volatile uint32_t DEVCR_FFD0_2; /* DEVCR_FFD0_2 */
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| 107 | /* end of struct st_scux_from_ffdir_ffd0_n */
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| 108 | volatile uint8_t dummy272[224]; /* */
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| 109 | /* start of struct st_scux_from_ffdir_ffd0_n */
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| 110 | volatile uint32_t FFDIR_FFD0_3; /* FFDIR_FFD0_3 */
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| 111 | volatile uint32_t FDAIR_FFD0_3; /* FDAIR_FFD0_3 */
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| 112 | volatile uint32_t DRQSR_FFD0_3; /* DRQSR_FFD0_3 */
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| 113 | volatile uint32_t FFDPR_FFD0_3; /* FFDPR_FFD0_3 */
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| 114 | volatile uint32_t FFDBR_FFD0_3; /* FFDBR_FFD0_3 */
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| 115 | volatile uint32_t DEVMR_FFD0_3; /* DEVMR_FFD0_3 */
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| 116 | volatile uint8_t dummy273[4]; /* */
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| 117 | volatile uint32_t DEVCR_FFD0_3; /* DEVCR_FFD0_3 */
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| 118 | /* end of struct st_scux_from_ffdir_ffd0_n */
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| 119 | volatile uint8_t dummy274[224]; /* */
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| 120 | /* start of struct st_scux_from_ffuir_ffu0_n */
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| 121 | volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */
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| 122 | volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */
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| 123 | volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */
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| 124 | volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */
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| 125 | volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */
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| 126 | volatile uint8_t dummy275[4]; /* */
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| 127 | volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */
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| 128 | /* end of struct st_scux_from_ffuir_ffu0_n */
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| 129 | volatile uint8_t dummy276[228]; /* */
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| 130 | /* start of struct st_scux_from_ffuir_ffu0_n */
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| 131 | volatile uint32_t FFUIR_FFU0_1; /* FFUIR_FFU0_1 */
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| 132 | volatile uint32_t FUAIR_FFU0_1; /* FUAIR_FFU0_1 */
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| 133 | volatile uint32_t URQSR_FFU0_1; /* URQSR_FFU0_1 */
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| 134 | volatile uint32_t FFUPR_FFU0_1; /* FFUPR_FFU0_1 */
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| 135 | volatile uint32_t UEVMR_FFU0_1; /* UEVMR_FFU0_1 */
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| 136 | volatile uint8_t dummy277[4]; /* */
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| 137 | volatile uint32_t UEVCR_FFU0_1; /* UEVCR_FFU0_1 */
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| 138 | /* end of struct st_scux_from_ffuir_ffu0_n */
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| 139 | volatile uint8_t dummy278[228]; /* */
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| 140 | /* start of struct st_scux_from_ffuir_ffu0_n */
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| 141 | volatile uint32_t FFUIR_FFU0_2; /* FFUIR_FFU0_2 */
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| 142 | volatile uint32_t FUAIR_FFU0_2; /* FUAIR_FFU0_2 */
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| 143 | volatile uint32_t URQSR_FFU0_2; /* URQSR_FFU0_2 */
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| 144 | volatile uint32_t FFUPR_FFU0_2; /* FFUPR_FFU0_2 */
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| 145 | volatile uint32_t UEVMR_FFU0_2; /* UEVMR_FFU0_2 */
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| 146 | volatile uint8_t dummy279[4]; /* */
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| 147 | volatile uint32_t UEVCR_FFU0_2; /* UEVCR_FFU0_2 */
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| 148 | /* end of struct st_scux_from_ffuir_ffu0_n */
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| 149 | volatile uint8_t dummy280[228]; /* */
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| 150 | /* start of struct st_scux_from_ffuir_ffu0_n */
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| 151 | volatile uint32_t FFUIR_FFU0_3; /* FFUIR_FFU0_3 */
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| 152 | volatile uint32_t FUAIR_FFU0_3; /* FUAIR_FFU0_3 */
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| 153 | volatile uint32_t URQSR_FFU0_3; /* URQSR_FFU0_3 */
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| 154 | volatile uint32_t FFUPR_FFU0_3; /* FFUPR_FFU0_3 */
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| 155 | volatile uint32_t UEVMR_FFU0_3; /* UEVMR_FFU0_3 */
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| 156 | volatile uint8_t dummy281[4]; /* */
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| 157 | volatile uint32_t UEVCR_FFU0_3; /* UEVCR_FFU0_3 */
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| 158 | /* end of struct st_scux_from_ffuir_ffu0_n */
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| 159 | volatile uint8_t dummy282[228]; /* */
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| 160 | /* start of struct st_scux_from_srcir0_2src0_n */
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| 161 | volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */
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| 162 | volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */
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| 163 | volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */
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| 164 | volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */
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| 165 | volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */
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| 166 | volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */
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| 167 | volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */
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| 168 | volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */
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| 169 | volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */
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| 170 | volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */
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| 171 | volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */
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| 172 | volatile uint8_t dummy283[4]; /* */
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| 173 | volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */
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| 174 | volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */
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| 175 | volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */
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| 176 | volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */
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| 177 | volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */
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| 178 | volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */
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| 179 | volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */
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| 180 | volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */
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| 181 | volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */
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| 182 | volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */
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| 183 | volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */
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| 184 | volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */
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| 185 | volatile uint8_t dummy284[4]; /* */
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| 186 | volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */
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| 187 | volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */
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| 188 | /* end of struct st_scux_from_srcir0_2src0_n */
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| 189 | volatile uint8_t dummy285[148]; /* */
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| 190 | /* start of struct st_scux_from_srcir0_2src0_n */
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| 191 | volatile uint32_t SRCIR0_2SRC0_1; /* SRCIR0_2SRC0_1 */
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| 192 | volatile uint32_t SADIR0_2SRC0_1; /* SADIR0_2SRC0_1 */
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| 193 | volatile uint32_t SRCBR0_2SRC0_1; /* SRCBR0_2SRC0_1 */
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| 194 | volatile uint32_t IFSCR0_2SRC0_1; /* IFSCR0_2SRC0_1 */
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| 195 | volatile uint32_t IFSVR0_2SRC0_1; /* IFSVR0_2SRC0_1 */
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| 196 | volatile uint32_t SRCCR0_2SRC0_1; /* SRCCR0_2SRC0_1 */
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| 197 | volatile uint32_t MNFSR0_2SRC0_1; /* MNFSR0_2SRC0_1 */
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| 198 | volatile uint32_t BFSSR0_2SRC0_1; /* BFSSR0_2SRC0_1 */
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| 199 | volatile uint32_t SC2SR0_2SRC0_1; /* SC2SR0_2SRC0_1 */
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| 200 | volatile uint32_t WATSR0_2SRC0_1; /* WATSR0_2SRC0_1 */
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| 201 | volatile uint32_t SEVMR0_2SRC0_1; /* SEVMR0_2SRC0_1 */
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| 202 | volatile uint8_t dummy286[4]; /* */
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| 203 | volatile uint32_t SEVCR0_2SRC0_1; /* SEVCR0_2SRC0_1 */
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| 204 | volatile uint32_t SRCIR1_2SRC0_1; /* SRCIR1_2SRC0_1 */
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| 205 | volatile uint32_t SADIR1_2SRC0_1; /* SADIR1_2SRC0_1 */
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| 206 | volatile uint32_t SRCBR1_2SRC0_1; /* SRCBR1_2SRC0_1 */
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| 207 | volatile uint32_t IFSCR1_2SRC0_1; /* IFSCR1_2SRC0_1 */
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| 208 | volatile uint32_t IFSVR1_2SRC0_1; /* IFSVR1_2SRC0_1 */
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| 209 | volatile uint32_t SRCCR1_2SRC0_1; /* SRCCR1_2SRC0_1 */
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| 210 | volatile uint32_t MNFSR1_2SRC0_1; /* MNFSR1_2SRC0_1 */
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| 211 | volatile uint32_t BFSSR1_2SRC0_1; /* BFSSR1_2SRC0_1 */
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| 212 | volatile uint32_t SC2SR1_2SRC0_1; /* SC2SR1_2SRC0_1 */
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| 213 | volatile uint32_t WATSR1_2SRC0_1; /* WATSR1_2SRC0_1 */
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| 214 | volatile uint32_t SEVMR1_2SRC0_1; /* SEVMR1_2SRC0_1 */
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| 215 | volatile uint8_t dummy287[4]; /* */
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| 216 | volatile uint32_t SEVCR1_2SRC0_1; /* SEVCR1_2SRC0_1 */
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| 217 | volatile uint32_t SRCIRR_2SRC0_1; /* SRCIRR_2SRC0_1 */
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| 218 | /* end of struct st_scux_from_srcir0_2src0_n */
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| 219 | volatile uint8_t dummy288[148]; /* */
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| 220 | /* start of struct st_scux_from_dvuir_dvu0_n */
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| 221 | volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */
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| 222 | volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */
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| 223 | volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */
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| 224 | volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */
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| 225 | volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */
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| 226 | volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */
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| 227 | volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */
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| 228 | volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */
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| 229 | volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */
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| 230 | volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */
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| 231 | volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */
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| 232 | volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */
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| 233 | volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */
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| 234 | volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */
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| 235 | volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */
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| 236 | volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */
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| 237 | volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */
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| 238 | volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */
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| 239 | volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */
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| 240 | volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */
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| 241 | volatile uint8_t dummy289[4]; /* */
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| 242 | volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */
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| 243 | /* end of struct st_scux_from_dvuir_dvu0_n */
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| 244 | volatile uint8_t dummy290[168]; /* */
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| 245 | /* start of struct st_scux_from_dvuir_dvu0_n */
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| 246 | volatile uint32_t DVUIR_DVU0_1; /* DVUIR_DVU0_1 */
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| 247 | volatile uint32_t VADIR_DVU0_1; /* VADIR_DVU0_1 */
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| 248 | volatile uint32_t DVUBR_DVU0_1; /* DVUBR_DVU0_1 */
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| 249 | volatile uint32_t DVUCR_DVU0_1; /* DVUCR_DVU0_1 */
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| 250 | volatile uint32_t ZCMCR_DVU0_1; /* ZCMCR_DVU0_1 */
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| 251 | volatile uint32_t VRCTR_DVU0_1; /* VRCTR_DVU0_1 */
|
---|
| 252 | volatile uint32_t VRPDR_DVU0_1; /* VRPDR_DVU0_1 */
|
---|
| 253 | volatile uint32_t VRDBR_DVU0_1; /* VRDBR_DVU0_1 */
|
---|
| 254 | volatile uint32_t VRWTR_DVU0_1; /* VRWTR_DVU0_1 */
|
---|
| 255 | volatile uint32_t VOL0R_DVU0_1; /* VOL0R_DVU0_1 */
|
---|
| 256 | volatile uint32_t VOL1R_DVU0_1; /* VOL1R_DVU0_1 */
|
---|
| 257 | volatile uint32_t VOL2R_DVU0_1; /* VOL2R_DVU0_1 */
|
---|
| 258 | volatile uint32_t VOL3R_DVU0_1; /* VOL3R_DVU0_1 */
|
---|
| 259 | volatile uint32_t VOL4R_DVU0_1; /* VOL4R_DVU0_1 */
|
---|
| 260 | volatile uint32_t VOL5R_DVU0_1; /* VOL5R_DVU0_1 */
|
---|
| 261 | volatile uint32_t VOL6R_DVU0_1; /* VOL6R_DVU0_1 */
|
---|
| 262 | volatile uint32_t VOL7R_DVU0_1; /* VOL7R_DVU0_1 */
|
---|
| 263 | volatile uint32_t DVUER_DVU0_1; /* DVUER_DVU0_1 */
|
---|
| 264 | volatile uint32_t DVUSR_DVU0_1; /* DVUSR_DVU0_1 */
|
---|
| 265 | volatile uint32_t VEVMR_DVU0_1; /* VEVMR_DVU0_1 */
|
---|
| 266 | volatile uint8_t dummy291[4]; /* */
|
---|
| 267 | volatile uint32_t VEVCR_DVU0_1; /* VEVCR_DVU0_1 */
|
---|
| 268 | /* end of struct st_scux_from_dvuir_dvu0_n */
|
---|
| 269 | volatile uint8_t dummy292[168]; /* */
|
---|
| 270 | /* start of struct st_scux_from_dvuir_dvu0_n */
|
---|
| 271 | volatile uint32_t DVUIR_DVU0_2; /* DVUIR_DVU0_2 */
|
---|
| 272 | volatile uint32_t VADIR_DVU0_2; /* VADIR_DVU0_2 */
|
---|
| 273 | volatile uint32_t DVUBR_DVU0_2; /* DVUBR_DVU0_2 */
|
---|
| 274 | volatile uint32_t DVUCR_DVU0_2; /* DVUCR_DVU0_2 */
|
---|
| 275 | volatile uint32_t ZCMCR_DVU0_2; /* ZCMCR_DVU0_2 */
|
---|
| 276 | volatile uint32_t VRCTR_DVU0_2; /* VRCTR_DVU0_2 */
|
---|
| 277 | volatile uint32_t VRPDR_DVU0_2; /* VRPDR_DVU0_2 */
|
---|
| 278 | volatile uint32_t VRDBR_DVU0_2; /* VRDBR_DVU0_2 */
|
---|
| 279 | volatile uint32_t VRWTR_DVU0_2; /* VRWTR_DVU0_2 */
|
---|
| 280 | volatile uint32_t VOL0R_DVU0_2; /* VOL0R_DVU0_2 */
|
---|
| 281 | volatile uint32_t VOL1R_DVU0_2; /* VOL1R_DVU0_2 */
|
---|
| 282 | volatile uint32_t VOL2R_DVU0_2; /* VOL2R_DVU0_2 */
|
---|
| 283 | volatile uint32_t VOL3R_DVU0_2; /* VOL3R_DVU0_2 */
|
---|
| 284 | volatile uint32_t VOL4R_DVU0_2; /* VOL4R_DVU0_2 */
|
---|
| 285 | volatile uint32_t VOL5R_DVU0_2; /* VOL5R_DVU0_2 */
|
---|
| 286 | volatile uint32_t VOL6R_DVU0_2; /* VOL6R_DVU0_2 */
|
---|
| 287 | volatile uint32_t VOL7R_DVU0_2; /* VOL7R_DVU0_2 */
|
---|
| 288 | volatile uint32_t DVUER_DVU0_2; /* DVUER_DVU0_2 */
|
---|
| 289 | volatile uint32_t DVUSR_DVU0_2; /* DVUSR_DVU0_2 */
|
---|
| 290 | volatile uint32_t VEVMR_DVU0_2; /* VEVMR_DVU0_2 */
|
---|
| 291 | volatile uint8_t dummy293[4]; /* */
|
---|
| 292 | volatile uint32_t VEVCR_DVU0_2; /* VEVCR_DVU0_2 */
|
---|
| 293 | /* end of struct st_scux_from_dvuir_dvu0_n */
|
---|
| 294 | volatile uint8_t dummy294[168]; /* */
|
---|
| 295 | /* start of struct st_scux_from_dvuir_dvu0_n */
|
---|
| 296 | volatile uint32_t DVUIR_DVU0_3; /* DVUIR_DVU0_3 */
|
---|
| 297 | volatile uint32_t VADIR_DVU0_3; /* VADIR_DVU0_3 */
|
---|
| 298 | volatile uint32_t DVUBR_DVU0_3; /* DVUBR_DVU0_3 */
|
---|
| 299 | volatile uint32_t DVUCR_DVU0_3; /* DVUCR_DVU0_3 */
|
---|
| 300 | volatile uint32_t ZCMCR_DVU0_3; /* ZCMCR_DVU0_3 */
|
---|
| 301 | volatile uint32_t VRCTR_DVU0_3; /* VRCTR_DVU0_3 */
|
---|
| 302 | volatile uint32_t VRPDR_DVU0_3; /* VRPDR_DVU0_3 */
|
---|
| 303 | volatile uint32_t VRDBR_DVU0_3; /* VRDBR_DVU0_3 */
|
---|
| 304 | volatile uint32_t VRWTR_DVU0_3; /* VRWTR_DVU0_3 */
|
---|
| 305 | volatile uint32_t VOL0R_DVU0_3; /* VOL0R_DVU0_3 */
|
---|
| 306 | volatile uint32_t VOL1R_DVU0_3; /* VOL1R_DVU0_3 */
|
---|
| 307 | volatile uint32_t VOL2R_DVU0_3; /* VOL2R_DVU0_3 */
|
---|
| 308 | volatile uint32_t VOL3R_DVU0_3; /* VOL3R_DVU0_3 */
|
---|
| 309 | volatile uint32_t VOL4R_DVU0_3; /* VOL4R_DVU0_3 */
|
---|
| 310 | volatile uint32_t VOL5R_DVU0_3; /* VOL5R_DVU0_3 */
|
---|
| 311 | volatile uint32_t VOL6R_DVU0_3; /* VOL6R_DVU0_3 */
|
---|
| 312 | volatile uint32_t VOL7R_DVU0_3; /* VOL7R_DVU0_3 */
|
---|
| 313 | volatile uint32_t DVUER_DVU0_3; /* DVUER_DVU0_3 */
|
---|
| 314 | volatile uint32_t DVUSR_DVU0_3; /* DVUSR_DVU0_3 */
|
---|
| 315 | volatile uint32_t VEVMR_DVU0_3; /* VEVMR_DVU0_3 */
|
---|
| 316 | volatile uint8_t dummy295[4]; /* */
|
---|
| 317 | volatile uint32_t VEVCR_DVU0_3; /* VEVCR_DVU0_3 */
|
---|
| 318 | /* end of struct st_scux_from_dvuir_dvu0_n */
|
---|
| 319 | volatile uint8_t dummy296[168]; /* */
|
---|
| 320 | volatile uint32_t MIXIR_MIX0_0; /* MIXIR_MIX0_0 */
|
---|
| 321 | volatile uint32_t MADIR_MIX0_0; /* MADIR_MIX0_0 */
|
---|
| 322 | volatile uint32_t MIXBR_MIX0_0; /* MIXBR_MIX0_0 */
|
---|
| 323 | volatile uint32_t MIXMR_MIX0_0; /* MIXMR_MIX0_0 */
|
---|
| 324 | volatile uint32_t MVPDR_MIX0_0; /* MVPDR_MIX0_0 */
|
---|
| 325 | volatile uint32_t MDBAR_MIX0_0; /* MDBAR_MIX0_0 */
|
---|
| 326 | volatile uint32_t MDBBR_MIX0_0; /* MDBBR_MIX0_0 */
|
---|
| 327 | volatile uint32_t MDBCR_MIX0_0; /* MDBCR_MIX0_0 */
|
---|
| 328 | volatile uint32_t MDBDR_MIX0_0; /* MDBDR_MIX0_0 */
|
---|
| 329 | volatile uint32_t MDBER_MIX0_0; /* MDBER_MIX0_0 */
|
---|
| 330 | volatile uint32_t MIXSR_MIX0_0; /* MIXSR_MIX0_0 */
|
---|
| 331 | volatile uint8_t dummy297[212]; /* */
|
---|
| 332 | volatile uint32_t SWRSR_CIM; /* SWRSR_CIM */
|
---|
| 333 | volatile uint32_t DMACR_CIM; /* DMACR_CIM */
|
---|
| 334 | #define SCUX_DMATDn_CIM_COUNT 4
|
---|
| 335 | union iodefine_reg32_16_t DMATD0_CIM; /* DMATD0_CIM */
|
---|
| 336 | union iodefine_reg32_16_t DMATD1_CIM; /* DMATD1_CIM */
|
---|
| 337 | union iodefine_reg32_16_t DMATD2_CIM; /* DMATD2_CIM */
|
---|
| 338 | union iodefine_reg32_16_t DMATD3_CIM; /* DMATD3_CIM */
|
---|
| 339 | #define SCUX_DMATUn_CIM_COUNT 4
|
---|
| 340 | union iodefine_reg32_16_t DMATU0_CIM; /* DMATU0_CIM */
|
---|
| 341 | union iodefine_reg32_16_t DMATU1_CIM; /* DMATU1_CIM */
|
---|
| 342 | union iodefine_reg32_16_t DMATU2_CIM; /* DMATU2_CIM */
|
---|
| 343 | union iodefine_reg32_16_t DMATU3_CIM; /* DMATU3_CIM */
|
---|
| 344 |
|
---|
| 345 | volatile uint8_t dummy298[16]; /* */
|
---|
| 346 | volatile uint32_t SSIRSEL_CIM; /* SSIRSEL_CIM */
|
---|
| 347 | #define SCUX_FDTSELn_CIM_COUNT 4
|
---|
| 348 | volatile uint32_t FDTSEL0_CIM; /* FDTSEL0_CIM */
|
---|
| 349 | volatile uint32_t FDTSEL1_CIM; /* FDTSEL1_CIM */
|
---|
| 350 | volatile uint32_t FDTSEL2_CIM; /* FDTSEL2_CIM */
|
---|
| 351 | volatile uint32_t FDTSEL3_CIM; /* FDTSEL3_CIM */
|
---|
| 352 | #define SCUX_FUTSELn_CIM_COUNT 4
|
---|
| 353 | volatile uint32_t FUTSEL0_CIM; /* FUTSEL0_CIM */
|
---|
| 354 | volatile uint32_t FUTSEL1_CIM; /* FUTSEL1_CIM */
|
---|
| 355 | volatile uint32_t FUTSEL2_CIM; /* FUTSEL2_CIM */
|
---|
| 356 | volatile uint32_t FUTSEL3_CIM; /* FUTSEL3_CIM */
|
---|
| 357 | volatile uint32_t SSIPMD_CIM; /* SSIPMD_CIM */
|
---|
| 358 | volatile uint32_t SSICTRL_CIM; /* SSICTRL_CIM */
|
---|
| 359 | #define SCUX_SRCRSELn_CIM_COUNT 4
|
---|
| 360 | volatile uint32_t SRCRSEL0_CIM; /* SRCRSEL0_CIM */
|
---|
| 361 | volatile uint32_t SRCRSEL1_CIM; /* SRCRSEL1_CIM */
|
---|
| 362 | volatile uint32_t SRCRSEL2_CIM; /* SRCRSEL2_CIM */
|
---|
| 363 | volatile uint32_t SRCRSEL3_CIM; /* SRCRSEL3_CIM */
|
---|
| 364 | volatile uint32_t MIXRSEL_CIM; /* MIXRSEL_CIM */
|
---|
| 365 | };
|
---|
| 366 |
|
---|
| 367 |
|
---|
| 368 | struct st_scux_from_ipcir_ipc0_n
|
---|
| 369 | {
|
---|
| 370 | volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */
|
---|
| 371 | volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */
|
---|
| 372 | volatile uint8_t dummy1[248]; /* */
|
---|
| 373 | };
|
---|
| 374 |
|
---|
| 375 |
|
---|
| 376 | struct st_scux_from_opcir_opc0_n
|
---|
| 377 | {
|
---|
| 378 | volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */
|
---|
| 379 | volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */
|
---|
| 380 | volatile uint8_t dummy1[248]; /* */
|
---|
| 381 | };
|
---|
| 382 |
|
---|
| 383 |
|
---|
| 384 | struct st_scux_from_ffdir_ffd0_n
|
---|
| 385 | {
|
---|
| 386 | volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */
|
---|
| 387 | volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */
|
---|
| 388 | volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */
|
---|
| 389 | volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */
|
---|
| 390 | volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */
|
---|
| 391 | volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */
|
---|
| 392 | volatile uint8_t dummy1[4]; /* */
|
---|
| 393 | volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */
|
---|
| 394 | };
|
---|
| 395 |
|
---|
| 396 |
|
---|
| 397 | struct st_scux_from_ffuir_ffu0_n
|
---|
| 398 | {
|
---|
| 399 | volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */
|
---|
| 400 | volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */
|
---|
| 401 | volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */
|
---|
| 402 | volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */
|
---|
| 403 | volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */
|
---|
| 404 | volatile uint8_t dummy1[4]; /* */
|
---|
| 405 | volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */
|
---|
| 406 | };
|
---|
| 407 |
|
---|
| 408 |
|
---|
| 409 | struct st_scux_from_srcir0_2src0_n
|
---|
| 410 | {
|
---|
| 411 | volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */
|
---|
| 412 | volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */
|
---|
| 413 | volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */
|
---|
| 414 | volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */
|
---|
| 415 | volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */
|
---|
| 416 | volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */
|
---|
| 417 | volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */
|
---|
| 418 | volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */
|
---|
| 419 | volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */
|
---|
| 420 | volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */
|
---|
| 421 | volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */
|
---|
| 422 | volatile uint8_t dummy1[4]; /* */
|
---|
| 423 | volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */
|
---|
| 424 | volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */
|
---|
| 425 | volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */
|
---|
| 426 | volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */
|
---|
| 427 | volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */
|
---|
| 428 | volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */
|
---|
| 429 | volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */
|
---|
| 430 | volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */
|
---|
| 431 | volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */
|
---|
| 432 | volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */
|
---|
| 433 | volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */
|
---|
| 434 | volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */
|
---|
| 435 | volatile uint8_t dummy2[4]; /* */
|
---|
| 436 | volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */
|
---|
| 437 | volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */
|
---|
| 438 | };
|
---|
| 439 |
|
---|
| 440 |
|
---|
| 441 | struct st_scux_from_dvuir_dvu0_n
|
---|
| 442 | {
|
---|
| 443 | volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */
|
---|
| 444 | volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */
|
---|
| 445 | volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */
|
---|
| 446 | volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */
|
---|
| 447 | volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */
|
---|
| 448 | volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */
|
---|
| 449 | volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */
|
---|
| 450 | volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */
|
---|
| 451 | volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */
|
---|
| 452 | volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */
|
---|
| 453 | volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */
|
---|
| 454 | volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */
|
---|
| 455 | volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */
|
---|
| 456 | volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */
|
---|
| 457 | volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */
|
---|
| 458 | volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */
|
---|
| 459 | volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */
|
---|
| 460 | volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */
|
---|
| 461 | volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */
|
---|
| 462 | volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */
|
---|
| 463 | volatile uint8_t dummy1[4]; /* */
|
---|
| 464 | volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */
|
---|
| 465 | };
|
---|
| 466 |
|
---|
| 467 |
|
---|
| 468 | #define SCUX (*(struct st_scux *)0xE8208000uL) /* SCUX */
|
---|
| 469 |
|
---|
| 470 |
|
---|
| 471 | /* Start of channnel array defines of SCUX */
|
---|
| 472 |
|
---|
| 473 | /* Channnel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */
|
---|
| 474 | /*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */
|
---|
| 475 | #define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT 4
|
---|
| 476 | #define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \
|
---|
| 477 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
|
---|
| 478 | &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \
|
---|
| 479 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
|
---|
| 480 | #define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */
|
---|
| 481 | #define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */
|
---|
| 482 | #define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */
|
---|
| 483 | #define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */
|
---|
| 484 |
|
---|
| 485 |
|
---|
| 486 | /* Channnel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */
|
---|
| 487 | /*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */
|
---|
| 488 | #define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT 2
|
---|
| 489 | #define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \
|
---|
| 490 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
|
---|
| 491 | &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \
|
---|
| 492 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
|
---|
| 493 | #define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */
|
---|
| 494 | #define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */
|
---|
| 495 |
|
---|
| 496 |
|
---|
| 497 | /* Channnel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */
|
---|
| 498 | /*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */
|
---|
| 499 | #define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT 4
|
---|
| 500 | #define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \
|
---|
| 501 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
|
---|
| 502 | &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \
|
---|
| 503 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
|
---|
| 504 | #define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */
|
---|
| 505 | #define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */
|
---|
| 506 | #define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */
|
---|
| 507 | #define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */
|
---|
| 508 |
|
---|
| 509 |
|
---|
| 510 | /* Channnel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */
|
---|
| 511 | /*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */
|
---|
| 512 | #define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT 4
|
---|
| 513 | #define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \
|
---|
| 514 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
|
---|
| 515 | &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \
|
---|
| 516 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
|
---|
| 517 | #define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */
|
---|
| 518 | #define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */
|
---|
| 519 | #define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */
|
---|
| 520 | #define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */
|
---|
| 521 |
|
---|
| 522 |
|
---|
| 523 | /* Channnel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */
|
---|
| 524 | /*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */
|
---|
| 525 | #define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT 4
|
---|
| 526 | #define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \
|
---|
| 527 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
|
---|
| 528 | &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \
|
---|
| 529 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
|
---|
| 530 | #define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */
|
---|
| 531 | #define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */
|
---|
| 532 | #define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */
|
---|
| 533 | #define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */
|
---|
| 534 |
|
---|
| 535 |
|
---|
| 536 | /* Channnel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */
|
---|
| 537 | /*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */
|
---|
| 538 | #define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT 4
|
---|
| 539 | #define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \
|
---|
| 540 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
|
---|
| 541 | &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \
|
---|
| 542 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
|
---|
| 543 | #define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */
|
---|
| 544 | #define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */
|
---|
| 545 | #define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */
|
---|
| 546 | #define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */
|
---|
| 547 |
|
---|
| 548 | /* End of channnel array defines of SCUX */
|
---|
| 549 |
|
---|
| 550 |
|
---|
| 551 | #define SCUXIPCIR_IPC0_0 SCUX.IPCIR_IPC0_0
|
---|
| 552 | #define SCUXIPSLR_IPC0_0 SCUX.IPSLR_IPC0_0
|
---|
| 553 | #define SCUXIPCIR_IPC0_1 SCUX.IPCIR_IPC0_1
|
---|
| 554 | #define SCUXIPSLR_IPC0_1 SCUX.IPSLR_IPC0_1
|
---|
| 555 | #define SCUXIPCIR_IPC0_2 SCUX.IPCIR_IPC0_2
|
---|
| 556 | #define SCUXIPSLR_IPC0_2 SCUX.IPSLR_IPC0_2
|
---|
| 557 | #define SCUXIPCIR_IPC0_3 SCUX.IPCIR_IPC0_3
|
---|
| 558 | #define SCUXIPSLR_IPC0_3 SCUX.IPSLR_IPC0_3
|
---|
| 559 | #define SCUXOPCIR_OPC0_0 SCUX.OPCIR_OPC0_0
|
---|
| 560 | #define SCUXOPSLR_OPC0_0 SCUX.OPSLR_OPC0_0
|
---|
| 561 | #define SCUXOPCIR_OPC0_1 SCUX.OPCIR_OPC0_1
|
---|
| 562 | #define SCUXOPSLR_OPC0_1 SCUX.OPSLR_OPC0_1
|
---|
| 563 | #define SCUXOPCIR_OPC0_2 SCUX.OPCIR_OPC0_2
|
---|
| 564 | #define SCUXOPSLR_OPC0_2 SCUX.OPSLR_OPC0_2
|
---|
| 565 | #define SCUXOPCIR_OPC0_3 SCUX.OPCIR_OPC0_3
|
---|
| 566 | #define SCUXOPSLR_OPC0_3 SCUX.OPSLR_OPC0_3
|
---|
| 567 | #define SCUXFFDIR_FFD0_0 SCUX.FFDIR_FFD0_0
|
---|
| 568 | #define SCUXFDAIR_FFD0_0 SCUX.FDAIR_FFD0_0
|
---|
| 569 | #define SCUXDRQSR_FFD0_0 SCUX.DRQSR_FFD0_0
|
---|
| 570 | #define SCUXFFDPR_FFD0_0 SCUX.FFDPR_FFD0_0
|
---|
| 571 | #define SCUXFFDBR_FFD0_0 SCUX.FFDBR_FFD0_0
|
---|
| 572 | #define SCUXDEVMR_FFD0_0 SCUX.DEVMR_FFD0_0
|
---|
| 573 | #define SCUXDEVCR_FFD0_0 SCUX.DEVCR_FFD0_0
|
---|
| 574 | #define SCUXFFDIR_FFD0_1 SCUX.FFDIR_FFD0_1
|
---|
| 575 | #define SCUXFDAIR_FFD0_1 SCUX.FDAIR_FFD0_1
|
---|
| 576 | #define SCUXDRQSR_FFD0_1 SCUX.DRQSR_FFD0_1
|
---|
| 577 | #define SCUXFFDPR_FFD0_1 SCUX.FFDPR_FFD0_1
|
---|
| 578 | #define SCUXFFDBR_FFD0_1 SCUX.FFDBR_FFD0_1
|
---|
| 579 | #define SCUXDEVMR_FFD0_1 SCUX.DEVMR_FFD0_1
|
---|
| 580 | #define SCUXDEVCR_FFD0_1 SCUX.DEVCR_FFD0_1
|
---|
| 581 | #define SCUXFFDIR_FFD0_2 SCUX.FFDIR_FFD0_2
|
---|
| 582 | #define SCUXFDAIR_FFD0_2 SCUX.FDAIR_FFD0_2
|
---|
| 583 | #define SCUXDRQSR_FFD0_2 SCUX.DRQSR_FFD0_2
|
---|
| 584 | #define SCUXFFDPR_FFD0_2 SCUX.FFDPR_FFD0_2
|
---|
| 585 | #define SCUXFFDBR_FFD0_2 SCUX.FFDBR_FFD0_2
|
---|
| 586 | #define SCUXDEVMR_FFD0_2 SCUX.DEVMR_FFD0_2
|
---|
| 587 | #define SCUXDEVCR_FFD0_2 SCUX.DEVCR_FFD0_2
|
---|
| 588 | #define SCUXFFDIR_FFD0_3 SCUX.FFDIR_FFD0_3
|
---|
| 589 | #define SCUXFDAIR_FFD0_3 SCUX.FDAIR_FFD0_3
|
---|
| 590 | #define SCUXDRQSR_FFD0_3 SCUX.DRQSR_FFD0_3
|
---|
| 591 | #define SCUXFFDPR_FFD0_3 SCUX.FFDPR_FFD0_3
|
---|
| 592 | #define SCUXFFDBR_FFD0_3 SCUX.FFDBR_FFD0_3
|
---|
| 593 | #define SCUXDEVMR_FFD0_3 SCUX.DEVMR_FFD0_3
|
---|
| 594 | #define SCUXDEVCR_FFD0_3 SCUX.DEVCR_FFD0_3
|
---|
| 595 | #define SCUXFFUIR_FFU0_0 SCUX.FFUIR_FFU0_0
|
---|
| 596 | #define SCUXFUAIR_FFU0_0 SCUX.FUAIR_FFU0_0
|
---|
| 597 | #define SCUXURQSR_FFU0_0 SCUX.URQSR_FFU0_0
|
---|
| 598 | #define SCUXFFUPR_FFU0_0 SCUX.FFUPR_FFU0_0
|
---|
| 599 | #define SCUXUEVMR_FFU0_0 SCUX.UEVMR_FFU0_0
|
---|
| 600 | #define SCUXUEVCR_FFU0_0 SCUX.UEVCR_FFU0_0
|
---|
| 601 | #define SCUXFFUIR_FFU0_1 SCUX.FFUIR_FFU0_1
|
---|
| 602 | #define SCUXFUAIR_FFU0_1 SCUX.FUAIR_FFU0_1
|
---|
| 603 | #define SCUXURQSR_FFU0_1 SCUX.URQSR_FFU0_1
|
---|
| 604 | #define SCUXFFUPR_FFU0_1 SCUX.FFUPR_FFU0_1
|
---|
| 605 | #define SCUXUEVMR_FFU0_1 SCUX.UEVMR_FFU0_1
|
---|
| 606 | #define SCUXUEVCR_FFU0_1 SCUX.UEVCR_FFU0_1
|
---|
| 607 | #define SCUXFFUIR_FFU0_2 SCUX.FFUIR_FFU0_2
|
---|
| 608 | #define SCUXFUAIR_FFU0_2 SCUX.FUAIR_FFU0_2
|
---|
| 609 | #define SCUXURQSR_FFU0_2 SCUX.URQSR_FFU0_2
|
---|
| 610 | #define SCUXFFUPR_FFU0_2 SCUX.FFUPR_FFU0_2
|
---|
| 611 | #define SCUXUEVMR_FFU0_2 SCUX.UEVMR_FFU0_2
|
---|
| 612 | #define SCUXUEVCR_FFU0_2 SCUX.UEVCR_FFU0_2
|
---|
| 613 | #define SCUXFFUIR_FFU0_3 SCUX.FFUIR_FFU0_3
|
---|
| 614 | #define SCUXFUAIR_FFU0_3 SCUX.FUAIR_FFU0_3
|
---|
| 615 | #define SCUXURQSR_FFU0_3 SCUX.URQSR_FFU0_3
|
---|
| 616 | #define SCUXFFUPR_FFU0_3 SCUX.FFUPR_FFU0_3
|
---|
| 617 | #define SCUXUEVMR_FFU0_3 SCUX.UEVMR_FFU0_3
|
---|
| 618 | #define SCUXUEVCR_FFU0_3 SCUX.UEVCR_FFU0_3
|
---|
| 619 | #define SCUXSRCIR0_2SRC0_0 SCUX.SRCIR0_2SRC0_0
|
---|
| 620 | #define SCUXSADIR0_2SRC0_0 SCUX.SADIR0_2SRC0_0
|
---|
| 621 | #define SCUXSRCBR0_2SRC0_0 SCUX.SRCBR0_2SRC0_0
|
---|
| 622 | #define SCUXIFSCR0_2SRC0_0 SCUX.IFSCR0_2SRC0_0
|
---|
| 623 | #define SCUXIFSVR0_2SRC0_0 SCUX.IFSVR0_2SRC0_0
|
---|
| 624 | #define SCUXSRCCR0_2SRC0_0 SCUX.SRCCR0_2SRC0_0
|
---|
| 625 | #define SCUXMNFSR0_2SRC0_0 SCUX.MNFSR0_2SRC0_0
|
---|
| 626 | #define SCUXBFSSR0_2SRC0_0 SCUX.BFSSR0_2SRC0_0
|
---|
| 627 | #define SCUXSC2SR0_2SRC0_0 SCUX.SC2SR0_2SRC0_0
|
---|
| 628 | #define SCUXWATSR0_2SRC0_0 SCUX.WATSR0_2SRC0_0
|
---|
| 629 | #define SCUXSEVMR0_2SRC0_0 SCUX.SEVMR0_2SRC0_0
|
---|
| 630 | #define SCUXSEVCR0_2SRC0_0 SCUX.SEVCR0_2SRC0_0
|
---|
| 631 | #define SCUXSRCIR1_2SRC0_0 SCUX.SRCIR1_2SRC0_0
|
---|
| 632 | #define SCUXSADIR1_2SRC0_0 SCUX.SADIR1_2SRC0_0
|
---|
| 633 | #define SCUXSRCBR1_2SRC0_0 SCUX.SRCBR1_2SRC0_0
|
---|
| 634 | #define SCUXIFSCR1_2SRC0_0 SCUX.IFSCR1_2SRC0_0
|
---|
| 635 | #define SCUXIFSVR1_2SRC0_0 SCUX.IFSVR1_2SRC0_0
|
---|
| 636 | #define SCUXSRCCR1_2SRC0_0 SCUX.SRCCR1_2SRC0_0
|
---|
| 637 | #define SCUXMNFSR1_2SRC0_0 SCUX.MNFSR1_2SRC0_0
|
---|
| 638 | #define SCUXBFSSR1_2SRC0_0 SCUX.BFSSR1_2SRC0_0
|
---|
| 639 | #define SCUXSC2SR1_2SRC0_0 SCUX.SC2SR1_2SRC0_0
|
---|
| 640 | #define SCUXWATSR1_2SRC0_0 SCUX.WATSR1_2SRC0_0
|
---|
| 641 | #define SCUXSEVMR1_2SRC0_0 SCUX.SEVMR1_2SRC0_0
|
---|
| 642 | #define SCUXSEVCR1_2SRC0_0 SCUX.SEVCR1_2SRC0_0
|
---|
| 643 | #define SCUXSRCIRR_2SRC0_0 SCUX.SRCIRR_2SRC0_0
|
---|
| 644 | #define SCUXSRCIR0_2SRC0_1 SCUX.SRCIR0_2SRC0_1
|
---|
| 645 | #define SCUXSADIR0_2SRC0_1 SCUX.SADIR0_2SRC0_1
|
---|
| 646 | #define SCUXSRCBR0_2SRC0_1 SCUX.SRCBR0_2SRC0_1
|
---|
| 647 | #define SCUXIFSCR0_2SRC0_1 SCUX.IFSCR0_2SRC0_1
|
---|
| 648 | #define SCUXIFSVR0_2SRC0_1 SCUX.IFSVR0_2SRC0_1
|
---|
| 649 | #define SCUXSRCCR0_2SRC0_1 SCUX.SRCCR0_2SRC0_1
|
---|
| 650 | #define SCUXMNFSR0_2SRC0_1 SCUX.MNFSR0_2SRC0_1
|
---|
| 651 | #define SCUXBFSSR0_2SRC0_1 SCUX.BFSSR0_2SRC0_1
|
---|
| 652 | #define SCUXSC2SR0_2SRC0_1 SCUX.SC2SR0_2SRC0_1
|
---|
| 653 | #define SCUXWATSR0_2SRC0_1 SCUX.WATSR0_2SRC0_1
|
---|
| 654 | #define SCUXSEVMR0_2SRC0_1 SCUX.SEVMR0_2SRC0_1
|
---|
| 655 | #define SCUXSEVCR0_2SRC0_1 SCUX.SEVCR0_2SRC0_1
|
---|
| 656 | #define SCUXSRCIR1_2SRC0_1 SCUX.SRCIR1_2SRC0_1
|
---|
| 657 | #define SCUXSADIR1_2SRC0_1 SCUX.SADIR1_2SRC0_1
|
---|
| 658 | #define SCUXSRCBR1_2SRC0_1 SCUX.SRCBR1_2SRC0_1
|
---|
| 659 | #define SCUXIFSCR1_2SRC0_1 SCUX.IFSCR1_2SRC0_1
|
---|
| 660 | #define SCUXIFSVR1_2SRC0_1 SCUX.IFSVR1_2SRC0_1
|
---|
| 661 | #define SCUXSRCCR1_2SRC0_1 SCUX.SRCCR1_2SRC0_1
|
---|
| 662 | #define SCUXMNFSR1_2SRC0_1 SCUX.MNFSR1_2SRC0_1
|
---|
| 663 | #define SCUXBFSSR1_2SRC0_1 SCUX.BFSSR1_2SRC0_1
|
---|
| 664 | #define SCUXSC2SR1_2SRC0_1 SCUX.SC2SR1_2SRC0_1
|
---|
| 665 | #define SCUXWATSR1_2SRC0_1 SCUX.WATSR1_2SRC0_1
|
---|
| 666 | #define SCUXSEVMR1_2SRC0_1 SCUX.SEVMR1_2SRC0_1
|
---|
| 667 | #define SCUXSEVCR1_2SRC0_1 SCUX.SEVCR1_2SRC0_1
|
---|
| 668 | #define SCUXSRCIRR_2SRC0_1 SCUX.SRCIRR_2SRC0_1
|
---|
| 669 | #define SCUXDVUIR_DVU0_0 SCUX.DVUIR_DVU0_0
|
---|
| 670 | #define SCUXVADIR_DVU0_0 SCUX.VADIR_DVU0_0
|
---|
| 671 | #define SCUXDVUBR_DVU0_0 SCUX.DVUBR_DVU0_0
|
---|
| 672 | #define SCUXDVUCR_DVU0_0 SCUX.DVUCR_DVU0_0
|
---|
| 673 | #define SCUXZCMCR_DVU0_0 SCUX.ZCMCR_DVU0_0
|
---|
| 674 | #define SCUXVRCTR_DVU0_0 SCUX.VRCTR_DVU0_0
|
---|
| 675 | #define SCUXVRPDR_DVU0_0 SCUX.VRPDR_DVU0_0
|
---|
| 676 | #define SCUXVRDBR_DVU0_0 SCUX.VRDBR_DVU0_0
|
---|
| 677 | #define SCUXVRWTR_DVU0_0 SCUX.VRWTR_DVU0_0
|
---|
| 678 | #define SCUXVOL0R_DVU0_0 SCUX.VOL0R_DVU0_0
|
---|
| 679 | #define SCUXVOL1R_DVU0_0 SCUX.VOL1R_DVU0_0
|
---|
| 680 | #define SCUXVOL2R_DVU0_0 SCUX.VOL2R_DVU0_0
|
---|
| 681 | #define SCUXVOL3R_DVU0_0 SCUX.VOL3R_DVU0_0
|
---|
| 682 | #define SCUXVOL4R_DVU0_0 SCUX.VOL4R_DVU0_0
|
---|
| 683 | #define SCUXVOL5R_DVU0_0 SCUX.VOL5R_DVU0_0
|
---|
| 684 | #define SCUXVOL6R_DVU0_0 SCUX.VOL6R_DVU0_0
|
---|
| 685 | #define SCUXVOL7R_DVU0_0 SCUX.VOL7R_DVU0_0
|
---|
| 686 | #define SCUXDVUER_DVU0_0 SCUX.DVUER_DVU0_0
|
---|
| 687 | #define SCUXDVUSR_DVU0_0 SCUX.DVUSR_DVU0_0
|
---|
| 688 | #define SCUXVEVMR_DVU0_0 SCUX.VEVMR_DVU0_0
|
---|
| 689 | #define SCUXVEVCR_DVU0_0 SCUX.VEVCR_DVU0_0
|
---|
| 690 | #define SCUXDVUIR_DVU0_1 SCUX.DVUIR_DVU0_1
|
---|
| 691 | #define SCUXVADIR_DVU0_1 SCUX.VADIR_DVU0_1
|
---|
| 692 | #define SCUXDVUBR_DVU0_1 SCUX.DVUBR_DVU0_1
|
---|
| 693 | #define SCUXDVUCR_DVU0_1 SCUX.DVUCR_DVU0_1
|
---|
| 694 | #define SCUXZCMCR_DVU0_1 SCUX.ZCMCR_DVU0_1
|
---|
| 695 | #define SCUXVRCTR_DVU0_1 SCUX.VRCTR_DVU0_1
|
---|
| 696 | #define SCUXVRPDR_DVU0_1 SCUX.VRPDR_DVU0_1
|
---|
| 697 | #define SCUXVRDBR_DVU0_1 SCUX.VRDBR_DVU0_1
|
---|
| 698 | #define SCUXVRWTR_DVU0_1 SCUX.VRWTR_DVU0_1
|
---|
| 699 | #define SCUXVOL0R_DVU0_1 SCUX.VOL0R_DVU0_1
|
---|
| 700 | #define SCUXVOL1R_DVU0_1 SCUX.VOL1R_DVU0_1
|
---|
| 701 | #define SCUXVOL2R_DVU0_1 SCUX.VOL2R_DVU0_1
|
---|
| 702 | #define SCUXVOL3R_DVU0_1 SCUX.VOL3R_DVU0_1
|
---|
| 703 | #define SCUXVOL4R_DVU0_1 SCUX.VOL4R_DVU0_1
|
---|
| 704 | #define SCUXVOL5R_DVU0_1 SCUX.VOL5R_DVU0_1
|
---|
| 705 | #define SCUXVOL6R_DVU0_1 SCUX.VOL6R_DVU0_1
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| 706 | #define SCUXVOL7R_DVU0_1 SCUX.VOL7R_DVU0_1
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| 707 | #define SCUXDVUER_DVU0_1 SCUX.DVUER_DVU0_1
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| 708 | #define SCUXDVUSR_DVU0_1 SCUX.DVUSR_DVU0_1
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| 709 | #define SCUXVEVMR_DVU0_1 SCUX.VEVMR_DVU0_1
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| 710 | #define SCUXVEVCR_DVU0_1 SCUX.VEVCR_DVU0_1
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| 711 | #define SCUXDVUIR_DVU0_2 SCUX.DVUIR_DVU0_2
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| 712 | #define SCUXVADIR_DVU0_2 SCUX.VADIR_DVU0_2
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| 713 | #define SCUXDVUBR_DVU0_2 SCUX.DVUBR_DVU0_2
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| 714 | #define SCUXDVUCR_DVU0_2 SCUX.DVUCR_DVU0_2
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| 715 | #define SCUXZCMCR_DVU0_2 SCUX.ZCMCR_DVU0_2
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| 716 | #define SCUXVRCTR_DVU0_2 SCUX.VRCTR_DVU0_2
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| 717 | #define SCUXVRPDR_DVU0_2 SCUX.VRPDR_DVU0_2
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| 718 | #define SCUXVRDBR_DVU0_2 SCUX.VRDBR_DVU0_2
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| 719 | #define SCUXVRWTR_DVU0_2 SCUX.VRWTR_DVU0_2
|
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| 720 | #define SCUXVOL0R_DVU0_2 SCUX.VOL0R_DVU0_2
|
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| 721 | #define SCUXVOL1R_DVU0_2 SCUX.VOL1R_DVU0_2
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| 722 | #define SCUXVOL2R_DVU0_2 SCUX.VOL2R_DVU0_2
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| 723 | #define SCUXVOL3R_DVU0_2 SCUX.VOL3R_DVU0_2
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| 724 | #define SCUXVOL4R_DVU0_2 SCUX.VOL4R_DVU0_2
|
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| 725 | #define SCUXVOL5R_DVU0_2 SCUX.VOL5R_DVU0_2
|
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| 726 | #define SCUXVOL6R_DVU0_2 SCUX.VOL6R_DVU0_2
|
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| 727 | #define SCUXVOL7R_DVU0_2 SCUX.VOL7R_DVU0_2
|
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| 728 | #define SCUXDVUER_DVU0_2 SCUX.DVUER_DVU0_2
|
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| 729 | #define SCUXDVUSR_DVU0_2 SCUX.DVUSR_DVU0_2
|
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| 730 | #define SCUXVEVMR_DVU0_2 SCUX.VEVMR_DVU0_2
|
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| 731 | #define SCUXVEVCR_DVU0_2 SCUX.VEVCR_DVU0_2
|
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| 732 | #define SCUXDVUIR_DVU0_3 SCUX.DVUIR_DVU0_3
|
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| 733 | #define SCUXVADIR_DVU0_3 SCUX.VADIR_DVU0_3
|
---|
| 734 | #define SCUXDVUBR_DVU0_3 SCUX.DVUBR_DVU0_3
|
---|
| 735 | #define SCUXDVUCR_DVU0_3 SCUX.DVUCR_DVU0_3
|
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| 736 | #define SCUXZCMCR_DVU0_3 SCUX.ZCMCR_DVU0_3
|
---|
| 737 | #define SCUXVRCTR_DVU0_3 SCUX.VRCTR_DVU0_3
|
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| 738 | #define SCUXVRPDR_DVU0_3 SCUX.VRPDR_DVU0_3
|
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| 739 | #define SCUXVRDBR_DVU0_3 SCUX.VRDBR_DVU0_3
|
---|
| 740 | #define SCUXVRWTR_DVU0_3 SCUX.VRWTR_DVU0_3
|
---|
| 741 | #define SCUXVOL0R_DVU0_3 SCUX.VOL0R_DVU0_3
|
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| 742 | #define SCUXVOL1R_DVU0_3 SCUX.VOL1R_DVU0_3
|
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| 743 | #define SCUXVOL2R_DVU0_3 SCUX.VOL2R_DVU0_3
|
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| 744 | #define SCUXVOL3R_DVU0_3 SCUX.VOL3R_DVU0_3
|
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| 745 | #define SCUXVOL4R_DVU0_3 SCUX.VOL4R_DVU0_3
|
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| 746 | #define SCUXVOL5R_DVU0_3 SCUX.VOL5R_DVU0_3
|
---|
| 747 | #define SCUXVOL6R_DVU0_3 SCUX.VOL6R_DVU0_3
|
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| 748 | #define SCUXVOL7R_DVU0_3 SCUX.VOL7R_DVU0_3
|
---|
| 749 | #define SCUXDVUER_DVU0_3 SCUX.DVUER_DVU0_3
|
---|
| 750 | #define SCUXDVUSR_DVU0_3 SCUX.DVUSR_DVU0_3
|
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| 751 | #define SCUXVEVMR_DVU0_3 SCUX.VEVMR_DVU0_3
|
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| 752 | #define SCUXVEVCR_DVU0_3 SCUX.VEVCR_DVU0_3
|
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| 753 | #define SCUXMIXIR_MIX0_0 SCUX.MIXIR_MIX0_0
|
---|
| 754 | #define SCUXMADIR_MIX0_0 SCUX.MADIR_MIX0_0
|
---|
| 755 | #define SCUXMIXBR_MIX0_0 SCUX.MIXBR_MIX0_0
|
---|
| 756 | #define SCUXMIXMR_MIX0_0 SCUX.MIXMR_MIX0_0
|
---|
| 757 | #define SCUXMVPDR_MIX0_0 SCUX.MVPDR_MIX0_0
|
---|
| 758 | #define SCUXMDBAR_MIX0_0 SCUX.MDBAR_MIX0_0
|
---|
| 759 | #define SCUXMDBBR_MIX0_0 SCUX.MDBBR_MIX0_0
|
---|
| 760 | #define SCUXMDBCR_MIX0_0 SCUX.MDBCR_MIX0_0
|
---|
| 761 | #define SCUXMDBDR_MIX0_0 SCUX.MDBDR_MIX0_0
|
---|
| 762 | #define SCUXMDBER_MIX0_0 SCUX.MDBER_MIX0_0
|
---|
| 763 | #define SCUXMIXSR_MIX0_0 SCUX.MIXSR_MIX0_0
|
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| 764 | #define SCUXSWRSR_CIM SCUX.SWRSR_CIM
|
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| 765 | #define SCUXDMACR_CIM SCUX.DMACR_CIM
|
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| 766 | #define SCUXDMATD0_CIM SCUX.DMATD0_CIM.UINT32
|
---|
| 767 | #define SCUXDMATD0_CIML SCUX.DMATD0_CIM.UINT16[L]
|
---|
| 768 | #define SCUXDMATD0_CIMH SCUX.DMATD0_CIM.UINT16[H]
|
---|
| 769 | #define SCUXDMATD1_CIM SCUX.DMATD1_CIM.UINT32
|
---|
| 770 | #define SCUXDMATD1_CIML SCUX.DMATD1_CIM.UINT16[L]
|
---|
| 771 | #define SCUXDMATD1_CIMH SCUX.DMATD1_CIM.UINT16[H]
|
---|
| 772 | #define SCUXDMATD2_CIM SCUX.DMATD2_CIM.UINT32
|
---|
| 773 | #define SCUXDMATD2_CIML SCUX.DMATD2_CIM.UINT16[L]
|
---|
| 774 | #define SCUXDMATD2_CIMH SCUX.DMATD2_CIM.UINT16[H]
|
---|
| 775 | #define SCUXDMATD3_CIM SCUX.DMATD3_CIM.UINT32
|
---|
| 776 | #define SCUXDMATD3_CIML SCUX.DMATD3_CIM.UINT16[L]
|
---|
| 777 | #define SCUXDMATD3_CIMH SCUX.DMATD3_CIM.UINT16[H]
|
---|
| 778 | #define SCUXDMATU0_CIM SCUX.DMATU0_CIM.UINT32
|
---|
| 779 | #define SCUXDMATU0_CIML SCUX.DMATU0_CIM.UINT16[L]
|
---|
| 780 | #define SCUXDMATU0_CIMH SCUX.DMATU0_CIM.UINT16[H]
|
---|
| 781 | #define SCUXDMATU1_CIM SCUX.DMATU1_CIM.UINT32
|
---|
| 782 | #define SCUXDMATU1_CIML SCUX.DMATU1_CIM.UINT16[L]
|
---|
| 783 | #define SCUXDMATU1_CIMH SCUX.DMATU1_CIM.UINT16[H]
|
---|
| 784 | #define SCUXDMATU2_CIM SCUX.DMATU2_CIM.UINT32
|
---|
| 785 | #define SCUXDMATU2_CIML SCUX.DMATU2_CIM.UINT16[L]
|
---|
| 786 | #define SCUXDMATU2_CIMH SCUX.DMATU2_CIM.UINT16[H]
|
---|
| 787 | #define SCUXDMATU3_CIM SCUX.DMATU3_CIM.UINT32
|
---|
| 788 | #define SCUXDMATU3_CIML SCUX.DMATU3_CIM.UINT16[L]
|
---|
| 789 | #define SCUXDMATU3_CIMH SCUX.DMATU3_CIM.UINT16[H]
|
---|
| 790 | #define SCUXSSIRSEL_CIM SCUX.SSIRSEL_CIM
|
---|
| 791 | #define SCUXFDTSEL0_CIM SCUX.FDTSEL0_CIM
|
---|
| 792 | #define SCUXFDTSEL1_CIM SCUX.FDTSEL1_CIM
|
---|
| 793 | #define SCUXFDTSEL2_CIM SCUX.FDTSEL2_CIM
|
---|
| 794 | #define SCUXFDTSEL3_CIM SCUX.FDTSEL3_CIM
|
---|
| 795 | #define SCUXFUTSEL0_CIM SCUX.FUTSEL0_CIM
|
---|
| 796 | #define SCUXFUTSEL1_CIM SCUX.FUTSEL1_CIM
|
---|
| 797 | #define SCUXFUTSEL2_CIM SCUX.FUTSEL2_CIM
|
---|
| 798 | #define SCUXFUTSEL3_CIM SCUX.FUTSEL3_CIM
|
---|
| 799 | #define SCUXSSIPMD_CIM SCUX.SSIPMD_CIM
|
---|
| 800 | #define SCUXSSICTRL_CIM SCUX.SSICTRL_CIM
|
---|
| 801 | #define SCUXSRCRSEL0_CIM SCUX.SRCRSEL0_CIM
|
---|
| 802 | #define SCUXSRCRSEL1_CIM SCUX.SRCRSEL1_CIM
|
---|
| 803 | #define SCUXSRCRSEL2_CIM SCUX.SRCRSEL2_CIM
|
---|
| 804 | #define SCUXSRCRSEL3_CIM SCUX.SRCRSEL3_CIM
|
---|
| 805 | #define SCUXMIXRSEL_CIM SCUX.MIXRSEL_CIM
|
---|
| 806 | /* <-SEC M1.10.1 */
|
---|
| 807 | /* <-QAC 0639 */
|
---|
| 808 | #endif
|
---|