source: EcnlProtoTool/trunk/asp3_dcre/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/scux_iodefine.h@ 270

Last change on this file since 270 was 270, checked in by coas-nagasima, 7 years ago

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1/*******************************************************************************
2* DISCLAIMER
3* This software is supplied by Renesas Electronics Corporation and is only
4* intended for use with Renesas products. No other uses are authorized. This
5* software is owned by Renesas Electronics Corporation and is protected under
6* all applicable laws, including copyright laws.
7* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16* Renesas reserves the right, without notice, to make changes to this software
17* and to discontinue the availability of this software. By using this software,
18* you agree to the additional terms and conditions found by accessing the
19* following link:
20* http://www.renesas.com/disclaimer*
21* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
22*******************************************************************************/
23/*******************************************************************************
24* File Name : scux_iodefine.h
25* $Rev: $
26* $Date:: $
27* Description : Definition of I/O Register (V1.00a)
28******************************************************************************/
29#ifndef SCUX_IODEFINE_H
30#define SCUX_IODEFINE_H
31/* ->QAC 0639 : Over 127 members (C90) */
32/* ->SEC M1.10.1 : Not magic number */
33
34struct st_scux
35{ /* SCUX */
36/* start of struct st_scux_from_ipcir_ipc0_n */
37 volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */
38 volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */
39 volatile uint8_t dummy259[248]; /* */
40/* end of struct st_scux_from_ipcir_ipc0_n */
41/* start of struct st_scux_from_ipcir_ipc0_n */
42 volatile uint32_t IPCIR_IPC0_1; /* IPCIR_IPC0_1 */
43 volatile uint32_t IPSLR_IPC0_1; /* IPSLR_IPC0_1 */
44 volatile uint8_t dummy260[248]; /* */
45/* end of struct st_scux_from_ipcir_ipc0_n */
46/* start of struct st_scux_from_ipcir_ipc0_n */
47 volatile uint32_t IPCIR_IPC0_2; /* IPCIR_IPC0_2 */
48 volatile uint32_t IPSLR_IPC0_2; /* IPSLR_IPC0_2 */
49 volatile uint8_t dummy261[248]; /* */
50/* end of struct st_scux_from_ipcir_ipc0_n */
51/* start of struct st_scux_from_ipcir_ipc0_n */
52 volatile uint32_t IPCIR_IPC0_3; /* IPCIR_IPC0_3 */
53 volatile uint32_t IPSLR_IPC0_3; /* IPSLR_IPC0_3 */
54 volatile uint8_t dummy262[248]; /* */
55/* end of struct st_scux_from_ipcir_ipc0_n */
56/* start of struct st_scux_from_opcir_opc0_n */
57 volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */
58 volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */
59 volatile uint8_t dummy263[248]; /* */
60/* end of struct st_scux_from_opcir_opc0_n */
61/* start of struct st_scux_from_opcir_opc0_n */
62 volatile uint32_t OPCIR_OPC0_1; /* OPCIR_OPC0_1 */
63 volatile uint32_t OPSLR_OPC0_1; /* OPSLR_OPC0_1 */
64 volatile uint8_t dummy264[248]; /* */
65/* end of struct st_scux_from_opcir_opc0_n */
66/* start of struct st_scux_from_opcir_opc0_n */
67 volatile uint32_t OPCIR_OPC0_2; /* OPCIR_OPC0_2 */
68 volatile uint32_t OPSLR_OPC0_2; /* OPSLR_OPC0_2 */
69 volatile uint8_t dummy265[248]; /* */
70/* end of struct st_scux_from_opcir_opc0_n */
71/* start of struct st_scux_from_opcir_opc0_n */
72 volatile uint32_t OPCIR_OPC0_3; /* OPCIR_OPC0_3 */
73 volatile uint32_t OPSLR_OPC0_3; /* OPSLR_OPC0_3 */
74 volatile uint8_t dummy266[248]; /* */
75/* end of struct st_scux_from_opcir_opc0_n */
76/* start of struct st_scux_from_ffdir_ffd0_n */
77 volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */
78 volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */
79 volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */
80 volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */
81 volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */
82 volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */
83 volatile uint8_t dummy267[4]; /* */
84 volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */
85/* end of struct st_scux_from_ffdir_ffd0_n */
86 volatile uint8_t dummy268[224]; /* */
87/* start of struct st_scux_from_ffdir_ffd0_n */
88 volatile uint32_t FFDIR_FFD0_1; /* FFDIR_FFD0_1 */
89 volatile uint32_t FDAIR_FFD0_1; /* FDAIR_FFD0_1 */
90 volatile uint32_t DRQSR_FFD0_1; /* DRQSR_FFD0_1 */
91 volatile uint32_t FFDPR_FFD0_1; /* FFDPR_FFD0_1 */
92 volatile uint32_t FFDBR_FFD0_1; /* FFDBR_FFD0_1 */
93 volatile uint32_t DEVMR_FFD0_1; /* DEVMR_FFD0_1 */
94 volatile uint8_t dummy269[4]; /* */
95 volatile uint32_t DEVCR_FFD0_1; /* DEVCR_FFD0_1 */
96/* end of struct st_scux_from_ffdir_ffd0_n */
97 volatile uint8_t dummy270[224]; /* */
98/* start of struct st_scux_from_ffdir_ffd0_n */
99 volatile uint32_t FFDIR_FFD0_2; /* FFDIR_FFD0_2 */
100 volatile uint32_t FDAIR_FFD0_2; /* FDAIR_FFD0_2 */
101 volatile uint32_t DRQSR_FFD0_2; /* DRQSR_FFD0_2 */
102 volatile uint32_t FFDPR_FFD0_2; /* FFDPR_FFD0_2 */
103 volatile uint32_t FFDBR_FFD0_2; /* FFDBR_FFD0_2 */
104 volatile uint32_t DEVMR_FFD0_2; /* DEVMR_FFD0_2 */
105 volatile uint8_t dummy271[4]; /* */
106 volatile uint32_t DEVCR_FFD0_2; /* DEVCR_FFD0_2 */
107/* end of struct st_scux_from_ffdir_ffd0_n */
108 volatile uint8_t dummy272[224]; /* */
109/* start of struct st_scux_from_ffdir_ffd0_n */
110 volatile uint32_t FFDIR_FFD0_3; /* FFDIR_FFD0_3 */
111 volatile uint32_t FDAIR_FFD0_3; /* FDAIR_FFD0_3 */
112 volatile uint32_t DRQSR_FFD0_3; /* DRQSR_FFD0_3 */
113 volatile uint32_t FFDPR_FFD0_3; /* FFDPR_FFD0_3 */
114 volatile uint32_t FFDBR_FFD0_3; /* FFDBR_FFD0_3 */
115 volatile uint32_t DEVMR_FFD0_3; /* DEVMR_FFD0_3 */
116 volatile uint8_t dummy273[4]; /* */
117 volatile uint32_t DEVCR_FFD0_3; /* DEVCR_FFD0_3 */
118/* end of struct st_scux_from_ffdir_ffd0_n */
119 volatile uint8_t dummy274[224]; /* */
120/* start of struct st_scux_from_ffuir_ffu0_n */
121 volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */
122 volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */
123 volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */
124 volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */
125 volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */
126 volatile uint8_t dummy275[4]; /* */
127 volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */
128/* end of struct st_scux_from_ffuir_ffu0_n */
129 volatile uint8_t dummy276[228]; /* */
130/* start of struct st_scux_from_ffuir_ffu0_n */
131 volatile uint32_t FFUIR_FFU0_1; /* FFUIR_FFU0_1 */
132 volatile uint32_t FUAIR_FFU0_1; /* FUAIR_FFU0_1 */
133 volatile uint32_t URQSR_FFU0_1; /* URQSR_FFU0_1 */
134 volatile uint32_t FFUPR_FFU0_1; /* FFUPR_FFU0_1 */
135 volatile uint32_t UEVMR_FFU0_1; /* UEVMR_FFU0_1 */
136 volatile uint8_t dummy277[4]; /* */
137 volatile uint32_t UEVCR_FFU0_1; /* UEVCR_FFU0_1 */
138/* end of struct st_scux_from_ffuir_ffu0_n */
139 volatile uint8_t dummy278[228]; /* */
140/* start of struct st_scux_from_ffuir_ffu0_n */
141 volatile uint32_t FFUIR_FFU0_2; /* FFUIR_FFU0_2 */
142 volatile uint32_t FUAIR_FFU0_2; /* FUAIR_FFU0_2 */
143 volatile uint32_t URQSR_FFU0_2; /* URQSR_FFU0_2 */
144 volatile uint32_t FFUPR_FFU0_2; /* FFUPR_FFU0_2 */
145 volatile uint32_t UEVMR_FFU0_2; /* UEVMR_FFU0_2 */
146 volatile uint8_t dummy279[4]; /* */
147 volatile uint32_t UEVCR_FFU0_2; /* UEVCR_FFU0_2 */
148/* end of struct st_scux_from_ffuir_ffu0_n */
149 volatile uint8_t dummy280[228]; /* */
150/* start of struct st_scux_from_ffuir_ffu0_n */
151 volatile uint32_t FFUIR_FFU0_3; /* FFUIR_FFU0_3 */
152 volatile uint32_t FUAIR_FFU0_3; /* FUAIR_FFU0_3 */
153 volatile uint32_t URQSR_FFU0_3; /* URQSR_FFU0_3 */
154 volatile uint32_t FFUPR_FFU0_3; /* FFUPR_FFU0_3 */
155 volatile uint32_t UEVMR_FFU0_3; /* UEVMR_FFU0_3 */
156 volatile uint8_t dummy281[4]; /* */
157 volatile uint32_t UEVCR_FFU0_3; /* UEVCR_FFU0_3 */
158/* end of struct st_scux_from_ffuir_ffu0_n */
159 volatile uint8_t dummy282[228]; /* */
160/* start of struct st_scux_from_srcir0_2src0_n */
161 volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */
162 volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */
163 volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */
164 volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */
165 volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */
166 volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */
167 volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */
168 volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */
169 volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */
170 volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */
171 volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */
172 volatile uint8_t dummy283[4]; /* */
173 volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */
174 volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */
175 volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */
176 volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */
177 volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */
178 volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */
179 volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */
180 volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */
181 volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */
182 volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */
183 volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */
184 volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */
185 volatile uint8_t dummy284[4]; /* */
186 volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */
187 volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */
188/* end of struct st_scux_from_srcir0_2src0_n */
189 volatile uint8_t dummy285[148]; /* */
190/* start of struct st_scux_from_srcir0_2src0_n */
191 volatile uint32_t SRCIR0_2SRC0_1; /* SRCIR0_2SRC0_1 */
192 volatile uint32_t SADIR0_2SRC0_1; /* SADIR0_2SRC0_1 */
193 volatile uint32_t SRCBR0_2SRC0_1; /* SRCBR0_2SRC0_1 */
194 volatile uint32_t IFSCR0_2SRC0_1; /* IFSCR0_2SRC0_1 */
195 volatile uint32_t IFSVR0_2SRC0_1; /* IFSVR0_2SRC0_1 */
196 volatile uint32_t SRCCR0_2SRC0_1; /* SRCCR0_2SRC0_1 */
197 volatile uint32_t MNFSR0_2SRC0_1; /* MNFSR0_2SRC0_1 */
198 volatile uint32_t BFSSR0_2SRC0_1; /* BFSSR0_2SRC0_1 */
199 volatile uint32_t SC2SR0_2SRC0_1; /* SC2SR0_2SRC0_1 */
200 volatile uint32_t WATSR0_2SRC0_1; /* WATSR0_2SRC0_1 */
201 volatile uint32_t SEVMR0_2SRC0_1; /* SEVMR0_2SRC0_1 */
202 volatile uint8_t dummy286[4]; /* */
203 volatile uint32_t SEVCR0_2SRC0_1; /* SEVCR0_2SRC0_1 */
204 volatile uint32_t SRCIR1_2SRC0_1; /* SRCIR1_2SRC0_1 */
205 volatile uint32_t SADIR1_2SRC0_1; /* SADIR1_2SRC0_1 */
206 volatile uint32_t SRCBR1_2SRC0_1; /* SRCBR1_2SRC0_1 */
207 volatile uint32_t IFSCR1_2SRC0_1; /* IFSCR1_2SRC0_1 */
208 volatile uint32_t IFSVR1_2SRC0_1; /* IFSVR1_2SRC0_1 */
209 volatile uint32_t SRCCR1_2SRC0_1; /* SRCCR1_2SRC0_1 */
210 volatile uint32_t MNFSR1_2SRC0_1; /* MNFSR1_2SRC0_1 */
211 volatile uint32_t BFSSR1_2SRC0_1; /* BFSSR1_2SRC0_1 */
212 volatile uint32_t SC2SR1_2SRC0_1; /* SC2SR1_2SRC0_1 */
213 volatile uint32_t WATSR1_2SRC0_1; /* WATSR1_2SRC0_1 */
214 volatile uint32_t SEVMR1_2SRC0_1; /* SEVMR1_2SRC0_1 */
215 volatile uint8_t dummy287[4]; /* */
216 volatile uint32_t SEVCR1_2SRC0_1; /* SEVCR1_2SRC0_1 */
217 volatile uint32_t SRCIRR_2SRC0_1; /* SRCIRR_2SRC0_1 */
218/* end of struct st_scux_from_srcir0_2src0_n */
219 volatile uint8_t dummy288[148]; /* */
220/* start of struct st_scux_from_dvuir_dvu0_n */
221 volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */
222 volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */
223 volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */
224 volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */
225 volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */
226 volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */
227 volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */
228 volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */
229 volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */
230 volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */
231 volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */
232 volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */
233 volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */
234 volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */
235 volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */
236 volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */
237 volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */
238 volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */
239 volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */
240 volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */
241 volatile uint8_t dummy289[4]; /* */
242 volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */
243/* end of struct st_scux_from_dvuir_dvu0_n */
244 volatile uint8_t dummy290[168]; /* */
245/* start of struct st_scux_from_dvuir_dvu0_n */
246 volatile uint32_t DVUIR_DVU0_1; /* DVUIR_DVU0_1 */
247 volatile uint32_t VADIR_DVU0_1; /* VADIR_DVU0_1 */
248 volatile uint32_t DVUBR_DVU0_1; /* DVUBR_DVU0_1 */
249 volatile uint32_t DVUCR_DVU0_1; /* DVUCR_DVU0_1 */
250 volatile uint32_t ZCMCR_DVU0_1; /* ZCMCR_DVU0_1 */
251 volatile uint32_t VRCTR_DVU0_1; /* VRCTR_DVU0_1 */
252 volatile uint32_t VRPDR_DVU0_1; /* VRPDR_DVU0_1 */
253 volatile uint32_t VRDBR_DVU0_1; /* VRDBR_DVU0_1 */
254 volatile uint32_t VRWTR_DVU0_1; /* VRWTR_DVU0_1 */
255 volatile uint32_t VOL0R_DVU0_1; /* VOL0R_DVU0_1 */
256 volatile uint32_t VOL1R_DVU0_1; /* VOL1R_DVU0_1 */
257 volatile uint32_t VOL2R_DVU0_1; /* VOL2R_DVU0_1 */
258 volatile uint32_t VOL3R_DVU0_1; /* VOL3R_DVU0_1 */
259 volatile uint32_t VOL4R_DVU0_1; /* VOL4R_DVU0_1 */
260 volatile uint32_t VOL5R_DVU0_1; /* VOL5R_DVU0_1 */
261 volatile uint32_t VOL6R_DVU0_1; /* VOL6R_DVU0_1 */
262 volatile uint32_t VOL7R_DVU0_1; /* VOL7R_DVU0_1 */
263 volatile uint32_t DVUER_DVU0_1; /* DVUER_DVU0_1 */
264 volatile uint32_t DVUSR_DVU0_1; /* DVUSR_DVU0_1 */
265 volatile uint32_t VEVMR_DVU0_1; /* VEVMR_DVU0_1 */
266 volatile uint8_t dummy291[4]; /* */
267 volatile uint32_t VEVCR_DVU0_1; /* VEVCR_DVU0_1 */
268/* end of struct st_scux_from_dvuir_dvu0_n */
269 volatile uint8_t dummy292[168]; /* */
270/* start of struct st_scux_from_dvuir_dvu0_n */
271 volatile uint32_t DVUIR_DVU0_2; /* DVUIR_DVU0_2 */
272 volatile uint32_t VADIR_DVU0_2; /* VADIR_DVU0_2 */
273 volatile uint32_t DVUBR_DVU0_2; /* DVUBR_DVU0_2 */
274 volatile uint32_t DVUCR_DVU0_2; /* DVUCR_DVU0_2 */
275 volatile uint32_t ZCMCR_DVU0_2; /* ZCMCR_DVU0_2 */
276 volatile uint32_t VRCTR_DVU0_2; /* VRCTR_DVU0_2 */
277 volatile uint32_t VRPDR_DVU0_2; /* VRPDR_DVU0_2 */
278 volatile uint32_t VRDBR_DVU0_2; /* VRDBR_DVU0_2 */
279 volatile uint32_t VRWTR_DVU0_2; /* VRWTR_DVU0_2 */
280 volatile uint32_t VOL0R_DVU0_2; /* VOL0R_DVU0_2 */
281 volatile uint32_t VOL1R_DVU0_2; /* VOL1R_DVU0_2 */
282 volatile uint32_t VOL2R_DVU0_2; /* VOL2R_DVU0_2 */
283 volatile uint32_t VOL3R_DVU0_2; /* VOL3R_DVU0_2 */
284 volatile uint32_t VOL4R_DVU0_2; /* VOL4R_DVU0_2 */
285 volatile uint32_t VOL5R_DVU0_2; /* VOL5R_DVU0_2 */
286 volatile uint32_t VOL6R_DVU0_2; /* VOL6R_DVU0_2 */
287 volatile uint32_t VOL7R_DVU0_2; /* VOL7R_DVU0_2 */
288 volatile uint32_t DVUER_DVU0_2; /* DVUER_DVU0_2 */
289 volatile uint32_t DVUSR_DVU0_2; /* DVUSR_DVU0_2 */
290 volatile uint32_t VEVMR_DVU0_2; /* VEVMR_DVU0_2 */
291 volatile uint8_t dummy293[4]; /* */
292 volatile uint32_t VEVCR_DVU0_2; /* VEVCR_DVU0_2 */
293/* end of struct st_scux_from_dvuir_dvu0_n */
294 volatile uint8_t dummy294[168]; /* */
295/* start of struct st_scux_from_dvuir_dvu0_n */
296 volatile uint32_t DVUIR_DVU0_3; /* DVUIR_DVU0_3 */
297 volatile uint32_t VADIR_DVU0_3; /* VADIR_DVU0_3 */
298 volatile uint32_t DVUBR_DVU0_3; /* DVUBR_DVU0_3 */
299 volatile uint32_t DVUCR_DVU0_3; /* DVUCR_DVU0_3 */
300 volatile uint32_t ZCMCR_DVU0_3; /* ZCMCR_DVU0_3 */
301 volatile uint32_t VRCTR_DVU0_3; /* VRCTR_DVU0_3 */
302 volatile uint32_t VRPDR_DVU0_3; /* VRPDR_DVU0_3 */
303 volatile uint32_t VRDBR_DVU0_3; /* VRDBR_DVU0_3 */
304 volatile uint32_t VRWTR_DVU0_3; /* VRWTR_DVU0_3 */
305 volatile uint32_t VOL0R_DVU0_3; /* VOL0R_DVU0_3 */
306 volatile uint32_t VOL1R_DVU0_3; /* VOL1R_DVU0_3 */
307 volatile uint32_t VOL2R_DVU0_3; /* VOL2R_DVU0_3 */
308 volatile uint32_t VOL3R_DVU0_3; /* VOL3R_DVU0_3 */
309 volatile uint32_t VOL4R_DVU0_3; /* VOL4R_DVU0_3 */
310 volatile uint32_t VOL5R_DVU0_3; /* VOL5R_DVU0_3 */
311 volatile uint32_t VOL6R_DVU0_3; /* VOL6R_DVU0_3 */
312 volatile uint32_t VOL7R_DVU0_3; /* VOL7R_DVU0_3 */
313 volatile uint32_t DVUER_DVU0_3; /* DVUER_DVU0_3 */
314 volatile uint32_t DVUSR_DVU0_3; /* DVUSR_DVU0_3 */
315 volatile uint32_t VEVMR_DVU0_3; /* VEVMR_DVU0_3 */
316 volatile uint8_t dummy295[4]; /* */
317 volatile uint32_t VEVCR_DVU0_3; /* VEVCR_DVU0_3 */
318/* end of struct st_scux_from_dvuir_dvu0_n */
319 volatile uint8_t dummy296[168]; /* */
320 volatile uint32_t MIXIR_MIX0_0; /* MIXIR_MIX0_0 */
321 volatile uint32_t MADIR_MIX0_0; /* MADIR_MIX0_0 */
322 volatile uint32_t MIXBR_MIX0_0; /* MIXBR_MIX0_0 */
323 volatile uint32_t MIXMR_MIX0_0; /* MIXMR_MIX0_0 */
324 volatile uint32_t MVPDR_MIX0_0; /* MVPDR_MIX0_0 */
325 volatile uint32_t MDBAR_MIX0_0; /* MDBAR_MIX0_0 */
326 volatile uint32_t MDBBR_MIX0_0; /* MDBBR_MIX0_0 */
327 volatile uint32_t MDBCR_MIX0_0; /* MDBCR_MIX0_0 */
328 volatile uint32_t MDBDR_MIX0_0; /* MDBDR_MIX0_0 */
329 volatile uint32_t MDBER_MIX0_0; /* MDBER_MIX0_0 */
330 volatile uint32_t MIXSR_MIX0_0; /* MIXSR_MIX0_0 */
331 volatile uint8_t dummy297[212]; /* */
332 volatile uint32_t SWRSR_CIM; /* SWRSR_CIM */
333 volatile uint32_t DMACR_CIM; /* DMACR_CIM */
334#define SCUX_DMATDn_CIM_COUNT 4
335 union iodefine_reg32_16_t DMATD0_CIM; /* DMATD0_CIM */
336 union iodefine_reg32_16_t DMATD1_CIM; /* DMATD1_CIM */
337 union iodefine_reg32_16_t DMATD2_CIM; /* DMATD2_CIM */
338 union iodefine_reg32_16_t DMATD3_CIM; /* DMATD3_CIM */
339#define SCUX_DMATUn_CIM_COUNT 4
340 union iodefine_reg32_16_t DMATU0_CIM; /* DMATU0_CIM */
341 union iodefine_reg32_16_t DMATU1_CIM; /* DMATU1_CIM */
342 union iodefine_reg32_16_t DMATU2_CIM; /* DMATU2_CIM */
343 union iodefine_reg32_16_t DMATU3_CIM; /* DMATU3_CIM */
344
345 volatile uint8_t dummy298[16]; /* */
346 volatile uint32_t SSIRSEL_CIM; /* SSIRSEL_CIM */
347#define SCUX_FDTSELn_CIM_COUNT 4
348 volatile uint32_t FDTSEL0_CIM; /* FDTSEL0_CIM */
349 volatile uint32_t FDTSEL1_CIM; /* FDTSEL1_CIM */
350 volatile uint32_t FDTSEL2_CIM; /* FDTSEL2_CIM */
351 volatile uint32_t FDTSEL3_CIM; /* FDTSEL3_CIM */
352#define SCUX_FUTSELn_CIM_COUNT 4
353 volatile uint32_t FUTSEL0_CIM; /* FUTSEL0_CIM */
354 volatile uint32_t FUTSEL1_CIM; /* FUTSEL1_CIM */
355 volatile uint32_t FUTSEL2_CIM; /* FUTSEL2_CIM */
356 volatile uint32_t FUTSEL3_CIM; /* FUTSEL3_CIM */
357 volatile uint32_t SSIPMD_CIM; /* SSIPMD_CIM */
358 volatile uint32_t SSICTRL_CIM; /* SSICTRL_CIM */
359#define SCUX_SRCRSELn_CIM_COUNT 4
360 volatile uint32_t SRCRSEL0_CIM; /* SRCRSEL0_CIM */
361 volatile uint32_t SRCRSEL1_CIM; /* SRCRSEL1_CIM */
362 volatile uint32_t SRCRSEL2_CIM; /* SRCRSEL2_CIM */
363 volatile uint32_t SRCRSEL3_CIM; /* SRCRSEL3_CIM */
364 volatile uint32_t MIXRSEL_CIM; /* MIXRSEL_CIM */
365};
366
367
368struct st_scux_from_ipcir_ipc0_n
369{
370 volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */
371 volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */
372 volatile uint8_t dummy1[248]; /* */
373};
374
375
376struct st_scux_from_opcir_opc0_n
377{
378 volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */
379 volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */
380 volatile uint8_t dummy1[248]; /* */
381};
382
383
384struct st_scux_from_ffdir_ffd0_n
385{
386 volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */
387 volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */
388 volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */
389 volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */
390 volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */
391 volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */
392 volatile uint8_t dummy1[4]; /* */
393 volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */
394};
395
396
397struct st_scux_from_ffuir_ffu0_n
398{
399 volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */
400 volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */
401 volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */
402 volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */
403 volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */
404 volatile uint8_t dummy1[4]; /* */
405 volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */
406};
407
408
409struct st_scux_from_srcir0_2src0_n
410{
411 volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */
412 volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */
413 volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */
414 volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */
415 volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */
416 volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */
417 volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */
418 volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */
419 volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */
420 volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */
421 volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */
422 volatile uint8_t dummy1[4]; /* */
423 volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */
424 volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */
425 volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */
426 volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */
427 volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */
428 volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */
429 volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */
430 volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */
431 volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */
432 volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */
433 volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */
434 volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */
435 volatile uint8_t dummy2[4]; /* */
436 volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */
437 volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */
438};
439
440
441struct st_scux_from_dvuir_dvu0_n
442{
443 volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */
444 volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */
445 volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */
446 volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */
447 volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */
448 volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */
449 volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */
450 volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */
451 volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */
452 volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */
453 volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */
454 volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */
455 volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */
456 volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */
457 volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */
458 volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */
459 volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */
460 volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */
461 volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */
462 volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */
463 volatile uint8_t dummy1[4]; /* */
464 volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */
465};
466
467
468#define SCUX (*(struct st_scux *)0xE8208000uL) /* SCUX */
469
470
471/* Start of channnel array defines of SCUX */
472
473/* Channnel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */
474/*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */
475#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT 4
476#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \
477{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
478 &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \
479} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
480#define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */
481#define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */
482#define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */
483#define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */
484
485
486/* Channnel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */
487/*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */
488#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT 2
489#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \
490{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
491 &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \
492} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
493#define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */
494#define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */
495
496
497/* Channnel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */
498/*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */
499#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT 4
500#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \
501{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
502 &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \
503} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
504#define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */
505#define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */
506#define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */
507#define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */
508
509
510/* Channnel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */
511/*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */
512#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT 4
513#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \
514{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
515 &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \
516} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
517#define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */
518#define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */
519#define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */
520#define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */
521
522
523/* Channnel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */
524/*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */
525#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT 4
526#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \
527{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
528 &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \
529} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
530#define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */
531#define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */
532#define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */
533#define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */
534
535
536/* Channnel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */
537/*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */
538#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT 4
539#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \
540{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
541 &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \
542} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
543#define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */
544#define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */
545#define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */
546#define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */
547
548/* End of channnel array defines of SCUX */
549
550
551#define SCUXIPCIR_IPC0_0 SCUX.IPCIR_IPC0_0
552#define SCUXIPSLR_IPC0_0 SCUX.IPSLR_IPC0_0
553#define SCUXIPCIR_IPC0_1 SCUX.IPCIR_IPC0_1
554#define SCUXIPSLR_IPC0_1 SCUX.IPSLR_IPC0_1
555#define SCUXIPCIR_IPC0_2 SCUX.IPCIR_IPC0_2
556#define SCUXIPSLR_IPC0_2 SCUX.IPSLR_IPC0_2
557#define SCUXIPCIR_IPC0_3 SCUX.IPCIR_IPC0_3
558#define SCUXIPSLR_IPC0_3 SCUX.IPSLR_IPC0_3
559#define SCUXOPCIR_OPC0_0 SCUX.OPCIR_OPC0_0
560#define SCUXOPSLR_OPC0_0 SCUX.OPSLR_OPC0_0
561#define SCUXOPCIR_OPC0_1 SCUX.OPCIR_OPC0_1
562#define SCUXOPSLR_OPC0_1 SCUX.OPSLR_OPC0_1
563#define SCUXOPCIR_OPC0_2 SCUX.OPCIR_OPC0_2
564#define SCUXOPSLR_OPC0_2 SCUX.OPSLR_OPC0_2
565#define SCUXOPCIR_OPC0_3 SCUX.OPCIR_OPC0_3
566#define SCUXOPSLR_OPC0_3 SCUX.OPSLR_OPC0_3
567#define SCUXFFDIR_FFD0_0 SCUX.FFDIR_FFD0_0
568#define SCUXFDAIR_FFD0_0 SCUX.FDAIR_FFD0_0
569#define SCUXDRQSR_FFD0_0 SCUX.DRQSR_FFD0_0
570#define SCUXFFDPR_FFD0_0 SCUX.FFDPR_FFD0_0
571#define SCUXFFDBR_FFD0_0 SCUX.FFDBR_FFD0_0
572#define SCUXDEVMR_FFD0_0 SCUX.DEVMR_FFD0_0
573#define SCUXDEVCR_FFD0_0 SCUX.DEVCR_FFD0_0
574#define SCUXFFDIR_FFD0_1 SCUX.FFDIR_FFD0_1
575#define SCUXFDAIR_FFD0_1 SCUX.FDAIR_FFD0_1
576#define SCUXDRQSR_FFD0_1 SCUX.DRQSR_FFD0_1
577#define SCUXFFDPR_FFD0_1 SCUX.FFDPR_FFD0_1
578#define SCUXFFDBR_FFD0_1 SCUX.FFDBR_FFD0_1
579#define SCUXDEVMR_FFD0_1 SCUX.DEVMR_FFD0_1
580#define SCUXDEVCR_FFD0_1 SCUX.DEVCR_FFD0_1
581#define SCUXFFDIR_FFD0_2 SCUX.FFDIR_FFD0_2
582#define SCUXFDAIR_FFD0_2 SCUX.FDAIR_FFD0_2
583#define SCUXDRQSR_FFD0_2 SCUX.DRQSR_FFD0_2
584#define SCUXFFDPR_FFD0_2 SCUX.FFDPR_FFD0_2
585#define SCUXFFDBR_FFD0_2 SCUX.FFDBR_FFD0_2
586#define SCUXDEVMR_FFD0_2 SCUX.DEVMR_FFD0_2
587#define SCUXDEVCR_FFD0_2 SCUX.DEVCR_FFD0_2
588#define SCUXFFDIR_FFD0_3 SCUX.FFDIR_FFD0_3
589#define SCUXFDAIR_FFD0_3 SCUX.FDAIR_FFD0_3
590#define SCUXDRQSR_FFD0_3 SCUX.DRQSR_FFD0_3
591#define SCUXFFDPR_FFD0_3 SCUX.FFDPR_FFD0_3
592#define SCUXFFDBR_FFD0_3 SCUX.FFDBR_FFD0_3
593#define SCUXDEVMR_FFD0_3 SCUX.DEVMR_FFD0_3
594#define SCUXDEVCR_FFD0_3 SCUX.DEVCR_FFD0_3
595#define SCUXFFUIR_FFU0_0 SCUX.FFUIR_FFU0_0
596#define SCUXFUAIR_FFU0_0 SCUX.FUAIR_FFU0_0
597#define SCUXURQSR_FFU0_0 SCUX.URQSR_FFU0_0
598#define SCUXFFUPR_FFU0_0 SCUX.FFUPR_FFU0_0
599#define SCUXUEVMR_FFU0_0 SCUX.UEVMR_FFU0_0
600#define SCUXUEVCR_FFU0_0 SCUX.UEVCR_FFU0_0
601#define SCUXFFUIR_FFU0_1 SCUX.FFUIR_FFU0_1
602#define SCUXFUAIR_FFU0_1 SCUX.FUAIR_FFU0_1
603#define SCUXURQSR_FFU0_1 SCUX.URQSR_FFU0_1
604#define SCUXFFUPR_FFU0_1 SCUX.FFUPR_FFU0_1
605#define SCUXUEVMR_FFU0_1 SCUX.UEVMR_FFU0_1
606#define SCUXUEVCR_FFU0_1 SCUX.UEVCR_FFU0_1
607#define SCUXFFUIR_FFU0_2 SCUX.FFUIR_FFU0_2
608#define SCUXFUAIR_FFU0_2 SCUX.FUAIR_FFU0_2
609#define SCUXURQSR_FFU0_2 SCUX.URQSR_FFU0_2
610#define SCUXFFUPR_FFU0_2 SCUX.FFUPR_FFU0_2
611#define SCUXUEVMR_FFU0_2 SCUX.UEVMR_FFU0_2
612#define SCUXUEVCR_FFU0_2 SCUX.UEVCR_FFU0_2
613#define SCUXFFUIR_FFU0_3 SCUX.FFUIR_FFU0_3
614#define SCUXFUAIR_FFU0_3 SCUX.FUAIR_FFU0_3
615#define SCUXURQSR_FFU0_3 SCUX.URQSR_FFU0_3
616#define SCUXFFUPR_FFU0_3 SCUX.FFUPR_FFU0_3
617#define SCUXUEVMR_FFU0_3 SCUX.UEVMR_FFU0_3
618#define SCUXUEVCR_FFU0_3 SCUX.UEVCR_FFU0_3
619#define SCUXSRCIR0_2SRC0_0 SCUX.SRCIR0_2SRC0_0
620#define SCUXSADIR0_2SRC0_0 SCUX.SADIR0_2SRC0_0
621#define SCUXSRCBR0_2SRC0_0 SCUX.SRCBR0_2SRC0_0
622#define SCUXIFSCR0_2SRC0_0 SCUX.IFSCR0_2SRC0_0
623#define SCUXIFSVR0_2SRC0_0 SCUX.IFSVR0_2SRC0_0
624#define SCUXSRCCR0_2SRC0_0 SCUX.SRCCR0_2SRC0_0
625#define SCUXMNFSR0_2SRC0_0 SCUX.MNFSR0_2SRC0_0
626#define SCUXBFSSR0_2SRC0_0 SCUX.BFSSR0_2SRC0_0
627#define SCUXSC2SR0_2SRC0_0 SCUX.SC2SR0_2SRC0_0
628#define SCUXWATSR0_2SRC0_0 SCUX.WATSR0_2SRC0_0
629#define SCUXSEVMR0_2SRC0_0 SCUX.SEVMR0_2SRC0_0
630#define SCUXSEVCR0_2SRC0_0 SCUX.SEVCR0_2SRC0_0
631#define SCUXSRCIR1_2SRC0_0 SCUX.SRCIR1_2SRC0_0
632#define SCUXSADIR1_2SRC0_0 SCUX.SADIR1_2SRC0_0
633#define SCUXSRCBR1_2SRC0_0 SCUX.SRCBR1_2SRC0_0
634#define SCUXIFSCR1_2SRC0_0 SCUX.IFSCR1_2SRC0_0
635#define SCUXIFSVR1_2SRC0_0 SCUX.IFSVR1_2SRC0_0
636#define SCUXSRCCR1_2SRC0_0 SCUX.SRCCR1_2SRC0_0
637#define SCUXMNFSR1_2SRC0_0 SCUX.MNFSR1_2SRC0_0
638#define SCUXBFSSR1_2SRC0_0 SCUX.BFSSR1_2SRC0_0
639#define SCUXSC2SR1_2SRC0_0 SCUX.SC2SR1_2SRC0_0
640#define SCUXWATSR1_2SRC0_0 SCUX.WATSR1_2SRC0_0
641#define SCUXSEVMR1_2SRC0_0 SCUX.SEVMR1_2SRC0_0
642#define SCUXSEVCR1_2SRC0_0 SCUX.SEVCR1_2SRC0_0
643#define SCUXSRCIRR_2SRC0_0 SCUX.SRCIRR_2SRC0_0
644#define SCUXSRCIR0_2SRC0_1 SCUX.SRCIR0_2SRC0_1
645#define SCUXSADIR0_2SRC0_1 SCUX.SADIR0_2SRC0_1
646#define SCUXSRCBR0_2SRC0_1 SCUX.SRCBR0_2SRC0_1
647#define SCUXIFSCR0_2SRC0_1 SCUX.IFSCR0_2SRC0_1
648#define SCUXIFSVR0_2SRC0_1 SCUX.IFSVR0_2SRC0_1
649#define SCUXSRCCR0_2SRC0_1 SCUX.SRCCR0_2SRC0_1
650#define SCUXMNFSR0_2SRC0_1 SCUX.MNFSR0_2SRC0_1
651#define SCUXBFSSR0_2SRC0_1 SCUX.BFSSR0_2SRC0_1
652#define SCUXSC2SR0_2SRC0_1 SCUX.SC2SR0_2SRC0_1
653#define SCUXWATSR0_2SRC0_1 SCUX.WATSR0_2SRC0_1
654#define SCUXSEVMR0_2SRC0_1 SCUX.SEVMR0_2SRC0_1
655#define SCUXSEVCR0_2SRC0_1 SCUX.SEVCR0_2SRC0_1
656#define SCUXSRCIR1_2SRC0_1 SCUX.SRCIR1_2SRC0_1
657#define SCUXSADIR1_2SRC0_1 SCUX.SADIR1_2SRC0_1
658#define SCUXSRCBR1_2SRC0_1 SCUX.SRCBR1_2SRC0_1
659#define SCUXIFSCR1_2SRC0_1 SCUX.IFSCR1_2SRC0_1
660#define SCUXIFSVR1_2SRC0_1 SCUX.IFSVR1_2SRC0_1
661#define SCUXSRCCR1_2SRC0_1 SCUX.SRCCR1_2SRC0_1
662#define SCUXMNFSR1_2SRC0_1 SCUX.MNFSR1_2SRC0_1
663#define SCUXBFSSR1_2SRC0_1 SCUX.BFSSR1_2SRC0_1
664#define SCUXSC2SR1_2SRC0_1 SCUX.SC2SR1_2SRC0_1
665#define SCUXWATSR1_2SRC0_1 SCUX.WATSR1_2SRC0_1
666#define SCUXSEVMR1_2SRC0_1 SCUX.SEVMR1_2SRC0_1
667#define SCUXSEVCR1_2SRC0_1 SCUX.SEVCR1_2SRC0_1
668#define SCUXSRCIRR_2SRC0_1 SCUX.SRCIRR_2SRC0_1
669#define SCUXDVUIR_DVU0_0 SCUX.DVUIR_DVU0_0
670#define SCUXVADIR_DVU0_0 SCUX.VADIR_DVU0_0
671#define SCUXDVUBR_DVU0_0 SCUX.DVUBR_DVU0_0
672#define SCUXDVUCR_DVU0_0 SCUX.DVUCR_DVU0_0
673#define SCUXZCMCR_DVU0_0 SCUX.ZCMCR_DVU0_0
674#define SCUXVRCTR_DVU0_0 SCUX.VRCTR_DVU0_0
675#define SCUXVRPDR_DVU0_0 SCUX.VRPDR_DVU0_0
676#define SCUXVRDBR_DVU0_0 SCUX.VRDBR_DVU0_0
677#define SCUXVRWTR_DVU0_0 SCUX.VRWTR_DVU0_0
678#define SCUXVOL0R_DVU0_0 SCUX.VOL0R_DVU0_0
679#define SCUXVOL1R_DVU0_0 SCUX.VOL1R_DVU0_0
680#define SCUXVOL2R_DVU0_0 SCUX.VOL2R_DVU0_0
681#define SCUXVOL3R_DVU0_0 SCUX.VOL3R_DVU0_0
682#define SCUXVOL4R_DVU0_0 SCUX.VOL4R_DVU0_0
683#define SCUXVOL5R_DVU0_0 SCUX.VOL5R_DVU0_0
684#define SCUXVOL6R_DVU0_0 SCUX.VOL6R_DVU0_0
685#define SCUXVOL7R_DVU0_0 SCUX.VOL7R_DVU0_0
686#define SCUXDVUER_DVU0_0 SCUX.DVUER_DVU0_0
687#define SCUXDVUSR_DVU0_0 SCUX.DVUSR_DVU0_0
688#define SCUXVEVMR_DVU0_0 SCUX.VEVMR_DVU0_0
689#define SCUXVEVCR_DVU0_0 SCUX.VEVCR_DVU0_0
690#define SCUXDVUIR_DVU0_1 SCUX.DVUIR_DVU0_1
691#define SCUXVADIR_DVU0_1 SCUX.VADIR_DVU0_1
692#define SCUXDVUBR_DVU0_1 SCUX.DVUBR_DVU0_1
693#define SCUXDVUCR_DVU0_1 SCUX.DVUCR_DVU0_1
694#define SCUXZCMCR_DVU0_1 SCUX.ZCMCR_DVU0_1
695#define SCUXVRCTR_DVU0_1 SCUX.VRCTR_DVU0_1
696#define SCUXVRPDR_DVU0_1 SCUX.VRPDR_DVU0_1
697#define SCUXVRDBR_DVU0_1 SCUX.VRDBR_DVU0_1
698#define SCUXVRWTR_DVU0_1 SCUX.VRWTR_DVU0_1
699#define SCUXVOL0R_DVU0_1 SCUX.VOL0R_DVU0_1
700#define SCUXVOL1R_DVU0_1 SCUX.VOL1R_DVU0_1
701#define SCUXVOL2R_DVU0_1 SCUX.VOL2R_DVU0_1
702#define SCUXVOL3R_DVU0_1 SCUX.VOL3R_DVU0_1
703#define SCUXVOL4R_DVU0_1 SCUX.VOL4R_DVU0_1
704#define SCUXVOL5R_DVU0_1 SCUX.VOL5R_DVU0_1
705#define SCUXVOL6R_DVU0_1 SCUX.VOL6R_DVU0_1
706#define SCUXVOL7R_DVU0_1 SCUX.VOL7R_DVU0_1
707#define SCUXDVUER_DVU0_1 SCUX.DVUER_DVU0_1
708#define SCUXDVUSR_DVU0_1 SCUX.DVUSR_DVU0_1
709#define SCUXVEVMR_DVU0_1 SCUX.VEVMR_DVU0_1
710#define SCUXVEVCR_DVU0_1 SCUX.VEVCR_DVU0_1
711#define SCUXDVUIR_DVU0_2 SCUX.DVUIR_DVU0_2
712#define SCUXVADIR_DVU0_2 SCUX.VADIR_DVU0_2
713#define SCUXDVUBR_DVU0_2 SCUX.DVUBR_DVU0_2
714#define SCUXDVUCR_DVU0_2 SCUX.DVUCR_DVU0_2
715#define SCUXZCMCR_DVU0_2 SCUX.ZCMCR_DVU0_2
716#define SCUXVRCTR_DVU0_2 SCUX.VRCTR_DVU0_2
717#define SCUXVRPDR_DVU0_2 SCUX.VRPDR_DVU0_2
718#define SCUXVRDBR_DVU0_2 SCUX.VRDBR_DVU0_2
719#define SCUXVRWTR_DVU0_2 SCUX.VRWTR_DVU0_2
720#define SCUXVOL0R_DVU0_2 SCUX.VOL0R_DVU0_2
721#define SCUXVOL1R_DVU0_2 SCUX.VOL1R_DVU0_2
722#define SCUXVOL2R_DVU0_2 SCUX.VOL2R_DVU0_2
723#define SCUXVOL3R_DVU0_2 SCUX.VOL3R_DVU0_2
724#define SCUXVOL4R_DVU0_2 SCUX.VOL4R_DVU0_2
725#define SCUXVOL5R_DVU0_2 SCUX.VOL5R_DVU0_2
726#define SCUXVOL6R_DVU0_2 SCUX.VOL6R_DVU0_2
727#define SCUXVOL7R_DVU0_2 SCUX.VOL7R_DVU0_2
728#define SCUXDVUER_DVU0_2 SCUX.DVUER_DVU0_2
729#define SCUXDVUSR_DVU0_2 SCUX.DVUSR_DVU0_2
730#define SCUXVEVMR_DVU0_2 SCUX.VEVMR_DVU0_2
731#define SCUXVEVCR_DVU0_2 SCUX.VEVCR_DVU0_2
732#define SCUXDVUIR_DVU0_3 SCUX.DVUIR_DVU0_3
733#define SCUXVADIR_DVU0_3 SCUX.VADIR_DVU0_3
734#define SCUXDVUBR_DVU0_3 SCUX.DVUBR_DVU0_3
735#define SCUXDVUCR_DVU0_3 SCUX.DVUCR_DVU0_3
736#define SCUXZCMCR_DVU0_3 SCUX.ZCMCR_DVU0_3
737#define SCUXVRCTR_DVU0_3 SCUX.VRCTR_DVU0_3
738#define SCUXVRPDR_DVU0_3 SCUX.VRPDR_DVU0_3
739#define SCUXVRDBR_DVU0_3 SCUX.VRDBR_DVU0_3
740#define SCUXVRWTR_DVU0_3 SCUX.VRWTR_DVU0_3
741#define SCUXVOL0R_DVU0_3 SCUX.VOL0R_DVU0_3
742#define SCUXVOL1R_DVU0_3 SCUX.VOL1R_DVU0_3
743#define SCUXVOL2R_DVU0_3 SCUX.VOL2R_DVU0_3
744#define SCUXVOL3R_DVU0_3 SCUX.VOL3R_DVU0_3
745#define SCUXVOL4R_DVU0_3 SCUX.VOL4R_DVU0_3
746#define SCUXVOL5R_DVU0_3 SCUX.VOL5R_DVU0_3
747#define SCUXVOL6R_DVU0_3 SCUX.VOL6R_DVU0_3
748#define SCUXVOL7R_DVU0_3 SCUX.VOL7R_DVU0_3
749#define SCUXDVUER_DVU0_3 SCUX.DVUER_DVU0_3
750#define SCUXDVUSR_DVU0_3 SCUX.DVUSR_DVU0_3
751#define SCUXVEVMR_DVU0_3 SCUX.VEVMR_DVU0_3
752#define SCUXVEVCR_DVU0_3 SCUX.VEVCR_DVU0_3
753#define SCUXMIXIR_MIX0_0 SCUX.MIXIR_MIX0_0
754#define SCUXMADIR_MIX0_0 SCUX.MADIR_MIX0_0
755#define SCUXMIXBR_MIX0_0 SCUX.MIXBR_MIX0_0
756#define SCUXMIXMR_MIX0_0 SCUX.MIXMR_MIX0_0
757#define SCUXMVPDR_MIX0_0 SCUX.MVPDR_MIX0_0
758#define SCUXMDBAR_MIX0_0 SCUX.MDBAR_MIX0_0
759#define SCUXMDBBR_MIX0_0 SCUX.MDBBR_MIX0_0
760#define SCUXMDBCR_MIX0_0 SCUX.MDBCR_MIX0_0
761#define SCUXMDBDR_MIX0_0 SCUX.MDBDR_MIX0_0
762#define SCUXMDBER_MIX0_0 SCUX.MDBER_MIX0_0
763#define SCUXMIXSR_MIX0_0 SCUX.MIXSR_MIX0_0
764#define SCUXSWRSR_CIM SCUX.SWRSR_CIM
765#define SCUXDMACR_CIM SCUX.DMACR_CIM
766#define SCUXDMATD0_CIM SCUX.DMATD0_CIM.UINT32
767#define SCUXDMATD0_CIML SCUX.DMATD0_CIM.UINT16[L]
768#define SCUXDMATD0_CIMH SCUX.DMATD0_CIM.UINT16[H]
769#define SCUXDMATD1_CIM SCUX.DMATD1_CIM.UINT32
770#define SCUXDMATD1_CIML SCUX.DMATD1_CIM.UINT16[L]
771#define SCUXDMATD1_CIMH SCUX.DMATD1_CIM.UINT16[H]
772#define SCUXDMATD2_CIM SCUX.DMATD2_CIM.UINT32
773#define SCUXDMATD2_CIML SCUX.DMATD2_CIM.UINT16[L]
774#define SCUXDMATD2_CIMH SCUX.DMATD2_CIM.UINT16[H]
775#define SCUXDMATD3_CIM SCUX.DMATD3_CIM.UINT32
776#define SCUXDMATD3_CIML SCUX.DMATD3_CIM.UINT16[L]
777#define SCUXDMATD3_CIMH SCUX.DMATD3_CIM.UINT16[H]
778#define SCUXDMATU0_CIM SCUX.DMATU0_CIM.UINT32
779#define SCUXDMATU0_CIML SCUX.DMATU0_CIM.UINT16[L]
780#define SCUXDMATU0_CIMH SCUX.DMATU0_CIM.UINT16[H]
781#define SCUXDMATU1_CIM SCUX.DMATU1_CIM.UINT32
782#define SCUXDMATU1_CIML SCUX.DMATU1_CIM.UINT16[L]
783#define SCUXDMATU1_CIMH SCUX.DMATU1_CIM.UINT16[H]
784#define SCUXDMATU2_CIM SCUX.DMATU2_CIM.UINT32
785#define SCUXDMATU2_CIML SCUX.DMATU2_CIM.UINT16[L]
786#define SCUXDMATU2_CIMH SCUX.DMATU2_CIM.UINT16[H]
787#define SCUXDMATU3_CIM SCUX.DMATU3_CIM.UINT32
788#define SCUXDMATU3_CIML SCUX.DMATU3_CIM.UINT16[L]
789#define SCUXDMATU3_CIMH SCUX.DMATU3_CIM.UINT16[H]
790#define SCUXSSIRSEL_CIM SCUX.SSIRSEL_CIM
791#define SCUXFDTSEL0_CIM SCUX.FDTSEL0_CIM
792#define SCUXFDTSEL1_CIM SCUX.FDTSEL1_CIM
793#define SCUXFDTSEL2_CIM SCUX.FDTSEL2_CIM
794#define SCUXFDTSEL3_CIM SCUX.FDTSEL3_CIM
795#define SCUXFUTSEL0_CIM SCUX.FUTSEL0_CIM
796#define SCUXFUTSEL1_CIM SCUX.FUTSEL1_CIM
797#define SCUXFUTSEL2_CIM SCUX.FUTSEL2_CIM
798#define SCUXFUTSEL3_CIM SCUX.FUTSEL3_CIM
799#define SCUXSSIPMD_CIM SCUX.SSIPMD_CIM
800#define SCUXSSICTRL_CIM SCUX.SSICTRL_CIM
801#define SCUXSRCRSEL0_CIM SCUX.SRCRSEL0_CIM
802#define SCUXSRCRSEL1_CIM SCUX.SRCRSEL1_CIM
803#define SCUXSRCRSEL2_CIM SCUX.SRCRSEL2_CIM
804#define SCUXSRCRSEL3_CIM SCUX.SRCRSEL3_CIM
805#define SCUXMIXRSEL_CIM SCUX.MIXRSEL_CIM
806/* <-SEC M1.10.1 */
807/* <-QAC 0639 */
808#endif
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