Index: /asp_wio_terminal/trunk/target/samd51_gcc/Makefile.target
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/Makefile.target	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/Makefile.target	(revision 460)
@@ -0,0 +1,125 @@
+#
+#  @(#) $Id: Makefile.target 2709 2015-11-22 10:35:14Z ertl-honda $
+# 
+
+#
+#		Makefile ã®ã¿ã¼ã²ããä¾å­é¨ï¼SAMD51ç¨ï¼
+#
+
+#
+#  ãã¼ãåï¼ãã­ã»ããµåï¼éçºç°å¢åã®å®ç¾©
+#
+BOARD = samd51
+PRC = arm_m
+TOOL = gcc
+
+#
+#  ã³ã¢ã¿ã¤ã
+#
+CORE_TYPE = CORTEX_M4
+
+#
+#  FPUãä½¿ç¨ããã
+#
+FPU_USAGE = FPU_LAZYSTACKING
+
+#
+# Atmel Studioã§çæããã©ã¤ãã©ãªã®ç½®ãå ´æ
+#
+HARMONYDIR = $(TARGETDIR)/lib
+
+#
+# FPUã®ABI
+#
+FPU_ABI = hard
+
+#
+#  ã³ã³ãã¤ã«ãªãã·ã§ã³
+#
+INCLUDES :=  $(INCLUDES) -I$(TARGETDIR) \
+            -I"$(HARMONYDIR)" \
+
+COPTS := $(COPTS)
+LDFLAGS := $(LDFLAGS)
+CDEFS := $(CDEFS)
+CFG1_OUT_LDFLAGS := -nostdlib $(CFG1_OUT_LDFLAGS)
+
+#
+# ãã¡ã¤ã«ãµã¤ãºåæ¸ã®ããã®ãªãã·ã§ã³
+#
+COPTS   := $(COPTS) -ffunction-sections -fdata-sections
+LDFLAGS := $(LDFLAGS) -Wl,--gc-sections
+
+#
+#  ã«ã¼ãã«ã«é¢ããå®ç¾©
+#
+KERNEL_DIR := $(KERNEL_DIR) $(TARGETDIR) \
+              $(HARMONYDIR)
+
+KERNEL_ASMOBJS := $(KERNEL_ASMOBJS) start.o
+KERNEL_COBJS := $(KERNEL_COBJS) target_config.o core_timer.o \
+                plib_clock.o target_vector.o
+                
+#
+#  ã·ã¹ãã ãµã¼ãã¹ã«é¢ããå®ç¾©
+#
+SYSSVC_DIR := $(SYSSVC_DIR)
+SYSSVC_COBJS := $(SYSSVC_COBJS) target_serial.o 
+
+#
+#  ã³ã³ãã£ã®ã¥ã¬ã¼ã¿é¢ä¿ã®å¤æ°ã®å®ç¾©
+#
+CFG_TABS := $(CFG_TABS) 
+# --cfg1-def-table $(TARGETDIR)/target_def.csv
+
+#
+#  ãã¬ã¼ã¹ã­ã°ã«é¢ããè¨­å®
+#
+ifeq ($(ENABLE_TRACE),true)
+      COPTS := $(COPTS) 
+      CDEFS := $(CDEFS) -DTOPPERS_ENABLE_TRACE
+      KERNEL_DIR := $(KERNEL_DIR) $(SRCDIR)/arch/logtrace
+      KERNEL_COBJS := $(KERNEL_COBJS) trace_config.o trace_dump.o
+endif
+
+#
+#  GNUéçºç°å¢ã®ã¿ã¼ã²ããã¢ã¼ã­ãã¯ãã£ã®å®ç¾©
+#
+GCC_TARGET = arm-none-eabi
+
+#
+#  ãªã³ã«ã¹ã¯ãªããã®å®ç¾©
+#
+LDSCRIPT = $(TARGETDIR)/samd51.ld
+
+#
+#  ã¹ã¿ã¼ãã¢ããã¢ã¸ã¥ã¼ã«ã«é¢ããå®ç¾©
+#
+#  samd51.ldã«ãSTARTUP(start.o)ããè¨è¿°ããããï¼ã¹ã¿ã¼ãã¢ããã¢ã¸ã¥ã¼
+#  ã«ã®ååãHIDDEN_OBJSã«å®ç¾©ããï¼
+#
+# HIDDEN_OBJS = start.o
+# 
+# $(HIDDEN_OBJS): %.o: %.S
+# 	$(CC) -c $(CFLAGS) $(KERNEL_CFLAGS) $<
+# 
+# $(HIDDEN_OBJS:.o=.d): %.d: %.S
+# 	@$(PERL) $(SRCDIR)/utils/makedep -C $(CC) \
+# 		-O "$(CFLAGS) $(KERNEL_CFLAGS)" $< >> Makefile.depend
+
+#
+#  ä¾å­é¢ä¿ã®å®ç¾©
+#
+# cfg1_out.c: $(TARGETDIR)/target_def.csv
+kernel_cfg.timestamp: $(TARGETDIR)/target.tf
+$(OBJFILE): $(TARGETDIR)/target_check.tf
+
+# 
+#  ãªãã»ãããã¡ã¤ã«çæã®ããã®å®ç¾© 
+# 
+OFFSET_TF := $(TARGETDIR)/target_offset.tf
+
+#
+#  ãã­ã»ããµä¾å­é¨ã®ã¤ã³ã¯ã«ã¼ã
+#
+include $(SRCDIR)/arch/$(PRC)_$(TOOL)/common/Makefile.core
Index: /asp_wio_terminal/trunk/target/samd51_gcc/lib/atsamd51p19a.h
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/lib/atsamd51p19a.h	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/lib/atsamd51p19a.h	(revision 460)
@@ -0,0 +1,1109 @@
+/**
+ * \brief Header file for ATSAMD51P19A
+ *
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * Subject to your compliance with these terms, you may use Microchip software and any derivatives
+ * exclusively with Microchip products. It is your responsibility to comply with third party license
+ * terms applicable to your use of third party software (including open source software) that may
+ * accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
+ * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
+ * FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
+ * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
+ * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ */
+
+/* file generated from device description version 2020-03-12T17:25:57Z */
+#ifndef _SAMD51P19A_H_
+#define _SAMD51P19A_H_
+
+// Header version uses Semantic Versioning 2.0.0 (https://semver.org/)
+#define HEADER_FORMAT_VERSION "2.0.0"
+
+#define HEADER_FORMAT_VERSION_MAJOR (2)
+#define HEADER_FORMAT_VERSION_MINOR (0)
+
+/** \addtogroup SAMD51P19A_definitions SAMD51P19A definitions
+  This file defines all structures and symbols for SAMD51P19A:
+    - registers and bitfields
+    - peripheral base address
+    - peripheral ID
+    - PIO definitions
+ *  @{
+ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#  include <stdint.h>
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !defined(SKIP_INTEGER_LITERALS)
+#  if defined(_U_) || defined(_L_) || defined(_UL_)
+#    error "Integer Literals macros already defined elsewhere"
+#  endif
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
+#  define _U_(x) (x ## U)    /**< C code: Unsigned integer literal constant value */
+#  define _L_(x) (x ## L)    /**< C code: Long integer literal constant value */
+#  define _UL_(x) (x ## UL)  /**< C code: Unsigned Long integer literal constant value */
+
+#else /* Assembler */
+
+#  define _U_(x) x    /**< Assembler: Unsigned integer literal constant value */
+#  define _L_(x) x    /**< Assembler: Long integer literal constant value */
+#  define _UL_(x) x   /**< Assembler: Unsigned Long integer literal constant value */
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* SKIP_INTEGER_LITERALS */
+/** @}  end of Atmel Global Defines */
+
+/* ************************************************************************** */
+/*   CMSIS DEFINITIONS FOR SAMD51P19A                                         */
+/* ************************************************************************** */
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  CORTEX-M4 Processor Exceptions Numbers ******************************/
+  Reset_IRQn                = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */
+  NonMaskableInt_IRQn       = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */
+  HardFault_IRQn            = -13, /**< -13 Hard Fault, all classes of Fault    */
+  MemoryManagement_IRQn     = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */
+  BusFault_IRQn             = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+  UsageFault_IRQn           = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+  SVCall_IRQn               =  -5, /**< -5  System Service Call via SVC instruction */
+  DebugMonitor_IRQn         =  -4, /**< -4  Debug Monitor                       */
+  PendSV_IRQn               =  -2, /**< -2  Pendable request for system service */
+  SysTick_IRQn              =  -1, /**< -1  System Tick Timer                   */
+/******  SAMD51P19A specific Interrupt Numbers ***********************************/
+  PM_IRQn                   =   0, /**< 0   Power Manager (PM)                  */
+  MCLK_IRQn                 =   1, /**< 1   Main Clock (MCLK)                   */
+  OSCCTRL_XOSC0_IRQn        =   2, /**< 2   Oscillators Control (OSCCTRL)       */
+  OSCCTRL_XOSC1_IRQn        =   3, /**< 3   Oscillators Control (OSCCTRL)       */
+  OSCCTRL_DFLL_IRQn         =   4, /**< 4   Oscillators Control (OSCCTRL)       */
+  OSCCTRL_DPLL0_IRQn        =   5, /**< 5   Oscillators Control (OSCCTRL)       */
+  OSCCTRL_DPLL1_IRQn        =   6, /**< 6   Oscillators Control (OSCCTRL)       */
+  OSC32KCTRL_IRQn           =   7, /**< 7   32kHz Oscillators Control (OSC32KCTRL) */
+  SUPC_OTHER_IRQn           =   8, /**< 8   Supply Controller (SUPC)            */
+  SUPC_BODDET_IRQn          =   9, /**< 9   Supply Controller (SUPC)            */
+  WDT_IRQn                  =  10, /**< 10  Watchdog Timer (WDT)                */
+  RTC_IRQn                  =  11, /**< 11  Real-Time Counter (RTC)             */
+  EIC_EXTINT_0_IRQn         =  12, /**< 12  External Interrupt Controller (EIC) */
+  EIC_EXTINT_1_IRQn         =  13, /**< 13  External Interrupt Controller (EIC) */
+  EIC_EXTINT_2_IRQn         =  14, /**< 14  External Interrupt Controller (EIC) */
+  EIC_EXTINT_3_IRQn         =  15, /**< 15  External Interrupt Controller (EIC) */
+  EIC_EXTINT_4_IRQn         =  16, /**< 16  External Interrupt Controller (EIC) */
+  EIC_EXTINT_5_IRQn         =  17, /**< 17  External Interrupt Controller (EIC) */
+  EIC_EXTINT_6_IRQn         =  18, /**< 18  External Interrupt Controller (EIC) */
+  EIC_EXTINT_7_IRQn         =  19, /**< 19  External Interrupt Controller (EIC) */
+  EIC_EXTINT_8_IRQn         =  20, /**< 20  External Interrupt Controller (EIC) */
+  EIC_EXTINT_9_IRQn         =  21, /**< 21  External Interrupt Controller (EIC) */
+  EIC_EXTINT_10_IRQn        =  22, /**< 22  External Interrupt Controller (EIC) */
+  EIC_EXTINT_11_IRQn        =  23, /**< 23  External Interrupt Controller (EIC) */
+  EIC_EXTINT_12_IRQn        =  24, /**< 24  External Interrupt Controller (EIC) */
+  EIC_EXTINT_13_IRQn        =  25, /**< 25  External Interrupt Controller (EIC) */
+  EIC_EXTINT_14_IRQn        =  26, /**< 26  External Interrupt Controller (EIC) */
+  EIC_EXTINT_15_IRQn        =  27, /**< 27  External Interrupt Controller (EIC) */
+  FREQM_IRQn                =  28, /**< 28  Frequency Meter (FREQM)             */
+  NVMCTRL_0_IRQn            =  29, /**< 29  Non-Volatile Memory Controller (NVMCTRL) */
+  NVMCTRL_1_IRQn            =  30, /**< 30  Non-Volatile Memory Controller (NVMCTRL) */
+  DMAC_0_IRQn               =  31, /**< 31  Direct Memory Access Controller (DMAC) */
+  DMAC_1_IRQn               =  32, /**< 32  Direct Memory Access Controller (DMAC) */
+  DMAC_2_IRQn               =  33, /**< 33  Direct Memory Access Controller (DMAC) */
+  DMAC_3_IRQn               =  34, /**< 34  Direct Memory Access Controller (DMAC) */
+  DMAC_OTHER_IRQn           =  35, /**< 35  Direct Memory Access Controller (DMAC) */
+  EVSYS_0_IRQn              =  36, /**< 36  Event System Interface (EVSYS)      */
+  EVSYS_1_IRQn              =  37, /**< 37  Event System Interface (EVSYS)      */
+  EVSYS_2_IRQn              =  38, /**< 38  Event System Interface (EVSYS)      */
+  EVSYS_3_IRQn              =  39, /**< 39  Event System Interface (EVSYS)      */
+  EVSYS_OTHER_IRQn          =  40, /**< 40  Event System Interface (EVSYS)      */
+  PAC_IRQn                  =  41, /**< 41  Peripheral Access Controller (PAC)  */
+  RAMECC_IRQn               =  45, /**< 45  RAM ECC (RAMECC)                    */
+  SERCOM0_0_IRQn            =  46, /**< 46  Serial Communication Interface (SERCOM0) */
+  SERCOM0_1_IRQn            =  47, /**< 47  Serial Communication Interface (SERCOM0) */
+  SERCOM0_2_IRQn            =  48, /**< 48  Serial Communication Interface (SERCOM0) */
+  SERCOM0_OTHER_IRQn        =  49, /**< 49  Serial Communication Interface (SERCOM0) */
+  SERCOM1_0_IRQn            =  50, /**< 50  Serial Communication Interface (SERCOM1) */
+  SERCOM1_1_IRQn            =  51, /**< 51  Serial Communication Interface (SERCOM1) */
+  SERCOM1_2_IRQn            =  52, /**< 52  Serial Communication Interface (SERCOM1) */
+  SERCOM1_OTHER_IRQn        =  53, /**< 53  Serial Communication Interface (SERCOM1) */
+  SERCOM2_0_IRQn            =  54, /**< 54  Serial Communication Interface (SERCOM2) */
+  SERCOM2_1_IRQn            =  55, /**< 55  Serial Communication Interface (SERCOM2) */
+  SERCOM2_2_IRQn            =  56, /**< 56  Serial Communication Interface (SERCOM2) */
+  SERCOM2_OTHER_IRQn        =  57, /**< 57  Serial Communication Interface (SERCOM2) */
+  SERCOM3_0_IRQn            =  58, /**< 58  Serial Communication Interface (SERCOM3) */
+  SERCOM3_1_IRQn            =  59, /**< 59  Serial Communication Interface (SERCOM3) */
+  SERCOM3_2_IRQn            =  60, /**< 60  Serial Communication Interface (SERCOM3) */
+  SERCOM3_OTHER_IRQn        =  61, /**< 61  Serial Communication Interface (SERCOM3) */
+  SERCOM4_0_IRQn            =  62, /**< 62  Serial Communication Interface (SERCOM4) */
+  SERCOM4_1_IRQn            =  63, /**< 63  Serial Communication Interface (SERCOM4) */
+  SERCOM4_2_IRQn            =  64, /**< 64  Serial Communication Interface (SERCOM4) */
+  SERCOM4_OTHER_IRQn        =  65, /**< 65  Serial Communication Interface (SERCOM4) */
+  SERCOM5_0_IRQn            =  66, /**< 66  Serial Communication Interface (SERCOM5) */
+  SERCOM5_1_IRQn            =  67, /**< 67  Serial Communication Interface (SERCOM5) */
+  SERCOM5_2_IRQn            =  68, /**< 68  Serial Communication Interface (SERCOM5) */
+  SERCOM5_OTHER_IRQn        =  69, /**< 69  Serial Communication Interface (SERCOM5) */
+  SERCOM6_0_IRQn            =  70, /**< 70  Serial Communication Interface (SERCOM6) */
+  SERCOM6_1_IRQn            =  71, /**< 71  Serial Communication Interface (SERCOM6) */
+  SERCOM6_2_IRQn            =  72, /**< 72  Serial Communication Interface (SERCOM6) */
+  SERCOM6_OTHER_IRQn        =  73, /**< 73  Serial Communication Interface (SERCOM6) */
+  SERCOM7_0_IRQn            =  74, /**< 74  Serial Communication Interface (SERCOM7) */
+  SERCOM7_1_IRQn            =  75, /**< 75  Serial Communication Interface (SERCOM7) */
+  SERCOM7_2_IRQn            =  76, /**< 76  Serial Communication Interface (SERCOM7) */
+  SERCOM7_OTHER_IRQn        =  77, /**< 77  Serial Communication Interface (SERCOM7) */
+  USB_OTHER_IRQn            =  80, /**< 80  Universal Serial Bus (USB)          */
+  USB_SOF_HSOF_IRQn         =  81, /**< 81  Universal Serial Bus (USB)          */
+  USB_TRCPT0_IRQn           =  82, /**< 82  Universal Serial Bus (USB)          */
+  USB_TRCPT1_IRQn           =  83, /**< 83  Universal Serial Bus (USB)          */
+  TCC0_OTHER_IRQn           =  85, /**< 85  Timer Counter Control (TCC0)        */
+  TCC0_MC0_IRQn             =  86, /**< 86  Timer Counter Control (TCC0)        */
+  TCC0_MC1_IRQn             =  87, /**< 87  Timer Counter Control (TCC0)        */
+  TCC0_MC2_IRQn             =  88, /**< 88  Timer Counter Control (TCC0)        */
+  TCC0_MC3_IRQn             =  89, /**< 89  Timer Counter Control (TCC0)        */
+  TCC0_MC4_IRQn             =  90, /**< 90  Timer Counter Control (TCC0)        */
+  TCC0_MC5_IRQn             =  91, /**< 91  Timer Counter Control (TCC0)        */
+  TCC1_OTHER_IRQn           =  92, /**< 92  Timer Counter Control (TCC1)        */
+  TCC1_MC0_IRQn             =  93, /**< 93  Timer Counter Control (TCC1)        */
+  TCC1_MC1_IRQn             =  94, /**< 94  Timer Counter Control (TCC1)        */
+  TCC1_MC2_IRQn             =  95, /**< 95  Timer Counter Control (TCC1)        */
+  TCC1_MC3_IRQn             =  96, /**< 96  Timer Counter Control (TCC1)        */
+  TCC2_OTHER_IRQn           =  97, /**< 97  Timer Counter Control (TCC2)        */
+  TCC2_MC0_IRQn             =  98, /**< 98  Timer Counter Control (TCC2)        */
+  TCC2_MC1_IRQn             =  99, /**< 99  Timer Counter Control (TCC2)        */
+  TCC2_MC2_IRQn             = 100, /**< 100 Timer Counter Control (TCC2)        */
+  TCC3_OTHER_IRQn           = 101, /**< 101 Timer Counter Control (TCC3)        */
+  TCC3_MC0_IRQn             = 102, /**< 102 Timer Counter Control (TCC3)        */
+  TCC3_MC1_IRQn             = 103, /**< 103 Timer Counter Control (TCC3)        */
+  TCC4_OTHER_IRQn           = 104, /**< 104 Timer Counter Control (TCC4)        */
+  TCC4_MC0_IRQn             = 105, /**< 105 Timer Counter Control (TCC4)        */
+  TCC4_MC1_IRQn             = 106, /**< 106 Timer Counter Control (TCC4)        */
+  TC0_IRQn                  = 107, /**< 107 Basic Timer Counter (TC0)           */
+  TC1_IRQn                  = 108, /**< 108 Basic Timer Counter (TC1)           */
+  TC2_IRQn                  = 109, /**< 109 Basic Timer Counter (TC2)           */
+  TC3_IRQn                  = 110, /**< 110 Basic Timer Counter (TC3)           */
+  TC4_IRQn                  = 111, /**< 111 Basic Timer Counter (TC4)           */
+  TC5_IRQn                  = 112, /**< 112 Basic Timer Counter (TC5)           */
+  TC6_IRQn                  = 113, /**< 113 Basic Timer Counter (TC6)           */
+  TC7_IRQn                  = 114, /**< 114 Basic Timer Counter (TC7)           */
+  PDEC_OTHER_IRQn           = 115, /**< 115 Quadrature Decodeur (PDEC)          */
+  PDEC_MC0_IRQn             = 116, /**< 116 Quadrature Decodeur (PDEC)          */
+  PDEC_MC1_IRQn             = 117, /**< 117 Quadrature Decodeur (PDEC)          */
+  ADC0_OTHER_IRQn           = 118, /**< 118 Analog Digital Converter (ADC0)     */
+  ADC0_RESRDY_IRQn          = 119, /**< 119 Analog Digital Converter (ADC0)     */
+  ADC1_OTHER_IRQn           = 120, /**< 120 Analog Digital Converter (ADC1)     */
+  ADC1_RESRDY_IRQn          = 121, /**< 121 Analog Digital Converter (ADC1)     */
+  AC_IRQn                   = 122, /**< 122 Analog Comparators (AC)             */
+  DAC_OTHER_IRQn            = 123, /**< 123 Digital-to-Analog Converter (DAC)   */
+  DAC_EMPTY_0_IRQn          = 124, /**< 124 Digital-to-Analog Converter (DAC)   */
+  DAC_EMPTY_1_IRQn          = 125, /**< 125 Digital-to-Analog Converter (DAC)   */
+  DAC_RESRDY_0_IRQn         = 126, /**< 126 Digital-to-Analog Converter (DAC)   */
+  DAC_RESRDY_1_IRQn         = 127, /**< 127 Digital-to-Analog Converter (DAC)   */
+  I2S_IRQn                  = 128, /**< 128 Inter-IC Sound Interface (I2S)      */
+  PCC_IRQn                  = 129, /**< 129 Parallel Capture Controller (PCC)   */
+  AES_IRQn                  = 130, /**< 130 Advanced Encryption Standard (AES)  */
+  TRNG_IRQn                 = 131, /**< 131 True Random Generator (TRNG)        */
+  ICM_IRQn                  = 132, /**< 132 Integrity Check Monitor (ICM)       */
+  PUKCC_IRQn                = 133, /**< 133 PUblic-Key Cryptography Controller (PUKCC) */
+  QSPI_IRQn                 = 134, /**< 134 Quad SPI interface (QSPI)           */
+  SDHC0_IRQn                = 135, /**< 135 SD/MMC Host Controller (SDHC0)      */
+  SDHC1_IRQn                = 136, /**< 136 SD/MMC Host Controller (SDHC1)      */
+
+  PERIPH_MAX_IRQn           = 136  /**< Max peripheral ID */
+} IRQn_Type;
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct _DeviceVectors
+{
+  /* Stack pointer */
+  void* pvStack;
+  /* Cortex-M handlers */
+  void* pfnReset_Handler;                        /* -15 Reset Vector, invoked on Power up and warm reset */
+  void* pfnNonMaskableInt_Handler;               /* -14 Non maskable Interrupt, cannot be stopped or preempted */
+  void* pfnHardFault_Handler;                    /* -13 Hard Fault, all classes of Fault */
+  void* pfnMemoryManagement_Handler;             /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */
+  void* pfnBusFault_Handler;                     /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+  void* pfnUsageFault_Handler;                   /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+  void* pvReservedC9;
+  void* pvReservedC8;
+  void* pvReservedC7;
+  void* pvReservedC6;
+  void* pfnSVCall_Handler;                       /*  -5 System Service Call via SVC instruction */
+  void* pfnDebugMonitor_Handler;                 /*  -4 Debug Monitor */
+  void* pvReservedC3;
+  void* pfnPendSV_Handler;                       /*  -2 Pendable request for system service */
+  void* pfnSysTick_Handler;                      /*  -1 System Tick Timer */
+
+  /* Peripheral handlers */
+  void* pfnPM_Handler;                           /*   0 Power Manager (PM) */
+  void* pfnMCLK_Handler;                         /*   1 Main Clock (MCLK) */
+  void* pfnOSCCTRL_XOSC0_Handler;                /*   2 Oscillators Control (OSCCTRL) */
+  void* pfnOSCCTRL_XOSC1_Handler;                /*   3 Oscillators Control (OSCCTRL) */
+  void* pfnOSCCTRL_DFLL_Handler;                 /*   4 Oscillators Control (OSCCTRL) */
+  void* pfnOSCCTRL_DPLL0_Handler;                /*   5 Oscillators Control (OSCCTRL) */
+  void* pfnOSCCTRL_DPLL1_Handler;                /*   6 Oscillators Control (OSCCTRL) */
+  void* pfnOSC32KCTRL_Handler;                   /*   7 32kHz Oscillators Control (OSC32KCTRL) */
+  void* pfnSUPC_OTHER_Handler;                   /*   8 Supply Controller (SUPC) */
+  void* pfnSUPC_BODDET_Handler;                  /*   9 Supply Controller (SUPC) */
+  void* pfnWDT_Handler;                          /*  10 Watchdog Timer (WDT) */
+  void* pfnRTC_Handler;                          /*  11 Real-Time Counter (RTC) */
+  void* pfnEIC_EXTINT_0_Handler;                 /*  12 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT_1_Handler;                 /*  13 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT_2_Handler;                 /*  14 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT_3_Handler;                 /*  15 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT_4_Handler;                 /*  16 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT_5_Handler;                 /*  17 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT_6_Handler;                 /*  18 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT_7_Handler;                 /*  19 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT_8_Handler;                 /*  20 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT_9_Handler;                 /*  21 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT_10_Handler;                /*  22 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT_11_Handler;                /*  23 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT_12_Handler;                /*  24 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT_13_Handler;                /*  25 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT_14_Handler;                /*  26 External Interrupt Controller (EIC) */
+  void* pfnEIC_EXTINT_15_Handler;                /*  27 External Interrupt Controller (EIC) */
+  void* pfnFREQM_Handler;                        /*  28 Frequency Meter (FREQM) */
+  void* pfnNVMCTRL_0_Handler;                    /*  29 Non-Volatile Memory Controller (NVMCTRL) */
+  void* pfnNVMCTRL_1_Handler;                    /*  30 Non-Volatile Memory Controller (NVMCTRL) */
+  void* pfnDMAC_0_Handler;                       /*  31 Direct Memory Access Controller (DMAC) */
+  void* pfnDMAC_1_Handler;                       /*  32 Direct Memory Access Controller (DMAC) */
+  void* pfnDMAC_2_Handler;                       /*  33 Direct Memory Access Controller (DMAC) */
+  void* pfnDMAC_3_Handler;                       /*  34 Direct Memory Access Controller (DMAC) */
+  void* pfnDMAC_OTHER_Handler;                   /*  35 Direct Memory Access Controller (DMAC) */
+  void* pfnEVSYS_0_Handler;                      /*  36 Event System Interface (EVSYS) */
+  void* pfnEVSYS_1_Handler;                      /*  37 Event System Interface (EVSYS) */
+  void* pfnEVSYS_2_Handler;                      /*  38 Event System Interface (EVSYS) */
+  void* pfnEVSYS_3_Handler;                      /*  39 Event System Interface (EVSYS) */
+  void* pfnEVSYS_OTHER_Handler;                  /*  40 Event System Interface (EVSYS) */
+  void* pfnPAC_Handler;                          /*  41 Peripheral Access Controller (PAC) */
+  void* pvReserved42;
+  void* pvReserved43;
+  void* pvReserved44;
+  void* pfnRAMECC_Handler;                       /*  45 RAM ECC (RAMECC) */
+  void* pfnSERCOM0_0_Handler;                    /*  46 Serial Communication Interface (SERCOM0) */
+  void* pfnSERCOM0_1_Handler;                    /*  47 Serial Communication Interface (SERCOM0) */
+  void* pfnSERCOM0_2_Handler;                    /*  48 Serial Communication Interface (SERCOM0) */
+  void* pfnSERCOM0_OTHER_Handler;                /*  49 Serial Communication Interface (SERCOM0) */
+  void* pfnSERCOM1_0_Handler;                    /*  50 Serial Communication Interface (SERCOM1) */
+  void* pfnSERCOM1_1_Handler;                    /*  51 Serial Communication Interface (SERCOM1) */
+  void* pfnSERCOM1_2_Handler;                    /*  52 Serial Communication Interface (SERCOM1) */
+  void* pfnSERCOM1_OTHER_Handler;                /*  53 Serial Communication Interface (SERCOM1) */
+  void* pfnSERCOM2_0_Handler;                    /*  54 Serial Communication Interface (SERCOM2) */
+  void* pfnSERCOM2_1_Handler;                    /*  55 Serial Communication Interface (SERCOM2) */
+  void* pfnSERCOM2_2_Handler;                    /*  56 Serial Communication Interface (SERCOM2) */
+  void* pfnSERCOM2_OTHER_Handler;                /*  57 Serial Communication Interface (SERCOM2) */
+  void* pfnSERCOM3_0_Handler;                    /*  58 Serial Communication Interface (SERCOM3) */
+  void* pfnSERCOM3_1_Handler;                    /*  59 Serial Communication Interface (SERCOM3) */
+  void* pfnSERCOM3_2_Handler;                    /*  60 Serial Communication Interface (SERCOM3) */
+  void* pfnSERCOM3_OTHER_Handler;                /*  61 Serial Communication Interface (SERCOM3) */
+  void* pfnSERCOM4_0_Handler;                    /*  62 Serial Communication Interface (SERCOM4) */
+  void* pfnSERCOM4_1_Handler;                    /*  63 Serial Communication Interface (SERCOM4) */
+  void* pfnSERCOM4_2_Handler;                    /*  64 Serial Communication Interface (SERCOM4) */
+  void* pfnSERCOM4_OTHER_Handler;                /*  65 Serial Communication Interface (SERCOM4) */
+  void* pfnSERCOM5_0_Handler;                    /*  66 Serial Communication Interface (SERCOM5) */
+  void* pfnSERCOM5_1_Handler;                    /*  67 Serial Communication Interface (SERCOM5) */
+  void* pfnSERCOM5_2_Handler;                    /*  68 Serial Communication Interface (SERCOM5) */
+  void* pfnSERCOM5_OTHER_Handler;                /*  69 Serial Communication Interface (SERCOM5) */
+  void* pfnSERCOM6_0_Handler;                    /*  70 Serial Communication Interface (SERCOM6) */
+  void* pfnSERCOM6_1_Handler;                    /*  71 Serial Communication Interface (SERCOM6) */
+  void* pfnSERCOM6_2_Handler;                    /*  72 Serial Communication Interface (SERCOM6) */
+  void* pfnSERCOM6_OTHER_Handler;                /*  73 Serial Communication Interface (SERCOM6) */
+  void* pfnSERCOM7_0_Handler;                    /*  74 Serial Communication Interface (SERCOM7) */
+  void* pfnSERCOM7_1_Handler;                    /*  75 Serial Communication Interface (SERCOM7) */
+  void* pfnSERCOM7_2_Handler;                    /*  76 Serial Communication Interface (SERCOM7) */
+  void* pfnSERCOM7_OTHER_Handler;                /*  77 Serial Communication Interface (SERCOM7) */
+  void* pvReserved78;
+  void* pvReserved79;
+  void* pfnUSB_OTHER_Handler;                    /*  80 Universal Serial Bus (USB) */
+  void* pfnUSB_SOF_HSOF_Handler;                 /*  81 Universal Serial Bus (USB) */
+  void* pfnUSB_TRCPT0_Handler;                   /*  82 Universal Serial Bus (USB) */
+  void* pfnUSB_TRCPT1_Handler;                   /*  83 Universal Serial Bus (USB) */
+  void* pvReserved84;
+  void* pfnTCC0_OTHER_Handler;                   /*  85 Timer Counter Control (TCC0) */
+  void* pfnTCC0_MC0_Handler;                     /*  86 Timer Counter Control (TCC0) */
+  void* pfnTCC0_MC1_Handler;                     /*  87 Timer Counter Control (TCC0) */
+  void* pfnTCC0_MC2_Handler;                     /*  88 Timer Counter Control (TCC0) */
+  void* pfnTCC0_MC3_Handler;                     /*  89 Timer Counter Control (TCC0) */
+  void* pfnTCC0_MC4_Handler;                     /*  90 Timer Counter Control (TCC0) */
+  void* pfnTCC0_MC5_Handler;                     /*  91 Timer Counter Control (TCC0) */
+  void* pfnTCC1_OTHER_Handler;                   /*  92 Timer Counter Control (TCC1) */
+  void* pfnTCC1_MC0_Handler;                     /*  93 Timer Counter Control (TCC1) */
+  void* pfnTCC1_MC1_Handler;                     /*  94 Timer Counter Control (TCC1) */
+  void* pfnTCC1_MC2_Handler;                     /*  95 Timer Counter Control (TCC1) */
+  void* pfnTCC1_MC3_Handler;                     /*  96 Timer Counter Control (TCC1) */
+  void* pfnTCC2_OTHER_Handler;                   /*  97 Timer Counter Control (TCC2) */
+  void* pfnTCC2_MC0_Handler;                     /*  98 Timer Counter Control (TCC2) */
+  void* pfnTCC2_MC1_Handler;                     /*  99 Timer Counter Control (TCC2) */
+  void* pfnTCC2_MC2_Handler;                     /* 100 Timer Counter Control (TCC2) */
+  void* pfnTCC3_OTHER_Handler;                   /* 101 Timer Counter Control (TCC3) */
+  void* pfnTCC3_MC0_Handler;                     /* 102 Timer Counter Control (TCC3) */
+  void* pfnTCC3_MC1_Handler;                     /* 103 Timer Counter Control (TCC3) */
+  void* pfnTCC4_OTHER_Handler;                   /* 104 Timer Counter Control (TCC4) */
+  void* pfnTCC4_MC0_Handler;                     /* 105 Timer Counter Control (TCC4) */
+  void* pfnTCC4_MC1_Handler;                     /* 106 Timer Counter Control (TCC4) */
+  void* pfnTC0_Handler;                          /* 107 Basic Timer Counter (TC0) */
+  void* pfnTC1_Handler;                          /* 108 Basic Timer Counter (TC1) */
+  void* pfnTC2_Handler;                          /* 109 Basic Timer Counter (TC2) */
+  void* pfnTC3_Handler;                          /* 110 Basic Timer Counter (TC3) */
+  void* pfnTC4_Handler;                          /* 111 Basic Timer Counter (TC4) */
+  void* pfnTC5_Handler;                          /* 112 Basic Timer Counter (TC5) */
+  void* pfnTC6_Handler;                          /* 113 Basic Timer Counter (TC6) */
+  void* pfnTC7_Handler;                          /* 114 Basic Timer Counter (TC7) */
+  void* pfnPDEC_OTHER_Handler;                   /* 115 Quadrature Decodeur (PDEC) */
+  void* pfnPDEC_MC0_Handler;                     /* 116 Quadrature Decodeur (PDEC) */
+  void* pfnPDEC_MC1_Handler;                     /* 117 Quadrature Decodeur (PDEC) */
+  void* pfnADC0_OTHER_Handler;                   /* 118 Analog Digital Converter (ADC0) */
+  void* pfnADC0_RESRDY_Handler;                  /* 119 Analog Digital Converter (ADC0) */
+  void* pfnADC1_OTHER_Handler;                   /* 120 Analog Digital Converter (ADC1) */
+  void* pfnADC1_RESRDY_Handler;                  /* 121 Analog Digital Converter (ADC1) */
+  void* pfnAC_Handler;                           /* 122 Analog Comparators (AC) */
+  void* pfnDAC_OTHER_Handler;                    /* 123 Digital-to-Analog Converter (DAC) */
+  void* pfnDAC_EMPTY_0_Handler;                  /* 124 Digital-to-Analog Converter (DAC) */
+  void* pfnDAC_EMPTY_1_Handler;                  /* 125 Digital-to-Analog Converter (DAC) */
+  void* pfnDAC_RESRDY_0_Handler;                 /* 126 Digital-to-Analog Converter (DAC) */
+  void* pfnDAC_RESRDY_1_Handler;                 /* 127 Digital-to-Analog Converter (DAC) */
+  void* pfnI2S_Handler;                          /* 128 Inter-IC Sound Interface (I2S) */
+  void* pfnPCC_Handler;                          /* 129 Parallel Capture Controller (PCC) */
+  void* pfnAES_Handler;                          /* 130 Advanced Encryption Standard (AES) */
+  void* pfnTRNG_Handler;                         /* 131 True Random Generator (TRNG) */
+  void* pfnICM_Handler;                          /* 132 Integrity Check Monitor (ICM) */
+  void* pfnPUKCC_Handler;                        /* 133 PUblic-Key Cryptography Controller (PUKCC) */
+  void* pfnQSPI_Handler;                         /* 134 Quad SPI interface (QSPI) */
+  void* pfnSDHC0_Handler;                        /* 135 SD/MMC Host Controller (SDHC0) */
+  void* pfnSDHC1_Handler;                        /* 136 SD/MMC Host Controller (SDHC1) */
+} DeviceVectors;
+
+/* Defines for Deprecated Interrupt and Exceptions handler names */
+#define pfnMemManage_Handler      pfnMemoryManagement_Handler     /**< \deprecated  Backward compatibility for ASF*/
+#define pfnDebugMon_Handler       pfnDebugMonitor_Handler         /**< \deprecated  Backward compatibility for ASF*/
+#define pfnNMI_Handler            pfnNonMaskableInt_Handler       /**< \deprecated  Backward compatibility for ASF*/
+#define pfnSVC_Handler            pfnSVCall_Handler               /**< \deprecated  Backward compatibility for ASF*/
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS
+/* CORTEX-M4 exception handlers */
+void Reset_Handler                 ( void );
+void NonMaskableInt_Handler        ( void );
+void HardFault_Handler             ( void );
+void MemoryManagement_Handler      ( void );
+void BusFault_Handler              ( void );
+void UsageFault_Handler            ( void );
+void SVCall_Handler                ( void );
+void DebugMonitor_Handler          ( void );
+void PendSV_Handler                ( void );
+void SysTick_Handler               ( void );
+#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */
+
+#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
+/* Peripherals interrupt handlers */
+void PM_Handler                    ( void );
+void MCLK_Handler                  ( void );
+void OSCCTRL_XOSC0_Handler         ( void );
+void OSCCTRL_XOSC1_Handler         ( void );
+void OSCCTRL_DFLL_Handler          ( void );
+void OSCCTRL_DPLL0_Handler         ( void );
+void OSCCTRL_DPLL1_Handler         ( void );
+void OSC32KCTRL_Handler            ( void );
+void SUPC_OTHER_Handler            ( void );
+void SUPC_BODDET_Handler           ( void );
+void WDT_Handler                   ( void );
+void RTC_Handler                   ( void );
+void EIC_EXTINT_0_Handler          ( void );
+void EIC_EXTINT_1_Handler          ( void );
+void EIC_EXTINT_2_Handler          ( void );
+void EIC_EXTINT_3_Handler          ( void );
+void EIC_EXTINT_4_Handler          ( void );
+void EIC_EXTINT_5_Handler          ( void );
+void EIC_EXTINT_6_Handler          ( void );
+void EIC_EXTINT_7_Handler          ( void );
+void EIC_EXTINT_8_Handler          ( void );
+void EIC_EXTINT_9_Handler          ( void );
+void EIC_EXTINT_10_Handler         ( void );
+void EIC_EXTINT_11_Handler         ( void );
+void EIC_EXTINT_12_Handler         ( void );
+void EIC_EXTINT_13_Handler         ( void );
+void EIC_EXTINT_14_Handler         ( void );
+void EIC_EXTINT_15_Handler         ( void );
+void FREQM_Handler                 ( void );
+void NVMCTRL_0_Handler             ( void );
+void NVMCTRL_1_Handler             ( void );
+void DMAC_0_Handler                ( void );
+void DMAC_1_Handler                ( void );
+void DMAC_2_Handler                ( void );
+void DMAC_3_Handler                ( void );
+void DMAC_OTHER_Handler            ( void );
+void EVSYS_0_Handler               ( void );
+void EVSYS_1_Handler               ( void );
+void EVSYS_2_Handler               ( void );
+void EVSYS_3_Handler               ( void );
+void EVSYS_OTHER_Handler           ( void );
+void PAC_Handler                   ( void );
+void RAMECC_Handler                ( void );
+void SERCOM0_0_Handler             ( void );
+void SERCOM0_1_Handler             ( void );
+void SERCOM0_2_Handler             ( void );
+void SERCOM0_OTHER_Handler         ( void );
+void SERCOM1_0_Handler             ( void );
+void SERCOM1_1_Handler             ( void );
+void SERCOM1_2_Handler             ( void );
+void SERCOM1_OTHER_Handler         ( void );
+void SERCOM2_0_Handler             ( void );
+void SERCOM2_1_Handler             ( void );
+void SERCOM2_2_Handler             ( void );
+void SERCOM2_OTHER_Handler         ( void );
+void SERCOM3_0_Handler             ( void );
+void SERCOM3_1_Handler             ( void );
+void SERCOM3_2_Handler             ( void );
+void SERCOM3_OTHER_Handler         ( void );
+void SERCOM4_0_Handler             ( void );
+void SERCOM4_1_Handler             ( void );
+void SERCOM4_2_Handler             ( void );
+void SERCOM4_OTHER_Handler         ( void );
+void SERCOM5_0_Handler             ( void );
+void SERCOM5_1_Handler             ( void );
+void SERCOM5_2_Handler             ( void );
+void SERCOM5_OTHER_Handler         ( void );
+void SERCOM6_0_Handler             ( void );
+void SERCOM6_1_Handler             ( void );
+void SERCOM6_2_Handler             ( void );
+void SERCOM6_OTHER_Handler         ( void );
+void SERCOM7_0_Handler             ( void );
+void SERCOM7_1_Handler             ( void );
+void SERCOM7_2_Handler             ( void );
+void SERCOM7_OTHER_Handler         ( void );
+void USB_OTHER_Handler             ( void );
+void USB_SOF_HSOF_Handler          ( void );
+void USB_TRCPT0_Handler            ( void );
+void USB_TRCPT1_Handler            ( void );
+void TCC0_OTHER_Handler            ( void );
+void TCC0_MC0_Handler              ( void );
+void TCC0_MC1_Handler              ( void );
+void TCC0_MC2_Handler              ( void );
+void TCC0_MC3_Handler              ( void );
+void TCC0_MC4_Handler              ( void );
+void TCC0_MC5_Handler              ( void );
+void TCC1_OTHER_Handler            ( void );
+void TCC1_MC0_Handler              ( void );
+void TCC1_MC1_Handler              ( void );
+void TCC1_MC2_Handler              ( void );
+void TCC1_MC3_Handler              ( void );
+void TCC2_OTHER_Handler            ( void );
+void TCC2_MC0_Handler              ( void );
+void TCC2_MC1_Handler              ( void );
+void TCC2_MC2_Handler              ( void );
+void TCC3_OTHER_Handler            ( void );
+void TCC3_MC0_Handler              ( void );
+void TCC3_MC1_Handler              ( void );
+void TCC4_OTHER_Handler            ( void );
+void TCC4_MC0_Handler              ( void );
+void TCC4_MC1_Handler              ( void );
+void TC0_Handler                   ( void );
+void TC1_Handler                   ( void );
+void TC2_Handler                   ( void );
+void TC3_Handler                   ( void );
+void TC4_Handler                   ( void );
+void TC5_Handler                   ( void );
+void TC6_Handler                   ( void );
+void TC7_Handler                   ( void );
+void PDEC_OTHER_Handler            ( void );
+void PDEC_MC0_Handler              ( void );
+void PDEC_MC1_Handler              ( void );
+void ADC0_OTHER_Handler            ( void );
+void ADC0_RESRDY_Handler           ( void );
+void ADC1_OTHER_Handler            ( void );
+void ADC1_RESRDY_Handler           ( void );
+void AC_Handler                    ( void );
+void DAC_OTHER_Handler             ( void );
+void DAC_EMPTY_0_Handler           ( void );
+void DAC_EMPTY_1_Handler           ( void );
+void DAC_RESRDY_0_Handler          ( void );
+void DAC_RESRDY_1_Handler          ( void );
+void I2S_Handler                   ( void );
+void PCC_Handler                   ( void );
+void AES_Handler                   ( void );
+void TRNG_Handler                  ( void );
+void ICM_Handler                   ( void );
+void PUKCC_Handler                 ( void );
+void QSPI_Handler                  ( void );
+void SDHC0_Handler                 ( void );
+void SDHC1_Handler                 ( void );
+#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */
+/* Defines for Deprecated Interrupt and Exceptions handler names */
+#define MemManage_Handler         MemoryManagement_Handler        /**< \deprecated  Backward compatibility*/
+#define DebugMon_Handler          DebugMonitor_Handler            /**< \deprecated  Backward compatibility*/
+#define NMI_Handler               NonMaskableInt_Handler          /**< \deprecated  Backward compatibility*/
+#define SVC_Handler               SVCall_Handler                  /**< \deprecated  Backward compatibility*/
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*
+ * \brief Configuration of the CORTEX-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV                 0x0001 /**< Cortex-M4 Core Revision                                                   */
+#define __DEBUG_LVL                    3 /**< Debug Level                                                               */
+#define __FPU_PRESENT                  1 /**< FPU present or not                                                        */
+#define __MPU_PRESENT                  1 /**< MPU present or not                                                        */
+#define __NVIC_PRIO_BITS               3 /**< Number of Bits used for Priority Levels                                   */
+#define __TRACE_LVL                    2 /**< Trace Level                                                               */
+#define __VTOR_PRESENT                 1 /**< Vector Table Offset Register present or not                               */
+#define __Vendor_SysTickConfig         0 /**< Set to 1 if different SysTick Config is used                              */
+#define __ARCH_ARM                     1
+#define __ARCH_ARM_CORTEX_M            1
+#define __DEVICE_IS_SAM                1
+
+/*
+ * \brief CMSIS includes
+ */
+//#include "core_cm4.h"
+#if defined USE_CMSIS_INIT
+//#include "system_samd51.h"
+#endif /* USE_CMSIS_INIT */
+
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+
+/** \defgroup SAMD51P19A_api Peripheral Software API
+ *  @{
+ */
+
+/* ************************************************************************** */
+/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51P19A                        */
+/* ************************************************************************** */
+//#include "ac.h"
+//#include "adc.h"
+//#include "aes.h"
+//#include "ccl.h"
+//#include "cmcc.h"
+//#include "dac.h"
+//#include "dmac.h"
+//#include "dsu.h"
+//#include "eic.h"
+//#include "evsys.h"
+//#include "freqm.h"
+#include "gclk.h"
+//#include "hmatrixb.h"
+//#include "i2s.h"
+//#include "icm.h"
+#include "mclk.h"
+//#include "nvmctrl.h"
+#include "osc32kctrl.h"
+#include "oscctrl.h"
+//#include "pac.h"
+//#include "pcc.h"
+//#include "pdec.h"
+//#include "pm.h"
+#include "port.h"
+//#include "pukcc.h"
+//#include "qspi.h"
+//#include "ramecc.h"
+//#include "rstc.h"
+//#include "rtc.h"
+//#include "sdhc.h"
+#include "sercom.h"
+//#include "supc.h"
+//#include "tc.h"
+//#include "tcc.h"
+//#include "trng.h"
+//#include "usb.h"
+//#include "wdt.h"
+/** @}  end of Peripheral Software API */
+
+/** \addtogroup SAMD51P19A_id Peripheral Ids Definitions
+ *  @{
+ */
+
+/* ************************************************************************** */
+/*  PERIPHERAL ID DEFINITIONS FOR SAMD51P19A                                  */
+/* ************************************************************************** */
+#define ID_PAC           (  0) /**< \brief Peripheral Access Controller (PAC) */
+#define ID_PM            (  1) /**< \brief Power Manager (PM) */
+#define ID_MCLK          (  2) /**< \brief Main Clock (MCLK) */
+#define ID_RSTC          (  3) /**< \brief Reset Controller (RSTC) */
+#define ID_OSCCTRL       (  4) /**< \brief Oscillators Control (OSCCTRL) */
+#define ID_OSC32KCTRL    (  5) /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */
+#define ID_SUPC          (  6) /**< \brief Supply Controller (SUPC) */
+#define ID_GCLK          (  7) /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT           (  8) /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC           (  9) /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC           ( 10) /**< \brief External Interrupt Controller (EIC) */
+#define ID_FREQM         ( 11) /**< \brief Frequency Meter (FREQM) */
+#define ID_SERCOM0       ( 12) /**< \brief Serial Communication Interface (SERCOM0) */
+#define ID_SERCOM1       ( 13) /**< \brief Serial Communication Interface (SERCOM1) */
+#define ID_TC0           ( 14) /**< \brief Basic Timer Counter (TC0) */
+#define ID_TC1           ( 15) /**< \brief Basic Timer Counter (TC1) */
+#define ID_USB           ( 32) /**< \brief Universal Serial Bus (USB) */
+#define ID_DSU           ( 33) /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL       ( 34) /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_CMCC          ( 35) /**< \brief Cortex M Cache Controller (CMCC) */
+#define ID_PORT          ( 36) /**< \brief Port Module (PORT) */
+#define ID_DMAC          ( 37) /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_HMATRIX       ( 38) /**< \brief HSB Matrix (HMATRIX) */
+#define ID_EVSYS         ( 39) /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM2       ( 41) /**< \brief Serial Communication Interface (SERCOM2) */
+#define ID_SERCOM3       ( 42) /**< \brief Serial Communication Interface (SERCOM3) */
+#define ID_TCC0          ( 43) /**< \brief Timer Counter Control (TCC0) */
+#define ID_TCC1          ( 44) /**< \brief Timer Counter Control (TCC1) */
+#define ID_TC2           ( 45) /**< \brief Basic Timer Counter (TC2) */
+#define ID_TC3           ( 46) /**< \brief Basic Timer Counter (TC3) */
+#define ID_RAMECC        ( 48) /**< \brief RAM ECC (RAMECC) */
+#define ID_TCC2          ( 67) /**< \brief Timer Counter Control (TCC2) */
+#define ID_TCC3          ( 68) /**< \brief Timer Counter Control (TCC3) */
+#define ID_TC4           ( 69) /**< \brief Basic Timer Counter (TC4) */
+#define ID_TC5           ( 70) /**< \brief Basic Timer Counter (TC5) */
+#define ID_PDEC          ( 71) /**< \brief Quadrature Decodeur (PDEC) */
+#define ID_AC            ( 72) /**< \brief Analog Comparators (AC) */
+#define ID_AES           ( 73) /**< \brief Advanced Encryption Standard (AES) */
+#define ID_TRNG          ( 74) /**< \brief True Random Generator (TRNG) */
+#define ID_ICM           ( 75) /**< \brief Integrity Check Monitor (ICM) */
+#define ID_PUKCC         ( 76) /**< \brief PUblic-Key Cryptography Controller (PUKCC) */
+#define ID_QSPI          ( 77) /**< \brief Quad SPI interface (QSPI) */
+#define ID_CCL           ( 78) /**< \brief Configurable Custom Logic (CCL) */
+#define ID_SERCOM4       ( 96) /**< \brief Serial Communication Interface (SERCOM4) */
+#define ID_SERCOM5       ( 97) /**< \brief Serial Communication Interface (SERCOM5) */
+#define ID_SERCOM6       ( 98) /**< \brief Serial Communication Interface (SERCOM6) */
+#define ID_SERCOM7       ( 99) /**< \brief Serial Communication Interface (SERCOM7) */
+#define ID_TCC4          (100) /**< \brief Timer Counter Control (TCC4) */
+#define ID_TC6           (101) /**< \brief Basic Timer Counter (TC6) */
+#define ID_TC7           (102) /**< \brief Basic Timer Counter (TC7) */
+#define ID_ADC0          (103) /**< \brief Analog Digital Converter (ADC0) */
+#define ID_ADC1          (104) /**< \brief Analog Digital Converter (ADC1) */
+#define ID_DAC           (105) /**< \brief Digital-to-Analog Converter (DAC) */
+#define ID_I2S           (106) /**< \brief Inter-IC Sound Interface (I2S) */
+#define ID_PCC           (107) /**< \brief Parallel Capture Controller (PCC) */
+
+#define ID_PERIPH_MAX    (107) /**< \brief Number of peripheral IDs */
+/** @}  end of Peripheral Ids Definitions */
+
+/** \addtogroup SAMD51P19A_base Peripheral Base Address Definitions
+ *  @{
+ */
+
+/* ************************************************************************** */
+/*   REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAMD51P19A                    */
+/* ************************************************************************** */
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+#define AC_REGS                          ((ac_registers_t*)0x42002000)                 /**< \brief AC Registers Address         */
+#define ADC0_REGS                        ((adc_registers_t*)0x43001c00)                /**< \brief ADC0 Registers Address       */
+#define ADC1_REGS                        ((adc_registers_t*)0x43002000)                /**< \brief ADC1 Registers Address       */
+#define AES_REGS                         ((aes_registers_t*)0x42002400)                /**< \brief AES Registers Address        */
+#define CCL_REGS                         ((ccl_registers_t*)0x42003800)                /**< \brief CCL Registers Address        */
+#define CMCC_REGS                        ((cmcc_registers_t*)0x41006000)               /**< \brief CMCC Registers Address       */
+#define DAC_REGS                         ((dac_registers_t*)0x43002400)                /**< \brief DAC Registers Address        */
+#define DMAC_REGS                        ((dmac_registers_t*)0x4100a000)               /**< \brief DMAC Registers Address       */
+#define DSU_REGS                         ((dsu_registers_t*)0x41002000)                /**< \brief DSU Registers Address        */
+#define EIC_REGS                         ((eic_registers_t*)0x40002800)                /**< \brief EIC Registers Address        */
+#define EVSYS_REGS                       ((evsys_registers_t*)0x4100e000)              /**< \brief EVSYS Registers Address      */
+#define FREQM_REGS                       ((freqm_registers_t*)0x40002c00)              /**< \brief FREQM Registers Address      */
+#define GCLK_REGS                        ((gclk_registers_t*)0x40001c00)               /**< \brief GCLK Registers Address       */
+#define HMATRIX_REGS                     ((hmatrixb_registers_t*)0x4100c000)           /**< \brief HMATRIX Registers Address    */
+#define ICM_REGS                         ((icm_registers_t*)0x42002c00)                /**< \brief ICM Registers Address        */
+#define I2S_REGS                         ((i2s_registers_t*)0x43002800)                /**< \brief I2S Registers Address        */
+#define MCLK_REGS                        ((mclk_registers_t*)0x40000800)               /**< \brief MCLK Registers Address       */
+#define NVMCTRL_REGS                     ((nvmctrl_registers_t*)0x41004000)            /**< \brief NVMCTRL Registers Address    */
+#define OSCCTRL_REGS                     ((oscctrl_registers_t*)0x40001000)            /**< \brief OSCCTRL Registers Address    */
+#define OSC32KCTRL_REGS                  ((osc32kctrl_registers_t*)0x40001400)         /**< \brief OSC32KCTRL Registers Address */
+#define PAC_REGS                         ((pac_registers_t*)0x40000000)                /**< \brief PAC Registers Address        */
+#define PCC_REGS                         ((pcc_registers_t*)0x43002c00)                /**< \brief PCC Registers Address        */
+#define PDEC_REGS                        ((pdec_registers_t*)0x42001c00)               /**< \brief PDEC Registers Address       */
+#define PM_REGS                          ((pm_registers_t*)0x40000400)                 /**< \brief PM Registers Address         */
+#define PORT_REGS                        ((port_registers_t*)0x41008000)               /**< \brief PORT Registers Address       */
+#define QSPI_REGS                        ((qspi_registers_t*)0x42003400)               /**< \brief QSPI Registers Address       */
+#define RAMECC_REGS                      ((ramecc_registers_t*)0x41020000)             /**< \brief RAMECC Registers Address     */
+#define RSTC_REGS                        ((rstc_registers_t*)0x40000c00)               /**< \brief RSTC Registers Address       */
+#define RTC_REGS                         ((rtc_registers_t*)0x40002400)                /**< \brief RTC Registers Address        */
+#define SDHC0_REGS                       ((sdhc_registers_t*)0x45000000)               /**< \brief SDHC0 Registers Address      */
+#define SDHC1_REGS                       ((sdhc_registers_t*)0x46000000)               /**< \brief SDHC1 Registers Address      */
+#define SERCOM0_REGS                     ((sercom_registers_t*)0x40003000)             /**< \brief SERCOM0 Registers Address    */
+#define SERCOM1_REGS                     ((sercom_registers_t*)0x40003400)             /**< \brief SERCOM1 Registers Address    */
+#define SERCOM2_REGS                     ((sercom_registers_t*)0x41012000)             /**< \brief SERCOM2 Registers Address    */
+#define SERCOM3_REGS                     ((sercom_registers_t*)0x41014000)             /**< \brief SERCOM3 Registers Address    */
+#define SERCOM4_REGS                     ((sercom_registers_t*)0x43000000)             /**< \brief SERCOM4 Registers Address    */
+#define SERCOM5_REGS                     ((sercom_registers_t*)0x43000400)             /**< \brief SERCOM5 Registers Address    */
+#define SERCOM6_REGS                     ((sercom_registers_t*)0x43000800)             /**< \brief SERCOM6 Registers Address    */
+#define SERCOM7_REGS                     ((sercom_registers_t*)0x43000c00)             /**< \brief SERCOM7 Registers Address    */
+#define SUPC_REGS                        ((supc_registers_t*)0x40001800)               /**< \brief SUPC Registers Address       */
+#define TC0_REGS                         ((tc_registers_t*)0x40003800)                 /**< \brief TC0 Registers Address        */
+#define TC1_REGS                         ((tc_registers_t*)0x40003c00)                 /**< \brief TC1 Registers Address        */
+#define TC2_REGS                         ((tc_registers_t*)0x4101a000)                 /**< \brief TC2 Registers Address        */
+#define TC3_REGS                         ((tc_registers_t*)0x4101c000)                 /**< \brief TC3 Registers Address        */
+#define TC4_REGS                         ((tc_registers_t*)0x42001400)                 /**< \brief TC4 Registers Address        */
+#define TC5_REGS                         ((tc_registers_t*)0x42001800)                 /**< \brief TC5 Registers Address        */
+#define TC6_REGS                         ((tc_registers_t*)0x43001400)                 /**< \brief TC6 Registers Address        */
+#define TC7_REGS                         ((tc_registers_t*)0x43001800)                 /**< \brief TC7 Registers Address        */
+#define TCC0_REGS                        ((tcc_registers_t*)0x41016000)                /**< \brief TCC0 Registers Address       */
+#define TCC1_REGS                        ((tcc_registers_t*)0x41018000)                /**< \brief TCC1 Registers Address       */
+#define TCC2_REGS                        ((tcc_registers_t*)0x42000c00)                /**< \brief TCC2 Registers Address       */
+#define TCC3_REGS                        ((tcc_registers_t*)0x42001000)                /**< \brief TCC3 Registers Address       */
+#define TCC4_REGS                        ((tcc_registers_t*)0x43001000)                /**< \brief TCC4 Registers Address       */
+#define TRNG_REGS                        ((trng_registers_t*)0x42002800)               /**< \brief TRNG Registers Address       */
+#define USB_REGS                         ((usb_registers_t*)0x41000000)                /**< \brief USB Registers Address        */
+#define WDT_REGS                         ((wdt_registers_t*)0x40002000)                /**< \brief WDT Registers Address        */
+#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+/** @}  end of Peripheral Base Address Definitions */
+
+/** \addtogroup SAMD51P19A_base Peripheral Base Address Definitions
+ *  @{
+ */
+
+/* ************************************************************************** */
+/*   BASE ADDRESS DEFINITIONS FOR SAMD51P19A                                  */
+/* ************************************************************************** */
+#define AC_BASE_ADDRESS                  _UL_(0x42002000)                              /**< \brief AC Base Address */
+#define ADC0_BASE_ADDRESS                _UL_(0x43001c00)                              /**< \brief ADC0 Base Address */
+#define ADC1_BASE_ADDRESS                _UL_(0x43002000)                              /**< \brief ADC1 Base Address */
+#define AES_BASE_ADDRESS                 _UL_(0x42002400)                              /**< \brief AES Base Address */
+#define CCL_BASE_ADDRESS                 _UL_(0x42003800)                              /**< \brief CCL Base Address */
+#define CMCC_BASE_ADDRESS                _UL_(0x41006000)                              /**< \brief CMCC Base Address */
+#define DAC_BASE_ADDRESS                 _UL_(0x43002400)                              /**< \brief DAC Base Address */
+#define DMAC_BASE_ADDRESS                _UL_(0x4100a000)                              /**< \brief DMAC Base Address */
+#define DSU_BASE_ADDRESS                 _UL_(0x41002000)                              /**< \brief DSU Base Address */
+#define EIC_BASE_ADDRESS                 _UL_(0x40002800)                              /**< \brief EIC Base Address */
+#define EVSYS_BASE_ADDRESS               _UL_(0x4100e000)                              /**< \brief EVSYS Base Address */
+#define FREQM_BASE_ADDRESS               _UL_(0x40002c00)                              /**< \brief FREQM Base Address */
+#define GCLK_BASE_ADDRESS                _UL_(0x40001c00)                              /**< \brief GCLK Base Address */
+#define HMATRIX_BASE_ADDRESS             _UL_(0x4100c000)                              /**< \brief HMATRIX Base Address */
+#define ICM_BASE_ADDRESS                 _UL_(0x42002c00)                              /**< \brief ICM Base Address */
+#define I2S_BASE_ADDRESS                 _UL_(0x43002800)                              /**< \brief I2S Base Address */
+#define MCLK_BASE_ADDRESS                _UL_(0x40000800)                              /**< \brief MCLK Base Address */
+#define NVMCTRL_BASE_ADDRESS             _UL_(0x41004000)                              /**< \brief NVMCTRL Base Address */
+#define OSCCTRL_BASE_ADDRESS             _UL_(0x40001000)                              /**< \brief OSCCTRL Base Address */
+#define OSC32KCTRL_BASE_ADDRESS          _UL_(0x40001400)                              /**< \brief OSC32KCTRL Base Address */
+#define PAC_BASE_ADDRESS                 _UL_(0x40000000)                              /**< \brief PAC Base Address */
+#define PCC_BASE_ADDRESS                 _UL_(0x43002c00)                              /**< \brief PCC Base Address */
+#define PDEC_BASE_ADDRESS                _UL_(0x42001c00)                              /**< \brief PDEC Base Address */
+#define PM_BASE_ADDRESS                  _UL_(0x40000400)                              /**< \brief PM Base Address */
+#define PORT_BASE_ADDRESS                _UL_(0x41008000)                              /**< \brief PORT Base Address */
+#define QSPI_BASE_ADDRESS                _UL_(0x42003400)                              /**< \brief QSPI Base Address */
+#define RAMECC_BASE_ADDRESS              _UL_(0x41020000)                              /**< \brief RAMECC Base Address */
+#define RSTC_BASE_ADDRESS                _UL_(0x40000c00)                              /**< \brief RSTC Base Address */
+#define RTC_BASE_ADDRESS                 _UL_(0x40002400)                              /**< \brief RTC Base Address */
+#define SDHC0_BASE_ADDRESS               _UL_(0x45000000)                              /**< \brief SDHC0 Base Address */
+#define SDHC1_BASE_ADDRESS               _UL_(0x46000000)                              /**< \brief SDHC1 Base Address */
+#define SERCOM0_BASE_ADDRESS             _UL_(0x40003000)                              /**< \brief SERCOM0 Base Address */
+#define SERCOM1_BASE_ADDRESS             _UL_(0x40003400)                              /**< \brief SERCOM1 Base Address */
+#define SERCOM2_BASE_ADDRESS             _UL_(0x41012000)                              /**< \brief SERCOM2 Base Address */
+#define SERCOM3_BASE_ADDRESS             _UL_(0x41014000)                              /**< \brief SERCOM3 Base Address */
+#define SERCOM4_BASE_ADDRESS             _UL_(0x43000000)                              /**< \brief SERCOM4 Base Address */
+#define SERCOM5_BASE_ADDRESS             _UL_(0x43000400)                              /**< \brief SERCOM5 Base Address */
+#define SERCOM6_BASE_ADDRESS             _UL_(0x43000800)                              /**< \brief SERCOM6 Base Address */
+#define SERCOM7_BASE_ADDRESS             _UL_(0x43000c00)                              /**< \brief SERCOM7 Base Address */
+#define SUPC_BASE_ADDRESS                _UL_(0x40001800)                              /**< \brief SUPC Base Address */
+#define TC0_BASE_ADDRESS                 _UL_(0x40003800)                              /**< \brief TC0 Base Address */
+#define TC1_BASE_ADDRESS                 _UL_(0x40003c00)                              /**< \brief TC1 Base Address */
+#define TC2_BASE_ADDRESS                 _UL_(0x4101a000)                              /**< \brief TC2 Base Address */
+#define TC3_BASE_ADDRESS                 _UL_(0x4101c000)                              /**< \brief TC3 Base Address */
+#define TC4_BASE_ADDRESS                 _UL_(0x42001400)                              /**< \brief TC4 Base Address */
+#define TC5_BASE_ADDRESS                 _UL_(0x42001800)                              /**< \brief TC5 Base Address */
+#define TC6_BASE_ADDRESS                 _UL_(0x43001400)                              /**< \brief TC6 Base Address */
+#define TC7_BASE_ADDRESS                 _UL_(0x43001800)                              /**< \brief TC7 Base Address */
+#define TCC0_BASE_ADDRESS                _UL_(0x41016000)                              /**< \brief TCC0 Base Address */
+#define TCC1_BASE_ADDRESS                _UL_(0x41018000)                              /**< \brief TCC1 Base Address */
+#define TCC2_BASE_ADDRESS                _UL_(0x42000c00)                              /**< \brief TCC2 Base Address */
+#define TCC3_BASE_ADDRESS                _UL_(0x42001000)                              /**< \brief TCC3 Base Address */
+#define TCC4_BASE_ADDRESS                _UL_(0x43001000)                              /**< \brief TCC4 Base Address */
+#define TRNG_BASE_ADDRESS                _UL_(0x42002800)                              /**< \brief TRNG Base Address */
+#define USB_BASE_ADDRESS                 _UL_(0x41000000)                              /**< \brief USB Base Address */
+#define WDT_BASE_ADDRESS                 _UL_(0x40002000)                              /**< \brief WDT Base Address */
+/** @}  end of Peripheral Base Address Definitions */
+
+/** \addtogroup SAMD51P19A_pio Peripheral Pio Definitions
+ *  @{
+ */
+
+/* ************************************************************************** */
+/*   PIO DEFINITIONS FOR SAMD51P19A                                           */
+/* ************************************************************************** */
+//#include "pio/samd51p19a.h"
+/** @}  end of Peripheral Pio Definitions */
+
+/* ************************************************************************** */
+/*   MEMORY MAPPING DEFINITIONS FOR SAMD51P19A                                */
+/* ************************************************************************** */
+
+#define FLASH_SIZE                     _UL_(0x00080000)    /*  512kB Memory segment type: flash */
+#define FLASH_PAGE_SIZE                _UL_(       512)
+#define FLASH_NB_OF_PAGES              _UL_(      1024)
+
+#define SW0_SIZE                       _UL_(0x00000010)    /*    0kB Memory segment type: fuses */
+#define TEMP_LOG_SIZE                  _UL_(0x00000200)    /*    0kB Memory segment type: fuses */
+#define TEMP_LOG_PAGE_SIZE             _UL_(       512)
+#define TEMP_LOG_NB_OF_PAGES           _UL_(         1)
+
+#define USER_PAGE_SIZE                 _UL_(0x00000200)    /*    0kB Memory segment type: user_page */
+#define USER_PAGE_PAGE_SIZE            _UL_(       512)
+#define USER_PAGE_NB_OF_PAGES          _UL_(         1)
+
+#define CMCC_SIZE                      _UL_(0x01000000)    /* 16384kB Memory segment type: io */
+#define CMCC_DATARAM_SIZE              _UL_(0x00001000)    /*    4kB Memory segment type: io */
+#define CMCC_TAGRAM_SIZE               _UL_(0x00000400)    /*    1kB Memory segment type: io */
+#define CMCC_VALIDRAM_SIZE             _UL_(0x00000040)    /*    0kB Memory segment type: io */
+#define QSPI_SIZE                      _UL_(0x01000000)    /* 16384kB Memory segment type: other */
+#define HSRAM_SIZE                     _UL_(0x00030000)    /*  192kB Memory segment type: ram */
+#define HSRAM_ETB_SIZE                 _UL_(0x00008000)    /*   32kB Memory segment type: ram */
+#define HSRAM_RET1_SIZE                _UL_(0x00008000)    /*   32kB Memory segment type: ram */
+#define HPB0_SIZE                      _UL_(0x00004400)    /*   17kB Memory segment type: io */
+#define HPB1_SIZE                      _UL_(0x00022000)    /*  136kB Memory segment type: io */
+#define HPB2_SIZE                      _UL_(0x00003c00)    /*   15kB Memory segment type: io */
+#define HPB3_SIZE                      _UL_(0x00003000)    /*   12kB Memory segment type: io */
+#define SEEPROM_SIZE                   _UL_(0x00020000)    /*  128kB Memory segment type: io */
+#define SDHC0_SIZE                     _UL_(0x00000c00)    /*    3kB Memory segment type: io */
+#define SDHC1_SIZE                     _UL_(0x00000c00)    /*    3kB Memory segment type: io */
+#define BKUPRAM_SIZE                   _UL_(0x00002000)    /*    8kB Memory segment type: ram */
+#define PPB_SIZE                       _UL_(0x00100000)    /* 1024kB Memory segment type: io */
+#define SCS_SIZE                       _UL_(0x00001000)    /*    4kB Memory segment type: io */
+
+#define FLASH_ADDR                     _UL_(0x00000000)    /**< FLASH base address (type: flash)*/
+#define SW0_ADDR                       _UL_(0x00800080)    /**< SW0 base address (type: fuses)*/
+#define TEMP_LOG_ADDR                  _UL_(0x00800100)    /**< TEMP_LOG base address (type: fuses)*/
+#define USER_PAGE_ADDR                 _UL_(0x00804000)    /**< USER_PAGE base address (type: user_page)*/
+#define CMCC_ADDR                      _UL_(0x03000000)    /**< CMCC base address (type: io)*/
+#define CMCC_DATARAM_ADDR              _UL_(0x03000000)    /**< CMCC_DATARAM base address (type: io)*/
+#define CMCC_TAGRAM_ADDR               _UL_(0x03001000)    /**< CMCC_TAGRAM base address (type: io)*/
+#define CMCC_VALIDRAM_ADDR             _UL_(0x03002000)    /**< CMCC_VALIDRAM base address (type: io)*/
+#define QSPI_ADDR                      _UL_(0x04000000)    /**< QSPI base address (type: other)*/
+#define HSRAM_ADDR                     _UL_(0x20000000)    /**< HSRAM base address (type: ram)*/
+#define HSRAM_ETB_ADDR                 _UL_(0x20000000)    /**< HSRAM_ETB base address (type: ram)*/
+#define HSRAM_RET1_ADDR                _UL_(0x20000000)    /**< HSRAM_RET1 base address (type: ram)*/
+#define HPB0_ADDR                      _UL_(0x40000000)    /**< HPB0 base address (type: io)*/
+#define HPB1_ADDR                      _UL_(0x41000000)    /**< HPB1 base address (type: io)*/
+#define HPB2_ADDR                      _UL_(0x42000000)    /**< HPB2 base address (type: io)*/
+#define HPB3_ADDR                      _UL_(0x43000000)    /**< HPB3 base address (type: io)*/
+#define SEEPROM_ADDR                   _UL_(0x44000000)    /**< SEEPROM base address (type: io)*/
+#define SDHC0_ADDR                     _UL_(0x45000000)    /**< SDHC0 base address (type: io)*/
+#define SDHC1_ADDR                     _UL_(0x46000000)    /**< SDHC1 base address (type: io)*/
+#define BKUPRAM_ADDR                   _UL_(0x47000000)    /**< BKUPRAM base address (type: ram)*/
+#define PPB_ADDR                       _UL_(0xe0000000)    /**< PPB base address (type: io)*/
+#define SCS_ADDR                       _UL_(0xe000e000)    /**< SCS base address (type: io)*/
+
+/* ************************************************************************** */
+/**  DEVICE SIGNATURES FOR SAMD51P19A                                         */
+/* ************************************************************************** */
+#define CHIP_DSU_DID                   _UL_(0X60060301)
+
+/* ************************************************************************** */
+/**  ELECTRICAL DEFINITIONS FOR SAMD51P19A                                    */
+/* ************************************************************************** */
+
+/* ************************************************************************** */
+/** Event Generator IDs for SAMD51P19A */
+/* ************************************************************************** */
+#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0                  1 /**< ID for OSCCTRL event generator XOSC_FAIL_0 */
+#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1                  2 /**< ID for OSCCTRL event generator XOSC_FAIL_1 */
+#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL              3 /**< ID for OSC32KCTRL event generator XOSC32K_FAIL */
+#define EVENT_ID_GEN_RTC_PER_0                            4 /**< ID for RTC event generator PER_0 */
+#define EVENT_ID_GEN_RTC_PER_1                            5 /**< ID for RTC event generator PER_1 */
+#define EVENT_ID_GEN_RTC_PER_2                            6 /**< ID for RTC event generator PER_2 */
+#define EVENT_ID_GEN_RTC_PER_3                            7 /**< ID for RTC event generator PER_3 */
+#define EVENT_ID_GEN_RTC_PER_4                            8 /**< ID for RTC event generator PER_4 */
+#define EVENT_ID_GEN_RTC_PER_5                            9 /**< ID for RTC event generator PER_5 */
+#define EVENT_ID_GEN_RTC_PER_6                           10 /**< ID for RTC event generator PER_6 */
+#define EVENT_ID_GEN_RTC_PER_7                           11 /**< ID for RTC event generator PER_7 */
+#define EVENT_ID_GEN_RTC_CMP_0                           12 /**< ID for RTC event generator CMP_0 */
+#define EVENT_ID_GEN_RTC_CMP_1                           13 /**< ID for RTC event generator CMP_1 */
+#define EVENT_ID_GEN_RTC_CMP_2                           14 /**< ID for RTC event generator CMP_2 */
+#define EVENT_ID_GEN_RTC_CMP_3                           15 /**< ID for RTC event generator CMP_3 */
+#define EVENT_ID_GEN_RTC_TAMPER                          16 /**< ID for RTC event generator TAMPER */
+#define EVENT_ID_GEN_RTC_OVF                             17 /**< ID for RTC event generator OVF */
+#define EVENT_ID_GEN_EIC_EXTINT_0                        18 /**< ID for EIC event generator EXTINT_0 */
+#define EVENT_ID_GEN_EIC_EXTINT_1                        19 /**< ID for EIC event generator EXTINT_1 */
+#define EVENT_ID_GEN_EIC_EXTINT_2                        20 /**< ID for EIC event generator EXTINT_2 */
+#define EVENT_ID_GEN_EIC_EXTINT_3                        21 /**< ID for EIC event generator EXTINT_3 */
+#define EVENT_ID_GEN_EIC_EXTINT_4                        22 /**< ID for EIC event generator EXTINT_4 */
+#define EVENT_ID_GEN_EIC_EXTINT_5                        23 /**< ID for EIC event generator EXTINT_5 */
+#define EVENT_ID_GEN_EIC_EXTINT_6                        24 /**< ID for EIC event generator EXTINT_6 */
+#define EVENT_ID_GEN_EIC_EXTINT_7                        25 /**< ID for EIC event generator EXTINT_7 */
+#define EVENT_ID_GEN_EIC_EXTINT_8                        26 /**< ID for EIC event generator EXTINT_8 */
+#define EVENT_ID_GEN_EIC_EXTINT_9                        27 /**< ID for EIC event generator EXTINT_9 */
+#define EVENT_ID_GEN_EIC_EXTINT_10                       28 /**< ID for EIC event generator EXTINT_10 */
+#define EVENT_ID_GEN_EIC_EXTINT_11                       29 /**< ID for EIC event generator EXTINT_11 */
+#define EVENT_ID_GEN_EIC_EXTINT_12                       30 /**< ID for EIC event generator EXTINT_12 */
+#define EVENT_ID_GEN_EIC_EXTINT_13                       31 /**< ID for EIC event generator EXTINT_13 */
+#define EVENT_ID_GEN_EIC_EXTINT_14                       32 /**< ID for EIC event generator EXTINT_14 */
+#define EVENT_ID_GEN_EIC_EXTINT_15                       33 /**< ID for EIC event generator EXTINT_15 */
+#define EVENT_ID_GEN_DMAC_CH_0                           34 /**< ID for DMAC event generator CH_0 */
+#define EVENT_ID_GEN_DMAC_CH_1                           35 /**< ID for DMAC event generator CH_1 */
+#define EVENT_ID_GEN_DMAC_CH_2                           36 /**< ID for DMAC event generator CH_2 */
+#define EVENT_ID_GEN_DMAC_CH_3                           37 /**< ID for DMAC event generator CH_3 */
+#define EVENT_ID_GEN_PAC_ACCERR                          38 /**< ID for PAC event generator ACCERR */
+#define EVENT_ID_GEN_TCC0_OVF                            41 /**< ID for TCC0 event generator OVF */
+#define EVENT_ID_GEN_TCC0_TRG                            42 /**< ID for TCC0 event generator TRG */
+#define EVENT_ID_GEN_TCC0_CNT                            43 /**< ID for TCC0 event generator CNT */
+#define EVENT_ID_GEN_TCC0_MC_0                           44 /**< ID for TCC0 event generator MC_0 */
+#define EVENT_ID_GEN_TCC0_MC_1                           45 /**< ID for TCC0 event generator MC_1 */
+#define EVENT_ID_GEN_TCC0_MC_2                           46 /**< ID for TCC0 event generator MC_2 */
+#define EVENT_ID_GEN_TCC0_MC_3                           47 /**< ID for TCC0 event generator MC_3 */
+#define EVENT_ID_GEN_TCC0_MC_4                           48 /**< ID for TCC0 event generator MC_4 */
+#define EVENT_ID_GEN_TCC0_MC_5                           49 /**< ID for TCC0 event generator MC_5 */
+#define EVENT_ID_GEN_TCC1_OVF                            50 /**< ID for TCC1 event generator OVF */
+#define EVENT_ID_GEN_TCC1_TRG                            51 /**< ID for TCC1 event generator TRG */
+#define EVENT_ID_GEN_TCC1_CNT                            52 /**< ID for TCC1 event generator CNT */
+#define EVENT_ID_GEN_TCC1_MC_0                           53 /**< ID for TCC1 event generator MC_0 */
+#define EVENT_ID_GEN_TCC1_MC_1                           54 /**< ID for TCC1 event generator MC_1 */
+#define EVENT_ID_GEN_TCC1_MC_2                           55 /**< ID for TCC1 event generator MC_2 */
+#define EVENT_ID_GEN_TCC1_MC_3                           56 /**< ID for TCC1 event generator MC_3 */
+#define EVENT_ID_GEN_TCC2_OVF                            57 /**< ID for TCC2 event generator OVF */
+#define EVENT_ID_GEN_TCC2_TRG                            58 /**< ID for TCC2 event generator TRG */
+#define EVENT_ID_GEN_TCC2_CNT                            59 /**< ID for TCC2 event generator CNT */
+#define EVENT_ID_GEN_TCC2_MC_0                           60 /**< ID for TCC2 event generator MC_0 */
+#define EVENT_ID_GEN_TCC2_MC_1                           61 /**< ID for TCC2 event generator MC_1 */
+#define EVENT_ID_GEN_TCC2_MC_2                           62 /**< ID for TCC2 event generator MC_2 */
+#define EVENT_ID_GEN_TCC3_OVF                            63 /**< ID for TCC3 event generator OVF */
+#define EVENT_ID_GEN_TCC3_TRG                            64 /**< ID for TCC3 event generator TRG */
+#define EVENT_ID_GEN_TCC3_CNT                            65 /**< ID for TCC3 event generator CNT */
+#define EVENT_ID_GEN_TCC3_MC_0                           66 /**< ID for TCC3 event generator MC_0 */
+#define EVENT_ID_GEN_TCC3_MC_1                           67 /**< ID for TCC3 event generator MC_1 */
+#define EVENT_ID_GEN_TCC4_OVF                            68 /**< ID for TCC4 event generator OVF */
+#define EVENT_ID_GEN_TCC4_TRG                            69 /**< ID for TCC4 event generator TRG */
+#define EVENT_ID_GEN_TCC4_CNT                            70 /**< ID for TCC4 event generator CNT */
+#define EVENT_ID_GEN_TCC4_MC_0                           71 /**< ID for TCC4 event generator MC_0 */
+#define EVENT_ID_GEN_TCC4_MC_1                           72 /**< ID for TCC4 event generator MC_1 */
+#define EVENT_ID_GEN_TC0_OVF                             73 /**< ID for TC0 event generator OVF */
+#define EVENT_ID_GEN_TC0_MC_0                            74 /**< ID for TC0 event generator MC_0 */
+#define EVENT_ID_GEN_TC0_MC_1                            75 /**< ID for TC0 event generator MC_1 */
+#define EVENT_ID_GEN_TC1_OVF                             76 /**< ID for TC1 event generator OVF */
+#define EVENT_ID_GEN_TC1_MC_0                            77 /**< ID for TC1 event generator MC_0 */
+#define EVENT_ID_GEN_TC1_MC_1                            78 /**< ID for TC1 event generator MC_1 */
+#define EVENT_ID_GEN_TC2_OVF                             79 /**< ID for TC2 event generator OVF */
+#define EVENT_ID_GEN_TC2_MC_0                            80 /**< ID for TC2 event generator MC_0 */
+#define EVENT_ID_GEN_TC2_MC_1                            81 /**< ID for TC2 event generator MC_1 */
+#define EVENT_ID_GEN_TC3_OVF                             82 /**< ID for TC3 event generator OVF */
+#define EVENT_ID_GEN_TC3_MC_0                            83 /**< ID for TC3 event generator MC_0 */
+#define EVENT_ID_GEN_TC3_MC_1                            84 /**< ID for TC3 event generator MC_1 */
+#define EVENT_ID_GEN_TC4_OVF                             85 /**< ID for TC4 event generator OVF */
+#define EVENT_ID_GEN_TC4_MC_0                            86 /**< ID for TC4 event generator MC_0 */
+#define EVENT_ID_GEN_TC4_MC_1                            87 /**< ID for TC4 event generator MC_1 */
+#define EVENT_ID_GEN_TC5_OVF                             88 /**< ID for TC5 event generator OVF */
+#define EVENT_ID_GEN_TC5_MC_0                            89 /**< ID for TC5 event generator MC_0 */
+#define EVENT_ID_GEN_TC5_MC_1                            90 /**< ID for TC5 event generator MC_1 */
+#define EVENT_ID_GEN_TC6_OVF                             91 /**< ID for TC6 event generator OVF */
+#define EVENT_ID_GEN_TC6_MC_0                            92 /**< ID for TC6 event generator MC_0 */
+#define EVENT_ID_GEN_TC6_MC_1                            93 /**< ID for TC6 event generator MC_1 */
+#define EVENT_ID_GEN_TC7_OVF                             94 /**< ID for TC7 event generator OVF */
+#define EVENT_ID_GEN_TC7_MC_0                            95 /**< ID for TC7 event generator MC_0 */
+#define EVENT_ID_GEN_TC7_MC_1                            96 /**< ID for TC7 event generator MC_1 */
+#define EVENT_ID_GEN_PDEC_OVF                            97 /**< ID for PDEC event generator OVF */
+#define EVENT_ID_GEN_PDEC_ERR                            98 /**< ID for PDEC event generator ERR */
+#define EVENT_ID_GEN_PDEC_DIR                            99 /**< ID for PDEC event generator DIR */
+#define EVENT_ID_GEN_PDEC_VLC                           100 /**< ID for PDEC event generator VLC */
+#define EVENT_ID_GEN_PDEC_MC_0                          101 /**< ID for PDEC event generator MC_0 */
+#define EVENT_ID_GEN_PDEC_MC_1                          102 /**< ID for PDEC event generator MC_1 */
+#define EVENT_ID_GEN_ADC0_RESRDY                        103 /**< ID for ADC0 event generator RESRDY */
+#define EVENT_ID_GEN_ADC0_WINMON                        104 /**< ID for ADC0 event generator WINMON */
+#define EVENT_ID_GEN_ADC1_RESRDY                        105 /**< ID for ADC1 event generator RESRDY */
+#define EVENT_ID_GEN_ADC1_WINMON                        106 /**< ID for ADC1 event generator WINMON */
+#define EVENT_ID_GEN_AC_COMP_0                          107 /**< ID for AC event generator COMP_0 */
+#define EVENT_ID_GEN_AC_COMP_1                          108 /**< ID for AC event generator COMP_1 */
+#define EVENT_ID_GEN_AC_WIN_0                           109 /**< ID for AC event generator WIN_0 */
+#define EVENT_ID_GEN_DAC_EMPTY_0                        110 /**< ID for DAC event generator EMPTY_0 */
+#define EVENT_ID_GEN_DAC_EMPTY_1                        111 /**< ID for DAC event generator EMPTY_1 */
+#define EVENT_ID_GEN_DAC_RESRDY_0                       112 /**< ID for DAC event generator RESRDY_0 */
+#define EVENT_ID_GEN_DAC_RESRDY_1                       113 /**< ID for DAC event generator RESRDY_1 */
+#define EVENT_ID_GEN_TRNG_READY                         115 /**< ID for TRNG event generator READY */
+#define EVENT_ID_GEN_CCL_LUTOUT_0                       116 /**< ID for CCL event generator LUTOUT_0 */
+#define EVENT_ID_GEN_CCL_LUTOUT_1                       117 /**< ID for CCL event generator LUTOUT_1 */
+#define EVENT_ID_GEN_CCL_LUTOUT_2                       118 /**< ID for CCL event generator LUTOUT_2 */
+#define EVENT_ID_GEN_CCL_LUTOUT_3                       119 /**< ID for CCL event generator LUTOUT_3 */
+
+/* ************************************************************************** */
+/** Event User IDs for SAMD51P19A */
+/* ************************************************************************** */
+#define EVENT_ID_USER_RTC_TAMPER                          0 /**< ID for RTC event user TAMPER */
+#define EVENT_ID_USER_PORT_EV_0                           1 /**< ID for PORT event user EV_0 */
+#define EVENT_ID_USER_PORT_EV_1                           2 /**< ID for PORT event user EV_1 */
+#define EVENT_ID_USER_PORT_EV_2                           3 /**< ID for PORT event user EV_2 */
+#define EVENT_ID_USER_PORT_EV_3                           4 /**< ID for PORT event user EV_3 */
+#define EVENT_ID_USER_DMAC_CH_0                           5 /**< ID for DMAC event user CH_0 */
+#define EVENT_ID_USER_DMAC_CH_1                           6 /**< ID for DMAC event user CH_1 */
+#define EVENT_ID_USER_DMAC_CH_2                           7 /**< ID for DMAC event user CH_2 */
+#define EVENT_ID_USER_DMAC_CH_3                           8 /**< ID for DMAC event user CH_3 */
+#define EVENT_ID_USER_DMAC_CH_4                           9 /**< ID for DMAC event user CH_4 */
+#define EVENT_ID_USER_DMAC_CH_5                          10 /**< ID for DMAC event user CH_5 */
+#define EVENT_ID_USER_DMAC_CH_6                          11 /**< ID for DMAC event user CH_6 */
+#define EVENT_ID_USER_DMAC_CH_7                          12 /**< ID for DMAC event user CH_7 */
+#define EVENT_ID_USER_CM4_TRACE_START                    14 /**< ID for CM4 event user TRACE_START */
+#define EVENT_ID_USER_CM4_TRACE_STOP                     15 /**< ID for CM4 event user TRACE_STOP */
+#define EVENT_ID_USER_CM4_TRACE_TRIG                     16 /**< ID for CM4 event user TRACE_TRIG */
+#define EVENT_ID_USER_TCC0_EV_0                          17 /**< ID for TCC0 event user EV_0 */
+#define EVENT_ID_USER_TCC0_EV_1                          18 /**< ID for TCC0 event user EV_1 */
+#define EVENT_ID_USER_TCC0_MC_0                          19 /**< ID for TCC0 event user MC_0 */
+#define EVENT_ID_USER_TCC0_MC_1                          20 /**< ID for TCC0 event user MC_1 */
+#define EVENT_ID_USER_TCC0_MC_2                          21 /**< ID for TCC0 event user MC_2 */
+#define EVENT_ID_USER_TCC0_MC_3                          22 /**< ID for TCC0 event user MC_3 */
+#define EVENT_ID_USER_TCC0_MC_4                          23 /**< ID for TCC0 event user MC_4 */
+#define EVENT_ID_USER_TCC0_MC_5                          24 /**< ID for TCC0 event user MC_5 */
+#define EVENT_ID_USER_TCC1_EV_0                          25 /**< ID for TCC1 event user EV_0 */
+#define EVENT_ID_USER_TCC1_EV_1                          26 /**< ID for TCC1 event user EV_1 */
+#define EVENT_ID_USER_TCC1_MC_0                          27 /**< ID for TCC1 event user MC_0 */
+#define EVENT_ID_USER_TCC1_MC_1                          28 /**< ID for TCC1 event user MC_1 */
+#define EVENT_ID_USER_TCC1_MC_2                          29 /**< ID for TCC1 event user MC_2 */
+#define EVENT_ID_USER_TCC1_MC_3                          30 /**< ID for TCC1 event user MC_3 */
+#define EVENT_ID_USER_TCC2_EV_0                          31 /**< ID for TCC2 event user EV_0 */
+#define EVENT_ID_USER_TCC2_EV_1                          32 /**< ID for TCC2 event user EV_1 */
+#define EVENT_ID_USER_TCC2_MC_0                          33 /**< ID for TCC2 event user MC_0 */
+#define EVENT_ID_USER_TCC2_MC_1                          34 /**< ID for TCC2 event user MC_1 */
+#define EVENT_ID_USER_TCC2_MC_2                          35 /**< ID for TCC2 event user MC_2 */
+#define EVENT_ID_USER_TCC3_EV_0                          36 /**< ID for TCC3 event user EV_0 */
+#define EVENT_ID_USER_TCC3_EV_1                          37 /**< ID for TCC3 event user EV_1 */
+#define EVENT_ID_USER_TCC3_MC_0                          38 /**< ID for TCC3 event user MC_0 */
+#define EVENT_ID_USER_TCC3_MC_1                          39 /**< ID for TCC3 event user MC_1 */
+#define EVENT_ID_USER_TCC4_EV_0                          40 /**< ID for TCC4 event user EV_0 */
+#define EVENT_ID_USER_TCC4_EV_1                          41 /**< ID for TCC4 event user EV_1 */
+#define EVENT_ID_USER_TCC4_MC_0                          42 /**< ID for TCC4 event user MC_0 */
+#define EVENT_ID_USER_TCC4_MC_1                          43 /**< ID for TCC4 event user MC_1 */
+#define EVENT_ID_USER_TC0_EVU                            44 /**< ID for TC0 event user EVU */
+#define EVENT_ID_USER_TC1_EVU                            45 /**< ID for TC1 event user EVU */
+#define EVENT_ID_USER_TC2_EVU                            46 /**< ID for TC2 event user EVU */
+#define EVENT_ID_USER_TC3_EVU                            47 /**< ID for TC3 event user EVU */
+#define EVENT_ID_USER_TC4_EVU                            48 /**< ID for TC4 event user EVU */
+#define EVENT_ID_USER_TC5_EVU                            49 /**< ID for TC5 event user EVU */
+#define EVENT_ID_USER_TC6_EVU                            50 /**< ID for TC6 event user EVU */
+#define EVENT_ID_USER_TC7_EVU                            51 /**< ID for TC7 event user EVU */
+#define EVENT_ID_USER_PDEC_EVU_0                         52 /**< ID for PDEC event user EVU_0 */
+#define EVENT_ID_USER_PDEC_EVU_1                         53 /**< ID for PDEC event user EVU_1 */
+#define EVENT_ID_USER_PDEC_EVU_2                         54 /**< ID for PDEC event user EVU_2 */
+#define EVENT_ID_USER_ADC0_START                         55 /**< ID for ADC0 event user START */
+#define EVENT_ID_USER_ADC0_SYNC                          56 /**< ID for ADC0 event user SYNC */
+#define EVENT_ID_USER_ADC1_START                         57 /**< ID for ADC1 event user START */
+#define EVENT_ID_USER_ADC1_SYNC                          58 /**< ID for ADC1 event user SYNC */
+#define EVENT_ID_USER_AC_SOC_0                           59 /**< ID for AC event user SOC_0 */
+#define EVENT_ID_USER_AC_SOC_1                           60 /**< ID for AC event user SOC_1 */
+#define EVENT_ID_USER_DAC_START_0                        61 /**< ID for DAC event user START_0 */
+#define EVENT_ID_USER_DAC_START_1                        62 /**< ID for DAC event user START_1 */
+#define EVENT_ID_USER_CCL_LUTIN_0                        63 /**< ID for CCL event user LUTIN_0 */
+#define EVENT_ID_USER_CCL_LUTIN_1                        64 /**< ID for CCL event user LUTIN_1 */
+#define EVENT_ID_USER_CCL_LUTIN_2                        65 /**< ID for CCL event user LUTIN_2 */
+#define EVENT_ID_USER_CCL_LUTIN_3                        66 /**< ID for CCL event user LUTIN_3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @}  end of SAMD51P19A definitions */
+
+
+#endif /* _SAMD51P19A_H_ */
+
Index: /asp_wio_terminal/trunk/target/samd51_gcc/lib/gclk.h
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/lib/gclk.h	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/lib/gclk.h	(revision 460)
@@ -0,0 +1,188 @@
+/**
+ * \brief Component description for GCLK
+ *
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * Subject to your compliance with these terms, you may use Microchip software and any derivatives
+ * exclusively with Microchip products. It is your responsibility to comply with third party license
+ * terms applicable to your use of third party software (including open source software) that may
+ * accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
+ * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
+ * FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
+ * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
+ * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ */
+
+/* file generated from device description version 2020-03-12T17:26:00Z */
+#ifndef _SAMD51_GCLK_COMPONENT_H_
+#define _SAMD51_GCLK_COMPONENT_H_
+
+/* ************************************************************************** */
+/*   SOFTWARE API DEFINITION FOR GCLK                                         */
+/* ************************************************************************** */
+
+/* -------- GCLK_CTRLA : (GCLK Offset: 0x00) (R/W 8) Control -------- */
+#define GCLK_CTRLA_RESETVALUE                 _U_(0x00)                                            /**<  (GCLK_CTRLA) Control  Reset Value */
+
+#define GCLK_CTRLA_SWRST_Pos                  _U_(0)                                               /**< (GCLK_CTRLA) Software Reset Position */
+#define GCLK_CTRLA_SWRST_Msk                  (_U_(0x1) << GCLK_CTRLA_SWRST_Pos)                   /**< (GCLK_CTRLA) Software Reset Mask */
+#define GCLK_CTRLA_SWRST(value)               (GCLK_CTRLA_SWRST_Msk & ((value) << GCLK_CTRLA_SWRST_Pos))
+#define GCLK_CTRLA_Msk                        _U_(0x01)                                            /**< (GCLK_CTRLA) Register Mask  */
+
+
+/* -------- GCLK_SYNCBUSY : (GCLK Offset: 0x04) ( R/ 32) Synchronization Busy -------- */
+#define GCLK_SYNCBUSY_RESETVALUE              _U_(0x00)                                            /**<  (GCLK_SYNCBUSY) Synchronization Busy  Reset Value */
+
+#define GCLK_SYNCBUSY_SWRST_Pos               _U_(0)                                               /**< (GCLK_SYNCBUSY) Software Reset Synchroniation Busy bit Position */
+#define GCLK_SYNCBUSY_SWRST_Msk               (_U_(0x1) << GCLK_SYNCBUSY_SWRST_Pos)                /**< (GCLK_SYNCBUSY) Software Reset Synchroniation Busy bit Mask */
+#define GCLK_SYNCBUSY_SWRST(value)            (GCLK_SYNCBUSY_SWRST_Msk & ((value) << GCLK_SYNCBUSY_SWRST_Pos))
+#define GCLK_SYNCBUSY_GENCTRL_Pos             _U_(2)                                               /**< (GCLK_SYNCBUSY) Generic Clock Generator Control n Synchronization Busy bits Position */
+#define GCLK_SYNCBUSY_GENCTRL_Msk             (_U_(0xFFF) << GCLK_SYNCBUSY_GENCTRL_Pos)            /**< (GCLK_SYNCBUSY) Generic Clock Generator Control n Synchronization Busy bits Mask */
+#define GCLK_SYNCBUSY_GENCTRL(value)          (GCLK_SYNCBUSY_GENCTRL_Msk & ((value) << GCLK_SYNCBUSY_GENCTRL_Pos))
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK0_Val     _U_(0x1)                                             /**< (GCLK_SYNCBUSY) Generic clock generator 0  */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK1_Val     _U_(0x2)                                             /**< (GCLK_SYNCBUSY) Generic clock generator 1  */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK2_Val     _U_(0x4)                                             /**< (GCLK_SYNCBUSY) Generic clock generator 2  */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK3_Val     _U_(0x8)                                             /**< (GCLK_SYNCBUSY) Generic clock generator 3  */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK4_Val     _U_(0x10)                                            /**< (GCLK_SYNCBUSY) Generic clock generator 4  */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK5_Val     _U_(0x20)                                            /**< (GCLK_SYNCBUSY) Generic clock generator 5  */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK6_Val     _U_(0x40)                                            /**< (GCLK_SYNCBUSY) Generic clock generator 6  */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK7_Val     _U_(0x80)                                            /**< (GCLK_SYNCBUSY) Generic clock generator 7  */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK8_Val     _U_(0x100)                                           /**< (GCLK_SYNCBUSY) Generic clock generator 8  */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK9_Val     _U_(0x200)                                           /**< (GCLK_SYNCBUSY) Generic clock generator 9  */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK10_Val    _U_(0x400)                                           /**< (GCLK_SYNCBUSY) Generic clock generator 10  */
+#define   GCLK_SYNCBUSY_GENCTRL_GCLK11_Val    _U_(0x800)                                           /**< (GCLK_SYNCBUSY) Generic clock generator 11  */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK0           (GCLK_SYNCBUSY_GENCTRL_GCLK0_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 0 Position  */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK1           (GCLK_SYNCBUSY_GENCTRL_GCLK1_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 1 Position  */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK2           (GCLK_SYNCBUSY_GENCTRL_GCLK2_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 2 Position  */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK3           (GCLK_SYNCBUSY_GENCTRL_GCLK3_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 3 Position  */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK4           (GCLK_SYNCBUSY_GENCTRL_GCLK4_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 4 Position  */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK5           (GCLK_SYNCBUSY_GENCTRL_GCLK5_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 5 Position  */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK6           (GCLK_SYNCBUSY_GENCTRL_GCLK6_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 6 Position  */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK7           (GCLK_SYNCBUSY_GENCTRL_GCLK7_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 7 Position  */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK8           (GCLK_SYNCBUSY_GENCTRL_GCLK8_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 8 Position  */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK9           (GCLK_SYNCBUSY_GENCTRL_GCLK9_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 9 Position  */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK10          (GCLK_SYNCBUSY_GENCTRL_GCLK10_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 10 Position  */
+#define GCLK_SYNCBUSY_GENCTRL_GCLK11          (GCLK_SYNCBUSY_GENCTRL_GCLK11_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 11 Position  */
+#define GCLK_SYNCBUSY_Msk                     _U_(0x00003FFD)                                      /**< (GCLK_SYNCBUSY) Register Mask  */
+
+
+/* -------- GCLK_GENCTRL : (GCLK Offset: 0x20) (R/W 32) Generic Clock Generator Control -------- */
+#define GCLK_GENCTRL_RESETVALUE               _U_(0x00)                                            /**<  (GCLK_GENCTRL) Generic Clock Generator Control  Reset Value */
+
+#define GCLK_GENCTRL_SRC_Pos                  _U_(0)                                               /**< (GCLK_GENCTRL) Source Select Position */
+#define GCLK_GENCTRL_SRC_Msk                  (_U_(0xF) << GCLK_GENCTRL_SRC_Pos)                   /**< (GCLK_GENCTRL) Source Select Mask */
+#define GCLK_GENCTRL_SRC(value)               (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
+#define   GCLK_GENCTRL_SRC_XOSC0_Val          _U_(0x0)                                             /**< (GCLK_GENCTRL) XOSC0 oscillator output  */
+#define   GCLK_GENCTRL_SRC_XOSC1_Val          _U_(0x1)                                             /**< (GCLK_GENCTRL) XOSC1 oscillator output  */
+#define   GCLK_GENCTRL_SRC_GCLKIN_Val         _U_(0x2)                                             /**< (GCLK_GENCTRL) Generator input pad  */
+#define   GCLK_GENCTRL_SRC_GCLKGEN1_Val       _U_(0x3)                                             /**< (GCLK_GENCTRL) Generic clock generator 1 output  */
+#define   GCLK_GENCTRL_SRC_OSCULP32K_Val      _U_(0x4)                                             /**< (GCLK_GENCTRL) OSCULP32K oscillator output  */
+#define   GCLK_GENCTRL_SRC_XOSC32K_Val        _U_(0x5)                                             /**< (GCLK_GENCTRL) XOSC32K oscillator output  */
+#define   GCLK_GENCTRL_SRC_DFLL_Val           _U_(0x6)                                             /**< (GCLK_GENCTRL) DFLL output  */
+#define   GCLK_GENCTRL_SRC_DPLL0_Val          _U_(0x7)                                             /**< (GCLK_GENCTRL) DPLL0 output  */
+#define   GCLK_GENCTRL_SRC_DPLL1_Val          _U_(0x8)                                             /**< (GCLK_GENCTRL) DPLL1 output  */
+#define GCLK_GENCTRL_SRC_XOSC0                (GCLK_GENCTRL_SRC_XOSC0_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) XOSC0 oscillator output Position  */
+#define GCLK_GENCTRL_SRC_XOSC1                (GCLK_GENCTRL_SRC_XOSC1_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) XOSC1 oscillator output Position  */
+#define GCLK_GENCTRL_SRC_GCLKIN               (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) Generator input pad Position  */
+#define GCLK_GENCTRL_SRC_GCLKGEN1             (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) Generic clock generator 1 output Position  */
+#define GCLK_GENCTRL_SRC_OSCULP32K            (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) OSCULP32K oscillator output Position  */
+#define GCLK_GENCTRL_SRC_XOSC32K              (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) XOSC32K oscillator output Position  */
+#define GCLK_GENCTRL_SRC_DFLL                 (GCLK_GENCTRL_SRC_DFLL_Val << GCLK_GENCTRL_SRC_Pos)  /**< (GCLK_GENCTRL) DFLL output Position  */
+#define GCLK_GENCTRL_SRC_DPLL0                (GCLK_GENCTRL_SRC_DPLL0_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) DPLL0 output Position  */
+#define GCLK_GENCTRL_SRC_DPLL1                (GCLK_GENCTRL_SRC_DPLL1_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) DPLL1 output Position  */
+#define GCLK_GENCTRL_GENEN_Pos                _U_(8)                                               /**< (GCLK_GENCTRL) Generic Clock Generator Enable Position */
+#define GCLK_GENCTRL_GENEN_Msk                (_U_(0x1) << GCLK_GENCTRL_GENEN_Pos)                 /**< (GCLK_GENCTRL) Generic Clock Generator Enable Mask */
+#define GCLK_GENCTRL_GENEN(value)             (GCLK_GENCTRL_GENEN_Msk & ((value) << GCLK_GENCTRL_GENEN_Pos))
+#define GCLK_GENCTRL_IDC_Pos                  _U_(9)                                               /**< (GCLK_GENCTRL) Improve Duty Cycle Position */
+#define GCLK_GENCTRL_IDC_Msk                  (_U_(0x1) << GCLK_GENCTRL_IDC_Pos)                   /**< (GCLK_GENCTRL) Improve Duty Cycle Mask */
+#define GCLK_GENCTRL_IDC(value)               (GCLK_GENCTRL_IDC_Msk & ((value) << GCLK_GENCTRL_IDC_Pos))
+#define GCLK_GENCTRL_OOV_Pos                  _U_(10)                                              /**< (GCLK_GENCTRL) Output Off Value Position */
+#define GCLK_GENCTRL_OOV_Msk                  (_U_(0x1) << GCLK_GENCTRL_OOV_Pos)                   /**< (GCLK_GENCTRL) Output Off Value Mask */
+#define GCLK_GENCTRL_OOV(value)               (GCLK_GENCTRL_OOV_Msk & ((value) << GCLK_GENCTRL_OOV_Pos))
+#define GCLK_GENCTRL_OE_Pos                   _U_(11)                                              /**< (GCLK_GENCTRL) Output Enable Position */
+#define GCLK_GENCTRL_OE_Msk                   (_U_(0x1) << GCLK_GENCTRL_OE_Pos)                    /**< (GCLK_GENCTRL) Output Enable Mask */
+#define GCLK_GENCTRL_OE(value)                (GCLK_GENCTRL_OE_Msk & ((value) << GCLK_GENCTRL_OE_Pos))
+#define GCLK_GENCTRL_DIVSEL_Pos               _U_(12)                                              /**< (GCLK_GENCTRL) Divide Selection Position */
+#define GCLK_GENCTRL_DIVSEL_Msk               (_U_(0x1) << GCLK_GENCTRL_DIVSEL_Pos)                /**< (GCLK_GENCTRL) Divide Selection Mask */
+#define GCLK_GENCTRL_DIVSEL(value)            (GCLK_GENCTRL_DIVSEL_Msk & ((value) << GCLK_GENCTRL_DIVSEL_Pos))
+#define   GCLK_GENCTRL_DIVSEL_DIV1_Val        _U_(0x0)                                             /**< (GCLK_GENCTRL) Divide input directly by divider factor  */
+#define   GCLK_GENCTRL_DIVSEL_DIV2_Val        _U_(0x1)                                             /**< (GCLK_GENCTRL) Divide input by 2^(divider factor+ 1)  */
+#define GCLK_GENCTRL_DIVSEL_DIV1              (GCLK_GENCTRL_DIVSEL_DIV1_Val << GCLK_GENCTRL_DIVSEL_Pos) /**< (GCLK_GENCTRL) Divide input directly by divider factor Position  */
+#define GCLK_GENCTRL_DIVSEL_DIV2              (GCLK_GENCTRL_DIVSEL_DIV2_Val << GCLK_GENCTRL_DIVSEL_Pos) /**< (GCLK_GENCTRL) Divide input by 2^(divider factor+ 1) Position  */
+#define GCLK_GENCTRL_RUNSTDBY_Pos             _U_(13)                                              /**< (GCLK_GENCTRL) Run in Standby Position */
+#define GCLK_GENCTRL_RUNSTDBY_Msk             (_U_(0x1) << GCLK_GENCTRL_RUNSTDBY_Pos)              /**< (GCLK_GENCTRL) Run in Standby Mask */
+#define GCLK_GENCTRL_RUNSTDBY(value)          (GCLK_GENCTRL_RUNSTDBY_Msk & ((value) << GCLK_GENCTRL_RUNSTDBY_Pos))
+#define GCLK_GENCTRL_DIV_Pos                  _U_(16)                                              /**< (GCLK_GENCTRL) Division Factor Position */
+#define GCLK_GENCTRL_DIV_Msk                  (_U_(0xFFFF) << GCLK_GENCTRL_DIV_Pos)                /**< (GCLK_GENCTRL) Division Factor Mask */
+#define GCLK_GENCTRL_DIV(value)               (GCLK_GENCTRL_DIV_Msk & ((value) << GCLK_GENCTRL_DIV_Pos))
+#define GCLK_GENCTRL_Msk                      _U_(0xFFFF3F0F)                                      /**< (GCLK_GENCTRL) Register Mask  */
+
+
+/* -------- GCLK_PCHCTRL : (GCLK Offset: 0x80) (R/W 32) Peripheral Clock Control -------- */
+#define GCLK_PCHCTRL_RESETVALUE               _U_(0x00)                                            /**<  (GCLK_PCHCTRL) Peripheral Clock Control  Reset Value */
+
+#define GCLK_PCHCTRL_GEN_Pos                  _U_(0)                                               /**< (GCLK_PCHCTRL) Generic Clock Generator Position */
+#define GCLK_PCHCTRL_GEN_Msk                  (_U_(0xF) << GCLK_PCHCTRL_GEN_Pos)                   /**< (GCLK_PCHCTRL) Generic Clock Generator Mask */
+#define GCLK_PCHCTRL_GEN(value)               (GCLK_PCHCTRL_GEN_Msk & ((value) << GCLK_PCHCTRL_GEN_Pos))
+#define   GCLK_PCHCTRL_GEN_GCLK0_Val          _U_(0x0)                                             /**< (GCLK_PCHCTRL) Generic clock generator 0  */
+#define   GCLK_PCHCTRL_GEN_GCLK1_Val          _U_(0x1)                                             /**< (GCLK_PCHCTRL) Generic clock generator 1  */
+#define   GCLK_PCHCTRL_GEN_GCLK2_Val          _U_(0x2)                                             /**< (GCLK_PCHCTRL) Generic clock generator 2  */
+#define   GCLK_PCHCTRL_GEN_GCLK3_Val          _U_(0x3)                                             /**< (GCLK_PCHCTRL) Generic clock generator 3  */
+#define   GCLK_PCHCTRL_GEN_GCLK4_Val          _U_(0x4)                                             /**< (GCLK_PCHCTRL) Generic clock generator 4  */
+#define   GCLK_PCHCTRL_GEN_GCLK5_Val          _U_(0x5)                                             /**< (GCLK_PCHCTRL) Generic clock generator 5  */
+#define   GCLK_PCHCTRL_GEN_GCLK6_Val          _U_(0x6)                                             /**< (GCLK_PCHCTRL) Generic clock generator 6  */
+#define   GCLK_PCHCTRL_GEN_GCLK7_Val          _U_(0x7)                                             /**< (GCLK_PCHCTRL) Generic clock generator 7  */
+#define   GCLK_PCHCTRL_GEN_GCLK8_Val          _U_(0x8)                                             /**< (GCLK_PCHCTRL) Generic clock generator 8  */
+#define   GCLK_PCHCTRL_GEN_GCLK9_Val          _U_(0x9)                                             /**< (GCLK_PCHCTRL) Generic clock generator 9  */
+#define   GCLK_PCHCTRL_GEN_GCLK10_Val         _U_(0xA)                                             /**< (GCLK_PCHCTRL) Generic clock generator 10  */
+#define   GCLK_PCHCTRL_GEN_GCLK11_Val         _U_(0xB)                                             /**< (GCLK_PCHCTRL) Generic clock generator 11  */
+#define GCLK_PCHCTRL_GEN_GCLK0                (GCLK_PCHCTRL_GEN_GCLK0_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 0 Position  */
+#define GCLK_PCHCTRL_GEN_GCLK1                (GCLK_PCHCTRL_GEN_GCLK1_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 1 Position  */
+#define GCLK_PCHCTRL_GEN_GCLK2                (GCLK_PCHCTRL_GEN_GCLK2_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 2 Position  */
+#define GCLK_PCHCTRL_GEN_GCLK3                (GCLK_PCHCTRL_GEN_GCLK3_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 3 Position  */
+#define GCLK_PCHCTRL_GEN_GCLK4                (GCLK_PCHCTRL_GEN_GCLK4_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 4 Position  */
+#define GCLK_PCHCTRL_GEN_GCLK5                (GCLK_PCHCTRL_GEN_GCLK5_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 5 Position  */
+#define GCLK_PCHCTRL_GEN_GCLK6                (GCLK_PCHCTRL_GEN_GCLK6_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 6 Position  */
+#define GCLK_PCHCTRL_GEN_GCLK7                (GCLK_PCHCTRL_GEN_GCLK7_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 7 Position  */
+#define GCLK_PCHCTRL_GEN_GCLK8                (GCLK_PCHCTRL_GEN_GCLK8_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 8 Position  */
+#define GCLK_PCHCTRL_GEN_GCLK9                (GCLK_PCHCTRL_GEN_GCLK9_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 9 Position  */
+#define GCLK_PCHCTRL_GEN_GCLK10               (GCLK_PCHCTRL_GEN_GCLK10_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 10 Position  */
+#define GCLK_PCHCTRL_GEN_GCLK11               (GCLK_PCHCTRL_GEN_GCLK11_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 11 Position  */
+#define GCLK_PCHCTRL_CHEN_Pos                 _U_(6)                                               /**< (GCLK_PCHCTRL) Channel Enable Position */
+#define GCLK_PCHCTRL_CHEN_Msk                 (_U_(0x1) << GCLK_PCHCTRL_CHEN_Pos)                  /**< (GCLK_PCHCTRL) Channel Enable Mask */
+#define GCLK_PCHCTRL_CHEN(value)              (GCLK_PCHCTRL_CHEN_Msk & ((value) << GCLK_PCHCTRL_CHEN_Pos))
+#define GCLK_PCHCTRL_WRTLOCK_Pos              _U_(7)                                               /**< (GCLK_PCHCTRL) Write Lock Position */
+#define GCLK_PCHCTRL_WRTLOCK_Msk              (_U_(0x1) << GCLK_PCHCTRL_WRTLOCK_Pos)               /**< (GCLK_PCHCTRL) Write Lock Mask */
+#define GCLK_PCHCTRL_WRTLOCK(value)           (GCLK_PCHCTRL_WRTLOCK_Msk & ((value) << GCLK_PCHCTRL_WRTLOCK_Pos))
+#define GCLK_PCHCTRL_Msk                      _U_(0x000000CF)                                      /**< (GCLK_PCHCTRL) Register Mask  */
+
+
+/** \brief GCLK register offsets definitions */
+#define GCLK_CTRLA_REG_OFST            (0x00)              /**< (GCLK_CTRLA) Control Offset */
+#define GCLK_SYNCBUSY_REG_OFST         (0x04)              /**< (GCLK_SYNCBUSY) Synchronization Busy Offset */
+#define GCLK_GENCTRL_REG_OFST          (0x20)              /**< (GCLK_GENCTRL) Generic Clock Generator Control Offset */
+#define GCLK_PCHCTRL_REG_OFST          (0x80)              /**< (GCLK_PCHCTRL) Peripheral Clock Control Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief GCLK register API structure */
+typedef struct
+{  /* Generic Clock Generator */
+  __IO  uint8_t                        GCLK_CTRLA;         /**< Offset: 0x00 (R/W  8) Control */
+  __I   uint8_t                        Reserved1[0x03];
+  __I   uint32_t                       GCLK_SYNCBUSY;      /**< Offset: 0x04 (R/   32) Synchronization Busy */
+  __I   uint8_t                        Reserved2[0x18];
+  __IO  uint32_t                       GCLK_GENCTRL[12];   /**< Offset: 0x20 (R/W  32) Generic Clock Generator Control */
+  __I   uint8_t                        Reserved3[0x30];
+  __IO  uint32_t                       GCLK_PCHCTRL[48];   /**< Offset: 0x80 (R/W  32) Peripheral Clock Control */
+} gclk_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _SAMD51_GCLK_COMPONENT_H_ */
Index: /asp_wio_terminal/trunk/target/samd51_gcc/lib/mclk.h
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/lib/mclk.h	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/lib/mclk.h	(revision 460)
@@ -0,0 +1,414 @@
+/**
+ * \brief Component description for MCLK
+ *
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * Subject to your compliance with these terms, you may use Microchip software and any derivatives
+ * exclusively with Microchip products. It is your responsibility to comply with third party license
+ * terms applicable to your use of third party software (including open source software) that may
+ * accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
+ * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
+ * FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
+ * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
+ * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ */
+
+/* file generated from device description version 2020-03-12T17:26:00Z */
+#ifndef _SAMD51_MCLK_COMPONENT_H_
+#define _SAMD51_MCLK_COMPONENT_H_
+
+/* ************************************************************************** */
+/*   SOFTWARE API DEFINITION FOR MCLK                                         */
+/* ************************************************************************** */
+
+/* -------- MCLK_INTENCLR : (MCLK Offset: 0x01) (R/W 8) Interrupt Enable Clear -------- */
+#define MCLK_INTENCLR_RESETVALUE              _U_(0x00)                                            /**<  (MCLK_INTENCLR) Interrupt Enable Clear  Reset Value */
+
+#define MCLK_INTENCLR_CKRDY_Pos               _U_(0)                                               /**< (MCLK_INTENCLR) Clock Ready Interrupt Enable Position */
+#define MCLK_INTENCLR_CKRDY_Msk               (_U_(0x1) << MCLK_INTENCLR_CKRDY_Pos)                /**< (MCLK_INTENCLR) Clock Ready Interrupt Enable Mask */
+#define MCLK_INTENCLR_CKRDY(value)            (MCLK_INTENCLR_CKRDY_Msk & ((value) << MCLK_INTENCLR_CKRDY_Pos))
+#define MCLK_INTENCLR_Msk                     _U_(0x01)                                            /**< (MCLK_INTENCLR) Register Mask  */
+
+
+/* -------- MCLK_INTENSET : (MCLK Offset: 0x02) (R/W 8) Interrupt Enable Set -------- */
+#define MCLK_INTENSET_RESETVALUE              _U_(0x00)                                            /**<  (MCLK_INTENSET) Interrupt Enable Set  Reset Value */
+
+#define MCLK_INTENSET_CKRDY_Pos               _U_(0)                                               /**< (MCLK_INTENSET) Clock Ready Interrupt Enable Position */
+#define MCLK_INTENSET_CKRDY_Msk               (_U_(0x1) << MCLK_INTENSET_CKRDY_Pos)                /**< (MCLK_INTENSET) Clock Ready Interrupt Enable Mask */
+#define MCLK_INTENSET_CKRDY(value)            (MCLK_INTENSET_CKRDY_Msk & ((value) << MCLK_INTENSET_CKRDY_Pos))
+#define MCLK_INTENSET_Msk                     _U_(0x01)                                            /**< (MCLK_INTENSET) Register Mask  */
+
+
+/* -------- MCLK_INTFLAG : (MCLK Offset: 0x03) (R/W 8) Interrupt Flag Status and Clear -------- */
+#define MCLK_INTFLAG_RESETVALUE               _U_(0x01)                                            /**<  (MCLK_INTFLAG) Interrupt Flag Status and Clear  Reset Value */
+
+#define MCLK_INTFLAG_CKRDY_Pos                _U_(0)                                               /**< (MCLK_INTFLAG) Clock Ready Position */
+#define MCLK_INTFLAG_CKRDY_Msk                (_U_(0x1) << MCLK_INTFLAG_CKRDY_Pos)                 /**< (MCLK_INTFLAG) Clock Ready Mask */
+#define MCLK_INTFLAG_CKRDY(value)             (MCLK_INTFLAG_CKRDY_Msk & ((value) << MCLK_INTFLAG_CKRDY_Pos))
+#define MCLK_INTFLAG_Msk                      _U_(0x01)                                            /**< (MCLK_INTFLAG) Register Mask  */
+
+
+/* -------- MCLK_HSDIV : (MCLK Offset: 0x04) ( R/ 8) HS Clock Division -------- */
+#define MCLK_HSDIV_RESETVALUE                 _U_(0x01)                                            /**<  (MCLK_HSDIV) HS Clock Division  Reset Value */
+
+#define MCLK_HSDIV_DIV_Pos                    _U_(0)                                               /**< (MCLK_HSDIV) CPU Clock Division Factor Position */
+#define MCLK_HSDIV_DIV_Msk                    (_U_(0xFF) << MCLK_HSDIV_DIV_Pos)                    /**< (MCLK_HSDIV) CPU Clock Division Factor Mask */
+#define MCLK_HSDIV_DIV(value)                 (MCLK_HSDIV_DIV_Msk & ((value) << MCLK_HSDIV_DIV_Pos))
+#define   MCLK_HSDIV_DIV_DIV1_Val             _U_(0x1)                                             /**< (MCLK_HSDIV) Divide by 1  */
+#define MCLK_HSDIV_DIV_DIV1                   (MCLK_HSDIV_DIV_DIV1_Val << MCLK_HSDIV_DIV_Pos)      /**< (MCLK_HSDIV) Divide by 1 Position  */
+#define MCLK_HSDIV_Msk                        _U_(0xFF)                                            /**< (MCLK_HSDIV) Register Mask  */
+
+
+/* -------- MCLK_CPUDIV : (MCLK Offset: 0x05) (R/W 8) CPU Clock Division -------- */
+#define MCLK_CPUDIV_RESETVALUE                _U_(0x01)                                            /**<  (MCLK_CPUDIV) CPU Clock Division  Reset Value */
+
+#define MCLK_CPUDIV_DIV_Pos                   _U_(0)                                               /**< (MCLK_CPUDIV) Low-Power Clock Division Factor Position */
+#define MCLK_CPUDIV_DIV_Msk                   (_U_(0xFF) << MCLK_CPUDIV_DIV_Pos)                   /**< (MCLK_CPUDIV) Low-Power Clock Division Factor Mask */
+#define MCLK_CPUDIV_DIV(value)                (MCLK_CPUDIV_DIV_Msk & ((value) << MCLK_CPUDIV_DIV_Pos))
+#define   MCLK_CPUDIV_DIV_DIV1_Val            _U_(0x1)                                             /**< (MCLK_CPUDIV) Divide by 1  */
+#define   MCLK_CPUDIV_DIV_DIV2_Val            _U_(0x2)                                             /**< (MCLK_CPUDIV) Divide by 2  */
+#define   MCLK_CPUDIV_DIV_DIV4_Val            _U_(0x4)                                             /**< (MCLK_CPUDIV) Divide by 4  */
+#define   MCLK_CPUDIV_DIV_DIV8_Val            _U_(0x8)                                             /**< (MCLK_CPUDIV) Divide by 8  */
+#define   MCLK_CPUDIV_DIV_DIV16_Val           _U_(0x10)                                            /**< (MCLK_CPUDIV) Divide by 16  */
+#define   MCLK_CPUDIV_DIV_DIV32_Val           _U_(0x20)                                            /**< (MCLK_CPUDIV) Divide by 32  */
+#define   MCLK_CPUDIV_DIV_DIV64_Val           _U_(0x40)                                            /**< (MCLK_CPUDIV) Divide by 64  */
+#define   MCLK_CPUDIV_DIV_DIV128_Val          _U_(0x80)                                            /**< (MCLK_CPUDIV) Divide by 128  */
+#define MCLK_CPUDIV_DIV_DIV1                  (MCLK_CPUDIV_DIV_DIV1_Val << MCLK_CPUDIV_DIV_Pos)    /**< (MCLK_CPUDIV) Divide by 1 Position  */
+#define MCLK_CPUDIV_DIV_DIV2                  (MCLK_CPUDIV_DIV_DIV2_Val << MCLK_CPUDIV_DIV_Pos)    /**< (MCLK_CPUDIV) Divide by 2 Position  */
+#define MCLK_CPUDIV_DIV_DIV4                  (MCLK_CPUDIV_DIV_DIV4_Val << MCLK_CPUDIV_DIV_Pos)    /**< (MCLK_CPUDIV) Divide by 4 Position  */
+#define MCLK_CPUDIV_DIV_DIV8                  (MCLK_CPUDIV_DIV_DIV8_Val << MCLK_CPUDIV_DIV_Pos)    /**< (MCLK_CPUDIV) Divide by 8 Position  */
+#define MCLK_CPUDIV_DIV_DIV16                 (MCLK_CPUDIV_DIV_DIV16_Val << MCLK_CPUDIV_DIV_Pos)   /**< (MCLK_CPUDIV) Divide by 16 Position  */
+#define MCLK_CPUDIV_DIV_DIV32                 (MCLK_CPUDIV_DIV_DIV32_Val << MCLK_CPUDIV_DIV_Pos)   /**< (MCLK_CPUDIV) Divide by 32 Position  */
+#define MCLK_CPUDIV_DIV_DIV64                 (MCLK_CPUDIV_DIV_DIV64_Val << MCLK_CPUDIV_DIV_Pos)   /**< (MCLK_CPUDIV) Divide by 64 Position  */
+#define MCLK_CPUDIV_DIV_DIV128                (MCLK_CPUDIV_DIV_DIV128_Val << MCLK_CPUDIV_DIV_Pos)  /**< (MCLK_CPUDIV) Divide by 128 Position  */
+#define MCLK_CPUDIV_Msk                       _U_(0xFF)                                            /**< (MCLK_CPUDIV) Register Mask  */
+
+
+/* -------- MCLK_AHBMASK : (MCLK Offset: 0x10) (R/W 32) AHB Mask -------- */
+#define MCLK_AHBMASK_RESETVALUE               _U_(0xFFFFFF)                                        /**<  (MCLK_AHBMASK) AHB Mask  Reset Value */
+
+#define MCLK_AHBMASK_HPB0_Pos                 _U_(0)                                               /**< (MCLK_AHBMASK) HPB0 AHB Clock Mask Position */
+#define MCLK_AHBMASK_HPB0_Msk                 (_U_(0x1) << MCLK_AHBMASK_HPB0_Pos)                  /**< (MCLK_AHBMASK) HPB0 AHB Clock Mask Mask */
+#define MCLK_AHBMASK_HPB0(value)              (MCLK_AHBMASK_HPB0_Msk & ((value) << MCLK_AHBMASK_HPB0_Pos))
+#define MCLK_AHBMASK_HPB1_Pos                 _U_(1)                                               /**< (MCLK_AHBMASK) HPB1 AHB Clock Mask Position */
+#define MCLK_AHBMASK_HPB1_Msk                 (_U_(0x1) << MCLK_AHBMASK_HPB1_Pos)                  /**< (MCLK_AHBMASK) HPB1 AHB Clock Mask Mask */
+#define MCLK_AHBMASK_HPB1(value)              (MCLK_AHBMASK_HPB1_Msk & ((value) << MCLK_AHBMASK_HPB1_Pos))
+#define MCLK_AHBMASK_HPB2_Pos                 _U_(2)                                               /**< (MCLK_AHBMASK) HPB2 AHB Clock Mask Position */
+#define MCLK_AHBMASK_HPB2_Msk                 (_U_(0x1) << MCLK_AHBMASK_HPB2_Pos)                  /**< (MCLK_AHBMASK) HPB2 AHB Clock Mask Mask */
+#define MCLK_AHBMASK_HPB2(value)              (MCLK_AHBMASK_HPB2_Msk & ((value) << MCLK_AHBMASK_HPB2_Pos))
+#define MCLK_AHBMASK_HPB3_Pos                 _U_(3)                                               /**< (MCLK_AHBMASK) HPB3 AHB Clock Mask Position */
+#define MCLK_AHBMASK_HPB3_Msk                 (_U_(0x1) << MCLK_AHBMASK_HPB3_Pos)                  /**< (MCLK_AHBMASK) HPB3 AHB Clock Mask Mask */
+#define MCLK_AHBMASK_HPB3(value)              (MCLK_AHBMASK_HPB3_Msk & ((value) << MCLK_AHBMASK_HPB3_Pos))
+#define MCLK_AHBMASK_DSU_Pos                  _U_(4)                                               /**< (MCLK_AHBMASK) DSU AHB Clock Mask Position */
+#define MCLK_AHBMASK_DSU_Msk                  (_U_(0x1) << MCLK_AHBMASK_DSU_Pos)                   /**< (MCLK_AHBMASK) DSU AHB Clock Mask Mask */
+#define MCLK_AHBMASK_DSU(value)               (MCLK_AHBMASK_DSU_Msk & ((value) << MCLK_AHBMASK_DSU_Pos))
+#define MCLK_AHBMASK_HMATRIX_Pos              _U_(5)                                               /**< (MCLK_AHBMASK) HMATRIX AHB Clock Mask Position */
+#define MCLK_AHBMASK_HMATRIX_Msk              (_U_(0x1) << MCLK_AHBMASK_HMATRIX_Pos)               /**< (MCLK_AHBMASK) HMATRIX AHB Clock Mask Mask */
+#define MCLK_AHBMASK_HMATRIX(value)           (MCLK_AHBMASK_HMATRIX_Msk & ((value) << MCLK_AHBMASK_HMATRIX_Pos))
+#define MCLK_AHBMASK_NVMCTRL_Pos              _U_(6)                                               /**< (MCLK_AHBMASK) NVMCTRL AHB Clock Mask Position */
+#define MCLK_AHBMASK_NVMCTRL_Msk              (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_Pos)               /**< (MCLK_AHBMASK) NVMCTRL AHB Clock Mask Mask */
+#define MCLK_AHBMASK_NVMCTRL(value)           (MCLK_AHBMASK_NVMCTRL_Msk & ((value) << MCLK_AHBMASK_NVMCTRL_Pos))
+#define MCLK_AHBMASK_HSRAM_Pos                _U_(7)                                               /**< (MCLK_AHBMASK) HSRAM AHB Clock Mask Position */
+#define MCLK_AHBMASK_HSRAM_Msk                (_U_(0x1) << MCLK_AHBMASK_HSRAM_Pos)                 /**< (MCLK_AHBMASK) HSRAM AHB Clock Mask Mask */
+#define MCLK_AHBMASK_HSRAM(value)             (MCLK_AHBMASK_HSRAM_Msk & ((value) << MCLK_AHBMASK_HSRAM_Pos))
+#define MCLK_AHBMASK_CMCC_Pos                 _U_(8)                                               /**< (MCLK_AHBMASK) CMCC AHB Clock Mask Position */
+#define MCLK_AHBMASK_CMCC_Msk                 (_U_(0x1) << MCLK_AHBMASK_CMCC_Pos)                  /**< (MCLK_AHBMASK) CMCC AHB Clock Mask Mask */
+#define MCLK_AHBMASK_CMCC(value)              (MCLK_AHBMASK_CMCC_Msk & ((value) << MCLK_AHBMASK_CMCC_Pos))
+#define MCLK_AHBMASK_DMAC_Pos                 _U_(9)                                               /**< (MCLK_AHBMASK) DMAC AHB Clock Mask Position */
+#define MCLK_AHBMASK_DMAC_Msk                 (_U_(0x1) << MCLK_AHBMASK_DMAC_Pos)                  /**< (MCLK_AHBMASK) DMAC AHB Clock Mask Mask */
+#define MCLK_AHBMASK_DMAC(value)              (MCLK_AHBMASK_DMAC_Msk & ((value) << MCLK_AHBMASK_DMAC_Pos))
+#define MCLK_AHBMASK_USB_Pos                  _U_(10)                                              /**< (MCLK_AHBMASK) USB AHB Clock Mask Position */
+#define MCLK_AHBMASK_USB_Msk                  (_U_(0x1) << MCLK_AHBMASK_USB_Pos)                   /**< (MCLK_AHBMASK) USB AHB Clock Mask Mask */
+#define MCLK_AHBMASK_USB(value)               (MCLK_AHBMASK_USB_Msk & ((value) << MCLK_AHBMASK_USB_Pos))
+#define MCLK_AHBMASK_BKUPRAM_Pos              _U_(11)                                              /**< (MCLK_AHBMASK) BKUPRAM AHB Clock Mask Position */
+#define MCLK_AHBMASK_BKUPRAM_Msk              (_U_(0x1) << MCLK_AHBMASK_BKUPRAM_Pos)               /**< (MCLK_AHBMASK) BKUPRAM AHB Clock Mask Mask */
+#define MCLK_AHBMASK_BKUPRAM(value)           (MCLK_AHBMASK_BKUPRAM_Msk & ((value) << MCLK_AHBMASK_BKUPRAM_Pos))
+#define MCLK_AHBMASK_PAC_Pos                  _U_(12)                                              /**< (MCLK_AHBMASK) PAC AHB Clock Mask Position */
+#define MCLK_AHBMASK_PAC_Msk                  (_U_(0x1) << MCLK_AHBMASK_PAC_Pos)                   /**< (MCLK_AHBMASK) PAC AHB Clock Mask Mask */
+#define MCLK_AHBMASK_PAC(value)               (MCLK_AHBMASK_PAC_Msk & ((value) << MCLK_AHBMASK_PAC_Pos))
+#define MCLK_AHBMASK_QSPI_Pos                 _U_(13)                                              /**< (MCLK_AHBMASK) QSPI AHB Clock Mask Position */
+#define MCLK_AHBMASK_QSPI_Msk                 (_U_(0x1) << MCLK_AHBMASK_QSPI_Pos)                  /**< (MCLK_AHBMASK) QSPI AHB Clock Mask Mask */
+#define MCLK_AHBMASK_QSPI(value)              (MCLK_AHBMASK_QSPI_Msk & ((value) << MCLK_AHBMASK_QSPI_Pos))
+#define MCLK_AHBMASK_SDHC0_Pos                _U_(15)                                              /**< (MCLK_AHBMASK) SDHC0 AHB Clock Mask Position */
+#define MCLK_AHBMASK_SDHC0_Msk                (_U_(0x1) << MCLK_AHBMASK_SDHC0_Pos)                 /**< (MCLK_AHBMASK) SDHC0 AHB Clock Mask Mask */
+#define MCLK_AHBMASK_SDHC0(value)             (MCLK_AHBMASK_SDHC0_Msk & ((value) << MCLK_AHBMASK_SDHC0_Pos))
+#define MCLK_AHBMASK_SDHC1_Pos                _U_(16)                                              /**< (MCLK_AHBMASK) SDHC1 AHB Clock Mask Position */
+#define MCLK_AHBMASK_SDHC1_Msk                (_U_(0x1) << MCLK_AHBMASK_SDHC1_Pos)                 /**< (MCLK_AHBMASK) SDHC1 AHB Clock Mask Mask */
+#define MCLK_AHBMASK_SDHC1(value)             (MCLK_AHBMASK_SDHC1_Msk & ((value) << MCLK_AHBMASK_SDHC1_Pos))
+#define MCLK_AHBMASK_ICM_Pos                  _U_(19)                                              /**< (MCLK_AHBMASK) ICM AHB Clock Mask Position */
+#define MCLK_AHBMASK_ICM_Msk                  (_U_(0x1) << MCLK_AHBMASK_ICM_Pos)                   /**< (MCLK_AHBMASK) ICM AHB Clock Mask Mask */
+#define MCLK_AHBMASK_ICM(value)               (MCLK_AHBMASK_ICM_Msk & ((value) << MCLK_AHBMASK_ICM_Pos))
+#define MCLK_AHBMASK_PUKCC_Pos                _U_(20)                                              /**< (MCLK_AHBMASK) PUKCC AHB Clock Mask Position */
+#define MCLK_AHBMASK_PUKCC_Msk                (_U_(0x1) << MCLK_AHBMASK_PUKCC_Pos)                 /**< (MCLK_AHBMASK) PUKCC AHB Clock Mask Mask */
+#define MCLK_AHBMASK_PUKCC(value)             (MCLK_AHBMASK_PUKCC_Msk & ((value) << MCLK_AHBMASK_PUKCC_Pos))
+#define MCLK_AHBMASK_QSPI_2X_Pos              _U_(21)                                              /**< (MCLK_AHBMASK) QSPI_2X AHB Clock Mask Position */
+#define MCLK_AHBMASK_QSPI_2X_Msk              (_U_(0x1) << MCLK_AHBMASK_QSPI_2X_Pos)               /**< (MCLK_AHBMASK) QSPI_2X AHB Clock Mask Mask */
+#define MCLK_AHBMASK_QSPI_2X(value)           (MCLK_AHBMASK_QSPI_2X_Msk & ((value) << MCLK_AHBMASK_QSPI_2X_Pos))
+#define MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos     _U_(22)                                              /**< (MCLK_AHBMASK) NVMCTRL_SMEEPROM AHB Clock Mask Position */
+#define MCLK_AHBMASK_NVMCTRL_SMEEPROM_Msk     (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos)      /**< (MCLK_AHBMASK) NVMCTRL_SMEEPROM AHB Clock Mask Mask */
+#define MCLK_AHBMASK_NVMCTRL_SMEEPROM(value)  (MCLK_AHBMASK_NVMCTRL_SMEEPROM_Msk & ((value) << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos))
+#define MCLK_AHBMASK_NVMCTRL_CACHE_Pos        _U_(23)                                              /**< (MCLK_AHBMASK) NVMCTRL_CACHE AHB Clock Mask Position */
+#define MCLK_AHBMASK_NVMCTRL_CACHE_Msk        (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_CACHE_Pos)         /**< (MCLK_AHBMASK) NVMCTRL_CACHE AHB Clock Mask Mask */
+#define MCLK_AHBMASK_NVMCTRL_CACHE(value)     (MCLK_AHBMASK_NVMCTRL_CACHE_Msk & ((value) << MCLK_AHBMASK_NVMCTRL_CACHE_Pos))
+#define MCLK_AHBMASK_Msk                      _U_(0x00F9BFFF)                                      /**< (MCLK_AHBMASK) Register Mask  */
+
+#define MCLK_AHBMASK_HPB_Pos                  _U_(0)                                               /**< (MCLK_AHBMASK Position) HPBx AHB Clock Mask */
+#define MCLK_AHBMASK_HPB_Msk                  (_U_(0xF) << MCLK_AHBMASK_HPB_Pos)                   /**< (MCLK_AHBMASK Mask) HPB */
+#define MCLK_AHBMASK_HPB(value)               (MCLK_AHBMASK_HPB_Msk & ((value) << MCLK_AHBMASK_HPB_Pos)) 
+#define MCLK_AHBMASK_SDHC_Pos                 _U_(15)                                              /**< (MCLK_AHBMASK Position) SDHCx AHB Clock Mask */
+#define MCLK_AHBMASK_SDHC_Msk                 (_U_(0x3) << MCLK_AHBMASK_SDHC_Pos)                  /**< (MCLK_AHBMASK Mask) SDHC */
+#define MCLK_AHBMASK_SDHC(value)              (MCLK_AHBMASK_SDHC_Msk & ((value) << MCLK_AHBMASK_SDHC_Pos)) 
+
+/* -------- MCLK_APBAMASK : (MCLK Offset: 0x14) (R/W 32) APBA Mask -------- */
+#define MCLK_APBAMASK_RESETVALUE              _U_(0x7FF)                                           /**<  (MCLK_APBAMASK) APBA Mask  Reset Value */
+
+#define MCLK_APBAMASK_PAC_Pos                 _U_(0)                                               /**< (MCLK_APBAMASK) PAC APB Clock Enable Position */
+#define MCLK_APBAMASK_PAC_Msk                 (_U_(0x1) << MCLK_APBAMASK_PAC_Pos)                  /**< (MCLK_APBAMASK) PAC APB Clock Enable Mask */
+#define MCLK_APBAMASK_PAC(value)              (MCLK_APBAMASK_PAC_Msk & ((value) << MCLK_APBAMASK_PAC_Pos))
+#define MCLK_APBAMASK_PM_Pos                  _U_(1)                                               /**< (MCLK_APBAMASK) PM APB Clock Enable Position */
+#define MCLK_APBAMASK_PM_Msk                  (_U_(0x1) << MCLK_APBAMASK_PM_Pos)                   /**< (MCLK_APBAMASK) PM APB Clock Enable Mask */
+#define MCLK_APBAMASK_PM(value)               (MCLK_APBAMASK_PM_Msk & ((value) << MCLK_APBAMASK_PM_Pos))
+#define MCLK_APBAMASK_MCLK_Pos                _U_(2)                                               /**< (MCLK_APBAMASK) MCLK APB Clock Enable Position */
+#define MCLK_APBAMASK_MCLK_Msk                (_U_(0x1) << MCLK_APBAMASK_MCLK_Pos)                 /**< (MCLK_APBAMASK) MCLK APB Clock Enable Mask */
+#define MCLK_APBAMASK_MCLK(value)             (MCLK_APBAMASK_MCLK_Msk & ((value) << MCLK_APBAMASK_MCLK_Pos))
+#define MCLK_APBAMASK_RSTC_Pos                _U_(3)                                               /**< (MCLK_APBAMASK) RSTC APB Clock Enable Position */
+#define MCLK_APBAMASK_RSTC_Msk                (_U_(0x1) << MCLK_APBAMASK_RSTC_Pos)                 /**< (MCLK_APBAMASK) RSTC APB Clock Enable Mask */
+#define MCLK_APBAMASK_RSTC(value)             (MCLK_APBAMASK_RSTC_Msk & ((value) << MCLK_APBAMASK_RSTC_Pos))
+#define MCLK_APBAMASK_OSCCTRL_Pos             _U_(4)                                               /**< (MCLK_APBAMASK) OSCCTRL APB Clock Enable Position */
+#define MCLK_APBAMASK_OSCCTRL_Msk             (_U_(0x1) << MCLK_APBAMASK_OSCCTRL_Pos)              /**< (MCLK_APBAMASK) OSCCTRL APB Clock Enable Mask */
+#define MCLK_APBAMASK_OSCCTRL(value)          (MCLK_APBAMASK_OSCCTRL_Msk & ((value) << MCLK_APBAMASK_OSCCTRL_Pos))
+#define MCLK_APBAMASK_OSC32KCTRL_Pos          _U_(5)                                               /**< (MCLK_APBAMASK) OSC32KCTRL APB Clock Enable Position */
+#define MCLK_APBAMASK_OSC32KCTRL_Msk          (_U_(0x1) << MCLK_APBAMASK_OSC32KCTRL_Pos)           /**< (MCLK_APBAMASK) OSC32KCTRL APB Clock Enable Mask */
+#define MCLK_APBAMASK_OSC32KCTRL(value)       (MCLK_APBAMASK_OSC32KCTRL_Msk & ((value) << MCLK_APBAMASK_OSC32KCTRL_Pos))
+#define MCLK_APBAMASK_SUPC_Pos                _U_(6)                                               /**< (MCLK_APBAMASK) SUPC APB Clock Enable Position */
+#define MCLK_APBAMASK_SUPC_Msk                (_U_(0x1) << MCLK_APBAMASK_SUPC_Pos)                 /**< (MCLK_APBAMASK) SUPC APB Clock Enable Mask */
+#define MCLK_APBAMASK_SUPC(value)             (MCLK_APBAMASK_SUPC_Msk & ((value) << MCLK_APBAMASK_SUPC_Pos))
+#define MCLK_APBAMASK_GCLK_Pos                _U_(7)                                               /**< (MCLK_APBAMASK) GCLK APB Clock Enable Position */
+#define MCLK_APBAMASK_GCLK_Msk                (_U_(0x1) << MCLK_APBAMASK_GCLK_Pos)                 /**< (MCLK_APBAMASK) GCLK APB Clock Enable Mask */
+#define MCLK_APBAMASK_GCLK(value)             (MCLK_APBAMASK_GCLK_Msk & ((value) << MCLK_APBAMASK_GCLK_Pos))
+#define MCLK_APBAMASK_WDT_Pos                 _U_(8)                                               /**< (MCLK_APBAMASK) WDT APB Clock Enable Position */
+#define MCLK_APBAMASK_WDT_Msk                 (_U_(0x1) << MCLK_APBAMASK_WDT_Pos)                  /**< (MCLK_APBAMASK) WDT APB Clock Enable Mask */
+#define MCLK_APBAMASK_WDT(value)              (MCLK_APBAMASK_WDT_Msk & ((value) << MCLK_APBAMASK_WDT_Pos))
+#define MCLK_APBAMASK_RTC_Pos                 _U_(9)                                               /**< (MCLK_APBAMASK) RTC APB Clock Enable Position */
+#define MCLK_APBAMASK_RTC_Msk                 (_U_(0x1) << MCLK_APBAMASK_RTC_Pos)                  /**< (MCLK_APBAMASK) RTC APB Clock Enable Mask */
+#define MCLK_APBAMASK_RTC(value)              (MCLK_APBAMASK_RTC_Msk & ((value) << MCLK_APBAMASK_RTC_Pos))
+#define MCLK_APBAMASK_EIC_Pos                 _U_(10)                                              /**< (MCLK_APBAMASK) EIC APB Clock Enable Position */
+#define MCLK_APBAMASK_EIC_Msk                 (_U_(0x1) << MCLK_APBAMASK_EIC_Pos)                  /**< (MCLK_APBAMASK) EIC APB Clock Enable Mask */
+#define MCLK_APBAMASK_EIC(value)              (MCLK_APBAMASK_EIC_Msk & ((value) << MCLK_APBAMASK_EIC_Pos))
+#define MCLK_APBAMASK_FREQM_Pos               _U_(11)                                              /**< (MCLK_APBAMASK) FREQM APB Clock Enable Position */
+#define MCLK_APBAMASK_FREQM_Msk               (_U_(0x1) << MCLK_APBAMASK_FREQM_Pos)                /**< (MCLK_APBAMASK) FREQM APB Clock Enable Mask */
+#define MCLK_APBAMASK_FREQM(value)            (MCLK_APBAMASK_FREQM_Msk & ((value) << MCLK_APBAMASK_FREQM_Pos))
+#define MCLK_APBAMASK_SERCOM0_Pos             _U_(12)                                              /**< (MCLK_APBAMASK) SERCOM0 APB Clock Enable Position */
+#define MCLK_APBAMASK_SERCOM0_Msk             (_U_(0x1) << MCLK_APBAMASK_SERCOM0_Pos)              /**< (MCLK_APBAMASK) SERCOM0 APB Clock Enable Mask */
+#define MCLK_APBAMASK_SERCOM0(value)          (MCLK_APBAMASK_SERCOM0_Msk & ((value) << MCLK_APBAMASK_SERCOM0_Pos))
+#define MCLK_APBAMASK_SERCOM1_Pos             _U_(13)                                              /**< (MCLK_APBAMASK) SERCOM1 APB Clock Enable Position */
+#define MCLK_APBAMASK_SERCOM1_Msk             (_U_(0x1) << MCLK_APBAMASK_SERCOM1_Pos)              /**< (MCLK_APBAMASK) SERCOM1 APB Clock Enable Mask */
+#define MCLK_APBAMASK_SERCOM1(value)          (MCLK_APBAMASK_SERCOM1_Msk & ((value) << MCLK_APBAMASK_SERCOM1_Pos))
+#define MCLK_APBAMASK_TC0_Pos                 _U_(14)                                              /**< (MCLK_APBAMASK) TC0 APB Clock Enable Position */
+#define MCLK_APBAMASK_TC0_Msk                 (_U_(0x1) << MCLK_APBAMASK_TC0_Pos)                  /**< (MCLK_APBAMASK) TC0 APB Clock Enable Mask */
+#define MCLK_APBAMASK_TC0(value)              (MCLK_APBAMASK_TC0_Msk & ((value) << MCLK_APBAMASK_TC0_Pos))
+#define MCLK_APBAMASK_TC1_Pos                 _U_(15)                                              /**< (MCLK_APBAMASK) TC1 APB Clock Enable Position */
+#define MCLK_APBAMASK_TC1_Msk                 (_U_(0x1) << MCLK_APBAMASK_TC1_Pos)                  /**< (MCLK_APBAMASK) TC1 APB Clock Enable Mask */
+#define MCLK_APBAMASK_TC1(value)              (MCLK_APBAMASK_TC1_Msk & ((value) << MCLK_APBAMASK_TC1_Pos))
+#define MCLK_APBAMASK_Msk                     _U_(0x0000FFFF)                                      /**< (MCLK_APBAMASK) Register Mask  */
+
+#define MCLK_APBAMASK_SERCOM_Pos              _U_(12)                                              /**< (MCLK_APBAMASK Position) SERCOMx APB Clock Enable */
+#define MCLK_APBAMASK_SERCOM_Msk              (_U_(0x3) << MCLK_APBAMASK_SERCOM_Pos)               /**< (MCLK_APBAMASK Mask) SERCOM */
+#define MCLK_APBAMASK_SERCOM(value)           (MCLK_APBAMASK_SERCOM_Msk & ((value) << MCLK_APBAMASK_SERCOM_Pos)) 
+#define MCLK_APBAMASK_TC_Pos                  _U_(14)                                              /**< (MCLK_APBAMASK Position) TCx APB Clock Enable */
+#define MCLK_APBAMASK_TC_Msk                  (_U_(0x3) << MCLK_APBAMASK_TC_Pos)                   /**< (MCLK_APBAMASK Mask) TC */
+#define MCLK_APBAMASK_TC(value)               (MCLK_APBAMASK_TC_Msk & ((value) << MCLK_APBAMASK_TC_Pos)) 
+
+/* -------- MCLK_APBBMASK : (MCLK Offset: 0x18) (R/W 32) APBB Mask -------- */
+#define MCLK_APBBMASK_RESETVALUE              _U_(0x18056)                                         /**<  (MCLK_APBBMASK) APBB Mask  Reset Value */
+
+#define MCLK_APBBMASK_USB_Pos                 _U_(0)                                               /**< (MCLK_APBBMASK) USB APB Clock Enable Position */
+#define MCLK_APBBMASK_USB_Msk                 (_U_(0x1) << MCLK_APBBMASK_USB_Pos)                  /**< (MCLK_APBBMASK) USB APB Clock Enable Mask */
+#define MCLK_APBBMASK_USB(value)              (MCLK_APBBMASK_USB_Msk & ((value) << MCLK_APBBMASK_USB_Pos))
+#define MCLK_APBBMASK_DSU_Pos                 _U_(1)                                               /**< (MCLK_APBBMASK) DSU APB Clock Enable Position */
+#define MCLK_APBBMASK_DSU_Msk                 (_U_(0x1) << MCLK_APBBMASK_DSU_Pos)                  /**< (MCLK_APBBMASK) DSU APB Clock Enable Mask */
+#define MCLK_APBBMASK_DSU(value)              (MCLK_APBBMASK_DSU_Msk & ((value) << MCLK_APBBMASK_DSU_Pos))
+#define MCLK_APBBMASK_NVMCTRL_Pos             _U_(2)                                               /**< (MCLK_APBBMASK) NVMCTRL APB Clock Enable Position */
+#define MCLK_APBBMASK_NVMCTRL_Msk             (_U_(0x1) << MCLK_APBBMASK_NVMCTRL_Pos)              /**< (MCLK_APBBMASK) NVMCTRL APB Clock Enable Mask */
+#define MCLK_APBBMASK_NVMCTRL(value)          (MCLK_APBBMASK_NVMCTRL_Msk & ((value) << MCLK_APBBMASK_NVMCTRL_Pos))
+#define MCLK_APBBMASK_PORT_Pos                _U_(4)                                               /**< (MCLK_APBBMASK) PORT APB Clock Enable Position */
+#define MCLK_APBBMASK_PORT_Msk                (_U_(0x1) << MCLK_APBBMASK_PORT_Pos)                 /**< (MCLK_APBBMASK) PORT APB Clock Enable Mask */
+#define MCLK_APBBMASK_PORT(value)             (MCLK_APBBMASK_PORT_Msk & ((value) << MCLK_APBBMASK_PORT_Pos))
+#define MCLK_APBBMASK_HMATRIX_Pos             _U_(6)                                               /**< (MCLK_APBBMASK) HMATRIX APB Clock Enable Position */
+#define MCLK_APBBMASK_HMATRIX_Msk             (_U_(0x1) << MCLK_APBBMASK_HMATRIX_Pos)              /**< (MCLK_APBBMASK) HMATRIX APB Clock Enable Mask */
+#define MCLK_APBBMASK_HMATRIX(value)          (MCLK_APBBMASK_HMATRIX_Msk & ((value) << MCLK_APBBMASK_HMATRIX_Pos))
+#define MCLK_APBBMASK_EVSYS_Pos               _U_(7)                                               /**< (MCLK_APBBMASK) EVSYS APB Clock Enable Position */
+#define MCLK_APBBMASK_EVSYS_Msk               (_U_(0x1) << MCLK_APBBMASK_EVSYS_Pos)                /**< (MCLK_APBBMASK) EVSYS APB Clock Enable Mask */
+#define MCLK_APBBMASK_EVSYS(value)            (MCLK_APBBMASK_EVSYS_Msk & ((value) << MCLK_APBBMASK_EVSYS_Pos))
+#define MCLK_APBBMASK_SERCOM2_Pos             _U_(9)                                               /**< (MCLK_APBBMASK) SERCOM2 APB Clock Enable Position */
+#define MCLK_APBBMASK_SERCOM2_Msk             (_U_(0x1) << MCLK_APBBMASK_SERCOM2_Pos)              /**< (MCLK_APBBMASK) SERCOM2 APB Clock Enable Mask */
+#define MCLK_APBBMASK_SERCOM2(value)          (MCLK_APBBMASK_SERCOM2_Msk & ((value) << MCLK_APBBMASK_SERCOM2_Pos))
+#define MCLK_APBBMASK_SERCOM3_Pos             _U_(10)                                              /**< (MCLK_APBBMASK) SERCOM3 APB Clock Enable Position */
+#define MCLK_APBBMASK_SERCOM3_Msk             (_U_(0x1) << MCLK_APBBMASK_SERCOM3_Pos)              /**< (MCLK_APBBMASK) SERCOM3 APB Clock Enable Mask */
+#define MCLK_APBBMASK_SERCOM3(value)          (MCLK_APBBMASK_SERCOM3_Msk & ((value) << MCLK_APBBMASK_SERCOM3_Pos))
+#define MCLK_APBBMASK_TCC0_Pos                _U_(11)                                              /**< (MCLK_APBBMASK) TCC0 APB Clock Enable Position */
+#define MCLK_APBBMASK_TCC0_Msk                (_U_(0x1) << MCLK_APBBMASK_TCC0_Pos)                 /**< (MCLK_APBBMASK) TCC0 APB Clock Enable Mask */
+#define MCLK_APBBMASK_TCC0(value)             (MCLK_APBBMASK_TCC0_Msk & ((value) << MCLK_APBBMASK_TCC0_Pos))
+#define MCLK_APBBMASK_TCC1_Pos                _U_(12)                                              /**< (MCLK_APBBMASK) TCC1 APB Clock Enable Position */
+#define MCLK_APBBMASK_TCC1_Msk                (_U_(0x1) << MCLK_APBBMASK_TCC1_Pos)                 /**< (MCLK_APBBMASK) TCC1 APB Clock Enable Mask */
+#define MCLK_APBBMASK_TCC1(value)             (MCLK_APBBMASK_TCC1_Msk & ((value) << MCLK_APBBMASK_TCC1_Pos))
+#define MCLK_APBBMASK_TC2_Pos                 _U_(13)                                              /**< (MCLK_APBBMASK) TC2 APB Clock Enable Position */
+#define MCLK_APBBMASK_TC2_Msk                 (_U_(0x1) << MCLK_APBBMASK_TC2_Pos)                  /**< (MCLK_APBBMASK) TC2 APB Clock Enable Mask */
+#define MCLK_APBBMASK_TC2(value)              (MCLK_APBBMASK_TC2_Msk & ((value) << MCLK_APBBMASK_TC2_Pos))
+#define MCLK_APBBMASK_TC3_Pos                 _U_(14)                                              /**< (MCLK_APBBMASK) TC3 APB Clock Enable Position */
+#define MCLK_APBBMASK_TC3_Msk                 (_U_(0x1) << MCLK_APBBMASK_TC3_Pos)                  /**< (MCLK_APBBMASK) TC3 APB Clock Enable Mask */
+#define MCLK_APBBMASK_TC3(value)              (MCLK_APBBMASK_TC3_Msk & ((value) << MCLK_APBBMASK_TC3_Pos))
+#define MCLK_APBBMASK_RAMECC_Pos              _U_(16)                                              /**< (MCLK_APBBMASK) RAMECC APB Clock Enable Position */
+#define MCLK_APBBMASK_RAMECC_Msk              (_U_(0x1) << MCLK_APBBMASK_RAMECC_Pos)               /**< (MCLK_APBBMASK) RAMECC APB Clock Enable Mask */
+#define MCLK_APBBMASK_RAMECC(value)           (MCLK_APBBMASK_RAMECC_Msk & ((value) << MCLK_APBBMASK_RAMECC_Pos))
+#define MCLK_APBBMASK_Msk                     _U_(0x00017ED7)                                      /**< (MCLK_APBBMASK) Register Mask  */
+
+#define MCLK_APBBMASK_SERCOM_Pos              _U_(9)                                               /**< (MCLK_APBBMASK Position) SERCOM2 APB Clock Enable */
+#define MCLK_APBBMASK_SERCOM_Msk              (_U_(0x3) << MCLK_APBBMASK_SERCOM_Pos)               /**< (MCLK_APBBMASK Mask) SERCOM */
+#define MCLK_APBBMASK_SERCOM(value)           (MCLK_APBBMASK_SERCOM_Msk & ((value) << MCLK_APBBMASK_SERCOM_Pos)) 
+#define MCLK_APBBMASK_TCC_Pos                 _U_(11)                                              /**< (MCLK_APBBMASK Position) TCCx APB Clock Enable */
+#define MCLK_APBBMASK_TCC_Msk                 (_U_(0x3) << MCLK_APBBMASK_TCC_Pos)                  /**< (MCLK_APBBMASK Mask) TCC */
+#define MCLK_APBBMASK_TCC(value)              (MCLK_APBBMASK_TCC_Msk & ((value) << MCLK_APBBMASK_TCC_Pos)) 
+#define MCLK_APBBMASK_TC_Pos                  _U_(13)                                              /**< (MCLK_APBBMASK Position) TC2 APB Clock Enable */
+#define MCLK_APBBMASK_TC_Msk                  (_U_(0x3) << MCLK_APBBMASK_TC_Pos)                   /**< (MCLK_APBBMASK Mask) TC */
+#define MCLK_APBBMASK_TC(value)               (MCLK_APBBMASK_TC_Msk & ((value) << MCLK_APBBMASK_TC_Pos)) 
+
+/* -------- MCLK_APBCMASK : (MCLK Offset: 0x1C) (R/W 32) APBC Mask -------- */
+#define MCLK_APBCMASK_RESETVALUE              _U_(0x2000)                                          /**<  (MCLK_APBCMASK) APBC Mask  Reset Value */
+
+#define MCLK_APBCMASK_TCC2_Pos                _U_(3)                                               /**< (MCLK_APBCMASK) TCC2 APB Clock Enable Position */
+#define MCLK_APBCMASK_TCC2_Msk                (_U_(0x1) << MCLK_APBCMASK_TCC2_Pos)                 /**< (MCLK_APBCMASK) TCC2 APB Clock Enable Mask */
+#define MCLK_APBCMASK_TCC2(value)             (MCLK_APBCMASK_TCC2_Msk & ((value) << MCLK_APBCMASK_TCC2_Pos))
+#define MCLK_APBCMASK_TCC3_Pos                _U_(4)                                               /**< (MCLK_APBCMASK) TCC3 APB Clock Enable Position */
+#define MCLK_APBCMASK_TCC3_Msk                (_U_(0x1) << MCLK_APBCMASK_TCC3_Pos)                 /**< (MCLK_APBCMASK) TCC3 APB Clock Enable Mask */
+#define MCLK_APBCMASK_TCC3(value)             (MCLK_APBCMASK_TCC3_Msk & ((value) << MCLK_APBCMASK_TCC3_Pos))
+#define MCLK_APBCMASK_TC4_Pos                 _U_(5)                                               /**< (MCLK_APBCMASK) TC4 APB Clock Enable Position */
+#define MCLK_APBCMASK_TC4_Msk                 (_U_(0x1) << MCLK_APBCMASK_TC4_Pos)                  /**< (MCLK_APBCMASK) TC4 APB Clock Enable Mask */
+#define MCLK_APBCMASK_TC4(value)              (MCLK_APBCMASK_TC4_Msk & ((value) << MCLK_APBCMASK_TC4_Pos))
+#define MCLK_APBCMASK_TC5_Pos                 _U_(6)                                               /**< (MCLK_APBCMASK) TC5 APB Clock Enable Position */
+#define MCLK_APBCMASK_TC5_Msk                 (_U_(0x1) << MCLK_APBCMASK_TC5_Pos)                  /**< (MCLK_APBCMASK) TC5 APB Clock Enable Mask */
+#define MCLK_APBCMASK_TC5(value)              (MCLK_APBCMASK_TC5_Msk & ((value) << MCLK_APBCMASK_TC5_Pos))
+#define MCLK_APBCMASK_PDEC_Pos                _U_(7)                                               /**< (MCLK_APBCMASK) PDEC APB Clock Enable Position */
+#define MCLK_APBCMASK_PDEC_Msk                (_U_(0x1) << MCLK_APBCMASK_PDEC_Pos)                 /**< (MCLK_APBCMASK) PDEC APB Clock Enable Mask */
+#define MCLK_APBCMASK_PDEC(value)             (MCLK_APBCMASK_PDEC_Msk & ((value) << MCLK_APBCMASK_PDEC_Pos))
+#define MCLK_APBCMASK_AC_Pos                  _U_(8)                                               /**< (MCLK_APBCMASK) AC APB Clock Enable Position */
+#define MCLK_APBCMASK_AC_Msk                  (_U_(0x1) << MCLK_APBCMASK_AC_Pos)                   /**< (MCLK_APBCMASK) AC APB Clock Enable Mask */
+#define MCLK_APBCMASK_AC(value)               (MCLK_APBCMASK_AC_Msk & ((value) << MCLK_APBCMASK_AC_Pos))
+#define MCLK_APBCMASK_AES_Pos                 _U_(9)                                               /**< (MCLK_APBCMASK) AES APB Clock Enable Position */
+#define MCLK_APBCMASK_AES_Msk                 (_U_(0x1) << MCLK_APBCMASK_AES_Pos)                  /**< (MCLK_APBCMASK) AES APB Clock Enable Mask */
+#define MCLK_APBCMASK_AES(value)              (MCLK_APBCMASK_AES_Msk & ((value) << MCLK_APBCMASK_AES_Pos))
+#define MCLK_APBCMASK_TRNG_Pos                _U_(10)                                              /**< (MCLK_APBCMASK) TRNG APB Clock Enable Position */
+#define MCLK_APBCMASK_TRNG_Msk                (_U_(0x1) << MCLK_APBCMASK_TRNG_Pos)                 /**< (MCLK_APBCMASK) TRNG APB Clock Enable Mask */
+#define MCLK_APBCMASK_TRNG(value)             (MCLK_APBCMASK_TRNG_Msk & ((value) << MCLK_APBCMASK_TRNG_Pos))
+#define MCLK_APBCMASK_ICM_Pos                 _U_(11)                                              /**< (MCLK_APBCMASK) ICM APB Clock Enable Position */
+#define MCLK_APBCMASK_ICM_Msk                 (_U_(0x1) << MCLK_APBCMASK_ICM_Pos)                  /**< (MCLK_APBCMASK) ICM APB Clock Enable Mask */
+#define MCLK_APBCMASK_ICM(value)              (MCLK_APBCMASK_ICM_Msk & ((value) << MCLK_APBCMASK_ICM_Pos))
+#define MCLK_APBCMASK_QSPI_Pos                _U_(13)                                              /**< (MCLK_APBCMASK) QSPI APB Clock Enable Position */
+#define MCLK_APBCMASK_QSPI_Msk                (_U_(0x1) << MCLK_APBCMASK_QSPI_Pos)                 /**< (MCLK_APBCMASK) QSPI APB Clock Enable Mask */
+#define MCLK_APBCMASK_QSPI(value)             (MCLK_APBCMASK_QSPI_Msk & ((value) << MCLK_APBCMASK_QSPI_Pos))
+#define MCLK_APBCMASK_CCL_Pos                 _U_(14)                                              /**< (MCLK_APBCMASK) CCL APB Clock Enable Position */
+#define MCLK_APBCMASK_CCL_Msk                 (_U_(0x1) << MCLK_APBCMASK_CCL_Pos)                  /**< (MCLK_APBCMASK) CCL APB Clock Enable Mask */
+#define MCLK_APBCMASK_CCL(value)              (MCLK_APBCMASK_CCL_Msk & ((value) << MCLK_APBCMASK_CCL_Pos))
+#define MCLK_APBCMASK_Msk                     _U_(0x00006FF8)                                      /**< (MCLK_APBCMASK) Register Mask  */
+
+#define MCLK_APBCMASK_TCC_Pos                 _U_(3)                                               /**< (MCLK_APBCMASK Position) TCC2 APB Clock Enable */
+#define MCLK_APBCMASK_TCC_Msk                 (_U_(0x3) << MCLK_APBCMASK_TCC_Pos)                  /**< (MCLK_APBCMASK Mask) TCC */
+#define MCLK_APBCMASK_TCC(value)              (MCLK_APBCMASK_TCC_Msk & ((value) << MCLK_APBCMASK_TCC_Pos)) 
+#define MCLK_APBCMASK_TC_Pos                  _U_(5)                                               /**< (MCLK_APBCMASK Position) TC4 APB Clock Enable */
+#define MCLK_APBCMASK_TC_Msk                  (_U_(0x3) << MCLK_APBCMASK_TC_Pos)                   /**< (MCLK_APBCMASK Mask) TC */
+#define MCLK_APBCMASK_TC(value)               (MCLK_APBCMASK_TC_Msk & ((value) << MCLK_APBCMASK_TC_Pos)) 
+
+/* -------- MCLK_APBDMASK : (MCLK Offset: 0x20) (R/W 32) APBD Mask -------- */
+#define MCLK_APBDMASK_RESETVALUE              _U_(0x00)                                            /**<  (MCLK_APBDMASK) APBD Mask  Reset Value */
+
+#define MCLK_APBDMASK_SERCOM4_Pos             _U_(0)                                               /**< (MCLK_APBDMASK) SERCOM4 APB Clock Enable Position */
+#define MCLK_APBDMASK_SERCOM4_Msk             (_U_(0x1) << MCLK_APBDMASK_SERCOM4_Pos)              /**< (MCLK_APBDMASK) SERCOM4 APB Clock Enable Mask */
+#define MCLK_APBDMASK_SERCOM4(value)          (MCLK_APBDMASK_SERCOM4_Msk & ((value) << MCLK_APBDMASK_SERCOM4_Pos))
+#define MCLK_APBDMASK_SERCOM5_Pos             _U_(1)                                               /**< (MCLK_APBDMASK) SERCOM5 APB Clock Enable Position */
+#define MCLK_APBDMASK_SERCOM5_Msk             (_U_(0x1) << MCLK_APBDMASK_SERCOM5_Pos)              /**< (MCLK_APBDMASK) SERCOM5 APB Clock Enable Mask */
+#define MCLK_APBDMASK_SERCOM5(value)          (MCLK_APBDMASK_SERCOM5_Msk & ((value) << MCLK_APBDMASK_SERCOM5_Pos))
+#define MCLK_APBDMASK_SERCOM6_Pos             _U_(2)                                               /**< (MCLK_APBDMASK) SERCOM6 APB Clock Enable Position */
+#define MCLK_APBDMASK_SERCOM6_Msk             (_U_(0x1) << MCLK_APBDMASK_SERCOM6_Pos)              /**< (MCLK_APBDMASK) SERCOM6 APB Clock Enable Mask */
+#define MCLK_APBDMASK_SERCOM6(value)          (MCLK_APBDMASK_SERCOM6_Msk & ((value) << MCLK_APBDMASK_SERCOM6_Pos))
+#define MCLK_APBDMASK_SERCOM7_Pos             _U_(3)                                               /**< (MCLK_APBDMASK) SERCOM7 APB Clock Enable Position */
+#define MCLK_APBDMASK_SERCOM7_Msk             (_U_(0x1) << MCLK_APBDMASK_SERCOM7_Pos)              /**< (MCLK_APBDMASK) SERCOM7 APB Clock Enable Mask */
+#define MCLK_APBDMASK_SERCOM7(value)          (MCLK_APBDMASK_SERCOM7_Msk & ((value) << MCLK_APBDMASK_SERCOM7_Pos))
+#define MCLK_APBDMASK_TCC4_Pos                _U_(4)                                               /**< (MCLK_APBDMASK) TCC4 APB Clock Enable Position */
+#define MCLK_APBDMASK_TCC4_Msk                (_U_(0x1) << MCLK_APBDMASK_TCC4_Pos)                 /**< (MCLK_APBDMASK) TCC4 APB Clock Enable Mask */
+#define MCLK_APBDMASK_TCC4(value)             (MCLK_APBDMASK_TCC4_Msk & ((value) << MCLK_APBDMASK_TCC4_Pos))
+#define MCLK_APBDMASK_TC6_Pos                 _U_(5)                                               /**< (MCLK_APBDMASK) TC6 APB Clock Enable Position */
+#define MCLK_APBDMASK_TC6_Msk                 (_U_(0x1) << MCLK_APBDMASK_TC6_Pos)                  /**< (MCLK_APBDMASK) TC6 APB Clock Enable Mask */
+#define MCLK_APBDMASK_TC6(value)              (MCLK_APBDMASK_TC6_Msk & ((value) << MCLK_APBDMASK_TC6_Pos))
+#define MCLK_APBDMASK_TC7_Pos                 _U_(6)                                               /**< (MCLK_APBDMASK) TC7 APB Clock Enable Position */
+#define MCLK_APBDMASK_TC7_Msk                 (_U_(0x1) << MCLK_APBDMASK_TC7_Pos)                  /**< (MCLK_APBDMASK) TC7 APB Clock Enable Mask */
+#define MCLK_APBDMASK_TC7(value)              (MCLK_APBDMASK_TC7_Msk & ((value) << MCLK_APBDMASK_TC7_Pos))
+#define MCLK_APBDMASK_ADC0_Pos                _U_(7)                                               /**< (MCLK_APBDMASK) ADC0 APB Clock Enable Position */
+#define MCLK_APBDMASK_ADC0_Msk                (_U_(0x1) << MCLK_APBDMASK_ADC0_Pos)                 /**< (MCLK_APBDMASK) ADC0 APB Clock Enable Mask */
+#define MCLK_APBDMASK_ADC0(value)             (MCLK_APBDMASK_ADC0_Msk & ((value) << MCLK_APBDMASK_ADC0_Pos))
+#define MCLK_APBDMASK_ADC1_Pos                _U_(8)                                               /**< (MCLK_APBDMASK) ADC1 APB Clock Enable Position */
+#define MCLK_APBDMASK_ADC1_Msk                (_U_(0x1) << MCLK_APBDMASK_ADC1_Pos)                 /**< (MCLK_APBDMASK) ADC1 APB Clock Enable Mask */
+#define MCLK_APBDMASK_ADC1(value)             (MCLK_APBDMASK_ADC1_Msk & ((value) << MCLK_APBDMASK_ADC1_Pos))
+#define MCLK_APBDMASK_DAC_Pos                 _U_(9)                                               /**< (MCLK_APBDMASK) DAC APB Clock Enable Position */
+#define MCLK_APBDMASK_DAC_Msk                 (_U_(0x1) << MCLK_APBDMASK_DAC_Pos)                  /**< (MCLK_APBDMASK) DAC APB Clock Enable Mask */
+#define MCLK_APBDMASK_DAC(value)              (MCLK_APBDMASK_DAC_Msk & ((value) << MCLK_APBDMASK_DAC_Pos))
+#define MCLK_APBDMASK_I2S_Pos                 _U_(10)                                              /**< (MCLK_APBDMASK) I2S APB Clock Enable Position */
+#define MCLK_APBDMASK_I2S_Msk                 (_U_(0x1) << MCLK_APBDMASK_I2S_Pos)                  /**< (MCLK_APBDMASK) I2S APB Clock Enable Mask */
+#define MCLK_APBDMASK_I2S(value)              (MCLK_APBDMASK_I2S_Msk & ((value) << MCLK_APBDMASK_I2S_Pos))
+#define MCLK_APBDMASK_PCC_Pos                 _U_(11)                                              /**< (MCLK_APBDMASK) PCC APB Clock Enable Position */
+#define MCLK_APBDMASK_PCC_Msk                 (_U_(0x1) << MCLK_APBDMASK_PCC_Pos)                  /**< (MCLK_APBDMASK) PCC APB Clock Enable Mask */
+#define MCLK_APBDMASK_PCC(value)              (MCLK_APBDMASK_PCC_Msk & ((value) << MCLK_APBDMASK_PCC_Pos))
+#define MCLK_APBDMASK_Msk                     _U_(0x00000FFF)                                      /**< (MCLK_APBDMASK) Register Mask  */
+
+#define MCLK_APBDMASK_SERCOM_Pos              _U_(0)                                               /**< (MCLK_APBDMASK Position) SERCOM4 APB Clock Enable */
+#define MCLK_APBDMASK_SERCOM_Msk              (_U_(0xF) << MCLK_APBDMASK_SERCOM_Pos)               /**< (MCLK_APBDMASK Mask) SERCOM */
+#define MCLK_APBDMASK_SERCOM(value)           (MCLK_APBDMASK_SERCOM_Msk & ((value) << MCLK_APBDMASK_SERCOM_Pos)) 
+#define MCLK_APBDMASK_TCC_Pos                 _U_(4)                                               /**< (MCLK_APBDMASK Position) TCC4 APB Clock Enable */
+#define MCLK_APBDMASK_TCC_Msk                 (_U_(0x1) << MCLK_APBDMASK_TCC_Pos)                  /**< (MCLK_APBDMASK Mask) TCC */
+#define MCLK_APBDMASK_TCC(value)              (MCLK_APBDMASK_TCC_Msk & ((value) << MCLK_APBDMASK_TCC_Pos)) 
+#define MCLK_APBDMASK_TC_Pos                  _U_(5)                                               /**< (MCLK_APBDMASK Position) TC6 APB Clock Enable */
+#define MCLK_APBDMASK_TC_Msk                  (_U_(0x3) << MCLK_APBDMASK_TC_Pos)                   /**< (MCLK_APBDMASK Mask) TC */
+#define MCLK_APBDMASK_TC(value)               (MCLK_APBDMASK_TC_Msk & ((value) << MCLK_APBDMASK_TC_Pos)) 
+#define MCLK_APBDMASK_ADC_Pos                 _U_(7)                                               /**< (MCLK_APBDMASK Position) ADCx APB Clock Enable */
+#define MCLK_APBDMASK_ADC_Msk                 (_U_(0x3) << MCLK_APBDMASK_ADC_Pos)                  /**< (MCLK_APBDMASK Mask) ADC */
+#define MCLK_APBDMASK_ADC(value)              (MCLK_APBDMASK_ADC_Msk & ((value) << MCLK_APBDMASK_ADC_Pos)) 
+
+/** \brief MCLK register offsets definitions */
+#define MCLK_INTENCLR_REG_OFST         (0x01)              /**< (MCLK_INTENCLR) Interrupt Enable Clear Offset */
+#define MCLK_INTENSET_REG_OFST         (0x02)              /**< (MCLK_INTENSET) Interrupt Enable Set Offset */
+#define MCLK_INTFLAG_REG_OFST          (0x03)              /**< (MCLK_INTFLAG) Interrupt Flag Status and Clear Offset */
+#define MCLK_HSDIV_REG_OFST            (0x04)              /**< (MCLK_HSDIV) HS Clock Division Offset */
+#define MCLK_CPUDIV_REG_OFST           (0x05)              /**< (MCLK_CPUDIV) CPU Clock Division Offset */
+#define MCLK_AHBMASK_REG_OFST          (0x10)              /**< (MCLK_AHBMASK) AHB Mask Offset */
+#define MCLK_APBAMASK_REG_OFST         (0x14)              /**< (MCLK_APBAMASK) APBA Mask Offset */
+#define MCLK_APBBMASK_REG_OFST         (0x18)              /**< (MCLK_APBBMASK) APBB Mask Offset */
+#define MCLK_APBCMASK_REG_OFST         (0x1C)              /**< (MCLK_APBCMASK) APBC Mask Offset */
+#define MCLK_APBDMASK_REG_OFST         (0x20)              /**< (MCLK_APBDMASK) APBD Mask Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief MCLK register API structure */
+typedef struct
+{  /* Main Clock */
+  __I   uint8_t                        Reserved1[0x01];
+  __IO  uint8_t                        MCLK_INTENCLR;      /**< Offset: 0x01 (R/W  8) Interrupt Enable Clear */
+  __IO  uint8_t                        MCLK_INTENSET;      /**< Offset: 0x02 (R/W  8) Interrupt Enable Set */
+  __IO  uint8_t                        MCLK_INTFLAG;       /**< Offset: 0x03 (R/W  8) Interrupt Flag Status and Clear */
+  __I   uint8_t                        MCLK_HSDIV;         /**< Offset: 0x04 (R/   8) HS Clock Division */
+  __IO  uint8_t                        MCLK_CPUDIV;        /**< Offset: 0x05 (R/W  8) CPU Clock Division */
+  __I   uint8_t                        Reserved2[0x0A];
+  __IO  uint32_t                       MCLK_AHBMASK;       /**< Offset: 0x10 (R/W  32) AHB Mask */
+  __IO  uint32_t                       MCLK_APBAMASK;      /**< Offset: 0x14 (R/W  32) APBA Mask */
+  __IO  uint32_t                       MCLK_APBBMASK;      /**< Offset: 0x18 (R/W  32) APBB Mask */
+  __IO  uint32_t                       MCLK_APBCMASK;      /**< Offset: 0x1C (R/W  32) APBC Mask */
+  __IO  uint32_t                       MCLK_APBDMASK;      /**< Offset: 0x20 (R/W  32) APBD Mask */
+} mclk_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _SAMD51_MCLK_COMPONENT_H_ */
Index: /asp_wio_terminal/trunk/target/samd51_gcc/lib/osc32kctrl.h
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/lib/osc32kctrl.h	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/lib/osc32kctrl.h	(revision 460)
@@ -0,0 +1,222 @@
+/**
+ * \brief Component description for OSC32KCTRL
+ *
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * Subject to your compliance with these terms, you may use Microchip software and any derivatives
+ * exclusively with Microchip products. It is your responsibility to comply with third party license
+ * terms applicable to your use of third party software (including open source software) that may
+ * accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
+ * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
+ * FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
+ * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
+ * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ */
+
+/* file generated from device description version 2020-03-12T17:26:00Z */
+#ifndef _SAMD51_OSC32KCTRL_COMPONENT_H_
+#define _SAMD51_OSC32KCTRL_COMPONENT_H_
+
+/* ************************************************************************** */
+/*   SOFTWARE API DEFINITION FOR OSC32KCTRL                                   */
+/* ************************************************************************** */
+
+/* -------- OSC32KCTRL_INTENCLR : (OSC32KCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
+#define OSC32KCTRL_INTENCLR_RESETVALUE        _U_(0x00)                                            /**<  (OSC32KCTRL_INTENCLR) Interrupt Enable Clear  Reset Value */
+
+#define OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos    _U_(0)                                               /**< (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable Position */
+#define OSC32KCTRL_INTENCLR_XOSC32KRDY_Msk    (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos)     /**< (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable Mask */
+#define OSC32KCTRL_INTENCLR_XOSC32KRDY(value) (OSC32KCTRL_INTENCLR_XOSC32KRDY_Msk & ((value) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos))
+#define OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos   _U_(2)                                               /**< (OSC32KCTRL_INTENCLR) XOSC32K Clock Failure Detector Interrupt Enable Position */
+#define OSC32KCTRL_INTENCLR_XOSC32KFAIL_Msk   (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos)    /**< (OSC32KCTRL_INTENCLR) XOSC32K Clock Failure Detector Interrupt Enable Mask */
+#define OSC32KCTRL_INTENCLR_XOSC32KFAIL(value) (OSC32KCTRL_INTENCLR_XOSC32KFAIL_Msk & ((value) << OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos))
+#define OSC32KCTRL_INTENCLR_Msk               _U_(0x00000005)                                      /**< (OSC32KCTRL_INTENCLR) Register Mask  */
+
+
+/* -------- OSC32KCTRL_INTENSET : (OSC32KCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
+#define OSC32KCTRL_INTENSET_RESETVALUE        _U_(0x00)                                            /**<  (OSC32KCTRL_INTENSET) Interrupt Enable Set  Reset Value */
+
+#define OSC32KCTRL_INTENSET_XOSC32KRDY_Pos    _U_(0)                                               /**< (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable Position */
+#define OSC32KCTRL_INTENSET_XOSC32KRDY_Msk    (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos)     /**< (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable Mask */
+#define OSC32KCTRL_INTENSET_XOSC32KRDY(value) (OSC32KCTRL_INTENSET_XOSC32KRDY_Msk & ((value) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos))
+#define OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos   _U_(2)                                               /**< (OSC32KCTRL_INTENSET) XOSC32K Clock Failure Detector Interrupt Enable Position */
+#define OSC32KCTRL_INTENSET_XOSC32KFAIL_Msk   (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos)    /**< (OSC32KCTRL_INTENSET) XOSC32K Clock Failure Detector Interrupt Enable Mask */
+#define OSC32KCTRL_INTENSET_XOSC32KFAIL(value) (OSC32KCTRL_INTENSET_XOSC32KFAIL_Msk & ((value) << OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos))
+#define OSC32KCTRL_INTENSET_Msk               _U_(0x00000005)                                      /**< (OSC32KCTRL_INTENSET) Register Mask  */
+
+
+/* -------- OSC32KCTRL_INTFLAG : (OSC32KCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
+#define OSC32KCTRL_INTFLAG_RESETVALUE         _U_(0x00)                                            /**<  (OSC32KCTRL_INTFLAG) Interrupt Flag Status and Clear  Reset Value */
+
+#define OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos     _U_(0)                                               /**< (OSC32KCTRL_INTFLAG) XOSC32K Ready Position */
+#define OSC32KCTRL_INTFLAG_XOSC32KRDY_Msk     (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos)      /**< (OSC32KCTRL_INTFLAG) XOSC32K Ready Mask */
+#define OSC32KCTRL_INTFLAG_XOSC32KRDY(value)  (OSC32KCTRL_INTFLAG_XOSC32KRDY_Msk & ((value) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos))
+#define OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos    _U_(2)                                               /**< (OSC32KCTRL_INTFLAG) XOSC32K Clock Failure Detector Position */
+#define OSC32KCTRL_INTFLAG_XOSC32KFAIL_Msk    (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos)     /**< (OSC32KCTRL_INTFLAG) XOSC32K Clock Failure Detector Mask */
+#define OSC32KCTRL_INTFLAG_XOSC32KFAIL(value) (OSC32KCTRL_INTFLAG_XOSC32KFAIL_Msk & ((value) << OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos))
+#define OSC32KCTRL_INTFLAG_Msk                _U_(0x00000005)                                      /**< (OSC32KCTRL_INTFLAG) Register Mask  */
+
+
+/* -------- OSC32KCTRL_STATUS : (OSC32KCTRL Offset: 0x0C) ( R/ 32) Power and Clocks Status -------- */
+#define OSC32KCTRL_STATUS_RESETVALUE          _U_(0x00)                                            /**<  (OSC32KCTRL_STATUS) Power and Clocks Status  Reset Value */
+
+#define OSC32KCTRL_STATUS_XOSC32KRDY_Pos      _U_(0)                                               /**< (OSC32KCTRL_STATUS) XOSC32K Ready Position */
+#define OSC32KCTRL_STATUS_XOSC32KRDY_Msk      (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos)       /**< (OSC32KCTRL_STATUS) XOSC32K Ready Mask */
+#define OSC32KCTRL_STATUS_XOSC32KRDY(value)   (OSC32KCTRL_STATUS_XOSC32KRDY_Msk & ((value) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos))
+#define OSC32KCTRL_STATUS_XOSC32KFAIL_Pos     _U_(2)                                               /**< (OSC32KCTRL_STATUS) XOSC32K Clock Failure Detector Position */
+#define OSC32KCTRL_STATUS_XOSC32KFAIL_Msk     (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KFAIL_Pos)      /**< (OSC32KCTRL_STATUS) XOSC32K Clock Failure Detector Mask */
+#define OSC32KCTRL_STATUS_XOSC32KFAIL(value)  (OSC32KCTRL_STATUS_XOSC32KFAIL_Msk & ((value) << OSC32KCTRL_STATUS_XOSC32KFAIL_Pos))
+#define OSC32KCTRL_STATUS_XOSC32KSW_Pos       _U_(3)                                               /**< (OSC32KCTRL_STATUS) XOSC32K Clock switch Position */
+#define OSC32KCTRL_STATUS_XOSC32KSW_Msk       (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KSW_Pos)        /**< (OSC32KCTRL_STATUS) XOSC32K Clock switch Mask */
+#define OSC32KCTRL_STATUS_XOSC32KSW(value)    (OSC32KCTRL_STATUS_XOSC32KSW_Msk & ((value) << OSC32KCTRL_STATUS_XOSC32KSW_Pos))
+#define OSC32KCTRL_STATUS_Msk                 _U_(0x0000000D)                                      /**< (OSC32KCTRL_STATUS) Register Mask  */
+
+
+/* -------- OSC32KCTRL_RTCCTRL : (OSC32KCTRL Offset: 0x10) (R/W 8) RTC Clock Selection -------- */
+#define OSC32KCTRL_RTCCTRL_RESETVALUE         _U_(0x00)                                            /**<  (OSC32KCTRL_RTCCTRL) RTC Clock Selection  Reset Value */
+
+#define OSC32KCTRL_RTCCTRL_RTCSEL_Pos         _U_(0)                                               /**< (OSC32KCTRL_RTCCTRL) RTC Clock Selection Position */
+#define OSC32KCTRL_RTCCTRL_RTCSEL_Msk         (_U_(0x7) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)          /**< (OSC32KCTRL_RTCCTRL) RTC Clock Selection Mask */
+#define OSC32KCTRL_RTCCTRL_RTCSEL(value)      (OSC32KCTRL_RTCCTRL_RTCSEL_Msk & ((value) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos))
+#define   OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val _U_(0x0)                                             /**< (OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator  */
+#define   OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val _U_(0x1)                                             /**< (OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator  */
+#define   OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val _U_(0x4)                                             /**< (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator  */
+#define   OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val _U_(0x5)                                             /**< (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator  */
+#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K       (OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) /**< (OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator Position  */
+#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K      (OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) /**< (OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator Position  */
+#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K      (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) /**< (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator Position  */
+#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K     (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) /**< (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator Position  */
+#define OSC32KCTRL_RTCCTRL_Msk                _U_(0x07)                                            /**< (OSC32KCTRL_RTCCTRL) Register Mask  */
+
+
+/* -------- OSC32KCTRL_XOSC32K : (OSC32KCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
+#define OSC32KCTRL_XOSC32K_RESETVALUE         _U_(0x2080)                                          /**<  (OSC32KCTRL_XOSC32K) 32kHz External Crystal Oscillator (XOSC32K) Control  Reset Value */
+
+#define OSC32KCTRL_XOSC32K_ENABLE_Pos         _U_(1)                                               /**< (OSC32KCTRL_XOSC32K) Oscillator Enable Position */
+#define OSC32KCTRL_XOSC32K_ENABLE_Msk         (_U_(0x1) << OSC32KCTRL_XOSC32K_ENABLE_Pos)          /**< (OSC32KCTRL_XOSC32K) Oscillator Enable Mask */
+#define OSC32KCTRL_XOSC32K_ENABLE(value)      (OSC32KCTRL_XOSC32K_ENABLE_Msk & ((value) << OSC32KCTRL_XOSC32K_ENABLE_Pos))
+#define OSC32KCTRL_XOSC32K_XTALEN_Pos         _U_(2)                                               /**< (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable Position */
+#define OSC32KCTRL_XOSC32K_XTALEN_Msk         (_U_(0x1) << OSC32KCTRL_XOSC32K_XTALEN_Pos)          /**< (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable Mask */
+#define OSC32KCTRL_XOSC32K_XTALEN(value)      (OSC32KCTRL_XOSC32K_XTALEN_Msk & ((value) << OSC32KCTRL_XOSC32K_XTALEN_Pos))
+#define OSC32KCTRL_XOSC32K_EN32K_Pos          _U_(3)                                               /**< (OSC32KCTRL_XOSC32K) 32kHz Output Enable Position */
+#define OSC32KCTRL_XOSC32K_EN32K_Msk          (_U_(0x1) << OSC32KCTRL_XOSC32K_EN32K_Pos)           /**< (OSC32KCTRL_XOSC32K) 32kHz Output Enable Mask */
+#define OSC32KCTRL_XOSC32K_EN32K(value)       (OSC32KCTRL_XOSC32K_EN32K_Msk & ((value) << OSC32KCTRL_XOSC32K_EN32K_Pos))
+#define OSC32KCTRL_XOSC32K_EN1K_Pos           _U_(4)                                               /**< (OSC32KCTRL_XOSC32K) 1kHz Output Enable Position */
+#define OSC32KCTRL_XOSC32K_EN1K_Msk           (_U_(0x1) << OSC32KCTRL_XOSC32K_EN1K_Pos)            /**< (OSC32KCTRL_XOSC32K) 1kHz Output Enable Mask */
+#define OSC32KCTRL_XOSC32K_EN1K(value)        (OSC32KCTRL_XOSC32K_EN1K_Msk & ((value) << OSC32KCTRL_XOSC32K_EN1K_Pos))
+#define OSC32KCTRL_XOSC32K_RUNSTDBY_Pos       _U_(6)                                               /**< (OSC32KCTRL_XOSC32K) Run in Standby Position */
+#define OSC32KCTRL_XOSC32K_RUNSTDBY_Msk       (_U_(0x1) << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos)        /**< (OSC32KCTRL_XOSC32K) Run in Standby Mask */
+#define OSC32KCTRL_XOSC32K_RUNSTDBY(value)    (OSC32KCTRL_XOSC32K_RUNSTDBY_Msk & ((value) << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos))
+#define OSC32KCTRL_XOSC32K_ONDEMAND_Pos       _U_(7)                                               /**< (OSC32KCTRL_XOSC32K) On Demand Control Position */
+#define OSC32KCTRL_XOSC32K_ONDEMAND_Msk       (_U_(0x1) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos)        /**< (OSC32KCTRL_XOSC32K) On Demand Control Mask */
+#define OSC32KCTRL_XOSC32K_ONDEMAND(value)    (OSC32KCTRL_XOSC32K_ONDEMAND_Msk & ((value) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos))
+#define OSC32KCTRL_XOSC32K_STARTUP_Pos        _U_(8)                                               /**< (OSC32KCTRL_XOSC32K) Oscillator Start-Up Time Position */
+#define OSC32KCTRL_XOSC32K_STARTUP_Msk        (_U_(0x7) << OSC32KCTRL_XOSC32K_STARTUP_Pos)         /**< (OSC32KCTRL_XOSC32K) Oscillator Start-Up Time Mask */
+#define OSC32KCTRL_XOSC32K_STARTUP(value)     (OSC32KCTRL_XOSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_XOSC32K_STARTUP_Pos))
+#define   OSC32KCTRL_XOSC32K_STARTUP_CYCLE2048_Val _U_(0x0)                                             /**< (OSC32KCTRL_XOSC32K) 62.6 ms  */
+#define   OSC32KCTRL_XOSC32K_STARTUP_CYCLE4096_Val _U_(0x1)                                             /**< (OSC32KCTRL_XOSC32K) 125 ms  */
+#define   OSC32KCTRL_XOSC32K_STARTUP_CYCLE16384_Val _U_(0x2)                                             /**< (OSC32KCTRL_XOSC32K) 500 ms  */
+#define   OSC32KCTRL_XOSC32K_STARTUP_CYCLE32768_Val _U_(0x3)                                             /**< (OSC32KCTRL_XOSC32K) 1000 ms  */
+#define   OSC32KCTRL_XOSC32K_STARTUP_CYCLE65536_Val _U_(0x4)                                             /**< (OSC32KCTRL_XOSC32K) 2000 ms  */
+#define   OSC32KCTRL_XOSC32K_STARTUP_CYCLE131072_Val _U_(0x5)                                             /**< (OSC32KCTRL_XOSC32K) 4000 ms  */
+#define   OSC32KCTRL_XOSC32K_STARTUP_CYCLE262144_Val _U_(0x6)                                             /**< (OSC32KCTRL_XOSC32K) 8000 ms  */
+#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE2048  (OSC32KCTRL_XOSC32K_STARTUP_CYCLE2048_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /**< (OSC32KCTRL_XOSC32K) 62.6 ms Position  */
+#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE4096  (OSC32KCTRL_XOSC32K_STARTUP_CYCLE4096_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /**< (OSC32KCTRL_XOSC32K) 125 ms Position  */
+#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE16384 (OSC32KCTRL_XOSC32K_STARTUP_CYCLE16384_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /**< (OSC32KCTRL_XOSC32K) 500 ms Position  */
+#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE32768 (OSC32KCTRL_XOSC32K_STARTUP_CYCLE32768_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /**< (OSC32KCTRL_XOSC32K) 1000 ms Position  */
+#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE65536 (OSC32KCTRL_XOSC32K_STARTUP_CYCLE65536_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /**< (OSC32KCTRL_XOSC32K) 2000 ms Position  */
+#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE131072 (OSC32KCTRL_XOSC32K_STARTUP_CYCLE131072_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /**< (OSC32KCTRL_XOSC32K) 4000 ms Position  */
+#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE262144 (OSC32KCTRL_XOSC32K_STARTUP_CYCLE262144_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /**< (OSC32KCTRL_XOSC32K) 8000 ms Position  */
+#define OSC32KCTRL_XOSC32K_WRTLOCK_Pos        _U_(12)                                              /**< (OSC32KCTRL_XOSC32K) Write Lock Position */
+#define OSC32KCTRL_XOSC32K_WRTLOCK_Msk        (_U_(0x1) << OSC32KCTRL_XOSC32K_WRTLOCK_Pos)         /**< (OSC32KCTRL_XOSC32K) Write Lock Mask */
+#define OSC32KCTRL_XOSC32K_WRTLOCK(value)     (OSC32KCTRL_XOSC32K_WRTLOCK_Msk & ((value) << OSC32KCTRL_XOSC32K_WRTLOCK_Pos))
+#define OSC32KCTRL_XOSC32K_CGM_Pos            _U_(13)                                              /**< (OSC32KCTRL_XOSC32K) Control Gain Mode Position */
+#define OSC32KCTRL_XOSC32K_CGM_Msk            (_U_(0x3) << OSC32KCTRL_XOSC32K_CGM_Pos)             /**< (OSC32KCTRL_XOSC32K) Control Gain Mode Mask */
+#define OSC32KCTRL_XOSC32K_CGM(value)         (OSC32KCTRL_XOSC32K_CGM_Msk & ((value) << OSC32KCTRL_XOSC32K_CGM_Pos))
+#define   OSC32KCTRL_XOSC32K_CGM_XT_Val       _U_(0x1)                                             /**< (OSC32KCTRL_XOSC32K) Standard mode  */
+#define   OSC32KCTRL_XOSC32K_CGM_HS_Val       _U_(0x2)                                             /**< (OSC32KCTRL_XOSC32K) High Speed mode  */
+#define OSC32KCTRL_XOSC32K_CGM_XT             (OSC32KCTRL_XOSC32K_CGM_XT_Val << OSC32KCTRL_XOSC32K_CGM_Pos) /**< (OSC32KCTRL_XOSC32K) Standard mode Position  */
+#define OSC32KCTRL_XOSC32K_CGM_HS             (OSC32KCTRL_XOSC32K_CGM_HS_Val << OSC32KCTRL_XOSC32K_CGM_Pos) /**< (OSC32KCTRL_XOSC32K) High Speed mode Position  */
+#define OSC32KCTRL_XOSC32K_Msk                _U_(0x77DE)                                          /**< (OSC32KCTRL_XOSC32K) Register Mask  */
+
+
+/* -------- OSC32KCTRL_CFDCTRL : (OSC32KCTRL Offset: 0x16) (R/W 8) Clock Failure Detector Control -------- */
+#define OSC32KCTRL_CFDCTRL_RESETVALUE         _U_(0x00)                                            /**<  (OSC32KCTRL_CFDCTRL) Clock Failure Detector Control  Reset Value */
+
+#define OSC32KCTRL_CFDCTRL_CFDEN_Pos          _U_(0)                                               /**< (OSC32KCTRL_CFDCTRL) Clock Failure Detector Enable Position */
+#define OSC32KCTRL_CFDCTRL_CFDEN_Msk          (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDEN_Pos)           /**< (OSC32KCTRL_CFDCTRL) Clock Failure Detector Enable Mask */
+#define OSC32KCTRL_CFDCTRL_CFDEN(value)       (OSC32KCTRL_CFDCTRL_CFDEN_Msk & ((value) << OSC32KCTRL_CFDCTRL_CFDEN_Pos))
+#define OSC32KCTRL_CFDCTRL_SWBACK_Pos         _U_(1)                                               /**< (OSC32KCTRL_CFDCTRL) Clock Switch Back Position */
+#define OSC32KCTRL_CFDCTRL_SWBACK_Msk         (_U_(0x1) << OSC32KCTRL_CFDCTRL_SWBACK_Pos)          /**< (OSC32KCTRL_CFDCTRL) Clock Switch Back Mask */
+#define OSC32KCTRL_CFDCTRL_SWBACK(value)      (OSC32KCTRL_CFDCTRL_SWBACK_Msk & ((value) << OSC32KCTRL_CFDCTRL_SWBACK_Pos))
+#define OSC32KCTRL_CFDCTRL_CFDPRESC_Pos       _U_(2)                                               /**< (OSC32KCTRL_CFDCTRL) Clock Failure Detector Prescaler Position */
+#define OSC32KCTRL_CFDCTRL_CFDPRESC_Msk       (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos)        /**< (OSC32KCTRL_CFDCTRL) Clock Failure Detector Prescaler Mask */
+#define OSC32KCTRL_CFDCTRL_CFDPRESC(value)    (OSC32KCTRL_CFDCTRL_CFDPRESC_Msk & ((value) << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos))
+#define OSC32KCTRL_CFDCTRL_Msk                _U_(0x07)                                            /**< (OSC32KCTRL_CFDCTRL) Register Mask  */
+
+
+/* -------- OSC32KCTRL_EVCTRL : (OSC32KCTRL Offset: 0x17) (R/W 8) Event Control -------- */
+#define OSC32KCTRL_EVCTRL_RESETVALUE          _U_(0x00)                                            /**<  (OSC32KCTRL_EVCTRL) Event Control  Reset Value */
+
+#define OSC32KCTRL_EVCTRL_CFDEO_Pos           _U_(0)                                               /**< (OSC32KCTRL_EVCTRL) Clock Failure Detector Event Output Enable Position */
+#define OSC32KCTRL_EVCTRL_CFDEO_Msk           (_U_(0x1) << OSC32KCTRL_EVCTRL_CFDEO_Pos)            /**< (OSC32KCTRL_EVCTRL) Clock Failure Detector Event Output Enable Mask */
+#define OSC32KCTRL_EVCTRL_CFDEO(value)        (OSC32KCTRL_EVCTRL_CFDEO_Msk & ((value) << OSC32KCTRL_EVCTRL_CFDEO_Pos))
+#define OSC32KCTRL_EVCTRL_Msk                 _U_(0x01)                                            /**< (OSC32KCTRL_EVCTRL) Register Mask  */
+
+
+/* -------- OSC32KCTRL_OSCULP32K : (OSC32KCTRL Offset: 0x1C) (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
+#define OSC32KCTRL_OSCULP32K_RESETVALUE       _U_(0x00)                                            /**<  (OSC32KCTRL_OSCULP32K) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control  Reset Value */
+
+#define OSC32KCTRL_OSCULP32K_EN32K_Pos        _U_(1)                                               /**< (OSC32KCTRL_OSCULP32K) Enable Out 32k Position */
+#define OSC32KCTRL_OSCULP32K_EN32K_Msk        (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN32K_Pos)         /**< (OSC32KCTRL_OSCULP32K) Enable Out 32k Mask */
+#define OSC32KCTRL_OSCULP32K_EN32K(value)     (OSC32KCTRL_OSCULP32K_EN32K_Msk & ((value) << OSC32KCTRL_OSCULP32K_EN32K_Pos))
+#define OSC32KCTRL_OSCULP32K_EN1K_Pos         _U_(2)                                               /**< (OSC32KCTRL_OSCULP32K) Enable Out 1k Position */
+#define OSC32KCTRL_OSCULP32K_EN1K_Msk         (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN1K_Pos)          /**< (OSC32KCTRL_OSCULP32K) Enable Out 1k Mask */
+#define OSC32KCTRL_OSCULP32K_EN1K(value)      (OSC32KCTRL_OSCULP32K_EN1K_Msk & ((value) << OSC32KCTRL_OSCULP32K_EN1K_Pos))
+#define OSC32KCTRL_OSCULP32K_CALIB_Pos        _U_(8)                                               /**< (OSC32KCTRL_OSCULP32K) Oscillator Calibration Position */
+#define OSC32KCTRL_OSCULP32K_CALIB_Msk        (_U_(0x3F) << OSC32KCTRL_OSCULP32K_CALIB_Pos)        /**< (OSC32KCTRL_OSCULP32K) Oscillator Calibration Mask */
+#define OSC32KCTRL_OSCULP32K_CALIB(value)     (OSC32KCTRL_OSCULP32K_CALIB_Msk & ((value) << OSC32KCTRL_OSCULP32K_CALIB_Pos))
+#define OSC32KCTRL_OSCULP32K_WRTLOCK_Pos      _U_(15)                                              /**< (OSC32KCTRL_OSCULP32K) Write Lock Position */
+#define OSC32KCTRL_OSCULP32K_WRTLOCK_Msk      (_U_(0x1) << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos)       /**< (OSC32KCTRL_OSCULP32K) Write Lock Mask */
+#define OSC32KCTRL_OSCULP32K_WRTLOCK(value)   (OSC32KCTRL_OSCULP32K_WRTLOCK_Msk & ((value) << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos))
+#define OSC32KCTRL_OSCULP32K_Msk              _U_(0x0000BF06)                                      /**< (OSC32KCTRL_OSCULP32K) Register Mask  */
+
+
+/** \brief OSC32KCTRL register offsets definitions */
+#define OSC32KCTRL_INTENCLR_REG_OFST   (0x00)              /**< (OSC32KCTRL_INTENCLR) Interrupt Enable Clear Offset */
+#define OSC32KCTRL_INTENSET_REG_OFST   (0x04)              /**< (OSC32KCTRL_INTENSET) Interrupt Enable Set Offset */
+#define OSC32KCTRL_INTFLAG_REG_OFST    (0x08)              /**< (OSC32KCTRL_INTFLAG) Interrupt Flag Status and Clear Offset */
+#define OSC32KCTRL_STATUS_REG_OFST     (0x0C)              /**< (OSC32KCTRL_STATUS) Power and Clocks Status Offset */
+#define OSC32KCTRL_RTCCTRL_REG_OFST    (0x10)              /**< (OSC32KCTRL_RTCCTRL) RTC Clock Selection Offset */
+#define OSC32KCTRL_XOSC32K_REG_OFST    (0x14)              /**< (OSC32KCTRL_XOSC32K) 32kHz External Crystal Oscillator (XOSC32K) Control Offset */
+#define OSC32KCTRL_CFDCTRL_REG_OFST    (0x16)              /**< (OSC32KCTRL_CFDCTRL) Clock Failure Detector Control Offset */
+#define OSC32KCTRL_EVCTRL_REG_OFST     (0x17)              /**< (OSC32KCTRL_EVCTRL) Event Control Offset */
+#define OSC32KCTRL_OSCULP32K_REG_OFST  (0x1C)              /**< (OSC32KCTRL_OSCULP32K) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief OSC32KCTRL register API structure */
+typedef struct
+{  /* 32kHz Oscillators Control */
+  __IO  uint32_t                       OSC32KCTRL_INTENCLR; /**< Offset: 0x00 (R/W  32) Interrupt Enable Clear */
+  __IO  uint32_t                       OSC32KCTRL_INTENSET; /**< Offset: 0x04 (R/W  32) Interrupt Enable Set */
+  __IO  uint32_t                       OSC32KCTRL_INTFLAG; /**< Offset: 0x08 (R/W  32) Interrupt Flag Status and Clear */
+  __I   uint32_t                       OSC32KCTRL_STATUS;  /**< Offset: 0x0C (R/   32) Power and Clocks Status */
+  __IO  uint8_t                        OSC32KCTRL_RTCCTRL; /**< Offset: 0x10 (R/W  8) RTC Clock Selection */
+  __I   uint8_t                        Reserved1[0x03];
+  __IO  uint16_t                       OSC32KCTRL_XOSC32K; /**< Offset: 0x14 (R/W  16) 32kHz External Crystal Oscillator (XOSC32K) Control */
+  __IO  uint8_t                        OSC32KCTRL_CFDCTRL; /**< Offset: 0x16 (R/W  8) Clock Failure Detector Control */
+  __IO  uint8_t                        OSC32KCTRL_EVCTRL;  /**< Offset: 0x17 (R/W  8) Event Control */
+  __I   uint8_t                        Reserved2[0x04];
+  __IO  uint32_t                       OSC32KCTRL_OSCULP32K; /**< Offset: 0x1C (R/W  32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+} osc32kctrl_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _SAMD51_OSC32KCTRL_COMPONENT_H_ */
Index: /asp_wio_terminal/trunk/target/samd51_gcc/lib/oscctrl.h
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/lib/oscctrl.h	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/lib/oscctrl.h	(revision 460)
@@ -0,0 +1,692 @@
+/**
+ * \brief Component description for OSCCTRL
+ *
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * Subject to your compliance with these terms, you may use Microchip software and any derivatives
+ * exclusively with Microchip products. It is your responsibility to comply with third party license
+ * terms applicable to your use of third party software (including open source software) that may
+ * accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
+ * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
+ * FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
+ * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
+ * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ */
+
+/* file generated from device description version 2020-03-12T17:26:00Z */
+#ifndef _SAMD51_OSCCTRL_COMPONENT_H_
+#define _SAMD51_OSCCTRL_COMPONENT_H_
+
+/* ************************************************************************** */
+/*   SOFTWARE API DEFINITION FOR OSCCTRL                                      */
+/* ************************************************************************** */
+
+/* -------- OSCCTRL_DPLLCTRLA : (OSCCTRL Offset: 0x00) (R/W 8) DPLL Control A -------- */
+#define OSCCTRL_DPLLCTRLA_RESETVALUE          _U_(0x80)                                            /**<  (OSCCTRL_DPLLCTRLA) DPLL Control A  Reset Value */
+
+#define OSCCTRL_DPLLCTRLA_ENABLE_Pos          _U_(1)                                               /**< (OSCCTRL_DPLLCTRLA) DPLL Enable Position */
+#define OSCCTRL_DPLLCTRLA_ENABLE_Msk          (_U_(0x1) << OSCCTRL_DPLLCTRLA_ENABLE_Pos)           /**< (OSCCTRL_DPLLCTRLA) DPLL Enable Mask */
+#define OSCCTRL_DPLLCTRLA_ENABLE(value)       (OSCCTRL_DPLLCTRLA_ENABLE_Msk & ((value) << OSCCTRL_DPLLCTRLA_ENABLE_Pos))
+#define OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos        _U_(6)                                               /**< (OSCCTRL_DPLLCTRLA) Run in Standby Position */
+#define OSCCTRL_DPLLCTRLA_RUNSTDBY_Msk        (_U_(0x1) << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos)         /**< (OSCCTRL_DPLLCTRLA) Run in Standby Mask */
+#define OSCCTRL_DPLLCTRLA_RUNSTDBY(value)     (OSCCTRL_DPLLCTRLA_RUNSTDBY_Msk & ((value) << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos))
+#define OSCCTRL_DPLLCTRLA_ONDEMAND_Pos        _U_(7)                                               /**< (OSCCTRL_DPLLCTRLA) On Demand Control Position */
+#define OSCCTRL_DPLLCTRLA_ONDEMAND_Msk        (_U_(0x1) << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos)         /**< (OSCCTRL_DPLLCTRLA) On Demand Control Mask */
+#define OSCCTRL_DPLLCTRLA_ONDEMAND(value)     (OSCCTRL_DPLLCTRLA_ONDEMAND_Msk & ((value) << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos))
+#define OSCCTRL_DPLLCTRLA_Msk                 _U_(0xC2)                                            /**< (OSCCTRL_DPLLCTRLA) Register Mask  */
+
+
+/* -------- OSCCTRL_DPLLRATIO : (OSCCTRL Offset: 0x04) (R/W 32) DPLL Ratio Control -------- */
+#define OSCCTRL_DPLLRATIO_RESETVALUE          _U_(0x00)                                            /**<  (OSCCTRL_DPLLRATIO) DPLL Ratio Control  Reset Value */
+
+#define OSCCTRL_DPLLRATIO_LDR_Pos             _U_(0)                                               /**< (OSCCTRL_DPLLRATIO) Loop Divider Ratio Position */
+#define OSCCTRL_DPLLRATIO_LDR_Msk             (_U_(0x1FFF) << OSCCTRL_DPLLRATIO_LDR_Pos)           /**< (OSCCTRL_DPLLRATIO) Loop Divider Ratio Mask */
+#define OSCCTRL_DPLLRATIO_LDR(value)          (OSCCTRL_DPLLRATIO_LDR_Msk & ((value) << OSCCTRL_DPLLRATIO_LDR_Pos))
+#define OSCCTRL_DPLLRATIO_LDRFRAC_Pos         _U_(16)                                              /**< (OSCCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part Position */
+#define OSCCTRL_DPLLRATIO_LDRFRAC_Msk         (_U_(0x1F) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos)         /**< (OSCCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part Mask */
+#define OSCCTRL_DPLLRATIO_LDRFRAC(value)      (OSCCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos))
+#define OSCCTRL_DPLLRATIO_Msk                 _U_(0x001F1FFF)                                      /**< (OSCCTRL_DPLLRATIO) Register Mask  */
+
+
+/* -------- OSCCTRL_DPLLCTRLB : (OSCCTRL Offset: 0x08) (R/W 32) DPLL Control B -------- */
+#define OSCCTRL_DPLLCTRLB_RESETVALUE          _U_(0x20)                                            /**<  (OSCCTRL_DPLLCTRLB) DPLL Control B  Reset Value */
+
+#define OSCCTRL_DPLLCTRLB_FILTER_Pos          _U_(0)                                               /**< (OSCCTRL_DPLLCTRLB) Proportional Integral Filter Selection Position */
+#define OSCCTRL_DPLLCTRLB_FILTER_Msk          (_U_(0xF) << OSCCTRL_DPLLCTRLB_FILTER_Pos)           /**< (OSCCTRL_DPLLCTRLB) Proportional Integral Filter Selection Mask */
+#define OSCCTRL_DPLLCTRLB_FILTER(value)       (OSCCTRL_DPLLCTRLB_FILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_FILTER_Pos))
+#define   OSCCTRL_DPLLCTRLB_FILTER_FILTER1_Val _U_(0x0)                                             /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 92.7Khz and Damping Factor = 0.76  */
+#define   OSCCTRL_DPLLCTRLB_FILTER_FILTER2_Val _U_(0x1)                                             /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 131Khz and Damping Factor = 1.08  */
+#define   OSCCTRL_DPLLCTRLB_FILTER_FILTER3_Val _U_(0x2)                                             /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 46.4Khz and Damping Factor = 0.38  */
+#define   OSCCTRL_DPLLCTRLB_FILTER_FILTER4_Val _U_(0x3)                                             /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 0.54  */
+#define   OSCCTRL_DPLLCTRLB_FILTER_FILTER5_Val _U_(0x4)                                             /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 131Khz and Damping Factor = 0.56  */
+#define   OSCCTRL_DPLLCTRLB_FILTER_FILTER6_Val _U_(0x5)                                             /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 185Khz and Damping Factor = 0.79  */
+#define   OSCCTRL_DPLLCTRLB_FILTER_FILTER7_Val _U_(0x6)                                             /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 0.28  */
+#define   OSCCTRL_DPLLCTRLB_FILTER_FILTER8_Val _U_(0x7)                                             /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 92.7Khz and Damping Factor = 0.39  */
+#define   OSCCTRL_DPLLCTRLB_FILTER_FILTER9_Val _U_(0x8)                                             /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 46.4Khz and Damping Factor = 1.49  */
+#define   OSCCTRL_DPLLCTRLB_FILTER_FILTER10_Val _U_(0x9)                                             /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 2.11  */
+#define   OSCCTRL_DPLLCTRLB_FILTER_FILTER11_Val _U_(0xA)                                             /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 23.2Khz and Damping Factor = 0.75  */
+#define   OSCCTRL_DPLLCTRLB_FILTER_FILTER12_Val _U_(0xB)                                             /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 32.8Khz and Damping Factor = 1.06  */
+#define   OSCCTRL_DPLLCTRLB_FILTER_FILTER13_Val _U_(0xC)                                             /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 1.07  */
+#define   OSCCTRL_DPLLCTRLB_FILTER_FILTER14_Val _U_(0xD)                                             /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 92.7Khz and Damping Factor = 1.51  */
+#define   OSCCTRL_DPLLCTRLB_FILTER_FILTER15_Val _U_(0xE)                                             /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 32.8Khz and Damping Factor = 0.53  */
+#define   OSCCTRL_DPLLCTRLB_FILTER_FILTER16_Val _U_(0xF)                                             /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 46.4Khz and Damping Factor = 0.75  */
+#define OSCCTRL_DPLLCTRLB_FILTER_FILTER1      (OSCCTRL_DPLLCTRLB_FILTER_FILTER1_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 92.7Khz and Damping Factor = 0.76 Position  */
+#define OSCCTRL_DPLLCTRLB_FILTER_FILTER2      (OSCCTRL_DPLLCTRLB_FILTER_FILTER2_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 131Khz and Damping Factor = 1.08 Position  */
+#define OSCCTRL_DPLLCTRLB_FILTER_FILTER3      (OSCCTRL_DPLLCTRLB_FILTER_FILTER3_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 46.4Khz and Damping Factor = 0.38 Position  */
+#define OSCCTRL_DPLLCTRLB_FILTER_FILTER4      (OSCCTRL_DPLLCTRLB_FILTER_FILTER4_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 0.54 Position  */
+#define OSCCTRL_DPLLCTRLB_FILTER_FILTER5      (OSCCTRL_DPLLCTRLB_FILTER_FILTER5_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 131Khz and Damping Factor = 0.56 Position  */
+#define OSCCTRL_DPLLCTRLB_FILTER_FILTER6      (OSCCTRL_DPLLCTRLB_FILTER_FILTER6_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 185Khz and Damping Factor = 0.79 Position  */
+#define OSCCTRL_DPLLCTRLB_FILTER_FILTER7      (OSCCTRL_DPLLCTRLB_FILTER_FILTER7_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 0.28 Position  */
+#define OSCCTRL_DPLLCTRLB_FILTER_FILTER8      (OSCCTRL_DPLLCTRLB_FILTER_FILTER8_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 92.7Khz and Damping Factor = 0.39 Position  */
+#define OSCCTRL_DPLLCTRLB_FILTER_FILTER9      (OSCCTRL_DPLLCTRLB_FILTER_FILTER9_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 46.4Khz and Damping Factor = 1.49 Position  */
+#define OSCCTRL_DPLLCTRLB_FILTER_FILTER10     (OSCCTRL_DPLLCTRLB_FILTER_FILTER10_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 2.11 Position  */
+#define OSCCTRL_DPLLCTRLB_FILTER_FILTER11     (OSCCTRL_DPLLCTRLB_FILTER_FILTER11_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 23.2Khz and Damping Factor = 0.75 Position  */
+#define OSCCTRL_DPLLCTRLB_FILTER_FILTER12     (OSCCTRL_DPLLCTRLB_FILTER_FILTER12_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 32.8Khz and Damping Factor = 1.06 Position  */
+#define OSCCTRL_DPLLCTRLB_FILTER_FILTER13     (OSCCTRL_DPLLCTRLB_FILTER_FILTER13_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 1.07 Position  */
+#define OSCCTRL_DPLLCTRLB_FILTER_FILTER14     (OSCCTRL_DPLLCTRLB_FILTER_FILTER14_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 92.7Khz and Damping Factor = 1.51 Position  */
+#define OSCCTRL_DPLLCTRLB_FILTER_FILTER15     (OSCCTRL_DPLLCTRLB_FILTER_FILTER15_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 32.8Khz and Damping Factor = 0.53 Position  */
+#define OSCCTRL_DPLLCTRLB_FILTER_FILTER16     (OSCCTRL_DPLLCTRLB_FILTER_FILTER16_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 46.4Khz and Damping Factor = 0.75 Position  */
+#define OSCCTRL_DPLLCTRLB_WUF_Pos             _U_(4)                                               /**< (OSCCTRL_DPLLCTRLB) Wake Up Fast Position */
+#define OSCCTRL_DPLLCTRLB_WUF_Msk             (_U_(0x1) << OSCCTRL_DPLLCTRLB_WUF_Pos)              /**< (OSCCTRL_DPLLCTRLB) Wake Up Fast Mask */
+#define OSCCTRL_DPLLCTRLB_WUF(value)          (OSCCTRL_DPLLCTRLB_WUF_Msk & ((value) << OSCCTRL_DPLLCTRLB_WUF_Pos))
+#define OSCCTRL_DPLLCTRLB_REFCLK_Pos          _U_(5)                                               /**< (OSCCTRL_DPLLCTRLB) Reference Clock Selection Position */
+#define OSCCTRL_DPLLCTRLB_REFCLK_Msk          (_U_(0x7) << OSCCTRL_DPLLCTRLB_REFCLK_Pos)           /**< (OSCCTRL_DPLLCTRLB) Reference Clock Selection Mask */
+#define OSCCTRL_DPLLCTRLB_REFCLK(value)       (OSCCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << OSCCTRL_DPLLCTRLB_REFCLK_Pos))
+#define   OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val   _U_(0x0)                                             /**< (OSCCTRL_DPLLCTRLB) Dedicated GCLK clock reference  */
+#define   OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val _U_(0x1)                                             /**< (OSCCTRL_DPLLCTRLB) XOSC32K clock reference  */
+#define   OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val  _U_(0x2)                                             /**< (OSCCTRL_DPLLCTRLB) XOSC0 clock reference  */
+#define   OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val  _U_(0x3)                                             /**< (OSCCTRL_DPLLCTRLB) XOSC1 clock reference  */
+#define OSCCTRL_DPLLCTRLB_REFCLK_GCLK         (OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos) /**< (OSCCTRL_DPLLCTRLB) Dedicated GCLK clock reference Position  */
+#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC32       (OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos) /**< (OSCCTRL_DPLLCTRLB) XOSC32K clock reference Position  */
+#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC0        (OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos) /**< (OSCCTRL_DPLLCTRLB) XOSC0 clock reference Position  */
+#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC1        (OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos) /**< (OSCCTRL_DPLLCTRLB) XOSC1 clock reference Position  */
+#define OSCCTRL_DPLLCTRLB_LTIME_Pos           _U_(8)                                               /**< (OSCCTRL_DPLLCTRLB) Lock Time Position */
+#define OSCCTRL_DPLLCTRLB_LTIME_Msk           (_U_(0x7) << OSCCTRL_DPLLCTRLB_LTIME_Pos)            /**< (OSCCTRL_DPLLCTRLB) Lock Time Mask */
+#define OSCCTRL_DPLLCTRLB_LTIME(value)        (OSCCTRL_DPLLCTRLB_LTIME_Msk & ((value) << OSCCTRL_DPLLCTRLB_LTIME_Pos))
+#define   OSCCTRL_DPLLCTRLB_LTIME_DEFAULT_Val _U_(0x0)                                             /**< (OSCCTRL_DPLLCTRLB) No time-out. Automatic lock  */
+#define   OSCCTRL_DPLLCTRLB_LTIME_800US_Val   _U_(0x4)                                             /**< (OSCCTRL_DPLLCTRLB) Time-out if no lock within 800us  */
+#define   OSCCTRL_DPLLCTRLB_LTIME_900US_Val   _U_(0x5)                                             /**< (OSCCTRL_DPLLCTRLB) Time-out if no lock within 900us  */
+#define   OSCCTRL_DPLLCTRLB_LTIME_1MS_Val     _U_(0x6)                                             /**< (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1ms  */
+#define   OSCCTRL_DPLLCTRLB_LTIME_1P1MS_Val   _U_(0x7)                                             /**< (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1.1ms  */
+#define OSCCTRL_DPLLCTRLB_LTIME_DEFAULT       (OSCCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos) /**< (OSCCTRL_DPLLCTRLB) No time-out. Automatic lock Position  */
+#define OSCCTRL_DPLLCTRLB_LTIME_800US         (OSCCTRL_DPLLCTRLB_LTIME_800US_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos) /**< (OSCCTRL_DPLLCTRLB) Time-out if no lock within 800us Position  */
+#define OSCCTRL_DPLLCTRLB_LTIME_900US         (OSCCTRL_DPLLCTRLB_LTIME_900US_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos) /**< (OSCCTRL_DPLLCTRLB) Time-out if no lock within 900us Position  */
+#define OSCCTRL_DPLLCTRLB_LTIME_1MS           (OSCCTRL_DPLLCTRLB_LTIME_1MS_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos) /**< (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1ms Position  */
+#define OSCCTRL_DPLLCTRLB_LTIME_1P1MS         (OSCCTRL_DPLLCTRLB_LTIME_1P1MS_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos) /**< (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1.1ms Position  */
+#define OSCCTRL_DPLLCTRLB_LBYPASS_Pos         _U_(11)                                              /**< (OSCCTRL_DPLLCTRLB) Lock Bypass Position */
+#define OSCCTRL_DPLLCTRLB_LBYPASS_Msk         (_U_(0x1) << OSCCTRL_DPLLCTRLB_LBYPASS_Pos)          /**< (OSCCTRL_DPLLCTRLB) Lock Bypass Mask */
+#define OSCCTRL_DPLLCTRLB_LBYPASS(value)      (OSCCTRL_DPLLCTRLB_LBYPASS_Msk & ((value) << OSCCTRL_DPLLCTRLB_LBYPASS_Pos))
+#define OSCCTRL_DPLLCTRLB_DCOFILTER_Pos       _U_(12)                                              /**< (OSCCTRL_DPLLCTRLB) Sigma-Delta DCO Filter Selection Position */
+#define OSCCTRL_DPLLCTRLB_DCOFILTER_Msk       (_U_(0x7) << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos)        /**< (OSCCTRL_DPLLCTRLB) Sigma-Delta DCO Filter Selection Mask */
+#define OSCCTRL_DPLLCTRLB_DCOFILTER(value)    (OSCCTRL_DPLLCTRLB_DCOFILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos))
+#define   OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER1_Val _U_(0x0)                                             /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 0.5 and Bandwidth Fn (MHz) = 3.21  */
+#define   OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER2_Val _U_(0x1)                                             /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 1 and Bandwidth Fn (MHz) = 1.6  */
+#define   OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER3_Val _U_(0x2)                                             /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 1.5 and Bandwidth Fn (MHz) = 1.1  */
+#define   OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER4_Val _U_(0x3)                                             /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 2 and Bandwidth Fn (MHz) = 0.8  */
+#define   OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER5_Val _U_(0x4)                                             /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 2.5 and Bandwidth Fn (MHz) = 0.64  */
+#define   OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER6_Val _U_(0x5)                                             /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 3 and Bandwidth Fn (MHz) = 0.55  */
+#define   OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER7_Val _U_(0x6)                                             /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 3.5 and Bandwidth Fn (MHz) = 0.45  */
+#define   OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER8_Val _U_(0x7)                                             /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 4 and Bandwidth Fn (MHz) = 0.4  */
+#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER1   (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER1_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 0.5 and Bandwidth Fn (MHz) = 3.21 Position  */
+#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER2   (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER2_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 1 and Bandwidth Fn (MHz) = 1.6 Position  */
+#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER3   (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER3_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 1.5 and Bandwidth Fn (MHz) = 1.1 Position  */
+#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER4   (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER4_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 2 and Bandwidth Fn (MHz) = 0.8 Position  */
+#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER5   (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER5_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 2.5 and Bandwidth Fn (MHz) = 0.64 Position  */
+#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER6   (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER6_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 3 and Bandwidth Fn (MHz) = 0.55 Position  */
+#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER7   (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER7_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 3.5 and Bandwidth Fn (MHz) = 0.45 Position  */
+#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER8   (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER8_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 4 and Bandwidth Fn (MHz) = 0.4 Position  */
+#define OSCCTRL_DPLLCTRLB_DCOEN_Pos           _U_(15)                                              /**< (OSCCTRL_DPLLCTRLB) DCO Filter Enable Position */
+#define OSCCTRL_DPLLCTRLB_DCOEN_Msk           (_U_(0x1) << OSCCTRL_DPLLCTRLB_DCOEN_Pos)            /**< (OSCCTRL_DPLLCTRLB) DCO Filter Enable Mask */
+#define OSCCTRL_DPLLCTRLB_DCOEN(value)        (OSCCTRL_DPLLCTRLB_DCOEN_Msk & ((value) << OSCCTRL_DPLLCTRLB_DCOEN_Pos))
+#define OSCCTRL_DPLLCTRLB_DIV_Pos             _U_(16)                                              /**< (OSCCTRL_DPLLCTRLB) Clock Divider Position */
+#define OSCCTRL_DPLLCTRLB_DIV_Msk             (_U_(0x7FF) << OSCCTRL_DPLLCTRLB_DIV_Pos)            /**< (OSCCTRL_DPLLCTRLB) Clock Divider Mask */
+#define OSCCTRL_DPLLCTRLB_DIV(value)          (OSCCTRL_DPLLCTRLB_DIV_Msk & ((value) << OSCCTRL_DPLLCTRLB_DIV_Pos))
+#define OSCCTRL_DPLLCTRLB_Msk                 _U_(0x07FFFFFF)                                      /**< (OSCCTRL_DPLLCTRLB) Register Mask  */
+
+
+/* -------- OSCCTRL_DPLLSYNCBUSY : (OSCCTRL Offset: 0x0C) ( R/ 32) DPLL Synchronization Busy -------- */
+#define OSCCTRL_DPLLSYNCBUSY_RESETVALUE       _U_(0x00)                                            /**<  (OSCCTRL_DPLLSYNCBUSY) DPLL Synchronization Busy  Reset Value */
+
+#define OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos       _U_(1)                                               /**< (OSCCTRL_DPLLSYNCBUSY) DPLL Enable Synchronization Status Position */
+#define OSCCTRL_DPLLSYNCBUSY_ENABLE_Msk       (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos)        /**< (OSCCTRL_DPLLSYNCBUSY) DPLL Enable Synchronization Status Mask */
+#define OSCCTRL_DPLLSYNCBUSY_ENABLE(value)    (OSCCTRL_DPLLSYNCBUSY_ENABLE_Msk & ((value) << OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos))
+#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos    _U_(2)                                               /**< (OSCCTRL_DPLLSYNCBUSY) DPLL Loop Divider Ratio Synchronization Status Position */
+#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Msk    (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos)     /**< (OSCCTRL_DPLLSYNCBUSY) DPLL Loop Divider Ratio Synchronization Status Mask */
+#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO(value) (OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Msk & ((value) << OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos))
+#define OSCCTRL_DPLLSYNCBUSY_Msk              _U_(0x00000006)                                      /**< (OSCCTRL_DPLLSYNCBUSY) Register Mask  */
+
+
+/* -------- OSCCTRL_DPLLSTATUS : (OSCCTRL Offset: 0x10) ( R/ 32) DPLL Status -------- */
+#define OSCCTRL_DPLLSTATUS_RESETVALUE         _U_(0x00)                                            /**<  (OSCCTRL_DPLLSTATUS) DPLL Status  Reset Value */
+
+#define OSCCTRL_DPLLSTATUS_LOCK_Pos           _U_(0)                                               /**< (OSCCTRL_DPLLSTATUS) DPLL Lock Status Position */
+#define OSCCTRL_DPLLSTATUS_LOCK_Msk           (_U_(0x1) << OSCCTRL_DPLLSTATUS_LOCK_Pos)            /**< (OSCCTRL_DPLLSTATUS) DPLL Lock Status Mask */
+#define OSCCTRL_DPLLSTATUS_LOCK(value)        (OSCCTRL_DPLLSTATUS_LOCK_Msk & ((value) << OSCCTRL_DPLLSTATUS_LOCK_Pos))
+#define OSCCTRL_DPLLSTATUS_CLKRDY_Pos         _U_(1)                                               /**< (OSCCTRL_DPLLSTATUS) DPLL Clock Ready Position */
+#define OSCCTRL_DPLLSTATUS_CLKRDY_Msk         (_U_(0x1) << OSCCTRL_DPLLSTATUS_CLKRDY_Pos)          /**< (OSCCTRL_DPLLSTATUS) DPLL Clock Ready Mask */
+#define OSCCTRL_DPLLSTATUS_CLKRDY(value)      (OSCCTRL_DPLLSTATUS_CLKRDY_Msk & ((value) << OSCCTRL_DPLLSTATUS_CLKRDY_Pos))
+#define OSCCTRL_DPLLSTATUS_Msk                _U_(0x00000003)                                      /**< (OSCCTRL_DPLLSTATUS) Register Mask  */
+
+
+/* -------- OSCCTRL_EVCTRL : (OSCCTRL Offset: 0x00) (R/W 8) Event Control -------- */
+#define OSCCTRL_EVCTRL_RESETVALUE             _U_(0x00)                                            /**<  (OSCCTRL_EVCTRL) Event Control  Reset Value */
+
+#define OSCCTRL_EVCTRL_CFDEO0_Pos             _U_(0)                                               /**< (OSCCTRL_EVCTRL) Clock 0 Failure Detector Event Output Enable Position */
+#define OSCCTRL_EVCTRL_CFDEO0_Msk             (_U_(0x1) << OSCCTRL_EVCTRL_CFDEO0_Pos)              /**< (OSCCTRL_EVCTRL) Clock 0 Failure Detector Event Output Enable Mask */
+#define OSCCTRL_EVCTRL_CFDEO0(value)          (OSCCTRL_EVCTRL_CFDEO0_Msk & ((value) << OSCCTRL_EVCTRL_CFDEO0_Pos))
+#define OSCCTRL_EVCTRL_CFDEO1_Pos             _U_(1)                                               /**< (OSCCTRL_EVCTRL) Clock 1 Failure Detector Event Output Enable Position */
+#define OSCCTRL_EVCTRL_CFDEO1_Msk             (_U_(0x1) << OSCCTRL_EVCTRL_CFDEO1_Pos)              /**< (OSCCTRL_EVCTRL) Clock 1 Failure Detector Event Output Enable Mask */
+#define OSCCTRL_EVCTRL_CFDEO1(value)          (OSCCTRL_EVCTRL_CFDEO1_Msk & ((value) << OSCCTRL_EVCTRL_CFDEO1_Pos))
+#define OSCCTRL_EVCTRL_Msk                    _U_(0x03)                                            /**< (OSCCTRL_EVCTRL) Register Mask  */
+
+#define OSCCTRL_EVCTRL_CFDEO_Pos              _U_(0)                                               /**< (OSCCTRL_EVCTRL Position) Clock x Failure Detector Event Output Enable */
+#define OSCCTRL_EVCTRL_CFDEO_Msk              (_U_(0x3) << OSCCTRL_EVCTRL_CFDEO_Pos)               /**< (OSCCTRL_EVCTRL Mask) CFDEO */
+#define OSCCTRL_EVCTRL_CFDEO(value)           (OSCCTRL_EVCTRL_CFDEO_Msk & ((value) << OSCCTRL_EVCTRL_CFDEO_Pos)) 
+
+/* -------- OSCCTRL_INTENCLR : (OSCCTRL Offset: 0x04) (R/W 32) Interrupt Enable Clear -------- */
+#define OSCCTRL_INTENCLR_RESETVALUE           _U_(0x00)                                            /**<  (OSCCTRL_INTENCLR) Interrupt Enable Clear  Reset Value */
+
+#define OSCCTRL_INTENCLR_XOSCRDY0_Pos         _U_(0)                                               /**< (OSCCTRL_INTENCLR) XOSC 0 Ready Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_XOSCRDY0_Msk         (_U_(0x1) << OSCCTRL_INTENCLR_XOSCRDY0_Pos)          /**< (OSCCTRL_INTENCLR) XOSC 0 Ready Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_XOSCRDY0(value)      (OSCCTRL_INTENCLR_XOSCRDY0_Msk & ((value) << OSCCTRL_INTENCLR_XOSCRDY0_Pos))
+#define OSCCTRL_INTENCLR_XOSCRDY1_Pos         _U_(1)                                               /**< (OSCCTRL_INTENCLR) XOSC 1 Ready Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_XOSCRDY1_Msk         (_U_(0x1) << OSCCTRL_INTENCLR_XOSCRDY1_Pos)          /**< (OSCCTRL_INTENCLR) XOSC 1 Ready Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_XOSCRDY1(value)      (OSCCTRL_INTENCLR_XOSCRDY1_Msk & ((value) << OSCCTRL_INTENCLR_XOSCRDY1_Pos))
+#define OSCCTRL_INTENCLR_XOSCFAIL0_Pos        _U_(2)                                               /**< (OSCCTRL_INTENCLR) XOSC 0 Clock Failure Detector Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_XOSCFAIL0_Msk        (_U_(0x1) << OSCCTRL_INTENCLR_XOSCFAIL0_Pos)         /**< (OSCCTRL_INTENCLR) XOSC 0 Clock Failure Detector Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_XOSCFAIL0(value)     (OSCCTRL_INTENCLR_XOSCFAIL0_Msk & ((value) << OSCCTRL_INTENCLR_XOSCFAIL0_Pos))
+#define OSCCTRL_INTENCLR_XOSCFAIL1_Pos        _U_(3)                                               /**< (OSCCTRL_INTENCLR) XOSC 1 Clock Failure Detector Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_XOSCFAIL1_Msk        (_U_(0x1) << OSCCTRL_INTENCLR_XOSCFAIL1_Pos)         /**< (OSCCTRL_INTENCLR) XOSC 1 Clock Failure Detector Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_XOSCFAIL1(value)     (OSCCTRL_INTENCLR_XOSCFAIL1_Msk & ((value) << OSCCTRL_INTENCLR_XOSCFAIL1_Pos))
+#define OSCCTRL_INTENCLR_DFLLRDY_Pos          _U_(8)                                               /**< (OSCCTRL_INTENCLR) DFLL Ready Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_DFLLRDY_Msk          (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRDY_Pos)           /**< (OSCCTRL_INTENCLR) DFLL Ready Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_DFLLRDY(value)       (OSCCTRL_INTENCLR_DFLLRDY_Msk & ((value) << OSCCTRL_INTENCLR_DFLLRDY_Pos))
+#define OSCCTRL_INTENCLR_DFLLOOB_Pos          _U_(9)                                               /**< (OSCCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_DFLLOOB_Msk          (_U_(0x1) << OSCCTRL_INTENCLR_DFLLOOB_Pos)           /**< (OSCCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_DFLLOOB(value)       (OSCCTRL_INTENCLR_DFLLOOB_Msk & ((value) << OSCCTRL_INTENCLR_DFLLOOB_Pos))
+#define OSCCTRL_INTENCLR_DFLLLCKF_Pos         _U_(10)                                              /**< (OSCCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_DFLLLCKF_Msk         (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKF_Pos)          /**< (OSCCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_DFLLLCKF(value)      (OSCCTRL_INTENCLR_DFLLLCKF_Msk & ((value) << OSCCTRL_INTENCLR_DFLLLCKF_Pos))
+#define OSCCTRL_INTENCLR_DFLLLCKC_Pos         _U_(11)                                              /**< (OSCCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_DFLLLCKC_Msk         (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKC_Pos)          /**< (OSCCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_DFLLLCKC(value)      (OSCCTRL_INTENCLR_DFLLLCKC_Msk & ((value) << OSCCTRL_INTENCLR_DFLLLCKC_Pos))
+#define OSCCTRL_INTENCLR_DFLLRCS_Pos          _U_(12)                                              /**< (OSCCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_DFLLRCS_Msk          (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRCS_Pos)           /**< (OSCCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_DFLLRCS(value)       (OSCCTRL_INTENCLR_DFLLRCS_Msk & ((value) << OSCCTRL_INTENCLR_DFLLRCS_Pos))
+#define OSCCTRL_INTENCLR_DPLL0LCKR_Pos        _U_(16)                                              /**< (OSCCTRL_INTENCLR) DPLL0 Lock Rise Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_DPLL0LCKR_Msk        (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LCKR_Pos)         /**< (OSCCTRL_INTENCLR) DPLL0 Lock Rise Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_DPLL0LCKR(value)     (OSCCTRL_INTENCLR_DPLL0LCKR_Msk & ((value) << OSCCTRL_INTENCLR_DPLL0LCKR_Pos))
+#define OSCCTRL_INTENCLR_DPLL0LCKF_Pos        _U_(17)                                              /**< (OSCCTRL_INTENCLR) DPLL0 Lock Fall Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_DPLL0LCKF_Msk        (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LCKF_Pos)         /**< (OSCCTRL_INTENCLR) DPLL0 Lock Fall Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_DPLL0LCKF(value)     (OSCCTRL_INTENCLR_DPLL0LCKF_Msk & ((value) << OSCCTRL_INTENCLR_DPLL0LCKF_Pos))
+#define OSCCTRL_INTENCLR_DPLL0LTO_Pos         _U_(18)                                              /**< (OSCCTRL_INTENCLR) DPLL0 Lock Timeout Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_DPLL0LTO_Msk         (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LTO_Pos)          /**< (OSCCTRL_INTENCLR) DPLL0 Lock Timeout Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_DPLL0LTO(value)      (OSCCTRL_INTENCLR_DPLL0LTO_Msk & ((value) << OSCCTRL_INTENCLR_DPLL0LTO_Pos))
+#define OSCCTRL_INTENCLR_DPLL0LDRTO_Pos       _U_(19)                                              /**< (OSCCTRL_INTENCLR) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_DPLL0LDRTO_Msk       (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LDRTO_Pos)        /**< (OSCCTRL_INTENCLR) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_DPLL0LDRTO(value)    (OSCCTRL_INTENCLR_DPLL0LDRTO_Msk & ((value) << OSCCTRL_INTENCLR_DPLL0LDRTO_Pos))
+#define OSCCTRL_INTENCLR_DPLL1LCKR_Pos        _U_(24)                                              /**< (OSCCTRL_INTENCLR) DPLL1 Lock Rise Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_DPLL1LCKR_Msk        (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LCKR_Pos)         /**< (OSCCTRL_INTENCLR) DPLL1 Lock Rise Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_DPLL1LCKR(value)     (OSCCTRL_INTENCLR_DPLL1LCKR_Msk & ((value) << OSCCTRL_INTENCLR_DPLL1LCKR_Pos))
+#define OSCCTRL_INTENCLR_DPLL1LCKF_Pos        _U_(25)                                              /**< (OSCCTRL_INTENCLR) DPLL1 Lock Fall Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_DPLL1LCKF_Msk        (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LCKF_Pos)         /**< (OSCCTRL_INTENCLR) DPLL1 Lock Fall Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_DPLL1LCKF(value)     (OSCCTRL_INTENCLR_DPLL1LCKF_Msk & ((value) << OSCCTRL_INTENCLR_DPLL1LCKF_Pos))
+#define OSCCTRL_INTENCLR_DPLL1LTO_Pos         _U_(26)                                              /**< (OSCCTRL_INTENCLR) DPLL1 Lock Timeout Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_DPLL1LTO_Msk         (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LTO_Pos)          /**< (OSCCTRL_INTENCLR) DPLL1 Lock Timeout Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_DPLL1LTO(value)      (OSCCTRL_INTENCLR_DPLL1LTO_Msk & ((value) << OSCCTRL_INTENCLR_DPLL1LTO_Pos))
+#define OSCCTRL_INTENCLR_DPLL1LDRTO_Pos       _U_(27)                                              /**< (OSCCTRL_INTENCLR) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable Position */
+#define OSCCTRL_INTENCLR_DPLL1LDRTO_Msk       (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LDRTO_Pos)        /**< (OSCCTRL_INTENCLR) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable Mask */
+#define OSCCTRL_INTENCLR_DPLL1LDRTO(value)    (OSCCTRL_INTENCLR_DPLL1LDRTO_Msk & ((value) << OSCCTRL_INTENCLR_DPLL1LDRTO_Pos))
+#define OSCCTRL_INTENCLR_Msk                  _U_(0x0F0F1F0F)                                      /**< (OSCCTRL_INTENCLR) Register Mask  */
+
+#define OSCCTRL_INTENCLR_XOSCRDY_Pos          _U_(0)                                               /**< (OSCCTRL_INTENCLR Position) XOSC x Ready Interrupt Enable */
+#define OSCCTRL_INTENCLR_XOSCRDY_Msk          (_U_(0x3) << OSCCTRL_INTENCLR_XOSCRDY_Pos)           /**< (OSCCTRL_INTENCLR Mask) XOSCRDY */
+#define OSCCTRL_INTENCLR_XOSCRDY(value)       (OSCCTRL_INTENCLR_XOSCRDY_Msk & ((value) << OSCCTRL_INTENCLR_XOSCRDY_Pos)) 
+#define OSCCTRL_INTENCLR_XOSCFAIL_Pos         _U_(2)                                               /**< (OSCCTRL_INTENCLR Position) XOSC x Clock Failure Detector Interrupt Enable */
+#define OSCCTRL_INTENCLR_XOSCFAIL_Msk         (_U_(0x3) << OSCCTRL_INTENCLR_XOSCFAIL_Pos)          /**< (OSCCTRL_INTENCLR Mask) XOSCFAIL */
+#define OSCCTRL_INTENCLR_XOSCFAIL(value)      (OSCCTRL_INTENCLR_XOSCFAIL_Msk & ((value) << OSCCTRL_INTENCLR_XOSCFAIL_Pos)) 
+
+/* -------- OSCCTRL_INTENSET : (OSCCTRL Offset: 0x08) (R/W 32) Interrupt Enable Set -------- */
+#define OSCCTRL_INTENSET_RESETVALUE           _U_(0x00)                                            /**<  (OSCCTRL_INTENSET) Interrupt Enable Set  Reset Value */
+
+#define OSCCTRL_INTENSET_XOSCRDY0_Pos         _U_(0)                                               /**< (OSCCTRL_INTENSET) XOSC 0 Ready Interrupt Enable Position */
+#define OSCCTRL_INTENSET_XOSCRDY0_Msk         (_U_(0x1) << OSCCTRL_INTENSET_XOSCRDY0_Pos)          /**< (OSCCTRL_INTENSET) XOSC 0 Ready Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_XOSCRDY0(value)      (OSCCTRL_INTENSET_XOSCRDY0_Msk & ((value) << OSCCTRL_INTENSET_XOSCRDY0_Pos))
+#define OSCCTRL_INTENSET_XOSCRDY1_Pos         _U_(1)                                               /**< (OSCCTRL_INTENSET) XOSC 1 Ready Interrupt Enable Position */
+#define OSCCTRL_INTENSET_XOSCRDY1_Msk         (_U_(0x1) << OSCCTRL_INTENSET_XOSCRDY1_Pos)          /**< (OSCCTRL_INTENSET) XOSC 1 Ready Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_XOSCRDY1(value)      (OSCCTRL_INTENSET_XOSCRDY1_Msk & ((value) << OSCCTRL_INTENSET_XOSCRDY1_Pos))
+#define OSCCTRL_INTENSET_XOSCFAIL0_Pos        _U_(2)                                               /**< (OSCCTRL_INTENSET) XOSC 0 Clock Failure Detector Interrupt Enable Position */
+#define OSCCTRL_INTENSET_XOSCFAIL0_Msk        (_U_(0x1) << OSCCTRL_INTENSET_XOSCFAIL0_Pos)         /**< (OSCCTRL_INTENSET) XOSC 0 Clock Failure Detector Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_XOSCFAIL0(value)     (OSCCTRL_INTENSET_XOSCFAIL0_Msk & ((value) << OSCCTRL_INTENSET_XOSCFAIL0_Pos))
+#define OSCCTRL_INTENSET_XOSCFAIL1_Pos        _U_(3)                                               /**< (OSCCTRL_INTENSET) XOSC 1 Clock Failure Detector Interrupt Enable Position */
+#define OSCCTRL_INTENSET_XOSCFAIL1_Msk        (_U_(0x1) << OSCCTRL_INTENSET_XOSCFAIL1_Pos)         /**< (OSCCTRL_INTENSET) XOSC 1 Clock Failure Detector Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_XOSCFAIL1(value)     (OSCCTRL_INTENSET_XOSCFAIL1_Msk & ((value) << OSCCTRL_INTENSET_XOSCFAIL1_Pos))
+#define OSCCTRL_INTENSET_DFLLRDY_Pos          _U_(8)                                               /**< (OSCCTRL_INTENSET) DFLL Ready Interrupt Enable Position */
+#define OSCCTRL_INTENSET_DFLLRDY_Msk          (_U_(0x1) << OSCCTRL_INTENSET_DFLLRDY_Pos)           /**< (OSCCTRL_INTENSET) DFLL Ready Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_DFLLRDY(value)       (OSCCTRL_INTENSET_DFLLRDY_Msk & ((value) << OSCCTRL_INTENSET_DFLLRDY_Pos))
+#define OSCCTRL_INTENSET_DFLLOOB_Pos          _U_(9)                                               /**< (OSCCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable Position */
+#define OSCCTRL_INTENSET_DFLLOOB_Msk          (_U_(0x1) << OSCCTRL_INTENSET_DFLLOOB_Pos)           /**< (OSCCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_DFLLOOB(value)       (OSCCTRL_INTENSET_DFLLOOB_Msk & ((value) << OSCCTRL_INTENSET_DFLLOOB_Pos))
+#define OSCCTRL_INTENSET_DFLLLCKF_Pos         _U_(10)                                              /**< (OSCCTRL_INTENSET) DFLL Lock Fine Interrupt Enable Position */
+#define OSCCTRL_INTENSET_DFLLLCKF_Msk         (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKF_Pos)          /**< (OSCCTRL_INTENSET) DFLL Lock Fine Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_DFLLLCKF(value)      (OSCCTRL_INTENSET_DFLLLCKF_Msk & ((value) << OSCCTRL_INTENSET_DFLLLCKF_Pos))
+#define OSCCTRL_INTENSET_DFLLLCKC_Pos         _U_(11)                                              /**< (OSCCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable Position */
+#define OSCCTRL_INTENSET_DFLLLCKC_Msk         (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKC_Pos)          /**< (OSCCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_DFLLLCKC(value)      (OSCCTRL_INTENSET_DFLLLCKC_Msk & ((value) << OSCCTRL_INTENSET_DFLLLCKC_Pos))
+#define OSCCTRL_INTENSET_DFLLRCS_Pos          _U_(12)                                              /**< (OSCCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable Position */
+#define OSCCTRL_INTENSET_DFLLRCS_Msk          (_U_(0x1) << OSCCTRL_INTENSET_DFLLRCS_Pos)           /**< (OSCCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_DFLLRCS(value)       (OSCCTRL_INTENSET_DFLLRCS_Msk & ((value) << OSCCTRL_INTENSET_DFLLRCS_Pos))
+#define OSCCTRL_INTENSET_DPLL0LCKR_Pos        _U_(16)                                              /**< (OSCCTRL_INTENSET) DPLL0 Lock Rise Interrupt Enable Position */
+#define OSCCTRL_INTENSET_DPLL0LCKR_Msk        (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LCKR_Pos)         /**< (OSCCTRL_INTENSET) DPLL0 Lock Rise Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_DPLL0LCKR(value)     (OSCCTRL_INTENSET_DPLL0LCKR_Msk & ((value) << OSCCTRL_INTENSET_DPLL0LCKR_Pos))
+#define OSCCTRL_INTENSET_DPLL0LCKF_Pos        _U_(17)                                              /**< (OSCCTRL_INTENSET) DPLL0 Lock Fall Interrupt Enable Position */
+#define OSCCTRL_INTENSET_DPLL0LCKF_Msk        (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LCKF_Pos)         /**< (OSCCTRL_INTENSET) DPLL0 Lock Fall Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_DPLL0LCKF(value)     (OSCCTRL_INTENSET_DPLL0LCKF_Msk & ((value) << OSCCTRL_INTENSET_DPLL0LCKF_Pos))
+#define OSCCTRL_INTENSET_DPLL0LTO_Pos         _U_(18)                                              /**< (OSCCTRL_INTENSET) DPLL0 Lock Timeout Interrupt Enable Position */
+#define OSCCTRL_INTENSET_DPLL0LTO_Msk         (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LTO_Pos)          /**< (OSCCTRL_INTENSET) DPLL0 Lock Timeout Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_DPLL0LTO(value)      (OSCCTRL_INTENSET_DPLL0LTO_Msk & ((value) << OSCCTRL_INTENSET_DPLL0LTO_Pos))
+#define OSCCTRL_INTENSET_DPLL0LDRTO_Pos       _U_(19)                                              /**< (OSCCTRL_INTENSET) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable Position */
+#define OSCCTRL_INTENSET_DPLL0LDRTO_Msk       (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LDRTO_Pos)        /**< (OSCCTRL_INTENSET) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_DPLL0LDRTO(value)    (OSCCTRL_INTENSET_DPLL0LDRTO_Msk & ((value) << OSCCTRL_INTENSET_DPLL0LDRTO_Pos))
+#define OSCCTRL_INTENSET_DPLL1LCKR_Pos        _U_(24)                                              /**< (OSCCTRL_INTENSET) DPLL1 Lock Rise Interrupt Enable Position */
+#define OSCCTRL_INTENSET_DPLL1LCKR_Msk        (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LCKR_Pos)         /**< (OSCCTRL_INTENSET) DPLL1 Lock Rise Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_DPLL1LCKR(value)     (OSCCTRL_INTENSET_DPLL1LCKR_Msk & ((value) << OSCCTRL_INTENSET_DPLL1LCKR_Pos))
+#define OSCCTRL_INTENSET_DPLL1LCKF_Pos        _U_(25)                                              /**< (OSCCTRL_INTENSET) DPLL1 Lock Fall Interrupt Enable Position */
+#define OSCCTRL_INTENSET_DPLL1LCKF_Msk        (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LCKF_Pos)         /**< (OSCCTRL_INTENSET) DPLL1 Lock Fall Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_DPLL1LCKF(value)     (OSCCTRL_INTENSET_DPLL1LCKF_Msk & ((value) << OSCCTRL_INTENSET_DPLL1LCKF_Pos))
+#define OSCCTRL_INTENSET_DPLL1LTO_Pos         _U_(26)                                              /**< (OSCCTRL_INTENSET) DPLL1 Lock Timeout Interrupt Enable Position */
+#define OSCCTRL_INTENSET_DPLL1LTO_Msk         (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LTO_Pos)          /**< (OSCCTRL_INTENSET) DPLL1 Lock Timeout Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_DPLL1LTO(value)      (OSCCTRL_INTENSET_DPLL1LTO_Msk & ((value) << OSCCTRL_INTENSET_DPLL1LTO_Pos))
+#define OSCCTRL_INTENSET_DPLL1LDRTO_Pos       _U_(27)                                              /**< (OSCCTRL_INTENSET) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable Position */
+#define OSCCTRL_INTENSET_DPLL1LDRTO_Msk       (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LDRTO_Pos)        /**< (OSCCTRL_INTENSET) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable Mask */
+#define OSCCTRL_INTENSET_DPLL1LDRTO(value)    (OSCCTRL_INTENSET_DPLL1LDRTO_Msk & ((value) << OSCCTRL_INTENSET_DPLL1LDRTO_Pos))
+#define OSCCTRL_INTENSET_Msk                  _U_(0x0F0F1F0F)                                      /**< (OSCCTRL_INTENSET) Register Mask  */
+
+#define OSCCTRL_INTENSET_XOSCRDY_Pos          _U_(0)                                               /**< (OSCCTRL_INTENSET Position) XOSC x Ready Interrupt Enable */
+#define OSCCTRL_INTENSET_XOSCRDY_Msk          (_U_(0x3) << OSCCTRL_INTENSET_XOSCRDY_Pos)           /**< (OSCCTRL_INTENSET Mask) XOSCRDY */
+#define OSCCTRL_INTENSET_XOSCRDY(value)       (OSCCTRL_INTENSET_XOSCRDY_Msk & ((value) << OSCCTRL_INTENSET_XOSCRDY_Pos)) 
+#define OSCCTRL_INTENSET_XOSCFAIL_Pos         _U_(2)                                               /**< (OSCCTRL_INTENSET Position) XOSC x Clock Failure Detector Interrupt Enable */
+#define OSCCTRL_INTENSET_XOSCFAIL_Msk         (_U_(0x3) << OSCCTRL_INTENSET_XOSCFAIL_Pos)          /**< (OSCCTRL_INTENSET Mask) XOSCFAIL */
+#define OSCCTRL_INTENSET_XOSCFAIL(value)      (OSCCTRL_INTENSET_XOSCFAIL_Msk & ((value) << OSCCTRL_INTENSET_XOSCFAIL_Pos)) 
+
+/* -------- OSCCTRL_INTFLAG : (OSCCTRL Offset: 0x0C) (R/W 32) Interrupt Flag Status and Clear -------- */
+#define OSCCTRL_INTFLAG_RESETVALUE            _U_(0x00)                                            /**<  (OSCCTRL_INTFLAG) Interrupt Flag Status and Clear  Reset Value */
+
+#define OSCCTRL_INTFLAG_XOSCRDY0_Pos          _U_(0)                                               /**< (OSCCTRL_INTFLAG) XOSC 0 Ready Position */
+#define OSCCTRL_INTFLAG_XOSCRDY0_Msk          (_U_(0x1) << OSCCTRL_INTFLAG_XOSCRDY0_Pos)           /**< (OSCCTRL_INTFLAG) XOSC 0 Ready Mask */
+#define OSCCTRL_INTFLAG_XOSCRDY0(value)       (OSCCTRL_INTFLAG_XOSCRDY0_Msk & ((value) << OSCCTRL_INTFLAG_XOSCRDY0_Pos))
+#define OSCCTRL_INTFLAG_XOSCRDY1_Pos          _U_(1)                                               /**< (OSCCTRL_INTFLAG) XOSC 1 Ready Position */
+#define OSCCTRL_INTFLAG_XOSCRDY1_Msk          (_U_(0x1) << OSCCTRL_INTFLAG_XOSCRDY1_Pos)           /**< (OSCCTRL_INTFLAG) XOSC 1 Ready Mask */
+#define OSCCTRL_INTFLAG_XOSCRDY1(value)       (OSCCTRL_INTFLAG_XOSCRDY1_Msk & ((value) << OSCCTRL_INTFLAG_XOSCRDY1_Pos))
+#define OSCCTRL_INTFLAG_XOSCFAIL0_Pos         _U_(2)                                               /**< (OSCCTRL_INTFLAG) XOSC 0 Clock Failure Detector Position */
+#define OSCCTRL_INTFLAG_XOSCFAIL0_Msk         (_U_(0x1) << OSCCTRL_INTFLAG_XOSCFAIL0_Pos)          /**< (OSCCTRL_INTFLAG) XOSC 0 Clock Failure Detector Mask */
+#define OSCCTRL_INTFLAG_XOSCFAIL0(value)      (OSCCTRL_INTFLAG_XOSCFAIL0_Msk & ((value) << OSCCTRL_INTFLAG_XOSCFAIL0_Pos))
+#define OSCCTRL_INTFLAG_XOSCFAIL1_Pos         _U_(3)                                               /**< (OSCCTRL_INTFLAG) XOSC 1 Clock Failure Detector Position */
+#define OSCCTRL_INTFLAG_XOSCFAIL1_Msk         (_U_(0x1) << OSCCTRL_INTFLAG_XOSCFAIL1_Pos)          /**< (OSCCTRL_INTFLAG) XOSC 1 Clock Failure Detector Mask */
+#define OSCCTRL_INTFLAG_XOSCFAIL1(value)      (OSCCTRL_INTFLAG_XOSCFAIL1_Msk & ((value) << OSCCTRL_INTFLAG_XOSCFAIL1_Pos))
+#define OSCCTRL_INTFLAG_DFLLRDY_Pos           _U_(8)                                               /**< (OSCCTRL_INTFLAG) DFLL Ready Position */
+#define OSCCTRL_INTFLAG_DFLLRDY_Msk           (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRDY_Pos)            /**< (OSCCTRL_INTFLAG) DFLL Ready Mask */
+#define OSCCTRL_INTFLAG_DFLLRDY(value)        (OSCCTRL_INTFLAG_DFLLRDY_Msk & ((value) << OSCCTRL_INTFLAG_DFLLRDY_Pos))
+#define OSCCTRL_INTFLAG_DFLLOOB_Pos           _U_(9)                                               /**< (OSCCTRL_INTFLAG) DFLL Out Of Bounds Position */
+#define OSCCTRL_INTFLAG_DFLLOOB_Msk           (_U_(0x1) << OSCCTRL_INTFLAG_DFLLOOB_Pos)            /**< (OSCCTRL_INTFLAG) DFLL Out Of Bounds Mask */
+#define OSCCTRL_INTFLAG_DFLLOOB(value)        (OSCCTRL_INTFLAG_DFLLOOB_Msk & ((value) << OSCCTRL_INTFLAG_DFLLOOB_Pos))
+#define OSCCTRL_INTFLAG_DFLLLCKF_Pos          _U_(10)                                              /**< (OSCCTRL_INTFLAG) DFLL Lock Fine Position */
+#define OSCCTRL_INTFLAG_DFLLLCKF_Msk          (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKF_Pos)           /**< (OSCCTRL_INTFLAG) DFLL Lock Fine Mask */
+#define OSCCTRL_INTFLAG_DFLLLCKF(value)       (OSCCTRL_INTFLAG_DFLLLCKF_Msk & ((value) << OSCCTRL_INTFLAG_DFLLLCKF_Pos))
+#define OSCCTRL_INTFLAG_DFLLLCKC_Pos          _U_(11)                                              /**< (OSCCTRL_INTFLAG) DFLL Lock Coarse Position */
+#define OSCCTRL_INTFLAG_DFLLLCKC_Msk          (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKC_Pos)           /**< (OSCCTRL_INTFLAG) DFLL Lock Coarse Mask */
+#define OSCCTRL_INTFLAG_DFLLLCKC(value)       (OSCCTRL_INTFLAG_DFLLLCKC_Msk & ((value) << OSCCTRL_INTFLAG_DFLLLCKC_Pos))
+#define OSCCTRL_INTFLAG_DFLLRCS_Pos           _U_(12)                                              /**< (OSCCTRL_INTFLAG) DFLL Reference Clock Stopped Position */
+#define OSCCTRL_INTFLAG_DFLLRCS_Msk           (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRCS_Pos)            /**< (OSCCTRL_INTFLAG) DFLL Reference Clock Stopped Mask */
+#define OSCCTRL_INTFLAG_DFLLRCS(value)        (OSCCTRL_INTFLAG_DFLLRCS_Msk & ((value) << OSCCTRL_INTFLAG_DFLLRCS_Pos))
+#define OSCCTRL_INTFLAG_DPLL0LCKR_Pos         _U_(16)                                              /**< (OSCCTRL_INTFLAG) DPLL0 Lock Rise Position */
+#define OSCCTRL_INTFLAG_DPLL0LCKR_Msk         (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LCKR_Pos)          /**< (OSCCTRL_INTFLAG) DPLL0 Lock Rise Mask */
+#define OSCCTRL_INTFLAG_DPLL0LCKR(value)      (OSCCTRL_INTFLAG_DPLL0LCKR_Msk & ((value) << OSCCTRL_INTFLAG_DPLL0LCKR_Pos))
+#define OSCCTRL_INTFLAG_DPLL0LCKF_Pos         _U_(17)                                              /**< (OSCCTRL_INTFLAG) DPLL0 Lock Fall Position */
+#define OSCCTRL_INTFLAG_DPLL0LCKF_Msk         (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LCKF_Pos)          /**< (OSCCTRL_INTFLAG) DPLL0 Lock Fall Mask */
+#define OSCCTRL_INTFLAG_DPLL0LCKF(value)      (OSCCTRL_INTFLAG_DPLL0LCKF_Msk & ((value) << OSCCTRL_INTFLAG_DPLL0LCKF_Pos))
+#define OSCCTRL_INTFLAG_DPLL0LTO_Pos          _U_(18)                                              /**< (OSCCTRL_INTFLAG) DPLL0 Lock Timeout Position */
+#define OSCCTRL_INTFLAG_DPLL0LTO_Msk          (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LTO_Pos)           /**< (OSCCTRL_INTFLAG) DPLL0 Lock Timeout Mask */
+#define OSCCTRL_INTFLAG_DPLL0LTO(value)       (OSCCTRL_INTFLAG_DPLL0LTO_Msk & ((value) << OSCCTRL_INTFLAG_DPLL0LTO_Pos))
+#define OSCCTRL_INTFLAG_DPLL0LDRTO_Pos        _U_(19)                                              /**< (OSCCTRL_INTFLAG) DPLL0 Loop Divider Ratio Update Complete Position */
+#define OSCCTRL_INTFLAG_DPLL0LDRTO_Msk        (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LDRTO_Pos)         /**< (OSCCTRL_INTFLAG) DPLL0 Loop Divider Ratio Update Complete Mask */
+#define OSCCTRL_INTFLAG_DPLL0LDRTO(value)     (OSCCTRL_INTFLAG_DPLL0LDRTO_Msk & ((value) << OSCCTRL_INTFLAG_DPLL0LDRTO_Pos))
+#define OSCCTRL_INTFLAG_DPLL1LCKR_Pos         _U_(24)                                              /**< (OSCCTRL_INTFLAG) DPLL1 Lock Rise Position */
+#define OSCCTRL_INTFLAG_DPLL1LCKR_Msk         (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LCKR_Pos)          /**< (OSCCTRL_INTFLAG) DPLL1 Lock Rise Mask */
+#define OSCCTRL_INTFLAG_DPLL1LCKR(value)      (OSCCTRL_INTFLAG_DPLL1LCKR_Msk & ((value) << OSCCTRL_INTFLAG_DPLL1LCKR_Pos))
+#define OSCCTRL_INTFLAG_DPLL1LCKF_Pos         _U_(25)                                              /**< (OSCCTRL_INTFLAG) DPLL1 Lock Fall Position */
+#define OSCCTRL_INTFLAG_DPLL1LCKF_Msk         (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LCKF_Pos)          /**< (OSCCTRL_INTFLAG) DPLL1 Lock Fall Mask */
+#define OSCCTRL_INTFLAG_DPLL1LCKF(value)      (OSCCTRL_INTFLAG_DPLL1LCKF_Msk & ((value) << OSCCTRL_INTFLAG_DPLL1LCKF_Pos))
+#define OSCCTRL_INTFLAG_DPLL1LTO_Pos          _U_(26)                                              /**< (OSCCTRL_INTFLAG) DPLL1 Lock Timeout Position */
+#define OSCCTRL_INTFLAG_DPLL1LTO_Msk          (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LTO_Pos)           /**< (OSCCTRL_INTFLAG) DPLL1 Lock Timeout Mask */
+#define OSCCTRL_INTFLAG_DPLL1LTO(value)       (OSCCTRL_INTFLAG_DPLL1LTO_Msk & ((value) << OSCCTRL_INTFLAG_DPLL1LTO_Pos))
+#define OSCCTRL_INTFLAG_DPLL1LDRTO_Pos        _U_(27)                                              /**< (OSCCTRL_INTFLAG) DPLL1 Loop Divider Ratio Update Complete Position */
+#define OSCCTRL_INTFLAG_DPLL1LDRTO_Msk        (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LDRTO_Pos)         /**< (OSCCTRL_INTFLAG) DPLL1 Loop Divider Ratio Update Complete Mask */
+#define OSCCTRL_INTFLAG_DPLL1LDRTO(value)     (OSCCTRL_INTFLAG_DPLL1LDRTO_Msk & ((value) << OSCCTRL_INTFLAG_DPLL1LDRTO_Pos))
+#define OSCCTRL_INTFLAG_Msk                   _U_(0x0F0F1F0F)                                      /**< (OSCCTRL_INTFLAG) Register Mask  */
+
+#define OSCCTRL_INTFLAG_XOSCRDY_Pos           _U_(0)                                               /**< (OSCCTRL_INTFLAG Position) XOSC x Ready */
+#define OSCCTRL_INTFLAG_XOSCRDY_Msk           (_U_(0x3) << OSCCTRL_INTFLAG_XOSCRDY_Pos)            /**< (OSCCTRL_INTFLAG Mask) XOSCRDY */
+#define OSCCTRL_INTFLAG_XOSCRDY(value)        (OSCCTRL_INTFLAG_XOSCRDY_Msk & ((value) << OSCCTRL_INTFLAG_XOSCRDY_Pos)) 
+#define OSCCTRL_INTFLAG_XOSCFAIL_Pos          _U_(2)                                               /**< (OSCCTRL_INTFLAG Position) XOSC x Clock Failure Detector */
+#define OSCCTRL_INTFLAG_XOSCFAIL_Msk          (_U_(0x3) << OSCCTRL_INTFLAG_XOSCFAIL_Pos)           /**< (OSCCTRL_INTFLAG Mask) XOSCFAIL */
+#define OSCCTRL_INTFLAG_XOSCFAIL(value)       (OSCCTRL_INTFLAG_XOSCFAIL_Msk & ((value) << OSCCTRL_INTFLAG_XOSCFAIL_Pos)) 
+
+/* -------- OSCCTRL_STATUS : (OSCCTRL Offset: 0x10) ( R/ 32) Status -------- */
+#define OSCCTRL_STATUS_RESETVALUE             _U_(0x00)                                            /**<  (OSCCTRL_STATUS) Status  Reset Value */
+
+#define OSCCTRL_STATUS_XOSCRDY0_Pos           _U_(0)                                               /**< (OSCCTRL_STATUS) XOSC 0 Ready Position */
+#define OSCCTRL_STATUS_XOSCRDY0_Msk           (_U_(0x1) << OSCCTRL_STATUS_XOSCRDY0_Pos)            /**< (OSCCTRL_STATUS) XOSC 0 Ready Mask */
+#define OSCCTRL_STATUS_XOSCRDY0(value)        (OSCCTRL_STATUS_XOSCRDY0_Msk & ((value) << OSCCTRL_STATUS_XOSCRDY0_Pos))
+#define OSCCTRL_STATUS_XOSCRDY1_Pos           _U_(1)                                               /**< (OSCCTRL_STATUS) XOSC 1 Ready Position */
+#define OSCCTRL_STATUS_XOSCRDY1_Msk           (_U_(0x1) << OSCCTRL_STATUS_XOSCRDY1_Pos)            /**< (OSCCTRL_STATUS) XOSC 1 Ready Mask */
+#define OSCCTRL_STATUS_XOSCRDY1(value)        (OSCCTRL_STATUS_XOSCRDY1_Msk & ((value) << OSCCTRL_STATUS_XOSCRDY1_Pos))
+#define OSCCTRL_STATUS_XOSCFAIL0_Pos          _U_(2)                                               /**< (OSCCTRL_STATUS) XOSC 0 Clock Failure Detector Position */
+#define OSCCTRL_STATUS_XOSCFAIL0_Msk          (_U_(0x1) << OSCCTRL_STATUS_XOSCFAIL0_Pos)           /**< (OSCCTRL_STATUS) XOSC 0 Clock Failure Detector Mask */
+#define OSCCTRL_STATUS_XOSCFAIL0(value)       (OSCCTRL_STATUS_XOSCFAIL0_Msk & ((value) << OSCCTRL_STATUS_XOSCFAIL0_Pos))
+#define OSCCTRL_STATUS_XOSCFAIL1_Pos          _U_(3)                                               /**< (OSCCTRL_STATUS) XOSC 1 Clock Failure Detector Position */
+#define OSCCTRL_STATUS_XOSCFAIL1_Msk          (_U_(0x1) << OSCCTRL_STATUS_XOSCFAIL1_Pos)           /**< (OSCCTRL_STATUS) XOSC 1 Clock Failure Detector Mask */
+#define OSCCTRL_STATUS_XOSCFAIL1(value)       (OSCCTRL_STATUS_XOSCFAIL1_Msk & ((value) << OSCCTRL_STATUS_XOSCFAIL1_Pos))
+#define OSCCTRL_STATUS_XOSCCKSW0_Pos          _U_(4)                                               /**< (OSCCTRL_STATUS) XOSC 0 Clock Switch Position */
+#define OSCCTRL_STATUS_XOSCCKSW0_Msk          (_U_(0x1) << OSCCTRL_STATUS_XOSCCKSW0_Pos)           /**< (OSCCTRL_STATUS) XOSC 0 Clock Switch Mask */
+#define OSCCTRL_STATUS_XOSCCKSW0(value)       (OSCCTRL_STATUS_XOSCCKSW0_Msk & ((value) << OSCCTRL_STATUS_XOSCCKSW0_Pos))
+#define OSCCTRL_STATUS_XOSCCKSW1_Pos          _U_(5)                                               /**< (OSCCTRL_STATUS) XOSC 1 Clock Switch Position */
+#define OSCCTRL_STATUS_XOSCCKSW1_Msk          (_U_(0x1) << OSCCTRL_STATUS_XOSCCKSW1_Pos)           /**< (OSCCTRL_STATUS) XOSC 1 Clock Switch Mask */
+#define OSCCTRL_STATUS_XOSCCKSW1(value)       (OSCCTRL_STATUS_XOSCCKSW1_Msk & ((value) << OSCCTRL_STATUS_XOSCCKSW1_Pos))
+#define OSCCTRL_STATUS_DFLLRDY_Pos            _U_(8)                                               /**< (OSCCTRL_STATUS) DFLL Ready Position */
+#define OSCCTRL_STATUS_DFLLRDY_Msk            (_U_(0x1) << OSCCTRL_STATUS_DFLLRDY_Pos)             /**< (OSCCTRL_STATUS) DFLL Ready Mask */
+#define OSCCTRL_STATUS_DFLLRDY(value)         (OSCCTRL_STATUS_DFLLRDY_Msk & ((value) << OSCCTRL_STATUS_DFLLRDY_Pos))
+#define OSCCTRL_STATUS_DFLLOOB_Pos            _U_(9)                                               /**< (OSCCTRL_STATUS) DFLL Out Of Bounds Position */
+#define OSCCTRL_STATUS_DFLLOOB_Msk            (_U_(0x1) << OSCCTRL_STATUS_DFLLOOB_Pos)             /**< (OSCCTRL_STATUS) DFLL Out Of Bounds Mask */
+#define OSCCTRL_STATUS_DFLLOOB(value)         (OSCCTRL_STATUS_DFLLOOB_Msk & ((value) << OSCCTRL_STATUS_DFLLOOB_Pos))
+#define OSCCTRL_STATUS_DFLLLCKF_Pos           _U_(10)                                              /**< (OSCCTRL_STATUS) DFLL Lock Fine Position */
+#define OSCCTRL_STATUS_DFLLLCKF_Msk           (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKF_Pos)            /**< (OSCCTRL_STATUS) DFLL Lock Fine Mask */
+#define OSCCTRL_STATUS_DFLLLCKF(value)        (OSCCTRL_STATUS_DFLLLCKF_Msk & ((value) << OSCCTRL_STATUS_DFLLLCKF_Pos))
+#define OSCCTRL_STATUS_DFLLLCKC_Pos           _U_(11)                                              /**< (OSCCTRL_STATUS) DFLL Lock Coarse Position */
+#define OSCCTRL_STATUS_DFLLLCKC_Msk           (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKC_Pos)            /**< (OSCCTRL_STATUS) DFLL Lock Coarse Mask */
+#define OSCCTRL_STATUS_DFLLLCKC(value)        (OSCCTRL_STATUS_DFLLLCKC_Msk & ((value) << OSCCTRL_STATUS_DFLLLCKC_Pos))
+#define OSCCTRL_STATUS_DFLLRCS_Pos            _U_(12)                                              /**< (OSCCTRL_STATUS) DFLL Reference Clock Stopped Position */
+#define OSCCTRL_STATUS_DFLLRCS_Msk            (_U_(0x1) << OSCCTRL_STATUS_DFLLRCS_Pos)             /**< (OSCCTRL_STATUS) DFLL Reference Clock Stopped Mask */
+#define OSCCTRL_STATUS_DFLLRCS(value)         (OSCCTRL_STATUS_DFLLRCS_Msk & ((value) << OSCCTRL_STATUS_DFLLRCS_Pos))
+#define OSCCTRL_STATUS_DPLL0LCKR_Pos          _U_(16)                                              /**< (OSCCTRL_STATUS) DPLL0 Lock Rise Position */
+#define OSCCTRL_STATUS_DPLL0LCKR_Msk          (_U_(0x1) << OSCCTRL_STATUS_DPLL0LCKR_Pos)           /**< (OSCCTRL_STATUS) DPLL0 Lock Rise Mask */
+#define OSCCTRL_STATUS_DPLL0LCKR(value)       (OSCCTRL_STATUS_DPLL0LCKR_Msk & ((value) << OSCCTRL_STATUS_DPLL0LCKR_Pos))
+#define OSCCTRL_STATUS_DPLL0LCKF_Pos          _U_(17)                                              /**< (OSCCTRL_STATUS) DPLL0 Lock Fall Position */
+#define OSCCTRL_STATUS_DPLL0LCKF_Msk          (_U_(0x1) << OSCCTRL_STATUS_DPLL0LCKF_Pos)           /**< (OSCCTRL_STATUS) DPLL0 Lock Fall Mask */
+#define OSCCTRL_STATUS_DPLL0LCKF(value)       (OSCCTRL_STATUS_DPLL0LCKF_Msk & ((value) << OSCCTRL_STATUS_DPLL0LCKF_Pos))
+#define OSCCTRL_STATUS_DPLL0TO_Pos            _U_(18)                                              /**< (OSCCTRL_STATUS) DPLL0 Timeout Position */
+#define OSCCTRL_STATUS_DPLL0TO_Msk            (_U_(0x1) << OSCCTRL_STATUS_DPLL0TO_Pos)             /**< (OSCCTRL_STATUS) DPLL0 Timeout Mask */
+#define OSCCTRL_STATUS_DPLL0TO(value)         (OSCCTRL_STATUS_DPLL0TO_Msk & ((value) << OSCCTRL_STATUS_DPLL0TO_Pos))
+#define OSCCTRL_STATUS_DPLL0LDRTO_Pos         _U_(19)                                              /**< (OSCCTRL_STATUS) DPLL0 Loop Divider Ratio Update Complete Position */
+#define OSCCTRL_STATUS_DPLL0LDRTO_Msk         (_U_(0x1) << OSCCTRL_STATUS_DPLL0LDRTO_Pos)          /**< (OSCCTRL_STATUS) DPLL0 Loop Divider Ratio Update Complete Mask */
+#define OSCCTRL_STATUS_DPLL0LDRTO(value)      (OSCCTRL_STATUS_DPLL0LDRTO_Msk & ((value) << OSCCTRL_STATUS_DPLL0LDRTO_Pos))
+#define OSCCTRL_STATUS_DPLL1LCKR_Pos          _U_(24)                                              /**< (OSCCTRL_STATUS) DPLL1 Lock Rise Position */
+#define OSCCTRL_STATUS_DPLL1LCKR_Msk          (_U_(0x1) << OSCCTRL_STATUS_DPLL1LCKR_Pos)           /**< (OSCCTRL_STATUS) DPLL1 Lock Rise Mask */
+#define OSCCTRL_STATUS_DPLL1LCKR(value)       (OSCCTRL_STATUS_DPLL1LCKR_Msk & ((value) << OSCCTRL_STATUS_DPLL1LCKR_Pos))
+#define OSCCTRL_STATUS_DPLL1LCKF_Pos          _U_(25)                                              /**< (OSCCTRL_STATUS) DPLL1 Lock Fall Position */
+#define OSCCTRL_STATUS_DPLL1LCKF_Msk          (_U_(0x1) << OSCCTRL_STATUS_DPLL1LCKF_Pos)           /**< (OSCCTRL_STATUS) DPLL1 Lock Fall Mask */
+#define OSCCTRL_STATUS_DPLL1LCKF(value)       (OSCCTRL_STATUS_DPLL1LCKF_Msk & ((value) << OSCCTRL_STATUS_DPLL1LCKF_Pos))
+#define OSCCTRL_STATUS_DPLL1TO_Pos            _U_(26)                                              /**< (OSCCTRL_STATUS) DPLL1 Timeout Position */
+#define OSCCTRL_STATUS_DPLL1TO_Msk            (_U_(0x1) << OSCCTRL_STATUS_DPLL1TO_Pos)             /**< (OSCCTRL_STATUS) DPLL1 Timeout Mask */
+#define OSCCTRL_STATUS_DPLL1TO(value)         (OSCCTRL_STATUS_DPLL1TO_Msk & ((value) << OSCCTRL_STATUS_DPLL1TO_Pos))
+#define OSCCTRL_STATUS_DPLL1LDRTO_Pos         _U_(27)                                              /**< (OSCCTRL_STATUS) DPLL1 Loop Divider Ratio Update Complete Position */
+#define OSCCTRL_STATUS_DPLL1LDRTO_Msk         (_U_(0x1) << OSCCTRL_STATUS_DPLL1LDRTO_Pos)          /**< (OSCCTRL_STATUS) DPLL1 Loop Divider Ratio Update Complete Mask */
+#define OSCCTRL_STATUS_DPLL1LDRTO(value)      (OSCCTRL_STATUS_DPLL1LDRTO_Msk & ((value) << OSCCTRL_STATUS_DPLL1LDRTO_Pos))
+#define OSCCTRL_STATUS_Msk                    _U_(0x0F0F1F3F)                                      /**< (OSCCTRL_STATUS) Register Mask  */
+
+#define OSCCTRL_STATUS_XOSCRDY_Pos            _U_(0)                                               /**< (OSCCTRL_STATUS Position) XOSC x Ready */
+#define OSCCTRL_STATUS_XOSCRDY_Msk            (_U_(0x3) << OSCCTRL_STATUS_XOSCRDY_Pos)             /**< (OSCCTRL_STATUS Mask) XOSCRDY */
+#define OSCCTRL_STATUS_XOSCRDY(value)         (OSCCTRL_STATUS_XOSCRDY_Msk & ((value) << OSCCTRL_STATUS_XOSCRDY_Pos)) 
+#define OSCCTRL_STATUS_XOSCFAIL_Pos           _U_(2)                                               /**< (OSCCTRL_STATUS Position) XOSC x Clock Failure Detector */
+#define OSCCTRL_STATUS_XOSCFAIL_Msk           (_U_(0x3) << OSCCTRL_STATUS_XOSCFAIL_Pos)            /**< (OSCCTRL_STATUS Mask) XOSCFAIL */
+#define OSCCTRL_STATUS_XOSCFAIL(value)        (OSCCTRL_STATUS_XOSCFAIL_Msk & ((value) << OSCCTRL_STATUS_XOSCFAIL_Pos)) 
+#define OSCCTRL_STATUS_XOSCCKSW_Pos           _U_(4)                                               /**< (OSCCTRL_STATUS Position) XOSC x Clock Switch */
+#define OSCCTRL_STATUS_XOSCCKSW_Msk           (_U_(0x3) << OSCCTRL_STATUS_XOSCCKSW_Pos)            /**< (OSCCTRL_STATUS Mask) XOSCCKSW */
+#define OSCCTRL_STATUS_XOSCCKSW(value)        (OSCCTRL_STATUS_XOSCCKSW_Msk & ((value) << OSCCTRL_STATUS_XOSCCKSW_Pos)) 
+
+/* -------- OSCCTRL_XOSCCTRL : (OSCCTRL Offset: 0x14) (R/W 32) External Multipurpose Crystal Oscillator Control -------- */
+#define OSCCTRL_XOSCCTRL_RESETVALUE           _U_(0x80)                                            /**<  (OSCCTRL_XOSCCTRL) External Multipurpose Crystal Oscillator Control  Reset Value */
+
+#define OSCCTRL_XOSCCTRL_ENABLE_Pos           _U_(1)                                               /**< (OSCCTRL_XOSCCTRL) Oscillator Enable Position */
+#define OSCCTRL_XOSCCTRL_ENABLE_Msk           (_U_(0x1) << OSCCTRL_XOSCCTRL_ENABLE_Pos)            /**< (OSCCTRL_XOSCCTRL) Oscillator Enable Mask */
+#define OSCCTRL_XOSCCTRL_ENABLE(value)        (OSCCTRL_XOSCCTRL_ENABLE_Msk & ((value) << OSCCTRL_XOSCCTRL_ENABLE_Pos))
+#define OSCCTRL_XOSCCTRL_XTALEN_Pos           _U_(2)                                               /**< (OSCCTRL_XOSCCTRL) Crystal Oscillator Enable Position */
+#define OSCCTRL_XOSCCTRL_XTALEN_Msk           (_U_(0x1) << OSCCTRL_XOSCCTRL_XTALEN_Pos)            /**< (OSCCTRL_XOSCCTRL) Crystal Oscillator Enable Mask */
+#define OSCCTRL_XOSCCTRL_XTALEN(value)        (OSCCTRL_XOSCCTRL_XTALEN_Msk & ((value) << OSCCTRL_XOSCCTRL_XTALEN_Pos))
+#define OSCCTRL_XOSCCTRL_RUNSTDBY_Pos         _U_(6)                                               /**< (OSCCTRL_XOSCCTRL) Run in Standby Position */
+#define OSCCTRL_XOSCCTRL_RUNSTDBY_Msk         (_U_(0x1) << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos)          /**< (OSCCTRL_XOSCCTRL) Run in Standby Mask */
+#define OSCCTRL_XOSCCTRL_RUNSTDBY(value)      (OSCCTRL_XOSCCTRL_RUNSTDBY_Msk & ((value) << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos))
+#define OSCCTRL_XOSCCTRL_ONDEMAND_Pos         _U_(7)                                               /**< (OSCCTRL_XOSCCTRL) On Demand Control Position */
+#define OSCCTRL_XOSCCTRL_ONDEMAND_Msk         (_U_(0x1) << OSCCTRL_XOSCCTRL_ONDEMAND_Pos)          /**< (OSCCTRL_XOSCCTRL) On Demand Control Mask */
+#define OSCCTRL_XOSCCTRL_ONDEMAND(value)      (OSCCTRL_XOSCCTRL_ONDEMAND_Msk & ((value) << OSCCTRL_XOSCCTRL_ONDEMAND_Pos))
+#define OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos       _U_(8)                                               /**< (OSCCTRL_XOSCCTRL) Low Buffer Gain Enable Position */
+#define OSCCTRL_XOSCCTRL_LOWBUFGAIN_Msk       (_U_(0x1) << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos)        /**< (OSCCTRL_XOSCCTRL) Low Buffer Gain Enable Mask */
+#define OSCCTRL_XOSCCTRL_LOWBUFGAIN(value)    (OSCCTRL_XOSCCTRL_LOWBUFGAIN_Msk & ((value) << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos))
+#define OSCCTRL_XOSCCTRL_IPTAT_Pos            _U_(9)                                               /**< (OSCCTRL_XOSCCTRL) Oscillator Current Reference Position */
+#define OSCCTRL_XOSCCTRL_IPTAT_Msk            (_U_(0x3) << OSCCTRL_XOSCCTRL_IPTAT_Pos)             /**< (OSCCTRL_XOSCCTRL) Oscillator Current Reference Mask */
+#define OSCCTRL_XOSCCTRL_IPTAT(value)         (OSCCTRL_XOSCCTRL_IPTAT_Msk & ((value) << OSCCTRL_XOSCCTRL_IPTAT_Pos))
+#define OSCCTRL_XOSCCTRL_IMULT_Pos            _U_(11)                                              /**< (OSCCTRL_XOSCCTRL) Oscillator Current Multiplier Position */
+#define OSCCTRL_XOSCCTRL_IMULT_Msk            (_U_(0xF) << OSCCTRL_XOSCCTRL_IMULT_Pos)             /**< (OSCCTRL_XOSCCTRL) Oscillator Current Multiplier Mask */
+#define OSCCTRL_XOSCCTRL_IMULT(value)         (OSCCTRL_XOSCCTRL_IMULT_Msk & ((value) << OSCCTRL_XOSCCTRL_IMULT_Pos))
+#define OSCCTRL_XOSCCTRL_ENALC_Pos            _U_(15)                                              /**< (OSCCTRL_XOSCCTRL) Automatic Loop Control Enable Position */
+#define OSCCTRL_XOSCCTRL_ENALC_Msk            (_U_(0x1) << OSCCTRL_XOSCCTRL_ENALC_Pos)             /**< (OSCCTRL_XOSCCTRL) Automatic Loop Control Enable Mask */
+#define OSCCTRL_XOSCCTRL_ENALC(value)         (OSCCTRL_XOSCCTRL_ENALC_Msk & ((value) << OSCCTRL_XOSCCTRL_ENALC_Pos))
+#define OSCCTRL_XOSCCTRL_CFDEN_Pos            _U_(16)                                              /**< (OSCCTRL_XOSCCTRL) Clock Failure Detector Enable Position */
+#define OSCCTRL_XOSCCTRL_CFDEN_Msk            (_U_(0x1) << OSCCTRL_XOSCCTRL_CFDEN_Pos)             /**< (OSCCTRL_XOSCCTRL) Clock Failure Detector Enable Mask */
+#define OSCCTRL_XOSCCTRL_CFDEN(value)         (OSCCTRL_XOSCCTRL_CFDEN_Msk & ((value) << OSCCTRL_XOSCCTRL_CFDEN_Pos))
+#define OSCCTRL_XOSCCTRL_SWBEN_Pos            _U_(17)                                              /**< (OSCCTRL_XOSCCTRL) Xosc Clock Switch Enable Position */
+#define OSCCTRL_XOSCCTRL_SWBEN_Msk            (_U_(0x1) << OSCCTRL_XOSCCTRL_SWBEN_Pos)             /**< (OSCCTRL_XOSCCTRL) Xosc Clock Switch Enable Mask */
+#define OSCCTRL_XOSCCTRL_SWBEN(value)         (OSCCTRL_XOSCCTRL_SWBEN_Msk & ((value) << OSCCTRL_XOSCCTRL_SWBEN_Pos))
+#define OSCCTRL_XOSCCTRL_STARTUP_Pos          _U_(20)                                              /**< (OSCCTRL_XOSCCTRL) Start-Up Time Position */
+#define OSCCTRL_XOSCCTRL_STARTUP_Msk          (_U_(0xF) << OSCCTRL_XOSCCTRL_STARTUP_Pos)           /**< (OSCCTRL_XOSCCTRL) Start-Up Time Mask */
+#define OSCCTRL_XOSCCTRL_STARTUP(value)       (OSCCTRL_XOSCCTRL_STARTUP_Msk & ((value) << OSCCTRL_XOSCCTRL_STARTUP_Pos))
+#define   OSCCTRL_XOSCCTRL_STARTUP_CYCLE1_Val _U_(0x0)                                             /**< (OSCCTRL_XOSCCTRL) 31 us  */
+#define   OSCCTRL_XOSCCTRL_STARTUP_CYCLE2_Val _U_(0x1)                                             /**< (OSCCTRL_XOSCCTRL) 61 us  */
+#define   OSCCTRL_XOSCCTRL_STARTUP_CYCLE4_Val _U_(0x2)                                             /**< (OSCCTRL_XOSCCTRL) 122 us  */
+#define   OSCCTRL_XOSCCTRL_STARTUP_CYCLE8_Val _U_(0x3)                                             /**< (OSCCTRL_XOSCCTRL) 244 us  */
+#define   OSCCTRL_XOSCCTRL_STARTUP_CYCLE16_Val _U_(0x4)                                             /**< (OSCCTRL_XOSCCTRL) 488 us  */
+#define   OSCCTRL_XOSCCTRL_STARTUP_CYCLE32_Val _U_(0x5)                                             /**< (OSCCTRL_XOSCCTRL) 977 us  */
+#define   OSCCTRL_XOSCCTRL_STARTUP_CYCLE64_Val _U_(0x6)                                             /**< (OSCCTRL_XOSCCTRL) 1953 us  */
+#define   OSCCTRL_XOSCCTRL_STARTUP_CYCLE128_Val _U_(0x7)                                             /**< (OSCCTRL_XOSCCTRL) 3906 us  */
+#define   OSCCTRL_XOSCCTRL_STARTUP_CYCLE256_Val _U_(0x8)                                             /**< (OSCCTRL_XOSCCTRL) 7813 us  */
+#define   OSCCTRL_XOSCCTRL_STARTUP_CYCLE512_Val _U_(0x9)                                             /**< (OSCCTRL_XOSCCTRL) 15625 us  */
+#define   OSCCTRL_XOSCCTRL_STARTUP_CYCLE1024_Val _U_(0xA)                                             /**< (OSCCTRL_XOSCCTRL) 31250 us  */
+#define   OSCCTRL_XOSCCTRL_STARTUP_CYCLE2048_Val _U_(0xB)                                             /**< (OSCCTRL_XOSCCTRL) 62500 us  */
+#define   OSCCTRL_XOSCCTRL_STARTUP_CYCLE4096_Val _U_(0xC)                                             /**< (OSCCTRL_XOSCCTRL) 125000 us  */
+#define   OSCCTRL_XOSCCTRL_STARTUP_CYCLE8192_Val _U_(0xD)                                             /**< (OSCCTRL_XOSCCTRL) 250000 us  */
+#define   OSCCTRL_XOSCCTRL_STARTUP_CYCLE16384_Val _U_(0xE)                                             /**< (OSCCTRL_XOSCCTRL) 500000 us  */
+#define   OSCCTRL_XOSCCTRL_STARTUP_CYCLE32768_Val _U_(0xF)                                             /**< (OSCCTRL_XOSCCTRL) 1000000 us  */
+#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE1       (OSCCTRL_XOSCCTRL_STARTUP_CYCLE1_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 31 us Position  */
+#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE2       (OSCCTRL_XOSCCTRL_STARTUP_CYCLE2_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 61 us Position  */
+#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE4       (OSCCTRL_XOSCCTRL_STARTUP_CYCLE4_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 122 us Position  */
+#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE8       (OSCCTRL_XOSCCTRL_STARTUP_CYCLE8_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 244 us Position  */
+#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE16      (OSCCTRL_XOSCCTRL_STARTUP_CYCLE16_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 488 us Position  */
+#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE32      (OSCCTRL_XOSCCTRL_STARTUP_CYCLE32_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 977 us Position  */
+#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE64      (OSCCTRL_XOSCCTRL_STARTUP_CYCLE64_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 1953 us Position  */
+#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE128     (OSCCTRL_XOSCCTRL_STARTUP_CYCLE128_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 3906 us Position  */
+#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE256     (OSCCTRL_XOSCCTRL_STARTUP_CYCLE256_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 7813 us Position  */
+#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE512     (OSCCTRL_XOSCCTRL_STARTUP_CYCLE512_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 15625 us Position  */
+#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE1024    (OSCCTRL_XOSCCTRL_STARTUP_CYCLE1024_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 31250 us Position  */
+#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE2048    (OSCCTRL_XOSCCTRL_STARTUP_CYCLE2048_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 62500 us Position  */
+#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE4096    (OSCCTRL_XOSCCTRL_STARTUP_CYCLE4096_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 125000 us Position  */
+#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE8192    (OSCCTRL_XOSCCTRL_STARTUP_CYCLE8192_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 250000 us Position  */
+#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE16384   (OSCCTRL_XOSCCTRL_STARTUP_CYCLE16384_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 500000 us Position  */
+#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE32768   (OSCCTRL_XOSCCTRL_STARTUP_CYCLE32768_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 1000000 us Position  */
+#define OSCCTRL_XOSCCTRL_CFDPRESC_Pos         _U_(24)                                              /**< (OSCCTRL_XOSCCTRL) Clock Failure Detector Prescaler Position */
+#define OSCCTRL_XOSCCTRL_CFDPRESC_Msk         (_U_(0xF) << OSCCTRL_XOSCCTRL_CFDPRESC_Pos)          /**< (OSCCTRL_XOSCCTRL) Clock Failure Detector Prescaler Mask */
+#define OSCCTRL_XOSCCTRL_CFDPRESC(value)      (OSCCTRL_XOSCCTRL_CFDPRESC_Msk & ((value) << OSCCTRL_XOSCCTRL_CFDPRESC_Pos))
+#define   OSCCTRL_XOSCCTRL_CFDPRESC_DIV1_Val  _U_(0x0)                                             /**< (OSCCTRL_XOSCCTRL) 48 MHz  */
+#define   OSCCTRL_XOSCCTRL_CFDPRESC_DIV2_Val  _U_(0x1)                                             /**< (OSCCTRL_XOSCCTRL) 24 MHz  */
+#define   OSCCTRL_XOSCCTRL_CFDPRESC_DIV4_Val  _U_(0x2)                                             /**< (OSCCTRL_XOSCCTRL) 12 MHz  */
+#define   OSCCTRL_XOSCCTRL_CFDPRESC_DIV8_Val  _U_(0x3)                                             /**< (OSCCTRL_XOSCCTRL) 6 MHz  */
+#define   OSCCTRL_XOSCCTRL_CFDPRESC_DIV16_Val _U_(0x4)                                             /**< (OSCCTRL_XOSCCTRL) 3 MHz  */
+#define   OSCCTRL_XOSCCTRL_CFDPRESC_DIV32_Val _U_(0x5)                                             /**< (OSCCTRL_XOSCCTRL) 1.5 MHz  */
+#define   OSCCTRL_XOSCCTRL_CFDPRESC_DIV64_Val _U_(0x6)                                             /**< (OSCCTRL_XOSCCTRL) 0.75 MHz  */
+#define   OSCCTRL_XOSCCTRL_CFDPRESC_DIV128_Val _U_(0x7)                                             /**< (OSCCTRL_XOSCCTRL) 0.3125 MHz  */
+#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV1        (OSCCTRL_XOSCCTRL_CFDPRESC_DIV1_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /**< (OSCCTRL_XOSCCTRL) 48 MHz Position  */
+#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV2        (OSCCTRL_XOSCCTRL_CFDPRESC_DIV2_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /**< (OSCCTRL_XOSCCTRL) 24 MHz Position  */
+#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV4        (OSCCTRL_XOSCCTRL_CFDPRESC_DIV4_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /**< (OSCCTRL_XOSCCTRL) 12 MHz Position  */
+#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV8        (OSCCTRL_XOSCCTRL_CFDPRESC_DIV8_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /**< (OSCCTRL_XOSCCTRL) 6 MHz Position  */
+#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV16       (OSCCTRL_XOSCCTRL_CFDPRESC_DIV16_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /**< (OSCCTRL_XOSCCTRL) 3 MHz Position  */
+#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV32       (OSCCTRL_XOSCCTRL_CFDPRESC_DIV32_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /**< (OSCCTRL_XOSCCTRL) 1.5 MHz Position  */
+#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV64       (OSCCTRL_XOSCCTRL_CFDPRESC_DIV64_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /**< (OSCCTRL_XOSCCTRL) 0.75 MHz Position  */
+#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV128      (OSCCTRL_XOSCCTRL_CFDPRESC_DIV128_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /**< (OSCCTRL_XOSCCTRL) 0.3125 MHz Position  */
+#define OSCCTRL_XOSCCTRL_Msk                  _U_(0x0FF3FFC6)                                      /**< (OSCCTRL_XOSCCTRL) Register Mask  */
+
+
+/* -------- OSCCTRL_DFLLCTRLA : (OSCCTRL Offset: 0x1C) (R/W 8) DFLL48M Control A -------- */
+#define OSCCTRL_DFLLCTRLA_RESETVALUE          _U_(0x82)                                            /**<  (OSCCTRL_DFLLCTRLA) DFLL48M Control A  Reset Value */
+
+#define OSCCTRL_DFLLCTRLA_ENABLE_Pos          _U_(1)                                               /**< (OSCCTRL_DFLLCTRLA) DFLL Enable Position */
+#define OSCCTRL_DFLLCTRLA_ENABLE_Msk          (_U_(0x1) << OSCCTRL_DFLLCTRLA_ENABLE_Pos)           /**< (OSCCTRL_DFLLCTRLA) DFLL Enable Mask */
+#define OSCCTRL_DFLLCTRLA_ENABLE(value)       (OSCCTRL_DFLLCTRLA_ENABLE_Msk & ((value) << OSCCTRL_DFLLCTRLA_ENABLE_Pos))
+#define OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos        _U_(6)                                               /**< (OSCCTRL_DFLLCTRLA) Run in Standby Position */
+#define OSCCTRL_DFLLCTRLA_RUNSTDBY_Msk        (_U_(0x1) << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos)         /**< (OSCCTRL_DFLLCTRLA) Run in Standby Mask */
+#define OSCCTRL_DFLLCTRLA_RUNSTDBY(value)     (OSCCTRL_DFLLCTRLA_RUNSTDBY_Msk & ((value) << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos))
+#define OSCCTRL_DFLLCTRLA_ONDEMAND_Pos        _U_(7)                                               /**< (OSCCTRL_DFLLCTRLA) On Demand Control Position */
+#define OSCCTRL_DFLLCTRLA_ONDEMAND_Msk        (_U_(0x1) << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos)         /**< (OSCCTRL_DFLLCTRLA) On Demand Control Mask */
+#define OSCCTRL_DFLLCTRLA_ONDEMAND(value)     (OSCCTRL_DFLLCTRLA_ONDEMAND_Msk & ((value) << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos))
+#define OSCCTRL_DFLLCTRLA_Msk                 _U_(0xC2)                                            /**< (OSCCTRL_DFLLCTRLA) Register Mask  */
+
+
+/* -------- OSCCTRL_DFLLCTRLB : (OSCCTRL Offset: 0x20) (R/W 8) DFLL48M Control B -------- */
+#define OSCCTRL_DFLLCTRLB_RESETVALUE          _U_(0x00)                                            /**<  (OSCCTRL_DFLLCTRLB) DFLL48M Control B  Reset Value */
+
+#define OSCCTRL_DFLLCTRLB_MODE_Pos            _U_(0)                                               /**< (OSCCTRL_DFLLCTRLB) Operating Mode Selection Position */
+#define OSCCTRL_DFLLCTRLB_MODE_Msk            (_U_(0x1) << OSCCTRL_DFLLCTRLB_MODE_Pos)             /**< (OSCCTRL_DFLLCTRLB) Operating Mode Selection Mask */
+#define OSCCTRL_DFLLCTRLB_MODE(value)         (OSCCTRL_DFLLCTRLB_MODE_Msk & ((value) << OSCCTRL_DFLLCTRLB_MODE_Pos))
+#define OSCCTRL_DFLLCTRLB_STABLE_Pos          _U_(1)                                               /**< (OSCCTRL_DFLLCTRLB) Stable DFLL Frequency Position */
+#define OSCCTRL_DFLLCTRLB_STABLE_Msk          (_U_(0x1) << OSCCTRL_DFLLCTRLB_STABLE_Pos)           /**< (OSCCTRL_DFLLCTRLB) Stable DFLL Frequency Mask */
+#define OSCCTRL_DFLLCTRLB_STABLE(value)       (OSCCTRL_DFLLCTRLB_STABLE_Msk & ((value) << OSCCTRL_DFLLCTRLB_STABLE_Pos))
+#define OSCCTRL_DFLLCTRLB_LLAW_Pos            _U_(2)                                               /**< (OSCCTRL_DFLLCTRLB) Lose Lock After Wake Position */
+#define OSCCTRL_DFLLCTRLB_LLAW_Msk            (_U_(0x1) << OSCCTRL_DFLLCTRLB_LLAW_Pos)             /**< (OSCCTRL_DFLLCTRLB) Lose Lock After Wake Mask */
+#define OSCCTRL_DFLLCTRLB_LLAW(value)         (OSCCTRL_DFLLCTRLB_LLAW_Msk & ((value) << OSCCTRL_DFLLCTRLB_LLAW_Pos))
+#define OSCCTRL_DFLLCTRLB_USBCRM_Pos          _U_(3)                                               /**< (OSCCTRL_DFLLCTRLB) USB Clock Recovery Mode Position */
+#define OSCCTRL_DFLLCTRLB_USBCRM_Msk          (_U_(0x1) << OSCCTRL_DFLLCTRLB_USBCRM_Pos)           /**< (OSCCTRL_DFLLCTRLB) USB Clock Recovery Mode Mask */
+#define OSCCTRL_DFLLCTRLB_USBCRM(value)       (OSCCTRL_DFLLCTRLB_USBCRM_Msk & ((value) << OSCCTRL_DFLLCTRLB_USBCRM_Pos))
+#define OSCCTRL_DFLLCTRLB_CCDIS_Pos           _U_(4)                                               /**< (OSCCTRL_DFLLCTRLB) Chill Cycle Disable Position */
+#define OSCCTRL_DFLLCTRLB_CCDIS_Msk           (_U_(0x1) << OSCCTRL_DFLLCTRLB_CCDIS_Pos)            /**< (OSCCTRL_DFLLCTRLB) Chill Cycle Disable Mask */
+#define OSCCTRL_DFLLCTRLB_CCDIS(value)        (OSCCTRL_DFLLCTRLB_CCDIS_Msk & ((value) << OSCCTRL_DFLLCTRLB_CCDIS_Pos))
+#define OSCCTRL_DFLLCTRLB_QLDIS_Pos           _U_(5)                                               /**< (OSCCTRL_DFLLCTRLB) Quick Lock Disable Position */
+#define OSCCTRL_DFLLCTRLB_QLDIS_Msk           (_U_(0x1) << OSCCTRL_DFLLCTRLB_QLDIS_Pos)            /**< (OSCCTRL_DFLLCTRLB) Quick Lock Disable Mask */
+#define OSCCTRL_DFLLCTRLB_QLDIS(value)        (OSCCTRL_DFLLCTRLB_QLDIS_Msk & ((value) << OSCCTRL_DFLLCTRLB_QLDIS_Pos))
+#define OSCCTRL_DFLLCTRLB_BPLCKC_Pos          _U_(6)                                               /**< (OSCCTRL_DFLLCTRLB) Bypass Coarse Lock Position */
+#define OSCCTRL_DFLLCTRLB_BPLCKC_Msk          (_U_(0x1) << OSCCTRL_DFLLCTRLB_BPLCKC_Pos)           /**< (OSCCTRL_DFLLCTRLB) Bypass Coarse Lock Mask */
+#define OSCCTRL_DFLLCTRLB_BPLCKC(value)       (OSCCTRL_DFLLCTRLB_BPLCKC_Msk & ((value) << OSCCTRL_DFLLCTRLB_BPLCKC_Pos))
+#define OSCCTRL_DFLLCTRLB_WAITLOCK_Pos        _U_(7)                                               /**< (OSCCTRL_DFLLCTRLB) Wait Lock Position */
+#define OSCCTRL_DFLLCTRLB_WAITLOCK_Msk        (_U_(0x1) << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos)         /**< (OSCCTRL_DFLLCTRLB) Wait Lock Mask */
+#define OSCCTRL_DFLLCTRLB_WAITLOCK(value)     (OSCCTRL_DFLLCTRLB_WAITLOCK_Msk & ((value) << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos))
+#define OSCCTRL_DFLLCTRLB_Msk                 _U_(0xFF)                                            /**< (OSCCTRL_DFLLCTRLB) Register Mask  */
+
+
+/* -------- OSCCTRL_DFLLVAL : (OSCCTRL Offset: 0x24) (R/W 32) DFLL48M Value -------- */
+#define OSCCTRL_DFLLVAL_RESETVALUE            _U_(0x00)                                            /**<  (OSCCTRL_DFLLVAL) DFLL48M Value  Reset Value */
+
+#define OSCCTRL_DFLLVAL_FINE_Pos              _U_(0)                                               /**< (OSCCTRL_DFLLVAL) Fine Value Position */
+#define OSCCTRL_DFLLVAL_FINE_Msk              (_U_(0xFF) << OSCCTRL_DFLLVAL_FINE_Pos)              /**< (OSCCTRL_DFLLVAL) Fine Value Mask */
+#define OSCCTRL_DFLLVAL_FINE(value)           (OSCCTRL_DFLLVAL_FINE_Msk & ((value) << OSCCTRL_DFLLVAL_FINE_Pos))
+#define OSCCTRL_DFLLVAL_COARSE_Pos            _U_(10)                                              /**< (OSCCTRL_DFLLVAL) Coarse Value Position */
+#define OSCCTRL_DFLLVAL_COARSE_Msk            (_U_(0x3F) << OSCCTRL_DFLLVAL_COARSE_Pos)            /**< (OSCCTRL_DFLLVAL) Coarse Value Mask */
+#define OSCCTRL_DFLLVAL_COARSE(value)         (OSCCTRL_DFLLVAL_COARSE_Msk & ((value) << OSCCTRL_DFLLVAL_COARSE_Pos))
+#define OSCCTRL_DFLLVAL_DIFF_Pos              _U_(16)                                              /**< (OSCCTRL_DFLLVAL) Multiplication Ratio Difference Position */
+#define OSCCTRL_DFLLVAL_DIFF_Msk              (_U_(0xFFFF) << OSCCTRL_DFLLVAL_DIFF_Pos)            /**< (OSCCTRL_DFLLVAL) Multiplication Ratio Difference Mask */
+#define OSCCTRL_DFLLVAL_DIFF(value)           (OSCCTRL_DFLLVAL_DIFF_Msk & ((value) << OSCCTRL_DFLLVAL_DIFF_Pos))
+#define OSCCTRL_DFLLVAL_Msk                   _U_(0xFFFFFCFF)                                      /**< (OSCCTRL_DFLLVAL) Register Mask  */
+
+
+/* -------- OSCCTRL_DFLLMUL : (OSCCTRL Offset: 0x28) (R/W 32) DFLL48M Multiplier -------- */
+#define OSCCTRL_DFLLMUL_RESETVALUE            _U_(0x00)                                            /**<  (OSCCTRL_DFLLMUL) DFLL48M Multiplier  Reset Value */
+
+#define OSCCTRL_DFLLMUL_MUL_Pos               _U_(0)                                               /**< (OSCCTRL_DFLLMUL) DFLL Multiply Factor Position */
+#define OSCCTRL_DFLLMUL_MUL_Msk               (_U_(0xFFFF) << OSCCTRL_DFLLMUL_MUL_Pos)             /**< (OSCCTRL_DFLLMUL) DFLL Multiply Factor Mask */
+#define OSCCTRL_DFLLMUL_MUL(value)            (OSCCTRL_DFLLMUL_MUL_Msk & ((value) << OSCCTRL_DFLLMUL_MUL_Pos))
+#define OSCCTRL_DFLLMUL_FSTEP_Pos             _U_(16)                                              /**< (OSCCTRL_DFLLMUL) Fine Maximum Step Position */
+#define OSCCTRL_DFLLMUL_FSTEP_Msk             (_U_(0xFF) << OSCCTRL_DFLLMUL_FSTEP_Pos)             /**< (OSCCTRL_DFLLMUL) Fine Maximum Step Mask */
+#define OSCCTRL_DFLLMUL_FSTEP(value)          (OSCCTRL_DFLLMUL_FSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_FSTEP_Pos))
+#define OSCCTRL_DFLLMUL_CSTEP_Pos             _U_(26)                                              /**< (OSCCTRL_DFLLMUL) Coarse Maximum Step Position */
+#define OSCCTRL_DFLLMUL_CSTEP_Msk             (_U_(0x3F) << OSCCTRL_DFLLMUL_CSTEP_Pos)             /**< (OSCCTRL_DFLLMUL) Coarse Maximum Step Mask */
+#define OSCCTRL_DFLLMUL_CSTEP(value)          (OSCCTRL_DFLLMUL_CSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_CSTEP_Pos))
+#define OSCCTRL_DFLLMUL_Msk                   _U_(0xFCFFFFFF)                                      /**< (OSCCTRL_DFLLMUL) Register Mask  */
+
+
+/* -------- OSCCTRL_DFLLSYNC : (OSCCTRL Offset: 0x2C) (R/W 8) DFLL48M Synchronization -------- */
+#define OSCCTRL_DFLLSYNC_RESETVALUE           _U_(0x00)                                            /**<  (OSCCTRL_DFLLSYNC) DFLL48M Synchronization  Reset Value */
+
+#define OSCCTRL_DFLLSYNC_ENABLE_Pos           _U_(1)                                               /**< (OSCCTRL_DFLLSYNC) ENABLE Synchronization Busy Position */
+#define OSCCTRL_DFLLSYNC_ENABLE_Msk           (_U_(0x1) << OSCCTRL_DFLLSYNC_ENABLE_Pos)            /**< (OSCCTRL_DFLLSYNC) ENABLE Synchronization Busy Mask */
+#define OSCCTRL_DFLLSYNC_ENABLE(value)        (OSCCTRL_DFLLSYNC_ENABLE_Msk & ((value) << OSCCTRL_DFLLSYNC_ENABLE_Pos))
+#define OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos        _U_(2)                                               /**< (OSCCTRL_DFLLSYNC) DFLLCTRLB Synchronization Busy Position */
+#define OSCCTRL_DFLLSYNC_DFLLCTRLB_Msk        (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos)         /**< (OSCCTRL_DFLLSYNC) DFLLCTRLB Synchronization Busy Mask */
+#define OSCCTRL_DFLLSYNC_DFLLCTRLB(value)     (OSCCTRL_DFLLSYNC_DFLLCTRLB_Msk & ((value) << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos))
+#define OSCCTRL_DFLLSYNC_DFLLVAL_Pos          _U_(3)                                               /**< (OSCCTRL_DFLLSYNC) DFLLVAL Synchronization Busy Position */
+#define OSCCTRL_DFLLSYNC_DFLLVAL_Msk          (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLVAL_Pos)           /**< (OSCCTRL_DFLLSYNC) DFLLVAL Synchronization Busy Mask */
+#define OSCCTRL_DFLLSYNC_DFLLVAL(value)       (OSCCTRL_DFLLSYNC_DFLLVAL_Msk & ((value) << OSCCTRL_DFLLSYNC_DFLLVAL_Pos))
+#define OSCCTRL_DFLLSYNC_DFLLMUL_Pos          _U_(4)                                               /**< (OSCCTRL_DFLLSYNC) DFLLMUL Synchronization Busy Position */
+#define OSCCTRL_DFLLSYNC_DFLLMUL_Msk          (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLMUL_Pos)           /**< (OSCCTRL_DFLLSYNC) DFLLMUL Synchronization Busy Mask */
+#define OSCCTRL_DFLLSYNC_DFLLMUL(value)       (OSCCTRL_DFLLSYNC_DFLLMUL_Msk & ((value) << OSCCTRL_DFLLSYNC_DFLLMUL_Pos))
+#define OSCCTRL_DFLLSYNC_Msk                  _U_(0x1E)                                            /**< (OSCCTRL_DFLLSYNC) Register Mask  */
+
+
+/** \brief OSCCTRL register offsets definitions */
+#define OSCCTRL_DPLLCTRLA_REG_OFST     (0x00)              /**< (OSCCTRL_DPLLCTRLA) DPLL Control A Offset */
+#define OSCCTRL_DPLLRATIO_REG_OFST     (0x04)              /**< (OSCCTRL_DPLLRATIO) DPLL Ratio Control Offset */
+#define OSCCTRL_DPLLCTRLB_REG_OFST     (0x08)              /**< (OSCCTRL_DPLLCTRLB) DPLL Control B Offset */
+#define OSCCTRL_DPLLSYNCBUSY_REG_OFST  (0x0C)              /**< (OSCCTRL_DPLLSYNCBUSY) DPLL Synchronization Busy Offset */
+#define OSCCTRL_DPLLSTATUS_REG_OFST    (0x10)              /**< (OSCCTRL_DPLLSTATUS) DPLL Status Offset */
+#define OSCCTRL_EVCTRL_REG_OFST        (0x00)              /**< (OSCCTRL_EVCTRL) Event Control Offset */
+#define OSCCTRL_INTENCLR_REG_OFST      (0x04)              /**< (OSCCTRL_INTENCLR) Interrupt Enable Clear Offset */
+#define OSCCTRL_INTENSET_REG_OFST      (0x08)              /**< (OSCCTRL_INTENSET) Interrupt Enable Set Offset */
+#define OSCCTRL_INTFLAG_REG_OFST       (0x0C)              /**< (OSCCTRL_INTFLAG) Interrupt Flag Status and Clear Offset */
+#define OSCCTRL_STATUS_REG_OFST        (0x10)              /**< (OSCCTRL_STATUS) Status Offset */
+#define OSCCTRL_XOSCCTRL_REG_OFST      (0x14)              /**< (OSCCTRL_XOSCCTRL) External Multipurpose Crystal Oscillator Control Offset */
+#define OSCCTRL_DFLLCTRLA_REG_OFST     (0x1C)              /**< (OSCCTRL_DFLLCTRLA) DFLL48M Control A Offset */
+#define OSCCTRL_DFLLCTRLB_REG_OFST     (0x20)              /**< (OSCCTRL_DFLLCTRLB) DFLL48M Control B Offset */
+#define OSCCTRL_DFLLVAL_REG_OFST       (0x24)              /**< (OSCCTRL_DFLLVAL) DFLL48M Value Offset */
+#define OSCCTRL_DFLLMUL_REG_OFST       (0x28)              /**< (OSCCTRL_DFLLMUL) DFLL48M Multiplier Offset */
+#define OSCCTRL_DFLLSYNC_REG_OFST      (0x2C)              /**< (OSCCTRL_DFLLSYNC) DFLL48M Synchronization Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief DPLL register API structure */
+typedef struct
+{
+  __IO  uint8_t                        OSCCTRL_DPLLCTRLA;  /**< Offset: 0x00 (R/W  8) DPLL Control A */
+  __I   uint8_t                        Reserved1[0x03];
+  __IO  uint32_t                       OSCCTRL_DPLLRATIO;  /**< Offset: 0x04 (R/W  32) DPLL Ratio Control */
+  __IO  uint32_t                       OSCCTRL_DPLLCTRLB;  /**< Offset: 0x08 (R/W  32) DPLL Control B */
+  __I   uint32_t                       OSCCTRL_DPLLSYNCBUSY; /**< Offset: 0x0C (R/   32) DPLL Synchronization Busy */
+  __I   uint32_t                       OSCCTRL_DPLLSTATUS; /**< Offset: 0x10 (R/   32) DPLL Status */
+} oscctrl_dpll_registers_t;
+
+#define OSCCTRL_DPLL_NUMBER _U_(2)
+
+/** \brief OSCCTRL register API structure */
+typedef struct
+{  /* Oscillators Control */
+  __IO  uint8_t                        OSCCTRL_EVCTRL;     /**< Offset: 0x00 (R/W  8) Event Control */
+  __I   uint8_t                        Reserved1[0x03];
+  __IO  uint32_t                       OSCCTRL_INTENCLR;   /**< Offset: 0x04 (R/W  32) Interrupt Enable Clear */
+  __IO  uint32_t                       OSCCTRL_INTENSET;   /**< Offset: 0x08 (R/W  32) Interrupt Enable Set */
+  __IO  uint32_t                       OSCCTRL_INTFLAG;    /**< Offset: 0x0C (R/W  32) Interrupt Flag Status and Clear */
+  __I   uint32_t                       OSCCTRL_STATUS;     /**< Offset: 0x10 (R/   32) Status */
+  __IO  uint32_t                       OSCCTRL_XOSCCTRL[2]; /**< Offset: 0x14 (R/W  32) External Multipurpose Crystal Oscillator Control */
+  __IO  uint8_t                        OSCCTRL_DFLLCTRLA;  /**< Offset: 0x1C (R/W  8) DFLL48M Control A */
+  __I   uint8_t                        Reserved2[0x03];
+  __IO  uint8_t                        OSCCTRL_DFLLCTRLB;  /**< Offset: 0x20 (R/W  8) DFLL48M Control B */
+  __I   uint8_t                        Reserved3[0x03];
+  __IO  uint32_t                       OSCCTRL_DFLLVAL;    /**< Offset: 0x24 (R/W  32) DFLL48M Value */
+  __IO  uint32_t                       OSCCTRL_DFLLMUL;    /**< Offset: 0x28 (R/W  32) DFLL48M Multiplier */
+  __IO  uint8_t                        OSCCTRL_DFLLSYNC;   /**< Offset: 0x2C (R/W  8) DFLL48M Synchronization */
+  __I   uint8_t                        Reserved4[0x03];
+        oscctrl_dpll_registers_t       DPLL[OSCCTRL_DPLL_NUMBER]; /**< Offset: 0x30  */
+} oscctrl_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _SAMD51_OSCCTRL_COMPONENT_H_ */
Index: /asp_wio_terminal/trunk/target/samd51_gcc/lib/plib_clock.c
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/lib/plib_clock.c	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/lib/plib_clock.c	(revision 460)
@@ -0,0 +1,245 @@
+/*******************************************************************************
+ CLOCK PLIB
+
+  Company:
+    Microchip Technology Inc.
+
+  File Name:
+    plib_clock.c
+
+  Summary:
+    CLOCK PLIB Implementation File.
+
+  Description:
+    None
+
+*******************************************************************************/
+
+/*******************************************************************************
+* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries.
+*
+* Subject to your compliance with these terms, you may use Microchip software
+* and any derivatives exclusively with Microchip products. It is your
+* responsibility to comply with third party license terms applicable to your
+* use of third party software (including open source software) that may
+* accompany Microchip software.
+*
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER
+* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED
+* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A
+* PARTICULAR PURPOSE.
+*
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE
+* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN
+* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+*******************************************************************************/
+
+#include "plib_clock.h"
+#include "atsamd51p19a.h"
+
+static void OSCCTRL_Initialize(void)
+{
+
+    /****************** XOSC1 Initialization   ********************************/
+
+    /* Configure External Oscillator */
+    OSCCTRL_REGS->OSCCTRL_XOSCCTRL[1] = OSCCTRL_XOSCCTRL_STARTUP(0) | OSCCTRL_XOSCCTRL_IMULT(6) | OSCCTRL_XOSCCTRL_IPTAT(3) | OSCCTRL_XOSCCTRL_XTALEN_Msk | OSCCTRL_XOSCCTRL_ENABLE_Msk;
+
+    while((OSCCTRL_REGS->OSCCTRL_STATUS & OSCCTRL_STATUS_XOSCRDY1_Msk) != OSCCTRL_STATUS_XOSCRDY1_Msk)
+    {
+        /* Waiting for the XOSC Ready state */
+    }
+}
+
+static void OSC32KCTRL_Initialize(void)
+{
+    /****************** XOSC32K initialization  ******************************/
+
+    /* Configure 32K External Oscillator */
+    OSC32KCTRL_REGS->OSC32KCTRL_XOSC32K = OSC32KCTRL_XOSC32K_STARTUP(2) | OSC32KCTRL_XOSC32K_ENABLE_Msk | OSC32KCTRL_XOSC32K_CGM(1) | OSC32KCTRL_XOSC32K_EN32K_Msk | OSC32KCTRL_XOSC32K_XTALEN_Msk;
+
+
+    while(!((OSC32KCTRL_REGS->OSC32KCTRL_STATUS & OSC32KCTRL_STATUS_XOSC32KRDY_Msk) == OSC32KCTRL_STATUS_XOSC32KRDY_Msk))
+    {
+        /* Waiting for the XOSC32K Ready state */
+    }
+
+    OSC32KCTRL_REGS->OSC32KCTRL_RTCCTRL = OSC32KCTRL_RTCCTRL_RTCSEL(0);
+}
+
+static void FDPLL0_Initialize(void)
+{
+    GCLK_REGS->GCLK_PCHCTRL[1] = GCLK_PCHCTRL_GEN(0x2)  | GCLK_PCHCTRL_CHEN_Msk;
+    while ((GCLK_REGS->GCLK_PCHCTRL[1] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk)
+    {
+        /* Wait for synchronization */
+    }
+
+    /****************** DPLL0 Initialization  *********************************/
+
+    /* Configure DPLL    */
+    OSCCTRL_REGS->DPLL[0].OSCCTRL_DPLLCTRLB = OSCCTRL_DPLLCTRLB_FILTER(0) | OSCCTRL_DPLLCTRLB_LTIME(0x0)| OSCCTRL_DPLLCTRLB_REFCLK(0) ;
+
+
+    OSCCTRL_REGS->DPLL[0].OSCCTRL_DPLLRATIO = OSCCTRL_DPLLRATIO_LDRFRAC(0) | OSCCTRL_DPLLRATIO_LDR(199);
+
+    while((OSCCTRL_REGS->DPLL[0].OSCCTRL_DPLLSYNCBUSY & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Msk) == OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Msk)
+    {
+        /* Waiting for the synchronization */
+    }
+
+    /* Enable DPLL */
+    OSCCTRL_REGS->DPLL[0].OSCCTRL_DPLLCTRLA = OSCCTRL_DPLLCTRLA_ENABLE_Msk   ;
+
+    while((OSCCTRL_REGS->DPLL[0].OSCCTRL_DPLLSYNCBUSY & OSCCTRL_DPLLSYNCBUSY_ENABLE_Msk) == OSCCTRL_DPLLSYNCBUSY_ENABLE_Msk )
+    {
+        /* Waiting for the DPLL enable synchronization */
+    }
+
+    while((OSCCTRL_REGS->DPLL[0].OSCCTRL_DPLLSTATUS & (OSCCTRL_DPLLSTATUS_LOCK_Msk | OSCCTRL_DPLLSTATUS_CLKRDY_Msk)) !=
+                (OSCCTRL_DPLLSTATUS_LOCK_Msk | OSCCTRL_DPLLSTATUS_CLKRDY_Msk))
+    {
+        /* Waiting for the Ready state */
+    }
+}
+
+static void FDPLL1_Initialize(void)
+{
+    GCLK_REGS->GCLK_PCHCTRL[2] = GCLK_PCHCTRL_GEN(0x2)  | GCLK_PCHCTRL_CHEN_Msk;
+    while ((GCLK_REGS->GCLK_PCHCTRL[1] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk)
+    {
+        /* Wait for synchronization */
+    }
+
+    /****************** DPLL1 Initialization  *********************************/
+
+    /* Configure DPLL    */
+    OSCCTRL_REGS->DPLL[1].OSCCTRL_DPLLCTRLB = OSCCTRL_DPLLCTRLB_FILTER(0) | OSCCTRL_DPLLCTRLB_LTIME(0x0)| OSCCTRL_DPLLCTRLB_REFCLK(0) ;
+
+
+    OSCCTRL_REGS->DPLL[1].OSCCTRL_DPLLRATIO = OSCCTRL_DPLLRATIO_LDRFRAC(0) | OSCCTRL_DPLLRATIO_LDR(159);
+
+    while((OSCCTRL_REGS->DPLL[1].OSCCTRL_DPLLSYNCBUSY & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Msk) == OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Msk)
+    {
+        /* Waiting for the synchronization */
+    }
+
+    /* Enable DPLL */
+    OSCCTRL_REGS->DPLL[1].OSCCTRL_DPLLCTRLA = OSCCTRL_DPLLCTRLA_ENABLE_Msk   ;
+
+    while((OSCCTRL_REGS->DPLL[1].OSCCTRL_DPLLSYNCBUSY & OSCCTRL_DPLLSYNCBUSY_ENABLE_Msk) == OSCCTRL_DPLLSYNCBUSY_ENABLE_Msk )
+    {
+        /* Waiting for the DPLL enable synchronization */
+    }
+
+    while((OSCCTRL_REGS->DPLL[1].OSCCTRL_DPLLSTATUS & (OSCCTRL_DPLLSTATUS_LOCK_Msk | OSCCTRL_DPLLSTATUS_CLKRDY_Msk)) !=
+                (OSCCTRL_DPLLSTATUS_LOCK_Msk | OSCCTRL_DPLLSTATUS_CLKRDY_Msk))
+    {
+        /* Waiting for the Ready state */
+    }
+}
+
+static void DFLL_Initialize(void)
+{
+}
+
+
+static void GCLK0_Initialize(void)
+{
+    
+    /* selection of the CPU clock Division */
+    MCLK_REGS->MCLK_CPUDIV = MCLK_CPUDIV_DIV(0x01);
+
+    while((MCLK_REGS->MCLK_INTFLAG & MCLK_INTFLAG_CKRDY_Msk) != MCLK_INTFLAG_CKRDY_Msk)
+    {
+        /* Wait for the Main Clock to be Ready */
+    }
+    GCLK_REGS->GCLK_GENCTRL[0] = GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_SRC(7) | GCLK_GENCTRL_GENEN_Msk;
+
+    while((GCLK_REGS->GCLK_SYNCBUSY & GCLK_SYNCBUSY_GENCTRL_GCLK0) == GCLK_SYNCBUSY_GENCTRL_GCLK0)
+    {
+        /* wait for the Generator 0 synchronization */
+    }
+}
+
+static void GCLK1_Initialize(void)
+{
+    GCLK_REGS->GCLK_GENCTRL[1] = GCLK_GENCTRL_DIV(2) | GCLK_GENCTRL_SRC(7) | GCLK_GENCTRL_GENEN_Msk;
+
+    while((GCLK_REGS->GCLK_SYNCBUSY & GCLK_SYNCBUSY_GENCTRL_GCLK1) == GCLK_SYNCBUSY_GENCTRL_GCLK1)
+    {
+        /* wait for the Generator 1 synchronization */
+    }
+}
+
+static void GCLK2_Initialize(void)
+{
+    GCLK_REGS->GCLK_GENCTRL[2] = GCLK_GENCTRL_DIV(32) | GCLK_GENCTRL_SRC(1) | GCLK_GENCTRL_GENEN_Msk;
+
+    while((GCLK_REGS->GCLK_SYNCBUSY & GCLK_SYNCBUSY_GENCTRL_GCLK2) == GCLK_SYNCBUSY_GENCTRL_GCLK2)
+    {
+        /* wait for the Generator 2 synchronization */
+    }
+}
+
+static void GCLK3_Initialize(void)
+{
+    GCLK_REGS->GCLK_GENCTRL[3] = GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_SRC(8) | GCLK_GENCTRL_GENEN_Msk;
+
+    while((GCLK_REGS->GCLK_SYNCBUSY & GCLK_SYNCBUSY_GENCTRL_GCLK3) == GCLK_SYNCBUSY_GENCTRL_GCLK3)
+    {
+        /* wait for the Generator 3 synchronization */
+    }
+}
+
+void CLOCK_Initialize (void)
+{
+    /* Function to Initialize the Oscillators */
+    OSCCTRL_Initialize();
+
+    /* Function to Initialize the 32KHz Oscillators */
+    OSC32KCTRL_Initialize();
+
+    DFLL_Initialize();
+    GCLK2_Initialize();
+    FDPLL0_Initialize();
+    FDPLL1_Initialize();
+    GCLK0_Initialize();
+    GCLK1_Initialize();
+    GCLK3_Initialize();
+
+
+
+    /* Selection of the Generator and write Lock for SERCOM2_CORE */
+    GCLK_REGS->GCLK_PCHCTRL[23] = GCLK_PCHCTRL_GEN(0x1)  | GCLK_PCHCTRL_CHEN_Msk;
+
+    while ((GCLK_REGS->GCLK_PCHCTRL[23] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk)
+    {
+        /* Wait for synchronization */
+    }
+    /* Selection of the Generator and write Lock for SERCOM7_CORE */
+    GCLK_REGS->GCLK_PCHCTRL[37] = GCLK_PCHCTRL_GEN(0x3)  | GCLK_PCHCTRL_CHEN_Msk;
+
+    while ((GCLK_REGS->GCLK_PCHCTRL[37] & GCLK_PCHCTRL_CHEN_Msk) != GCLK_PCHCTRL_CHEN_Msk)
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Configure the AHB Bridge Clocks */
+    MCLK_REGS->MCLK_AHBMASK = 0xffffff;
+
+    /* Configure the APBA Bridge Clocks */
+    MCLK_REGS->MCLK_APBAMASK = 0x7ff;
+
+    /* Configure the APBB Bridge Clocks */
+    MCLK_REGS->MCLK_APBBMASK = 0x18256;
+
+    /* Configure the APBD Bridge Clocks */
+    MCLK_REGS->MCLK_APBDMASK = 0x8;
+
+
+}
Index: /asp_wio_terminal/trunk/target/samd51_gcc/lib/plib_clock.h
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/lib/plib_clock.h	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/lib/plib_clock.h	(revision 460)
@@ -0,0 +1,136 @@
+/*******************************************************************************
+  CLOCK PLIB
+
+  Company:
+    Microchip Technology Inc.
+
+  File Name:
+    plib_clock.h
+
+  Summary:
+    CLOCK PLIB Header File.
+
+  Description:
+    The Clock PLIB initializes all the oscillators based on the
+    requirements.
+
+*******************************************************************************/
+
+/*******************************************************************************
+* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries.
+*
+* Subject to your compliance with these terms, you may use Microchip software
+* and any derivatives exclusively with Microchip products. It is your
+* responsibility to comply with third party license terms applicable to your
+* use of third party software (including open source software) that may
+* accompany Microchip software.
+*
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER
+* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED
+* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A
+* PARTICULAR PURPOSE.
+*
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE
+* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN
+* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+*******************************************************************************/
+
+#ifndef PLIB_CLOCK_H
+#define PLIB_CLOCK_H
+
+// *****************************************************************************
+// *****************************************************************************
+// Section: Included Files
+// *****************************************************************************
+// *****************************************************************************
+/* This section lists the other files that are included in this file.
+*/
+// DOM-IGNORE-BEGIN
+#ifdef __cplusplus // Provide C++ Compatibility
+extern "C" {
+#endif
+
+// DOM-IGNORE-END
+
+// *****************************************************************************
+// *****************************************************************************
+// Section: Data Types
+// *****************************************************************************
+// *****************************************************************************
+
+
+
+// *****************************************************************************
+// *****************************************************************************
+// Section: Interface Routines
+// *****************************************************************************
+// *****************************************************************************
+/* The following functions make up the methods (set of possible operations) of
+this interface.
+*/
+
+// *****************************************************************************
+/* Function:
+    void CLOCK_Initialize (void);
+
+  Summary:
+    Initializes all the modules related to the system clock.
+
+  Description:
+    This function initializes the clock as defined by the MHC and Clock Manager
+    selections. The function will configure the NVM Flash Wait states based on
+    the configured CPU operational frequency. It will then configure the
+    oscillators.
+
+    For each of the clock sources (External Oscillator, Digital Phase Locked
+    Loop, Internal 48MHz Oscillator, External 32KHz oscillator and the Internal
+    32KHz oscillator) enabled in MHC, the function will configure the clock
+    settings and will then wait till the clock is ready. In case of DPLL, the
+    function will wait till a lock is obtained.
+
+    The function will then configure the Generic clock generators based on MHC
+    configurations. If a Generic Clock is enabled in MHC, this will be enabled
+    in the CLOCK_Initialize() function. The function will apply the CPU clock
+    divider and will wait for the Main Clock module to get ready. If the Main
+    Clock to the Peripheral APB and AHB interfaces was enabled in MHC, these
+    will be enabled in the CLOCK_Initialize() function. If the Peripheral Clock
+    Channels were enabled in MHC, these will be enabled in the
+    CLOCK_Initialize() function.
+
+    The peripheral AHB and APB main clock and peripheral channel clocks will be
+    enabled when the peripheral specific initialize functions are called. This
+    will override the setting in MHC. The Generic Clock Generator source for
+    desired peripheral channel must be configured in MHC.
+
+  Precondition:
+    MHC GUI should be configured with the right values. Incorrect configuration
+    of the Clock will result in incorrect peripheral behavior or a non
+    functional device.
+
+  Parameters:
+    None.
+
+  Returns:
+    None.
+
+  Example:
+    <code>
+        CLOCK_Initialize();
+    </code>
+
+  Remarks:
+    This function should be called before calling other Clock library functions.
+*/
+
+void CLOCK_Initialize (void);
+
+
+#ifdef __cplusplus // Provide C++ Compatibility
+}
+#endif
+
+#endif /* PLIB_CLOCK_H */
Index: /asp_wio_terminal/trunk/target/samd51_gcc/lib/port.h
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/lib/port.h	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/lib/port.h	(revision 460)
@@ -0,0 +1,281 @@
+/**
+ * \brief Component description for PORT
+ *
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * Subject to your compliance with these terms, you may use Microchip software and any derivatives
+ * exclusively with Microchip products. It is your responsibility to comply with third party license
+ * terms applicable to your use of third party software (including open source software) that may
+ * accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
+ * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
+ * FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
+ * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
+ * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ */
+
+/* file generated from device description version 2020-03-12T17:26:00Z */
+#ifndef _SAMD51_PORT_COMPONENT_H_
+#define _SAMD51_PORT_COMPONENT_H_
+
+/* ************************************************************************** */
+/*   SOFTWARE API DEFINITION FOR PORT                                         */
+/* ************************************************************************** */
+
+/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) Data Direction -------- */
+#define PORT_DIR_RESETVALUE                   _U_(0x00)                                            /**<  (PORT_DIR) Data Direction  Reset Value */
+
+#define PORT_DIR_DIR_Pos                      _U_(0)                                               /**< (PORT_DIR) Port Data Direction Position */
+#define PORT_DIR_DIR_Msk                      (_U_(0xFFFFFFFF) << PORT_DIR_DIR_Pos)                /**< (PORT_DIR) Port Data Direction Mask */
+#define PORT_DIR_DIR(value)                   (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos))  
+#define PORT_DIR_Msk                          _U_(0xFFFFFFFF)                                      /**< (PORT_DIR) Register Mask  */
+
+
+/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) Data Direction Clear -------- */
+#define PORT_DIRCLR_RESETVALUE                _U_(0x00)                                            /**<  (PORT_DIRCLR) Data Direction Clear  Reset Value */
+
+#define PORT_DIRCLR_DIRCLR_Pos                _U_(0)                                               /**< (PORT_DIRCLR) Port Data Direction Clear Position */
+#define PORT_DIRCLR_DIRCLR_Msk                (_U_(0xFFFFFFFF) << PORT_DIRCLR_DIRCLR_Pos)          /**< (PORT_DIRCLR) Port Data Direction Clear Mask */
+#define PORT_DIRCLR_DIRCLR(value)             (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos))
+#define PORT_DIRCLR_Msk                       _U_(0xFFFFFFFF)                                      /**< (PORT_DIRCLR) Register Mask  */
+
+
+/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) Data Direction Set -------- */
+#define PORT_DIRSET_RESETVALUE                _U_(0x00)                                            /**<  (PORT_DIRSET) Data Direction Set  Reset Value */
+
+#define PORT_DIRSET_DIRSET_Pos                _U_(0)                                               /**< (PORT_DIRSET) Port Data Direction Set Position */
+#define PORT_DIRSET_DIRSET_Msk                (_U_(0xFFFFFFFF) << PORT_DIRSET_DIRSET_Pos)          /**< (PORT_DIRSET) Port Data Direction Set Mask */
+#define PORT_DIRSET_DIRSET(value)             (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos))
+#define PORT_DIRSET_Msk                       _U_(0xFFFFFFFF)                                      /**< (PORT_DIRSET) Register Mask  */
+
+
+/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) Data Direction Toggle -------- */
+#define PORT_DIRTGL_RESETVALUE                _U_(0x00)                                            /**<  (PORT_DIRTGL) Data Direction Toggle  Reset Value */
+
+#define PORT_DIRTGL_DIRTGL_Pos                _U_(0)                                               /**< (PORT_DIRTGL) Port Data Direction Toggle Position */
+#define PORT_DIRTGL_DIRTGL_Msk                (_U_(0xFFFFFFFF) << PORT_DIRTGL_DIRTGL_Pos)          /**< (PORT_DIRTGL) Port Data Direction Toggle Mask */
+#define PORT_DIRTGL_DIRTGL(value)             (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos))
+#define PORT_DIRTGL_Msk                       _U_(0xFFFFFFFF)                                      /**< (PORT_DIRTGL) Register Mask  */
+
+
+/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) Data Output Value -------- */
+#define PORT_OUT_RESETVALUE                   _U_(0x00)                                            /**<  (PORT_OUT) Data Output Value  Reset Value */
+
+#define PORT_OUT_OUT_Pos                      _U_(0)                                               /**< (PORT_OUT) PORT Data Output Value Position */
+#define PORT_OUT_OUT_Msk                      (_U_(0xFFFFFFFF) << PORT_OUT_OUT_Pos)                /**< (PORT_OUT) PORT Data Output Value Mask */
+#define PORT_OUT_OUT(value)                   (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos))  
+#define PORT_OUT_Msk                          _U_(0xFFFFFFFF)                                      /**< (PORT_OUT) Register Mask  */
+
+
+/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) Data Output Value Clear -------- */
+#define PORT_OUTCLR_RESETVALUE                _U_(0x00)                                            /**<  (PORT_OUTCLR) Data Output Value Clear  Reset Value */
+
+#define PORT_OUTCLR_OUTCLR_Pos                _U_(0)                                               /**< (PORT_OUTCLR) PORT Data Output Value Clear Position */
+#define PORT_OUTCLR_OUTCLR_Msk                (_U_(0xFFFFFFFF) << PORT_OUTCLR_OUTCLR_Pos)          /**< (PORT_OUTCLR) PORT Data Output Value Clear Mask */
+#define PORT_OUTCLR_OUTCLR(value)             (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos))
+#define PORT_OUTCLR_Msk                       _U_(0xFFFFFFFF)                                      /**< (PORT_OUTCLR) Register Mask  */
+
+
+/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) Data Output Value Set -------- */
+#define PORT_OUTSET_RESETVALUE                _U_(0x00)                                            /**<  (PORT_OUTSET) Data Output Value Set  Reset Value */
+
+#define PORT_OUTSET_OUTSET_Pos                _U_(0)                                               /**< (PORT_OUTSET) PORT Data Output Value Set Position */
+#define PORT_OUTSET_OUTSET_Msk                (_U_(0xFFFFFFFF) << PORT_OUTSET_OUTSET_Pos)          /**< (PORT_OUTSET) PORT Data Output Value Set Mask */
+#define PORT_OUTSET_OUTSET(value)             (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos))
+#define PORT_OUTSET_Msk                       _U_(0xFFFFFFFF)                                      /**< (PORT_OUTSET) Register Mask  */
+
+
+/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) Data Output Value Toggle -------- */
+#define PORT_OUTTGL_RESETVALUE                _U_(0x00)                                            /**<  (PORT_OUTTGL) Data Output Value Toggle  Reset Value */
+
+#define PORT_OUTTGL_OUTTGL_Pos                _U_(0)                                               /**< (PORT_OUTTGL) PORT Data Output Value Toggle Position */
+#define PORT_OUTTGL_OUTTGL_Msk                (_U_(0xFFFFFFFF) << PORT_OUTTGL_OUTTGL_Pos)          /**< (PORT_OUTTGL) PORT Data Output Value Toggle Mask */
+#define PORT_OUTTGL_OUTTGL(value)             (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos))
+#define PORT_OUTTGL_Msk                       _U_(0xFFFFFFFF)                                      /**< (PORT_OUTTGL) Register Mask  */
+
+
+/* -------- PORT_IN : (PORT Offset: 0x20) ( R/ 32) Data Input Value -------- */
+#define PORT_IN_RESETVALUE                    _U_(0x00)                                            /**<  (PORT_IN) Data Input Value  Reset Value */
+
+#define PORT_IN_IN_Pos                        _U_(0)                                               /**< (PORT_IN) PORT Data Input Value Position */
+#define PORT_IN_IN_Msk                        (_U_(0xFFFFFFFF) << PORT_IN_IN_Pos)                  /**< (PORT_IN) PORT Data Input Value Mask */
+#define PORT_IN_IN(value)                     (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos))      
+#define PORT_IN_Msk                           _U_(0xFFFFFFFF)                                      /**< (PORT_IN) Register Mask  */
+
+
+/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) Control -------- */
+#define PORT_CTRL_RESETVALUE                  _U_(0x00)                                            /**<  (PORT_CTRL) Control  Reset Value */
+
+#define PORT_CTRL_SAMPLING_Pos                _U_(0)                                               /**< (PORT_CTRL) Input Sampling Mode Position */
+#define PORT_CTRL_SAMPLING_Msk                (_U_(0xFFFFFFFF) << PORT_CTRL_SAMPLING_Pos)          /**< (PORT_CTRL) Input Sampling Mode Mask */
+#define PORT_CTRL_SAMPLING(value)             (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))
+#define PORT_CTRL_Msk                         _U_(0xFFFFFFFF)                                      /**< (PORT_CTRL) Register Mask  */
+
+
+/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) Write Configuration -------- */
+#define PORT_WRCONFIG_RESETVALUE              _U_(0x00)                                            /**<  (PORT_WRCONFIG) Write Configuration  Reset Value */
+
+#define PORT_WRCONFIG_PINMASK_Pos             _U_(0)                                               /**< (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration Position */
+#define PORT_WRCONFIG_PINMASK_Msk             (_U_(0xFFFF) << PORT_WRCONFIG_PINMASK_Pos)           /**< (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration Mask */
+#define PORT_WRCONFIG_PINMASK(value)          (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))
+#define PORT_WRCONFIG_PMUXEN_Pos              _U_(16)                                              /**< (PORT_WRCONFIG) Peripheral Multiplexer Enable Position */
+#define PORT_WRCONFIG_PMUXEN_Msk              (_U_(0x1) << PORT_WRCONFIG_PMUXEN_Pos)               /**< (PORT_WRCONFIG) Peripheral Multiplexer Enable Mask */
+#define PORT_WRCONFIG_PMUXEN(value)           (PORT_WRCONFIG_PMUXEN_Msk & ((value) << PORT_WRCONFIG_PMUXEN_Pos))
+#define PORT_WRCONFIG_INEN_Pos                _U_(17)                                              /**< (PORT_WRCONFIG) Input Enable Position */
+#define PORT_WRCONFIG_INEN_Msk                (_U_(0x1) << PORT_WRCONFIG_INEN_Pos)                 /**< (PORT_WRCONFIG) Input Enable Mask */
+#define PORT_WRCONFIG_INEN(value)             (PORT_WRCONFIG_INEN_Msk & ((value) << PORT_WRCONFIG_INEN_Pos))
+#define PORT_WRCONFIG_PULLEN_Pos              _U_(18)                                              /**< (PORT_WRCONFIG) Pull Enable Position */
+#define PORT_WRCONFIG_PULLEN_Msk              (_U_(0x1) << PORT_WRCONFIG_PULLEN_Pos)               /**< (PORT_WRCONFIG) Pull Enable Mask */
+#define PORT_WRCONFIG_PULLEN(value)           (PORT_WRCONFIG_PULLEN_Msk & ((value) << PORT_WRCONFIG_PULLEN_Pos))
+#define PORT_WRCONFIG_DRVSTR_Pos              _U_(22)                                              /**< (PORT_WRCONFIG) Output Driver Strength Selection Position */
+#define PORT_WRCONFIG_DRVSTR_Msk              (_U_(0x1) << PORT_WRCONFIG_DRVSTR_Pos)               /**< (PORT_WRCONFIG) Output Driver Strength Selection Mask */
+#define PORT_WRCONFIG_DRVSTR(value)           (PORT_WRCONFIG_DRVSTR_Msk & ((value) << PORT_WRCONFIG_DRVSTR_Pos))
+#define PORT_WRCONFIG_PMUX_Pos                _U_(24)                                              /**< (PORT_WRCONFIG) Peripheral Multiplexing Position */
+#define PORT_WRCONFIG_PMUX_Msk                (_U_(0xF) << PORT_WRCONFIG_PMUX_Pos)                 /**< (PORT_WRCONFIG) Peripheral Multiplexing Mask */
+#define PORT_WRCONFIG_PMUX(value)             (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))
+#define PORT_WRCONFIG_WRPMUX_Pos              _U_(28)                                              /**< (PORT_WRCONFIG) Write PMUX Position */
+#define PORT_WRCONFIG_WRPMUX_Msk              (_U_(0x1) << PORT_WRCONFIG_WRPMUX_Pos)               /**< (PORT_WRCONFIG) Write PMUX Mask */
+#define PORT_WRCONFIG_WRPMUX(value)           (PORT_WRCONFIG_WRPMUX_Msk & ((value) << PORT_WRCONFIG_WRPMUX_Pos))
+#define PORT_WRCONFIG_WRPINCFG_Pos            _U_(30)                                              /**< (PORT_WRCONFIG) Write PINCFG Position */
+#define PORT_WRCONFIG_WRPINCFG_Msk            (_U_(0x1) << PORT_WRCONFIG_WRPINCFG_Pos)             /**< (PORT_WRCONFIG) Write PINCFG Mask */
+#define PORT_WRCONFIG_WRPINCFG(value)         (PORT_WRCONFIG_WRPINCFG_Msk & ((value) << PORT_WRCONFIG_WRPINCFG_Pos))
+#define PORT_WRCONFIG_HWSEL_Pos               _U_(31)                                              /**< (PORT_WRCONFIG) Half-Word Select Position */
+#define PORT_WRCONFIG_HWSEL_Msk               (_U_(0x1) << PORT_WRCONFIG_HWSEL_Pos)                /**< (PORT_WRCONFIG) Half-Word Select Mask */
+#define PORT_WRCONFIG_HWSEL(value)            (PORT_WRCONFIG_HWSEL_Msk & ((value) << PORT_WRCONFIG_HWSEL_Pos))
+#define PORT_WRCONFIG_Msk                     _U_(0xDF47FFFF)                                      /**< (PORT_WRCONFIG) Register Mask  */
+
+
+/* -------- PORT_EVCTRL : (PORT Offset: 0x2C) (R/W 32) Event Input Control -------- */
+#define PORT_EVCTRL_RESETVALUE                _U_(0x00)                                            /**<  (PORT_EVCTRL) Event Input Control  Reset Value */
+
+#define PORT_EVCTRL_PID0_Pos                  _U_(0)                                               /**< (PORT_EVCTRL) PORT Event Pin Identifier 0 Position */
+#define PORT_EVCTRL_PID0_Msk                  (_U_(0x1F) << PORT_EVCTRL_PID0_Pos)                  /**< (PORT_EVCTRL) PORT Event Pin Identifier 0 Mask */
+#define PORT_EVCTRL_PID0(value)               (PORT_EVCTRL_PID0_Msk & ((value) << PORT_EVCTRL_PID0_Pos))
+#define PORT_EVCTRL_EVACT0_Pos                _U_(5)                                               /**< (PORT_EVCTRL) PORT Event Action 0 Position */
+#define PORT_EVCTRL_EVACT0_Msk                (_U_(0x3) << PORT_EVCTRL_EVACT0_Pos)                 /**< (PORT_EVCTRL) PORT Event Action 0 Mask */
+#define PORT_EVCTRL_EVACT0(value)             (PORT_EVCTRL_EVACT0_Msk & ((value) << PORT_EVCTRL_EVACT0_Pos))
+#define   PORT_EVCTRL_EVACT0_OUT_Val          _U_(0x0)                                             /**< (PORT_EVCTRL) Event output to pin  */
+#define   PORT_EVCTRL_EVACT0_SET_Val          _U_(0x1)                                             /**< (PORT_EVCTRL) Set output register of pin on event  */
+#define   PORT_EVCTRL_EVACT0_CLR_Val          _U_(0x2)                                             /**< (PORT_EVCTRL) Clear output register of pin on event  */
+#define   PORT_EVCTRL_EVACT0_TGL_Val          _U_(0x3)                                             /**< (PORT_EVCTRL) Toggle output register of pin on event  */
+#define PORT_EVCTRL_EVACT0_OUT                (PORT_EVCTRL_EVACT0_OUT_Val << PORT_EVCTRL_EVACT0_Pos) /**< (PORT_EVCTRL) Event output to pin Position  */
+#define PORT_EVCTRL_EVACT0_SET                (PORT_EVCTRL_EVACT0_SET_Val << PORT_EVCTRL_EVACT0_Pos) /**< (PORT_EVCTRL) Set output register of pin on event Position  */
+#define PORT_EVCTRL_EVACT0_CLR                (PORT_EVCTRL_EVACT0_CLR_Val << PORT_EVCTRL_EVACT0_Pos) /**< (PORT_EVCTRL) Clear output register of pin on event Position  */
+#define PORT_EVCTRL_EVACT0_TGL                (PORT_EVCTRL_EVACT0_TGL_Val << PORT_EVCTRL_EVACT0_Pos) /**< (PORT_EVCTRL) Toggle output register of pin on event Position  */
+#define PORT_EVCTRL_PORTEI0_Pos               _U_(7)                                               /**< (PORT_EVCTRL) PORT Event Input Enable 0 Position */
+#define PORT_EVCTRL_PORTEI0_Msk               (_U_(0x1) << PORT_EVCTRL_PORTEI0_Pos)                /**< (PORT_EVCTRL) PORT Event Input Enable 0 Mask */
+#define PORT_EVCTRL_PORTEI0(value)            (PORT_EVCTRL_PORTEI0_Msk & ((value) << PORT_EVCTRL_PORTEI0_Pos))
+#define PORT_EVCTRL_PID1_Pos                  _U_(8)                                               /**< (PORT_EVCTRL) PORT Event Pin Identifier 1 Position */
+#define PORT_EVCTRL_PID1_Msk                  (_U_(0x1F) << PORT_EVCTRL_PID1_Pos)                  /**< (PORT_EVCTRL) PORT Event Pin Identifier 1 Mask */
+#define PORT_EVCTRL_PID1(value)               (PORT_EVCTRL_PID1_Msk & ((value) << PORT_EVCTRL_PID1_Pos))
+#define PORT_EVCTRL_EVACT1_Pos                _U_(13)                                              /**< (PORT_EVCTRL) PORT Event Action 1 Position */
+#define PORT_EVCTRL_EVACT1_Msk                (_U_(0x3) << PORT_EVCTRL_EVACT1_Pos)                 /**< (PORT_EVCTRL) PORT Event Action 1 Mask */
+#define PORT_EVCTRL_EVACT1(value)             (PORT_EVCTRL_EVACT1_Msk & ((value) << PORT_EVCTRL_EVACT1_Pos))
+#define PORT_EVCTRL_PORTEI1_Pos               _U_(15)                                              /**< (PORT_EVCTRL) PORT Event Input Enable 1 Position */
+#define PORT_EVCTRL_PORTEI1_Msk               (_U_(0x1) << PORT_EVCTRL_PORTEI1_Pos)                /**< (PORT_EVCTRL) PORT Event Input Enable 1 Mask */
+#define PORT_EVCTRL_PORTEI1(value)            (PORT_EVCTRL_PORTEI1_Msk & ((value) << PORT_EVCTRL_PORTEI1_Pos))
+#define PORT_EVCTRL_PID2_Pos                  _U_(16)                                              /**< (PORT_EVCTRL) PORT Event Pin Identifier 2 Position */
+#define PORT_EVCTRL_PID2_Msk                  (_U_(0x1F) << PORT_EVCTRL_PID2_Pos)                  /**< (PORT_EVCTRL) PORT Event Pin Identifier 2 Mask */
+#define PORT_EVCTRL_PID2(value)               (PORT_EVCTRL_PID2_Msk & ((value) << PORT_EVCTRL_PID2_Pos))
+#define PORT_EVCTRL_EVACT2_Pos                _U_(21)                                              /**< (PORT_EVCTRL) PORT Event Action 2 Position */
+#define PORT_EVCTRL_EVACT2_Msk                (_U_(0x3) << PORT_EVCTRL_EVACT2_Pos)                 /**< (PORT_EVCTRL) PORT Event Action 2 Mask */
+#define PORT_EVCTRL_EVACT2(value)             (PORT_EVCTRL_EVACT2_Msk & ((value) << PORT_EVCTRL_EVACT2_Pos))
+#define PORT_EVCTRL_PORTEI2_Pos               _U_(23)                                              /**< (PORT_EVCTRL) PORT Event Input Enable 2 Position */
+#define PORT_EVCTRL_PORTEI2_Msk               (_U_(0x1) << PORT_EVCTRL_PORTEI2_Pos)                /**< (PORT_EVCTRL) PORT Event Input Enable 2 Mask */
+#define PORT_EVCTRL_PORTEI2(value)            (PORT_EVCTRL_PORTEI2_Msk & ((value) << PORT_EVCTRL_PORTEI2_Pos))
+#define PORT_EVCTRL_PID3_Pos                  _U_(24)                                              /**< (PORT_EVCTRL) PORT Event Pin Identifier 3 Position */
+#define PORT_EVCTRL_PID3_Msk                  (_U_(0x1F) << PORT_EVCTRL_PID3_Pos)                  /**< (PORT_EVCTRL) PORT Event Pin Identifier 3 Mask */
+#define PORT_EVCTRL_PID3(value)               (PORT_EVCTRL_PID3_Msk & ((value) << PORT_EVCTRL_PID3_Pos))
+#define PORT_EVCTRL_EVACT3_Pos                _U_(29)                                              /**< (PORT_EVCTRL) PORT Event Action 3 Position */
+#define PORT_EVCTRL_EVACT3_Msk                (_U_(0x3) << PORT_EVCTRL_EVACT3_Pos)                 /**< (PORT_EVCTRL) PORT Event Action 3 Mask */
+#define PORT_EVCTRL_EVACT3(value)             (PORT_EVCTRL_EVACT3_Msk & ((value) << PORT_EVCTRL_EVACT3_Pos))
+#define PORT_EVCTRL_PORTEI3_Pos               _U_(31)                                              /**< (PORT_EVCTRL) PORT Event Input Enable 3 Position */
+#define PORT_EVCTRL_PORTEI3_Msk               (_U_(0x1) << PORT_EVCTRL_PORTEI3_Pos)                /**< (PORT_EVCTRL) PORT Event Input Enable 3 Mask */
+#define PORT_EVCTRL_PORTEI3(value)            (PORT_EVCTRL_PORTEI3_Msk & ((value) << PORT_EVCTRL_PORTEI3_Pos))
+#define PORT_EVCTRL_Msk                       _U_(0xFFFFFFFF)                                      /**< (PORT_EVCTRL) Register Mask  */
+
+
+/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) Peripheral Multiplexing -------- */
+#define PORT_PMUX_RESETVALUE                  _U_(0x00)                                            /**<  (PORT_PMUX) Peripheral Multiplexing  Reset Value */
+
+#define PORT_PMUX_PMUXE_Pos                   _U_(0)                                               /**< (PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin Position */
+#define PORT_PMUX_PMUXE_Msk                   (_U_(0xF) << PORT_PMUX_PMUXE_Pos)                    /**< (PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin Mask */
+#define PORT_PMUX_PMUXE(value)                (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))
+#define PORT_PMUX_PMUXO_Pos                   _U_(4)                                               /**< (PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin Position */
+#define PORT_PMUX_PMUXO_Msk                   (_U_(0xF) << PORT_PMUX_PMUXO_Pos)                    /**< (PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin Mask */
+#define PORT_PMUX_PMUXO(value)                (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))
+#define PORT_PMUX_Msk                         _U_(0xFF)                                            /**< (PORT_PMUX) Register Mask  */
+
+
+/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) Pin Configuration -------- */
+#define PORT_PINCFG_RESETVALUE                _U_(0x00)                                            /**<  (PORT_PINCFG) Pin Configuration  Reset Value */
+
+#define PORT_PINCFG_PMUXEN_Pos                _U_(0)                                               /**< (PORT_PINCFG) Peripheral Multiplexer Enable Position */
+#define PORT_PINCFG_PMUXEN_Msk                (_U_(0x1) << PORT_PINCFG_PMUXEN_Pos)                 /**< (PORT_PINCFG) Peripheral Multiplexer Enable Mask */
+#define PORT_PINCFG_PMUXEN(value)             (PORT_PINCFG_PMUXEN_Msk & ((value) << PORT_PINCFG_PMUXEN_Pos))
+#define PORT_PINCFG_INEN_Pos                  _U_(1)                                               /**< (PORT_PINCFG) Input Enable Position */
+#define PORT_PINCFG_INEN_Msk                  (_U_(0x1) << PORT_PINCFG_INEN_Pos)                   /**< (PORT_PINCFG) Input Enable Mask */
+#define PORT_PINCFG_INEN(value)               (PORT_PINCFG_INEN_Msk & ((value) << PORT_PINCFG_INEN_Pos))
+#define PORT_PINCFG_PULLEN_Pos                _U_(2)                                               /**< (PORT_PINCFG) Pull Enable Position */
+#define PORT_PINCFG_PULLEN_Msk                (_U_(0x1) << PORT_PINCFG_PULLEN_Pos)                 /**< (PORT_PINCFG) Pull Enable Mask */
+#define PORT_PINCFG_PULLEN(value)             (PORT_PINCFG_PULLEN_Msk & ((value) << PORT_PINCFG_PULLEN_Pos))
+#define PORT_PINCFG_DRVSTR_Pos                _U_(6)                                               /**< (PORT_PINCFG) Output Driver Strength Selection Position */
+#define PORT_PINCFG_DRVSTR_Msk                (_U_(0x1) << PORT_PINCFG_DRVSTR_Pos)                 /**< (PORT_PINCFG) Output Driver Strength Selection Mask */
+#define PORT_PINCFG_DRVSTR(value)             (PORT_PINCFG_DRVSTR_Msk & ((value) << PORT_PINCFG_DRVSTR_Pos))
+#define PORT_PINCFG_Msk                       _U_(0x47)                                            /**< (PORT_PINCFG) Register Mask  */
+
+
+/** \brief PORT register offsets definitions */
+#define PORT_DIR_REG_OFST              (0x00)              /**< (PORT_DIR) Data Direction Offset */
+#define PORT_DIRCLR_REG_OFST           (0x04)              /**< (PORT_DIRCLR) Data Direction Clear Offset */
+#define PORT_DIRSET_REG_OFST           (0x08)              /**< (PORT_DIRSET) Data Direction Set Offset */
+#define PORT_DIRTGL_REG_OFST           (0x0C)              /**< (PORT_DIRTGL) Data Direction Toggle Offset */
+#define PORT_OUT_REG_OFST              (0x10)              /**< (PORT_OUT) Data Output Value Offset */
+#define PORT_OUTCLR_REG_OFST           (0x14)              /**< (PORT_OUTCLR) Data Output Value Clear Offset */
+#define PORT_OUTSET_REG_OFST           (0x18)              /**< (PORT_OUTSET) Data Output Value Set Offset */
+#define PORT_OUTTGL_REG_OFST           (0x1C)              /**< (PORT_OUTTGL) Data Output Value Toggle Offset */
+#define PORT_IN_REG_OFST               (0x20)              /**< (PORT_IN) Data Input Value Offset */
+#define PORT_CTRL_REG_OFST             (0x24)              /**< (PORT_CTRL) Control Offset */
+#define PORT_WRCONFIG_REG_OFST         (0x28)              /**< (PORT_WRCONFIG) Write Configuration Offset */
+#define PORT_EVCTRL_REG_OFST           (0x2C)              /**< (PORT_EVCTRL) Event Input Control Offset */
+#define PORT_PMUX_REG_OFST             (0x30)              /**< (PORT_PMUX) Peripheral Multiplexing Offset */
+#define PORT_PINCFG_REG_OFST           (0x40)              /**< (PORT_PINCFG) Pin Configuration Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief GROUP register API structure */
+typedef struct
+{
+  __IO  uint32_t                       PORT_DIR;           /**< Offset: 0x00 (R/W  32) Data Direction */
+  __IO  uint32_t                       PORT_DIRCLR;        /**< Offset: 0x04 (R/W  32) Data Direction Clear */
+  __IO  uint32_t                       PORT_DIRSET;        /**< Offset: 0x08 (R/W  32) Data Direction Set */
+  __IO  uint32_t                       PORT_DIRTGL;        /**< Offset: 0x0C (R/W  32) Data Direction Toggle */
+  __IO  uint32_t                       PORT_OUT;           /**< Offset: 0x10 (R/W  32) Data Output Value */
+  __IO  uint32_t                       PORT_OUTCLR;        /**< Offset: 0x14 (R/W  32) Data Output Value Clear */
+  __IO  uint32_t                       PORT_OUTSET;        /**< Offset: 0x18 (R/W  32) Data Output Value Set */
+  __IO  uint32_t                       PORT_OUTTGL;        /**< Offset: 0x1C (R/W  32) Data Output Value Toggle */
+  __I   uint32_t                       PORT_IN;            /**< Offset: 0x20 (R/   32) Data Input Value */
+  __IO  uint32_t                       PORT_CTRL;          /**< Offset: 0x24 (R/W  32) Control */
+  __O   uint32_t                       PORT_WRCONFIG;      /**< Offset: 0x28 ( /W  32) Write Configuration */
+  __IO  uint32_t                       PORT_EVCTRL;        /**< Offset: 0x2C (R/W  32) Event Input Control */
+  __IO  uint8_t                        PORT_PMUX[16];      /**< Offset: 0x30 (R/W  8) Peripheral Multiplexing */
+  __IO  uint8_t                        PORT_PINCFG[32];    /**< Offset: 0x40 (R/W  8) Pin Configuration */
+  __I   uint8_t                        Reserved1[0x20];
+} port_group_registers_t;
+
+#define PORT_GROUP_NUMBER _U_(4)
+
+/** \brief PORT register API structure */
+typedef struct
+{  /* Port Module */
+        port_group_registers_t         GROUP[PORT_GROUP_NUMBER]; /**< Offset: 0x00  */
+} port_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _SAMD51_PORT_COMPONENT_H_ */
Index: /asp_wio_terminal/trunk/target/samd51_gcc/lib/sercom.h
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/lib/sercom.h	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/lib/sercom.h	(revision 460)
@@ -0,0 +1,2200 @@
+/**
+ * \brief Component description for SERCOM
+ *
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * Subject to your compliance with these terms, you may use Microchip software and any derivatives
+ * exclusively with Microchip products. It is your responsibility to comply with third party license
+ * terms applicable to your use of third party software (including open source software) that may
+ * accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
+ * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
+ * FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
+ * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
+ * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ */
+
+/* file generated from device description version 2020-03-12T17:26:00Z */
+#ifndef _SAMD51_SERCOM_COMPONENT_H_
+#define _SAMD51_SERCOM_COMPONENT_H_
+
+/* ************************************************************************** */
+/*   SOFTWARE API DEFINITION FOR SERCOM                                       */
+/* ************************************************************************** */
+
+/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM Control A -------- */
+#define SERCOM_I2CM_CTRLA_RESETVALUE          _U_(0x00)                                            /**<  (SERCOM_I2CM_CTRLA) I2CM Control A  Reset Value */
+
+#define SERCOM_I2CM_CTRLA_SWRST_Pos           _U_(0)                                               /**< (SERCOM_I2CM_CTRLA) Software Reset Position */
+#define SERCOM_I2CM_CTRLA_SWRST_Msk           (_U_(0x1) << SERCOM_I2CM_CTRLA_SWRST_Pos)            /**< (SERCOM_I2CM_CTRLA) Software Reset Mask */
+#define SERCOM_I2CM_CTRLA_SWRST(value)        (SERCOM_I2CM_CTRLA_SWRST_Msk & ((value) << SERCOM_I2CM_CTRLA_SWRST_Pos))
+#define SERCOM_I2CM_CTRLA_ENABLE_Pos          _U_(1)                                               /**< (SERCOM_I2CM_CTRLA) Enable Position */
+#define SERCOM_I2CM_CTRLA_ENABLE_Msk          (_U_(0x1) << SERCOM_I2CM_CTRLA_ENABLE_Pos)           /**< (SERCOM_I2CM_CTRLA) Enable Mask */
+#define SERCOM_I2CM_CTRLA_ENABLE(value)       (SERCOM_I2CM_CTRLA_ENABLE_Msk & ((value) << SERCOM_I2CM_CTRLA_ENABLE_Pos))
+#define SERCOM_I2CM_CTRLA_MODE_Pos            _U_(2)                                               /**< (SERCOM_I2CM_CTRLA) Operating Mode Position */
+#define SERCOM_I2CM_CTRLA_MODE_Msk            (_U_(0x7) << SERCOM_I2CM_CTRLA_MODE_Pos)             /**< (SERCOM_I2CM_CTRLA) Operating Mode Mask */
+#define SERCOM_I2CM_CTRLA_MODE(value)         (SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos))
+#define   SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val _U_(0x0)                                             /**< (SERCOM_I2CM_CTRLA) USART with external clock  */
+#define   SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val _U_(0x1)                                             /**< (SERCOM_I2CM_CTRLA) USART with internal clock  */
+#define   SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val _U_(0x2)                                             /**< (SERCOM_I2CM_CTRLA) SPI in slave operation  */
+#define   SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val _U_(0x3)                                             /**< (SERCOM_I2CM_CTRLA) SPI in master operation  */
+#define   SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val _U_(0x4)                                             /**< (SERCOM_I2CM_CTRLA) I2C slave operation  */
+#define   SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val _U_(0x5)                                             /**< (SERCOM_I2CM_CTRLA) I2C master operation  */
+#define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK  (SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos) /**< (SERCOM_I2CM_CTRLA) USART with external clock Position  */
+#define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK  (SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos) /**< (SERCOM_I2CM_CTRLA) USART with internal clock Position  */
+#define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE      (SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos) /**< (SERCOM_I2CM_CTRLA) SPI in slave operation Position  */
+#define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER     (SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos) /**< (SERCOM_I2CM_CTRLA) SPI in master operation Position  */
+#define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE      (SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos) /**< (SERCOM_I2CM_CTRLA) I2C slave operation Position  */
+#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER     (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos) /**< (SERCOM_I2CM_CTRLA) I2C master operation Position  */
+#define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos        _U_(7)                                               /**< (SERCOM_I2CM_CTRLA) Run in Standby Position */
+#define SERCOM_I2CM_CTRLA_RUNSTDBY_Msk        (_U_(0x1) << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)         /**< (SERCOM_I2CM_CTRLA) Run in Standby Mask */
+#define SERCOM_I2CM_CTRLA_RUNSTDBY(value)     (SERCOM_I2CM_CTRLA_RUNSTDBY_Msk & ((value) << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos))
+#define SERCOM_I2CM_CTRLA_PINOUT_Pos          _U_(16)                                              /**< (SERCOM_I2CM_CTRLA) Pin Usage Position */
+#define SERCOM_I2CM_CTRLA_PINOUT_Msk          (_U_(0x1) << SERCOM_I2CM_CTRLA_PINOUT_Pos)           /**< (SERCOM_I2CM_CTRLA) Pin Usage Mask */
+#define SERCOM_I2CM_CTRLA_PINOUT(value)       (SERCOM_I2CM_CTRLA_PINOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_PINOUT_Pos))
+#define SERCOM_I2CM_CTRLA_SDAHOLD_Pos         _U_(20)                                              /**< (SERCOM_I2CM_CTRLA) SDA Hold Time Position */
+#define SERCOM_I2CM_CTRLA_SDAHOLD_Msk         (_U_(0x3) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)          /**< (SERCOM_I2CM_CTRLA) SDA Hold Time Mask */
+#define SERCOM_I2CM_CTRLA_SDAHOLD(value)      (SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos))
+#define   SERCOM_I2CM_CTRLA_SDAHOLD_DISABLE_Val _U_(0x0)                                             /**< (SERCOM_I2CM_CTRLA) Disabled  */
+#define   SERCOM_I2CM_CTRLA_SDAHOLD_75NS_Val  _U_(0x1)                                             /**< (SERCOM_I2CM_CTRLA) 50-100ns hold time  */
+#define   SERCOM_I2CM_CTRLA_SDAHOLD_450NS_Val _U_(0x2)                                             /**< (SERCOM_I2CM_CTRLA) 300-600ns hold time  */
+#define   SERCOM_I2CM_CTRLA_SDAHOLD_600NS_Val _U_(0x3)                                             /**< (SERCOM_I2CM_CTRLA) 400-800ns hold time  */
+#define SERCOM_I2CM_CTRLA_SDAHOLD_DISABLE     (SERCOM_I2CM_CTRLA_SDAHOLD_DISABLE_Val << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) /**< (SERCOM_I2CM_CTRLA) Disabled Position  */
+#define SERCOM_I2CM_CTRLA_SDAHOLD_75NS        (SERCOM_I2CM_CTRLA_SDAHOLD_75NS_Val << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) /**< (SERCOM_I2CM_CTRLA) 50-100ns hold time Position  */
+#define SERCOM_I2CM_CTRLA_SDAHOLD_450NS       (SERCOM_I2CM_CTRLA_SDAHOLD_450NS_Val << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) /**< (SERCOM_I2CM_CTRLA) 300-600ns hold time Position  */
+#define SERCOM_I2CM_CTRLA_SDAHOLD_600NS       (SERCOM_I2CM_CTRLA_SDAHOLD_600NS_Val << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) /**< (SERCOM_I2CM_CTRLA) 400-800ns hold time Position  */
+#define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos        _U_(22)                                              /**< (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout Position */
+#define SERCOM_I2CM_CTRLA_MEXTTOEN_Msk        (_U_(0x1) << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)         /**< (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout Mask */
+#define SERCOM_I2CM_CTRLA_MEXTTOEN(value)     (SERCOM_I2CM_CTRLA_MEXTTOEN_Msk & ((value) << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos))
+#define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos        _U_(23)                                              /**< (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout Position */
+#define SERCOM_I2CM_CTRLA_SEXTTOEN_Msk        (_U_(0x1) << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)         /**< (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout Mask */
+#define SERCOM_I2CM_CTRLA_SEXTTOEN(value)     (SERCOM_I2CM_CTRLA_SEXTTOEN_Msk & ((value) << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos))
+#define SERCOM_I2CM_CTRLA_SPEED_Pos           _U_(24)                                              /**< (SERCOM_I2CM_CTRLA) Transfer Speed Position */
+#define SERCOM_I2CM_CTRLA_SPEED_Msk           (_U_(0x3) << SERCOM_I2CM_CTRLA_SPEED_Pos)            /**< (SERCOM_I2CM_CTRLA) Transfer Speed Mask */
+#define SERCOM_I2CM_CTRLA_SPEED(value)        (SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos))
+#define   SERCOM_I2CM_CTRLA_SPEED_STANDARD_AND_FAST_MODE_Val _U_(0x0)                                             /**< (SERCOM_I2CM_CTRLA) Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz   */
+#define   SERCOM_I2CM_CTRLA_SPEED_FASTPLUS_MODE_Val _U_(0x1)                                             /**< (SERCOM_I2CM_CTRLA) Fast-mode Plus Upto 1MHz  */
+#define   SERCOM_I2CM_CTRLA_SPEED_HIGH_SPEED_MODE_Val _U_(0x2)                                             /**< (SERCOM_I2CM_CTRLA) High-speed mode Upto 3.4MHz  */
+#define SERCOM_I2CM_CTRLA_SPEED_STANDARD_AND_FAST_MODE (SERCOM_I2CM_CTRLA_SPEED_STANDARD_AND_FAST_MODE_Val << SERCOM_I2CM_CTRLA_SPEED_Pos) /**< (SERCOM_I2CM_CTRLA) Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz  Position  */
+#define SERCOM_I2CM_CTRLA_SPEED_FASTPLUS_MODE (SERCOM_I2CM_CTRLA_SPEED_FASTPLUS_MODE_Val << SERCOM_I2CM_CTRLA_SPEED_Pos) /**< (SERCOM_I2CM_CTRLA) Fast-mode Plus Upto 1MHz Position  */
+#define SERCOM_I2CM_CTRLA_SPEED_HIGH_SPEED_MODE (SERCOM_I2CM_CTRLA_SPEED_HIGH_SPEED_MODE_Val << SERCOM_I2CM_CTRLA_SPEED_Pos) /**< (SERCOM_I2CM_CTRLA) High-speed mode Upto 3.4MHz Position  */
+#define SERCOM_I2CM_CTRLA_SCLSM_Pos           _U_(27)                                              /**< (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode Position */
+#define SERCOM_I2CM_CTRLA_SCLSM_Msk           (_U_(0x1) << SERCOM_I2CM_CTRLA_SCLSM_Pos)            /**< (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode Mask */
+#define SERCOM_I2CM_CTRLA_SCLSM(value)        (SERCOM_I2CM_CTRLA_SCLSM_Msk & ((value) << SERCOM_I2CM_CTRLA_SCLSM_Pos))
+#define SERCOM_I2CM_CTRLA_INACTOUT_Pos        _U_(28)                                              /**< (SERCOM_I2CM_CTRLA) Inactive Time-Out Position */
+#define SERCOM_I2CM_CTRLA_INACTOUT_Msk        (_U_(0x3) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)         /**< (SERCOM_I2CM_CTRLA) Inactive Time-Out Mask */
+#define SERCOM_I2CM_CTRLA_INACTOUT(value)     (SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos))
+#define   SERCOM_I2CM_CTRLA_INACTOUT_DISABLE_Val _U_(0x0)                                             /**< (SERCOM_I2CM_CTRLA) Disabled  */
+#define   SERCOM_I2CM_CTRLA_INACTOUT_55US_Val _U_(0x1)                                             /**< (SERCOM_I2CM_CTRLA) 5-6 SCL Time-Out(50-60us)  */
+#define   SERCOM_I2CM_CTRLA_INACTOUT_105US_Val _U_(0x2)                                             /**< (SERCOM_I2CM_CTRLA) 10-11 SCL Time-Out(100-110us)  */
+#define   SERCOM_I2CM_CTRLA_INACTOUT_205US_Val _U_(0x3)                                             /**< (SERCOM_I2CM_CTRLA) 20-21 SCL Time-Out(200-210us)  */
+#define SERCOM_I2CM_CTRLA_INACTOUT_DISABLE    (SERCOM_I2CM_CTRLA_INACTOUT_DISABLE_Val << SERCOM_I2CM_CTRLA_INACTOUT_Pos) /**< (SERCOM_I2CM_CTRLA) Disabled Position  */
+#define SERCOM_I2CM_CTRLA_INACTOUT_55US       (SERCOM_I2CM_CTRLA_INACTOUT_55US_Val << SERCOM_I2CM_CTRLA_INACTOUT_Pos) /**< (SERCOM_I2CM_CTRLA) 5-6 SCL Time-Out(50-60us) Position  */
+#define SERCOM_I2CM_CTRLA_INACTOUT_105US      (SERCOM_I2CM_CTRLA_INACTOUT_105US_Val << SERCOM_I2CM_CTRLA_INACTOUT_Pos) /**< (SERCOM_I2CM_CTRLA) 10-11 SCL Time-Out(100-110us) Position  */
+#define SERCOM_I2CM_CTRLA_INACTOUT_205US      (SERCOM_I2CM_CTRLA_INACTOUT_205US_Val << SERCOM_I2CM_CTRLA_INACTOUT_Pos) /**< (SERCOM_I2CM_CTRLA) 20-21 SCL Time-Out(200-210us) Position  */
+#define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos       _U_(30)                                              /**< (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable Position */
+#define SERCOM_I2CM_CTRLA_LOWTOUTEN_Msk       (_U_(0x1) << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)        /**< (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable Mask */
+#define SERCOM_I2CM_CTRLA_LOWTOUTEN(value)    (SERCOM_I2CM_CTRLA_LOWTOUTEN_Msk & ((value) << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos))
+#define SERCOM_I2CM_CTRLA_Msk                 _U_(0x7BF1009F)                                      /**< (SERCOM_I2CM_CTRLA) Register Mask  */
+
+
+/* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS Control A -------- */
+#define SERCOM_I2CS_CTRLA_RESETVALUE          _U_(0x00)                                            /**<  (SERCOM_I2CS_CTRLA) I2CS Control A  Reset Value */
+
+#define SERCOM_I2CS_CTRLA_SWRST_Pos           _U_(0)                                               /**< (SERCOM_I2CS_CTRLA) Software Reset Position */
+#define SERCOM_I2CS_CTRLA_SWRST_Msk           (_U_(0x1) << SERCOM_I2CS_CTRLA_SWRST_Pos)            /**< (SERCOM_I2CS_CTRLA) Software Reset Mask */
+#define SERCOM_I2CS_CTRLA_SWRST(value)        (SERCOM_I2CS_CTRLA_SWRST_Msk & ((value) << SERCOM_I2CS_CTRLA_SWRST_Pos))
+#define SERCOM_I2CS_CTRLA_ENABLE_Pos          _U_(1)                                               /**< (SERCOM_I2CS_CTRLA) Enable Position */
+#define SERCOM_I2CS_CTRLA_ENABLE_Msk          (_U_(0x1) << SERCOM_I2CS_CTRLA_ENABLE_Pos)           /**< (SERCOM_I2CS_CTRLA) Enable Mask */
+#define SERCOM_I2CS_CTRLA_ENABLE(value)       (SERCOM_I2CS_CTRLA_ENABLE_Msk & ((value) << SERCOM_I2CS_CTRLA_ENABLE_Pos))
+#define SERCOM_I2CS_CTRLA_MODE_Pos            _U_(2)                                               /**< (SERCOM_I2CS_CTRLA) Operating Mode Position */
+#define SERCOM_I2CS_CTRLA_MODE_Msk            (_U_(0x7) << SERCOM_I2CS_CTRLA_MODE_Pos)             /**< (SERCOM_I2CS_CTRLA) Operating Mode Mask */
+#define SERCOM_I2CS_CTRLA_MODE(value)         (SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos))
+#define   SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val _U_(0x0)                                             /**< (SERCOM_I2CS_CTRLA) USART with external clock  */
+#define   SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val _U_(0x1)                                             /**< (SERCOM_I2CS_CTRLA) USART with internal clock  */
+#define   SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val _U_(0x2)                                             /**< (SERCOM_I2CS_CTRLA) SPI in slave operation  */
+#define   SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val _U_(0x3)                                             /**< (SERCOM_I2CS_CTRLA) SPI in master operation  */
+#define   SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val _U_(0x4)                                             /**< (SERCOM_I2CS_CTRLA) I2C slave operation  */
+#define   SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val _U_(0x5)                                             /**< (SERCOM_I2CS_CTRLA) I2C master operation  */
+#define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK  (SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos) /**< (SERCOM_I2CS_CTRLA) USART with external clock Position  */
+#define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK  (SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos) /**< (SERCOM_I2CS_CTRLA) USART with internal clock Position  */
+#define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE      (SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos) /**< (SERCOM_I2CS_CTRLA) SPI in slave operation Position  */
+#define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER     (SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos) /**< (SERCOM_I2CS_CTRLA) SPI in master operation Position  */
+#define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE      (SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos) /**< (SERCOM_I2CS_CTRLA) I2C slave operation Position  */
+#define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER     (SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos) /**< (SERCOM_I2CS_CTRLA) I2C master operation Position  */
+#define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos        _U_(7)                                               /**< (SERCOM_I2CS_CTRLA) Run during Standby Position */
+#define SERCOM_I2CS_CTRLA_RUNSTDBY_Msk        (_U_(0x1) << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)         /**< (SERCOM_I2CS_CTRLA) Run during Standby Mask */
+#define SERCOM_I2CS_CTRLA_RUNSTDBY(value)     (SERCOM_I2CS_CTRLA_RUNSTDBY_Msk & ((value) << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos))
+#define SERCOM_I2CS_CTRLA_PINOUT_Pos          _U_(16)                                              /**< (SERCOM_I2CS_CTRLA) Pin Usage Position */
+#define SERCOM_I2CS_CTRLA_PINOUT_Msk          (_U_(0x1) << SERCOM_I2CS_CTRLA_PINOUT_Pos)           /**< (SERCOM_I2CS_CTRLA) Pin Usage Mask */
+#define SERCOM_I2CS_CTRLA_PINOUT(value)       (SERCOM_I2CS_CTRLA_PINOUT_Msk & ((value) << SERCOM_I2CS_CTRLA_PINOUT_Pos))
+#define SERCOM_I2CS_CTRLA_SDAHOLD_Pos         _U_(20)                                              /**< (SERCOM_I2CS_CTRLA) SDA Hold Time Position */
+#define SERCOM_I2CS_CTRLA_SDAHOLD_Msk         (_U_(0x3) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)          /**< (SERCOM_I2CS_CTRLA) SDA Hold Time Mask */
+#define SERCOM_I2CS_CTRLA_SDAHOLD(value)      (SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))
+#define   SERCOM_I2CS_CTRLA_SDAHOLD_DISABLE_Val _U_(0x0)                                             /**< (SERCOM_I2CS_CTRLA) Disabled  */
+#define   SERCOM_I2CS_CTRLA_SDAHOLD_75NS_Val  _U_(0x1)                                             /**< (SERCOM_I2CS_CTRLA) 50-100ns hold time  */
+#define   SERCOM_I2CS_CTRLA_SDAHOLD_450NS_Val _U_(0x2)                                             /**< (SERCOM_I2CS_CTRLA) 300-600ns hold time  */
+#define   SERCOM_I2CS_CTRLA_SDAHOLD_600NS_Val _U_(0x3)                                             /**< (SERCOM_I2CS_CTRLA) 400-800ns hold time  */
+#define SERCOM_I2CS_CTRLA_SDAHOLD_DISABLE     (SERCOM_I2CS_CTRLA_SDAHOLD_DISABLE_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) /**< (SERCOM_I2CS_CTRLA) Disabled Position  */
+#define SERCOM_I2CS_CTRLA_SDAHOLD_75NS        (SERCOM_I2CS_CTRLA_SDAHOLD_75NS_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) /**< (SERCOM_I2CS_CTRLA) 50-100ns hold time Position  */
+#define SERCOM_I2CS_CTRLA_SDAHOLD_450NS       (SERCOM_I2CS_CTRLA_SDAHOLD_450NS_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) /**< (SERCOM_I2CS_CTRLA) 300-600ns hold time Position  */
+#define SERCOM_I2CS_CTRLA_SDAHOLD_600NS       (SERCOM_I2CS_CTRLA_SDAHOLD_600NS_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) /**< (SERCOM_I2CS_CTRLA) 400-800ns hold time Position  */
+#define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos        _U_(23)                                              /**< (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout Position */
+#define SERCOM_I2CS_CTRLA_SEXTTOEN_Msk        (_U_(0x1) << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)         /**< (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout Mask */
+#define SERCOM_I2CS_CTRLA_SEXTTOEN(value)     (SERCOM_I2CS_CTRLA_SEXTTOEN_Msk & ((value) << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos))
+#define SERCOM_I2CS_CTRLA_SPEED_Pos           _U_(24)                                              /**< (SERCOM_I2CS_CTRLA) Transfer Speed Position */
+#define SERCOM_I2CS_CTRLA_SPEED_Msk           (_U_(0x3) << SERCOM_I2CS_CTRLA_SPEED_Pos)            /**< (SERCOM_I2CS_CTRLA) Transfer Speed Mask */
+#define SERCOM_I2CS_CTRLA_SPEED(value)        (SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos))
+#define   SERCOM_I2CS_CTRLA_SPEED_STANDARD_AND_FAST_MODE_Val _U_(0x0)                                             /**< (SERCOM_I2CS_CTRLA) Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz   */
+#define   SERCOM_I2CS_CTRLA_SPEED_FASTPLUS_MODE_Val _U_(0x1)                                             /**< (SERCOM_I2CS_CTRLA) Fast-mode Plus Upto 1MHz  */
+#define   SERCOM_I2CS_CTRLA_SPEED_HIGH_SPEED_MODE_Val _U_(0x2)                                             /**< (SERCOM_I2CS_CTRLA) High-speed mode Upto 3.4MHz  */
+#define SERCOM_I2CS_CTRLA_SPEED_STANDARD_AND_FAST_MODE (SERCOM_I2CS_CTRLA_SPEED_STANDARD_AND_FAST_MODE_Val << SERCOM_I2CS_CTRLA_SPEED_Pos) /**< (SERCOM_I2CS_CTRLA) Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz  Position  */
+#define SERCOM_I2CS_CTRLA_SPEED_FASTPLUS_MODE (SERCOM_I2CS_CTRLA_SPEED_FASTPLUS_MODE_Val << SERCOM_I2CS_CTRLA_SPEED_Pos) /**< (SERCOM_I2CS_CTRLA) Fast-mode Plus Upto 1MHz Position  */
+#define SERCOM_I2CS_CTRLA_SPEED_HIGH_SPEED_MODE (SERCOM_I2CS_CTRLA_SPEED_HIGH_SPEED_MODE_Val << SERCOM_I2CS_CTRLA_SPEED_Pos) /**< (SERCOM_I2CS_CTRLA) High-speed mode Upto 3.4MHz Position  */
+#define SERCOM_I2CS_CTRLA_SCLSM_Pos           _U_(27)                                              /**< (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode Position */
+#define SERCOM_I2CS_CTRLA_SCLSM_Msk           (_U_(0x1) << SERCOM_I2CS_CTRLA_SCLSM_Pos)            /**< (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode Mask */
+#define SERCOM_I2CS_CTRLA_SCLSM(value)        (SERCOM_I2CS_CTRLA_SCLSM_Msk & ((value) << SERCOM_I2CS_CTRLA_SCLSM_Pos))
+#define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos       _U_(30)                                              /**< (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable Position */
+#define SERCOM_I2CS_CTRLA_LOWTOUTEN_Msk       (_U_(0x1) << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos)        /**< (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable Mask */
+#define SERCOM_I2CS_CTRLA_LOWTOUTEN(value)    (SERCOM_I2CS_CTRLA_LOWTOUTEN_Msk & ((value) << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos))
+#define SERCOM_I2CS_CTRLA_Msk                 _U_(0x4BB1009F)                                      /**< (SERCOM_I2CS_CTRLA) Register Mask  */
+
+
+/* -------- SERCOM_SPIM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPIM Control A -------- */
+#define SERCOM_SPIM_CTRLA_RESETVALUE          _U_(0x00)                                            /**<  (SERCOM_SPIM_CTRLA) SPIM Control A  Reset Value */
+
+#define SERCOM_SPIM_CTRLA_SWRST_Pos           _U_(0)                                               /**< (SERCOM_SPIM_CTRLA) Software Reset Position */
+#define SERCOM_SPIM_CTRLA_SWRST_Msk           (_U_(0x1) << SERCOM_SPIM_CTRLA_SWRST_Pos)            /**< (SERCOM_SPIM_CTRLA) Software Reset Mask */
+#define SERCOM_SPIM_CTRLA_SWRST(value)        (SERCOM_SPIM_CTRLA_SWRST_Msk & ((value) << SERCOM_SPIM_CTRLA_SWRST_Pos))
+#define SERCOM_SPIM_CTRLA_ENABLE_Pos          _U_(1)                                               /**< (SERCOM_SPIM_CTRLA) Enable Position */
+#define SERCOM_SPIM_CTRLA_ENABLE_Msk          (_U_(0x1) << SERCOM_SPIM_CTRLA_ENABLE_Pos)           /**< (SERCOM_SPIM_CTRLA) Enable Mask */
+#define SERCOM_SPIM_CTRLA_ENABLE(value)       (SERCOM_SPIM_CTRLA_ENABLE_Msk & ((value) << SERCOM_SPIM_CTRLA_ENABLE_Pos))
+#define SERCOM_SPIM_CTRLA_MODE_Pos            _U_(2)                                               /**< (SERCOM_SPIM_CTRLA) Operating Mode Position */
+#define SERCOM_SPIM_CTRLA_MODE_Msk            (_U_(0x7) << SERCOM_SPIM_CTRLA_MODE_Pos)             /**< (SERCOM_SPIM_CTRLA) Operating Mode Mask */
+#define SERCOM_SPIM_CTRLA_MODE(value)         (SERCOM_SPIM_CTRLA_MODE_Msk & ((value) << SERCOM_SPIM_CTRLA_MODE_Pos))
+#define   SERCOM_SPIM_CTRLA_MODE_USART_EXT_CLK_Val _U_(0x0)                                             /**< (SERCOM_SPIM_CTRLA) USART with external clock  */
+#define   SERCOM_SPIM_CTRLA_MODE_USART_INT_CLK_Val _U_(0x1)                                             /**< (SERCOM_SPIM_CTRLA) USART with internal clock  */
+#define   SERCOM_SPIM_CTRLA_MODE_SPI_SLAVE_Val _U_(0x2)                                             /**< (SERCOM_SPIM_CTRLA) SPI in slave operation  */
+#define   SERCOM_SPIM_CTRLA_MODE_SPI_MASTER_Val _U_(0x3)                                             /**< (SERCOM_SPIM_CTRLA) SPI in master operation  */
+#define   SERCOM_SPIM_CTRLA_MODE_I2C_SLAVE_Val _U_(0x4)                                             /**< (SERCOM_SPIM_CTRLA) I2C slave operation  */
+#define   SERCOM_SPIM_CTRLA_MODE_I2C_MASTER_Val _U_(0x5)                                             /**< (SERCOM_SPIM_CTRLA) I2C master operation  */
+#define SERCOM_SPIM_CTRLA_MODE_USART_EXT_CLK  (SERCOM_SPIM_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_SPIM_CTRLA_MODE_Pos) /**< (SERCOM_SPIM_CTRLA) USART with external clock Position  */
+#define SERCOM_SPIM_CTRLA_MODE_USART_INT_CLK  (SERCOM_SPIM_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_SPIM_CTRLA_MODE_Pos) /**< (SERCOM_SPIM_CTRLA) USART with internal clock Position  */
+#define SERCOM_SPIM_CTRLA_MODE_SPI_SLAVE      (SERCOM_SPIM_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_SPIM_CTRLA_MODE_Pos) /**< (SERCOM_SPIM_CTRLA) SPI in slave operation Position  */
+#define SERCOM_SPIM_CTRLA_MODE_SPI_MASTER     (SERCOM_SPIM_CTRLA_MODE_SPI_MASTER_Val << SERCOM_SPIM_CTRLA_MODE_Pos) /**< (SERCOM_SPIM_CTRLA) SPI in master operation Position  */
+#define SERCOM_SPIM_CTRLA_MODE_I2C_SLAVE      (SERCOM_SPIM_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_SPIM_CTRLA_MODE_Pos) /**< (SERCOM_SPIM_CTRLA) I2C slave operation Position  */
+#define SERCOM_SPIM_CTRLA_MODE_I2C_MASTER     (SERCOM_SPIM_CTRLA_MODE_I2C_MASTER_Val << SERCOM_SPIM_CTRLA_MODE_Pos) /**< (SERCOM_SPIM_CTRLA) I2C master operation Position  */
+#define SERCOM_SPIM_CTRLA_RUNSTDBY_Pos        _U_(7)                                               /**< (SERCOM_SPIM_CTRLA) Run during Standby Position */
+#define SERCOM_SPIM_CTRLA_RUNSTDBY_Msk        (_U_(0x1) << SERCOM_SPIM_CTRLA_RUNSTDBY_Pos)         /**< (SERCOM_SPIM_CTRLA) Run during Standby Mask */
+#define SERCOM_SPIM_CTRLA_RUNSTDBY(value)     (SERCOM_SPIM_CTRLA_RUNSTDBY_Msk & ((value) << SERCOM_SPIM_CTRLA_RUNSTDBY_Pos))
+#define SERCOM_SPIM_CTRLA_IBON_Pos            _U_(8)                                               /**< (SERCOM_SPIM_CTRLA) Immediate Buffer Overflow Notification Position */
+#define SERCOM_SPIM_CTRLA_IBON_Msk            (_U_(0x1) << SERCOM_SPIM_CTRLA_IBON_Pos)             /**< (SERCOM_SPIM_CTRLA) Immediate Buffer Overflow Notification Mask */
+#define SERCOM_SPIM_CTRLA_IBON(value)         (SERCOM_SPIM_CTRLA_IBON_Msk & ((value) << SERCOM_SPIM_CTRLA_IBON_Pos))
+#define SERCOM_SPIM_CTRLA_DOPO_Pos            _U_(16)                                              /**< (SERCOM_SPIM_CTRLA) Data Out Pinout Position */
+#define SERCOM_SPIM_CTRLA_DOPO_Msk            (_U_(0x3) << SERCOM_SPIM_CTRLA_DOPO_Pos)             /**< (SERCOM_SPIM_CTRLA) Data Out Pinout Mask */
+#define SERCOM_SPIM_CTRLA_DOPO(value)         (SERCOM_SPIM_CTRLA_DOPO_Msk & ((value) << SERCOM_SPIM_CTRLA_DOPO_Pos))
+#define   SERCOM_SPIM_CTRLA_DOPO_PAD0_Val     _U_(0x0)                                             /**< (SERCOM_SPIM_CTRLA) DO on PAD[0], SCK on PAD[1] and SS on PAD[2]  */
+#define   SERCOM_SPIM_CTRLA_DOPO_PAD2_Val     _U_(0x2)                                             /**< (SERCOM_SPIM_CTRLA) DO on PAD[3], SCK on PAD[1] and SS on PAD[2]  */
+#define SERCOM_SPIM_CTRLA_DOPO_PAD0           (SERCOM_SPIM_CTRLA_DOPO_PAD0_Val << SERCOM_SPIM_CTRLA_DOPO_Pos) /**< (SERCOM_SPIM_CTRLA) DO on PAD[0], SCK on PAD[1] and SS on PAD[2] Position  */
+#define SERCOM_SPIM_CTRLA_DOPO_PAD2           (SERCOM_SPIM_CTRLA_DOPO_PAD2_Val << SERCOM_SPIM_CTRLA_DOPO_Pos) /**< (SERCOM_SPIM_CTRLA) DO on PAD[3], SCK on PAD[1] and SS on PAD[2] Position  */
+#define SERCOM_SPIM_CTRLA_DIPO_Pos            _U_(20)                                              /**< (SERCOM_SPIM_CTRLA) Data In Pinout Position */
+#define SERCOM_SPIM_CTRLA_DIPO_Msk            (_U_(0x3) << SERCOM_SPIM_CTRLA_DIPO_Pos)             /**< (SERCOM_SPIM_CTRLA) Data In Pinout Mask */
+#define SERCOM_SPIM_CTRLA_DIPO(value)         (SERCOM_SPIM_CTRLA_DIPO_Msk & ((value) << SERCOM_SPIM_CTRLA_DIPO_Pos))
+#define   SERCOM_SPIM_CTRLA_DIPO_PAD0_Val     _U_(0x0)                                             /**< (SERCOM_SPIM_CTRLA) SERCOM PAD[0] is used as data input  */
+#define   SERCOM_SPIM_CTRLA_DIPO_PAD1_Val     _U_(0x1)                                             /**< (SERCOM_SPIM_CTRLA) SERCOM PAD[1] is used as data input  */
+#define   SERCOM_SPIM_CTRLA_DIPO_PAD2_Val     _U_(0x2)                                             /**< (SERCOM_SPIM_CTRLA) SERCOM PAD[2] is used as data input  */
+#define   SERCOM_SPIM_CTRLA_DIPO_PAD3_Val     _U_(0x3)                                             /**< (SERCOM_SPIM_CTRLA) SERCOM PAD[3] is used as data input  */
+#define SERCOM_SPIM_CTRLA_DIPO_PAD0           (SERCOM_SPIM_CTRLA_DIPO_PAD0_Val << SERCOM_SPIM_CTRLA_DIPO_Pos) /**< (SERCOM_SPIM_CTRLA) SERCOM PAD[0] is used as data input Position  */
+#define SERCOM_SPIM_CTRLA_DIPO_PAD1           (SERCOM_SPIM_CTRLA_DIPO_PAD1_Val << SERCOM_SPIM_CTRLA_DIPO_Pos) /**< (SERCOM_SPIM_CTRLA) SERCOM PAD[1] is used as data input Position  */
+#define SERCOM_SPIM_CTRLA_DIPO_PAD2           (SERCOM_SPIM_CTRLA_DIPO_PAD2_Val << SERCOM_SPIM_CTRLA_DIPO_Pos) /**< (SERCOM_SPIM_CTRLA) SERCOM PAD[2] is used as data input Position  */
+#define SERCOM_SPIM_CTRLA_DIPO_PAD3           (SERCOM_SPIM_CTRLA_DIPO_PAD3_Val << SERCOM_SPIM_CTRLA_DIPO_Pos) /**< (SERCOM_SPIM_CTRLA) SERCOM PAD[3] is used as data input Position  */
+#define SERCOM_SPIM_CTRLA_FORM_Pos            _U_(24)                                              /**< (SERCOM_SPIM_CTRLA) Frame Format Position */
+#define SERCOM_SPIM_CTRLA_FORM_Msk            (_U_(0xF) << SERCOM_SPIM_CTRLA_FORM_Pos)             /**< (SERCOM_SPIM_CTRLA) Frame Format Mask */
+#define SERCOM_SPIM_CTRLA_FORM(value)         (SERCOM_SPIM_CTRLA_FORM_Msk & ((value) << SERCOM_SPIM_CTRLA_FORM_Pos))
+#define   SERCOM_SPIM_CTRLA_FORM_SPI_FRAME_Val _U_(0x0)                                             /**< (SERCOM_SPIM_CTRLA) SPI Frame  */
+#define   SERCOM_SPIM_CTRLA_FORM_SPI_FRAME_WITH_ADDR_Val _U_(0x2)                                             /**< (SERCOM_SPIM_CTRLA) SPI Frame with Addr  */
+#define SERCOM_SPIM_CTRLA_FORM_SPI_FRAME      (SERCOM_SPIM_CTRLA_FORM_SPI_FRAME_Val << SERCOM_SPIM_CTRLA_FORM_Pos) /**< (SERCOM_SPIM_CTRLA) SPI Frame Position  */
+#define SERCOM_SPIM_CTRLA_FORM_SPI_FRAME_WITH_ADDR (SERCOM_SPIM_CTRLA_FORM_SPI_FRAME_WITH_ADDR_Val << SERCOM_SPIM_CTRLA_FORM_Pos) /**< (SERCOM_SPIM_CTRLA) SPI Frame with Addr Position  */
+#define SERCOM_SPIM_CTRLA_CPHA_Pos            _U_(28)                                              /**< (SERCOM_SPIM_CTRLA) Clock Phase Position */
+#define SERCOM_SPIM_CTRLA_CPHA_Msk            (_U_(0x1) << SERCOM_SPIM_CTRLA_CPHA_Pos)             /**< (SERCOM_SPIM_CTRLA) Clock Phase Mask */
+#define SERCOM_SPIM_CTRLA_CPHA(value)         (SERCOM_SPIM_CTRLA_CPHA_Msk & ((value) << SERCOM_SPIM_CTRLA_CPHA_Pos))
+#define   SERCOM_SPIM_CTRLA_CPHA_LEADING_EDGE_Val _U_(0x0)                                             /**< (SERCOM_SPIM_CTRLA) The data is sampled on a leading SCK edge and changed on a trailing SCK edge  */
+#define   SERCOM_SPIM_CTRLA_CPHA_TRAILING_EDGE_Val _U_(0x1)                                             /**< (SERCOM_SPIM_CTRLA) The data is sampled on a trailing SCK edge and changed on a leading SCK edge  */
+#define SERCOM_SPIM_CTRLA_CPHA_LEADING_EDGE   (SERCOM_SPIM_CTRLA_CPHA_LEADING_EDGE_Val << SERCOM_SPIM_CTRLA_CPHA_Pos) /**< (SERCOM_SPIM_CTRLA) The data is sampled on a leading SCK edge and changed on a trailing SCK edge Position  */
+#define SERCOM_SPIM_CTRLA_CPHA_TRAILING_EDGE  (SERCOM_SPIM_CTRLA_CPHA_TRAILING_EDGE_Val << SERCOM_SPIM_CTRLA_CPHA_Pos) /**< (SERCOM_SPIM_CTRLA) The data is sampled on a trailing SCK edge and changed on a leading SCK edge Position  */
+#define SERCOM_SPIM_CTRLA_CPOL_Pos            _U_(29)                                              /**< (SERCOM_SPIM_CTRLA) Clock Polarity Position */
+#define SERCOM_SPIM_CTRLA_CPOL_Msk            (_U_(0x1) << SERCOM_SPIM_CTRLA_CPOL_Pos)             /**< (SERCOM_SPIM_CTRLA) Clock Polarity Mask */
+#define SERCOM_SPIM_CTRLA_CPOL(value)         (SERCOM_SPIM_CTRLA_CPOL_Msk & ((value) << SERCOM_SPIM_CTRLA_CPOL_Pos))
+#define   SERCOM_SPIM_CTRLA_CPOL_IDLE_LOW_Val _U_(0x0)                                             /**< (SERCOM_SPIM_CTRLA) SCK is low when idle  */
+#define   SERCOM_SPIM_CTRLA_CPOL_IDLE_HIGH_Val _U_(0x1)                                             /**< (SERCOM_SPIM_CTRLA) SCK is high when idle  */
+#define SERCOM_SPIM_CTRLA_CPOL_IDLE_LOW       (SERCOM_SPIM_CTRLA_CPOL_IDLE_LOW_Val << SERCOM_SPIM_CTRLA_CPOL_Pos) /**< (SERCOM_SPIM_CTRLA) SCK is low when idle Position  */
+#define SERCOM_SPIM_CTRLA_CPOL_IDLE_HIGH      (SERCOM_SPIM_CTRLA_CPOL_IDLE_HIGH_Val << SERCOM_SPIM_CTRLA_CPOL_Pos) /**< (SERCOM_SPIM_CTRLA) SCK is high when idle Position  */
+#define SERCOM_SPIM_CTRLA_DORD_Pos            _U_(30)                                              /**< (SERCOM_SPIM_CTRLA) Data Order Position */
+#define SERCOM_SPIM_CTRLA_DORD_Msk            (_U_(0x1) << SERCOM_SPIM_CTRLA_DORD_Pos)             /**< (SERCOM_SPIM_CTRLA) Data Order Mask */
+#define SERCOM_SPIM_CTRLA_DORD(value)         (SERCOM_SPIM_CTRLA_DORD_Msk & ((value) << SERCOM_SPIM_CTRLA_DORD_Pos))
+#define   SERCOM_SPIM_CTRLA_DORD_MSB_Val      _U_(0x0)                                             /**< (SERCOM_SPIM_CTRLA) MSB is transferred first  */
+#define   SERCOM_SPIM_CTRLA_DORD_LSB_Val      _U_(0x1)                                             /**< (SERCOM_SPIM_CTRLA) LSB is transferred first  */
+#define SERCOM_SPIM_CTRLA_DORD_MSB            (SERCOM_SPIM_CTRLA_DORD_MSB_Val << SERCOM_SPIM_CTRLA_DORD_Pos) /**< (SERCOM_SPIM_CTRLA) MSB is transferred first Position  */
+#define SERCOM_SPIM_CTRLA_DORD_LSB            (SERCOM_SPIM_CTRLA_DORD_LSB_Val << SERCOM_SPIM_CTRLA_DORD_Pos) /**< (SERCOM_SPIM_CTRLA) LSB is transferred first Position  */
+#define SERCOM_SPIM_CTRLA_Msk                 _U_(0x7F33019F)                                      /**< (SERCOM_SPIM_CTRLA) Register Mask  */
+
+
+/* -------- SERCOM_SPIS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPIS Control A -------- */
+#define SERCOM_SPIS_CTRLA_RESETVALUE          _U_(0x00)                                            /**<  (SERCOM_SPIS_CTRLA) SPIS Control A  Reset Value */
+
+#define SERCOM_SPIS_CTRLA_SWRST_Pos           _U_(0)                                               /**< (SERCOM_SPIS_CTRLA) Software Reset Position */
+#define SERCOM_SPIS_CTRLA_SWRST_Msk           (_U_(0x1) << SERCOM_SPIS_CTRLA_SWRST_Pos)            /**< (SERCOM_SPIS_CTRLA) Software Reset Mask */
+#define SERCOM_SPIS_CTRLA_SWRST(value)        (SERCOM_SPIS_CTRLA_SWRST_Msk & ((value) << SERCOM_SPIS_CTRLA_SWRST_Pos))
+#define SERCOM_SPIS_CTRLA_ENABLE_Pos          _U_(1)                                               /**< (SERCOM_SPIS_CTRLA) Enable Position */
+#define SERCOM_SPIS_CTRLA_ENABLE_Msk          (_U_(0x1) << SERCOM_SPIS_CTRLA_ENABLE_Pos)           /**< (SERCOM_SPIS_CTRLA) Enable Mask */
+#define SERCOM_SPIS_CTRLA_ENABLE(value)       (SERCOM_SPIS_CTRLA_ENABLE_Msk & ((value) << SERCOM_SPIS_CTRLA_ENABLE_Pos))
+#define SERCOM_SPIS_CTRLA_MODE_Pos            _U_(2)                                               /**< (SERCOM_SPIS_CTRLA) Operating Mode Position */
+#define SERCOM_SPIS_CTRLA_MODE_Msk            (_U_(0x7) << SERCOM_SPIS_CTRLA_MODE_Pos)             /**< (SERCOM_SPIS_CTRLA) Operating Mode Mask */
+#define SERCOM_SPIS_CTRLA_MODE(value)         (SERCOM_SPIS_CTRLA_MODE_Msk & ((value) << SERCOM_SPIS_CTRLA_MODE_Pos))
+#define   SERCOM_SPIS_CTRLA_MODE_USART_EXT_CLK_Val _U_(0x0)                                             /**< (SERCOM_SPIS_CTRLA) USART with external clock  */
+#define   SERCOM_SPIS_CTRLA_MODE_USART_INT_CLK_Val _U_(0x1)                                             /**< (SERCOM_SPIS_CTRLA) USART with internal clock  */
+#define   SERCOM_SPIS_CTRLA_MODE_SPI_SLAVE_Val _U_(0x2)                                             /**< (SERCOM_SPIS_CTRLA) SPI in slave operation  */
+#define   SERCOM_SPIS_CTRLA_MODE_SPI_MASTER_Val _U_(0x3)                                             /**< (SERCOM_SPIS_CTRLA) SPI in master operation  */
+#define   SERCOM_SPIS_CTRLA_MODE_I2C_SLAVE_Val _U_(0x4)                                             /**< (SERCOM_SPIS_CTRLA) I2C slave operation  */
+#define   SERCOM_SPIS_CTRLA_MODE_I2C_MASTER_Val _U_(0x5)                                             /**< (SERCOM_SPIS_CTRLA) I2C master operation  */
+#define SERCOM_SPIS_CTRLA_MODE_USART_EXT_CLK  (SERCOM_SPIS_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_SPIS_CTRLA_MODE_Pos) /**< (SERCOM_SPIS_CTRLA) USART with external clock Position  */
+#define SERCOM_SPIS_CTRLA_MODE_USART_INT_CLK  (SERCOM_SPIS_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_SPIS_CTRLA_MODE_Pos) /**< (SERCOM_SPIS_CTRLA) USART with internal clock Position  */
+#define SERCOM_SPIS_CTRLA_MODE_SPI_SLAVE      (SERCOM_SPIS_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_SPIS_CTRLA_MODE_Pos) /**< (SERCOM_SPIS_CTRLA) SPI in slave operation Position  */
+#define SERCOM_SPIS_CTRLA_MODE_SPI_MASTER     (SERCOM_SPIS_CTRLA_MODE_SPI_MASTER_Val << SERCOM_SPIS_CTRLA_MODE_Pos) /**< (SERCOM_SPIS_CTRLA) SPI in master operation Position  */
+#define SERCOM_SPIS_CTRLA_MODE_I2C_SLAVE      (SERCOM_SPIS_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_SPIS_CTRLA_MODE_Pos) /**< (SERCOM_SPIS_CTRLA) I2C slave operation Position  */
+#define SERCOM_SPIS_CTRLA_MODE_I2C_MASTER     (SERCOM_SPIS_CTRLA_MODE_I2C_MASTER_Val << SERCOM_SPIS_CTRLA_MODE_Pos) /**< (SERCOM_SPIS_CTRLA) I2C master operation Position  */
+#define SERCOM_SPIS_CTRLA_RUNSTDBY_Pos        _U_(7)                                               /**< (SERCOM_SPIS_CTRLA) Run during Standby Position */
+#define SERCOM_SPIS_CTRLA_RUNSTDBY_Msk        (_U_(0x1) << SERCOM_SPIS_CTRLA_RUNSTDBY_Pos)         /**< (SERCOM_SPIS_CTRLA) Run during Standby Mask */
+#define SERCOM_SPIS_CTRLA_RUNSTDBY(value)     (SERCOM_SPIS_CTRLA_RUNSTDBY_Msk & ((value) << SERCOM_SPIS_CTRLA_RUNSTDBY_Pos))
+#define SERCOM_SPIS_CTRLA_IBON_Pos            _U_(8)                                               /**< (SERCOM_SPIS_CTRLA) Immediate Buffer Overflow Notification Position */
+#define SERCOM_SPIS_CTRLA_IBON_Msk            (_U_(0x1) << SERCOM_SPIS_CTRLA_IBON_Pos)             /**< (SERCOM_SPIS_CTRLA) Immediate Buffer Overflow Notification Mask */
+#define SERCOM_SPIS_CTRLA_IBON(value)         (SERCOM_SPIS_CTRLA_IBON_Msk & ((value) << SERCOM_SPIS_CTRLA_IBON_Pos))
+#define SERCOM_SPIS_CTRLA_DOPO_Pos            _U_(16)                                              /**< (SERCOM_SPIS_CTRLA) Data Out Pinout Position */
+#define SERCOM_SPIS_CTRLA_DOPO_Msk            (_U_(0x3) << SERCOM_SPIS_CTRLA_DOPO_Pos)             /**< (SERCOM_SPIS_CTRLA) Data Out Pinout Mask */
+#define SERCOM_SPIS_CTRLA_DOPO(value)         (SERCOM_SPIS_CTRLA_DOPO_Msk & ((value) << SERCOM_SPIS_CTRLA_DOPO_Pos))
+#define   SERCOM_SPIS_CTRLA_DOPO_PAD0_Val     _U_(0x0)                                             /**< (SERCOM_SPIS_CTRLA) DO on PAD[0], SCK on PAD[1] and SS on PAD[2]  */
+#define   SERCOM_SPIS_CTRLA_DOPO_PAD2_Val     _U_(0x2)                                             /**< (SERCOM_SPIS_CTRLA) DO on PAD[3], SCK on PAD[1] and SS on PAD[2]  */
+#define SERCOM_SPIS_CTRLA_DOPO_PAD0           (SERCOM_SPIS_CTRLA_DOPO_PAD0_Val << SERCOM_SPIS_CTRLA_DOPO_Pos) /**< (SERCOM_SPIS_CTRLA) DO on PAD[0], SCK on PAD[1] and SS on PAD[2] Position  */
+#define SERCOM_SPIS_CTRLA_DOPO_PAD2           (SERCOM_SPIS_CTRLA_DOPO_PAD2_Val << SERCOM_SPIS_CTRLA_DOPO_Pos) /**< (SERCOM_SPIS_CTRLA) DO on PAD[3], SCK on PAD[1] and SS on PAD[2] Position  */
+#define SERCOM_SPIS_CTRLA_DIPO_Pos            _U_(20)                                              /**< (SERCOM_SPIS_CTRLA) Data In Pinout Position */
+#define SERCOM_SPIS_CTRLA_DIPO_Msk            (_U_(0x3) << SERCOM_SPIS_CTRLA_DIPO_Pos)             /**< (SERCOM_SPIS_CTRLA) Data In Pinout Mask */
+#define SERCOM_SPIS_CTRLA_DIPO(value)         (SERCOM_SPIS_CTRLA_DIPO_Msk & ((value) << SERCOM_SPIS_CTRLA_DIPO_Pos))
+#define   SERCOM_SPIS_CTRLA_DIPO_PAD0_Val     _U_(0x0)                                             /**< (SERCOM_SPIS_CTRLA) SERCOM PAD[0] is used as data input  */
+#define   SERCOM_SPIS_CTRLA_DIPO_PAD1_Val     _U_(0x1)                                             /**< (SERCOM_SPIS_CTRLA) SERCOM PAD[1] is used as data input  */
+#define   SERCOM_SPIS_CTRLA_DIPO_PAD2_Val     _U_(0x2)                                             /**< (SERCOM_SPIS_CTRLA) SERCOM PAD[2] is used as data input  */
+#define   SERCOM_SPIS_CTRLA_DIPO_PAD3_Val     _U_(0x3)                                             /**< (SERCOM_SPIS_CTRLA) SERCOM PAD[3] is used as data input  */
+#define SERCOM_SPIS_CTRLA_DIPO_PAD0           (SERCOM_SPIS_CTRLA_DIPO_PAD0_Val << SERCOM_SPIS_CTRLA_DIPO_Pos) /**< (SERCOM_SPIS_CTRLA) SERCOM PAD[0] is used as data input Position  */
+#define SERCOM_SPIS_CTRLA_DIPO_PAD1           (SERCOM_SPIS_CTRLA_DIPO_PAD1_Val << SERCOM_SPIS_CTRLA_DIPO_Pos) /**< (SERCOM_SPIS_CTRLA) SERCOM PAD[1] is used as data input Position  */
+#define SERCOM_SPIS_CTRLA_DIPO_PAD2           (SERCOM_SPIS_CTRLA_DIPO_PAD2_Val << SERCOM_SPIS_CTRLA_DIPO_Pos) /**< (SERCOM_SPIS_CTRLA) SERCOM PAD[2] is used as data input Position  */
+#define SERCOM_SPIS_CTRLA_DIPO_PAD3           (SERCOM_SPIS_CTRLA_DIPO_PAD3_Val << SERCOM_SPIS_CTRLA_DIPO_Pos) /**< (SERCOM_SPIS_CTRLA) SERCOM PAD[3] is used as data input Position  */
+#define SERCOM_SPIS_CTRLA_FORM_Pos            _U_(24)                                              /**< (SERCOM_SPIS_CTRLA) Frame Format Position */
+#define SERCOM_SPIS_CTRLA_FORM_Msk            (_U_(0xF) << SERCOM_SPIS_CTRLA_FORM_Pos)             /**< (SERCOM_SPIS_CTRLA) Frame Format Mask */
+#define SERCOM_SPIS_CTRLA_FORM(value)         (SERCOM_SPIS_CTRLA_FORM_Msk & ((value) << SERCOM_SPIS_CTRLA_FORM_Pos))
+#define   SERCOM_SPIS_CTRLA_FORM_SPI_FRAME_Val _U_(0x0)                                             /**< (SERCOM_SPIS_CTRLA) SPI Frame  */
+#define   SERCOM_SPIS_CTRLA_FORM_SPI_FRAME_WITH_ADDR_Val _U_(0x2)                                             /**< (SERCOM_SPIS_CTRLA) SPI Frame with Addr  */
+#define SERCOM_SPIS_CTRLA_FORM_SPI_FRAME      (SERCOM_SPIS_CTRLA_FORM_SPI_FRAME_Val << SERCOM_SPIS_CTRLA_FORM_Pos) /**< (SERCOM_SPIS_CTRLA) SPI Frame Position  */
+#define SERCOM_SPIS_CTRLA_FORM_SPI_FRAME_WITH_ADDR (SERCOM_SPIS_CTRLA_FORM_SPI_FRAME_WITH_ADDR_Val << SERCOM_SPIS_CTRLA_FORM_Pos) /**< (SERCOM_SPIS_CTRLA) SPI Frame with Addr Position  */
+#define SERCOM_SPIS_CTRLA_CPHA_Pos            _U_(28)                                              /**< (SERCOM_SPIS_CTRLA) Clock Phase Position */
+#define SERCOM_SPIS_CTRLA_CPHA_Msk            (_U_(0x1) << SERCOM_SPIS_CTRLA_CPHA_Pos)             /**< (SERCOM_SPIS_CTRLA) Clock Phase Mask */
+#define SERCOM_SPIS_CTRLA_CPHA(value)         (SERCOM_SPIS_CTRLA_CPHA_Msk & ((value) << SERCOM_SPIS_CTRLA_CPHA_Pos))
+#define   SERCOM_SPIS_CTRLA_CPHA_LEADING_EDGE_Val _U_(0x0)                                             /**< (SERCOM_SPIS_CTRLA) The data is sampled on a leading SCK edge and changed on a trailing SCK edge  */
+#define   SERCOM_SPIS_CTRLA_CPHA_TRAILING_EDGE_Val _U_(0x1)                                             /**< (SERCOM_SPIS_CTRLA) The data is sampled on a trailing SCK edge and changed on a leading SCK edge  */
+#define SERCOM_SPIS_CTRLA_CPHA_LEADING_EDGE   (SERCOM_SPIS_CTRLA_CPHA_LEADING_EDGE_Val << SERCOM_SPIS_CTRLA_CPHA_Pos) /**< (SERCOM_SPIS_CTRLA) The data is sampled on a leading SCK edge and changed on a trailing SCK edge Position  */
+#define SERCOM_SPIS_CTRLA_CPHA_TRAILING_EDGE  (SERCOM_SPIS_CTRLA_CPHA_TRAILING_EDGE_Val << SERCOM_SPIS_CTRLA_CPHA_Pos) /**< (SERCOM_SPIS_CTRLA) The data is sampled on a trailing SCK edge and changed on a leading SCK edge Position  */
+#define SERCOM_SPIS_CTRLA_CPOL_Pos            _U_(29)                                              /**< (SERCOM_SPIS_CTRLA) Clock Polarity Position */
+#define SERCOM_SPIS_CTRLA_CPOL_Msk            (_U_(0x1) << SERCOM_SPIS_CTRLA_CPOL_Pos)             /**< (SERCOM_SPIS_CTRLA) Clock Polarity Mask */
+#define SERCOM_SPIS_CTRLA_CPOL(value)         (SERCOM_SPIS_CTRLA_CPOL_Msk & ((value) << SERCOM_SPIS_CTRLA_CPOL_Pos))
+#define   SERCOM_SPIS_CTRLA_CPOL_IDLE_LOW_Val _U_(0x0)                                             /**< (SERCOM_SPIS_CTRLA) SCK is low when idle  */
+#define   SERCOM_SPIS_CTRLA_CPOL_IDLE_HIGH_Val _U_(0x1)                                             /**< (SERCOM_SPIS_CTRLA) SCK is high when idle  */
+#define SERCOM_SPIS_CTRLA_CPOL_IDLE_LOW       (SERCOM_SPIS_CTRLA_CPOL_IDLE_LOW_Val << SERCOM_SPIS_CTRLA_CPOL_Pos) /**< (SERCOM_SPIS_CTRLA) SCK is low when idle Position  */
+#define SERCOM_SPIS_CTRLA_CPOL_IDLE_HIGH      (SERCOM_SPIS_CTRLA_CPOL_IDLE_HIGH_Val << SERCOM_SPIS_CTRLA_CPOL_Pos) /**< (SERCOM_SPIS_CTRLA) SCK is high when idle Position  */
+#define SERCOM_SPIS_CTRLA_DORD_Pos            _U_(30)                                              /**< (SERCOM_SPIS_CTRLA) Data Order Position */
+#define SERCOM_SPIS_CTRLA_DORD_Msk            (_U_(0x1) << SERCOM_SPIS_CTRLA_DORD_Pos)             /**< (SERCOM_SPIS_CTRLA) Data Order Mask */
+#define SERCOM_SPIS_CTRLA_DORD(value)         (SERCOM_SPIS_CTRLA_DORD_Msk & ((value) << SERCOM_SPIS_CTRLA_DORD_Pos))
+#define   SERCOM_SPIS_CTRLA_DORD_MSB_Val      _U_(0x0)                                             /**< (SERCOM_SPIS_CTRLA) MSB is transferred first  */
+#define   SERCOM_SPIS_CTRLA_DORD_LSB_Val      _U_(0x1)                                             /**< (SERCOM_SPIS_CTRLA) LSB is transferred first  */
+#define SERCOM_SPIS_CTRLA_DORD_MSB            (SERCOM_SPIS_CTRLA_DORD_MSB_Val << SERCOM_SPIS_CTRLA_DORD_Pos) /**< (SERCOM_SPIS_CTRLA) MSB is transferred first Position  */
+#define SERCOM_SPIS_CTRLA_DORD_LSB            (SERCOM_SPIS_CTRLA_DORD_LSB_Val << SERCOM_SPIS_CTRLA_DORD_Pos) /**< (SERCOM_SPIS_CTRLA) LSB is transferred first Position  */
+#define SERCOM_SPIS_CTRLA_Msk                 _U_(0x7F33019F)                                      /**< (SERCOM_SPIS_CTRLA) Register Mask  */
+
+
+/* -------- SERCOM_USART_EXT_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART_EXT Control A -------- */
+#define SERCOM_USART_EXT_CTRLA_RESETVALUE     _U_(0x00)                                            /**<  (SERCOM_USART_EXT_CTRLA) USART_EXT Control A  Reset Value */
+
+#define SERCOM_USART_EXT_CTRLA_SWRST_Pos      _U_(0)                                               /**< (SERCOM_USART_EXT_CTRLA) Software Reset Position */
+#define SERCOM_USART_EXT_CTRLA_SWRST_Msk      (_U_(0x1) << SERCOM_USART_EXT_CTRLA_SWRST_Pos)       /**< (SERCOM_USART_EXT_CTRLA) Software Reset Mask */
+#define SERCOM_USART_EXT_CTRLA_SWRST(value)   (SERCOM_USART_EXT_CTRLA_SWRST_Msk & ((value) << SERCOM_USART_EXT_CTRLA_SWRST_Pos))
+#define SERCOM_USART_EXT_CTRLA_ENABLE_Pos     _U_(1)                                               /**< (SERCOM_USART_EXT_CTRLA) Enable Position */
+#define SERCOM_USART_EXT_CTRLA_ENABLE_Msk     (_U_(0x1) << SERCOM_USART_EXT_CTRLA_ENABLE_Pos)      /**< (SERCOM_USART_EXT_CTRLA) Enable Mask */
+#define SERCOM_USART_EXT_CTRLA_ENABLE(value)  (SERCOM_USART_EXT_CTRLA_ENABLE_Msk & ((value) << SERCOM_USART_EXT_CTRLA_ENABLE_Pos))
+#define SERCOM_USART_EXT_CTRLA_MODE_Pos       _U_(2)                                               /**< (SERCOM_USART_EXT_CTRLA) Operating Mode Position */
+#define SERCOM_USART_EXT_CTRLA_MODE_Msk       (_U_(0x7) << SERCOM_USART_EXT_CTRLA_MODE_Pos)        /**< (SERCOM_USART_EXT_CTRLA) Operating Mode Mask */
+#define SERCOM_USART_EXT_CTRLA_MODE(value)    (SERCOM_USART_EXT_CTRLA_MODE_Msk & ((value) << SERCOM_USART_EXT_CTRLA_MODE_Pos))
+#define   SERCOM_USART_EXT_CTRLA_MODE_USART_EXT_CLK_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLA) USART with external clock  */
+#define   SERCOM_USART_EXT_CTRLA_MODE_USART_INT_CLK_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLA) USART with internal clock  */
+#define   SERCOM_USART_EXT_CTRLA_MODE_SPI_SLAVE_Val _U_(0x2)                                             /**< (SERCOM_USART_EXT_CTRLA) SPI in slave operation  */
+#define   SERCOM_USART_EXT_CTRLA_MODE_SPI_MASTER_Val _U_(0x3)                                             /**< (SERCOM_USART_EXT_CTRLA) SPI in master operation  */
+#define   SERCOM_USART_EXT_CTRLA_MODE_I2C_SLAVE_Val _U_(0x4)                                             /**< (SERCOM_USART_EXT_CTRLA) I2C slave operation  */
+#define   SERCOM_USART_EXT_CTRLA_MODE_I2C_MASTER_Val _U_(0x5)                                             /**< (SERCOM_USART_EXT_CTRLA) I2C master operation  */
+#define SERCOM_USART_EXT_CTRLA_MODE_USART_EXT_CLK (SERCOM_USART_EXT_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_USART_EXT_CTRLA_MODE_Pos) /**< (SERCOM_USART_EXT_CTRLA) USART with external clock Position  */
+#define SERCOM_USART_EXT_CTRLA_MODE_USART_INT_CLK (SERCOM_USART_EXT_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_USART_EXT_CTRLA_MODE_Pos) /**< (SERCOM_USART_EXT_CTRLA) USART with internal clock Position  */
+#define SERCOM_USART_EXT_CTRLA_MODE_SPI_SLAVE (SERCOM_USART_EXT_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_USART_EXT_CTRLA_MODE_Pos) /**< (SERCOM_USART_EXT_CTRLA) SPI in slave operation Position  */
+#define SERCOM_USART_EXT_CTRLA_MODE_SPI_MASTER (SERCOM_USART_EXT_CTRLA_MODE_SPI_MASTER_Val << SERCOM_USART_EXT_CTRLA_MODE_Pos) /**< (SERCOM_USART_EXT_CTRLA) SPI in master operation Position  */
+#define SERCOM_USART_EXT_CTRLA_MODE_I2C_SLAVE (SERCOM_USART_EXT_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_USART_EXT_CTRLA_MODE_Pos) /**< (SERCOM_USART_EXT_CTRLA) I2C slave operation Position  */
+#define SERCOM_USART_EXT_CTRLA_MODE_I2C_MASTER (SERCOM_USART_EXT_CTRLA_MODE_I2C_MASTER_Val << SERCOM_USART_EXT_CTRLA_MODE_Pos) /**< (SERCOM_USART_EXT_CTRLA) I2C master operation Position  */
+#define SERCOM_USART_EXT_CTRLA_RUNSTDBY_Pos   _U_(7)                                               /**< (SERCOM_USART_EXT_CTRLA) Run during Standby Position */
+#define SERCOM_USART_EXT_CTRLA_RUNSTDBY_Msk   (_U_(0x1) << SERCOM_USART_EXT_CTRLA_RUNSTDBY_Pos)    /**< (SERCOM_USART_EXT_CTRLA) Run during Standby Mask */
+#define SERCOM_USART_EXT_CTRLA_RUNSTDBY(value) (SERCOM_USART_EXT_CTRLA_RUNSTDBY_Msk & ((value) << SERCOM_USART_EXT_CTRLA_RUNSTDBY_Pos))
+#define SERCOM_USART_EXT_CTRLA_IBON_Pos       _U_(8)                                               /**< (SERCOM_USART_EXT_CTRLA) Immediate Buffer Overflow Notification Position */
+#define SERCOM_USART_EXT_CTRLA_IBON_Msk       (_U_(0x1) << SERCOM_USART_EXT_CTRLA_IBON_Pos)        /**< (SERCOM_USART_EXT_CTRLA) Immediate Buffer Overflow Notification Mask */
+#define SERCOM_USART_EXT_CTRLA_IBON(value)    (SERCOM_USART_EXT_CTRLA_IBON_Msk & ((value) << SERCOM_USART_EXT_CTRLA_IBON_Pos))
+#define SERCOM_USART_EXT_CTRLA_TXINV_Pos      _U_(9)                                               /**< (SERCOM_USART_EXT_CTRLA) Transmit Data Invert Position */
+#define SERCOM_USART_EXT_CTRLA_TXINV_Msk      (_U_(0x1) << SERCOM_USART_EXT_CTRLA_TXINV_Pos)       /**< (SERCOM_USART_EXT_CTRLA) Transmit Data Invert Mask */
+#define SERCOM_USART_EXT_CTRLA_TXINV(value)   (SERCOM_USART_EXT_CTRLA_TXINV_Msk & ((value) << SERCOM_USART_EXT_CTRLA_TXINV_Pos))
+#define SERCOM_USART_EXT_CTRLA_RXINV_Pos      _U_(10)                                              /**< (SERCOM_USART_EXT_CTRLA) Receive Data Invert Position */
+#define SERCOM_USART_EXT_CTRLA_RXINV_Msk      (_U_(0x1) << SERCOM_USART_EXT_CTRLA_RXINV_Pos)       /**< (SERCOM_USART_EXT_CTRLA) Receive Data Invert Mask */
+#define SERCOM_USART_EXT_CTRLA_RXINV(value)   (SERCOM_USART_EXT_CTRLA_RXINV_Msk & ((value) << SERCOM_USART_EXT_CTRLA_RXINV_Pos))
+#define SERCOM_USART_EXT_CTRLA_SAMPR_Pos      _U_(13)                                              /**< (SERCOM_USART_EXT_CTRLA) Sample Position */
+#define SERCOM_USART_EXT_CTRLA_SAMPR_Msk      (_U_(0x7) << SERCOM_USART_EXT_CTRLA_SAMPR_Pos)       /**< (SERCOM_USART_EXT_CTRLA) Sample Mask */
+#define SERCOM_USART_EXT_CTRLA_SAMPR(value)   (SERCOM_USART_EXT_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_EXT_CTRLA_SAMPR_Pos))
+#define   SERCOM_USART_EXT_CTRLA_SAMPR_16X_ARITHMETIC_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLA) 16x over-sampling using arithmetic baudrate generation  */
+#define   SERCOM_USART_EXT_CTRLA_SAMPR_16X_FRACTIONAL_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLA) 16x over-sampling using fractional baudrate generation  */
+#define   SERCOM_USART_EXT_CTRLA_SAMPR_8X_ARITHMETIC_Val _U_(0x2)                                             /**< (SERCOM_USART_EXT_CTRLA) 8x over-sampling using arithmetic baudrate generation  */
+#define   SERCOM_USART_EXT_CTRLA_SAMPR_8X_FRACTIONAL_Val _U_(0x3)                                             /**< (SERCOM_USART_EXT_CTRLA) 8x over-sampling using fractional baudrate generation  */
+#define   SERCOM_USART_EXT_CTRLA_SAMPR_3X_ARITHMETIC_Val _U_(0x4)                                             /**< (SERCOM_USART_EXT_CTRLA) 3x over-sampling using arithmetic baudrate generation  */
+#define SERCOM_USART_EXT_CTRLA_SAMPR_16X_ARITHMETIC (SERCOM_USART_EXT_CTRLA_SAMPR_16X_ARITHMETIC_Val << SERCOM_USART_EXT_CTRLA_SAMPR_Pos) /**< (SERCOM_USART_EXT_CTRLA) 16x over-sampling using arithmetic baudrate generation Position  */
+#define SERCOM_USART_EXT_CTRLA_SAMPR_16X_FRACTIONAL (SERCOM_USART_EXT_CTRLA_SAMPR_16X_FRACTIONAL_Val << SERCOM_USART_EXT_CTRLA_SAMPR_Pos) /**< (SERCOM_USART_EXT_CTRLA) 16x over-sampling using fractional baudrate generation Position  */
+#define SERCOM_USART_EXT_CTRLA_SAMPR_8X_ARITHMETIC (SERCOM_USART_EXT_CTRLA_SAMPR_8X_ARITHMETIC_Val << SERCOM_USART_EXT_CTRLA_SAMPR_Pos) /**< (SERCOM_USART_EXT_CTRLA) 8x over-sampling using arithmetic baudrate generation Position  */
+#define SERCOM_USART_EXT_CTRLA_SAMPR_8X_FRACTIONAL (SERCOM_USART_EXT_CTRLA_SAMPR_8X_FRACTIONAL_Val << SERCOM_USART_EXT_CTRLA_SAMPR_Pos) /**< (SERCOM_USART_EXT_CTRLA) 8x over-sampling using fractional baudrate generation Position  */
+#define SERCOM_USART_EXT_CTRLA_SAMPR_3X_ARITHMETIC (SERCOM_USART_EXT_CTRLA_SAMPR_3X_ARITHMETIC_Val << SERCOM_USART_EXT_CTRLA_SAMPR_Pos) /**< (SERCOM_USART_EXT_CTRLA) 3x over-sampling using arithmetic baudrate generation Position  */
+#define SERCOM_USART_EXT_CTRLA_TXPO_Pos       _U_(16)                                              /**< (SERCOM_USART_EXT_CTRLA) Transmit Data Pinout Position */
+#define SERCOM_USART_EXT_CTRLA_TXPO_Msk       (_U_(0x3) << SERCOM_USART_EXT_CTRLA_TXPO_Pos)        /**< (SERCOM_USART_EXT_CTRLA) Transmit Data Pinout Mask */
+#define SERCOM_USART_EXT_CTRLA_TXPO(value)    (SERCOM_USART_EXT_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_EXT_CTRLA_TXPO_Pos))
+#define   SERCOM_USART_EXT_CTRLA_TXPO_PAD0_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLA) PAD[0] = TxD; PAD[1] = XCK  */
+#define   SERCOM_USART_EXT_CTRLA_TXPO_PAD2_Val _U_(0x2)                                             /**< (SERCOM_USART_EXT_CTRLA) PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS  */
+#define   SERCOM_USART_EXT_CTRLA_TXPO_PAD3_Val _U_(0x3)                                             /**< (SERCOM_USART_EXT_CTRLA) PAD[0] = TxD; PAD[1] = XCK; PAD[2] = TE  */
+#define SERCOM_USART_EXT_CTRLA_TXPO_PAD0      (SERCOM_USART_EXT_CTRLA_TXPO_PAD0_Val << SERCOM_USART_EXT_CTRLA_TXPO_Pos) /**< (SERCOM_USART_EXT_CTRLA) PAD[0] = TxD; PAD[1] = XCK Position  */
+#define SERCOM_USART_EXT_CTRLA_TXPO_PAD2      (SERCOM_USART_EXT_CTRLA_TXPO_PAD2_Val << SERCOM_USART_EXT_CTRLA_TXPO_Pos) /**< (SERCOM_USART_EXT_CTRLA) PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS Position  */
+#define SERCOM_USART_EXT_CTRLA_TXPO_PAD3      (SERCOM_USART_EXT_CTRLA_TXPO_PAD3_Val << SERCOM_USART_EXT_CTRLA_TXPO_Pos) /**< (SERCOM_USART_EXT_CTRLA) PAD[0] = TxD; PAD[1] = XCK; PAD[2] = TE Position  */
+#define SERCOM_USART_EXT_CTRLA_RXPO_Pos       _U_(20)                                              /**< (SERCOM_USART_EXT_CTRLA) Receive Data Pinout Position */
+#define SERCOM_USART_EXT_CTRLA_RXPO_Msk       (_U_(0x3) << SERCOM_USART_EXT_CTRLA_RXPO_Pos)        /**< (SERCOM_USART_EXT_CTRLA) Receive Data Pinout Mask */
+#define SERCOM_USART_EXT_CTRLA_RXPO(value)    (SERCOM_USART_EXT_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_EXT_CTRLA_RXPO_Pos))
+#define   SERCOM_USART_EXT_CTRLA_RXPO_PAD0_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLA) SERCOM PAD[0] is used for data reception  */
+#define   SERCOM_USART_EXT_CTRLA_RXPO_PAD1_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLA) SERCOM PAD[1] is used for data reception  */
+#define   SERCOM_USART_EXT_CTRLA_RXPO_PAD2_Val _U_(0x2)                                             /**< (SERCOM_USART_EXT_CTRLA) SERCOM PAD[2] is used for data reception  */
+#define   SERCOM_USART_EXT_CTRLA_RXPO_PAD3_Val _U_(0x3)                                             /**< (SERCOM_USART_EXT_CTRLA) SERCOM PAD[3] is used for data reception  */
+#define SERCOM_USART_EXT_CTRLA_RXPO_PAD0      (SERCOM_USART_EXT_CTRLA_RXPO_PAD0_Val << SERCOM_USART_EXT_CTRLA_RXPO_Pos) /**< (SERCOM_USART_EXT_CTRLA) SERCOM PAD[0] is used for data reception Position  */
+#define SERCOM_USART_EXT_CTRLA_RXPO_PAD1      (SERCOM_USART_EXT_CTRLA_RXPO_PAD1_Val << SERCOM_USART_EXT_CTRLA_RXPO_Pos) /**< (SERCOM_USART_EXT_CTRLA) SERCOM PAD[1] is used for data reception Position  */
+#define SERCOM_USART_EXT_CTRLA_RXPO_PAD2      (SERCOM_USART_EXT_CTRLA_RXPO_PAD2_Val << SERCOM_USART_EXT_CTRLA_RXPO_Pos) /**< (SERCOM_USART_EXT_CTRLA) SERCOM PAD[2] is used for data reception Position  */
+#define SERCOM_USART_EXT_CTRLA_RXPO_PAD3      (SERCOM_USART_EXT_CTRLA_RXPO_PAD3_Val << SERCOM_USART_EXT_CTRLA_RXPO_Pos) /**< (SERCOM_USART_EXT_CTRLA) SERCOM PAD[3] is used for data reception Position  */
+#define SERCOM_USART_EXT_CTRLA_SAMPA_Pos      _U_(22)                                              /**< (SERCOM_USART_EXT_CTRLA) Sample Adjustment Position */
+#define SERCOM_USART_EXT_CTRLA_SAMPA_Msk      (_U_(0x3) << SERCOM_USART_EXT_CTRLA_SAMPA_Pos)       /**< (SERCOM_USART_EXT_CTRLA) Sample Adjustment Mask */
+#define SERCOM_USART_EXT_CTRLA_SAMPA(value)   (SERCOM_USART_EXT_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_EXT_CTRLA_SAMPA_Pos))
+#define   SERCOM_USART_EXT_CTRLA_SAMPA_ADJ0_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLA) 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5  */
+#define   SERCOM_USART_EXT_CTRLA_SAMPA_ADJ1_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLA) 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6  */
+#define   SERCOM_USART_EXT_CTRLA_SAMPA_ADJ2_Val _U_(0x2)                                             /**< (SERCOM_USART_EXT_CTRLA) 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7  */
+#define   SERCOM_USART_EXT_CTRLA_SAMPA_ADJ3_Val _U_(0x3)                                             /**< (SERCOM_USART_EXT_CTRLA) 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8  */
+#define SERCOM_USART_EXT_CTRLA_SAMPA_ADJ0     (SERCOM_USART_EXT_CTRLA_SAMPA_ADJ0_Val << SERCOM_USART_EXT_CTRLA_SAMPA_Pos) /**< (SERCOM_USART_EXT_CTRLA) 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5 Position  */
+#define SERCOM_USART_EXT_CTRLA_SAMPA_ADJ1     (SERCOM_USART_EXT_CTRLA_SAMPA_ADJ1_Val << SERCOM_USART_EXT_CTRLA_SAMPA_Pos) /**< (SERCOM_USART_EXT_CTRLA) 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6 Position  */
+#define SERCOM_USART_EXT_CTRLA_SAMPA_ADJ2     (SERCOM_USART_EXT_CTRLA_SAMPA_ADJ2_Val << SERCOM_USART_EXT_CTRLA_SAMPA_Pos) /**< (SERCOM_USART_EXT_CTRLA) 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7 Position  */
+#define SERCOM_USART_EXT_CTRLA_SAMPA_ADJ3     (SERCOM_USART_EXT_CTRLA_SAMPA_ADJ3_Val << SERCOM_USART_EXT_CTRLA_SAMPA_Pos) /**< (SERCOM_USART_EXT_CTRLA) 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8 Position  */
+#define SERCOM_USART_EXT_CTRLA_FORM_Pos       _U_(24)                                              /**< (SERCOM_USART_EXT_CTRLA) Frame Format Position */
+#define SERCOM_USART_EXT_CTRLA_FORM_Msk       (_U_(0xF) << SERCOM_USART_EXT_CTRLA_FORM_Pos)        /**< (SERCOM_USART_EXT_CTRLA) Frame Format Mask */
+#define SERCOM_USART_EXT_CTRLA_FORM(value)    (SERCOM_USART_EXT_CTRLA_FORM_Msk & ((value) << SERCOM_USART_EXT_CTRLA_FORM_Pos))
+#define   SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_NO_PARITY_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLA) USART frame  */
+#define   SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_WITH_PARITY_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLA) USART frame with parity  */
+#define   SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_LIN_MASTER_MODE_Val _U_(0x2)                                             /**< (SERCOM_USART_EXT_CTRLA) LIN Master - Break and sync generation  */
+#define   SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_NO_PARITY_Val _U_(0x4)                                             /**< (SERCOM_USART_EXT_CTRLA) Auto-baud (LIN Slave) - break detection and auto-baud  */
+#define   SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_WITH_PARITY_Val _U_(0x5)                                             /**< (SERCOM_USART_EXT_CTRLA) Auto-baud - break detection and auto-baud with parity  */
+#define   SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_ISO_7816_Val _U_(0x7)                                             /**< (SERCOM_USART_EXT_CTRLA) ISO 7816  */
+#define SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_NO_PARITY (SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_NO_PARITY_Val << SERCOM_USART_EXT_CTRLA_FORM_Pos) /**< (SERCOM_USART_EXT_CTRLA) USART frame Position  */
+#define SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_WITH_PARITY (SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_WITH_PARITY_Val << SERCOM_USART_EXT_CTRLA_FORM_Pos) /**< (SERCOM_USART_EXT_CTRLA) USART frame with parity Position  */
+#define SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_LIN_MASTER_MODE (SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_LIN_MASTER_MODE_Val << SERCOM_USART_EXT_CTRLA_FORM_Pos) /**< (SERCOM_USART_EXT_CTRLA) LIN Master - Break and sync generation Position  */
+#define SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_NO_PARITY (SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_NO_PARITY_Val << SERCOM_USART_EXT_CTRLA_FORM_Pos) /**< (SERCOM_USART_EXT_CTRLA) Auto-baud (LIN Slave) - break detection and auto-baud Position  */
+#define SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_WITH_PARITY (SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_WITH_PARITY_Val << SERCOM_USART_EXT_CTRLA_FORM_Pos) /**< (SERCOM_USART_EXT_CTRLA) Auto-baud - break detection and auto-baud with parity Position  */
+#define SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_ISO_7816 (SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_ISO_7816_Val << SERCOM_USART_EXT_CTRLA_FORM_Pos) /**< (SERCOM_USART_EXT_CTRLA) ISO 7816 Position  */
+#define SERCOM_USART_EXT_CTRLA_CMODE_Pos      _U_(28)                                              /**< (SERCOM_USART_EXT_CTRLA) Communication Mode Position */
+#define SERCOM_USART_EXT_CTRLA_CMODE_Msk      (_U_(0x1) << SERCOM_USART_EXT_CTRLA_CMODE_Pos)       /**< (SERCOM_USART_EXT_CTRLA) Communication Mode Mask */
+#define SERCOM_USART_EXT_CTRLA_CMODE(value)   (SERCOM_USART_EXT_CTRLA_CMODE_Msk & ((value) << SERCOM_USART_EXT_CTRLA_CMODE_Pos))
+#define   SERCOM_USART_EXT_CTRLA_CMODE_ASYNC_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLA) Asynchronous Communication  */
+#define   SERCOM_USART_EXT_CTRLA_CMODE_SYNC_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLA) Synchronous Communication  */
+#define SERCOM_USART_EXT_CTRLA_CMODE_ASYNC    (SERCOM_USART_EXT_CTRLA_CMODE_ASYNC_Val << SERCOM_USART_EXT_CTRLA_CMODE_Pos) /**< (SERCOM_USART_EXT_CTRLA) Asynchronous Communication Position  */
+#define SERCOM_USART_EXT_CTRLA_CMODE_SYNC     (SERCOM_USART_EXT_CTRLA_CMODE_SYNC_Val << SERCOM_USART_EXT_CTRLA_CMODE_Pos) /**< (SERCOM_USART_EXT_CTRLA) Synchronous Communication Position  */
+#define SERCOM_USART_EXT_CTRLA_CPOL_Pos       _U_(29)                                              /**< (SERCOM_USART_EXT_CTRLA) Clock Polarity Position */
+#define SERCOM_USART_EXT_CTRLA_CPOL_Msk       (_U_(0x1) << SERCOM_USART_EXT_CTRLA_CPOL_Pos)        /**< (SERCOM_USART_EXT_CTRLA) Clock Polarity Mask */
+#define SERCOM_USART_EXT_CTRLA_CPOL(value)    (SERCOM_USART_EXT_CTRLA_CPOL_Msk & ((value) << SERCOM_USART_EXT_CTRLA_CPOL_Pos))
+#define   SERCOM_USART_EXT_CTRLA_CPOL_IDLE_LOW_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLA) TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge  */
+#define   SERCOM_USART_EXT_CTRLA_CPOL_IDLE_HIGH_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLA) TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge  */
+#define SERCOM_USART_EXT_CTRLA_CPOL_IDLE_LOW  (SERCOM_USART_EXT_CTRLA_CPOL_IDLE_LOW_Val << SERCOM_USART_EXT_CTRLA_CPOL_Pos) /**< (SERCOM_USART_EXT_CTRLA) TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge Position  */
+#define SERCOM_USART_EXT_CTRLA_CPOL_IDLE_HIGH (SERCOM_USART_EXT_CTRLA_CPOL_IDLE_HIGH_Val << SERCOM_USART_EXT_CTRLA_CPOL_Pos) /**< (SERCOM_USART_EXT_CTRLA) TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge Position  */
+#define SERCOM_USART_EXT_CTRLA_DORD_Pos       _U_(30)                                              /**< (SERCOM_USART_EXT_CTRLA) Data Order Position */
+#define SERCOM_USART_EXT_CTRLA_DORD_Msk       (_U_(0x1) << SERCOM_USART_EXT_CTRLA_DORD_Pos)        /**< (SERCOM_USART_EXT_CTRLA) Data Order Mask */
+#define SERCOM_USART_EXT_CTRLA_DORD(value)    (SERCOM_USART_EXT_CTRLA_DORD_Msk & ((value) << SERCOM_USART_EXT_CTRLA_DORD_Pos))
+#define   SERCOM_USART_EXT_CTRLA_DORD_MSB_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLA) MSB is transmitted first  */
+#define   SERCOM_USART_EXT_CTRLA_DORD_LSB_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLA) LSB is transmitted first  */
+#define SERCOM_USART_EXT_CTRLA_DORD_MSB       (SERCOM_USART_EXT_CTRLA_DORD_MSB_Val << SERCOM_USART_EXT_CTRLA_DORD_Pos) /**< (SERCOM_USART_EXT_CTRLA) MSB is transmitted first Position  */
+#define SERCOM_USART_EXT_CTRLA_DORD_LSB       (SERCOM_USART_EXT_CTRLA_DORD_LSB_Val << SERCOM_USART_EXT_CTRLA_DORD_Pos) /**< (SERCOM_USART_EXT_CTRLA) LSB is transmitted first Position  */
+#define SERCOM_USART_EXT_CTRLA_Msk            _U_(0x7FF3E79F)                                      /**< (SERCOM_USART_EXT_CTRLA) Register Mask  */
+
+
+/* -------- SERCOM_USART_INT_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART_INT Control A -------- */
+#define SERCOM_USART_INT_CTRLA_RESETVALUE     _U_(0x00)                                            /**<  (SERCOM_USART_INT_CTRLA) USART_INT Control A  Reset Value */
+
+#define SERCOM_USART_INT_CTRLA_SWRST_Pos      _U_(0)                                               /**< (SERCOM_USART_INT_CTRLA) Software Reset Position */
+#define SERCOM_USART_INT_CTRLA_SWRST_Msk      (_U_(0x1) << SERCOM_USART_INT_CTRLA_SWRST_Pos)       /**< (SERCOM_USART_INT_CTRLA) Software Reset Mask */
+#define SERCOM_USART_INT_CTRLA_SWRST(value)   (SERCOM_USART_INT_CTRLA_SWRST_Msk & ((value) << SERCOM_USART_INT_CTRLA_SWRST_Pos))
+#define SERCOM_USART_INT_CTRLA_ENABLE_Pos     _U_(1)                                               /**< (SERCOM_USART_INT_CTRLA) Enable Position */
+#define SERCOM_USART_INT_CTRLA_ENABLE_Msk     (_U_(0x1) << SERCOM_USART_INT_CTRLA_ENABLE_Pos)      /**< (SERCOM_USART_INT_CTRLA) Enable Mask */
+#define SERCOM_USART_INT_CTRLA_ENABLE(value)  (SERCOM_USART_INT_CTRLA_ENABLE_Msk & ((value) << SERCOM_USART_INT_CTRLA_ENABLE_Pos))
+#define SERCOM_USART_INT_CTRLA_MODE_Pos       _U_(2)                                               /**< (SERCOM_USART_INT_CTRLA) Operating Mode Position */
+#define SERCOM_USART_INT_CTRLA_MODE_Msk       (_U_(0x7) << SERCOM_USART_INT_CTRLA_MODE_Pos)        /**< (SERCOM_USART_INT_CTRLA) Operating Mode Mask */
+#define SERCOM_USART_INT_CTRLA_MODE(value)    (SERCOM_USART_INT_CTRLA_MODE_Msk & ((value) << SERCOM_USART_INT_CTRLA_MODE_Pos))
+#define   SERCOM_USART_INT_CTRLA_MODE_USART_EXT_CLK_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLA) USART with external clock  */
+#define   SERCOM_USART_INT_CTRLA_MODE_USART_INT_CLK_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLA) USART with internal clock  */
+#define   SERCOM_USART_INT_CTRLA_MODE_SPI_SLAVE_Val _U_(0x2)                                             /**< (SERCOM_USART_INT_CTRLA) SPI in slave operation  */
+#define   SERCOM_USART_INT_CTRLA_MODE_SPI_MASTER_Val _U_(0x3)                                             /**< (SERCOM_USART_INT_CTRLA) SPI in master operation  */
+#define   SERCOM_USART_INT_CTRLA_MODE_I2C_SLAVE_Val _U_(0x4)                                             /**< (SERCOM_USART_INT_CTRLA) I2C slave operation  */
+#define   SERCOM_USART_INT_CTRLA_MODE_I2C_MASTER_Val _U_(0x5)                                             /**< (SERCOM_USART_INT_CTRLA) I2C master operation  */
+#define SERCOM_USART_INT_CTRLA_MODE_USART_EXT_CLK (SERCOM_USART_INT_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_USART_INT_CTRLA_MODE_Pos) /**< (SERCOM_USART_INT_CTRLA) USART with external clock Position  */
+#define SERCOM_USART_INT_CTRLA_MODE_USART_INT_CLK (SERCOM_USART_INT_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_USART_INT_CTRLA_MODE_Pos) /**< (SERCOM_USART_INT_CTRLA) USART with internal clock Position  */
+#define SERCOM_USART_INT_CTRLA_MODE_SPI_SLAVE (SERCOM_USART_INT_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_USART_INT_CTRLA_MODE_Pos) /**< (SERCOM_USART_INT_CTRLA) SPI in slave operation Position  */
+#define SERCOM_USART_INT_CTRLA_MODE_SPI_MASTER (SERCOM_USART_INT_CTRLA_MODE_SPI_MASTER_Val << SERCOM_USART_INT_CTRLA_MODE_Pos) /**< (SERCOM_USART_INT_CTRLA) SPI in master operation Position  */
+#define SERCOM_USART_INT_CTRLA_MODE_I2C_SLAVE (SERCOM_USART_INT_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_USART_INT_CTRLA_MODE_Pos) /**< (SERCOM_USART_INT_CTRLA) I2C slave operation Position  */
+#define SERCOM_USART_INT_CTRLA_MODE_I2C_MASTER (SERCOM_USART_INT_CTRLA_MODE_I2C_MASTER_Val << SERCOM_USART_INT_CTRLA_MODE_Pos) /**< (SERCOM_USART_INT_CTRLA) I2C master operation Position  */
+#define SERCOM_USART_INT_CTRLA_RUNSTDBY_Pos   _U_(7)                                               /**< (SERCOM_USART_INT_CTRLA) Run during Standby Position */
+#define SERCOM_USART_INT_CTRLA_RUNSTDBY_Msk   (_U_(0x1) << SERCOM_USART_INT_CTRLA_RUNSTDBY_Pos)    /**< (SERCOM_USART_INT_CTRLA) Run during Standby Mask */
+#define SERCOM_USART_INT_CTRLA_RUNSTDBY(value) (SERCOM_USART_INT_CTRLA_RUNSTDBY_Msk & ((value) << SERCOM_USART_INT_CTRLA_RUNSTDBY_Pos))
+#define SERCOM_USART_INT_CTRLA_IBON_Pos       _U_(8)                                               /**< (SERCOM_USART_INT_CTRLA) Immediate Buffer Overflow Notification Position */
+#define SERCOM_USART_INT_CTRLA_IBON_Msk       (_U_(0x1) << SERCOM_USART_INT_CTRLA_IBON_Pos)        /**< (SERCOM_USART_INT_CTRLA) Immediate Buffer Overflow Notification Mask */
+#define SERCOM_USART_INT_CTRLA_IBON(value)    (SERCOM_USART_INT_CTRLA_IBON_Msk & ((value) << SERCOM_USART_INT_CTRLA_IBON_Pos))
+#define SERCOM_USART_INT_CTRLA_TXINV_Pos      _U_(9)                                               /**< (SERCOM_USART_INT_CTRLA) Transmit Data Invert Position */
+#define SERCOM_USART_INT_CTRLA_TXINV_Msk      (_U_(0x1) << SERCOM_USART_INT_CTRLA_TXINV_Pos)       /**< (SERCOM_USART_INT_CTRLA) Transmit Data Invert Mask */
+#define SERCOM_USART_INT_CTRLA_TXINV(value)   (SERCOM_USART_INT_CTRLA_TXINV_Msk & ((value) << SERCOM_USART_INT_CTRLA_TXINV_Pos))
+#define SERCOM_USART_INT_CTRLA_RXINV_Pos      _U_(10)                                              /**< (SERCOM_USART_INT_CTRLA) Receive Data Invert Position */
+#define SERCOM_USART_INT_CTRLA_RXINV_Msk      (_U_(0x1) << SERCOM_USART_INT_CTRLA_RXINV_Pos)       /**< (SERCOM_USART_INT_CTRLA) Receive Data Invert Mask */
+#define SERCOM_USART_INT_CTRLA_RXINV(value)   (SERCOM_USART_INT_CTRLA_RXINV_Msk & ((value) << SERCOM_USART_INT_CTRLA_RXINV_Pos))
+#define SERCOM_USART_INT_CTRLA_SAMPR_Pos      _U_(13)                                              /**< (SERCOM_USART_INT_CTRLA) Sample Position */
+#define SERCOM_USART_INT_CTRLA_SAMPR_Msk      (_U_(0x7) << SERCOM_USART_INT_CTRLA_SAMPR_Pos)       /**< (SERCOM_USART_INT_CTRLA) Sample Mask */
+#define SERCOM_USART_INT_CTRLA_SAMPR(value)   (SERCOM_USART_INT_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_INT_CTRLA_SAMPR_Pos))
+#define   SERCOM_USART_INT_CTRLA_SAMPR_16X_ARITHMETIC_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLA) 16x over-sampling using arithmetic baudrate generation  */
+#define   SERCOM_USART_INT_CTRLA_SAMPR_16X_FRACTIONAL_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLA) 16x over-sampling using fractional baudrate generation  */
+#define   SERCOM_USART_INT_CTRLA_SAMPR_8X_ARITHMETIC_Val _U_(0x2)                                             /**< (SERCOM_USART_INT_CTRLA) 8x over-sampling using arithmetic baudrate generation  */
+#define   SERCOM_USART_INT_CTRLA_SAMPR_8X_FRACTIONAL_Val _U_(0x3)                                             /**< (SERCOM_USART_INT_CTRLA) 8x over-sampling using fractional baudrate generation  */
+#define   SERCOM_USART_INT_CTRLA_SAMPR_3X_ARITHMETIC_Val _U_(0x4)                                             /**< (SERCOM_USART_INT_CTRLA) 3x over-sampling using arithmetic baudrate generation  */
+#define SERCOM_USART_INT_CTRLA_SAMPR_16X_ARITHMETIC (SERCOM_USART_INT_CTRLA_SAMPR_16X_ARITHMETIC_Val << SERCOM_USART_INT_CTRLA_SAMPR_Pos) /**< (SERCOM_USART_INT_CTRLA) 16x over-sampling using arithmetic baudrate generation Position  */
+#define SERCOM_USART_INT_CTRLA_SAMPR_16X_FRACTIONAL (SERCOM_USART_INT_CTRLA_SAMPR_16X_FRACTIONAL_Val << SERCOM_USART_INT_CTRLA_SAMPR_Pos) /**< (SERCOM_USART_INT_CTRLA) 16x over-sampling using fractional baudrate generation Position  */
+#define SERCOM_USART_INT_CTRLA_SAMPR_8X_ARITHMETIC (SERCOM_USART_INT_CTRLA_SAMPR_8X_ARITHMETIC_Val << SERCOM_USART_INT_CTRLA_SAMPR_Pos) /**< (SERCOM_USART_INT_CTRLA) 8x over-sampling using arithmetic baudrate generation Position  */
+#define SERCOM_USART_INT_CTRLA_SAMPR_8X_FRACTIONAL (SERCOM_USART_INT_CTRLA_SAMPR_8X_FRACTIONAL_Val << SERCOM_USART_INT_CTRLA_SAMPR_Pos) /**< (SERCOM_USART_INT_CTRLA) 8x over-sampling using fractional baudrate generation Position  */
+#define SERCOM_USART_INT_CTRLA_SAMPR_3X_ARITHMETIC (SERCOM_USART_INT_CTRLA_SAMPR_3X_ARITHMETIC_Val << SERCOM_USART_INT_CTRLA_SAMPR_Pos) /**< (SERCOM_USART_INT_CTRLA) 3x over-sampling using arithmetic baudrate generation Position  */
+#define SERCOM_USART_INT_CTRLA_TXPO_Pos       _U_(16)                                              /**< (SERCOM_USART_INT_CTRLA) Transmit Data Pinout Position */
+#define SERCOM_USART_INT_CTRLA_TXPO_Msk       (_U_(0x3) << SERCOM_USART_INT_CTRLA_TXPO_Pos)        /**< (SERCOM_USART_INT_CTRLA) Transmit Data Pinout Mask */
+#define SERCOM_USART_INT_CTRLA_TXPO(value)    (SERCOM_USART_INT_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_INT_CTRLA_TXPO_Pos))
+#define   SERCOM_USART_INT_CTRLA_TXPO_PAD0_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLA) PAD[0] = TxD; PAD[1] = XCK  */
+#define   SERCOM_USART_INT_CTRLA_TXPO_PAD2_Val _U_(0x2)                                             /**< (SERCOM_USART_INT_CTRLA) PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS  */
+#define   SERCOM_USART_INT_CTRLA_TXPO_PAD3_Val _U_(0x3)                                             /**< (SERCOM_USART_INT_CTRLA) PAD[0] = TxD; PAD[1] = XCK; PAD[2] = TE  */
+#define SERCOM_USART_INT_CTRLA_TXPO_PAD0      (SERCOM_USART_INT_CTRLA_TXPO_PAD0_Val << SERCOM_USART_INT_CTRLA_TXPO_Pos) /**< (SERCOM_USART_INT_CTRLA) PAD[0] = TxD; PAD[1] = XCK Position  */
+#define SERCOM_USART_INT_CTRLA_TXPO_PAD2      (SERCOM_USART_INT_CTRLA_TXPO_PAD2_Val << SERCOM_USART_INT_CTRLA_TXPO_Pos) /**< (SERCOM_USART_INT_CTRLA) PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS Position  */
+#define SERCOM_USART_INT_CTRLA_TXPO_PAD3      (SERCOM_USART_INT_CTRLA_TXPO_PAD3_Val << SERCOM_USART_INT_CTRLA_TXPO_Pos) /**< (SERCOM_USART_INT_CTRLA) PAD[0] = TxD; PAD[1] = XCK; PAD[2] = TE Position  */
+#define SERCOM_USART_INT_CTRLA_RXPO_Pos       _U_(20)                                              /**< (SERCOM_USART_INT_CTRLA) Receive Data Pinout Position */
+#define SERCOM_USART_INT_CTRLA_RXPO_Msk       (_U_(0x3) << SERCOM_USART_INT_CTRLA_RXPO_Pos)        /**< (SERCOM_USART_INT_CTRLA) Receive Data Pinout Mask */
+#define SERCOM_USART_INT_CTRLA_RXPO(value)    (SERCOM_USART_INT_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_INT_CTRLA_RXPO_Pos))
+#define   SERCOM_USART_INT_CTRLA_RXPO_PAD0_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLA) SERCOM PAD[0] is used for data reception  */
+#define   SERCOM_USART_INT_CTRLA_RXPO_PAD1_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLA) SERCOM PAD[1] is used for data reception  */
+#define   SERCOM_USART_INT_CTRLA_RXPO_PAD2_Val _U_(0x2)                                             /**< (SERCOM_USART_INT_CTRLA) SERCOM PAD[2] is used for data reception  */
+#define   SERCOM_USART_INT_CTRLA_RXPO_PAD3_Val _U_(0x3)                                             /**< (SERCOM_USART_INT_CTRLA) SERCOM PAD[3] is used for data reception  */
+#define SERCOM_USART_INT_CTRLA_RXPO_PAD0      (SERCOM_USART_INT_CTRLA_RXPO_PAD0_Val << SERCOM_USART_INT_CTRLA_RXPO_Pos) /**< (SERCOM_USART_INT_CTRLA) SERCOM PAD[0] is used for data reception Position  */
+#define SERCOM_USART_INT_CTRLA_RXPO_PAD1      (SERCOM_USART_INT_CTRLA_RXPO_PAD1_Val << SERCOM_USART_INT_CTRLA_RXPO_Pos) /**< (SERCOM_USART_INT_CTRLA) SERCOM PAD[1] is used for data reception Position  */
+#define SERCOM_USART_INT_CTRLA_RXPO_PAD2      (SERCOM_USART_INT_CTRLA_RXPO_PAD2_Val << SERCOM_USART_INT_CTRLA_RXPO_Pos) /**< (SERCOM_USART_INT_CTRLA) SERCOM PAD[2] is used for data reception Position  */
+#define SERCOM_USART_INT_CTRLA_RXPO_PAD3      (SERCOM_USART_INT_CTRLA_RXPO_PAD3_Val << SERCOM_USART_INT_CTRLA_RXPO_Pos) /**< (SERCOM_USART_INT_CTRLA) SERCOM PAD[3] is used for data reception Position  */
+#define SERCOM_USART_INT_CTRLA_SAMPA_Pos      _U_(22)                                              /**< (SERCOM_USART_INT_CTRLA) Sample Adjustment Position */
+#define SERCOM_USART_INT_CTRLA_SAMPA_Msk      (_U_(0x3) << SERCOM_USART_INT_CTRLA_SAMPA_Pos)       /**< (SERCOM_USART_INT_CTRLA) Sample Adjustment Mask */
+#define SERCOM_USART_INT_CTRLA_SAMPA(value)   (SERCOM_USART_INT_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_INT_CTRLA_SAMPA_Pos))
+#define   SERCOM_USART_INT_CTRLA_SAMPA_ADJ0_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLA) 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5  */
+#define   SERCOM_USART_INT_CTRLA_SAMPA_ADJ1_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLA) 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6  */
+#define   SERCOM_USART_INT_CTRLA_SAMPA_ADJ2_Val _U_(0x2)                                             /**< (SERCOM_USART_INT_CTRLA) 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7  */
+#define   SERCOM_USART_INT_CTRLA_SAMPA_ADJ3_Val _U_(0x3)                                             /**< (SERCOM_USART_INT_CTRLA) 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8  */
+#define SERCOM_USART_INT_CTRLA_SAMPA_ADJ0     (SERCOM_USART_INT_CTRLA_SAMPA_ADJ0_Val << SERCOM_USART_INT_CTRLA_SAMPA_Pos) /**< (SERCOM_USART_INT_CTRLA) 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5 Position  */
+#define SERCOM_USART_INT_CTRLA_SAMPA_ADJ1     (SERCOM_USART_INT_CTRLA_SAMPA_ADJ1_Val << SERCOM_USART_INT_CTRLA_SAMPA_Pos) /**< (SERCOM_USART_INT_CTRLA) 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6 Position  */
+#define SERCOM_USART_INT_CTRLA_SAMPA_ADJ2     (SERCOM_USART_INT_CTRLA_SAMPA_ADJ2_Val << SERCOM_USART_INT_CTRLA_SAMPA_Pos) /**< (SERCOM_USART_INT_CTRLA) 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7 Position  */
+#define SERCOM_USART_INT_CTRLA_SAMPA_ADJ3     (SERCOM_USART_INT_CTRLA_SAMPA_ADJ3_Val << SERCOM_USART_INT_CTRLA_SAMPA_Pos) /**< (SERCOM_USART_INT_CTRLA) 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8 Position  */
+#define SERCOM_USART_INT_CTRLA_FORM_Pos       _U_(24)                                              /**< (SERCOM_USART_INT_CTRLA) Frame Format Position */
+#define SERCOM_USART_INT_CTRLA_FORM_Msk       (_U_(0xF) << SERCOM_USART_INT_CTRLA_FORM_Pos)        /**< (SERCOM_USART_INT_CTRLA) Frame Format Mask */
+#define SERCOM_USART_INT_CTRLA_FORM(value)    (SERCOM_USART_INT_CTRLA_FORM_Msk & ((value) << SERCOM_USART_INT_CTRLA_FORM_Pos))
+#define   SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_NO_PARITY_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLA) USART frame  */
+#define   SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_WITH_PARITY_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLA) USART frame with parity  */
+#define   SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_LIN_MASTER_MODE_Val _U_(0x2)                                             /**< (SERCOM_USART_INT_CTRLA) LIN Master - Break and sync generation  */
+#define   SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_NO_PARITY_Val _U_(0x4)                                             /**< (SERCOM_USART_INT_CTRLA) Auto-baud (LIN Slave) - break detection and auto-baud  */
+#define   SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_WITH_PARITY_Val _U_(0x5)                                             /**< (SERCOM_USART_INT_CTRLA) Auto-baud - break detection and auto-baud with parity  */
+#define   SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_ISO_7816_Val _U_(0x7)                                             /**< (SERCOM_USART_INT_CTRLA) ISO 7816  */
+#define SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_NO_PARITY (SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_NO_PARITY_Val << SERCOM_USART_INT_CTRLA_FORM_Pos) /**< (SERCOM_USART_INT_CTRLA) USART frame Position  */
+#define SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_WITH_PARITY (SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_WITH_PARITY_Val << SERCOM_USART_INT_CTRLA_FORM_Pos) /**< (SERCOM_USART_INT_CTRLA) USART frame with parity Position  */
+#define SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_LIN_MASTER_MODE (SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_LIN_MASTER_MODE_Val << SERCOM_USART_INT_CTRLA_FORM_Pos) /**< (SERCOM_USART_INT_CTRLA) LIN Master - Break and sync generation Position  */
+#define SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_NO_PARITY (SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_NO_PARITY_Val << SERCOM_USART_INT_CTRLA_FORM_Pos) /**< (SERCOM_USART_INT_CTRLA) Auto-baud (LIN Slave) - break detection and auto-baud Position  */
+#define SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_WITH_PARITY (SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_WITH_PARITY_Val << SERCOM_USART_INT_CTRLA_FORM_Pos) /**< (SERCOM_USART_INT_CTRLA) Auto-baud - break detection and auto-baud with parity Position  */
+#define SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_ISO_7816 (SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_ISO_7816_Val << SERCOM_USART_INT_CTRLA_FORM_Pos) /**< (SERCOM_USART_INT_CTRLA) ISO 7816 Position  */
+#define SERCOM_USART_INT_CTRLA_CMODE_Pos      _U_(28)                                              /**< (SERCOM_USART_INT_CTRLA) Communication Mode Position */
+#define SERCOM_USART_INT_CTRLA_CMODE_Msk      (_U_(0x1) << SERCOM_USART_INT_CTRLA_CMODE_Pos)       /**< (SERCOM_USART_INT_CTRLA) Communication Mode Mask */
+#define SERCOM_USART_INT_CTRLA_CMODE(value)   (SERCOM_USART_INT_CTRLA_CMODE_Msk & ((value) << SERCOM_USART_INT_CTRLA_CMODE_Pos))
+#define   SERCOM_USART_INT_CTRLA_CMODE_ASYNC_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLA) Asynchronous Communication  */
+#define   SERCOM_USART_INT_CTRLA_CMODE_SYNC_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLA) Synchronous Communication  */
+#define SERCOM_USART_INT_CTRLA_CMODE_ASYNC    (SERCOM_USART_INT_CTRLA_CMODE_ASYNC_Val << SERCOM_USART_INT_CTRLA_CMODE_Pos) /**< (SERCOM_USART_INT_CTRLA) Asynchronous Communication Position  */
+#define SERCOM_USART_INT_CTRLA_CMODE_SYNC     (SERCOM_USART_INT_CTRLA_CMODE_SYNC_Val << SERCOM_USART_INT_CTRLA_CMODE_Pos) /**< (SERCOM_USART_INT_CTRLA) Synchronous Communication Position  */
+#define SERCOM_USART_INT_CTRLA_CPOL_Pos       _U_(29)                                              /**< (SERCOM_USART_INT_CTRLA) Clock Polarity Position */
+#define SERCOM_USART_INT_CTRLA_CPOL_Msk       (_U_(0x1) << SERCOM_USART_INT_CTRLA_CPOL_Pos)        /**< (SERCOM_USART_INT_CTRLA) Clock Polarity Mask */
+#define SERCOM_USART_INT_CTRLA_CPOL(value)    (SERCOM_USART_INT_CTRLA_CPOL_Msk & ((value) << SERCOM_USART_INT_CTRLA_CPOL_Pos))
+#define   SERCOM_USART_INT_CTRLA_CPOL_IDLE_LOW_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLA) TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge  */
+#define   SERCOM_USART_INT_CTRLA_CPOL_IDLE_HIGH_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLA) TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge  */
+#define SERCOM_USART_INT_CTRLA_CPOL_IDLE_LOW  (SERCOM_USART_INT_CTRLA_CPOL_IDLE_LOW_Val << SERCOM_USART_INT_CTRLA_CPOL_Pos) /**< (SERCOM_USART_INT_CTRLA) TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge Position  */
+#define SERCOM_USART_INT_CTRLA_CPOL_IDLE_HIGH (SERCOM_USART_INT_CTRLA_CPOL_IDLE_HIGH_Val << SERCOM_USART_INT_CTRLA_CPOL_Pos) /**< (SERCOM_USART_INT_CTRLA) TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge Position  */
+#define SERCOM_USART_INT_CTRLA_DORD_Pos       _U_(30)                                              /**< (SERCOM_USART_INT_CTRLA) Data Order Position */
+#define SERCOM_USART_INT_CTRLA_DORD_Msk       (_U_(0x1) << SERCOM_USART_INT_CTRLA_DORD_Pos)        /**< (SERCOM_USART_INT_CTRLA) Data Order Mask */
+#define SERCOM_USART_INT_CTRLA_DORD(value)    (SERCOM_USART_INT_CTRLA_DORD_Msk & ((value) << SERCOM_USART_INT_CTRLA_DORD_Pos))
+#define   SERCOM_USART_INT_CTRLA_DORD_MSB_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLA) MSB is transmitted first  */
+#define   SERCOM_USART_INT_CTRLA_DORD_LSB_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLA) LSB is transmitted first  */
+#define SERCOM_USART_INT_CTRLA_DORD_MSB       (SERCOM_USART_INT_CTRLA_DORD_MSB_Val << SERCOM_USART_INT_CTRLA_DORD_Pos) /**< (SERCOM_USART_INT_CTRLA) MSB is transmitted first Position  */
+#define SERCOM_USART_INT_CTRLA_DORD_LSB       (SERCOM_USART_INT_CTRLA_DORD_LSB_Val << SERCOM_USART_INT_CTRLA_DORD_Pos) /**< (SERCOM_USART_INT_CTRLA) LSB is transmitted first Position  */
+#define SERCOM_USART_INT_CTRLA_Msk            _U_(0x7FF3E79F)                                      /**< (SERCOM_USART_INT_CTRLA) Register Mask  */
+
+
+/* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM Control B -------- */
+#define SERCOM_I2CM_CTRLB_RESETVALUE          _U_(0x00)                                            /**<  (SERCOM_I2CM_CTRLB) I2CM Control B  Reset Value */
+
+#define SERCOM_I2CM_CTRLB_SMEN_Pos            _U_(8)                                               /**< (SERCOM_I2CM_CTRLB) Smart Mode Enable Position */
+#define SERCOM_I2CM_CTRLB_SMEN_Msk            (_U_(0x1) << SERCOM_I2CM_CTRLB_SMEN_Pos)             /**< (SERCOM_I2CM_CTRLB) Smart Mode Enable Mask */
+#define SERCOM_I2CM_CTRLB_SMEN(value)         (SERCOM_I2CM_CTRLB_SMEN_Msk & ((value) << SERCOM_I2CM_CTRLB_SMEN_Pos))
+#define SERCOM_I2CM_CTRLB_QCEN_Pos            _U_(9)                                               /**< (SERCOM_I2CM_CTRLB) Quick Command Enable Position */
+#define SERCOM_I2CM_CTRLB_QCEN_Msk            (_U_(0x1) << SERCOM_I2CM_CTRLB_QCEN_Pos)             /**< (SERCOM_I2CM_CTRLB) Quick Command Enable Mask */
+#define SERCOM_I2CM_CTRLB_QCEN(value)         (SERCOM_I2CM_CTRLB_QCEN_Msk & ((value) << SERCOM_I2CM_CTRLB_QCEN_Pos))
+#define SERCOM_I2CM_CTRLB_CMD_Pos             _U_(16)                                              /**< (SERCOM_I2CM_CTRLB) Command Position */
+#define SERCOM_I2CM_CTRLB_CMD_Msk             (_U_(0x3) << SERCOM_I2CM_CTRLB_CMD_Pos)              /**< (SERCOM_I2CM_CTRLB) Command Mask */
+#define SERCOM_I2CM_CTRLB_CMD(value)          (SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos))
+#define SERCOM_I2CM_CTRLB_ACKACT_Pos          _U_(18)                                              /**< (SERCOM_I2CM_CTRLB) Acknowledge Action Position */
+#define SERCOM_I2CM_CTRLB_ACKACT_Msk          (_U_(0x1) << SERCOM_I2CM_CTRLB_ACKACT_Pos)           /**< (SERCOM_I2CM_CTRLB) Acknowledge Action Mask */
+#define SERCOM_I2CM_CTRLB_ACKACT(value)       (SERCOM_I2CM_CTRLB_ACKACT_Msk & ((value) << SERCOM_I2CM_CTRLB_ACKACT_Pos))
+#define SERCOM_I2CM_CTRLB_Msk                 _U_(0x00070300)                                      /**< (SERCOM_I2CM_CTRLB) Register Mask  */
+
+
+/* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS Control B -------- */
+#define SERCOM_I2CS_CTRLB_RESETVALUE          _U_(0x00)                                            /**<  (SERCOM_I2CS_CTRLB) I2CS Control B  Reset Value */
+
+#define SERCOM_I2CS_CTRLB_SMEN_Pos            _U_(8)                                               /**< (SERCOM_I2CS_CTRLB) Smart Mode Enable Position */
+#define SERCOM_I2CS_CTRLB_SMEN_Msk            (_U_(0x1) << SERCOM_I2CS_CTRLB_SMEN_Pos)             /**< (SERCOM_I2CS_CTRLB) Smart Mode Enable Mask */
+#define SERCOM_I2CS_CTRLB_SMEN(value)         (SERCOM_I2CS_CTRLB_SMEN_Msk & ((value) << SERCOM_I2CS_CTRLB_SMEN_Pos))
+#define SERCOM_I2CS_CTRLB_GCMD_Pos            _U_(9)                                               /**< (SERCOM_I2CS_CTRLB) PMBus Group Command Position */
+#define SERCOM_I2CS_CTRLB_GCMD_Msk            (_U_(0x1) << SERCOM_I2CS_CTRLB_GCMD_Pos)             /**< (SERCOM_I2CS_CTRLB) PMBus Group Command Mask */
+#define SERCOM_I2CS_CTRLB_GCMD(value)         (SERCOM_I2CS_CTRLB_GCMD_Msk & ((value) << SERCOM_I2CS_CTRLB_GCMD_Pos))
+#define SERCOM_I2CS_CTRLB_AACKEN_Pos          _U_(10)                                              /**< (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge Position */
+#define SERCOM_I2CS_CTRLB_AACKEN_Msk          (_U_(0x1) << SERCOM_I2CS_CTRLB_AACKEN_Pos)           /**< (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge Mask */
+#define SERCOM_I2CS_CTRLB_AACKEN(value)       (SERCOM_I2CS_CTRLB_AACKEN_Msk & ((value) << SERCOM_I2CS_CTRLB_AACKEN_Pos))
+#define SERCOM_I2CS_CTRLB_AMODE_Pos           _U_(14)                                              /**< (SERCOM_I2CS_CTRLB) Address Mode Position */
+#define SERCOM_I2CS_CTRLB_AMODE_Msk           (_U_(0x3) << SERCOM_I2CS_CTRLB_AMODE_Pos)            /**< (SERCOM_I2CS_CTRLB) Address Mode Mask */
+#define SERCOM_I2CS_CTRLB_AMODE(value)        (SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos))
+#define SERCOM_I2CS_CTRLB_CMD_Pos             _U_(16)                                              /**< (SERCOM_I2CS_CTRLB) Command Position */
+#define SERCOM_I2CS_CTRLB_CMD_Msk             (_U_(0x3) << SERCOM_I2CS_CTRLB_CMD_Pos)              /**< (SERCOM_I2CS_CTRLB) Command Mask */
+#define SERCOM_I2CS_CTRLB_CMD(value)          (SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos))
+#define SERCOM_I2CS_CTRLB_ACKACT_Pos          _U_(18)                                              /**< (SERCOM_I2CS_CTRLB) Acknowledge Action Position */
+#define SERCOM_I2CS_CTRLB_ACKACT_Msk          (_U_(0x1) << SERCOM_I2CS_CTRLB_ACKACT_Pos)           /**< (SERCOM_I2CS_CTRLB) Acknowledge Action Mask */
+#define SERCOM_I2CS_CTRLB_ACKACT(value)       (SERCOM_I2CS_CTRLB_ACKACT_Msk & ((value) << SERCOM_I2CS_CTRLB_ACKACT_Pos))
+#define SERCOM_I2CS_CTRLB_Msk                 _U_(0x0007C700)                                      /**< (SERCOM_I2CS_CTRLB) Register Mask  */
+
+
+/* -------- SERCOM_SPIM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPIM Control B -------- */
+#define SERCOM_SPIM_CTRLB_RESETVALUE          _U_(0x00)                                            /**<  (SERCOM_SPIM_CTRLB) SPIM Control B  Reset Value */
+
+#define SERCOM_SPIM_CTRLB_CHSIZE_Pos          _U_(0)                                               /**< (SERCOM_SPIM_CTRLB) Character Size Position */
+#define SERCOM_SPIM_CTRLB_CHSIZE_Msk          (_U_(0x7) << SERCOM_SPIM_CTRLB_CHSIZE_Pos)           /**< (SERCOM_SPIM_CTRLB) Character Size Mask */
+#define SERCOM_SPIM_CTRLB_CHSIZE(value)       (SERCOM_SPIM_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPIM_CTRLB_CHSIZE_Pos))
+#define   SERCOM_SPIM_CTRLB_CHSIZE_8_BIT_Val  _U_(0x0)                                             /**< (SERCOM_SPIM_CTRLB) 8 bits  */
+#define   SERCOM_SPIM_CTRLB_CHSIZE_9_BIT_Val  _U_(0x1)                                             /**< (SERCOM_SPIM_CTRLB) 9 bits  */
+#define SERCOM_SPIM_CTRLB_CHSIZE_8_BIT        (SERCOM_SPIM_CTRLB_CHSIZE_8_BIT_Val << SERCOM_SPIM_CTRLB_CHSIZE_Pos) /**< (SERCOM_SPIM_CTRLB) 8 bits Position  */
+#define SERCOM_SPIM_CTRLB_CHSIZE_9_BIT        (SERCOM_SPIM_CTRLB_CHSIZE_9_BIT_Val << SERCOM_SPIM_CTRLB_CHSIZE_Pos) /**< (SERCOM_SPIM_CTRLB) 9 bits Position  */
+#define SERCOM_SPIM_CTRLB_PLOADEN_Pos         _U_(6)                                               /**< (SERCOM_SPIM_CTRLB) Data Preload Enable Position */
+#define SERCOM_SPIM_CTRLB_PLOADEN_Msk         (_U_(0x1) << SERCOM_SPIM_CTRLB_PLOADEN_Pos)          /**< (SERCOM_SPIM_CTRLB) Data Preload Enable Mask */
+#define SERCOM_SPIM_CTRLB_PLOADEN(value)      (SERCOM_SPIM_CTRLB_PLOADEN_Msk & ((value) << SERCOM_SPIM_CTRLB_PLOADEN_Pos))
+#define SERCOM_SPIM_CTRLB_SSDE_Pos            _U_(9)                                               /**< (SERCOM_SPIM_CTRLB) Slave Select Low Detect Enable Position */
+#define SERCOM_SPIM_CTRLB_SSDE_Msk            (_U_(0x1) << SERCOM_SPIM_CTRLB_SSDE_Pos)             /**< (SERCOM_SPIM_CTRLB) Slave Select Low Detect Enable Mask */
+#define SERCOM_SPIM_CTRLB_SSDE(value)         (SERCOM_SPIM_CTRLB_SSDE_Msk & ((value) << SERCOM_SPIM_CTRLB_SSDE_Pos))
+#define SERCOM_SPIM_CTRLB_MSSEN_Pos           _U_(13)                                              /**< (SERCOM_SPIM_CTRLB) Master Slave Select Enable Position */
+#define SERCOM_SPIM_CTRLB_MSSEN_Msk           (_U_(0x1) << SERCOM_SPIM_CTRLB_MSSEN_Pos)            /**< (SERCOM_SPIM_CTRLB) Master Slave Select Enable Mask */
+#define SERCOM_SPIM_CTRLB_MSSEN(value)        (SERCOM_SPIM_CTRLB_MSSEN_Msk & ((value) << SERCOM_SPIM_CTRLB_MSSEN_Pos))
+#define SERCOM_SPIM_CTRLB_AMODE_Pos           _U_(14)                                              /**< (SERCOM_SPIM_CTRLB) Address Mode Position */
+#define SERCOM_SPIM_CTRLB_AMODE_Msk           (_U_(0x3) << SERCOM_SPIM_CTRLB_AMODE_Pos)            /**< (SERCOM_SPIM_CTRLB) Address Mode Mask */
+#define SERCOM_SPIM_CTRLB_AMODE(value)        (SERCOM_SPIM_CTRLB_AMODE_Msk & ((value) << SERCOM_SPIM_CTRLB_AMODE_Pos))
+#define   SERCOM_SPIM_CTRLB_AMODE_MASK_Val    _U_(0x0)                                             /**< (SERCOM_SPIM_CTRLB) SPI Address mask   */
+#define   SERCOM_SPIM_CTRLB_AMODE_2_ADDRESSES_Val _U_(0x1)                                             /**< (SERCOM_SPIM_CTRLB) Two unique Addressess  */
+#define   SERCOM_SPIM_CTRLB_AMODE_RANGE_Val   _U_(0x2)                                             /**< (SERCOM_SPIM_CTRLB) Address Range  */
+#define SERCOM_SPIM_CTRLB_AMODE_MASK          (SERCOM_SPIM_CTRLB_AMODE_MASK_Val << SERCOM_SPIM_CTRLB_AMODE_Pos) /**< (SERCOM_SPIM_CTRLB) SPI Address mask  Position  */
+#define SERCOM_SPIM_CTRLB_AMODE_2_ADDRESSES   (SERCOM_SPIM_CTRLB_AMODE_2_ADDRESSES_Val << SERCOM_SPIM_CTRLB_AMODE_Pos) /**< (SERCOM_SPIM_CTRLB) Two unique Addressess Position  */
+#define SERCOM_SPIM_CTRLB_AMODE_RANGE         (SERCOM_SPIM_CTRLB_AMODE_RANGE_Val << SERCOM_SPIM_CTRLB_AMODE_Pos) /**< (SERCOM_SPIM_CTRLB) Address Range Position  */
+#define SERCOM_SPIM_CTRLB_RXEN_Pos            _U_(17)                                              /**< (SERCOM_SPIM_CTRLB) Receiver Enable Position */
+#define SERCOM_SPIM_CTRLB_RXEN_Msk            (_U_(0x1) << SERCOM_SPIM_CTRLB_RXEN_Pos)             /**< (SERCOM_SPIM_CTRLB) Receiver Enable Mask */
+#define SERCOM_SPIM_CTRLB_RXEN(value)         (SERCOM_SPIM_CTRLB_RXEN_Msk & ((value) << SERCOM_SPIM_CTRLB_RXEN_Pos))
+#define SERCOM_SPIM_CTRLB_Msk                 _U_(0x0002E247)                                      /**< (SERCOM_SPIM_CTRLB) Register Mask  */
+
+
+/* -------- SERCOM_SPIS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPIS Control B -------- */
+#define SERCOM_SPIS_CTRLB_RESETVALUE          _U_(0x00)                                            /**<  (SERCOM_SPIS_CTRLB) SPIS Control B  Reset Value */
+
+#define SERCOM_SPIS_CTRLB_CHSIZE_Pos          _U_(0)                                               /**< (SERCOM_SPIS_CTRLB) Character Size Position */
+#define SERCOM_SPIS_CTRLB_CHSIZE_Msk          (_U_(0x7) << SERCOM_SPIS_CTRLB_CHSIZE_Pos)           /**< (SERCOM_SPIS_CTRLB) Character Size Mask */
+#define SERCOM_SPIS_CTRLB_CHSIZE(value)       (SERCOM_SPIS_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPIS_CTRLB_CHSIZE_Pos))
+#define   SERCOM_SPIS_CTRLB_CHSIZE_8_BIT_Val  _U_(0x0)                                             /**< (SERCOM_SPIS_CTRLB) 8 bits  */
+#define   SERCOM_SPIS_CTRLB_CHSIZE_9_BIT_Val  _U_(0x1)                                             /**< (SERCOM_SPIS_CTRLB) 9 bits  */
+#define SERCOM_SPIS_CTRLB_CHSIZE_8_BIT        (SERCOM_SPIS_CTRLB_CHSIZE_8_BIT_Val << SERCOM_SPIS_CTRLB_CHSIZE_Pos) /**< (SERCOM_SPIS_CTRLB) 8 bits Position  */
+#define SERCOM_SPIS_CTRLB_CHSIZE_9_BIT        (SERCOM_SPIS_CTRLB_CHSIZE_9_BIT_Val << SERCOM_SPIS_CTRLB_CHSIZE_Pos) /**< (SERCOM_SPIS_CTRLB) 9 bits Position  */
+#define SERCOM_SPIS_CTRLB_PLOADEN_Pos         _U_(6)                                               /**< (SERCOM_SPIS_CTRLB) Data Preload Enable Position */
+#define SERCOM_SPIS_CTRLB_PLOADEN_Msk         (_U_(0x1) << SERCOM_SPIS_CTRLB_PLOADEN_Pos)          /**< (SERCOM_SPIS_CTRLB) Data Preload Enable Mask */
+#define SERCOM_SPIS_CTRLB_PLOADEN(value)      (SERCOM_SPIS_CTRLB_PLOADEN_Msk & ((value) << SERCOM_SPIS_CTRLB_PLOADEN_Pos))
+#define SERCOM_SPIS_CTRLB_SSDE_Pos            _U_(9)                                               /**< (SERCOM_SPIS_CTRLB) Slave Select Low Detect Enable Position */
+#define SERCOM_SPIS_CTRLB_SSDE_Msk            (_U_(0x1) << SERCOM_SPIS_CTRLB_SSDE_Pos)             /**< (SERCOM_SPIS_CTRLB) Slave Select Low Detect Enable Mask */
+#define SERCOM_SPIS_CTRLB_SSDE(value)         (SERCOM_SPIS_CTRLB_SSDE_Msk & ((value) << SERCOM_SPIS_CTRLB_SSDE_Pos))
+#define SERCOM_SPIS_CTRLB_MSSEN_Pos           _U_(13)                                              /**< (SERCOM_SPIS_CTRLB) Master Slave Select Enable Position */
+#define SERCOM_SPIS_CTRLB_MSSEN_Msk           (_U_(0x1) << SERCOM_SPIS_CTRLB_MSSEN_Pos)            /**< (SERCOM_SPIS_CTRLB) Master Slave Select Enable Mask */
+#define SERCOM_SPIS_CTRLB_MSSEN(value)        (SERCOM_SPIS_CTRLB_MSSEN_Msk & ((value) << SERCOM_SPIS_CTRLB_MSSEN_Pos))
+#define SERCOM_SPIS_CTRLB_AMODE_Pos           _U_(14)                                              /**< (SERCOM_SPIS_CTRLB) Address Mode Position */
+#define SERCOM_SPIS_CTRLB_AMODE_Msk           (_U_(0x3) << SERCOM_SPIS_CTRLB_AMODE_Pos)            /**< (SERCOM_SPIS_CTRLB) Address Mode Mask */
+#define SERCOM_SPIS_CTRLB_AMODE(value)        (SERCOM_SPIS_CTRLB_AMODE_Msk & ((value) << SERCOM_SPIS_CTRLB_AMODE_Pos))
+#define   SERCOM_SPIS_CTRLB_AMODE_MASK_Val    _U_(0x0)                                             /**< (SERCOM_SPIS_CTRLB) SPI Address mask   */
+#define   SERCOM_SPIS_CTRLB_AMODE_2_ADDRESSES_Val _U_(0x1)                                             /**< (SERCOM_SPIS_CTRLB) Two unique Addressess  */
+#define   SERCOM_SPIS_CTRLB_AMODE_RANGE_Val   _U_(0x2)                                             /**< (SERCOM_SPIS_CTRLB) Address Range  */
+#define SERCOM_SPIS_CTRLB_AMODE_MASK          (SERCOM_SPIS_CTRLB_AMODE_MASK_Val << SERCOM_SPIS_CTRLB_AMODE_Pos) /**< (SERCOM_SPIS_CTRLB) SPI Address mask  Position  */
+#define SERCOM_SPIS_CTRLB_AMODE_2_ADDRESSES   (SERCOM_SPIS_CTRLB_AMODE_2_ADDRESSES_Val << SERCOM_SPIS_CTRLB_AMODE_Pos) /**< (SERCOM_SPIS_CTRLB) Two unique Addressess Position  */
+#define SERCOM_SPIS_CTRLB_AMODE_RANGE         (SERCOM_SPIS_CTRLB_AMODE_RANGE_Val << SERCOM_SPIS_CTRLB_AMODE_Pos) /**< (SERCOM_SPIS_CTRLB) Address Range Position  */
+#define SERCOM_SPIS_CTRLB_RXEN_Pos            _U_(17)                                              /**< (SERCOM_SPIS_CTRLB) Receiver Enable Position */
+#define SERCOM_SPIS_CTRLB_RXEN_Msk            (_U_(0x1) << SERCOM_SPIS_CTRLB_RXEN_Pos)             /**< (SERCOM_SPIS_CTRLB) Receiver Enable Mask */
+#define SERCOM_SPIS_CTRLB_RXEN(value)         (SERCOM_SPIS_CTRLB_RXEN_Msk & ((value) << SERCOM_SPIS_CTRLB_RXEN_Pos))
+#define SERCOM_SPIS_CTRLB_Msk                 _U_(0x0002E247)                                      /**< (SERCOM_SPIS_CTRLB) Register Mask  */
+
+
+/* -------- SERCOM_USART_EXT_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART_EXT Control B -------- */
+#define SERCOM_USART_EXT_CTRLB_RESETVALUE     _U_(0x00)                                            /**<  (SERCOM_USART_EXT_CTRLB) USART_EXT Control B  Reset Value */
+
+#define SERCOM_USART_EXT_CTRLB_CHSIZE_Pos     _U_(0)                                               /**< (SERCOM_USART_EXT_CTRLB) Character Size Position */
+#define SERCOM_USART_EXT_CTRLB_CHSIZE_Msk     (_U_(0x7) << SERCOM_USART_EXT_CTRLB_CHSIZE_Pos)      /**< (SERCOM_USART_EXT_CTRLB) Character Size Mask */
+#define SERCOM_USART_EXT_CTRLB_CHSIZE(value)  (SERCOM_USART_EXT_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_EXT_CTRLB_CHSIZE_Pos))
+#define   SERCOM_USART_EXT_CTRLB_CHSIZE_8_BIT_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLB) 8 Bits  */
+#define   SERCOM_USART_EXT_CTRLB_CHSIZE_9_BIT_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLB) 9 Bits  */
+#define   SERCOM_USART_EXT_CTRLB_CHSIZE_5_BIT_Val _U_(0x5)                                             /**< (SERCOM_USART_EXT_CTRLB) 5 Bits  */
+#define   SERCOM_USART_EXT_CTRLB_CHSIZE_6_BIT_Val _U_(0x6)                                             /**< (SERCOM_USART_EXT_CTRLB) 6 Bits  */
+#define   SERCOM_USART_EXT_CTRLB_CHSIZE_7_BIT_Val _U_(0x7)                                             /**< (SERCOM_USART_EXT_CTRLB) 7 Bits  */
+#define SERCOM_USART_EXT_CTRLB_CHSIZE_8_BIT   (SERCOM_USART_EXT_CTRLB_CHSIZE_8_BIT_Val << SERCOM_USART_EXT_CTRLB_CHSIZE_Pos) /**< (SERCOM_USART_EXT_CTRLB) 8 Bits Position  */
+#define SERCOM_USART_EXT_CTRLB_CHSIZE_9_BIT   (SERCOM_USART_EXT_CTRLB_CHSIZE_9_BIT_Val << SERCOM_USART_EXT_CTRLB_CHSIZE_Pos) /**< (SERCOM_USART_EXT_CTRLB) 9 Bits Position  */
+#define SERCOM_USART_EXT_CTRLB_CHSIZE_5_BIT   (SERCOM_USART_EXT_CTRLB_CHSIZE_5_BIT_Val << SERCOM_USART_EXT_CTRLB_CHSIZE_Pos) /**< (SERCOM_USART_EXT_CTRLB) 5 Bits Position  */
+#define SERCOM_USART_EXT_CTRLB_CHSIZE_6_BIT   (SERCOM_USART_EXT_CTRLB_CHSIZE_6_BIT_Val << SERCOM_USART_EXT_CTRLB_CHSIZE_Pos) /**< (SERCOM_USART_EXT_CTRLB) 6 Bits Position  */
+#define SERCOM_USART_EXT_CTRLB_CHSIZE_7_BIT   (SERCOM_USART_EXT_CTRLB_CHSIZE_7_BIT_Val << SERCOM_USART_EXT_CTRLB_CHSIZE_Pos) /**< (SERCOM_USART_EXT_CTRLB) 7 Bits Position  */
+#define SERCOM_USART_EXT_CTRLB_SBMODE_Pos     _U_(6)                                               /**< (SERCOM_USART_EXT_CTRLB) Stop Bit Mode Position */
+#define SERCOM_USART_EXT_CTRLB_SBMODE_Msk     (_U_(0x1) << SERCOM_USART_EXT_CTRLB_SBMODE_Pos)      /**< (SERCOM_USART_EXT_CTRLB) Stop Bit Mode Mask */
+#define SERCOM_USART_EXT_CTRLB_SBMODE(value)  (SERCOM_USART_EXT_CTRLB_SBMODE_Msk & ((value) << SERCOM_USART_EXT_CTRLB_SBMODE_Pos))
+#define   SERCOM_USART_EXT_CTRLB_SBMODE_1_BIT_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLB) One Stop Bit  */
+#define   SERCOM_USART_EXT_CTRLB_SBMODE_2_BIT_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLB) Two Stop Bits  */
+#define SERCOM_USART_EXT_CTRLB_SBMODE_1_BIT   (SERCOM_USART_EXT_CTRLB_SBMODE_1_BIT_Val << SERCOM_USART_EXT_CTRLB_SBMODE_Pos) /**< (SERCOM_USART_EXT_CTRLB) One Stop Bit Position  */
+#define SERCOM_USART_EXT_CTRLB_SBMODE_2_BIT   (SERCOM_USART_EXT_CTRLB_SBMODE_2_BIT_Val << SERCOM_USART_EXT_CTRLB_SBMODE_Pos) /**< (SERCOM_USART_EXT_CTRLB) Two Stop Bits Position  */
+#define SERCOM_USART_EXT_CTRLB_COLDEN_Pos     _U_(8)                                               /**< (SERCOM_USART_EXT_CTRLB) Collision Detection Enable Position */
+#define SERCOM_USART_EXT_CTRLB_COLDEN_Msk     (_U_(0x1) << SERCOM_USART_EXT_CTRLB_COLDEN_Pos)      /**< (SERCOM_USART_EXT_CTRLB) Collision Detection Enable Mask */
+#define SERCOM_USART_EXT_CTRLB_COLDEN(value)  (SERCOM_USART_EXT_CTRLB_COLDEN_Msk & ((value) << SERCOM_USART_EXT_CTRLB_COLDEN_Pos))
+#define SERCOM_USART_EXT_CTRLB_SFDE_Pos       _U_(9)                                               /**< (SERCOM_USART_EXT_CTRLB) Start of Frame Detection Enable Position */
+#define SERCOM_USART_EXT_CTRLB_SFDE_Msk       (_U_(0x1) << SERCOM_USART_EXT_CTRLB_SFDE_Pos)        /**< (SERCOM_USART_EXT_CTRLB) Start of Frame Detection Enable Mask */
+#define SERCOM_USART_EXT_CTRLB_SFDE(value)    (SERCOM_USART_EXT_CTRLB_SFDE_Msk & ((value) << SERCOM_USART_EXT_CTRLB_SFDE_Pos))
+#define SERCOM_USART_EXT_CTRLB_ENC_Pos        _U_(10)                                              /**< (SERCOM_USART_EXT_CTRLB) Encoding Format Position */
+#define SERCOM_USART_EXT_CTRLB_ENC_Msk        (_U_(0x1) << SERCOM_USART_EXT_CTRLB_ENC_Pos)         /**< (SERCOM_USART_EXT_CTRLB) Encoding Format Mask */
+#define SERCOM_USART_EXT_CTRLB_ENC(value)     (SERCOM_USART_EXT_CTRLB_ENC_Msk & ((value) << SERCOM_USART_EXT_CTRLB_ENC_Pos))
+#define SERCOM_USART_EXT_CTRLB_PMODE_Pos      _U_(13)                                              /**< (SERCOM_USART_EXT_CTRLB) Parity Mode Position */
+#define SERCOM_USART_EXT_CTRLB_PMODE_Msk      (_U_(0x1) << SERCOM_USART_EXT_CTRLB_PMODE_Pos)       /**< (SERCOM_USART_EXT_CTRLB) Parity Mode Mask */
+#define SERCOM_USART_EXT_CTRLB_PMODE(value)   (SERCOM_USART_EXT_CTRLB_PMODE_Msk & ((value) << SERCOM_USART_EXT_CTRLB_PMODE_Pos))
+#define   SERCOM_USART_EXT_CTRLB_PMODE_EVEN_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLB) Even Parity  */
+#define   SERCOM_USART_EXT_CTRLB_PMODE_ODD_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLB) Odd Parity  */
+#define SERCOM_USART_EXT_CTRLB_PMODE_EVEN     (SERCOM_USART_EXT_CTRLB_PMODE_EVEN_Val << SERCOM_USART_EXT_CTRLB_PMODE_Pos) /**< (SERCOM_USART_EXT_CTRLB) Even Parity Position  */
+#define SERCOM_USART_EXT_CTRLB_PMODE_ODD      (SERCOM_USART_EXT_CTRLB_PMODE_ODD_Val << SERCOM_USART_EXT_CTRLB_PMODE_Pos) /**< (SERCOM_USART_EXT_CTRLB) Odd Parity Position  */
+#define SERCOM_USART_EXT_CTRLB_TXEN_Pos       _U_(16)                                              /**< (SERCOM_USART_EXT_CTRLB) Transmitter Enable Position */
+#define SERCOM_USART_EXT_CTRLB_TXEN_Msk       (_U_(0x1) << SERCOM_USART_EXT_CTRLB_TXEN_Pos)        /**< (SERCOM_USART_EXT_CTRLB) Transmitter Enable Mask */
+#define SERCOM_USART_EXT_CTRLB_TXEN(value)    (SERCOM_USART_EXT_CTRLB_TXEN_Msk & ((value) << SERCOM_USART_EXT_CTRLB_TXEN_Pos))
+#define SERCOM_USART_EXT_CTRLB_RXEN_Pos       _U_(17)                                              /**< (SERCOM_USART_EXT_CTRLB) Receiver Enable Position */
+#define SERCOM_USART_EXT_CTRLB_RXEN_Msk       (_U_(0x1) << SERCOM_USART_EXT_CTRLB_RXEN_Pos)        /**< (SERCOM_USART_EXT_CTRLB) Receiver Enable Mask */
+#define SERCOM_USART_EXT_CTRLB_RXEN(value)    (SERCOM_USART_EXT_CTRLB_RXEN_Msk & ((value) << SERCOM_USART_EXT_CTRLB_RXEN_Pos))
+#define SERCOM_USART_EXT_CTRLB_LINCMD_Pos     _U_(24)                                              /**< (SERCOM_USART_EXT_CTRLB) LIN Command Position */
+#define SERCOM_USART_EXT_CTRLB_LINCMD_Msk     (_U_(0x3) << SERCOM_USART_EXT_CTRLB_LINCMD_Pos)      /**< (SERCOM_USART_EXT_CTRLB) LIN Command Mask */
+#define SERCOM_USART_EXT_CTRLB_LINCMD(value)  (SERCOM_USART_EXT_CTRLB_LINCMD_Msk & ((value) << SERCOM_USART_EXT_CTRLB_LINCMD_Pos))
+#define   SERCOM_USART_EXT_CTRLB_LINCMD_NONE_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLB) Normal USART transmission  */
+#define   SERCOM_USART_EXT_CTRLB_LINCMD_SOFTWARE_CONTROL_TRANSMIT_CMD_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLB) Break field is transmitted when DATA is written  */
+#define   SERCOM_USART_EXT_CTRLB_LINCMD_AUTO_TRANSMIT_CMD_Val _U_(0x2)                                             /**< (SERCOM_USART_EXT_CTRLB) Break, sync and identifier are automatically transmitted when DATA is written with the identifier  */
+#define SERCOM_USART_EXT_CTRLB_LINCMD_NONE    (SERCOM_USART_EXT_CTRLB_LINCMD_NONE_Val << SERCOM_USART_EXT_CTRLB_LINCMD_Pos) /**< (SERCOM_USART_EXT_CTRLB) Normal USART transmission Position  */
+#define SERCOM_USART_EXT_CTRLB_LINCMD_SOFTWARE_CONTROL_TRANSMIT_CMD (SERCOM_USART_EXT_CTRLB_LINCMD_SOFTWARE_CONTROL_TRANSMIT_CMD_Val << SERCOM_USART_EXT_CTRLB_LINCMD_Pos) /**< (SERCOM_USART_EXT_CTRLB) Break field is transmitted when DATA is written Position  */
+#define SERCOM_USART_EXT_CTRLB_LINCMD_AUTO_TRANSMIT_CMD (SERCOM_USART_EXT_CTRLB_LINCMD_AUTO_TRANSMIT_CMD_Val << SERCOM_USART_EXT_CTRLB_LINCMD_Pos) /**< (SERCOM_USART_EXT_CTRLB) Break, sync and identifier are automatically transmitted when DATA is written with the identifier Position  */
+#define SERCOM_USART_EXT_CTRLB_Msk            _U_(0x03032747)                                      /**< (SERCOM_USART_EXT_CTRLB) Register Mask  */
+
+
+/* -------- SERCOM_USART_INT_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART_INT Control B -------- */
+#define SERCOM_USART_INT_CTRLB_RESETVALUE     _U_(0x00)                                            /**<  (SERCOM_USART_INT_CTRLB) USART_INT Control B  Reset Value */
+
+#define SERCOM_USART_INT_CTRLB_CHSIZE_Pos     _U_(0)                                               /**< (SERCOM_USART_INT_CTRLB) Character Size Position */
+#define SERCOM_USART_INT_CTRLB_CHSIZE_Msk     (_U_(0x7) << SERCOM_USART_INT_CTRLB_CHSIZE_Pos)      /**< (SERCOM_USART_INT_CTRLB) Character Size Mask */
+#define SERCOM_USART_INT_CTRLB_CHSIZE(value)  (SERCOM_USART_INT_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_INT_CTRLB_CHSIZE_Pos))
+#define   SERCOM_USART_INT_CTRLB_CHSIZE_8_BIT_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLB) 8 Bits  */
+#define   SERCOM_USART_INT_CTRLB_CHSIZE_9_BIT_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLB) 9 Bits  */
+#define   SERCOM_USART_INT_CTRLB_CHSIZE_5_BIT_Val _U_(0x5)                                             /**< (SERCOM_USART_INT_CTRLB) 5 Bits  */
+#define   SERCOM_USART_INT_CTRLB_CHSIZE_6_BIT_Val _U_(0x6)                                             /**< (SERCOM_USART_INT_CTRLB) 6 Bits  */
+#define   SERCOM_USART_INT_CTRLB_CHSIZE_7_BIT_Val _U_(0x7)                                             /**< (SERCOM_USART_INT_CTRLB) 7 Bits  */
+#define SERCOM_USART_INT_CTRLB_CHSIZE_8_BIT   (SERCOM_USART_INT_CTRLB_CHSIZE_8_BIT_Val << SERCOM_USART_INT_CTRLB_CHSIZE_Pos) /**< (SERCOM_USART_INT_CTRLB) 8 Bits Position  */
+#define SERCOM_USART_INT_CTRLB_CHSIZE_9_BIT   (SERCOM_USART_INT_CTRLB_CHSIZE_9_BIT_Val << SERCOM_USART_INT_CTRLB_CHSIZE_Pos) /**< (SERCOM_USART_INT_CTRLB) 9 Bits Position  */
+#define SERCOM_USART_INT_CTRLB_CHSIZE_5_BIT   (SERCOM_USART_INT_CTRLB_CHSIZE_5_BIT_Val << SERCOM_USART_INT_CTRLB_CHSIZE_Pos) /**< (SERCOM_USART_INT_CTRLB) 5 Bits Position  */
+#define SERCOM_USART_INT_CTRLB_CHSIZE_6_BIT   (SERCOM_USART_INT_CTRLB_CHSIZE_6_BIT_Val << SERCOM_USART_INT_CTRLB_CHSIZE_Pos) /**< (SERCOM_USART_INT_CTRLB) 6 Bits Position  */
+#define SERCOM_USART_INT_CTRLB_CHSIZE_7_BIT   (SERCOM_USART_INT_CTRLB_CHSIZE_7_BIT_Val << SERCOM_USART_INT_CTRLB_CHSIZE_Pos) /**< (SERCOM_USART_INT_CTRLB) 7 Bits Position  */
+#define SERCOM_USART_INT_CTRLB_SBMODE_Pos     _U_(6)                                               /**< (SERCOM_USART_INT_CTRLB) Stop Bit Mode Position */
+#define SERCOM_USART_INT_CTRLB_SBMODE_Msk     (_U_(0x1) << SERCOM_USART_INT_CTRLB_SBMODE_Pos)      /**< (SERCOM_USART_INT_CTRLB) Stop Bit Mode Mask */
+#define SERCOM_USART_INT_CTRLB_SBMODE(value)  (SERCOM_USART_INT_CTRLB_SBMODE_Msk & ((value) << SERCOM_USART_INT_CTRLB_SBMODE_Pos))
+#define   SERCOM_USART_INT_CTRLB_SBMODE_1_BIT_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLB) One Stop Bit  */
+#define   SERCOM_USART_INT_CTRLB_SBMODE_2_BIT_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLB) Two Stop Bits  */
+#define SERCOM_USART_INT_CTRLB_SBMODE_1_BIT   (SERCOM_USART_INT_CTRLB_SBMODE_1_BIT_Val << SERCOM_USART_INT_CTRLB_SBMODE_Pos) /**< (SERCOM_USART_INT_CTRLB) One Stop Bit Position  */
+#define SERCOM_USART_INT_CTRLB_SBMODE_2_BIT   (SERCOM_USART_INT_CTRLB_SBMODE_2_BIT_Val << SERCOM_USART_INT_CTRLB_SBMODE_Pos) /**< (SERCOM_USART_INT_CTRLB) Two Stop Bits Position  */
+#define SERCOM_USART_INT_CTRLB_COLDEN_Pos     _U_(8)                                               /**< (SERCOM_USART_INT_CTRLB) Collision Detection Enable Position */
+#define SERCOM_USART_INT_CTRLB_COLDEN_Msk     (_U_(0x1) << SERCOM_USART_INT_CTRLB_COLDEN_Pos)      /**< (SERCOM_USART_INT_CTRLB) Collision Detection Enable Mask */
+#define SERCOM_USART_INT_CTRLB_COLDEN(value)  (SERCOM_USART_INT_CTRLB_COLDEN_Msk & ((value) << SERCOM_USART_INT_CTRLB_COLDEN_Pos))
+#define SERCOM_USART_INT_CTRLB_SFDE_Pos       _U_(9)                                               /**< (SERCOM_USART_INT_CTRLB) Start of Frame Detection Enable Position */
+#define SERCOM_USART_INT_CTRLB_SFDE_Msk       (_U_(0x1) << SERCOM_USART_INT_CTRLB_SFDE_Pos)        /**< (SERCOM_USART_INT_CTRLB) Start of Frame Detection Enable Mask */
+#define SERCOM_USART_INT_CTRLB_SFDE(value)    (SERCOM_USART_INT_CTRLB_SFDE_Msk & ((value) << SERCOM_USART_INT_CTRLB_SFDE_Pos))
+#define SERCOM_USART_INT_CTRLB_ENC_Pos        _U_(10)                                              /**< (SERCOM_USART_INT_CTRLB) Encoding Format Position */
+#define SERCOM_USART_INT_CTRLB_ENC_Msk        (_U_(0x1) << SERCOM_USART_INT_CTRLB_ENC_Pos)         /**< (SERCOM_USART_INT_CTRLB) Encoding Format Mask */
+#define SERCOM_USART_INT_CTRLB_ENC(value)     (SERCOM_USART_INT_CTRLB_ENC_Msk & ((value) << SERCOM_USART_INT_CTRLB_ENC_Pos))
+#define SERCOM_USART_INT_CTRLB_PMODE_Pos      _U_(13)                                              /**< (SERCOM_USART_INT_CTRLB) Parity Mode Position */
+#define SERCOM_USART_INT_CTRLB_PMODE_Msk      (_U_(0x1) << SERCOM_USART_INT_CTRLB_PMODE_Pos)       /**< (SERCOM_USART_INT_CTRLB) Parity Mode Mask */
+#define SERCOM_USART_INT_CTRLB_PMODE(value)   (SERCOM_USART_INT_CTRLB_PMODE_Msk & ((value) << SERCOM_USART_INT_CTRLB_PMODE_Pos))
+#define   SERCOM_USART_INT_CTRLB_PMODE_EVEN_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLB) Even Parity  */
+#define   SERCOM_USART_INT_CTRLB_PMODE_ODD_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLB) Odd Parity  */
+#define SERCOM_USART_INT_CTRLB_PMODE_EVEN     (SERCOM_USART_INT_CTRLB_PMODE_EVEN_Val << SERCOM_USART_INT_CTRLB_PMODE_Pos) /**< (SERCOM_USART_INT_CTRLB) Even Parity Position  */
+#define SERCOM_USART_INT_CTRLB_PMODE_ODD      (SERCOM_USART_INT_CTRLB_PMODE_ODD_Val << SERCOM_USART_INT_CTRLB_PMODE_Pos) /**< (SERCOM_USART_INT_CTRLB) Odd Parity Position  */
+#define SERCOM_USART_INT_CTRLB_TXEN_Pos       _U_(16)                                              /**< (SERCOM_USART_INT_CTRLB) Transmitter Enable Position */
+#define SERCOM_USART_INT_CTRLB_TXEN_Msk       (_U_(0x1) << SERCOM_USART_INT_CTRLB_TXEN_Pos)        /**< (SERCOM_USART_INT_CTRLB) Transmitter Enable Mask */
+#define SERCOM_USART_INT_CTRLB_TXEN(value)    (SERCOM_USART_INT_CTRLB_TXEN_Msk & ((value) << SERCOM_USART_INT_CTRLB_TXEN_Pos))
+#define SERCOM_USART_INT_CTRLB_RXEN_Pos       _U_(17)                                              /**< (SERCOM_USART_INT_CTRLB) Receiver Enable Position */
+#define SERCOM_USART_INT_CTRLB_RXEN_Msk       (_U_(0x1) << SERCOM_USART_INT_CTRLB_RXEN_Pos)        /**< (SERCOM_USART_INT_CTRLB) Receiver Enable Mask */
+#define SERCOM_USART_INT_CTRLB_RXEN(value)    (SERCOM_USART_INT_CTRLB_RXEN_Msk & ((value) << SERCOM_USART_INT_CTRLB_RXEN_Pos))
+#define SERCOM_USART_INT_CTRLB_LINCMD_Pos     _U_(24)                                              /**< (SERCOM_USART_INT_CTRLB) LIN Command Position */
+#define SERCOM_USART_INT_CTRLB_LINCMD_Msk     (_U_(0x3) << SERCOM_USART_INT_CTRLB_LINCMD_Pos)      /**< (SERCOM_USART_INT_CTRLB) LIN Command Mask */
+#define SERCOM_USART_INT_CTRLB_LINCMD(value)  (SERCOM_USART_INT_CTRLB_LINCMD_Msk & ((value) << SERCOM_USART_INT_CTRLB_LINCMD_Pos))
+#define   SERCOM_USART_INT_CTRLB_LINCMD_NONE_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLB) Normal USART transmission  */
+#define   SERCOM_USART_INT_CTRLB_LINCMD_SOFTWARE_CONTROL_TRANSMIT_CMD_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLB) Break field is transmitted when DATA is written  */
+#define   SERCOM_USART_INT_CTRLB_LINCMD_AUTO_TRANSMIT_CMD_Val _U_(0x2)                                             /**< (SERCOM_USART_INT_CTRLB) Break, sync and identifier are automatically transmitted when DATA is written with the identifier  */
+#define SERCOM_USART_INT_CTRLB_LINCMD_NONE    (SERCOM_USART_INT_CTRLB_LINCMD_NONE_Val << SERCOM_USART_INT_CTRLB_LINCMD_Pos) /**< (SERCOM_USART_INT_CTRLB) Normal USART transmission Position  */
+#define SERCOM_USART_INT_CTRLB_LINCMD_SOFTWARE_CONTROL_TRANSMIT_CMD (SERCOM_USART_INT_CTRLB_LINCMD_SOFTWARE_CONTROL_TRANSMIT_CMD_Val << SERCOM_USART_INT_CTRLB_LINCMD_Pos) /**< (SERCOM_USART_INT_CTRLB) Break field is transmitted when DATA is written Position  */
+#define SERCOM_USART_INT_CTRLB_LINCMD_AUTO_TRANSMIT_CMD (SERCOM_USART_INT_CTRLB_LINCMD_AUTO_TRANSMIT_CMD_Val << SERCOM_USART_INT_CTRLB_LINCMD_Pos) /**< (SERCOM_USART_INT_CTRLB) Break, sync and identifier are automatically transmitted when DATA is written with the identifier Position  */
+#define SERCOM_USART_INT_CTRLB_Msk            _U_(0x03032747)                                      /**< (SERCOM_USART_INT_CTRLB) Register Mask  */
+
+
+/* -------- SERCOM_I2CM_CTRLC : (SERCOM Offset: 0x08) (R/W 32) I2CM Control C -------- */
+#define SERCOM_I2CM_CTRLC_RESETVALUE          _U_(0x00)                                            /**<  (SERCOM_I2CM_CTRLC) I2CM Control C  Reset Value */
+
+#define SERCOM_I2CM_CTRLC_DATA32B_Pos         _U_(24)                                              /**< (SERCOM_I2CM_CTRLC) Data 32 Bit Position */
+#define SERCOM_I2CM_CTRLC_DATA32B_Msk         (_U_(0x1) << SERCOM_I2CM_CTRLC_DATA32B_Pos)          /**< (SERCOM_I2CM_CTRLC) Data 32 Bit Mask */
+#define SERCOM_I2CM_CTRLC_DATA32B(value)      (SERCOM_I2CM_CTRLC_DATA32B_Msk & ((value) << SERCOM_I2CM_CTRLC_DATA32B_Pos))
+#define   SERCOM_I2CM_CTRLC_DATA32B_DATA_TRANS_8BIT_Val _U_(0x0)                                             /**< (SERCOM_I2CM_CTRLC) Data transaction from/to DATA register are 8-bit  */
+#define   SERCOM_I2CM_CTRLC_DATA32B_DATA_TRANS_32BIT_Val _U_(0x1)                                             /**< (SERCOM_I2CM_CTRLC) Data transaction from/to DATA register are 32-bit  */
+#define SERCOM_I2CM_CTRLC_DATA32B_DATA_TRANS_8BIT (SERCOM_I2CM_CTRLC_DATA32B_DATA_TRANS_8BIT_Val << SERCOM_I2CM_CTRLC_DATA32B_Pos) /**< (SERCOM_I2CM_CTRLC) Data transaction from/to DATA register are 8-bit Position  */
+#define SERCOM_I2CM_CTRLC_DATA32B_DATA_TRANS_32BIT (SERCOM_I2CM_CTRLC_DATA32B_DATA_TRANS_32BIT_Val << SERCOM_I2CM_CTRLC_DATA32B_Pos) /**< (SERCOM_I2CM_CTRLC) Data transaction from/to DATA register are 32-bit Position  */
+#define SERCOM_I2CM_CTRLC_Msk                 _U_(0x01000000)                                      /**< (SERCOM_I2CM_CTRLC) Register Mask  */
+
+
+/* -------- SERCOM_I2CS_CTRLC : (SERCOM Offset: 0x08) (R/W 32) I2CS Control C -------- */
+#define SERCOM_I2CS_CTRLC_RESETVALUE          _U_(0x00)                                            /**<  (SERCOM_I2CS_CTRLC) I2CS Control C  Reset Value */
+
+#define SERCOM_I2CS_CTRLC_SDASETUP_Pos        _U_(0)                                               /**< (SERCOM_I2CS_CTRLC) SDA Setup Time Position */
+#define SERCOM_I2CS_CTRLC_SDASETUP_Msk        (_U_(0xF) << SERCOM_I2CS_CTRLC_SDASETUP_Pos)         /**< (SERCOM_I2CS_CTRLC) SDA Setup Time Mask */
+#define SERCOM_I2CS_CTRLC_SDASETUP(value)     (SERCOM_I2CS_CTRLC_SDASETUP_Msk & ((value) << SERCOM_I2CS_CTRLC_SDASETUP_Pos))
+#define SERCOM_I2CS_CTRLC_DATA32B_Pos         _U_(24)                                              /**< (SERCOM_I2CS_CTRLC) Data 32 Bit Position */
+#define SERCOM_I2CS_CTRLC_DATA32B_Msk         (_U_(0x1) << SERCOM_I2CS_CTRLC_DATA32B_Pos)          /**< (SERCOM_I2CS_CTRLC) Data 32 Bit Mask */
+#define SERCOM_I2CS_CTRLC_DATA32B(value)      (SERCOM_I2CS_CTRLC_DATA32B_Msk & ((value) << SERCOM_I2CS_CTRLC_DATA32B_Pos))
+#define   SERCOM_I2CS_CTRLC_DATA32B_DATA_TRANS_8BIT_Val _U_(0x0)                                             /**< (SERCOM_I2CS_CTRLC) Data transaction from/to DATA register are 8-bit  */
+#define   SERCOM_I2CS_CTRLC_DATA32B_DATA_TRANS_32BIT_Val _U_(0x1)                                             /**< (SERCOM_I2CS_CTRLC) Data transaction from/to DATA register are 32-bit  */
+#define SERCOM_I2CS_CTRLC_DATA32B_DATA_TRANS_8BIT (SERCOM_I2CS_CTRLC_DATA32B_DATA_TRANS_8BIT_Val << SERCOM_I2CS_CTRLC_DATA32B_Pos) /**< (SERCOM_I2CS_CTRLC) Data transaction from/to DATA register are 8-bit Position  */
+#define SERCOM_I2CS_CTRLC_DATA32B_DATA_TRANS_32BIT (SERCOM_I2CS_CTRLC_DATA32B_DATA_TRANS_32BIT_Val << SERCOM_I2CS_CTRLC_DATA32B_Pos) /**< (SERCOM_I2CS_CTRLC) Data transaction from/to DATA register are 32-bit Position  */
+#define SERCOM_I2CS_CTRLC_Msk                 _U_(0x0100000F)                                      /**< (SERCOM_I2CS_CTRLC) Register Mask  */
+
+
+/* -------- SERCOM_SPIM_CTRLC : (SERCOM Offset: 0x08) (R/W 32) SPIM Control C -------- */
+#define SERCOM_SPIM_CTRLC_RESETVALUE          _U_(0x00)                                            /**<  (SERCOM_SPIM_CTRLC) SPIM Control C  Reset Value */
+
+#define SERCOM_SPIM_CTRLC_ICSPACE_Pos         _U_(0)                                               /**< (SERCOM_SPIM_CTRLC) Inter-Character Spacing Position */
+#define SERCOM_SPIM_CTRLC_ICSPACE_Msk         (_U_(0x3F) << SERCOM_SPIM_CTRLC_ICSPACE_Pos)         /**< (SERCOM_SPIM_CTRLC) Inter-Character Spacing Mask */
+#define SERCOM_SPIM_CTRLC_ICSPACE(value)      (SERCOM_SPIM_CTRLC_ICSPACE_Msk & ((value) << SERCOM_SPIM_CTRLC_ICSPACE_Pos))
+#define SERCOM_SPIM_CTRLC_DATA32B_Pos         _U_(24)                                              /**< (SERCOM_SPIM_CTRLC) Data 32 Bit Position */
+#define SERCOM_SPIM_CTRLC_DATA32B_Msk         (_U_(0x1) << SERCOM_SPIM_CTRLC_DATA32B_Pos)          /**< (SERCOM_SPIM_CTRLC) Data 32 Bit Mask */
+#define SERCOM_SPIM_CTRLC_DATA32B(value)      (SERCOM_SPIM_CTRLC_DATA32B_Msk & ((value) << SERCOM_SPIM_CTRLC_DATA32B_Pos))
+#define   SERCOM_SPIM_CTRLC_DATA32B_DATA_TRANS_8BIT_Val _U_(0x0)                                             /**< (SERCOM_SPIM_CTRLC) Transaction from and to DATA register are 8-bit  */
+#define   SERCOM_SPIM_CTRLC_DATA32B_DATA_TRANS_32BIT_Val _U_(0x1)                                             /**< (SERCOM_SPIM_CTRLC) Transaction from and to DATA register are 32-bit  */
+#define SERCOM_SPIM_CTRLC_DATA32B_DATA_TRANS_8BIT (SERCOM_SPIM_CTRLC_DATA32B_DATA_TRANS_8BIT_Val << SERCOM_SPIM_CTRLC_DATA32B_Pos) /**< (SERCOM_SPIM_CTRLC) Transaction from and to DATA register are 8-bit Position  */
+#define SERCOM_SPIM_CTRLC_DATA32B_DATA_TRANS_32BIT (SERCOM_SPIM_CTRLC_DATA32B_DATA_TRANS_32BIT_Val << SERCOM_SPIM_CTRLC_DATA32B_Pos) /**< (SERCOM_SPIM_CTRLC) Transaction from and to DATA register are 32-bit Position  */
+#define SERCOM_SPIM_CTRLC_Msk                 _U_(0x0100003F)                                      /**< (SERCOM_SPIM_CTRLC) Register Mask  */
+
+
+/* -------- SERCOM_SPIS_CTRLC : (SERCOM Offset: 0x08) (R/W 32) SPIS Control C -------- */
+#define SERCOM_SPIS_CTRLC_RESETVALUE          _U_(0x00)                                            /**<  (SERCOM_SPIS_CTRLC) SPIS Control C  Reset Value */
+
+#define SERCOM_SPIS_CTRLC_ICSPACE_Pos         _U_(0)                                               /**< (SERCOM_SPIS_CTRLC) Inter-Character Spacing Position */
+#define SERCOM_SPIS_CTRLC_ICSPACE_Msk         (_U_(0x3F) << SERCOM_SPIS_CTRLC_ICSPACE_Pos)         /**< (SERCOM_SPIS_CTRLC) Inter-Character Spacing Mask */
+#define SERCOM_SPIS_CTRLC_ICSPACE(value)      (SERCOM_SPIS_CTRLC_ICSPACE_Msk & ((value) << SERCOM_SPIS_CTRLC_ICSPACE_Pos))
+#define SERCOM_SPIS_CTRLC_DATA32B_Pos         _U_(24)                                              /**< (SERCOM_SPIS_CTRLC) Data 32 Bit Position */
+#define SERCOM_SPIS_CTRLC_DATA32B_Msk         (_U_(0x1) << SERCOM_SPIS_CTRLC_DATA32B_Pos)          /**< (SERCOM_SPIS_CTRLC) Data 32 Bit Mask */
+#define SERCOM_SPIS_CTRLC_DATA32B(value)      (SERCOM_SPIS_CTRLC_DATA32B_Msk & ((value) << SERCOM_SPIS_CTRLC_DATA32B_Pos))
+#define   SERCOM_SPIS_CTRLC_DATA32B_DATA_TRANS_8BIT_Val _U_(0x0)                                             /**< (SERCOM_SPIS_CTRLC) Transaction from and to DATA register are 8-bit  */
+#define   SERCOM_SPIS_CTRLC_DATA32B_DATA_TRANS_32BIT_Val _U_(0x1)                                             /**< (SERCOM_SPIS_CTRLC) Transaction from and to DATA register are 32-bit  */
+#define SERCOM_SPIS_CTRLC_DATA32B_DATA_TRANS_8BIT (SERCOM_SPIS_CTRLC_DATA32B_DATA_TRANS_8BIT_Val << SERCOM_SPIS_CTRLC_DATA32B_Pos) /**< (SERCOM_SPIS_CTRLC) Transaction from and to DATA register are 8-bit Position  */
+#define SERCOM_SPIS_CTRLC_DATA32B_DATA_TRANS_32BIT (SERCOM_SPIS_CTRLC_DATA32B_DATA_TRANS_32BIT_Val << SERCOM_SPIS_CTRLC_DATA32B_Pos) /**< (SERCOM_SPIS_CTRLC) Transaction from and to DATA register are 32-bit Position  */
+#define SERCOM_SPIS_CTRLC_Msk                 _U_(0x0100003F)                                      /**< (SERCOM_SPIS_CTRLC) Register Mask  */
+
+
+/* -------- SERCOM_USART_EXT_CTRLC : (SERCOM Offset: 0x08) (R/W 32) USART_EXT Control C -------- */
+#define SERCOM_USART_EXT_CTRLC_RESETVALUE     _U_(0x00)                                            /**<  (SERCOM_USART_EXT_CTRLC) USART_EXT Control C  Reset Value */
+
+#define SERCOM_USART_EXT_CTRLC_GTIME_Pos      _U_(0)                                               /**< (SERCOM_USART_EXT_CTRLC) Guard Time Position */
+#define SERCOM_USART_EXT_CTRLC_GTIME_Msk      (_U_(0x7) << SERCOM_USART_EXT_CTRLC_GTIME_Pos)       /**< (SERCOM_USART_EXT_CTRLC) Guard Time Mask */
+#define SERCOM_USART_EXT_CTRLC_GTIME(value)   (SERCOM_USART_EXT_CTRLC_GTIME_Msk & ((value) << SERCOM_USART_EXT_CTRLC_GTIME_Pos))
+#define SERCOM_USART_EXT_CTRLC_BRKLEN_Pos     _U_(8)                                               /**< (SERCOM_USART_EXT_CTRLC) LIN Master Break Length Position */
+#define SERCOM_USART_EXT_CTRLC_BRKLEN_Msk     (_U_(0x3) << SERCOM_USART_EXT_CTRLC_BRKLEN_Pos)      /**< (SERCOM_USART_EXT_CTRLC) LIN Master Break Length Mask */
+#define SERCOM_USART_EXT_CTRLC_BRKLEN(value)  (SERCOM_USART_EXT_CTRLC_BRKLEN_Msk & ((value) << SERCOM_USART_EXT_CTRLC_BRKLEN_Pos))
+#define   SERCOM_USART_EXT_CTRLC_BRKLEN_13_BIT_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLC) Break field transmission is 13 bit times  */
+#define   SERCOM_USART_EXT_CTRLC_BRKLEN_17_BIT_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLC) Break field transmission is 17 bit times  */
+#define   SERCOM_USART_EXT_CTRLC_BRKLEN_21_BIT_Val _U_(0x2)                                             /**< (SERCOM_USART_EXT_CTRLC) Break field transmission is 21 bit times  */
+#define   SERCOM_USART_EXT_CTRLC_BRKLEN_26_BIT_Val _U_(0x3)                                             /**< (SERCOM_USART_EXT_CTRLC) Break field transmission is 26 bit times  */
+#define SERCOM_USART_EXT_CTRLC_BRKLEN_13_BIT  (SERCOM_USART_EXT_CTRLC_BRKLEN_13_BIT_Val << SERCOM_USART_EXT_CTRLC_BRKLEN_Pos) /**< (SERCOM_USART_EXT_CTRLC) Break field transmission is 13 bit times Position  */
+#define SERCOM_USART_EXT_CTRLC_BRKLEN_17_BIT  (SERCOM_USART_EXT_CTRLC_BRKLEN_17_BIT_Val << SERCOM_USART_EXT_CTRLC_BRKLEN_Pos) /**< (SERCOM_USART_EXT_CTRLC) Break field transmission is 17 bit times Position  */
+#define SERCOM_USART_EXT_CTRLC_BRKLEN_21_BIT  (SERCOM_USART_EXT_CTRLC_BRKLEN_21_BIT_Val << SERCOM_USART_EXT_CTRLC_BRKLEN_Pos) /**< (SERCOM_USART_EXT_CTRLC) Break field transmission is 21 bit times Position  */
+#define SERCOM_USART_EXT_CTRLC_BRKLEN_26_BIT  (SERCOM_USART_EXT_CTRLC_BRKLEN_26_BIT_Val << SERCOM_USART_EXT_CTRLC_BRKLEN_Pos) /**< (SERCOM_USART_EXT_CTRLC) Break field transmission is 26 bit times Position  */
+#define SERCOM_USART_EXT_CTRLC_HDRDLY_Pos     _U_(10)                                              /**< (SERCOM_USART_EXT_CTRLC) LIN Master Header Delay Position */
+#define SERCOM_USART_EXT_CTRLC_HDRDLY_Msk     (_U_(0x3) << SERCOM_USART_EXT_CTRLC_HDRDLY_Pos)      /**< (SERCOM_USART_EXT_CTRLC) LIN Master Header Delay Mask */
+#define SERCOM_USART_EXT_CTRLC_HDRDLY(value)  (SERCOM_USART_EXT_CTRLC_HDRDLY_Msk & ((value) << SERCOM_USART_EXT_CTRLC_HDRDLY_Pos))
+#define   SERCOM_USART_EXT_CTRLC_HDRDLY_DELAY0_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLC) Delay between break and sync transmission is 1 bit time; Delay between sync and ID transmission is 1 bit time  */
+#define   SERCOM_USART_EXT_CTRLC_HDRDLY_DELAY1_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLC) Delay between break and sync transmission is 4 bit time; Delay between sync and ID transmission is 4 bit time  */
+#define   SERCOM_USART_EXT_CTRLC_HDRDLY_DELAY2_Val _U_(0x2)                                             /**< (SERCOM_USART_EXT_CTRLC) Delay between break and sync transmission is 8 bit time; Delay between sync and ID transmission is 4 bit time  */
+#define   SERCOM_USART_EXT_CTRLC_HDRDLY_DELAY3_Val _U_(0x3)                                             /**< (SERCOM_USART_EXT_CTRLC) Delay between break and sync transmission is 14 bit time; Delay between sync and ID transmission is 4 bit time  */
+#define SERCOM_USART_EXT_CTRLC_HDRDLY_DELAY0  (SERCOM_USART_EXT_CTRLC_HDRDLY_DELAY0_Val << SERCOM_USART_EXT_CTRLC_HDRDLY_Pos) /**< (SERCOM_USART_EXT_CTRLC) Delay between break and sync transmission is 1 bit time; Delay between sync and ID transmission is 1 bit time Position  */
+#define SERCOM_USART_EXT_CTRLC_HDRDLY_DELAY1  (SERCOM_USART_EXT_CTRLC_HDRDLY_DELAY1_Val << SERCOM_USART_EXT_CTRLC_HDRDLY_Pos) /**< (SERCOM_USART_EXT_CTRLC) Delay between break and sync transmission is 4 bit time; Delay between sync and ID transmission is 4 bit time Position  */
+#define SERCOM_USART_EXT_CTRLC_HDRDLY_DELAY2  (SERCOM_USART_EXT_CTRLC_HDRDLY_DELAY2_Val << SERCOM_USART_EXT_CTRLC_HDRDLY_Pos) /**< (SERCOM_USART_EXT_CTRLC) Delay between break and sync transmission is 8 bit time; Delay between sync and ID transmission is 4 bit time Position  */
+#define SERCOM_USART_EXT_CTRLC_HDRDLY_DELAY3  (SERCOM_USART_EXT_CTRLC_HDRDLY_DELAY3_Val << SERCOM_USART_EXT_CTRLC_HDRDLY_Pos) /**< (SERCOM_USART_EXT_CTRLC) Delay between break and sync transmission is 14 bit time; Delay between sync and ID transmission is 4 bit time Position  */
+#define SERCOM_USART_EXT_CTRLC_INACK_Pos      _U_(16)                                              /**< (SERCOM_USART_EXT_CTRLC) Inhibit Not Acknowledge Position */
+#define SERCOM_USART_EXT_CTRLC_INACK_Msk      (_U_(0x1) << SERCOM_USART_EXT_CTRLC_INACK_Pos)       /**< (SERCOM_USART_EXT_CTRLC) Inhibit Not Acknowledge Mask */
+#define SERCOM_USART_EXT_CTRLC_INACK(value)   (SERCOM_USART_EXT_CTRLC_INACK_Msk & ((value) << SERCOM_USART_EXT_CTRLC_INACK_Pos))
+#define SERCOM_USART_EXT_CTRLC_DSNACK_Pos     _U_(17)                                              /**< (SERCOM_USART_EXT_CTRLC) Disable Successive NACK Position */
+#define SERCOM_USART_EXT_CTRLC_DSNACK_Msk     (_U_(0x1) << SERCOM_USART_EXT_CTRLC_DSNACK_Pos)      /**< (SERCOM_USART_EXT_CTRLC) Disable Successive NACK Mask */
+#define SERCOM_USART_EXT_CTRLC_DSNACK(value)  (SERCOM_USART_EXT_CTRLC_DSNACK_Msk & ((value) << SERCOM_USART_EXT_CTRLC_DSNACK_Pos))
+#define SERCOM_USART_EXT_CTRLC_MAXITER_Pos    _U_(20)                                              /**< (SERCOM_USART_EXT_CTRLC) Maximum Iterations Position */
+#define SERCOM_USART_EXT_CTRLC_MAXITER_Msk    (_U_(0x7) << SERCOM_USART_EXT_CTRLC_MAXITER_Pos)     /**< (SERCOM_USART_EXT_CTRLC) Maximum Iterations Mask */
+#define SERCOM_USART_EXT_CTRLC_MAXITER(value) (SERCOM_USART_EXT_CTRLC_MAXITER_Msk & ((value) << SERCOM_USART_EXT_CTRLC_MAXITER_Pos))
+#define SERCOM_USART_EXT_CTRLC_DATA32B_Pos    _U_(24)                                              /**< (SERCOM_USART_EXT_CTRLC) Data 32 Bit Position */
+#define SERCOM_USART_EXT_CTRLC_DATA32B_Msk    (_U_(0x3) << SERCOM_USART_EXT_CTRLC_DATA32B_Pos)     /**< (SERCOM_USART_EXT_CTRLC) Data 32 Bit Mask */
+#define SERCOM_USART_EXT_CTRLC_DATA32B(value) (SERCOM_USART_EXT_CTRLC_DATA32B_Msk & ((value) << SERCOM_USART_EXT_CTRLC_DATA32B_Pos))
+#define   SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_WRITE_CHSIZE_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLC) Data reads and writes according CTRLB.CHSIZE  */
+#define   SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_CHSIZE_WRITE_32BIT_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLC) Data reads according CTRLB.CHSIZE and writes according 32-bit extension  */
+#define   SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_32BIT_WRITE_CHSIZE_Val _U_(0x2)                                             /**< (SERCOM_USART_EXT_CTRLC) Data reads according 32-bit extension and writes according CTRLB.CHSIZE  */
+#define   SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_WRITE_32BIT_Val _U_(0x3)                                             /**< (SERCOM_USART_EXT_CTRLC) Data reads and writes according 32-bit extension  */
+#define SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_WRITE_CHSIZE (SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_WRITE_CHSIZE_Val << SERCOM_USART_EXT_CTRLC_DATA32B_Pos) /**< (SERCOM_USART_EXT_CTRLC) Data reads and writes according CTRLB.CHSIZE Position  */
+#define SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_CHSIZE_WRITE_32BIT (SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_CHSIZE_WRITE_32BIT_Val << SERCOM_USART_EXT_CTRLC_DATA32B_Pos) /**< (SERCOM_USART_EXT_CTRLC) Data reads according CTRLB.CHSIZE and writes according 32-bit extension Position  */
+#define SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_32BIT_WRITE_CHSIZE (SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_32BIT_WRITE_CHSIZE_Val << SERCOM_USART_EXT_CTRLC_DATA32B_Pos) /**< (SERCOM_USART_EXT_CTRLC) Data reads according 32-bit extension and writes according CTRLB.CHSIZE Position  */
+#define SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_WRITE_32BIT (SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_WRITE_32BIT_Val << SERCOM_USART_EXT_CTRLC_DATA32B_Pos) /**< (SERCOM_USART_EXT_CTRLC) Data reads and writes according 32-bit extension Position  */
+#define SERCOM_USART_EXT_CTRLC_Msk            _U_(0x03730F07)                                      /**< (SERCOM_USART_EXT_CTRLC) Register Mask  */
+
+
+/* -------- SERCOM_USART_INT_CTRLC : (SERCOM Offset: 0x08) (R/W 32) USART_INT Control C -------- */
+#define SERCOM_USART_INT_CTRLC_RESETVALUE     _U_(0x00)                                            /**<  (SERCOM_USART_INT_CTRLC) USART_INT Control C  Reset Value */
+
+#define SERCOM_USART_INT_CTRLC_GTIME_Pos      _U_(0)                                               /**< (SERCOM_USART_INT_CTRLC) Guard Time Position */
+#define SERCOM_USART_INT_CTRLC_GTIME_Msk      (_U_(0x7) << SERCOM_USART_INT_CTRLC_GTIME_Pos)       /**< (SERCOM_USART_INT_CTRLC) Guard Time Mask */
+#define SERCOM_USART_INT_CTRLC_GTIME(value)   (SERCOM_USART_INT_CTRLC_GTIME_Msk & ((value) << SERCOM_USART_INT_CTRLC_GTIME_Pos))
+#define SERCOM_USART_INT_CTRLC_BRKLEN_Pos     _U_(8)                                               /**< (SERCOM_USART_INT_CTRLC) LIN Master Break Length Position */
+#define SERCOM_USART_INT_CTRLC_BRKLEN_Msk     (_U_(0x3) << SERCOM_USART_INT_CTRLC_BRKLEN_Pos)      /**< (SERCOM_USART_INT_CTRLC) LIN Master Break Length Mask */
+#define SERCOM_USART_INT_CTRLC_BRKLEN(value)  (SERCOM_USART_INT_CTRLC_BRKLEN_Msk & ((value) << SERCOM_USART_INT_CTRLC_BRKLEN_Pos))
+#define   SERCOM_USART_INT_CTRLC_BRKLEN_13_BIT_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLC) Break field transmission is 13 bit times  */
+#define   SERCOM_USART_INT_CTRLC_BRKLEN_17_BIT_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLC) Break field transmission is 17 bit times  */
+#define   SERCOM_USART_INT_CTRLC_BRKLEN_21_BIT_Val _U_(0x2)                                             /**< (SERCOM_USART_INT_CTRLC) Break field transmission is 21 bit times  */
+#define   SERCOM_USART_INT_CTRLC_BRKLEN_26_BIT_Val _U_(0x3)                                             /**< (SERCOM_USART_INT_CTRLC) Break field transmission is 26 bit times  */
+#define SERCOM_USART_INT_CTRLC_BRKLEN_13_BIT  (SERCOM_USART_INT_CTRLC_BRKLEN_13_BIT_Val << SERCOM_USART_INT_CTRLC_BRKLEN_Pos) /**< (SERCOM_USART_INT_CTRLC) Break field transmission is 13 bit times Position  */
+#define SERCOM_USART_INT_CTRLC_BRKLEN_17_BIT  (SERCOM_USART_INT_CTRLC_BRKLEN_17_BIT_Val << SERCOM_USART_INT_CTRLC_BRKLEN_Pos) /**< (SERCOM_USART_INT_CTRLC) Break field transmission is 17 bit times Position  */
+#define SERCOM_USART_INT_CTRLC_BRKLEN_21_BIT  (SERCOM_USART_INT_CTRLC_BRKLEN_21_BIT_Val << SERCOM_USART_INT_CTRLC_BRKLEN_Pos) /**< (SERCOM_USART_INT_CTRLC) Break field transmission is 21 bit times Position  */
+#define SERCOM_USART_INT_CTRLC_BRKLEN_26_BIT  (SERCOM_USART_INT_CTRLC_BRKLEN_26_BIT_Val << SERCOM_USART_INT_CTRLC_BRKLEN_Pos) /**< (SERCOM_USART_INT_CTRLC) Break field transmission is 26 bit times Position  */
+#define SERCOM_USART_INT_CTRLC_HDRDLY_Pos     _U_(10)                                              /**< (SERCOM_USART_INT_CTRLC) LIN Master Header Delay Position */
+#define SERCOM_USART_INT_CTRLC_HDRDLY_Msk     (_U_(0x3) << SERCOM_USART_INT_CTRLC_HDRDLY_Pos)      /**< (SERCOM_USART_INT_CTRLC) LIN Master Header Delay Mask */
+#define SERCOM_USART_INT_CTRLC_HDRDLY(value)  (SERCOM_USART_INT_CTRLC_HDRDLY_Msk & ((value) << SERCOM_USART_INT_CTRLC_HDRDLY_Pos))
+#define   SERCOM_USART_INT_CTRLC_HDRDLY_DELAY0_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLC) Delay between break and sync transmission is 1 bit time; Delay between sync and ID transmission is 1 bit time  */
+#define   SERCOM_USART_INT_CTRLC_HDRDLY_DELAY1_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLC) Delay between break and sync transmission is 4 bit time; Delay between sync and ID transmission is 4 bit time  */
+#define   SERCOM_USART_INT_CTRLC_HDRDLY_DELAY2_Val _U_(0x2)                                             /**< (SERCOM_USART_INT_CTRLC) Delay between break and sync transmission is 8 bit time; Delay between sync and ID transmission is 4 bit time  */
+#define   SERCOM_USART_INT_CTRLC_HDRDLY_DELAY3_Val _U_(0x3)                                             /**< (SERCOM_USART_INT_CTRLC) Delay between break and sync transmission is 14 bit time; Delay between sync and ID transmission is 4 bit time  */
+#define SERCOM_USART_INT_CTRLC_HDRDLY_DELAY0  (SERCOM_USART_INT_CTRLC_HDRDLY_DELAY0_Val << SERCOM_USART_INT_CTRLC_HDRDLY_Pos) /**< (SERCOM_USART_INT_CTRLC) Delay between break and sync transmission is 1 bit time; Delay between sync and ID transmission is 1 bit time Position  */
+#define SERCOM_USART_INT_CTRLC_HDRDLY_DELAY1  (SERCOM_USART_INT_CTRLC_HDRDLY_DELAY1_Val << SERCOM_USART_INT_CTRLC_HDRDLY_Pos) /**< (SERCOM_USART_INT_CTRLC) Delay between break and sync transmission is 4 bit time; Delay between sync and ID transmission is 4 bit time Position  */
+#define SERCOM_USART_INT_CTRLC_HDRDLY_DELAY2  (SERCOM_USART_INT_CTRLC_HDRDLY_DELAY2_Val << SERCOM_USART_INT_CTRLC_HDRDLY_Pos) /**< (SERCOM_USART_INT_CTRLC) Delay between break and sync transmission is 8 bit time; Delay between sync and ID transmission is 4 bit time Position  */
+#define SERCOM_USART_INT_CTRLC_HDRDLY_DELAY3  (SERCOM_USART_INT_CTRLC_HDRDLY_DELAY3_Val << SERCOM_USART_INT_CTRLC_HDRDLY_Pos) /**< (SERCOM_USART_INT_CTRLC) Delay between break and sync transmission is 14 bit time; Delay between sync and ID transmission is 4 bit time Position  */
+#define SERCOM_USART_INT_CTRLC_INACK_Pos      _U_(16)                                              /**< (SERCOM_USART_INT_CTRLC) Inhibit Not Acknowledge Position */
+#define SERCOM_USART_INT_CTRLC_INACK_Msk      (_U_(0x1) << SERCOM_USART_INT_CTRLC_INACK_Pos)       /**< (SERCOM_USART_INT_CTRLC) Inhibit Not Acknowledge Mask */
+#define SERCOM_USART_INT_CTRLC_INACK(value)   (SERCOM_USART_INT_CTRLC_INACK_Msk & ((value) << SERCOM_USART_INT_CTRLC_INACK_Pos))
+#define SERCOM_USART_INT_CTRLC_DSNACK_Pos     _U_(17)                                              /**< (SERCOM_USART_INT_CTRLC) Disable Successive NACK Position */
+#define SERCOM_USART_INT_CTRLC_DSNACK_Msk     (_U_(0x1) << SERCOM_USART_INT_CTRLC_DSNACK_Pos)      /**< (SERCOM_USART_INT_CTRLC) Disable Successive NACK Mask */
+#define SERCOM_USART_INT_CTRLC_DSNACK(value)  (SERCOM_USART_INT_CTRLC_DSNACK_Msk & ((value) << SERCOM_USART_INT_CTRLC_DSNACK_Pos))
+#define SERCOM_USART_INT_CTRLC_MAXITER_Pos    _U_(20)                                              /**< (SERCOM_USART_INT_CTRLC) Maximum Iterations Position */
+#define SERCOM_USART_INT_CTRLC_MAXITER_Msk    (_U_(0x7) << SERCOM_USART_INT_CTRLC_MAXITER_Pos)     /**< (SERCOM_USART_INT_CTRLC) Maximum Iterations Mask */
+#define SERCOM_USART_INT_CTRLC_MAXITER(value) (SERCOM_USART_INT_CTRLC_MAXITER_Msk & ((value) << SERCOM_USART_INT_CTRLC_MAXITER_Pos))
+#define SERCOM_USART_INT_CTRLC_DATA32B_Pos    _U_(24)                                              /**< (SERCOM_USART_INT_CTRLC) Data 32 Bit Position */
+#define SERCOM_USART_INT_CTRLC_DATA32B_Msk    (_U_(0x3) << SERCOM_USART_INT_CTRLC_DATA32B_Pos)     /**< (SERCOM_USART_INT_CTRLC) Data 32 Bit Mask */
+#define SERCOM_USART_INT_CTRLC_DATA32B(value) (SERCOM_USART_INT_CTRLC_DATA32B_Msk & ((value) << SERCOM_USART_INT_CTRLC_DATA32B_Pos))
+#define   SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_WRITE_CHSIZE_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLC) Data reads and writes according CTRLB.CHSIZE  */
+#define   SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_CHSIZE_WRITE_32BIT_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLC) Data reads according CTRLB.CHSIZE and writes according 32-bit extension  */
+#define   SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_32BIT_WRITE_CHSIZE_Val _U_(0x2)                                             /**< (SERCOM_USART_INT_CTRLC) Data reads according 32-bit extension and writes according CTRLB.CHSIZE  */
+#define   SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_WRITE_32BIT_Val _U_(0x3)                                             /**< (SERCOM_USART_INT_CTRLC) Data reads and writes according 32-bit extension  */
+#define SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_WRITE_CHSIZE (SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_WRITE_CHSIZE_Val << SERCOM_USART_INT_CTRLC_DATA32B_Pos) /**< (SERCOM_USART_INT_CTRLC) Data reads and writes according CTRLB.CHSIZE Position  */
+#define SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_CHSIZE_WRITE_32BIT (SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_CHSIZE_WRITE_32BIT_Val << SERCOM_USART_INT_CTRLC_DATA32B_Pos) /**< (SERCOM_USART_INT_CTRLC) Data reads according CTRLB.CHSIZE and writes according 32-bit extension Position  */
+#define SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_32BIT_WRITE_CHSIZE (SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_32BIT_WRITE_CHSIZE_Val << SERCOM_USART_INT_CTRLC_DATA32B_Pos) /**< (SERCOM_USART_INT_CTRLC) Data reads according 32-bit extension and writes according CTRLB.CHSIZE Position  */
+#define SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_WRITE_32BIT (SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_WRITE_32BIT_Val << SERCOM_USART_INT_CTRLC_DATA32B_Pos) /**< (SERCOM_USART_INT_CTRLC) Data reads and writes according 32-bit extension Position  */
+#define SERCOM_USART_INT_CTRLC_Msk            _U_(0x03730F07)                                      /**< (SERCOM_USART_INT_CTRLC) Register Mask  */
+
+
+/* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM Baud Rate -------- */
+#define SERCOM_I2CM_BAUD_RESETVALUE           _U_(0x00)                                            /**<  (SERCOM_I2CM_BAUD) I2CM Baud Rate  Reset Value */
+
+#define SERCOM_I2CM_BAUD_BAUD_Pos             _U_(0)                                               /**< (SERCOM_I2CM_BAUD) Baud Rate Value Position */
+#define SERCOM_I2CM_BAUD_BAUD_Msk             (_U_(0xFF) << SERCOM_I2CM_BAUD_BAUD_Pos)             /**< (SERCOM_I2CM_BAUD) Baud Rate Value Mask */
+#define SERCOM_I2CM_BAUD_BAUD(value)          (SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos))
+#define SERCOM_I2CM_BAUD_BAUDLOW_Pos          _U_(8)                                               /**< (SERCOM_I2CM_BAUD) Baud Rate Value Low Position */
+#define SERCOM_I2CM_BAUD_BAUDLOW_Msk          (_U_(0xFF) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)          /**< (SERCOM_I2CM_BAUD) Baud Rate Value Low Mask */
+#define SERCOM_I2CM_BAUD_BAUDLOW(value)       (SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos))
+#define SERCOM_I2CM_BAUD_HSBAUD_Pos           _U_(16)                                              /**< (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Position */
+#define SERCOM_I2CM_BAUD_HSBAUD_Msk           (_U_(0xFF) << SERCOM_I2CM_BAUD_HSBAUD_Pos)           /**< (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Mask */
+#define SERCOM_I2CM_BAUD_HSBAUD(value)        (SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos))
+#define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos        _U_(24)                                              /**< (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low Position */
+#define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk        (_U_(0xFF) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)        /**< (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low Mask */
+#define SERCOM_I2CM_BAUD_HSBAUDLOW(value)     (SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos))
+#define SERCOM_I2CM_BAUD_Msk                  _U_(0xFFFFFFFF)                                      /**< (SERCOM_I2CM_BAUD) Register Mask  */
+
+
+/* -------- SERCOM_SPIM_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPIM Baud Rate -------- */
+#define SERCOM_SPIM_BAUD_RESETVALUE           _U_(0x00)                                            /**<  (SERCOM_SPIM_BAUD) SPIM Baud Rate  Reset Value */
+
+#define SERCOM_SPIM_BAUD_BAUD_Pos             _U_(0)                                               /**< (SERCOM_SPIM_BAUD) Baud Rate Value Position */
+#define SERCOM_SPIM_BAUD_BAUD_Msk             (_U_(0xFF) << SERCOM_SPIM_BAUD_BAUD_Pos)             /**< (SERCOM_SPIM_BAUD) Baud Rate Value Mask */
+#define SERCOM_SPIM_BAUD_BAUD(value)          (SERCOM_SPIM_BAUD_BAUD_Msk & ((value) << SERCOM_SPIM_BAUD_BAUD_Pos))
+#define SERCOM_SPIM_BAUD_Msk                  _U_(0xFF)                                            /**< (SERCOM_SPIM_BAUD) Register Mask  */
+
+
+/* -------- SERCOM_SPIS_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPIS Baud Rate -------- */
+#define SERCOM_SPIS_BAUD_RESETVALUE           _U_(0x00)                                            /**<  (SERCOM_SPIS_BAUD) SPIS Baud Rate  Reset Value */
+
+#define SERCOM_SPIS_BAUD_BAUD_Pos             _U_(0)                                               /**< (SERCOM_SPIS_BAUD) Baud Rate Value Position */
+#define SERCOM_SPIS_BAUD_BAUD_Msk             (_U_(0xFF) << SERCOM_SPIS_BAUD_BAUD_Pos)             /**< (SERCOM_SPIS_BAUD) Baud Rate Value Mask */
+#define SERCOM_SPIS_BAUD_BAUD(value)          (SERCOM_SPIS_BAUD_BAUD_Msk & ((value) << SERCOM_SPIS_BAUD_BAUD_Pos))
+#define SERCOM_SPIS_BAUD_Msk                  _U_(0xFF)                                            /**< (SERCOM_SPIS_BAUD) Register Mask  */
+
+
+/* -------- SERCOM_USART_EXT_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART_EXT Baud Rate -------- */
+#define SERCOM_USART_EXT_BAUD_RESETVALUE      _U_(0x00)                                            /**<  (SERCOM_USART_EXT_BAUD) USART_EXT Baud Rate  Reset Value */
+
+#define SERCOM_USART_EXT_BAUD_BAUD_Pos        _U_(0)                                               /**< (SERCOM_USART_EXT_BAUD) Baud Rate Value Position */
+#define SERCOM_USART_EXT_BAUD_BAUD_Msk        (_U_(0xFFFF) << SERCOM_USART_EXT_BAUD_BAUD_Pos)      /**< (SERCOM_USART_EXT_BAUD) Baud Rate Value Mask */
+#define SERCOM_USART_EXT_BAUD_BAUD(value)     (SERCOM_USART_EXT_BAUD_BAUD_Msk & ((value) << SERCOM_USART_EXT_BAUD_BAUD_Pos))
+#define SERCOM_USART_EXT_BAUD_Msk             _U_(0xFFFF)                                          /**< (SERCOM_USART_EXT_BAUD) Register Mask  */
+
+/* FRAC mode */
+#define SERCOM_USART_EXT_BAUD_FRAC_BAUD_Pos   _U_(0)                                               /**< (SERCOM_USART_EXT_BAUD) Baud Rate Value Position */
+#define SERCOM_USART_EXT_BAUD_FRAC_BAUD_Msk   (_U_(0x1FFF) << SERCOM_USART_EXT_BAUD_FRAC_BAUD_Pos) /**< (SERCOM_USART_EXT_BAUD) Baud Rate Value Mask */
+#define SERCOM_USART_EXT_BAUD_FRAC_BAUD(value) (SERCOM_USART_EXT_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_EXT_BAUD_FRAC_BAUD_Pos))
+#define SERCOM_USART_EXT_BAUD_FRAC_FP_Pos     _U_(13)                                              /**< (SERCOM_USART_EXT_BAUD) Fractional Part Position */
+#define SERCOM_USART_EXT_BAUD_FRAC_FP_Msk     (_U_(0x7) << SERCOM_USART_EXT_BAUD_FRAC_FP_Pos)      /**< (SERCOM_USART_EXT_BAUD) Fractional Part Mask */
+#define SERCOM_USART_EXT_BAUD_FRAC_FP(value)  (SERCOM_USART_EXT_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_EXT_BAUD_FRAC_FP_Pos))
+#define SERCOM_USART_EXT_BAUD_FRAC_Msk        _U_(0xFFFF)                                           /**< (SERCOM_USART_EXT_BAUD_FRAC) Register Mask  */
+
+/* FRACFP mode */
+#define SERCOM_USART_EXT_BAUD_FRACFP_BAUD_Pos _U_(0)                                               /**< (SERCOM_USART_EXT_BAUD) Baud Rate Value Position */
+#define SERCOM_USART_EXT_BAUD_FRACFP_BAUD_Msk (_U_(0x1FFF) << SERCOM_USART_EXT_BAUD_FRACFP_BAUD_Pos) /**< (SERCOM_USART_EXT_BAUD) Baud Rate Value Mask */
+#define SERCOM_USART_EXT_BAUD_FRACFP_BAUD(value) (SERCOM_USART_EXT_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_EXT_BAUD_FRACFP_BAUD_Pos))
+#define SERCOM_USART_EXT_BAUD_FRACFP_FP_Pos   _U_(13)                                              /**< (SERCOM_USART_EXT_BAUD) Fractional Part Position */
+#define SERCOM_USART_EXT_BAUD_FRACFP_FP_Msk   (_U_(0x7) << SERCOM_USART_EXT_BAUD_FRACFP_FP_Pos)    /**< (SERCOM_USART_EXT_BAUD) Fractional Part Mask */
+#define SERCOM_USART_EXT_BAUD_FRACFP_FP(value) (SERCOM_USART_EXT_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_EXT_BAUD_FRACFP_FP_Pos))
+#define SERCOM_USART_EXT_BAUD_FRACFP_Msk      _U_(0xFFFF)                                           /**< (SERCOM_USART_EXT_BAUD_FRACFP) Register Mask  */
+
+/* USARTFP mode */
+#define SERCOM_USART_EXT_BAUD_USARTFP_BAUD_Pos _U_(0)                                               /**< (SERCOM_USART_EXT_BAUD) Baud Rate Value Position */
+#define SERCOM_USART_EXT_BAUD_USARTFP_BAUD_Msk (_U_(0xFFFF) << SERCOM_USART_EXT_BAUD_USARTFP_BAUD_Pos) /**< (SERCOM_USART_EXT_BAUD) Baud Rate Value Mask */
+#define SERCOM_USART_EXT_BAUD_USARTFP_BAUD(value) (SERCOM_USART_EXT_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_EXT_BAUD_USARTFP_BAUD_Pos))
+#define SERCOM_USART_EXT_BAUD_USARTFP_Msk     _U_(0xFFFF)                                           /**< (SERCOM_USART_EXT_BAUD_USARTFP) Register Mask  */
+
+
+/* -------- SERCOM_USART_INT_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART_INT Baud Rate -------- */
+#define SERCOM_USART_INT_BAUD_RESETVALUE      _U_(0x00)                                            /**<  (SERCOM_USART_INT_BAUD) USART_INT Baud Rate  Reset Value */
+
+#define SERCOM_USART_INT_BAUD_BAUD_Pos        _U_(0)                                               /**< (SERCOM_USART_INT_BAUD) Baud Rate Value Position */
+#define SERCOM_USART_INT_BAUD_BAUD_Msk        (_U_(0xFFFF) << SERCOM_USART_INT_BAUD_BAUD_Pos)      /**< (SERCOM_USART_INT_BAUD) Baud Rate Value Mask */
+#define SERCOM_USART_INT_BAUD_BAUD(value)     (SERCOM_USART_INT_BAUD_BAUD_Msk & ((value) << SERCOM_USART_INT_BAUD_BAUD_Pos))
+#define SERCOM_USART_INT_BAUD_Msk             _U_(0xFFFF)                                          /**< (SERCOM_USART_INT_BAUD) Register Mask  */
+
+/* FRAC mode */
+#define SERCOM_USART_INT_BAUD_FRAC_BAUD_Pos   _U_(0)                                               /**< (SERCOM_USART_INT_BAUD) Baud Rate Value Position */
+#define SERCOM_USART_INT_BAUD_FRAC_BAUD_Msk   (_U_(0x1FFF) << SERCOM_USART_INT_BAUD_FRAC_BAUD_Pos) /**< (SERCOM_USART_INT_BAUD) Baud Rate Value Mask */
+#define SERCOM_USART_INT_BAUD_FRAC_BAUD(value) (SERCOM_USART_INT_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_INT_BAUD_FRAC_BAUD_Pos))
+#define SERCOM_USART_INT_BAUD_FRAC_FP_Pos     _U_(13)                                              /**< (SERCOM_USART_INT_BAUD) Fractional Part Position */
+#define SERCOM_USART_INT_BAUD_FRAC_FP_Msk     (_U_(0x7) << SERCOM_USART_INT_BAUD_FRAC_FP_Pos)      /**< (SERCOM_USART_INT_BAUD) Fractional Part Mask */
+#define SERCOM_USART_INT_BAUD_FRAC_FP(value)  (SERCOM_USART_INT_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_INT_BAUD_FRAC_FP_Pos))
+#define SERCOM_USART_INT_BAUD_FRAC_Msk        _U_(0xFFFF)                                           /**< (SERCOM_USART_INT_BAUD_FRAC) Register Mask  */
+
+/* FRACFP mode */
+#define SERCOM_USART_INT_BAUD_FRACFP_BAUD_Pos _U_(0)                                               /**< (SERCOM_USART_INT_BAUD) Baud Rate Value Position */
+#define SERCOM_USART_INT_BAUD_FRACFP_BAUD_Msk (_U_(0x1FFF) << SERCOM_USART_INT_BAUD_FRACFP_BAUD_Pos) /**< (SERCOM_USART_INT_BAUD) Baud Rate Value Mask */
+#define SERCOM_USART_INT_BAUD_FRACFP_BAUD(value) (SERCOM_USART_INT_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_INT_BAUD_FRACFP_BAUD_Pos))
+#define SERCOM_USART_INT_BAUD_FRACFP_FP_Pos   _U_(13)                                              /**< (SERCOM_USART_INT_BAUD) Fractional Part Position */
+#define SERCOM_USART_INT_BAUD_FRACFP_FP_Msk   (_U_(0x7) << SERCOM_USART_INT_BAUD_FRACFP_FP_Pos)    /**< (SERCOM_USART_INT_BAUD) Fractional Part Mask */
+#define SERCOM_USART_INT_BAUD_FRACFP_FP(value) (SERCOM_USART_INT_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_INT_BAUD_FRACFP_FP_Pos))
+#define SERCOM_USART_INT_BAUD_FRACFP_Msk      _U_(0xFFFF)                                           /**< (SERCOM_USART_INT_BAUD_FRACFP) Register Mask  */
+
+/* USARTFP mode */
+#define SERCOM_USART_INT_BAUD_USARTFP_BAUD_Pos _U_(0)                                               /**< (SERCOM_USART_INT_BAUD) Baud Rate Value Position */
+#define SERCOM_USART_INT_BAUD_USARTFP_BAUD_Msk (_U_(0xFFFF) << SERCOM_USART_INT_BAUD_USARTFP_BAUD_Pos) /**< (SERCOM_USART_INT_BAUD) Baud Rate Value Mask */
+#define SERCOM_USART_INT_BAUD_USARTFP_BAUD(value) (SERCOM_USART_INT_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_INT_BAUD_USARTFP_BAUD_Pos))
+#define SERCOM_USART_INT_BAUD_USARTFP_Msk     _U_(0xFFFF)                                           /**< (SERCOM_USART_INT_BAUD_USARTFP) Register Mask  */
+
+
+/* -------- SERCOM_USART_EXT_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART_EXT Receive Pulse Length -------- */
+#define SERCOM_USART_EXT_RXPL_RESETVALUE      _U_(0x00)                                            /**<  (SERCOM_USART_EXT_RXPL) USART_EXT Receive Pulse Length  Reset Value */
+
+#define SERCOM_USART_EXT_RXPL_RXPL_Pos        _U_(0)                                               /**< (SERCOM_USART_EXT_RXPL) Receive Pulse Length Position */
+#define SERCOM_USART_EXT_RXPL_RXPL_Msk        (_U_(0xFF) << SERCOM_USART_EXT_RXPL_RXPL_Pos)        /**< (SERCOM_USART_EXT_RXPL) Receive Pulse Length Mask */
+#define SERCOM_USART_EXT_RXPL_RXPL(value)     (SERCOM_USART_EXT_RXPL_RXPL_Msk & ((value) << SERCOM_USART_EXT_RXPL_RXPL_Pos))
+#define SERCOM_USART_EXT_RXPL_Msk             _U_(0xFF)                                            /**< (SERCOM_USART_EXT_RXPL) Register Mask  */
+
+
+/* -------- SERCOM_USART_INT_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART_INT Receive Pulse Length -------- */
+#define SERCOM_USART_INT_RXPL_RESETVALUE      _U_(0x00)                                            /**<  (SERCOM_USART_INT_RXPL) USART_INT Receive Pulse Length  Reset Value */
+
+#define SERCOM_USART_INT_RXPL_RXPL_Pos        _U_(0)                                               /**< (SERCOM_USART_INT_RXPL) Receive Pulse Length Position */
+#define SERCOM_USART_INT_RXPL_RXPL_Msk        (_U_(0xFF) << SERCOM_USART_INT_RXPL_RXPL_Pos)        /**< (SERCOM_USART_INT_RXPL) Receive Pulse Length Mask */
+#define SERCOM_USART_INT_RXPL_RXPL(value)     (SERCOM_USART_INT_RXPL_RXPL_Msk & ((value) << SERCOM_USART_INT_RXPL_RXPL_Pos))
+#define SERCOM_USART_INT_RXPL_Msk             _U_(0xFF)                                            /**< (SERCOM_USART_INT_RXPL) Register Mask  */
+
+
+/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM Interrupt Enable Clear -------- */
+#define SERCOM_I2CM_INTENCLR_RESETVALUE       _U_(0x00)                                            /**<  (SERCOM_I2CM_INTENCLR) I2CM Interrupt Enable Clear  Reset Value */
+
+#define SERCOM_I2CM_INTENCLR_MB_Pos           _U_(0)                                               /**< (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable Position */
+#define SERCOM_I2CM_INTENCLR_MB_Msk           (_U_(0x1) << SERCOM_I2CM_INTENCLR_MB_Pos)            /**< (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable Mask */
+#define SERCOM_I2CM_INTENCLR_MB(value)        (SERCOM_I2CM_INTENCLR_MB_Msk & ((value) << SERCOM_I2CM_INTENCLR_MB_Pos))
+#define SERCOM_I2CM_INTENCLR_SB_Pos           _U_(1)                                               /**< (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable Position */
+#define SERCOM_I2CM_INTENCLR_SB_Msk           (_U_(0x1) << SERCOM_I2CM_INTENCLR_SB_Pos)            /**< (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable Mask */
+#define SERCOM_I2CM_INTENCLR_SB(value)        (SERCOM_I2CM_INTENCLR_SB_Msk & ((value) << SERCOM_I2CM_INTENCLR_SB_Pos))
+#define SERCOM_I2CM_INTENCLR_ERROR_Pos        _U_(7)                                               /**< (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable Position */
+#define SERCOM_I2CM_INTENCLR_ERROR_Msk        (_U_(0x1) << SERCOM_I2CM_INTENCLR_ERROR_Pos)         /**< (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable Mask */
+#define SERCOM_I2CM_INTENCLR_ERROR(value)     (SERCOM_I2CM_INTENCLR_ERROR_Msk & ((value) << SERCOM_I2CM_INTENCLR_ERROR_Pos))
+#define SERCOM_I2CM_INTENCLR_Msk              _U_(0x83)                                            /**< (SERCOM_I2CM_INTENCLR) Register Mask  */
+
+
+/* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS Interrupt Enable Clear -------- */
+#define SERCOM_I2CS_INTENCLR_RESETVALUE       _U_(0x00)                                            /**<  (SERCOM_I2CS_INTENCLR) I2CS Interrupt Enable Clear  Reset Value */
+
+#define SERCOM_I2CS_INTENCLR_PREC_Pos         _U_(0)                                               /**< (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable Position */
+#define SERCOM_I2CS_INTENCLR_PREC_Msk         (_U_(0x1) << SERCOM_I2CS_INTENCLR_PREC_Pos)          /**< (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable Mask */
+#define SERCOM_I2CS_INTENCLR_PREC(value)      (SERCOM_I2CS_INTENCLR_PREC_Msk & ((value) << SERCOM_I2CS_INTENCLR_PREC_Pos))
+#define SERCOM_I2CS_INTENCLR_AMATCH_Pos       _U_(1)                                               /**< (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable Position */
+#define SERCOM_I2CS_INTENCLR_AMATCH_Msk       (_U_(0x1) << SERCOM_I2CS_INTENCLR_AMATCH_Pos)        /**< (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable Mask */
+#define SERCOM_I2CS_INTENCLR_AMATCH(value)    (SERCOM_I2CS_INTENCLR_AMATCH_Msk & ((value) << SERCOM_I2CS_INTENCLR_AMATCH_Pos))
+#define SERCOM_I2CS_INTENCLR_DRDY_Pos         _U_(2)                                               /**< (SERCOM_I2CS_INTENCLR) Data Interrupt Disable Position */
+#define SERCOM_I2CS_INTENCLR_DRDY_Msk         (_U_(0x1) << SERCOM_I2CS_INTENCLR_DRDY_Pos)          /**< (SERCOM_I2CS_INTENCLR) Data Interrupt Disable Mask */
+#define SERCOM_I2CS_INTENCLR_DRDY(value)      (SERCOM_I2CS_INTENCLR_DRDY_Msk & ((value) << SERCOM_I2CS_INTENCLR_DRDY_Pos))
+#define SERCOM_I2CS_INTENCLR_ERROR_Pos        _U_(7)                                               /**< (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable Position */
+#define SERCOM_I2CS_INTENCLR_ERROR_Msk        (_U_(0x1) << SERCOM_I2CS_INTENCLR_ERROR_Pos)         /**< (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable Mask */
+#define SERCOM_I2CS_INTENCLR_ERROR(value)     (SERCOM_I2CS_INTENCLR_ERROR_Msk & ((value) << SERCOM_I2CS_INTENCLR_ERROR_Pos))
+#define SERCOM_I2CS_INTENCLR_Msk              _U_(0x87)                                            /**< (SERCOM_I2CS_INTENCLR) Register Mask  */
+
+
+/* -------- SERCOM_SPIM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPIM Interrupt Enable Clear -------- */
+#define SERCOM_SPIM_INTENCLR_RESETVALUE       _U_(0x00)                                            /**<  (SERCOM_SPIM_INTENCLR) SPIM Interrupt Enable Clear  Reset Value */
+
+#define SERCOM_SPIM_INTENCLR_DRE_Pos          _U_(0)                                               /**< (SERCOM_SPIM_INTENCLR) Data Register Empty Interrupt Disable Position */
+#define SERCOM_SPIM_INTENCLR_DRE_Msk          (_U_(0x1) << SERCOM_SPIM_INTENCLR_DRE_Pos)           /**< (SERCOM_SPIM_INTENCLR) Data Register Empty Interrupt Disable Mask */
+#define SERCOM_SPIM_INTENCLR_DRE(value)       (SERCOM_SPIM_INTENCLR_DRE_Msk & ((value) << SERCOM_SPIM_INTENCLR_DRE_Pos))
+#define SERCOM_SPIM_INTENCLR_TXC_Pos          _U_(1)                                               /**< (SERCOM_SPIM_INTENCLR) Transmit Complete Interrupt Disable Position */
+#define SERCOM_SPIM_INTENCLR_TXC_Msk          (_U_(0x1) << SERCOM_SPIM_INTENCLR_TXC_Pos)           /**< (SERCOM_SPIM_INTENCLR) Transmit Complete Interrupt Disable Mask */
+#define SERCOM_SPIM_INTENCLR_TXC(value)       (SERCOM_SPIM_INTENCLR_TXC_Msk & ((value) << SERCOM_SPIM_INTENCLR_TXC_Pos))
+#define SERCOM_SPIM_INTENCLR_RXC_Pos          _U_(2)                                               /**< (SERCOM_SPIM_INTENCLR) Receive Complete Interrupt Disable Position */
+#define SERCOM_SPIM_INTENCLR_RXC_Msk          (_U_(0x1) << SERCOM_SPIM_INTENCLR_RXC_Pos)           /**< (SERCOM_SPIM_INTENCLR) Receive Complete Interrupt Disable Mask */
+#define SERCOM_SPIM_INTENCLR_RXC(value)       (SERCOM_SPIM_INTENCLR_RXC_Msk & ((value) << SERCOM_SPIM_INTENCLR_RXC_Pos))
+#define SERCOM_SPIM_INTENCLR_SSL_Pos          _U_(3)                                               /**< (SERCOM_SPIM_INTENCLR) Slave Select Low Interrupt Disable Position */
+#define SERCOM_SPIM_INTENCLR_SSL_Msk          (_U_(0x1) << SERCOM_SPIM_INTENCLR_SSL_Pos)           /**< (SERCOM_SPIM_INTENCLR) Slave Select Low Interrupt Disable Mask */
+#define SERCOM_SPIM_INTENCLR_SSL(value)       (SERCOM_SPIM_INTENCLR_SSL_Msk & ((value) << SERCOM_SPIM_INTENCLR_SSL_Pos))
+#define SERCOM_SPIM_INTENCLR_ERROR_Pos        _U_(7)                                               /**< (SERCOM_SPIM_INTENCLR) Combined Error Interrupt Disable Position */
+#define SERCOM_SPIM_INTENCLR_ERROR_Msk        (_U_(0x1) << SERCOM_SPIM_INTENCLR_ERROR_Pos)         /**< (SERCOM_SPIM_INTENCLR) Combined Error Interrupt Disable Mask */
+#define SERCOM_SPIM_INTENCLR_ERROR(value)     (SERCOM_SPIM_INTENCLR_ERROR_Msk & ((value) << SERCOM_SPIM_INTENCLR_ERROR_Pos))
+#define SERCOM_SPIM_INTENCLR_Msk              _U_(0x8F)                                            /**< (SERCOM_SPIM_INTENCLR) Register Mask  */
+
+
+/* -------- SERCOM_SPIS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPIS Interrupt Enable Clear -------- */
+#define SERCOM_SPIS_INTENCLR_RESETVALUE       _U_(0x00)                                            /**<  (SERCOM_SPIS_INTENCLR) SPIS Interrupt Enable Clear  Reset Value */
+
+#define SERCOM_SPIS_INTENCLR_DRE_Pos          _U_(0)                                               /**< (SERCOM_SPIS_INTENCLR) Data Register Empty Interrupt Disable Position */
+#define SERCOM_SPIS_INTENCLR_DRE_Msk          (_U_(0x1) << SERCOM_SPIS_INTENCLR_DRE_Pos)           /**< (SERCOM_SPIS_INTENCLR) Data Register Empty Interrupt Disable Mask */
+#define SERCOM_SPIS_INTENCLR_DRE(value)       (SERCOM_SPIS_INTENCLR_DRE_Msk & ((value) << SERCOM_SPIS_INTENCLR_DRE_Pos))
+#define SERCOM_SPIS_INTENCLR_TXC_Pos          _U_(1)                                               /**< (SERCOM_SPIS_INTENCLR) Transmit Complete Interrupt Disable Position */
+#define SERCOM_SPIS_INTENCLR_TXC_Msk          (_U_(0x1) << SERCOM_SPIS_INTENCLR_TXC_Pos)           /**< (SERCOM_SPIS_INTENCLR) Transmit Complete Interrupt Disable Mask */
+#define SERCOM_SPIS_INTENCLR_TXC(value)       (SERCOM_SPIS_INTENCLR_TXC_Msk & ((value) << SERCOM_SPIS_INTENCLR_TXC_Pos))
+#define SERCOM_SPIS_INTENCLR_RXC_Pos          _U_(2)                                               /**< (SERCOM_SPIS_INTENCLR) Receive Complete Interrupt Disable Position */
+#define SERCOM_SPIS_INTENCLR_RXC_Msk          (_U_(0x1) << SERCOM_SPIS_INTENCLR_RXC_Pos)           /**< (SERCOM_SPIS_INTENCLR) Receive Complete Interrupt Disable Mask */
+#define SERCOM_SPIS_INTENCLR_RXC(value)       (SERCOM_SPIS_INTENCLR_RXC_Msk & ((value) << SERCOM_SPIS_INTENCLR_RXC_Pos))
+#define SERCOM_SPIS_INTENCLR_SSL_Pos          _U_(3)                                               /**< (SERCOM_SPIS_INTENCLR) Slave Select Low Interrupt Disable Position */
+#define SERCOM_SPIS_INTENCLR_SSL_Msk          (_U_(0x1) << SERCOM_SPIS_INTENCLR_SSL_Pos)           /**< (SERCOM_SPIS_INTENCLR) Slave Select Low Interrupt Disable Mask */
+#define SERCOM_SPIS_INTENCLR_SSL(value)       (SERCOM_SPIS_INTENCLR_SSL_Msk & ((value) << SERCOM_SPIS_INTENCLR_SSL_Pos))
+#define SERCOM_SPIS_INTENCLR_ERROR_Pos        _U_(7)                                               /**< (SERCOM_SPIS_INTENCLR) Combined Error Interrupt Disable Position */
+#define SERCOM_SPIS_INTENCLR_ERROR_Msk        (_U_(0x1) << SERCOM_SPIS_INTENCLR_ERROR_Pos)         /**< (SERCOM_SPIS_INTENCLR) Combined Error Interrupt Disable Mask */
+#define SERCOM_SPIS_INTENCLR_ERROR(value)     (SERCOM_SPIS_INTENCLR_ERROR_Msk & ((value) << SERCOM_SPIS_INTENCLR_ERROR_Pos))
+#define SERCOM_SPIS_INTENCLR_Msk              _U_(0x8F)                                            /**< (SERCOM_SPIS_INTENCLR) Register Mask  */
+
+
+/* -------- SERCOM_USART_EXT_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART_EXT Interrupt Enable Clear -------- */
+#define SERCOM_USART_EXT_INTENCLR_RESETVALUE  _U_(0x00)                                            /**<  (SERCOM_USART_EXT_INTENCLR) USART_EXT Interrupt Enable Clear  Reset Value */
+
+#define SERCOM_USART_EXT_INTENCLR_DRE_Pos     _U_(0)                                               /**< (SERCOM_USART_EXT_INTENCLR) Data Register Empty Interrupt Disable Position */
+#define SERCOM_USART_EXT_INTENCLR_DRE_Msk     (_U_(0x1) << SERCOM_USART_EXT_INTENCLR_DRE_Pos)      /**< (SERCOM_USART_EXT_INTENCLR) Data Register Empty Interrupt Disable Mask */
+#define SERCOM_USART_EXT_INTENCLR_DRE(value)  (SERCOM_USART_EXT_INTENCLR_DRE_Msk & ((value) << SERCOM_USART_EXT_INTENCLR_DRE_Pos))
+#define SERCOM_USART_EXT_INTENCLR_TXC_Pos     _U_(1)                                               /**< (SERCOM_USART_EXT_INTENCLR) Transmit Complete Interrupt Disable Position */
+#define SERCOM_USART_EXT_INTENCLR_TXC_Msk     (_U_(0x1) << SERCOM_USART_EXT_INTENCLR_TXC_Pos)      /**< (SERCOM_USART_EXT_INTENCLR) Transmit Complete Interrupt Disable Mask */
+#define SERCOM_USART_EXT_INTENCLR_TXC(value)  (SERCOM_USART_EXT_INTENCLR_TXC_Msk & ((value) << SERCOM_USART_EXT_INTENCLR_TXC_Pos))
+#define SERCOM_USART_EXT_INTENCLR_RXC_Pos     _U_(2)                                               /**< (SERCOM_USART_EXT_INTENCLR) Receive Complete Interrupt Disable Position */
+#define SERCOM_USART_EXT_INTENCLR_RXC_Msk     (_U_(0x1) << SERCOM_USART_EXT_INTENCLR_RXC_Pos)      /**< (SERCOM_USART_EXT_INTENCLR) Receive Complete Interrupt Disable Mask */
+#define SERCOM_USART_EXT_INTENCLR_RXC(value)  (SERCOM_USART_EXT_INTENCLR_RXC_Msk & ((value) << SERCOM_USART_EXT_INTENCLR_RXC_Pos))
+#define SERCOM_USART_EXT_INTENCLR_RXS_Pos     _U_(3)                                               /**< (SERCOM_USART_EXT_INTENCLR) Receive Start Interrupt Disable Position */
+#define SERCOM_USART_EXT_INTENCLR_RXS_Msk     (_U_(0x1) << SERCOM_USART_EXT_INTENCLR_RXS_Pos)      /**< (SERCOM_USART_EXT_INTENCLR) Receive Start Interrupt Disable Mask */
+#define SERCOM_USART_EXT_INTENCLR_RXS(value)  (SERCOM_USART_EXT_INTENCLR_RXS_Msk & ((value) << SERCOM_USART_EXT_INTENCLR_RXS_Pos))
+#define SERCOM_USART_EXT_INTENCLR_CTSIC_Pos   _U_(4)                                               /**< (SERCOM_USART_EXT_INTENCLR) Clear To Send Input Change Interrupt Disable Position */
+#define SERCOM_USART_EXT_INTENCLR_CTSIC_Msk   (_U_(0x1) << SERCOM_USART_EXT_INTENCLR_CTSIC_Pos)    /**< (SERCOM_USART_EXT_INTENCLR) Clear To Send Input Change Interrupt Disable Mask */
+#define SERCOM_USART_EXT_INTENCLR_CTSIC(value) (SERCOM_USART_EXT_INTENCLR_CTSIC_Msk & ((value) << SERCOM_USART_EXT_INTENCLR_CTSIC_Pos))
+#define SERCOM_USART_EXT_INTENCLR_RXBRK_Pos   _U_(5)                                               /**< (SERCOM_USART_EXT_INTENCLR) Break Received Interrupt Disable Position */
+#define SERCOM_USART_EXT_INTENCLR_RXBRK_Msk   (_U_(0x1) << SERCOM_USART_EXT_INTENCLR_RXBRK_Pos)    /**< (SERCOM_USART_EXT_INTENCLR) Break Received Interrupt Disable Mask */
+#define SERCOM_USART_EXT_INTENCLR_RXBRK(value) (SERCOM_USART_EXT_INTENCLR_RXBRK_Msk & ((value) << SERCOM_USART_EXT_INTENCLR_RXBRK_Pos))
+#define SERCOM_USART_EXT_INTENCLR_ERROR_Pos   _U_(7)                                               /**< (SERCOM_USART_EXT_INTENCLR) Combined Error Interrupt Disable Position */
+#define SERCOM_USART_EXT_INTENCLR_ERROR_Msk   (_U_(0x1) << SERCOM_USART_EXT_INTENCLR_ERROR_Pos)    /**< (SERCOM_USART_EXT_INTENCLR) Combined Error Interrupt Disable Mask */
+#define SERCOM_USART_EXT_INTENCLR_ERROR(value) (SERCOM_USART_EXT_INTENCLR_ERROR_Msk & ((value) << SERCOM_USART_EXT_INTENCLR_ERROR_Pos))
+#define SERCOM_USART_EXT_INTENCLR_Msk         _U_(0xBF)                                            /**< (SERCOM_USART_EXT_INTENCLR) Register Mask  */
+
+
+/* -------- SERCOM_USART_INT_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART_INT Interrupt Enable Clear -------- */
+#define SERCOM_USART_INT_INTENCLR_RESETVALUE  _U_(0x00)                                            /**<  (SERCOM_USART_INT_INTENCLR) USART_INT Interrupt Enable Clear  Reset Value */
+
+#define SERCOM_USART_INT_INTENCLR_DRE_Pos     _U_(0)                                               /**< (SERCOM_USART_INT_INTENCLR) Data Register Empty Interrupt Disable Position */
+#define SERCOM_USART_INT_INTENCLR_DRE_Msk     (_U_(0x1) << SERCOM_USART_INT_INTENCLR_DRE_Pos)      /**< (SERCOM_USART_INT_INTENCLR) Data Register Empty Interrupt Disable Mask */
+#define SERCOM_USART_INT_INTENCLR_DRE(value)  (SERCOM_USART_INT_INTENCLR_DRE_Msk & ((value) << SERCOM_USART_INT_INTENCLR_DRE_Pos))
+#define SERCOM_USART_INT_INTENCLR_TXC_Pos     _U_(1)                                               /**< (SERCOM_USART_INT_INTENCLR) Transmit Complete Interrupt Disable Position */
+#define SERCOM_USART_INT_INTENCLR_TXC_Msk     (_U_(0x1) << SERCOM_USART_INT_INTENCLR_TXC_Pos)      /**< (SERCOM_USART_INT_INTENCLR) Transmit Complete Interrupt Disable Mask */
+#define SERCOM_USART_INT_INTENCLR_TXC(value)  (SERCOM_USART_INT_INTENCLR_TXC_Msk & ((value) << SERCOM_USART_INT_INTENCLR_TXC_Pos))
+#define SERCOM_USART_INT_INTENCLR_RXC_Pos     _U_(2)                                               /**< (SERCOM_USART_INT_INTENCLR) Receive Complete Interrupt Disable Position */
+#define SERCOM_USART_INT_INTENCLR_RXC_Msk     (_U_(0x1) << SERCOM_USART_INT_INTENCLR_RXC_Pos)      /**< (SERCOM_USART_INT_INTENCLR) Receive Complete Interrupt Disable Mask */
+#define SERCOM_USART_INT_INTENCLR_RXC(value)  (SERCOM_USART_INT_INTENCLR_RXC_Msk & ((value) << SERCOM_USART_INT_INTENCLR_RXC_Pos))
+#define SERCOM_USART_INT_INTENCLR_RXS_Pos     _U_(3)                                               /**< (SERCOM_USART_INT_INTENCLR) Receive Start Interrupt Disable Position */
+#define SERCOM_USART_INT_INTENCLR_RXS_Msk     (_U_(0x1) << SERCOM_USART_INT_INTENCLR_RXS_Pos)      /**< (SERCOM_USART_INT_INTENCLR) Receive Start Interrupt Disable Mask */
+#define SERCOM_USART_INT_INTENCLR_RXS(value)  (SERCOM_USART_INT_INTENCLR_RXS_Msk & ((value) << SERCOM_USART_INT_INTENCLR_RXS_Pos))
+#define SERCOM_USART_INT_INTENCLR_CTSIC_Pos   _U_(4)                                               /**< (SERCOM_USART_INT_INTENCLR) Clear To Send Input Change Interrupt Disable Position */
+#define SERCOM_USART_INT_INTENCLR_CTSIC_Msk   (_U_(0x1) << SERCOM_USART_INT_INTENCLR_CTSIC_Pos)    /**< (SERCOM_USART_INT_INTENCLR) Clear To Send Input Change Interrupt Disable Mask */
+#define SERCOM_USART_INT_INTENCLR_CTSIC(value) (SERCOM_USART_INT_INTENCLR_CTSIC_Msk & ((value) << SERCOM_USART_INT_INTENCLR_CTSIC_Pos))
+#define SERCOM_USART_INT_INTENCLR_RXBRK_Pos   _U_(5)                                               /**< (SERCOM_USART_INT_INTENCLR) Break Received Interrupt Disable Position */
+#define SERCOM_USART_INT_INTENCLR_RXBRK_Msk   (_U_(0x1) << SERCOM_USART_INT_INTENCLR_RXBRK_Pos)    /**< (SERCOM_USART_INT_INTENCLR) Break Received Interrupt Disable Mask */
+#define SERCOM_USART_INT_INTENCLR_RXBRK(value) (SERCOM_USART_INT_INTENCLR_RXBRK_Msk & ((value) << SERCOM_USART_INT_INTENCLR_RXBRK_Pos))
+#define SERCOM_USART_INT_INTENCLR_ERROR_Pos   _U_(7)                                               /**< (SERCOM_USART_INT_INTENCLR) Combined Error Interrupt Disable Position */
+#define SERCOM_USART_INT_INTENCLR_ERROR_Msk   (_U_(0x1) << SERCOM_USART_INT_INTENCLR_ERROR_Pos)    /**< (SERCOM_USART_INT_INTENCLR) Combined Error Interrupt Disable Mask */
+#define SERCOM_USART_INT_INTENCLR_ERROR(value) (SERCOM_USART_INT_INTENCLR_ERROR_Msk & ((value) << SERCOM_USART_INT_INTENCLR_ERROR_Pos))
+#define SERCOM_USART_INT_INTENCLR_Msk         _U_(0xBF)                                            /**< (SERCOM_USART_INT_INTENCLR) Register Mask  */
+
+
+/* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM Interrupt Enable Set -------- */
+#define SERCOM_I2CM_INTENSET_RESETVALUE       _U_(0x00)                                            /**<  (SERCOM_I2CM_INTENSET) I2CM Interrupt Enable Set  Reset Value */
+
+#define SERCOM_I2CM_INTENSET_MB_Pos           _U_(0)                                               /**< (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable Position */
+#define SERCOM_I2CM_INTENSET_MB_Msk           (_U_(0x1) << SERCOM_I2CM_INTENSET_MB_Pos)            /**< (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable Mask */
+#define SERCOM_I2CM_INTENSET_MB(value)        (SERCOM_I2CM_INTENSET_MB_Msk & ((value) << SERCOM_I2CM_INTENSET_MB_Pos))
+#define SERCOM_I2CM_INTENSET_SB_Pos           _U_(1)                                               /**< (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable Position */
+#define SERCOM_I2CM_INTENSET_SB_Msk           (_U_(0x1) << SERCOM_I2CM_INTENSET_SB_Pos)            /**< (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable Mask */
+#define SERCOM_I2CM_INTENSET_SB(value)        (SERCOM_I2CM_INTENSET_SB_Msk & ((value) << SERCOM_I2CM_INTENSET_SB_Pos))
+#define SERCOM_I2CM_INTENSET_ERROR_Pos        _U_(7)                                               /**< (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable Position */
+#define SERCOM_I2CM_INTENSET_ERROR_Msk        (_U_(0x1) << SERCOM_I2CM_INTENSET_ERROR_Pos)         /**< (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable Mask */
+#define SERCOM_I2CM_INTENSET_ERROR(value)     (SERCOM_I2CM_INTENSET_ERROR_Msk & ((value) << SERCOM_I2CM_INTENSET_ERROR_Pos))
+#define SERCOM_I2CM_INTENSET_Msk              _U_(0x83)                                            /**< (SERCOM_I2CM_INTENSET) Register Mask  */
+
+
+/* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS Interrupt Enable Set -------- */
+#define SERCOM_I2CS_INTENSET_RESETVALUE       _U_(0x00)                                            /**<  (SERCOM_I2CS_INTENSET) I2CS Interrupt Enable Set  Reset Value */
+
+#define SERCOM_I2CS_INTENSET_PREC_Pos         _U_(0)                                               /**< (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable Position */
+#define SERCOM_I2CS_INTENSET_PREC_Msk         (_U_(0x1) << SERCOM_I2CS_INTENSET_PREC_Pos)          /**< (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable Mask */
+#define SERCOM_I2CS_INTENSET_PREC(value)      (SERCOM_I2CS_INTENSET_PREC_Msk & ((value) << SERCOM_I2CS_INTENSET_PREC_Pos))
+#define SERCOM_I2CS_INTENSET_AMATCH_Pos       _U_(1)                                               /**< (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable Position */
+#define SERCOM_I2CS_INTENSET_AMATCH_Msk       (_U_(0x1) << SERCOM_I2CS_INTENSET_AMATCH_Pos)        /**< (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable Mask */
+#define SERCOM_I2CS_INTENSET_AMATCH(value)    (SERCOM_I2CS_INTENSET_AMATCH_Msk & ((value) << SERCOM_I2CS_INTENSET_AMATCH_Pos))
+#define SERCOM_I2CS_INTENSET_DRDY_Pos         _U_(2)                                               /**< (SERCOM_I2CS_INTENSET) Data Interrupt Enable Position */
+#define SERCOM_I2CS_INTENSET_DRDY_Msk         (_U_(0x1) << SERCOM_I2CS_INTENSET_DRDY_Pos)          /**< (SERCOM_I2CS_INTENSET) Data Interrupt Enable Mask */
+#define SERCOM_I2CS_INTENSET_DRDY(value)      (SERCOM_I2CS_INTENSET_DRDY_Msk & ((value) << SERCOM_I2CS_INTENSET_DRDY_Pos))
+#define SERCOM_I2CS_INTENSET_ERROR_Pos        _U_(7)                                               /**< (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable Position */
+#define SERCOM_I2CS_INTENSET_ERROR_Msk        (_U_(0x1) << SERCOM_I2CS_INTENSET_ERROR_Pos)         /**< (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable Mask */
+#define SERCOM_I2CS_INTENSET_ERROR(value)     (SERCOM_I2CS_INTENSET_ERROR_Msk & ((value) << SERCOM_I2CS_INTENSET_ERROR_Pos))
+#define SERCOM_I2CS_INTENSET_Msk              _U_(0x87)                                            /**< (SERCOM_I2CS_INTENSET) Register Mask  */
+
+
+/* -------- SERCOM_SPIM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPIM Interrupt Enable Set -------- */
+#define SERCOM_SPIM_INTENSET_RESETVALUE       _U_(0x00)                                            /**<  (SERCOM_SPIM_INTENSET) SPIM Interrupt Enable Set  Reset Value */
+
+#define SERCOM_SPIM_INTENSET_DRE_Pos          _U_(0)                                               /**< (SERCOM_SPIM_INTENSET) Data Register Empty Interrupt Enable Position */
+#define SERCOM_SPIM_INTENSET_DRE_Msk          (_U_(0x1) << SERCOM_SPIM_INTENSET_DRE_Pos)           /**< (SERCOM_SPIM_INTENSET) Data Register Empty Interrupt Enable Mask */
+#define SERCOM_SPIM_INTENSET_DRE(value)       (SERCOM_SPIM_INTENSET_DRE_Msk & ((value) << SERCOM_SPIM_INTENSET_DRE_Pos))
+#define SERCOM_SPIM_INTENSET_TXC_Pos          _U_(1)                                               /**< (SERCOM_SPIM_INTENSET) Transmit Complete Interrupt Enable Position */
+#define SERCOM_SPIM_INTENSET_TXC_Msk          (_U_(0x1) << SERCOM_SPIM_INTENSET_TXC_Pos)           /**< (SERCOM_SPIM_INTENSET) Transmit Complete Interrupt Enable Mask */
+#define SERCOM_SPIM_INTENSET_TXC(value)       (SERCOM_SPIM_INTENSET_TXC_Msk & ((value) << SERCOM_SPIM_INTENSET_TXC_Pos))
+#define SERCOM_SPIM_INTENSET_RXC_Pos          _U_(2)                                               /**< (SERCOM_SPIM_INTENSET) Receive Complete Interrupt Enable Position */
+#define SERCOM_SPIM_INTENSET_RXC_Msk          (_U_(0x1) << SERCOM_SPIM_INTENSET_RXC_Pos)           /**< (SERCOM_SPIM_INTENSET) Receive Complete Interrupt Enable Mask */
+#define SERCOM_SPIM_INTENSET_RXC(value)       (SERCOM_SPIM_INTENSET_RXC_Msk & ((value) << SERCOM_SPIM_INTENSET_RXC_Pos))
+#define SERCOM_SPIM_INTENSET_SSL_Pos          _U_(3)                                               /**< (SERCOM_SPIM_INTENSET) Slave Select Low Interrupt Enable Position */
+#define SERCOM_SPIM_INTENSET_SSL_Msk          (_U_(0x1) << SERCOM_SPIM_INTENSET_SSL_Pos)           /**< (SERCOM_SPIM_INTENSET) Slave Select Low Interrupt Enable Mask */
+#define SERCOM_SPIM_INTENSET_SSL(value)       (SERCOM_SPIM_INTENSET_SSL_Msk & ((value) << SERCOM_SPIM_INTENSET_SSL_Pos))
+#define SERCOM_SPIM_INTENSET_ERROR_Pos        _U_(7)                                               /**< (SERCOM_SPIM_INTENSET) Combined Error Interrupt Enable Position */
+#define SERCOM_SPIM_INTENSET_ERROR_Msk        (_U_(0x1) << SERCOM_SPIM_INTENSET_ERROR_Pos)         /**< (SERCOM_SPIM_INTENSET) Combined Error Interrupt Enable Mask */
+#define SERCOM_SPIM_INTENSET_ERROR(value)     (SERCOM_SPIM_INTENSET_ERROR_Msk & ((value) << SERCOM_SPIM_INTENSET_ERROR_Pos))
+#define SERCOM_SPIM_INTENSET_Msk              _U_(0x8F)                                            /**< (SERCOM_SPIM_INTENSET) Register Mask  */
+
+
+/* -------- SERCOM_SPIS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPIS Interrupt Enable Set -------- */
+#define SERCOM_SPIS_INTENSET_RESETVALUE       _U_(0x00)                                            /**<  (SERCOM_SPIS_INTENSET) SPIS Interrupt Enable Set  Reset Value */
+
+#define SERCOM_SPIS_INTENSET_DRE_Pos          _U_(0)                                               /**< (SERCOM_SPIS_INTENSET) Data Register Empty Interrupt Enable Position */
+#define SERCOM_SPIS_INTENSET_DRE_Msk          (_U_(0x1) << SERCOM_SPIS_INTENSET_DRE_Pos)           /**< (SERCOM_SPIS_INTENSET) Data Register Empty Interrupt Enable Mask */
+#define SERCOM_SPIS_INTENSET_DRE(value)       (SERCOM_SPIS_INTENSET_DRE_Msk & ((value) << SERCOM_SPIS_INTENSET_DRE_Pos))
+#define SERCOM_SPIS_INTENSET_TXC_Pos          _U_(1)                                               /**< (SERCOM_SPIS_INTENSET) Transmit Complete Interrupt Enable Position */
+#define SERCOM_SPIS_INTENSET_TXC_Msk          (_U_(0x1) << SERCOM_SPIS_INTENSET_TXC_Pos)           /**< (SERCOM_SPIS_INTENSET) Transmit Complete Interrupt Enable Mask */
+#define SERCOM_SPIS_INTENSET_TXC(value)       (SERCOM_SPIS_INTENSET_TXC_Msk & ((value) << SERCOM_SPIS_INTENSET_TXC_Pos))
+#define SERCOM_SPIS_INTENSET_RXC_Pos          _U_(2)                                               /**< (SERCOM_SPIS_INTENSET) Receive Complete Interrupt Enable Position */
+#define SERCOM_SPIS_INTENSET_RXC_Msk          (_U_(0x1) << SERCOM_SPIS_INTENSET_RXC_Pos)           /**< (SERCOM_SPIS_INTENSET) Receive Complete Interrupt Enable Mask */
+#define SERCOM_SPIS_INTENSET_RXC(value)       (SERCOM_SPIS_INTENSET_RXC_Msk & ((value) << SERCOM_SPIS_INTENSET_RXC_Pos))
+#define SERCOM_SPIS_INTENSET_SSL_Pos          _U_(3)                                               /**< (SERCOM_SPIS_INTENSET) Slave Select Low Interrupt Enable Position */
+#define SERCOM_SPIS_INTENSET_SSL_Msk          (_U_(0x1) << SERCOM_SPIS_INTENSET_SSL_Pos)           /**< (SERCOM_SPIS_INTENSET) Slave Select Low Interrupt Enable Mask */
+#define SERCOM_SPIS_INTENSET_SSL(value)       (SERCOM_SPIS_INTENSET_SSL_Msk & ((value) << SERCOM_SPIS_INTENSET_SSL_Pos))
+#define SERCOM_SPIS_INTENSET_ERROR_Pos        _U_(7)                                               /**< (SERCOM_SPIS_INTENSET) Combined Error Interrupt Enable Position */
+#define SERCOM_SPIS_INTENSET_ERROR_Msk        (_U_(0x1) << SERCOM_SPIS_INTENSET_ERROR_Pos)         /**< (SERCOM_SPIS_INTENSET) Combined Error Interrupt Enable Mask */
+#define SERCOM_SPIS_INTENSET_ERROR(value)     (SERCOM_SPIS_INTENSET_ERROR_Msk & ((value) << SERCOM_SPIS_INTENSET_ERROR_Pos))
+#define SERCOM_SPIS_INTENSET_Msk              _U_(0x8F)                                            /**< (SERCOM_SPIS_INTENSET) Register Mask  */
+
+
+/* -------- SERCOM_USART_EXT_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART_EXT Interrupt Enable Set -------- */
+#define SERCOM_USART_EXT_INTENSET_RESETVALUE  _U_(0x00)                                            /**<  (SERCOM_USART_EXT_INTENSET) USART_EXT Interrupt Enable Set  Reset Value */
+
+#define SERCOM_USART_EXT_INTENSET_DRE_Pos     _U_(0)                                               /**< (SERCOM_USART_EXT_INTENSET) Data Register Empty Interrupt Enable Position */
+#define SERCOM_USART_EXT_INTENSET_DRE_Msk     (_U_(0x1) << SERCOM_USART_EXT_INTENSET_DRE_Pos)      /**< (SERCOM_USART_EXT_INTENSET) Data Register Empty Interrupt Enable Mask */
+#define SERCOM_USART_EXT_INTENSET_DRE(value)  (SERCOM_USART_EXT_INTENSET_DRE_Msk & ((value) << SERCOM_USART_EXT_INTENSET_DRE_Pos))
+#define SERCOM_USART_EXT_INTENSET_TXC_Pos     _U_(1)                                               /**< (SERCOM_USART_EXT_INTENSET) Transmit Complete Interrupt Enable Position */
+#define SERCOM_USART_EXT_INTENSET_TXC_Msk     (_U_(0x1) << SERCOM_USART_EXT_INTENSET_TXC_Pos)      /**< (SERCOM_USART_EXT_INTENSET) Transmit Complete Interrupt Enable Mask */
+#define SERCOM_USART_EXT_INTENSET_TXC(value)  (SERCOM_USART_EXT_INTENSET_TXC_Msk & ((value) << SERCOM_USART_EXT_INTENSET_TXC_Pos))
+#define SERCOM_USART_EXT_INTENSET_RXC_Pos     _U_(2)                                               /**< (SERCOM_USART_EXT_INTENSET) Receive Complete Interrupt Enable Position */
+#define SERCOM_USART_EXT_INTENSET_RXC_Msk     (_U_(0x1) << SERCOM_USART_EXT_INTENSET_RXC_Pos)      /**< (SERCOM_USART_EXT_INTENSET) Receive Complete Interrupt Enable Mask */
+#define SERCOM_USART_EXT_INTENSET_RXC(value)  (SERCOM_USART_EXT_INTENSET_RXC_Msk & ((value) << SERCOM_USART_EXT_INTENSET_RXC_Pos))
+#define SERCOM_USART_EXT_INTENSET_RXS_Pos     _U_(3)                                               /**< (SERCOM_USART_EXT_INTENSET) Receive Start Interrupt Enable Position */
+#define SERCOM_USART_EXT_INTENSET_RXS_Msk     (_U_(0x1) << SERCOM_USART_EXT_INTENSET_RXS_Pos)      /**< (SERCOM_USART_EXT_INTENSET) Receive Start Interrupt Enable Mask */
+#define SERCOM_USART_EXT_INTENSET_RXS(value)  (SERCOM_USART_EXT_INTENSET_RXS_Msk & ((value) << SERCOM_USART_EXT_INTENSET_RXS_Pos))
+#define SERCOM_USART_EXT_INTENSET_CTSIC_Pos   _U_(4)                                               /**< (SERCOM_USART_EXT_INTENSET) Clear To Send Input Change Interrupt Enable Position */
+#define SERCOM_USART_EXT_INTENSET_CTSIC_Msk   (_U_(0x1) << SERCOM_USART_EXT_INTENSET_CTSIC_Pos)    /**< (SERCOM_USART_EXT_INTENSET) Clear To Send Input Change Interrupt Enable Mask */
+#define SERCOM_USART_EXT_INTENSET_CTSIC(value) (SERCOM_USART_EXT_INTENSET_CTSIC_Msk & ((value) << SERCOM_USART_EXT_INTENSET_CTSIC_Pos))
+#define SERCOM_USART_EXT_INTENSET_RXBRK_Pos   _U_(5)                                               /**< (SERCOM_USART_EXT_INTENSET) Break Received Interrupt Enable Position */
+#define SERCOM_USART_EXT_INTENSET_RXBRK_Msk   (_U_(0x1) << SERCOM_USART_EXT_INTENSET_RXBRK_Pos)    /**< (SERCOM_USART_EXT_INTENSET) Break Received Interrupt Enable Mask */
+#define SERCOM_USART_EXT_INTENSET_RXBRK(value) (SERCOM_USART_EXT_INTENSET_RXBRK_Msk & ((value) << SERCOM_USART_EXT_INTENSET_RXBRK_Pos))
+#define SERCOM_USART_EXT_INTENSET_ERROR_Pos   _U_(7)                                               /**< (SERCOM_USART_EXT_INTENSET) Combined Error Interrupt Enable Position */
+#define SERCOM_USART_EXT_INTENSET_ERROR_Msk   (_U_(0x1) << SERCOM_USART_EXT_INTENSET_ERROR_Pos)    /**< (SERCOM_USART_EXT_INTENSET) Combined Error Interrupt Enable Mask */
+#define SERCOM_USART_EXT_INTENSET_ERROR(value) (SERCOM_USART_EXT_INTENSET_ERROR_Msk & ((value) << SERCOM_USART_EXT_INTENSET_ERROR_Pos))
+#define SERCOM_USART_EXT_INTENSET_Msk         _U_(0xBF)                                            /**< (SERCOM_USART_EXT_INTENSET) Register Mask  */
+
+
+/* -------- SERCOM_USART_INT_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART_INT Interrupt Enable Set -------- */
+#define SERCOM_USART_INT_INTENSET_RESETVALUE  _U_(0x00)                                            /**<  (SERCOM_USART_INT_INTENSET) USART_INT Interrupt Enable Set  Reset Value */
+
+#define SERCOM_USART_INT_INTENSET_DRE_Pos     _U_(0)                                               /**< (SERCOM_USART_INT_INTENSET) Data Register Empty Interrupt Enable Position */
+#define SERCOM_USART_INT_INTENSET_DRE_Msk     (_U_(0x1) << SERCOM_USART_INT_INTENSET_DRE_Pos)      /**< (SERCOM_USART_INT_INTENSET) Data Register Empty Interrupt Enable Mask */
+#define SERCOM_USART_INT_INTENSET_DRE(value)  (SERCOM_USART_INT_INTENSET_DRE_Msk & ((value) << SERCOM_USART_INT_INTENSET_DRE_Pos))
+#define SERCOM_USART_INT_INTENSET_TXC_Pos     _U_(1)                                               /**< (SERCOM_USART_INT_INTENSET) Transmit Complete Interrupt Enable Position */
+#define SERCOM_USART_INT_INTENSET_TXC_Msk     (_U_(0x1) << SERCOM_USART_INT_INTENSET_TXC_Pos)      /**< (SERCOM_USART_INT_INTENSET) Transmit Complete Interrupt Enable Mask */
+#define SERCOM_USART_INT_INTENSET_TXC(value)  (SERCOM_USART_INT_INTENSET_TXC_Msk & ((value) << SERCOM_USART_INT_INTENSET_TXC_Pos))
+#define SERCOM_USART_INT_INTENSET_RXC_Pos     _U_(2)                                               /**< (SERCOM_USART_INT_INTENSET) Receive Complete Interrupt Enable Position */
+#define SERCOM_USART_INT_INTENSET_RXC_Msk     (_U_(0x1) << SERCOM_USART_INT_INTENSET_RXC_Pos)      /**< (SERCOM_USART_INT_INTENSET) Receive Complete Interrupt Enable Mask */
+#define SERCOM_USART_INT_INTENSET_RXC(value)  (SERCOM_USART_INT_INTENSET_RXC_Msk & ((value) << SERCOM_USART_INT_INTENSET_RXC_Pos))
+#define SERCOM_USART_INT_INTENSET_RXS_Pos     _U_(3)                                               /**< (SERCOM_USART_INT_INTENSET) Receive Start Interrupt Enable Position */
+#define SERCOM_USART_INT_INTENSET_RXS_Msk     (_U_(0x1) << SERCOM_USART_INT_INTENSET_RXS_Pos)      /**< (SERCOM_USART_INT_INTENSET) Receive Start Interrupt Enable Mask */
+#define SERCOM_USART_INT_INTENSET_RXS(value)  (SERCOM_USART_INT_INTENSET_RXS_Msk & ((value) << SERCOM_USART_INT_INTENSET_RXS_Pos))
+#define SERCOM_USART_INT_INTENSET_CTSIC_Pos   _U_(4)                                               /**< (SERCOM_USART_INT_INTENSET) Clear To Send Input Change Interrupt Enable Position */
+#define SERCOM_USART_INT_INTENSET_CTSIC_Msk   (_U_(0x1) << SERCOM_USART_INT_INTENSET_CTSIC_Pos)    /**< (SERCOM_USART_INT_INTENSET) Clear To Send Input Change Interrupt Enable Mask */
+#define SERCOM_USART_INT_INTENSET_CTSIC(value) (SERCOM_USART_INT_INTENSET_CTSIC_Msk & ((value) << SERCOM_USART_INT_INTENSET_CTSIC_Pos))
+#define SERCOM_USART_INT_INTENSET_RXBRK_Pos   _U_(5)                                               /**< (SERCOM_USART_INT_INTENSET) Break Received Interrupt Enable Position */
+#define SERCOM_USART_INT_INTENSET_RXBRK_Msk   (_U_(0x1) << SERCOM_USART_INT_INTENSET_RXBRK_Pos)    /**< (SERCOM_USART_INT_INTENSET) Break Received Interrupt Enable Mask */
+#define SERCOM_USART_INT_INTENSET_RXBRK(value) (SERCOM_USART_INT_INTENSET_RXBRK_Msk & ((value) << SERCOM_USART_INT_INTENSET_RXBRK_Pos))
+#define SERCOM_USART_INT_INTENSET_ERROR_Pos   _U_(7)                                               /**< (SERCOM_USART_INT_INTENSET) Combined Error Interrupt Enable Position */
+#define SERCOM_USART_INT_INTENSET_ERROR_Msk   (_U_(0x1) << SERCOM_USART_INT_INTENSET_ERROR_Pos)    /**< (SERCOM_USART_INT_INTENSET) Combined Error Interrupt Enable Mask */
+#define SERCOM_USART_INT_INTENSET_ERROR(value) (SERCOM_USART_INT_INTENSET_ERROR_Msk & ((value) << SERCOM_USART_INT_INTENSET_ERROR_Pos))
+#define SERCOM_USART_INT_INTENSET_Msk         _U_(0xBF)                                            /**< (SERCOM_USART_INT_INTENSET) Register Mask  */
+
+
+/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM Interrupt Flag Status and Clear -------- */
+#define SERCOM_I2CM_INTFLAG_RESETVALUE        _U_(0x00)                                            /**<  (SERCOM_I2CM_INTFLAG) I2CM Interrupt Flag Status and Clear  Reset Value */
+
+#define SERCOM_I2CM_INTFLAG_MB_Pos            _U_(0)                                               /**< (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt Position */
+#define SERCOM_I2CM_INTFLAG_MB_Msk            (_U_(0x1) << SERCOM_I2CM_INTFLAG_MB_Pos)             /**< (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt Mask */
+#define SERCOM_I2CM_INTFLAG_MB(value)         (SERCOM_I2CM_INTFLAG_MB_Msk & ((value) << SERCOM_I2CM_INTFLAG_MB_Pos))
+#define SERCOM_I2CM_INTFLAG_SB_Pos            _U_(1)                                               /**< (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt Position */
+#define SERCOM_I2CM_INTFLAG_SB_Msk            (_U_(0x1) << SERCOM_I2CM_INTFLAG_SB_Pos)             /**< (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt Mask */
+#define SERCOM_I2CM_INTFLAG_SB(value)         (SERCOM_I2CM_INTFLAG_SB_Msk & ((value) << SERCOM_I2CM_INTFLAG_SB_Pos))
+#define SERCOM_I2CM_INTFLAG_ERROR_Pos         _U_(7)                                               /**< (SERCOM_I2CM_INTFLAG) Combined Error Interrupt Position */
+#define SERCOM_I2CM_INTFLAG_ERROR_Msk         (_U_(0x1) << SERCOM_I2CM_INTFLAG_ERROR_Pos)          /**< (SERCOM_I2CM_INTFLAG) Combined Error Interrupt Mask */
+#define SERCOM_I2CM_INTFLAG_ERROR(value)      (SERCOM_I2CM_INTFLAG_ERROR_Msk & ((value) << SERCOM_I2CM_INTFLAG_ERROR_Pos))
+#define SERCOM_I2CM_INTFLAG_Msk               _U_(0x83)                                            /**< (SERCOM_I2CM_INTFLAG) Register Mask  */
+
+
+/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS Interrupt Flag Status and Clear -------- */
+#define SERCOM_I2CS_INTFLAG_RESETVALUE        _U_(0x00)                                            /**<  (SERCOM_I2CS_INTFLAG) I2CS Interrupt Flag Status and Clear  Reset Value */
+
+#define SERCOM_I2CS_INTFLAG_PREC_Pos          _U_(0)                                               /**< (SERCOM_I2CS_INTFLAG) Stop Received Interrupt Position */
+#define SERCOM_I2CS_INTFLAG_PREC_Msk          (_U_(0x1) << SERCOM_I2CS_INTFLAG_PREC_Pos)           /**< (SERCOM_I2CS_INTFLAG) Stop Received Interrupt Mask */
+#define SERCOM_I2CS_INTFLAG_PREC(value)       (SERCOM_I2CS_INTFLAG_PREC_Msk & ((value) << SERCOM_I2CS_INTFLAG_PREC_Pos))
+#define SERCOM_I2CS_INTFLAG_AMATCH_Pos        _U_(1)                                               /**< (SERCOM_I2CS_INTFLAG) Address Match Interrupt Position */
+#define SERCOM_I2CS_INTFLAG_AMATCH_Msk        (_U_(0x1) << SERCOM_I2CS_INTFLAG_AMATCH_Pos)         /**< (SERCOM_I2CS_INTFLAG) Address Match Interrupt Mask */
+#define SERCOM_I2CS_INTFLAG_AMATCH(value)     (SERCOM_I2CS_INTFLAG_AMATCH_Msk & ((value) << SERCOM_I2CS_INTFLAG_AMATCH_Pos))
+#define SERCOM_I2CS_INTFLAG_DRDY_Pos          _U_(2)                                               /**< (SERCOM_I2CS_INTFLAG) Data Interrupt Position */
+#define SERCOM_I2CS_INTFLAG_DRDY_Msk          (_U_(0x1) << SERCOM_I2CS_INTFLAG_DRDY_Pos)           /**< (SERCOM_I2CS_INTFLAG) Data Interrupt Mask */
+#define SERCOM_I2CS_INTFLAG_DRDY(value)       (SERCOM_I2CS_INTFLAG_DRDY_Msk & ((value) << SERCOM_I2CS_INTFLAG_DRDY_Pos))
+#define SERCOM_I2CS_INTFLAG_ERROR_Pos         _U_(7)                                               /**< (SERCOM_I2CS_INTFLAG) Combined Error Interrupt Position */
+#define SERCOM_I2CS_INTFLAG_ERROR_Msk         (_U_(0x1) << SERCOM_I2CS_INTFLAG_ERROR_Pos)          /**< (SERCOM_I2CS_INTFLAG) Combined Error Interrupt Mask */
+#define SERCOM_I2CS_INTFLAG_ERROR(value)      (SERCOM_I2CS_INTFLAG_ERROR_Msk & ((value) << SERCOM_I2CS_INTFLAG_ERROR_Pos))
+#define SERCOM_I2CS_INTFLAG_Msk               _U_(0x87)                                            /**< (SERCOM_I2CS_INTFLAG) Register Mask  */
+
+
+/* -------- SERCOM_SPIM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPIM Interrupt Flag Status and Clear -------- */
+#define SERCOM_SPIM_INTFLAG_RESETVALUE        _U_(0x00)                                            /**<  (SERCOM_SPIM_INTFLAG) SPIM Interrupt Flag Status and Clear  Reset Value */
+
+#define SERCOM_SPIM_INTFLAG_DRE_Pos           _U_(0)                                               /**< (SERCOM_SPIM_INTFLAG) Data Register Empty Interrupt Position */
+#define SERCOM_SPIM_INTFLAG_DRE_Msk           (_U_(0x1) << SERCOM_SPIM_INTFLAG_DRE_Pos)            /**< (SERCOM_SPIM_INTFLAG) Data Register Empty Interrupt Mask */
+#define SERCOM_SPIM_INTFLAG_DRE(value)        (SERCOM_SPIM_INTFLAG_DRE_Msk & ((value) << SERCOM_SPIM_INTFLAG_DRE_Pos))
+#define SERCOM_SPIM_INTFLAG_TXC_Pos           _U_(1)                                               /**< (SERCOM_SPIM_INTFLAG) Transmit Complete Interrupt Position */
+#define SERCOM_SPIM_INTFLAG_TXC_Msk           (_U_(0x1) << SERCOM_SPIM_INTFLAG_TXC_Pos)            /**< (SERCOM_SPIM_INTFLAG) Transmit Complete Interrupt Mask */
+#define SERCOM_SPIM_INTFLAG_TXC(value)        (SERCOM_SPIM_INTFLAG_TXC_Msk & ((value) << SERCOM_SPIM_INTFLAG_TXC_Pos))
+#define SERCOM_SPIM_INTFLAG_RXC_Pos           _U_(2)                                               /**< (SERCOM_SPIM_INTFLAG) Receive Complete Interrupt Position */
+#define SERCOM_SPIM_INTFLAG_RXC_Msk           (_U_(0x1) << SERCOM_SPIM_INTFLAG_RXC_Pos)            /**< (SERCOM_SPIM_INTFLAG) Receive Complete Interrupt Mask */
+#define SERCOM_SPIM_INTFLAG_RXC(value)        (SERCOM_SPIM_INTFLAG_RXC_Msk & ((value) << SERCOM_SPIM_INTFLAG_RXC_Pos))
+#define SERCOM_SPIM_INTFLAG_SSL_Pos           _U_(3)                                               /**< (SERCOM_SPIM_INTFLAG) Slave Select Low Interrupt Flag Position */
+#define SERCOM_SPIM_INTFLAG_SSL_Msk           (_U_(0x1) << SERCOM_SPIM_INTFLAG_SSL_Pos)            /**< (SERCOM_SPIM_INTFLAG) Slave Select Low Interrupt Flag Mask */
+#define SERCOM_SPIM_INTFLAG_SSL(value)        (SERCOM_SPIM_INTFLAG_SSL_Msk & ((value) << SERCOM_SPIM_INTFLAG_SSL_Pos))
+#define SERCOM_SPIM_INTFLAG_ERROR_Pos         _U_(7)                                               /**< (SERCOM_SPIM_INTFLAG) Combined Error Interrupt Position */
+#define SERCOM_SPIM_INTFLAG_ERROR_Msk         (_U_(0x1) << SERCOM_SPIM_INTFLAG_ERROR_Pos)          /**< (SERCOM_SPIM_INTFLAG) Combined Error Interrupt Mask */
+#define SERCOM_SPIM_INTFLAG_ERROR(value)      (SERCOM_SPIM_INTFLAG_ERROR_Msk & ((value) << SERCOM_SPIM_INTFLAG_ERROR_Pos))
+#define SERCOM_SPIM_INTFLAG_Msk               _U_(0x8F)                                            /**< (SERCOM_SPIM_INTFLAG) Register Mask  */
+
+
+/* -------- SERCOM_SPIS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPIS Interrupt Flag Status and Clear -------- */
+#define SERCOM_SPIS_INTFLAG_RESETVALUE        _U_(0x00)                                            /**<  (SERCOM_SPIS_INTFLAG) SPIS Interrupt Flag Status and Clear  Reset Value */
+
+#define SERCOM_SPIS_INTFLAG_DRE_Pos           _U_(0)                                               /**< (SERCOM_SPIS_INTFLAG) Data Register Empty Interrupt Position */
+#define SERCOM_SPIS_INTFLAG_DRE_Msk           (_U_(0x1) << SERCOM_SPIS_INTFLAG_DRE_Pos)            /**< (SERCOM_SPIS_INTFLAG) Data Register Empty Interrupt Mask */
+#define SERCOM_SPIS_INTFLAG_DRE(value)        (SERCOM_SPIS_INTFLAG_DRE_Msk & ((value) << SERCOM_SPIS_INTFLAG_DRE_Pos))
+#define SERCOM_SPIS_INTFLAG_TXC_Pos           _U_(1)                                               /**< (SERCOM_SPIS_INTFLAG) Transmit Complete Interrupt Position */
+#define SERCOM_SPIS_INTFLAG_TXC_Msk           (_U_(0x1) << SERCOM_SPIS_INTFLAG_TXC_Pos)            /**< (SERCOM_SPIS_INTFLAG) Transmit Complete Interrupt Mask */
+#define SERCOM_SPIS_INTFLAG_TXC(value)        (SERCOM_SPIS_INTFLAG_TXC_Msk & ((value) << SERCOM_SPIS_INTFLAG_TXC_Pos))
+#define SERCOM_SPIS_INTFLAG_RXC_Pos           _U_(2)                                               /**< (SERCOM_SPIS_INTFLAG) Receive Complete Interrupt Position */
+#define SERCOM_SPIS_INTFLAG_RXC_Msk           (_U_(0x1) << SERCOM_SPIS_INTFLAG_RXC_Pos)            /**< (SERCOM_SPIS_INTFLAG) Receive Complete Interrupt Mask */
+#define SERCOM_SPIS_INTFLAG_RXC(value)        (SERCOM_SPIS_INTFLAG_RXC_Msk & ((value) << SERCOM_SPIS_INTFLAG_RXC_Pos))
+#define SERCOM_SPIS_INTFLAG_SSL_Pos           _U_(3)                                               /**< (SERCOM_SPIS_INTFLAG) Slave Select Low Interrupt Flag Position */
+#define SERCOM_SPIS_INTFLAG_SSL_Msk           (_U_(0x1) << SERCOM_SPIS_INTFLAG_SSL_Pos)            /**< (SERCOM_SPIS_INTFLAG) Slave Select Low Interrupt Flag Mask */
+#define SERCOM_SPIS_INTFLAG_SSL(value)        (SERCOM_SPIS_INTFLAG_SSL_Msk & ((value) << SERCOM_SPIS_INTFLAG_SSL_Pos))
+#define SERCOM_SPIS_INTFLAG_ERROR_Pos         _U_(7)                                               /**< (SERCOM_SPIS_INTFLAG) Combined Error Interrupt Position */
+#define SERCOM_SPIS_INTFLAG_ERROR_Msk         (_U_(0x1) << SERCOM_SPIS_INTFLAG_ERROR_Pos)          /**< (SERCOM_SPIS_INTFLAG) Combined Error Interrupt Mask */
+#define SERCOM_SPIS_INTFLAG_ERROR(value)      (SERCOM_SPIS_INTFLAG_ERROR_Msk & ((value) << SERCOM_SPIS_INTFLAG_ERROR_Pos))
+#define SERCOM_SPIS_INTFLAG_Msk               _U_(0x8F)                                            /**< (SERCOM_SPIS_INTFLAG) Register Mask  */
+
+
+/* -------- SERCOM_USART_EXT_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART_EXT Interrupt Flag Status and Clear -------- */
+#define SERCOM_USART_EXT_INTFLAG_RESETVALUE   _U_(0x00)                                            /**<  (SERCOM_USART_EXT_INTFLAG) USART_EXT Interrupt Flag Status and Clear  Reset Value */
+
+#define SERCOM_USART_EXT_INTFLAG_DRE_Pos      _U_(0)                                               /**< (SERCOM_USART_EXT_INTFLAG) Data Register Empty Interrupt Position */
+#define SERCOM_USART_EXT_INTFLAG_DRE_Msk      (_U_(0x1) << SERCOM_USART_EXT_INTFLAG_DRE_Pos)       /**< (SERCOM_USART_EXT_INTFLAG) Data Register Empty Interrupt Mask */
+#define SERCOM_USART_EXT_INTFLAG_DRE(value)   (SERCOM_USART_EXT_INTFLAG_DRE_Msk & ((value) << SERCOM_USART_EXT_INTFLAG_DRE_Pos))
+#define SERCOM_USART_EXT_INTFLAG_TXC_Pos      _U_(1)                                               /**< (SERCOM_USART_EXT_INTFLAG) Transmit Complete Interrupt Position */
+#define SERCOM_USART_EXT_INTFLAG_TXC_Msk      (_U_(0x1) << SERCOM_USART_EXT_INTFLAG_TXC_Pos)       /**< (SERCOM_USART_EXT_INTFLAG) Transmit Complete Interrupt Mask */
+#define SERCOM_USART_EXT_INTFLAG_TXC(value)   (SERCOM_USART_EXT_INTFLAG_TXC_Msk & ((value) << SERCOM_USART_EXT_INTFLAG_TXC_Pos))
+#define SERCOM_USART_EXT_INTFLAG_RXC_Pos      _U_(2)                                               /**< (SERCOM_USART_EXT_INTFLAG) Receive Complete Interrupt Position */
+#define SERCOM_USART_EXT_INTFLAG_RXC_Msk      (_U_(0x1) << SERCOM_USART_EXT_INTFLAG_RXC_Pos)       /**< (SERCOM_USART_EXT_INTFLAG) Receive Complete Interrupt Mask */
+#define SERCOM_USART_EXT_INTFLAG_RXC(value)   (SERCOM_USART_EXT_INTFLAG_RXC_Msk & ((value) << SERCOM_USART_EXT_INTFLAG_RXC_Pos))
+#define SERCOM_USART_EXT_INTFLAG_RXS_Pos      _U_(3)                                               /**< (SERCOM_USART_EXT_INTFLAG) Receive Start Interrupt Position */
+#define SERCOM_USART_EXT_INTFLAG_RXS_Msk      (_U_(0x1) << SERCOM_USART_EXT_INTFLAG_RXS_Pos)       /**< (SERCOM_USART_EXT_INTFLAG) Receive Start Interrupt Mask */
+#define SERCOM_USART_EXT_INTFLAG_RXS(value)   (SERCOM_USART_EXT_INTFLAG_RXS_Msk & ((value) << SERCOM_USART_EXT_INTFLAG_RXS_Pos))
+#define SERCOM_USART_EXT_INTFLAG_CTSIC_Pos    _U_(4)                                               /**< (SERCOM_USART_EXT_INTFLAG) Clear To Send Input Change Interrupt Position */
+#define SERCOM_USART_EXT_INTFLAG_CTSIC_Msk    (_U_(0x1) << SERCOM_USART_EXT_INTFLAG_CTSIC_Pos)     /**< (SERCOM_USART_EXT_INTFLAG) Clear To Send Input Change Interrupt Mask */
+#define SERCOM_USART_EXT_INTFLAG_CTSIC(value) (SERCOM_USART_EXT_INTFLAG_CTSIC_Msk & ((value) << SERCOM_USART_EXT_INTFLAG_CTSIC_Pos))
+#define SERCOM_USART_EXT_INTFLAG_RXBRK_Pos    _U_(5)                                               /**< (SERCOM_USART_EXT_INTFLAG) Break Received Interrupt Position */
+#define SERCOM_USART_EXT_INTFLAG_RXBRK_Msk    (_U_(0x1) << SERCOM_USART_EXT_INTFLAG_RXBRK_Pos)     /**< (SERCOM_USART_EXT_INTFLAG) Break Received Interrupt Mask */
+#define SERCOM_USART_EXT_INTFLAG_RXBRK(value) (SERCOM_USART_EXT_INTFLAG_RXBRK_Msk & ((value) << SERCOM_USART_EXT_INTFLAG_RXBRK_Pos))
+#define SERCOM_USART_EXT_INTFLAG_ERROR_Pos    _U_(7)                                               /**< (SERCOM_USART_EXT_INTFLAG) Combined Error Interrupt Position */
+#define SERCOM_USART_EXT_INTFLAG_ERROR_Msk    (_U_(0x1) << SERCOM_USART_EXT_INTFLAG_ERROR_Pos)     /**< (SERCOM_USART_EXT_INTFLAG) Combined Error Interrupt Mask */
+#define SERCOM_USART_EXT_INTFLAG_ERROR(value) (SERCOM_USART_EXT_INTFLAG_ERROR_Msk & ((value) << SERCOM_USART_EXT_INTFLAG_ERROR_Pos))
+#define SERCOM_USART_EXT_INTFLAG_Msk          _U_(0xBF)                                            /**< (SERCOM_USART_EXT_INTFLAG) Register Mask  */
+
+
+/* -------- SERCOM_USART_INT_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART_INT Interrupt Flag Status and Clear -------- */
+#define SERCOM_USART_INT_INTFLAG_RESETVALUE   _U_(0x00)                                            /**<  (SERCOM_USART_INT_INTFLAG) USART_INT Interrupt Flag Status and Clear  Reset Value */
+
+#define SERCOM_USART_INT_INTFLAG_DRE_Pos      _U_(0)                                               /**< (SERCOM_USART_INT_INTFLAG) Data Register Empty Interrupt Position */
+#define SERCOM_USART_INT_INTFLAG_DRE_Msk      (_U_(0x1) << SERCOM_USART_INT_INTFLAG_DRE_Pos)       /**< (SERCOM_USART_INT_INTFLAG) Data Register Empty Interrupt Mask */
+#define SERCOM_USART_INT_INTFLAG_DRE(value)   (SERCOM_USART_INT_INTFLAG_DRE_Msk & ((value) << SERCOM_USART_INT_INTFLAG_DRE_Pos))
+#define SERCOM_USART_INT_INTFLAG_TXC_Pos      _U_(1)                                               /**< (SERCOM_USART_INT_INTFLAG) Transmit Complete Interrupt Position */
+#define SERCOM_USART_INT_INTFLAG_TXC_Msk      (_U_(0x1) << SERCOM_USART_INT_INTFLAG_TXC_Pos)       /**< (SERCOM_USART_INT_INTFLAG) Transmit Complete Interrupt Mask */
+#define SERCOM_USART_INT_INTFLAG_TXC(value)   (SERCOM_USART_INT_INTFLAG_TXC_Msk & ((value) << SERCOM_USART_INT_INTFLAG_TXC_Pos))
+#define SERCOM_USART_INT_INTFLAG_RXC_Pos      _U_(2)                                               /**< (SERCOM_USART_INT_INTFLAG) Receive Complete Interrupt Position */
+#define SERCOM_USART_INT_INTFLAG_RXC_Msk      (_U_(0x1) << SERCOM_USART_INT_INTFLAG_RXC_Pos)       /**< (SERCOM_USART_INT_INTFLAG) Receive Complete Interrupt Mask */
+#define SERCOM_USART_INT_INTFLAG_RXC(value)   (SERCOM_USART_INT_INTFLAG_RXC_Msk & ((value) << SERCOM_USART_INT_INTFLAG_RXC_Pos))
+#define SERCOM_USART_INT_INTFLAG_RXS_Pos      _U_(3)                                               /**< (SERCOM_USART_INT_INTFLAG) Receive Start Interrupt Position */
+#define SERCOM_USART_INT_INTFLAG_RXS_Msk      (_U_(0x1) << SERCOM_USART_INT_INTFLAG_RXS_Pos)       /**< (SERCOM_USART_INT_INTFLAG) Receive Start Interrupt Mask */
+#define SERCOM_USART_INT_INTFLAG_RXS(value)   (SERCOM_USART_INT_INTFLAG_RXS_Msk & ((value) << SERCOM_USART_INT_INTFLAG_RXS_Pos))
+#define SERCOM_USART_INT_INTFLAG_CTSIC_Pos    _U_(4)                                               /**< (SERCOM_USART_INT_INTFLAG) Clear To Send Input Change Interrupt Position */
+#define SERCOM_USART_INT_INTFLAG_CTSIC_Msk    (_U_(0x1) << SERCOM_USART_INT_INTFLAG_CTSIC_Pos)     /**< (SERCOM_USART_INT_INTFLAG) Clear To Send Input Change Interrupt Mask */
+#define SERCOM_USART_INT_INTFLAG_CTSIC(value) (SERCOM_USART_INT_INTFLAG_CTSIC_Msk & ((value) << SERCOM_USART_INT_INTFLAG_CTSIC_Pos))
+#define SERCOM_USART_INT_INTFLAG_RXBRK_Pos    _U_(5)                                               /**< (SERCOM_USART_INT_INTFLAG) Break Received Interrupt Position */
+#define SERCOM_USART_INT_INTFLAG_RXBRK_Msk    (_U_(0x1) << SERCOM_USART_INT_INTFLAG_RXBRK_Pos)     /**< (SERCOM_USART_INT_INTFLAG) Break Received Interrupt Mask */
+#define SERCOM_USART_INT_INTFLAG_RXBRK(value) (SERCOM_USART_INT_INTFLAG_RXBRK_Msk & ((value) << SERCOM_USART_INT_INTFLAG_RXBRK_Pos))
+#define SERCOM_USART_INT_INTFLAG_ERROR_Pos    _U_(7)                                               /**< (SERCOM_USART_INT_INTFLAG) Combined Error Interrupt Position */
+#define SERCOM_USART_INT_INTFLAG_ERROR_Msk    (_U_(0x1) << SERCOM_USART_INT_INTFLAG_ERROR_Pos)     /**< (SERCOM_USART_INT_INTFLAG) Combined Error Interrupt Mask */
+#define SERCOM_USART_INT_INTFLAG_ERROR(value) (SERCOM_USART_INT_INTFLAG_ERROR_Msk & ((value) << SERCOM_USART_INT_INTFLAG_ERROR_Pos))
+#define SERCOM_USART_INT_INTFLAG_Msk          _U_(0xBF)                                            /**< (SERCOM_USART_INT_INTFLAG) Register Mask  */
+
+
+/* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM Status -------- */
+#define SERCOM_I2CM_STATUS_RESETVALUE         _U_(0x00)                                            /**<  (SERCOM_I2CM_STATUS) I2CM Status  Reset Value */
+
+#define SERCOM_I2CM_STATUS_BUSERR_Pos         _U_(0)                                               /**< (SERCOM_I2CM_STATUS) Bus Error Position */
+#define SERCOM_I2CM_STATUS_BUSERR_Msk         (_U_(0x1) << SERCOM_I2CM_STATUS_BUSERR_Pos)          /**< (SERCOM_I2CM_STATUS) Bus Error Mask */
+#define SERCOM_I2CM_STATUS_BUSERR(value)      (SERCOM_I2CM_STATUS_BUSERR_Msk & ((value) << SERCOM_I2CM_STATUS_BUSERR_Pos))
+#define SERCOM_I2CM_STATUS_ARBLOST_Pos        _U_(1)                                               /**< (SERCOM_I2CM_STATUS) Arbitration Lost Position */
+#define SERCOM_I2CM_STATUS_ARBLOST_Msk        (_U_(0x1) << SERCOM_I2CM_STATUS_ARBLOST_Pos)         /**< (SERCOM_I2CM_STATUS) Arbitration Lost Mask */
+#define SERCOM_I2CM_STATUS_ARBLOST(value)     (SERCOM_I2CM_STATUS_ARBLOST_Msk & ((value) << SERCOM_I2CM_STATUS_ARBLOST_Pos))
+#define SERCOM_I2CM_STATUS_RXNACK_Pos         _U_(2)                                               /**< (SERCOM_I2CM_STATUS) Received Not Acknowledge Position */
+#define SERCOM_I2CM_STATUS_RXNACK_Msk         (_U_(0x1) << SERCOM_I2CM_STATUS_RXNACK_Pos)          /**< (SERCOM_I2CM_STATUS) Received Not Acknowledge Mask */
+#define SERCOM_I2CM_STATUS_RXNACK(value)      (SERCOM_I2CM_STATUS_RXNACK_Msk & ((value) << SERCOM_I2CM_STATUS_RXNACK_Pos))
+#define SERCOM_I2CM_STATUS_BUSSTATE_Pos       _U_(4)                                               /**< (SERCOM_I2CM_STATUS) Bus State Position */
+#define SERCOM_I2CM_STATUS_BUSSTATE_Msk       (_U_(0x3) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)        /**< (SERCOM_I2CM_STATUS) Bus State Mask */
+#define SERCOM_I2CM_STATUS_BUSSTATE(value)    (SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos))
+#define SERCOM_I2CM_STATUS_LOWTOUT_Pos        _U_(6)                                               /**< (SERCOM_I2CM_STATUS) SCL Low Timeout Position */
+#define SERCOM_I2CM_STATUS_LOWTOUT_Msk        (_U_(0x1) << SERCOM_I2CM_STATUS_LOWTOUT_Pos)         /**< (SERCOM_I2CM_STATUS) SCL Low Timeout Mask */
+#define SERCOM_I2CM_STATUS_LOWTOUT(value)     (SERCOM_I2CM_STATUS_LOWTOUT_Msk & ((value) << SERCOM_I2CM_STATUS_LOWTOUT_Pos))
+#define SERCOM_I2CM_STATUS_CLKHOLD_Pos        _U_(7)                                               /**< (SERCOM_I2CM_STATUS) Clock Hold Position */
+#define SERCOM_I2CM_STATUS_CLKHOLD_Msk        (_U_(0x1) << SERCOM_I2CM_STATUS_CLKHOLD_Pos)         /**< (SERCOM_I2CM_STATUS) Clock Hold Mask */
+#define SERCOM_I2CM_STATUS_CLKHOLD(value)     (SERCOM_I2CM_STATUS_CLKHOLD_Msk & ((value) << SERCOM_I2CM_STATUS_CLKHOLD_Pos))
+#define SERCOM_I2CM_STATUS_MEXTTOUT_Pos       _U_(8)                                               /**< (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout Position */
+#define SERCOM_I2CM_STATUS_MEXTTOUT_Msk       (_U_(0x1) << SERCOM_I2CM_STATUS_MEXTTOUT_Pos)        /**< (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout Mask */
+#define SERCOM_I2CM_STATUS_MEXTTOUT(value)    (SERCOM_I2CM_STATUS_MEXTTOUT_Msk & ((value) << SERCOM_I2CM_STATUS_MEXTTOUT_Pos))
+#define SERCOM_I2CM_STATUS_SEXTTOUT_Pos       _U_(9)                                               /**< (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout Position */
+#define SERCOM_I2CM_STATUS_SEXTTOUT_Msk       (_U_(0x1) << SERCOM_I2CM_STATUS_SEXTTOUT_Pos)        /**< (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout Mask */
+#define SERCOM_I2CM_STATUS_SEXTTOUT(value)    (SERCOM_I2CM_STATUS_SEXTTOUT_Msk & ((value) << SERCOM_I2CM_STATUS_SEXTTOUT_Pos))
+#define SERCOM_I2CM_STATUS_LENERR_Pos         _U_(10)                                              /**< (SERCOM_I2CM_STATUS) Length Error Position */
+#define SERCOM_I2CM_STATUS_LENERR_Msk         (_U_(0x1) << SERCOM_I2CM_STATUS_LENERR_Pos)          /**< (SERCOM_I2CM_STATUS) Length Error Mask */
+#define SERCOM_I2CM_STATUS_LENERR(value)      (SERCOM_I2CM_STATUS_LENERR_Msk & ((value) << SERCOM_I2CM_STATUS_LENERR_Pos))
+#define SERCOM_I2CM_STATUS_Msk                _U_(0x07F7)                                          /**< (SERCOM_I2CM_STATUS) Register Mask  */
+
+
+/* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS Status -------- */
+#define SERCOM_I2CS_STATUS_RESETVALUE         _U_(0x00)                                            /**<  (SERCOM_I2CS_STATUS) I2CS Status  Reset Value */
+
+#define SERCOM_I2CS_STATUS_BUSERR_Pos         _U_(0)                                               /**< (SERCOM_I2CS_STATUS) Bus Error Position */
+#define SERCOM_I2CS_STATUS_BUSERR_Msk         (_U_(0x1) << SERCOM_I2CS_STATUS_BUSERR_Pos)          /**< (SERCOM_I2CS_STATUS) Bus Error Mask */
+#define SERCOM_I2CS_STATUS_BUSERR(value)      (SERCOM_I2CS_STATUS_BUSERR_Msk & ((value) << SERCOM_I2CS_STATUS_BUSERR_Pos))
+#define SERCOM_I2CS_STATUS_COLL_Pos           _U_(1)                                               /**< (SERCOM_I2CS_STATUS) Transmit Collision Position */
+#define SERCOM_I2CS_STATUS_COLL_Msk           (_U_(0x1) << SERCOM_I2CS_STATUS_COLL_Pos)            /**< (SERCOM_I2CS_STATUS) Transmit Collision Mask */
+#define SERCOM_I2CS_STATUS_COLL(value)        (SERCOM_I2CS_STATUS_COLL_Msk & ((value) << SERCOM_I2CS_STATUS_COLL_Pos))
+#define SERCOM_I2CS_STATUS_RXNACK_Pos         _U_(2)                                               /**< (SERCOM_I2CS_STATUS) Received Not Acknowledge Position */
+#define SERCOM_I2CS_STATUS_RXNACK_Msk         (_U_(0x1) << SERCOM_I2CS_STATUS_RXNACK_Pos)          /**< (SERCOM_I2CS_STATUS) Received Not Acknowledge Mask */
+#define SERCOM_I2CS_STATUS_RXNACK(value)      (SERCOM_I2CS_STATUS_RXNACK_Msk & ((value) << SERCOM_I2CS_STATUS_RXNACK_Pos))
+#define SERCOM_I2CS_STATUS_DIR_Pos            _U_(3)                                               /**< (SERCOM_I2CS_STATUS) Read/Write Direction Position */
+#define SERCOM_I2CS_STATUS_DIR_Msk            (_U_(0x1) << SERCOM_I2CS_STATUS_DIR_Pos)             /**< (SERCOM_I2CS_STATUS) Read/Write Direction Mask */
+#define SERCOM_I2CS_STATUS_DIR(value)         (SERCOM_I2CS_STATUS_DIR_Msk & ((value) << SERCOM_I2CS_STATUS_DIR_Pos))
+#define SERCOM_I2CS_STATUS_SR_Pos             _U_(4)                                               /**< (SERCOM_I2CS_STATUS) Repeated Start Position */
+#define SERCOM_I2CS_STATUS_SR_Msk             (_U_(0x1) << SERCOM_I2CS_STATUS_SR_Pos)              /**< (SERCOM_I2CS_STATUS) Repeated Start Mask */
+#define SERCOM_I2CS_STATUS_SR(value)          (SERCOM_I2CS_STATUS_SR_Msk & ((value) << SERCOM_I2CS_STATUS_SR_Pos))
+#define SERCOM_I2CS_STATUS_LOWTOUT_Pos        _U_(6)                                               /**< (SERCOM_I2CS_STATUS) SCL Low Timeout Position */
+#define SERCOM_I2CS_STATUS_LOWTOUT_Msk        (_U_(0x1) << SERCOM_I2CS_STATUS_LOWTOUT_Pos)         /**< (SERCOM_I2CS_STATUS) SCL Low Timeout Mask */
+#define SERCOM_I2CS_STATUS_LOWTOUT(value)     (SERCOM_I2CS_STATUS_LOWTOUT_Msk & ((value) << SERCOM_I2CS_STATUS_LOWTOUT_Pos))
+#define SERCOM_I2CS_STATUS_CLKHOLD_Pos        _U_(7)                                               /**< (SERCOM_I2CS_STATUS) Clock Hold Position */
+#define SERCOM_I2CS_STATUS_CLKHOLD_Msk        (_U_(0x1) << SERCOM_I2CS_STATUS_CLKHOLD_Pos)         /**< (SERCOM_I2CS_STATUS) Clock Hold Mask */
+#define SERCOM_I2CS_STATUS_CLKHOLD(value)     (SERCOM_I2CS_STATUS_CLKHOLD_Msk & ((value) << SERCOM_I2CS_STATUS_CLKHOLD_Pos))
+#define SERCOM_I2CS_STATUS_SEXTTOUT_Pos       _U_(9)                                               /**< (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout Position */
+#define SERCOM_I2CS_STATUS_SEXTTOUT_Msk       (_U_(0x1) << SERCOM_I2CS_STATUS_SEXTTOUT_Pos)        /**< (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout Mask */
+#define SERCOM_I2CS_STATUS_SEXTTOUT(value)    (SERCOM_I2CS_STATUS_SEXTTOUT_Msk & ((value) << SERCOM_I2CS_STATUS_SEXTTOUT_Pos))
+#define SERCOM_I2CS_STATUS_HS_Pos             _U_(10)                                              /**< (SERCOM_I2CS_STATUS) High Speed Position */
+#define SERCOM_I2CS_STATUS_HS_Msk             (_U_(0x1) << SERCOM_I2CS_STATUS_HS_Pos)              /**< (SERCOM_I2CS_STATUS) High Speed Mask */
+#define SERCOM_I2CS_STATUS_HS(value)          (SERCOM_I2CS_STATUS_HS_Msk & ((value) << SERCOM_I2CS_STATUS_HS_Pos))
+#define SERCOM_I2CS_STATUS_LENERR_Pos         _U_(11)                                              /**< (SERCOM_I2CS_STATUS) Transaction Length Error Position */
+#define SERCOM_I2CS_STATUS_LENERR_Msk         (_U_(0x1) << SERCOM_I2CS_STATUS_LENERR_Pos)          /**< (SERCOM_I2CS_STATUS) Transaction Length Error Mask */
+#define SERCOM_I2CS_STATUS_LENERR(value)      (SERCOM_I2CS_STATUS_LENERR_Msk & ((value) << SERCOM_I2CS_STATUS_LENERR_Pos))
+#define SERCOM_I2CS_STATUS_Msk                _U_(0x0EDF)                                          /**< (SERCOM_I2CS_STATUS) Register Mask  */
+
+
+/* -------- SERCOM_SPIM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPIM Status -------- */
+#define SERCOM_SPIM_STATUS_RESETVALUE         _U_(0x00)                                            /**<  (SERCOM_SPIM_STATUS) SPIM Status  Reset Value */
+
+#define SERCOM_SPIM_STATUS_BUFOVF_Pos         _U_(2)                                               /**< (SERCOM_SPIM_STATUS) Buffer Overflow Position */
+#define SERCOM_SPIM_STATUS_BUFOVF_Msk         (_U_(0x1) << SERCOM_SPIM_STATUS_BUFOVF_Pos)          /**< (SERCOM_SPIM_STATUS) Buffer Overflow Mask */
+#define SERCOM_SPIM_STATUS_BUFOVF(value)      (SERCOM_SPIM_STATUS_BUFOVF_Msk & ((value) << SERCOM_SPIM_STATUS_BUFOVF_Pos))
+#define SERCOM_SPIM_STATUS_LENERR_Pos         _U_(11)                                              /**< (SERCOM_SPIM_STATUS) Transaction Length Error Position */
+#define SERCOM_SPIM_STATUS_LENERR_Msk         (_U_(0x1) << SERCOM_SPIM_STATUS_LENERR_Pos)          /**< (SERCOM_SPIM_STATUS) Transaction Length Error Mask */
+#define SERCOM_SPIM_STATUS_LENERR(value)      (SERCOM_SPIM_STATUS_LENERR_Msk & ((value) << SERCOM_SPIM_STATUS_LENERR_Pos))
+#define SERCOM_SPIM_STATUS_Msk                _U_(0x0804)                                          /**< (SERCOM_SPIM_STATUS) Register Mask  */
+
+
+/* -------- SERCOM_SPIS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPIS Status -------- */
+#define SERCOM_SPIS_STATUS_RESETVALUE         _U_(0x00)                                            /**<  (SERCOM_SPIS_STATUS) SPIS Status  Reset Value */
+
+#define SERCOM_SPIS_STATUS_BUFOVF_Pos         _U_(2)                                               /**< (SERCOM_SPIS_STATUS) Buffer Overflow Position */
+#define SERCOM_SPIS_STATUS_BUFOVF_Msk         (_U_(0x1) << SERCOM_SPIS_STATUS_BUFOVF_Pos)          /**< (SERCOM_SPIS_STATUS) Buffer Overflow Mask */
+#define SERCOM_SPIS_STATUS_BUFOVF(value)      (SERCOM_SPIS_STATUS_BUFOVF_Msk & ((value) << SERCOM_SPIS_STATUS_BUFOVF_Pos))
+#define SERCOM_SPIS_STATUS_LENERR_Pos         _U_(11)                                              /**< (SERCOM_SPIS_STATUS) Transaction Length Error Position */
+#define SERCOM_SPIS_STATUS_LENERR_Msk         (_U_(0x1) << SERCOM_SPIS_STATUS_LENERR_Pos)          /**< (SERCOM_SPIS_STATUS) Transaction Length Error Mask */
+#define SERCOM_SPIS_STATUS_LENERR(value)      (SERCOM_SPIS_STATUS_LENERR_Msk & ((value) << SERCOM_SPIS_STATUS_LENERR_Pos))
+#define SERCOM_SPIS_STATUS_Msk                _U_(0x0804)                                          /**< (SERCOM_SPIS_STATUS) Register Mask  */
+
+
+/* -------- SERCOM_USART_EXT_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART_EXT Status -------- */
+#define SERCOM_USART_EXT_STATUS_RESETVALUE    _U_(0x00)                                            /**<  (SERCOM_USART_EXT_STATUS) USART_EXT Status  Reset Value */
+
+#define SERCOM_USART_EXT_STATUS_PERR_Pos      _U_(0)                                               /**< (SERCOM_USART_EXT_STATUS) Parity Error Position */
+#define SERCOM_USART_EXT_STATUS_PERR_Msk      (_U_(0x1) << SERCOM_USART_EXT_STATUS_PERR_Pos)       /**< (SERCOM_USART_EXT_STATUS) Parity Error Mask */
+#define SERCOM_USART_EXT_STATUS_PERR(value)   (SERCOM_USART_EXT_STATUS_PERR_Msk & ((value) << SERCOM_USART_EXT_STATUS_PERR_Pos))
+#define SERCOM_USART_EXT_STATUS_FERR_Pos      _U_(1)                                               /**< (SERCOM_USART_EXT_STATUS) Frame Error Position */
+#define SERCOM_USART_EXT_STATUS_FERR_Msk      (_U_(0x1) << SERCOM_USART_EXT_STATUS_FERR_Pos)       /**< (SERCOM_USART_EXT_STATUS) Frame Error Mask */
+#define SERCOM_USART_EXT_STATUS_FERR(value)   (SERCOM_USART_EXT_STATUS_FERR_Msk & ((value) << SERCOM_USART_EXT_STATUS_FERR_Pos))
+#define SERCOM_USART_EXT_STATUS_BUFOVF_Pos    _U_(2)                                               /**< (SERCOM_USART_EXT_STATUS) Buffer Overflow Position */
+#define SERCOM_USART_EXT_STATUS_BUFOVF_Msk    (_U_(0x1) << SERCOM_USART_EXT_STATUS_BUFOVF_Pos)     /**< (SERCOM_USART_EXT_STATUS) Buffer Overflow Mask */
+#define SERCOM_USART_EXT_STATUS_BUFOVF(value) (SERCOM_USART_EXT_STATUS_BUFOVF_Msk & ((value) << SERCOM_USART_EXT_STATUS_BUFOVF_Pos))
+#define SERCOM_USART_EXT_STATUS_CTS_Pos       _U_(3)                                               /**< (SERCOM_USART_EXT_STATUS) Clear To Send Position */
+#define SERCOM_USART_EXT_STATUS_CTS_Msk       (_U_(0x1) << SERCOM_USART_EXT_STATUS_CTS_Pos)        /**< (SERCOM_USART_EXT_STATUS) Clear To Send Mask */
+#define SERCOM_USART_EXT_STATUS_CTS(value)    (SERCOM_USART_EXT_STATUS_CTS_Msk & ((value) << SERCOM_USART_EXT_STATUS_CTS_Pos))
+#define SERCOM_USART_EXT_STATUS_ISF_Pos       _U_(4)                                               /**< (SERCOM_USART_EXT_STATUS) Inconsistent Sync Field Position */
+#define SERCOM_USART_EXT_STATUS_ISF_Msk       (_U_(0x1) << SERCOM_USART_EXT_STATUS_ISF_Pos)        /**< (SERCOM_USART_EXT_STATUS) Inconsistent Sync Field Mask */
+#define SERCOM_USART_EXT_STATUS_ISF(value)    (SERCOM_USART_EXT_STATUS_ISF_Msk & ((value) << SERCOM_USART_EXT_STATUS_ISF_Pos))
+#define SERCOM_USART_EXT_STATUS_COLL_Pos      _U_(5)                                               /**< (SERCOM_USART_EXT_STATUS) Collision Detected Position */
+#define SERCOM_USART_EXT_STATUS_COLL_Msk      (_U_(0x1) << SERCOM_USART_EXT_STATUS_COLL_Pos)       /**< (SERCOM_USART_EXT_STATUS) Collision Detected Mask */
+#define SERCOM_USART_EXT_STATUS_COLL(value)   (SERCOM_USART_EXT_STATUS_COLL_Msk & ((value) << SERCOM_USART_EXT_STATUS_COLL_Pos))
+#define SERCOM_USART_EXT_STATUS_TXE_Pos       _U_(6)                                               /**< (SERCOM_USART_EXT_STATUS) Transmitter Empty Position */
+#define SERCOM_USART_EXT_STATUS_TXE_Msk       (_U_(0x1) << SERCOM_USART_EXT_STATUS_TXE_Pos)        /**< (SERCOM_USART_EXT_STATUS) Transmitter Empty Mask */
+#define SERCOM_USART_EXT_STATUS_TXE(value)    (SERCOM_USART_EXT_STATUS_TXE_Msk & ((value) << SERCOM_USART_EXT_STATUS_TXE_Pos))
+#define SERCOM_USART_EXT_STATUS_ITER_Pos      _U_(7)                                               /**< (SERCOM_USART_EXT_STATUS) Maximum Number of Repetitions Reached Position */
+#define SERCOM_USART_EXT_STATUS_ITER_Msk      (_U_(0x1) << SERCOM_USART_EXT_STATUS_ITER_Pos)       /**< (SERCOM_USART_EXT_STATUS) Maximum Number of Repetitions Reached Mask */
+#define SERCOM_USART_EXT_STATUS_ITER(value)   (SERCOM_USART_EXT_STATUS_ITER_Msk & ((value) << SERCOM_USART_EXT_STATUS_ITER_Pos))
+#define SERCOM_USART_EXT_STATUS_Msk           _U_(0x00FF)                                          /**< (SERCOM_USART_EXT_STATUS) Register Mask  */
+
+
+/* -------- SERCOM_USART_INT_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART_INT Status -------- */
+#define SERCOM_USART_INT_STATUS_RESETVALUE    _U_(0x00)                                            /**<  (SERCOM_USART_INT_STATUS) USART_INT Status  Reset Value */
+
+#define SERCOM_USART_INT_STATUS_PERR_Pos      _U_(0)                                               /**< (SERCOM_USART_INT_STATUS) Parity Error Position */
+#define SERCOM_USART_INT_STATUS_PERR_Msk      (_U_(0x1) << SERCOM_USART_INT_STATUS_PERR_Pos)       /**< (SERCOM_USART_INT_STATUS) Parity Error Mask */
+#define SERCOM_USART_INT_STATUS_PERR(value)   (SERCOM_USART_INT_STATUS_PERR_Msk & ((value) << SERCOM_USART_INT_STATUS_PERR_Pos))
+#define SERCOM_USART_INT_STATUS_FERR_Pos      _U_(1)                                               /**< (SERCOM_USART_INT_STATUS) Frame Error Position */
+#define SERCOM_USART_INT_STATUS_FERR_Msk      (_U_(0x1) << SERCOM_USART_INT_STATUS_FERR_Pos)       /**< (SERCOM_USART_INT_STATUS) Frame Error Mask */
+#define SERCOM_USART_INT_STATUS_FERR(value)   (SERCOM_USART_INT_STATUS_FERR_Msk & ((value) << SERCOM_USART_INT_STATUS_FERR_Pos))
+#define SERCOM_USART_INT_STATUS_BUFOVF_Pos    _U_(2)                                               /**< (SERCOM_USART_INT_STATUS) Buffer Overflow Position */
+#define SERCOM_USART_INT_STATUS_BUFOVF_Msk    (_U_(0x1) << SERCOM_USART_INT_STATUS_BUFOVF_Pos)     /**< (SERCOM_USART_INT_STATUS) Buffer Overflow Mask */
+#define SERCOM_USART_INT_STATUS_BUFOVF(value) (SERCOM_USART_INT_STATUS_BUFOVF_Msk & ((value) << SERCOM_USART_INT_STATUS_BUFOVF_Pos))
+#define SERCOM_USART_INT_STATUS_CTS_Pos       _U_(3)                                               /**< (SERCOM_USART_INT_STATUS) Clear To Send Position */
+#define SERCOM_USART_INT_STATUS_CTS_Msk       (_U_(0x1) << SERCOM_USART_INT_STATUS_CTS_Pos)        /**< (SERCOM_USART_INT_STATUS) Clear To Send Mask */
+#define SERCOM_USART_INT_STATUS_CTS(value)    (SERCOM_USART_INT_STATUS_CTS_Msk & ((value) << SERCOM_USART_INT_STATUS_CTS_Pos))
+#define SERCOM_USART_INT_STATUS_ISF_Pos       _U_(4)                                               /**< (SERCOM_USART_INT_STATUS) Inconsistent Sync Field Position */
+#define SERCOM_USART_INT_STATUS_ISF_Msk       (_U_(0x1) << SERCOM_USART_INT_STATUS_ISF_Pos)        /**< (SERCOM_USART_INT_STATUS) Inconsistent Sync Field Mask */
+#define SERCOM_USART_INT_STATUS_ISF(value)    (SERCOM_USART_INT_STATUS_ISF_Msk & ((value) << SERCOM_USART_INT_STATUS_ISF_Pos))
+#define SERCOM_USART_INT_STATUS_COLL_Pos      _U_(5)                                               /**< (SERCOM_USART_INT_STATUS) Collision Detected Position */
+#define SERCOM_USART_INT_STATUS_COLL_Msk      (_U_(0x1) << SERCOM_USART_INT_STATUS_COLL_Pos)       /**< (SERCOM_USART_INT_STATUS) Collision Detected Mask */
+#define SERCOM_USART_INT_STATUS_COLL(value)   (SERCOM_USART_INT_STATUS_COLL_Msk & ((value) << SERCOM_USART_INT_STATUS_COLL_Pos))
+#define SERCOM_USART_INT_STATUS_TXE_Pos       _U_(6)                                               /**< (SERCOM_USART_INT_STATUS) Transmitter Empty Position */
+#define SERCOM_USART_INT_STATUS_TXE_Msk       (_U_(0x1) << SERCOM_USART_INT_STATUS_TXE_Pos)        /**< (SERCOM_USART_INT_STATUS) Transmitter Empty Mask */
+#define SERCOM_USART_INT_STATUS_TXE(value)    (SERCOM_USART_INT_STATUS_TXE_Msk & ((value) << SERCOM_USART_INT_STATUS_TXE_Pos))
+#define SERCOM_USART_INT_STATUS_ITER_Pos      _U_(7)                                               /**< (SERCOM_USART_INT_STATUS) Maximum Number of Repetitions Reached Position */
+#define SERCOM_USART_INT_STATUS_ITER_Msk      (_U_(0x1) << SERCOM_USART_INT_STATUS_ITER_Pos)       /**< (SERCOM_USART_INT_STATUS) Maximum Number of Repetitions Reached Mask */
+#define SERCOM_USART_INT_STATUS_ITER(value)   (SERCOM_USART_INT_STATUS_ITER_Msk & ((value) << SERCOM_USART_INT_STATUS_ITER_Pos))
+#define SERCOM_USART_INT_STATUS_Msk           _U_(0x00FF)                                          /**< (SERCOM_USART_INT_STATUS) Register Mask  */
+
+
+/* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) ( R/ 32) I2CM Synchronization Busy -------- */
+#define SERCOM_I2CM_SYNCBUSY_RESETVALUE       _U_(0x00)                                            /**<  (SERCOM_I2CM_SYNCBUSY) I2CM Synchronization Busy  Reset Value */
+
+#define SERCOM_I2CM_SYNCBUSY_SWRST_Pos        _U_(0)                                               /**< (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy Position */
+#define SERCOM_I2CM_SYNCBUSY_SWRST_Msk        (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_SWRST_Pos)         /**< (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy Mask */
+#define SERCOM_I2CM_SYNCBUSY_SWRST(value)     (SERCOM_I2CM_SYNCBUSY_SWRST_Msk & ((value) << SERCOM_I2CM_SYNCBUSY_SWRST_Pos))
+#define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos       _U_(1)                                               /**< (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy Position */
+#define SERCOM_I2CM_SYNCBUSY_ENABLE_Msk       (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos)        /**< (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy Mask */
+#define SERCOM_I2CM_SYNCBUSY_ENABLE(value)    (SERCOM_I2CM_SYNCBUSY_ENABLE_Msk & ((value) << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos))
+#define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos        _U_(2)                                               /**< (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy Position */
+#define SERCOM_I2CM_SYNCBUSY_SYSOP_Msk        (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos)         /**< (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy Mask */
+#define SERCOM_I2CM_SYNCBUSY_SYSOP(value)     (SERCOM_I2CM_SYNCBUSY_SYSOP_Msk & ((value) << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos))
+#define SERCOM_I2CM_SYNCBUSY_LENGTH_Pos       _U_(4)                                               /**< (SERCOM_I2CM_SYNCBUSY) Length Synchronization Busy Position */
+#define SERCOM_I2CM_SYNCBUSY_LENGTH_Msk       (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_LENGTH_Pos)        /**< (SERCOM_I2CM_SYNCBUSY) Length Synchronization Busy Mask */
+#define SERCOM_I2CM_SYNCBUSY_LENGTH(value)    (SERCOM_I2CM_SYNCBUSY_LENGTH_Msk & ((value) << SERCOM_I2CM_SYNCBUSY_LENGTH_Pos))
+#define SERCOM_I2CM_SYNCBUSY_Msk              _U_(0x00000017)                                      /**< (SERCOM_I2CM_SYNCBUSY) Register Mask  */
+
+
+/* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) ( R/ 32) I2CS Synchronization Busy -------- */
+#define SERCOM_I2CS_SYNCBUSY_RESETVALUE       _U_(0x00)                                            /**<  (SERCOM_I2CS_SYNCBUSY) I2CS Synchronization Busy  Reset Value */
+
+#define SERCOM_I2CS_SYNCBUSY_SWRST_Pos        _U_(0)                                               /**< (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy Position */
+#define SERCOM_I2CS_SYNCBUSY_SWRST_Msk        (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_SWRST_Pos)         /**< (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy Mask */
+#define SERCOM_I2CS_SYNCBUSY_SWRST(value)     (SERCOM_I2CS_SYNCBUSY_SWRST_Msk & ((value) << SERCOM_I2CS_SYNCBUSY_SWRST_Pos))
+#define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos       _U_(1)                                               /**< (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy Position */
+#define SERCOM_I2CS_SYNCBUSY_ENABLE_Msk       (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos)        /**< (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy Mask */
+#define SERCOM_I2CS_SYNCBUSY_ENABLE(value)    (SERCOM_I2CS_SYNCBUSY_ENABLE_Msk & ((value) << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos))
+#define SERCOM_I2CS_SYNCBUSY_LENGTH_Pos       _U_(4)                                               /**< (SERCOM_I2CS_SYNCBUSY) Length Synchronization Busy Position */
+#define SERCOM_I2CS_SYNCBUSY_LENGTH_Msk       (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_LENGTH_Pos)        /**< (SERCOM_I2CS_SYNCBUSY) Length Synchronization Busy Mask */
+#define SERCOM_I2CS_SYNCBUSY_LENGTH(value)    (SERCOM_I2CS_SYNCBUSY_LENGTH_Msk & ((value) << SERCOM_I2CS_SYNCBUSY_LENGTH_Pos))
+#define SERCOM_I2CS_SYNCBUSY_Msk              _U_(0x00000013)                                      /**< (SERCOM_I2CS_SYNCBUSY) Register Mask  */
+
+
+/* -------- SERCOM_SPIM_SYNCBUSY : (SERCOM Offset: 0x1C) ( R/ 32) SPIM Synchronization Busy -------- */
+#define SERCOM_SPIM_SYNCBUSY_RESETVALUE       _U_(0x00)                                            /**<  (SERCOM_SPIM_SYNCBUSY) SPIM Synchronization Busy  Reset Value */
+
+#define SERCOM_SPIM_SYNCBUSY_SWRST_Pos        _U_(0)                                               /**< (SERCOM_SPIM_SYNCBUSY) Software Reset Synchronization Busy Position */
+#define SERCOM_SPIM_SYNCBUSY_SWRST_Msk        (_U_(0x1) << SERCOM_SPIM_SYNCBUSY_SWRST_Pos)         /**< (SERCOM_SPIM_SYNCBUSY) Software Reset Synchronization Busy Mask */
+#define SERCOM_SPIM_SYNCBUSY_SWRST(value)     (SERCOM_SPIM_SYNCBUSY_SWRST_Msk & ((value) << SERCOM_SPIM_SYNCBUSY_SWRST_Pos))
+#define SERCOM_SPIM_SYNCBUSY_ENABLE_Pos       _U_(1)                                               /**< (SERCOM_SPIM_SYNCBUSY) SERCOM Enable Synchronization Busy Position */
+#define SERCOM_SPIM_SYNCBUSY_ENABLE_Msk       (_U_(0x1) << SERCOM_SPIM_SYNCBUSY_ENABLE_Pos)        /**< (SERCOM_SPIM_SYNCBUSY) SERCOM Enable Synchronization Busy Mask */
+#define SERCOM_SPIM_SYNCBUSY_ENABLE(value)    (SERCOM_SPIM_SYNCBUSY_ENABLE_Msk & ((value) << SERCOM_SPIM_SYNCBUSY_ENABLE_Pos))
+#define SERCOM_SPIM_SYNCBUSY_CTRLB_Pos        _U_(2)                                               /**< (SERCOM_SPIM_SYNCBUSY) CTRLB Synchronization Busy Position */
+#define SERCOM_SPIM_SYNCBUSY_CTRLB_Msk        (_U_(0x1) << SERCOM_SPIM_SYNCBUSY_CTRLB_Pos)         /**< (SERCOM_SPIM_SYNCBUSY) CTRLB Synchronization Busy Mask */
+#define SERCOM_SPIM_SYNCBUSY_CTRLB(value)     (SERCOM_SPIM_SYNCBUSY_CTRLB_Msk & ((value) << SERCOM_SPIM_SYNCBUSY_CTRLB_Pos))
+#define SERCOM_SPIM_SYNCBUSY_LENGTH_Pos       _U_(4)                                               /**< (SERCOM_SPIM_SYNCBUSY) LENGTH Synchronization Busy Position */
+#define SERCOM_SPIM_SYNCBUSY_LENGTH_Msk       (_U_(0x1) << SERCOM_SPIM_SYNCBUSY_LENGTH_Pos)        /**< (SERCOM_SPIM_SYNCBUSY) LENGTH Synchronization Busy Mask */
+#define SERCOM_SPIM_SYNCBUSY_LENGTH(value)    (SERCOM_SPIM_SYNCBUSY_LENGTH_Msk & ((value) << SERCOM_SPIM_SYNCBUSY_LENGTH_Pos))
+#define SERCOM_SPIM_SYNCBUSY_Msk              _U_(0x00000017)                                      /**< (SERCOM_SPIM_SYNCBUSY) Register Mask  */
+
+
+/* -------- SERCOM_SPIS_SYNCBUSY : (SERCOM Offset: 0x1C) ( R/ 32) SPIS Synchronization Busy -------- */
+#define SERCOM_SPIS_SYNCBUSY_RESETVALUE       _U_(0x00)                                            /**<  (SERCOM_SPIS_SYNCBUSY) SPIS Synchronization Busy  Reset Value */
+
+#define SERCOM_SPIS_SYNCBUSY_SWRST_Pos        _U_(0)                                               /**< (SERCOM_SPIS_SYNCBUSY) Software Reset Synchronization Busy Position */
+#define SERCOM_SPIS_SYNCBUSY_SWRST_Msk        (_U_(0x1) << SERCOM_SPIS_SYNCBUSY_SWRST_Pos)         /**< (SERCOM_SPIS_SYNCBUSY) Software Reset Synchronization Busy Mask */
+#define SERCOM_SPIS_SYNCBUSY_SWRST(value)     (SERCOM_SPIS_SYNCBUSY_SWRST_Msk & ((value) << SERCOM_SPIS_SYNCBUSY_SWRST_Pos))
+#define SERCOM_SPIS_SYNCBUSY_ENABLE_Pos       _U_(1)                                               /**< (SERCOM_SPIS_SYNCBUSY) SERCOM Enable Synchronization Busy Position */
+#define SERCOM_SPIS_SYNCBUSY_ENABLE_Msk       (_U_(0x1) << SERCOM_SPIS_SYNCBUSY_ENABLE_Pos)        /**< (SERCOM_SPIS_SYNCBUSY) SERCOM Enable Synchronization Busy Mask */
+#define SERCOM_SPIS_SYNCBUSY_ENABLE(value)    (SERCOM_SPIS_SYNCBUSY_ENABLE_Msk & ((value) << SERCOM_SPIS_SYNCBUSY_ENABLE_Pos))
+#define SERCOM_SPIS_SYNCBUSY_CTRLB_Pos        _U_(2)                                               /**< (SERCOM_SPIS_SYNCBUSY) CTRLB Synchronization Busy Position */
+#define SERCOM_SPIS_SYNCBUSY_CTRLB_Msk        (_U_(0x1) << SERCOM_SPIS_SYNCBUSY_CTRLB_Pos)         /**< (SERCOM_SPIS_SYNCBUSY) CTRLB Synchronization Busy Mask */
+#define SERCOM_SPIS_SYNCBUSY_CTRLB(value)     (SERCOM_SPIS_SYNCBUSY_CTRLB_Msk & ((value) << SERCOM_SPIS_SYNCBUSY_CTRLB_Pos))
+#define SERCOM_SPIS_SYNCBUSY_LENGTH_Pos       _U_(4)                                               /**< (SERCOM_SPIS_SYNCBUSY) LENGTH Synchronization Busy Position */
+#define SERCOM_SPIS_SYNCBUSY_LENGTH_Msk       (_U_(0x1) << SERCOM_SPIS_SYNCBUSY_LENGTH_Pos)        /**< (SERCOM_SPIS_SYNCBUSY) LENGTH Synchronization Busy Mask */
+#define SERCOM_SPIS_SYNCBUSY_LENGTH(value)    (SERCOM_SPIS_SYNCBUSY_LENGTH_Msk & ((value) << SERCOM_SPIS_SYNCBUSY_LENGTH_Pos))
+#define SERCOM_SPIS_SYNCBUSY_Msk              _U_(0x00000017)                                      /**< (SERCOM_SPIS_SYNCBUSY) Register Mask  */
+
+
+/* -------- SERCOM_USART_EXT_SYNCBUSY : (SERCOM Offset: 0x1C) ( R/ 32) USART_EXT Synchronization Busy -------- */
+#define SERCOM_USART_EXT_SYNCBUSY_RESETVALUE  _U_(0x00)                                            /**<  (SERCOM_USART_EXT_SYNCBUSY) USART_EXT Synchronization Busy  Reset Value */
+
+#define SERCOM_USART_EXT_SYNCBUSY_SWRST_Pos   _U_(0)                                               /**< (SERCOM_USART_EXT_SYNCBUSY) Software Reset Synchronization Busy Position */
+#define SERCOM_USART_EXT_SYNCBUSY_SWRST_Msk   (_U_(0x1) << SERCOM_USART_EXT_SYNCBUSY_SWRST_Pos)    /**< (SERCOM_USART_EXT_SYNCBUSY) Software Reset Synchronization Busy Mask */
+#define SERCOM_USART_EXT_SYNCBUSY_SWRST(value) (SERCOM_USART_EXT_SYNCBUSY_SWRST_Msk & ((value) << SERCOM_USART_EXT_SYNCBUSY_SWRST_Pos))
+#define SERCOM_USART_EXT_SYNCBUSY_ENABLE_Pos  _U_(1)                                               /**< (SERCOM_USART_EXT_SYNCBUSY) SERCOM Enable Synchronization Busy Position */
+#define SERCOM_USART_EXT_SYNCBUSY_ENABLE_Msk  (_U_(0x1) << SERCOM_USART_EXT_SYNCBUSY_ENABLE_Pos)   /**< (SERCOM_USART_EXT_SYNCBUSY) SERCOM Enable Synchronization Busy Mask */
+#define SERCOM_USART_EXT_SYNCBUSY_ENABLE(value) (SERCOM_USART_EXT_SYNCBUSY_ENABLE_Msk & ((value) << SERCOM_USART_EXT_SYNCBUSY_ENABLE_Pos))
+#define SERCOM_USART_EXT_SYNCBUSY_CTRLB_Pos   _U_(2)                                               /**< (SERCOM_USART_EXT_SYNCBUSY) CTRLB Synchronization Busy Position */
+#define SERCOM_USART_EXT_SYNCBUSY_CTRLB_Msk   (_U_(0x1) << SERCOM_USART_EXT_SYNCBUSY_CTRLB_Pos)    /**< (SERCOM_USART_EXT_SYNCBUSY) CTRLB Synchronization Busy Mask */
+#define SERCOM_USART_EXT_SYNCBUSY_CTRLB(value) (SERCOM_USART_EXT_SYNCBUSY_CTRLB_Msk & ((value) << SERCOM_USART_EXT_SYNCBUSY_CTRLB_Pos))
+#define SERCOM_USART_EXT_SYNCBUSY_RXERRCNT_Pos _U_(3)                                               /**< (SERCOM_USART_EXT_SYNCBUSY) RXERRCNT Synchronization Busy Position */
+#define SERCOM_USART_EXT_SYNCBUSY_RXERRCNT_Msk (_U_(0x1) << SERCOM_USART_EXT_SYNCBUSY_RXERRCNT_Pos) /**< (SERCOM_USART_EXT_SYNCBUSY) RXERRCNT Synchronization Busy Mask */
+#define SERCOM_USART_EXT_SYNCBUSY_RXERRCNT(value) (SERCOM_USART_EXT_SYNCBUSY_RXERRCNT_Msk & ((value) << SERCOM_USART_EXT_SYNCBUSY_RXERRCNT_Pos))
+#define SERCOM_USART_EXT_SYNCBUSY_LENGTH_Pos  _U_(4)                                               /**< (SERCOM_USART_EXT_SYNCBUSY) LENGTH Synchronization Busy Position */
+#define SERCOM_USART_EXT_SYNCBUSY_LENGTH_Msk  (_U_(0x1) << SERCOM_USART_EXT_SYNCBUSY_LENGTH_Pos)   /**< (SERCOM_USART_EXT_SYNCBUSY) LENGTH Synchronization Busy Mask */
+#define SERCOM_USART_EXT_SYNCBUSY_LENGTH(value) (SERCOM_USART_EXT_SYNCBUSY_LENGTH_Msk & ((value) << SERCOM_USART_EXT_SYNCBUSY_LENGTH_Pos))
+#define SERCOM_USART_EXT_SYNCBUSY_Msk         _U_(0x0000001F)                                      /**< (SERCOM_USART_EXT_SYNCBUSY) Register Mask  */
+
+
+/* -------- SERCOM_USART_INT_SYNCBUSY : (SERCOM Offset: 0x1C) ( R/ 32) USART_INT Synchronization Busy -------- */
+#define SERCOM_USART_INT_SYNCBUSY_RESETVALUE  _U_(0x00)                                            /**<  (SERCOM_USART_INT_SYNCBUSY) USART_INT Synchronization Busy  Reset Value */
+
+#define SERCOM_USART_INT_SYNCBUSY_SWRST_Pos   _U_(0)                                               /**< (SERCOM_USART_INT_SYNCBUSY) Software Reset Synchronization Busy Position */
+#define SERCOM_USART_INT_SYNCBUSY_SWRST_Msk   (_U_(0x1) << SERCOM_USART_INT_SYNCBUSY_SWRST_Pos)    /**< (SERCOM_USART_INT_SYNCBUSY) Software Reset Synchronization Busy Mask */
+#define SERCOM_USART_INT_SYNCBUSY_SWRST(value) (SERCOM_USART_INT_SYNCBUSY_SWRST_Msk & ((value) << SERCOM_USART_INT_SYNCBUSY_SWRST_Pos))
+#define SERCOM_USART_INT_SYNCBUSY_ENABLE_Pos  _U_(1)                                               /**< (SERCOM_USART_INT_SYNCBUSY) SERCOM Enable Synchronization Busy Position */
+#define SERCOM_USART_INT_SYNCBUSY_ENABLE_Msk  (_U_(0x1) << SERCOM_USART_INT_SYNCBUSY_ENABLE_Pos)   /**< (SERCOM_USART_INT_SYNCBUSY) SERCOM Enable Synchronization Busy Mask */
+#define SERCOM_USART_INT_SYNCBUSY_ENABLE(value) (SERCOM_USART_INT_SYNCBUSY_ENABLE_Msk & ((value) << SERCOM_USART_INT_SYNCBUSY_ENABLE_Pos))
+#define SERCOM_USART_INT_SYNCBUSY_CTRLB_Pos   _U_(2)                                               /**< (SERCOM_USART_INT_SYNCBUSY) CTRLB Synchronization Busy Position */
+#define SERCOM_USART_INT_SYNCBUSY_CTRLB_Msk   (_U_(0x1) << SERCOM_USART_INT_SYNCBUSY_CTRLB_Pos)    /**< (SERCOM_USART_INT_SYNCBUSY) CTRLB Synchronization Busy Mask */
+#define SERCOM_USART_INT_SYNCBUSY_CTRLB(value) (SERCOM_USART_INT_SYNCBUSY_CTRLB_Msk & ((value) << SERCOM_USART_INT_SYNCBUSY_CTRLB_Pos))
+#define SERCOM_USART_INT_SYNCBUSY_RXERRCNT_Pos _U_(3)                                               /**< (SERCOM_USART_INT_SYNCBUSY) RXERRCNT Synchronization Busy Position */
+#define SERCOM_USART_INT_SYNCBUSY_RXERRCNT_Msk (_U_(0x1) << SERCOM_USART_INT_SYNCBUSY_RXERRCNT_Pos) /**< (SERCOM_USART_INT_SYNCBUSY) RXERRCNT Synchronization Busy Mask */
+#define SERCOM_USART_INT_SYNCBUSY_RXERRCNT(value) (SERCOM_USART_INT_SYNCBUSY_RXERRCNT_Msk & ((value) << SERCOM_USART_INT_SYNCBUSY_RXERRCNT_Pos))
+#define SERCOM_USART_INT_SYNCBUSY_LENGTH_Pos  _U_(4)                                               /**< (SERCOM_USART_INT_SYNCBUSY) LENGTH Synchronization Busy Position */
+#define SERCOM_USART_INT_SYNCBUSY_LENGTH_Msk  (_U_(0x1) << SERCOM_USART_INT_SYNCBUSY_LENGTH_Pos)   /**< (SERCOM_USART_INT_SYNCBUSY) LENGTH Synchronization Busy Mask */
+#define SERCOM_USART_INT_SYNCBUSY_LENGTH(value) (SERCOM_USART_INT_SYNCBUSY_LENGTH_Msk & ((value) << SERCOM_USART_INT_SYNCBUSY_LENGTH_Pos))
+#define SERCOM_USART_INT_SYNCBUSY_Msk         _U_(0x0000001F)                                      /**< (SERCOM_USART_INT_SYNCBUSY) Register Mask  */
+
+
+/* -------- SERCOM_USART_EXT_RXERRCNT : (SERCOM Offset: 0x20) ( R/ 8) USART_EXT Receive Error Count -------- */
+#define SERCOM_USART_EXT_RXERRCNT_RESETVALUE  _U_(0x00)                                            /**<  (SERCOM_USART_EXT_RXERRCNT) USART_EXT Receive Error Count  Reset Value */
+
+#define SERCOM_USART_EXT_RXERRCNT_RXERRCNT_Pos _U_(0)                                               /**< (SERCOM_USART_EXT_RXERRCNT) Receive Error Count Position */
+#define SERCOM_USART_EXT_RXERRCNT_RXERRCNT_Msk (_U_(0xFF) << SERCOM_USART_EXT_RXERRCNT_RXERRCNT_Pos) /**< (SERCOM_USART_EXT_RXERRCNT) Receive Error Count Mask */
+#define SERCOM_USART_EXT_RXERRCNT_RXERRCNT(value) (SERCOM_USART_EXT_RXERRCNT_RXERRCNT_Msk & ((value) << SERCOM_USART_EXT_RXERRCNT_RXERRCNT_Pos))
+#define SERCOM_USART_EXT_RXERRCNT_Msk         _U_(0xFF)                                            /**< (SERCOM_USART_EXT_RXERRCNT) Register Mask  */
+
+
+/* -------- SERCOM_USART_INT_RXERRCNT : (SERCOM Offset: 0x20) ( R/ 8) USART_INT Receive Error Count -------- */
+#define SERCOM_USART_INT_RXERRCNT_RESETVALUE  _U_(0x00)                                            /**<  (SERCOM_USART_INT_RXERRCNT) USART_INT Receive Error Count  Reset Value */
+
+#define SERCOM_USART_INT_RXERRCNT_RXERRCNT_Pos _U_(0)                                               /**< (SERCOM_USART_INT_RXERRCNT) Receive Error Count Position */
+#define SERCOM_USART_INT_RXERRCNT_RXERRCNT_Msk (_U_(0xFF) << SERCOM_USART_INT_RXERRCNT_RXERRCNT_Pos) /**< (SERCOM_USART_INT_RXERRCNT) Receive Error Count Mask */
+#define SERCOM_USART_INT_RXERRCNT_RXERRCNT(value) (SERCOM_USART_INT_RXERRCNT_RXERRCNT_Msk & ((value) << SERCOM_USART_INT_RXERRCNT_RXERRCNT_Pos))
+#define SERCOM_USART_INT_RXERRCNT_Msk         _U_(0xFF)                                            /**< (SERCOM_USART_INT_RXERRCNT) Register Mask  */
+
+
+/* -------- SERCOM_I2CS_LENGTH : (SERCOM Offset: 0x22) (R/W 16) I2CS Length -------- */
+#define SERCOM_I2CS_LENGTH_RESETVALUE         _U_(0x00)                                            /**<  (SERCOM_I2CS_LENGTH) I2CS Length  Reset Value */
+
+#define SERCOM_I2CS_LENGTH_LEN_Pos            _U_(0)                                               /**< (SERCOM_I2CS_LENGTH) Data Length Position */
+#define SERCOM_I2CS_LENGTH_LEN_Msk            (_U_(0xFF) << SERCOM_I2CS_LENGTH_LEN_Pos)            /**< (SERCOM_I2CS_LENGTH) Data Length Mask */
+#define SERCOM_I2CS_LENGTH_LEN(value)         (SERCOM_I2CS_LENGTH_LEN_Msk & ((value) << SERCOM_I2CS_LENGTH_LEN_Pos))
+#define SERCOM_I2CS_LENGTH_LENEN_Pos          _U_(8)                                               /**< (SERCOM_I2CS_LENGTH) Data Length Enable Position */
+#define SERCOM_I2CS_LENGTH_LENEN_Msk          (_U_(0x1) << SERCOM_I2CS_LENGTH_LENEN_Pos)           /**< (SERCOM_I2CS_LENGTH) Data Length Enable Mask */
+#define SERCOM_I2CS_LENGTH_LENEN(value)       (SERCOM_I2CS_LENGTH_LENEN_Msk & ((value) << SERCOM_I2CS_LENGTH_LENEN_Pos))
+#define SERCOM_I2CS_LENGTH_Msk                _U_(0x01FF)                                          /**< (SERCOM_I2CS_LENGTH) Register Mask  */
+
+
+/* -------- SERCOM_SPIM_LENGTH : (SERCOM Offset: 0x22) (R/W 16) SPIM Length -------- */
+#define SERCOM_SPIM_LENGTH_RESETVALUE         _U_(0x00)                                            /**<  (SERCOM_SPIM_LENGTH) SPIM Length  Reset Value */
+
+#define SERCOM_SPIM_LENGTH_LEN_Pos            _U_(0)                                               /**< (SERCOM_SPIM_LENGTH) Data Length Position */
+#define SERCOM_SPIM_LENGTH_LEN_Msk            (_U_(0xFF) << SERCOM_SPIM_LENGTH_LEN_Pos)            /**< (SERCOM_SPIM_LENGTH) Data Length Mask */
+#define SERCOM_SPIM_LENGTH_LEN(value)         (SERCOM_SPIM_LENGTH_LEN_Msk & ((value) << SERCOM_SPIM_LENGTH_LEN_Pos))
+#define SERCOM_SPIM_LENGTH_LENEN_Pos          _U_(8)                                               /**< (SERCOM_SPIM_LENGTH) Data Length Enable Position */
+#define SERCOM_SPIM_LENGTH_LENEN_Msk          (_U_(0x1) << SERCOM_SPIM_LENGTH_LENEN_Pos)           /**< (SERCOM_SPIM_LENGTH) Data Length Enable Mask */
+#define SERCOM_SPIM_LENGTH_LENEN(value)       (SERCOM_SPIM_LENGTH_LENEN_Msk & ((value) << SERCOM_SPIM_LENGTH_LENEN_Pos))
+#define SERCOM_SPIM_LENGTH_Msk                _U_(0x01FF)                                          /**< (SERCOM_SPIM_LENGTH) Register Mask  */
+
+
+/* -------- SERCOM_SPIS_LENGTH : (SERCOM Offset: 0x22) (R/W 16) SPIS Length -------- */
+#define SERCOM_SPIS_LENGTH_RESETVALUE         _U_(0x00)                                            /**<  (SERCOM_SPIS_LENGTH) SPIS Length  Reset Value */
+
+#define SERCOM_SPIS_LENGTH_LEN_Pos            _U_(0)                                               /**< (SERCOM_SPIS_LENGTH) Data Length Position */
+#define SERCOM_SPIS_LENGTH_LEN_Msk            (_U_(0xFF) << SERCOM_SPIS_LENGTH_LEN_Pos)            /**< (SERCOM_SPIS_LENGTH) Data Length Mask */
+#define SERCOM_SPIS_LENGTH_LEN(value)         (SERCOM_SPIS_LENGTH_LEN_Msk & ((value) << SERCOM_SPIS_LENGTH_LEN_Pos))
+#define SERCOM_SPIS_LENGTH_LENEN_Pos          _U_(8)                                               /**< (SERCOM_SPIS_LENGTH) Data Length Enable Position */
+#define SERCOM_SPIS_LENGTH_LENEN_Msk          (_U_(0x1) << SERCOM_SPIS_LENGTH_LENEN_Pos)           /**< (SERCOM_SPIS_LENGTH) Data Length Enable Mask */
+#define SERCOM_SPIS_LENGTH_LENEN(value)       (SERCOM_SPIS_LENGTH_LENEN_Msk & ((value) << SERCOM_SPIS_LENGTH_LENEN_Pos))
+#define SERCOM_SPIS_LENGTH_Msk                _U_(0x01FF)                                          /**< (SERCOM_SPIS_LENGTH) Register Mask  */
+
+
+/* -------- SERCOM_USART_EXT_LENGTH : (SERCOM Offset: 0x22) (R/W 16) USART_EXT Length -------- */
+#define SERCOM_USART_EXT_LENGTH_RESETVALUE    _U_(0x00)                                            /**<  (SERCOM_USART_EXT_LENGTH) USART_EXT Length  Reset Value */
+
+#define SERCOM_USART_EXT_LENGTH_LEN_Pos       _U_(0)                                               /**< (SERCOM_USART_EXT_LENGTH) Data Length Position */
+#define SERCOM_USART_EXT_LENGTH_LEN_Msk       (_U_(0xFF) << SERCOM_USART_EXT_LENGTH_LEN_Pos)       /**< (SERCOM_USART_EXT_LENGTH) Data Length Mask */
+#define SERCOM_USART_EXT_LENGTH_LEN(value)    (SERCOM_USART_EXT_LENGTH_LEN_Msk & ((value) << SERCOM_USART_EXT_LENGTH_LEN_Pos))
+#define SERCOM_USART_EXT_LENGTH_LENEN_Pos     _U_(8)                                               /**< (SERCOM_USART_EXT_LENGTH) Data Length Enable Position */
+#define SERCOM_USART_EXT_LENGTH_LENEN_Msk     (_U_(0x3) << SERCOM_USART_EXT_LENGTH_LENEN_Pos)      /**< (SERCOM_USART_EXT_LENGTH) Data Length Enable Mask */
+#define SERCOM_USART_EXT_LENGTH_LENEN(value)  (SERCOM_USART_EXT_LENGTH_LENEN_Msk & ((value) << SERCOM_USART_EXT_LENGTH_LENEN_Pos))
+#define SERCOM_USART_EXT_LENGTH_Msk           _U_(0x03FF)                                          /**< (SERCOM_USART_EXT_LENGTH) Register Mask  */
+
+
+/* -------- SERCOM_USART_INT_LENGTH : (SERCOM Offset: 0x22) (R/W 16) USART_INT Length -------- */
+#define SERCOM_USART_INT_LENGTH_RESETVALUE    _U_(0x00)                                            /**<  (SERCOM_USART_INT_LENGTH) USART_INT Length  Reset Value */
+
+#define SERCOM_USART_INT_LENGTH_LEN_Pos       _U_(0)                                               /**< (SERCOM_USART_INT_LENGTH) Data Length Position */
+#define SERCOM_USART_INT_LENGTH_LEN_Msk       (_U_(0xFF) << SERCOM_USART_INT_LENGTH_LEN_Pos)       /**< (SERCOM_USART_INT_LENGTH) Data Length Mask */
+#define SERCOM_USART_INT_LENGTH_LEN(value)    (SERCOM_USART_INT_LENGTH_LEN_Msk & ((value) << SERCOM_USART_INT_LENGTH_LEN_Pos))
+#define SERCOM_USART_INT_LENGTH_LENEN_Pos     _U_(8)                                               /**< (SERCOM_USART_INT_LENGTH) Data Length Enable Position */
+#define SERCOM_USART_INT_LENGTH_LENEN_Msk     (_U_(0x3) << SERCOM_USART_INT_LENGTH_LENEN_Pos)      /**< (SERCOM_USART_INT_LENGTH) Data Length Enable Mask */
+#define SERCOM_USART_INT_LENGTH_LENEN(value)  (SERCOM_USART_INT_LENGTH_LENEN_Msk & ((value) << SERCOM_USART_INT_LENGTH_LENEN_Pos))
+#define SERCOM_USART_INT_LENGTH_Msk           _U_(0x03FF)                                          /**< (SERCOM_USART_INT_LENGTH) Register Mask  */
+
+
+/* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM Address -------- */
+#define SERCOM_I2CM_ADDR_RESETVALUE           _U_(0x00)                                            /**<  (SERCOM_I2CM_ADDR) I2CM Address  Reset Value */
+
+#define SERCOM_I2CM_ADDR_ADDR_Pos             _U_(0)                                               /**< (SERCOM_I2CM_ADDR) Address Value Position */
+#define SERCOM_I2CM_ADDR_ADDR_Msk             (_U_(0x7FF) << SERCOM_I2CM_ADDR_ADDR_Pos)            /**< (SERCOM_I2CM_ADDR) Address Value Mask */
+#define SERCOM_I2CM_ADDR_ADDR(value)          (SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos))
+#define SERCOM_I2CM_ADDR_LENEN_Pos            _U_(13)                                              /**< (SERCOM_I2CM_ADDR) Length Enable Position */
+#define SERCOM_I2CM_ADDR_LENEN_Msk            (_U_(0x1) << SERCOM_I2CM_ADDR_LENEN_Pos)             /**< (SERCOM_I2CM_ADDR) Length Enable Mask */
+#define SERCOM_I2CM_ADDR_LENEN(value)         (SERCOM_I2CM_ADDR_LENEN_Msk & ((value) << SERCOM_I2CM_ADDR_LENEN_Pos))
+#define SERCOM_I2CM_ADDR_HS_Pos               _U_(14)                                              /**< (SERCOM_I2CM_ADDR) High Speed Mode Position */
+#define SERCOM_I2CM_ADDR_HS_Msk               (_U_(0x1) << SERCOM_I2CM_ADDR_HS_Pos)                /**< (SERCOM_I2CM_ADDR) High Speed Mode Mask */
+#define SERCOM_I2CM_ADDR_HS(value)            (SERCOM_I2CM_ADDR_HS_Msk & ((value) << SERCOM_I2CM_ADDR_HS_Pos))
+#define SERCOM_I2CM_ADDR_TENBITEN_Pos         _U_(15)                                              /**< (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable Position */
+#define SERCOM_I2CM_ADDR_TENBITEN_Msk         (_U_(0x1) << SERCOM_I2CM_ADDR_TENBITEN_Pos)          /**< (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable Mask */
+#define SERCOM_I2CM_ADDR_TENBITEN(value)      (SERCOM_I2CM_ADDR_TENBITEN_Msk & ((value) << SERCOM_I2CM_ADDR_TENBITEN_Pos))
+#define SERCOM_I2CM_ADDR_LEN_Pos              _U_(16)                                              /**< (SERCOM_I2CM_ADDR) Length Position */
+#define SERCOM_I2CM_ADDR_LEN_Msk              (_U_(0xFF) << SERCOM_I2CM_ADDR_LEN_Pos)              /**< (SERCOM_I2CM_ADDR) Length Mask */
+#define SERCOM_I2CM_ADDR_LEN(value)           (SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos))
+#define SERCOM_I2CM_ADDR_Msk                  _U_(0x00FFE7FF)                                      /**< (SERCOM_I2CM_ADDR) Register Mask  */
+
+
+/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS Address -------- */
+#define SERCOM_I2CS_ADDR_RESETVALUE           _U_(0x00)                                            /**<  (SERCOM_I2CS_ADDR) I2CS Address  Reset Value */
+
+#define SERCOM_I2CS_ADDR_GENCEN_Pos           _U_(0)                                               /**< (SERCOM_I2CS_ADDR) General Call Address Enable Position */
+#define SERCOM_I2CS_ADDR_GENCEN_Msk           (_U_(0x1) << SERCOM_I2CS_ADDR_GENCEN_Pos)            /**< (SERCOM_I2CS_ADDR) General Call Address Enable Mask */
+#define SERCOM_I2CS_ADDR_GENCEN(value)        (SERCOM_I2CS_ADDR_GENCEN_Msk & ((value) << SERCOM_I2CS_ADDR_GENCEN_Pos))
+#define SERCOM_I2CS_ADDR_ADDR_Pos             _U_(1)                                               /**< (SERCOM_I2CS_ADDR) Address Value Position */
+#define SERCOM_I2CS_ADDR_ADDR_Msk             (_U_(0x3FF) << SERCOM_I2CS_ADDR_ADDR_Pos)            /**< (SERCOM_I2CS_ADDR) Address Value Mask */
+#define SERCOM_I2CS_ADDR_ADDR(value)          (SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos))
+#define SERCOM_I2CS_ADDR_TENBITEN_Pos         _U_(15)                                              /**< (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable Position */
+#define SERCOM_I2CS_ADDR_TENBITEN_Msk         (_U_(0x1) << SERCOM_I2CS_ADDR_TENBITEN_Pos)          /**< (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable Mask */
+#define SERCOM_I2CS_ADDR_TENBITEN(value)      (SERCOM_I2CS_ADDR_TENBITEN_Msk & ((value) << SERCOM_I2CS_ADDR_TENBITEN_Pos))
+#define SERCOM_I2CS_ADDR_ADDRMASK_Pos         _U_(17)                                              /**< (SERCOM_I2CS_ADDR) Address Mask Position */
+#define SERCOM_I2CS_ADDR_ADDRMASK_Msk         (_U_(0x3FF) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)        /**< (SERCOM_I2CS_ADDR) Address Mask Mask */
+#define SERCOM_I2CS_ADDR_ADDRMASK(value)      (SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos))
+#define SERCOM_I2CS_ADDR_Msk                  _U_(0x07FE87FF)                                      /**< (SERCOM_I2CS_ADDR) Register Mask  */
+
+
+/* -------- SERCOM_SPIM_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPIM Address -------- */
+#define SERCOM_SPIM_ADDR_RESETVALUE           _U_(0x00)                                            /**<  (SERCOM_SPIM_ADDR) SPIM Address  Reset Value */
+
+#define SERCOM_SPIM_ADDR_ADDR_Pos             _U_(0)                                               /**< (SERCOM_SPIM_ADDR) Address Value Position */
+#define SERCOM_SPIM_ADDR_ADDR_Msk             (_U_(0xFF) << SERCOM_SPIM_ADDR_ADDR_Pos)             /**< (SERCOM_SPIM_ADDR) Address Value Mask */
+#define SERCOM_SPIM_ADDR_ADDR(value)          (SERCOM_SPIM_ADDR_ADDR_Msk & ((value) << SERCOM_SPIM_ADDR_ADDR_Pos))
+#define SERCOM_SPIM_ADDR_ADDRMASK_Pos         _U_(16)                                              /**< (SERCOM_SPIM_ADDR) Address Mask Position */
+#define SERCOM_SPIM_ADDR_ADDRMASK_Msk         (_U_(0xFF) << SERCOM_SPIM_ADDR_ADDRMASK_Pos)         /**< (SERCOM_SPIM_ADDR) Address Mask Mask */
+#define SERCOM_SPIM_ADDR_ADDRMASK(value)      (SERCOM_SPIM_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPIM_ADDR_ADDRMASK_Pos))
+#define SERCOM_SPIM_ADDR_Msk                  _U_(0x00FF00FF)                                      /**< (SERCOM_SPIM_ADDR) Register Mask  */
+
+
+/* -------- SERCOM_SPIS_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPIS Address -------- */
+#define SERCOM_SPIS_ADDR_RESETVALUE           _U_(0x00)                                            /**<  (SERCOM_SPIS_ADDR) SPIS Address  Reset Value */
+
+#define SERCOM_SPIS_ADDR_ADDR_Pos             _U_(0)                                               /**< (SERCOM_SPIS_ADDR) Address Value Position */
+#define SERCOM_SPIS_ADDR_ADDR_Msk             (_U_(0xFF) << SERCOM_SPIS_ADDR_ADDR_Pos)             /**< (SERCOM_SPIS_ADDR) Address Value Mask */
+#define SERCOM_SPIS_ADDR_ADDR(value)          (SERCOM_SPIS_ADDR_ADDR_Msk & ((value) << SERCOM_SPIS_ADDR_ADDR_Pos))
+#define SERCOM_SPIS_ADDR_ADDRMASK_Pos         _U_(16)                                              /**< (SERCOM_SPIS_ADDR) Address Mask Position */
+#define SERCOM_SPIS_ADDR_ADDRMASK_Msk         (_U_(0xFF) << SERCOM_SPIS_ADDR_ADDRMASK_Pos)         /**< (SERCOM_SPIS_ADDR) Address Mask Mask */
+#define SERCOM_SPIS_ADDR_ADDRMASK(value)      (SERCOM_SPIS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPIS_ADDR_ADDRMASK_Pos))
+#define SERCOM_SPIS_ADDR_Msk                  _U_(0x00FF00FF)                                      /**< (SERCOM_SPIS_ADDR) Register Mask  */
+
+
+/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM Data -------- */
+#define SERCOM_I2CM_DATA_RESETVALUE           _U_(0x00)                                            /**<  (SERCOM_I2CM_DATA) I2CM Data  Reset Value */
+
+#define SERCOM_I2CM_DATA_DATA_Pos             _U_(0)                                               /**< (SERCOM_I2CM_DATA) Data Value Position */
+#define SERCOM_I2CM_DATA_DATA_Msk             (_U_(0xFF) << SERCOM_I2CM_DATA_DATA_Pos)             /**< (SERCOM_I2CM_DATA) Data Value Mask */
+#define SERCOM_I2CM_DATA_DATA(value)          (SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos))
+#define SERCOM_I2CM_DATA_Msk                  _U_(0xFF)                                            /**< (SERCOM_I2CM_DATA) Register Mask  */
+
+
+/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 32) I2CS Data -------- */
+#define SERCOM_I2CS_DATA_RESETVALUE           _U_(0x00)                                            /**<  (SERCOM_I2CS_DATA) I2CS Data  Reset Value */
+
+#define SERCOM_I2CS_DATA_DATA_Pos             _U_(0)                                               /**< (SERCOM_I2CS_DATA) Data Value Position */
+#define SERCOM_I2CS_DATA_DATA_Msk             (_U_(0xFFFFFFFF) << SERCOM_I2CS_DATA_DATA_Pos)       /**< (SERCOM_I2CS_DATA) Data Value Mask */
+#define SERCOM_I2CS_DATA_DATA(value)          (SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos))
+#define SERCOM_I2CS_DATA_Msk                  _U_(0xFFFFFFFF)                                      /**< (SERCOM_I2CS_DATA) Register Mask  */
+
+
+/* -------- SERCOM_SPIM_DATA : (SERCOM Offset: 0x28) (R/W 32) SPIM Data -------- */
+#define SERCOM_SPIM_DATA_RESETVALUE           _U_(0x00)                                            /**<  (SERCOM_SPIM_DATA) SPIM Data  Reset Value */
+
+#define SERCOM_SPIM_DATA_DATA_Pos             _U_(0)                                               /**< (SERCOM_SPIM_DATA) Data Value Position */
+#define SERCOM_SPIM_DATA_DATA_Msk             (_U_(0xFFFFFFFF) << SERCOM_SPIM_DATA_DATA_Pos)       /**< (SERCOM_SPIM_DATA) Data Value Mask */
+#define SERCOM_SPIM_DATA_DATA(value)          (SERCOM_SPIM_DATA_DATA_Msk & ((value) << SERCOM_SPIM_DATA_DATA_Pos))
+#define SERCOM_SPIM_DATA_Msk                  _U_(0xFFFFFFFF)                                      /**< (SERCOM_SPIM_DATA) Register Mask  */
+
+
+/* -------- SERCOM_SPIS_DATA : (SERCOM Offset: 0x28) (R/W 32) SPIS Data -------- */
+#define SERCOM_SPIS_DATA_RESETVALUE           _U_(0x00)                                            /**<  (SERCOM_SPIS_DATA) SPIS Data  Reset Value */
+
+#define SERCOM_SPIS_DATA_DATA_Pos             _U_(0)                                               /**< (SERCOM_SPIS_DATA) Data Value Position */
+#define SERCOM_SPIS_DATA_DATA_Msk             (_U_(0xFFFFFFFF) << SERCOM_SPIS_DATA_DATA_Pos)       /**< (SERCOM_SPIS_DATA) Data Value Mask */
+#define SERCOM_SPIS_DATA_DATA(value)          (SERCOM_SPIS_DATA_DATA_Msk & ((value) << SERCOM_SPIS_DATA_DATA_Pos))
+#define SERCOM_SPIS_DATA_Msk                  _U_(0xFFFFFFFF)                                      /**< (SERCOM_SPIS_DATA) Register Mask  */
+
+
+/* -------- SERCOM_USART_EXT_DATA : (SERCOM Offset: 0x28) (R/W 32) USART_EXT Data -------- */
+#define SERCOM_USART_EXT_DATA_RESETVALUE      _U_(0x00)                                            /**<  (SERCOM_USART_EXT_DATA) USART_EXT Data  Reset Value */
+
+#define SERCOM_USART_EXT_DATA_DATA_Pos        _U_(0)                                               /**< (SERCOM_USART_EXT_DATA) Data Value Position */
+#define SERCOM_USART_EXT_DATA_DATA_Msk        (_U_(0xFFFFFFFF) << SERCOM_USART_EXT_DATA_DATA_Pos)  /**< (SERCOM_USART_EXT_DATA) Data Value Mask */
+#define SERCOM_USART_EXT_DATA_DATA(value)     (SERCOM_USART_EXT_DATA_DATA_Msk & ((value) << SERCOM_USART_EXT_DATA_DATA_Pos))
+#define SERCOM_USART_EXT_DATA_Msk             _U_(0xFFFFFFFF)                                      /**< (SERCOM_USART_EXT_DATA) Register Mask  */
+
+
+/* -------- SERCOM_USART_INT_DATA : (SERCOM Offset: 0x28) (R/W 32) USART_INT Data -------- */
+#define SERCOM_USART_INT_DATA_RESETVALUE      _U_(0x00)                                            /**<  (SERCOM_USART_INT_DATA) USART_INT Data  Reset Value */
+
+#define SERCOM_USART_INT_DATA_DATA_Pos        _U_(0)                                               /**< (SERCOM_USART_INT_DATA) Data Value Position */
+#define SERCOM_USART_INT_DATA_DATA_Msk        (_U_(0xFFFFFFFF) << SERCOM_USART_INT_DATA_DATA_Pos)  /**< (SERCOM_USART_INT_DATA) Data Value Mask */
+#define SERCOM_USART_INT_DATA_DATA(value)     (SERCOM_USART_INT_DATA_DATA_Msk & ((value) << SERCOM_USART_INT_DATA_DATA_Pos))
+#define SERCOM_USART_INT_DATA_Msk             _U_(0xFFFFFFFF)                                      /**< (SERCOM_USART_INT_DATA) Register Mask  */
+
+
+/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM Debug Control -------- */
+#define SERCOM_I2CM_DBGCTRL_RESETVALUE        _U_(0x00)                                            /**<  (SERCOM_I2CM_DBGCTRL) I2CM Debug Control  Reset Value */
+
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos       _U_(0)                                               /**< (SERCOM_I2CM_DBGCTRL) Debug Mode Position */
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP_Msk       (_U_(0x1) << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos)        /**< (SERCOM_I2CM_DBGCTRL) Debug Mode Mask */
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP(value)    (SERCOM_I2CM_DBGCTRL_DBGSTOP_Msk & ((value) << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos))
+#define SERCOM_I2CM_DBGCTRL_Msk               _U_(0x01)                                            /**< (SERCOM_I2CM_DBGCTRL) Register Mask  */
+
+
+/* -------- SERCOM_SPIM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPIM Debug Control -------- */
+#define SERCOM_SPIM_DBGCTRL_RESETVALUE        _U_(0x00)                                            /**<  (SERCOM_SPIM_DBGCTRL) SPIM Debug Control  Reset Value */
+
+#define SERCOM_SPIM_DBGCTRL_DBGSTOP_Pos       _U_(0)                                               /**< (SERCOM_SPIM_DBGCTRL) Debug Mode Position */
+#define SERCOM_SPIM_DBGCTRL_DBGSTOP_Msk       (_U_(0x1) << SERCOM_SPIM_DBGCTRL_DBGSTOP_Pos)        /**< (SERCOM_SPIM_DBGCTRL) Debug Mode Mask */
+#define SERCOM_SPIM_DBGCTRL_DBGSTOP(value)    (SERCOM_SPIM_DBGCTRL_DBGSTOP_Msk & ((value) << SERCOM_SPIM_DBGCTRL_DBGSTOP_Pos))
+#define SERCOM_SPIM_DBGCTRL_Msk               _U_(0x01)                                            /**< (SERCOM_SPIM_DBGCTRL) Register Mask  */
+
+
+/* -------- SERCOM_SPIS_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPIS Debug Control -------- */
+#define SERCOM_SPIS_DBGCTRL_RESETVALUE        _U_(0x00)                                            /**<  (SERCOM_SPIS_DBGCTRL) SPIS Debug Control  Reset Value */
+
+#define SERCOM_SPIS_DBGCTRL_DBGSTOP_Pos       _U_(0)                                               /**< (SERCOM_SPIS_DBGCTRL) Debug Mode Position */
+#define SERCOM_SPIS_DBGCTRL_DBGSTOP_Msk       (_U_(0x1) << SERCOM_SPIS_DBGCTRL_DBGSTOP_Pos)        /**< (SERCOM_SPIS_DBGCTRL) Debug Mode Mask */
+#define SERCOM_SPIS_DBGCTRL_DBGSTOP(value)    (SERCOM_SPIS_DBGCTRL_DBGSTOP_Msk & ((value) << SERCOM_SPIS_DBGCTRL_DBGSTOP_Pos))
+#define SERCOM_SPIS_DBGCTRL_Msk               _U_(0x01)                                            /**< (SERCOM_SPIS_DBGCTRL) Register Mask  */
+
+
+/* -------- SERCOM_USART_EXT_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART_EXT Debug Control -------- */
+#define SERCOM_USART_EXT_DBGCTRL_RESETVALUE   _U_(0x00)                                            /**<  (SERCOM_USART_EXT_DBGCTRL) USART_EXT Debug Control  Reset Value */
+
+#define SERCOM_USART_EXT_DBGCTRL_DBGSTOP_Pos  _U_(0)                                               /**< (SERCOM_USART_EXT_DBGCTRL) Debug Mode Position */
+#define SERCOM_USART_EXT_DBGCTRL_DBGSTOP_Msk  (_U_(0x1) << SERCOM_USART_EXT_DBGCTRL_DBGSTOP_Pos)   /**< (SERCOM_USART_EXT_DBGCTRL) Debug Mode Mask */
+#define SERCOM_USART_EXT_DBGCTRL_DBGSTOP(value) (SERCOM_USART_EXT_DBGCTRL_DBGSTOP_Msk & ((value) << SERCOM_USART_EXT_DBGCTRL_DBGSTOP_Pos))
+#define SERCOM_USART_EXT_DBGCTRL_Msk          _U_(0x01)                                            /**< (SERCOM_USART_EXT_DBGCTRL) Register Mask  */
+
+
+/* -------- SERCOM_USART_INT_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART_INT Debug Control -------- */
+#define SERCOM_USART_INT_DBGCTRL_RESETVALUE   _U_(0x00)                                            /**<  (SERCOM_USART_INT_DBGCTRL) USART_INT Debug Control  Reset Value */
+
+#define SERCOM_USART_INT_DBGCTRL_DBGSTOP_Pos  _U_(0)                                               /**< (SERCOM_USART_INT_DBGCTRL) Debug Mode Position */
+#define SERCOM_USART_INT_DBGCTRL_DBGSTOP_Msk  (_U_(0x1) << SERCOM_USART_INT_DBGCTRL_DBGSTOP_Pos)   /**< (SERCOM_USART_INT_DBGCTRL) Debug Mode Mask */
+#define SERCOM_USART_INT_DBGCTRL_DBGSTOP(value) (SERCOM_USART_INT_DBGCTRL_DBGSTOP_Msk & ((value) << SERCOM_USART_INT_DBGCTRL_DBGSTOP_Pos))
+#define SERCOM_USART_INT_DBGCTRL_Msk          _U_(0x01)                                            /**< (SERCOM_USART_INT_DBGCTRL) Register Mask  */
+
+
+/** \brief SERCOM register offsets definitions */
+#define SERCOM_I2CM_CTRLA_REG_OFST     (0x00)              /**< (SERCOM_I2CM_CTRLA) I2CM Control A Offset */
+#define SERCOM_I2CS_CTRLA_REG_OFST     (0x00)              /**< (SERCOM_I2CS_CTRLA) I2CS Control A Offset */
+#define SERCOM_SPIM_CTRLA_REG_OFST     (0x00)              /**< (SERCOM_SPIM_CTRLA) SPIM Control A Offset */
+#define SERCOM_SPIS_CTRLA_REG_OFST     (0x00)              /**< (SERCOM_SPIS_CTRLA) SPIS Control A Offset */
+#define SERCOM_USART_EXT_CTRLA_REG_OFST (0x00)              /**< (SERCOM_USART_EXT_CTRLA) USART_EXT Control A Offset */
+#define SERCOM_USART_INT_CTRLA_REG_OFST (0x00)              /**< (SERCOM_USART_INT_CTRLA) USART_INT Control A Offset */
+#define SERCOM_I2CM_CTRLB_REG_OFST     (0x04)              /**< (SERCOM_I2CM_CTRLB) I2CM Control B Offset */
+#define SERCOM_I2CS_CTRLB_REG_OFST     (0x04)              /**< (SERCOM_I2CS_CTRLB) I2CS Control B Offset */
+#define SERCOM_SPIM_CTRLB_REG_OFST     (0x04)              /**< (SERCOM_SPIM_CTRLB) SPIM Control B Offset */
+#define SERCOM_SPIS_CTRLB_REG_OFST     (0x04)              /**< (SERCOM_SPIS_CTRLB) SPIS Control B Offset */
+#define SERCOM_USART_EXT_CTRLB_REG_OFST (0x04)              /**< (SERCOM_USART_EXT_CTRLB) USART_EXT Control B Offset */
+#define SERCOM_USART_INT_CTRLB_REG_OFST (0x04)              /**< (SERCOM_USART_INT_CTRLB) USART_INT Control B Offset */
+#define SERCOM_I2CM_CTRLC_REG_OFST     (0x08)              /**< (SERCOM_I2CM_CTRLC) I2CM Control C Offset */
+#define SERCOM_I2CS_CTRLC_REG_OFST     (0x08)              /**< (SERCOM_I2CS_CTRLC) I2CS Control C Offset */
+#define SERCOM_SPIM_CTRLC_REG_OFST     (0x08)              /**< (SERCOM_SPIM_CTRLC) SPIM Control C Offset */
+#define SERCOM_SPIS_CTRLC_REG_OFST     (0x08)              /**< (SERCOM_SPIS_CTRLC) SPIS Control C Offset */
+#define SERCOM_USART_EXT_CTRLC_REG_OFST (0x08)              /**< (SERCOM_USART_EXT_CTRLC) USART_EXT Control C Offset */
+#define SERCOM_USART_INT_CTRLC_REG_OFST (0x08)              /**< (SERCOM_USART_INT_CTRLC) USART_INT Control C Offset */
+#define SERCOM_I2CM_BAUD_REG_OFST      (0x0C)              /**< (SERCOM_I2CM_BAUD) I2CM Baud Rate Offset */
+#define SERCOM_SPIM_BAUD_REG_OFST      (0x0C)              /**< (SERCOM_SPIM_BAUD) SPIM Baud Rate Offset */
+#define SERCOM_SPIS_BAUD_REG_OFST      (0x0C)              /**< (SERCOM_SPIS_BAUD) SPIS Baud Rate Offset */
+#define SERCOM_USART_EXT_BAUD_REG_OFST (0x0C)              /**< (SERCOM_USART_EXT_BAUD) USART_EXT Baud Rate Offset */
+#define SERCOM_USART_INT_BAUD_REG_OFST (0x0C)              /**< (SERCOM_USART_INT_BAUD) USART_INT Baud Rate Offset */
+#define SERCOM_USART_EXT_RXPL_REG_OFST (0x0E)              /**< (SERCOM_USART_EXT_RXPL) USART_EXT Receive Pulse Length Offset */
+#define SERCOM_USART_INT_RXPL_REG_OFST (0x0E)              /**< (SERCOM_USART_INT_RXPL) USART_INT Receive Pulse Length Offset */
+#define SERCOM_I2CM_INTENCLR_REG_OFST  (0x14)              /**< (SERCOM_I2CM_INTENCLR) I2CM Interrupt Enable Clear Offset */
+#define SERCOM_I2CS_INTENCLR_REG_OFST  (0x14)              /**< (SERCOM_I2CS_INTENCLR) I2CS Interrupt Enable Clear Offset */
+#define SERCOM_SPIM_INTENCLR_REG_OFST  (0x14)              /**< (SERCOM_SPIM_INTENCLR) SPIM Interrupt Enable Clear Offset */
+#define SERCOM_SPIS_INTENCLR_REG_OFST  (0x14)              /**< (SERCOM_SPIS_INTENCLR) SPIS Interrupt Enable Clear Offset */
+#define SERCOM_USART_EXT_INTENCLR_REG_OFST (0x14)              /**< (SERCOM_USART_EXT_INTENCLR) USART_EXT Interrupt Enable Clear Offset */
+#define SERCOM_USART_INT_INTENCLR_REG_OFST (0x14)              /**< (SERCOM_USART_INT_INTENCLR) USART_INT Interrupt Enable Clear Offset */
+#define SERCOM_I2CM_INTENSET_REG_OFST  (0x16)              /**< (SERCOM_I2CM_INTENSET) I2CM Interrupt Enable Set Offset */
+#define SERCOM_I2CS_INTENSET_REG_OFST  (0x16)              /**< (SERCOM_I2CS_INTENSET) I2CS Interrupt Enable Set Offset */
+#define SERCOM_SPIM_INTENSET_REG_OFST  (0x16)              /**< (SERCOM_SPIM_INTENSET) SPIM Interrupt Enable Set Offset */
+#define SERCOM_SPIS_INTENSET_REG_OFST  (0x16)              /**< (SERCOM_SPIS_INTENSET) SPIS Interrupt Enable Set Offset */
+#define SERCOM_USART_EXT_INTENSET_REG_OFST (0x16)              /**< (SERCOM_USART_EXT_INTENSET) USART_EXT Interrupt Enable Set Offset */
+#define SERCOM_USART_INT_INTENSET_REG_OFST (0x16)              /**< (SERCOM_USART_INT_INTENSET) USART_INT Interrupt Enable Set Offset */
+#define SERCOM_I2CM_INTFLAG_REG_OFST   (0x18)              /**< (SERCOM_I2CM_INTFLAG) I2CM Interrupt Flag Status and Clear Offset */
+#define SERCOM_I2CS_INTFLAG_REG_OFST   (0x18)              /**< (SERCOM_I2CS_INTFLAG) I2CS Interrupt Flag Status and Clear Offset */
+#define SERCOM_SPIM_INTFLAG_REG_OFST   (0x18)              /**< (SERCOM_SPIM_INTFLAG) SPIM Interrupt Flag Status and Clear Offset */
+#define SERCOM_SPIS_INTFLAG_REG_OFST   (0x18)              /**< (SERCOM_SPIS_INTFLAG) SPIS Interrupt Flag Status and Clear Offset */
+#define SERCOM_USART_EXT_INTFLAG_REG_OFST (0x18)              /**< (SERCOM_USART_EXT_INTFLAG) USART_EXT Interrupt Flag Status and Clear Offset */
+#define SERCOM_USART_INT_INTFLAG_REG_OFST (0x18)              /**< (SERCOM_USART_INT_INTFLAG) USART_INT Interrupt Flag Status and Clear Offset */
+#define SERCOM_I2CM_STATUS_REG_OFST    (0x1A)              /**< (SERCOM_I2CM_STATUS) I2CM Status Offset */
+#define SERCOM_I2CS_STATUS_REG_OFST    (0x1A)              /**< (SERCOM_I2CS_STATUS) I2CS Status Offset */
+#define SERCOM_SPIM_STATUS_REG_OFST    (0x1A)              /**< (SERCOM_SPIM_STATUS) SPIM Status Offset */
+#define SERCOM_SPIS_STATUS_REG_OFST    (0x1A)              /**< (SERCOM_SPIS_STATUS) SPIS Status Offset */
+#define SERCOM_USART_EXT_STATUS_REG_OFST (0x1A)              /**< (SERCOM_USART_EXT_STATUS) USART_EXT Status Offset */
+#define SERCOM_USART_INT_STATUS_REG_OFST (0x1A)              /**< (SERCOM_USART_INT_STATUS) USART_INT Status Offset */
+#define SERCOM_I2CM_SYNCBUSY_REG_OFST  (0x1C)              /**< (SERCOM_I2CM_SYNCBUSY) I2CM Synchronization Busy Offset */
+#define SERCOM_I2CS_SYNCBUSY_REG_OFST  (0x1C)              /**< (SERCOM_I2CS_SYNCBUSY) I2CS Synchronization Busy Offset */
+#define SERCOM_SPIM_SYNCBUSY_REG_OFST  (0x1C)              /**< (SERCOM_SPIM_SYNCBUSY) SPIM Synchronization Busy Offset */
+#define SERCOM_SPIS_SYNCBUSY_REG_OFST  (0x1C)              /**< (SERCOM_SPIS_SYNCBUSY) SPIS Synchronization Busy Offset */
+#define SERCOM_USART_EXT_SYNCBUSY_REG_OFST (0x1C)              /**< (SERCOM_USART_EXT_SYNCBUSY) USART_EXT Synchronization Busy Offset */
+#define SERCOM_USART_INT_SYNCBUSY_REG_OFST (0x1C)              /**< (SERCOM_USART_INT_SYNCBUSY) USART_INT Synchronization Busy Offset */
+#define SERCOM_USART_EXT_RXERRCNT_REG_OFST (0x20)              /**< (SERCOM_USART_EXT_RXERRCNT) USART_EXT Receive Error Count Offset */
+#define SERCOM_USART_INT_RXERRCNT_REG_OFST (0x20)              /**< (SERCOM_USART_INT_RXERRCNT) USART_INT Receive Error Count Offset */
+#define SERCOM_I2CS_LENGTH_REG_OFST    (0x22)              /**< (SERCOM_I2CS_LENGTH) I2CS Length Offset */
+#define SERCOM_SPIM_LENGTH_REG_OFST    (0x22)              /**< (SERCOM_SPIM_LENGTH) SPIM Length Offset */
+#define SERCOM_SPIS_LENGTH_REG_OFST    (0x22)              /**< (SERCOM_SPIS_LENGTH) SPIS Length Offset */
+#define SERCOM_USART_EXT_LENGTH_REG_OFST (0x22)              /**< (SERCOM_USART_EXT_LENGTH) USART_EXT Length Offset */
+#define SERCOM_USART_INT_LENGTH_REG_OFST (0x22)              /**< (SERCOM_USART_INT_LENGTH) USART_INT Length Offset */
+#define SERCOM_I2CM_ADDR_REG_OFST      (0x24)              /**< (SERCOM_I2CM_ADDR) I2CM Address Offset */
+#define SERCOM_I2CS_ADDR_REG_OFST      (0x24)              /**< (SERCOM_I2CS_ADDR) I2CS Address Offset */
+#define SERCOM_SPIM_ADDR_REG_OFST      (0x24)              /**< (SERCOM_SPIM_ADDR) SPIM Address Offset */
+#define SERCOM_SPIS_ADDR_REG_OFST      (0x24)              /**< (SERCOM_SPIS_ADDR) SPIS Address Offset */
+#define SERCOM_I2CM_DATA_REG_OFST      (0x28)              /**< (SERCOM_I2CM_DATA) I2CM Data Offset */
+#define SERCOM_I2CS_DATA_REG_OFST      (0x28)              /**< (SERCOM_I2CS_DATA) I2CS Data Offset */
+#define SERCOM_SPIM_DATA_REG_OFST      (0x28)              /**< (SERCOM_SPIM_DATA) SPIM Data Offset */
+#define SERCOM_SPIS_DATA_REG_OFST      (0x28)              /**< (SERCOM_SPIS_DATA) SPIS Data Offset */
+#define SERCOM_USART_EXT_DATA_REG_OFST (0x28)              /**< (SERCOM_USART_EXT_DATA) USART_EXT Data Offset */
+#define SERCOM_USART_INT_DATA_REG_OFST (0x28)              /**< (SERCOM_USART_INT_DATA) USART_INT Data Offset */
+#define SERCOM_I2CM_DBGCTRL_REG_OFST   (0x30)              /**< (SERCOM_I2CM_DBGCTRL) I2CM Debug Control Offset */
+#define SERCOM_SPIM_DBGCTRL_REG_OFST   (0x30)              /**< (SERCOM_SPIM_DBGCTRL) SPIM Debug Control Offset */
+#define SERCOM_SPIS_DBGCTRL_REG_OFST   (0x30)              /**< (SERCOM_SPIS_DBGCTRL) SPIS Debug Control Offset */
+#define SERCOM_USART_EXT_DBGCTRL_REG_OFST (0x30)              /**< (SERCOM_USART_EXT_DBGCTRL) USART_EXT Debug Control Offset */
+#define SERCOM_USART_INT_DBGCTRL_REG_OFST (0x30)              /**< (SERCOM_USART_INT_DBGCTRL) USART_INT Debug Control Offset */
+
+#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
+/** \brief SERCOM register API structure */
+typedef struct
+{  /* Serial Communication Interface */
+  __IO  uint32_t                       SERCOM_CTRLA;       /**< Offset: 0x00 (R/W  32) I2CM Control A */
+  __IO  uint32_t                       SERCOM_CTRLB;       /**< Offset: 0x04 (R/W  32) I2CM Control B */
+  __IO  uint32_t                       SERCOM_CTRLC;       /**< Offset: 0x08 (R/W  32) I2CM Control C */
+  __IO  uint32_t                       SERCOM_BAUD;        /**< Offset: 0x0C (R/W  32) I2CM Baud Rate */
+  __I   uint8_t                        Reserved1[0x04];
+  __IO  uint8_t                        SERCOM_INTENCLR;    /**< Offset: 0x14 (R/W  8) I2CM Interrupt Enable Clear */
+  __I   uint8_t                        Reserved2[0x01];
+  __IO  uint8_t                        SERCOM_INTENSET;    /**< Offset: 0x16 (R/W  8) I2CM Interrupt Enable Set */
+  __I   uint8_t                        Reserved3[0x01];
+  __IO  uint8_t                        SERCOM_INTFLAG;     /**< Offset: 0x18 (R/W  8) I2CM Interrupt Flag Status and Clear */
+  __I   uint8_t                        Reserved4[0x01];
+  __IO  uint16_t                       SERCOM_STATUS;      /**< Offset: 0x1A (R/W  16) I2CM Status */
+  __I   uint32_t                       SERCOM_SYNCBUSY;    /**< Offset: 0x1C (R/   32) I2CM Synchronization Busy */
+  __I   uint8_t                        Reserved5[0x04];
+  __IO  uint32_t                       SERCOM_ADDR;        /**< Offset: 0x24 (R/W  32) I2CM Address */
+  __IO  uint8_t                        SERCOM_DATA;        /**< Offset: 0x28 (R/W  8) I2CM Data */
+  __I   uint8_t                        Reserved6[0x07];
+  __IO  uint8_t                        SERCOM_DBGCTRL;     /**< Offset: 0x30 (R/W  8) I2CM Debug Control */
+} sercom_i2cm_registers_t;
+
+/** \brief SERCOM register API structure */
+typedef struct
+{  /* Serial Communication Interface */
+  __IO  uint32_t                       SERCOM_CTRLA;       /**< Offset: 0x00 (R/W  32) I2CS Control A */
+  __IO  uint32_t                       SERCOM_CTRLB;       /**< Offset: 0x04 (R/W  32) I2CS Control B */
+  __IO  uint32_t                       SERCOM_CTRLC;       /**< Offset: 0x08 (R/W  32) I2CS Control C */
+  __I   uint8_t                        Reserved1[0x08];
+  __IO  uint8_t                        SERCOM_INTENCLR;    /**< Offset: 0x14 (R/W  8) I2CS Interrupt Enable Clear */
+  __I   uint8_t                        Reserved2[0x01];
+  __IO  uint8_t                        SERCOM_INTENSET;    /**< Offset: 0x16 (R/W  8) I2CS Interrupt Enable Set */
+  __I   uint8_t                        Reserved3[0x01];
+  __IO  uint8_t                        SERCOM_INTFLAG;     /**< Offset: 0x18 (R/W  8) I2CS Interrupt Flag Status and Clear */
+  __I   uint8_t                        Reserved4[0x01];
+  __IO  uint16_t                       SERCOM_STATUS;      /**< Offset: 0x1A (R/W  16) I2CS Status */
+  __I   uint32_t                       SERCOM_SYNCBUSY;    /**< Offset: 0x1C (R/   32) I2CS Synchronization Busy */
+  __I   uint8_t                        Reserved5[0x02];
+  __IO  uint16_t                       SERCOM_LENGTH;      /**< Offset: 0x22 (R/W  16) I2CS Length */
+  __IO  uint32_t                       SERCOM_ADDR;        /**< Offset: 0x24 (R/W  32) I2CS Address */
+  __IO  uint32_t                       SERCOM_DATA;        /**< Offset: 0x28 (R/W  32) I2CS Data */
+} sercom_i2cs_registers_t;
+
+/** \brief SERCOM register API structure */
+typedef struct
+{  /* Serial Communication Interface */
+  __IO  uint32_t                       SERCOM_CTRLA;       /**< Offset: 0x00 (R/W  32) SPIS Control A */
+  __IO  uint32_t                       SERCOM_CTRLB;       /**< Offset: 0x04 (R/W  32) SPIS Control B */
+  __IO  uint32_t                       SERCOM_CTRLC;       /**< Offset: 0x08 (R/W  32) SPIS Control C */
+  __IO  uint8_t                        SERCOM_BAUD;        /**< Offset: 0x0C (R/W  8) SPIS Baud Rate */
+  __I   uint8_t                        Reserved1[0x07];
+  __IO  uint8_t                        SERCOM_INTENCLR;    /**< Offset: 0x14 (R/W  8) SPIS Interrupt Enable Clear */
+  __I   uint8_t                        Reserved2[0x01];
+  __IO  uint8_t                        SERCOM_INTENSET;    /**< Offset: 0x16 (R/W  8) SPIS Interrupt Enable Set */
+  __I   uint8_t                        Reserved3[0x01];
+  __IO  uint8_t                        SERCOM_INTFLAG;     /**< Offset: 0x18 (R/W  8) SPIS Interrupt Flag Status and Clear */
+  __I   uint8_t                        Reserved4[0x01];
+  __IO  uint16_t                       SERCOM_STATUS;      /**< Offset: 0x1A (R/W  16) SPIS Status */
+  __I   uint32_t                       SERCOM_SYNCBUSY;    /**< Offset: 0x1C (R/   32) SPIS Synchronization Busy */
+  __I   uint8_t                        Reserved5[0x02];
+  __IO  uint16_t                       SERCOM_LENGTH;      /**< Offset: 0x22 (R/W  16) SPIS Length */
+  __IO  uint32_t                       SERCOM_ADDR;        /**< Offset: 0x24 (R/W  32) SPIS Address */
+  __IO  uint32_t                       SERCOM_DATA;        /**< Offset: 0x28 (R/W  32) SPIS Data */
+  __I   uint8_t                        Reserved6[0x04];
+  __IO  uint8_t                        SERCOM_DBGCTRL;     /**< Offset: 0x30 (R/W  8) SPIS Debug Control */
+} sercom_spis_registers_t;
+
+/** \brief SERCOM register API structure */
+typedef struct
+{  /* Serial Communication Interface */
+  __IO  uint32_t                       SERCOM_CTRLA;       /**< Offset: 0x00 (R/W  32) SPIM Control A */
+  __IO  uint32_t                       SERCOM_CTRLB;       /**< Offset: 0x04 (R/W  32) SPIM Control B */
+  __IO  uint32_t                       SERCOM_CTRLC;       /**< Offset: 0x08 (R/W  32) SPIM Control C */
+  __IO  uint8_t                        SERCOM_BAUD;        /**< Offset: 0x0C (R/W  8) SPIM Baud Rate */
+  __I   uint8_t                        Reserved1[0x07];
+  __IO  uint8_t                        SERCOM_INTENCLR;    /**< Offset: 0x14 (R/W  8) SPIM Interrupt Enable Clear */
+  __I   uint8_t                        Reserved2[0x01];
+  __IO  uint8_t                        SERCOM_INTENSET;    /**< Offset: 0x16 (R/W  8) SPIM Interrupt Enable Set */
+  __I   uint8_t                        Reserved3[0x01];
+  __IO  uint8_t                        SERCOM_INTFLAG;     /**< Offset: 0x18 (R/W  8) SPIM Interrupt Flag Status and Clear */
+  __I   uint8_t                        Reserved4[0x01];
+  __IO  uint16_t                       SERCOM_STATUS;      /**< Offset: 0x1A (R/W  16) SPIM Status */
+  __I   uint32_t                       SERCOM_SYNCBUSY;    /**< Offset: 0x1C (R/   32) SPIM Synchronization Busy */
+  __I   uint8_t                        Reserved5[0x02];
+  __IO  uint16_t                       SERCOM_LENGTH;      /**< Offset: 0x22 (R/W  16) SPIM Length */
+  __IO  uint32_t                       SERCOM_ADDR;        /**< Offset: 0x24 (R/W  32) SPIM Address */
+  __IO  uint32_t                       SERCOM_DATA;        /**< Offset: 0x28 (R/W  32) SPIM Data */
+  __I   uint8_t                        Reserved6[0x04];
+  __IO  uint8_t                        SERCOM_DBGCTRL;     /**< Offset: 0x30 (R/W  8) SPIM Debug Control */
+} sercom_spim_registers_t;
+
+/** \brief SERCOM register API structure */
+typedef struct
+{  /* Serial Communication Interface */
+  __IO  uint32_t                       SERCOM_CTRLA;       /**< Offset: 0x00 (R/W  32) USART_EXT Control A */
+  __IO  uint32_t                       SERCOM_CTRLB;       /**< Offset: 0x04 (R/W  32) USART_EXT Control B */
+  __IO  uint32_t                       SERCOM_CTRLC;       /**< Offset: 0x08 (R/W  32) USART_EXT Control C */
+  __IO  uint16_t                       SERCOM_BAUD;        /**< Offset: 0x0C (R/W  16) USART_EXT Baud Rate */
+  __IO  uint8_t                        SERCOM_RXPL;        /**< Offset: 0x0E (R/W  8) USART_EXT Receive Pulse Length */
+  __I   uint8_t                        Reserved1[0x05];
+  __IO  uint8_t                        SERCOM_INTENCLR;    /**< Offset: 0x14 (R/W  8) USART_EXT Interrupt Enable Clear */
+  __I   uint8_t                        Reserved2[0x01];
+  __IO  uint8_t                        SERCOM_INTENSET;    /**< Offset: 0x16 (R/W  8) USART_EXT Interrupt Enable Set */
+  __I   uint8_t                        Reserved3[0x01];
+  __IO  uint8_t                        SERCOM_INTFLAG;     /**< Offset: 0x18 (R/W  8) USART_EXT Interrupt Flag Status and Clear */
+  __I   uint8_t                        Reserved4[0x01];
+  __IO  uint16_t                       SERCOM_STATUS;      /**< Offset: 0x1A (R/W  16) USART_EXT Status */
+  __I   uint32_t                       SERCOM_SYNCBUSY;    /**< Offset: 0x1C (R/   32) USART_EXT Synchronization Busy */
+  __I   uint8_t                        SERCOM_RXERRCNT;    /**< Offset: 0x20 (R/   8) USART_EXT Receive Error Count */
+  __I   uint8_t                        Reserved5[0x01];
+  __IO  uint16_t                       SERCOM_LENGTH;      /**< Offset: 0x22 (R/W  16) USART_EXT Length */
+  __I   uint8_t                        Reserved6[0x04];
+  __IO  uint32_t                       SERCOM_DATA;        /**< Offset: 0x28 (R/W  32) USART_EXT Data */
+  __I   uint8_t                        Reserved7[0x04];
+  __IO  uint8_t                        SERCOM_DBGCTRL;     /**< Offset: 0x30 (R/W  8) USART_EXT Debug Control */
+} sercom_usart_ext_registers_t;
+
+/** \brief SERCOM register API structure */
+typedef struct
+{  /* Serial Communication Interface */
+  __IO  uint32_t                       SERCOM_CTRLA;       /**< Offset: 0x00 (R/W  32) USART_INT Control A */
+  __IO  uint32_t                       SERCOM_CTRLB;       /**< Offset: 0x04 (R/W  32) USART_INT Control B */
+  __IO  uint32_t                       SERCOM_CTRLC;       /**< Offset: 0x08 (R/W  32) USART_INT Control C */
+  __IO  uint16_t                       SERCOM_BAUD;        /**< Offset: 0x0C (R/W  16) USART_INT Baud Rate */
+  __IO  uint8_t                        SERCOM_RXPL;        /**< Offset: 0x0E (R/W  8) USART_INT Receive Pulse Length */
+  __I   uint8_t                        Reserved1[0x05];
+  __IO  uint8_t                        SERCOM_INTENCLR;    /**< Offset: 0x14 (R/W  8) USART_INT Interrupt Enable Clear */
+  __I   uint8_t                        Reserved2[0x01];
+  __IO  uint8_t                        SERCOM_INTENSET;    /**< Offset: 0x16 (R/W  8) USART_INT Interrupt Enable Set */
+  __I   uint8_t                        Reserved3[0x01];
+  __IO  uint8_t                        SERCOM_INTFLAG;     /**< Offset: 0x18 (R/W  8) USART_INT Interrupt Flag Status and Clear */
+  __I   uint8_t                        Reserved4[0x01];
+  __IO  uint16_t                       SERCOM_STATUS;      /**< Offset: 0x1A (R/W  16) USART_INT Status */
+  __I   uint32_t                       SERCOM_SYNCBUSY;    /**< Offset: 0x1C (R/   32) USART_INT Synchronization Busy */
+  __I   uint8_t                        SERCOM_RXERRCNT;    /**< Offset: 0x20 (R/   8) USART_INT Receive Error Count */
+  __I   uint8_t                        Reserved5[0x01];
+  __IO  uint16_t                       SERCOM_LENGTH;      /**< Offset: 0x22 (R/W  16) USART_INT Length */
+  __I   uint8_t                        Reserved6[0x04];
+  __IO  uint32_t                       SERCOM_DATA;        /**< Offset: 0x28 (R/W  32) USART_INT Data */
+  __I   uint8_t                        Reserved7[0x04];
+  __IO  uint8_t                        SERCOM_DBGCTRL;     /**< Offset: 0x30 (R/W  8) USART_INT Debug Control */
+} sercom_usart_int_registers_t;
+
+/** \brief SERCOM hardware registers */
+typedef union
+{  /* Serial Communication Interface */
+       sercom_i2cm_registers_t        I2CM;           /**< I2C Master Mode */
+       sercom_i2cs_registers_t        I2CS;           /**< I2C Slave Mode */
+       sercom_spis_registers_t        SPIS;           /**< SPI Slave Mode */
+       sercom_spim_registers_t        SPIM;           /**< SPI Master Mode */
+       sercom_usart_ext_registers_t   USART_EXT;      /**< USART EXTERNAL CLOCK Mode */
+       sercom_usart_int_registers_t   USART_INT;      /**< USART INTERNAL CLOCK Mode */
+} sercom_registers_t;
+
+
+#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
+#endif /* _SAMD51_SERCOM_COMPONENT_H_ */
Index: /asp_wio_terminal/trunk/target/samd51_gcc/samd51.h
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/samd51.h	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/samd51.h	(revision 460)
@@ -0,0 +1,73 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2015 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id: sercom.h 2693 2015-11-04 03:55:57Z ertl-honda $
+ */
+
+#ifndef TOPPERS_SAMD51_H
+#define TOPPERS_SAMD51_H
+
+#include <sil.h>
+
+#define CORE_CLOCK_HZ		120000000U
+#define SERCOM_CLOCK_HZ		16000000
+                      
+/*
+ *  å²è¾¼ã¿çªå·ã®æå¤§å¤
+ */
+#define TMAX_INTNO   (16 + 138)
+/*
+ *  ã¢ã¼ã­ãã¯ãã£
+ */
+#define __TARGET_ARCH_THUMB		4
+
+#endif /* TOPPERS_SAMD51_H */
Index: /asp_wio_terminal/trunk/target/samd51_gcc/samd51.ld
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/samd51.ld	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/samd51.ld	(revision 460)
@@ -0,0 +1,66 @@
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00004000, LENGTH = 0x00080000-0x4000
+/*  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00080000-0x4000 */
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
+  bkupram  (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
+  qspi     (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
+}
+
+PROVIDE(software_term_hook = 0);
+
+ENTRY(_kernel__start)
+
+SECTIONS
+{
+	.vector : {
+		*(.rodata.vector)
+	} > rom
+	
+	.text :
+	{
+		__text = .;
+		*(.text)
+		*(.text.*)
+	} > rom
+	_etext = .;
+	PROVIDE(etext = .);
+
+	.rodata :
+	{
+		*(.rodata)
+		*(.rodata.*)
+	} > rom
+
+	.ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) }
+	__exidx_start = .;
+	.ARM.exidx   : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }
+	__exidx_end = .;
+
+	. = ALIGN(4);
+	__idata_start = .;
+	.data : AT (__idata_start)
+	{
+		__data_start = .;
+		*(.data)
+		*(.data.*)
+	} > ram
+	__idata_end = __idata_start + SIZEOF(.data);
+	_edata = .;
+	PROVIDE(edata = .);
+
+	. = ALIGN(4);
+
+	.bss :
+	{
+		__bss_start  = .;
+		*(.bss)
+		*(.bss.*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end = .;
+	} > ram
+	. = ALIGN(4);
+	_end = .;
+	PROVIDE(end = .);
+}
Index: /asp_wio_terminal/trunk/target/samd51_gcc/target.tf
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/target.tf	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/target.tf	(revision 460)
@@ -0,0 +1,8 @@
+$ 
+$     パス2のターゲット依存テンプレート（stm32f4_discovery用）
+$ 
+
+$ 
+$  コア依存テンプレートのインクルード
+$ 
+$INCLUDE"arm_m_gcc/common/core.tf"$
Index: /asp_wio_terminal/trunk/target/samd51_gcc/target_asm.inc
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/target_asm.inc	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/target_asm.inc	(revision 460)
@@ -0,0 +1,1 @@
+#include "arm_m_gcc/common/core_asm.inc"
Index: /asp_wio_terminal/trunk/target/samd51_gcc/target_cfg1_out.h
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/target_cfg1_out.h	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/target_cfg1_out.h	(revision 460)
@@ -0,0 +1,10 @@
+/*
+ *		cfg1_out.cをリンクするために必要なスタブの定義
+ */
+
+STK_T *const	_kernel_istkpt = 0x00;
+
+/*
+ *  コア依存のスタブの定義 
+ */
+#include <core_cfg1_out.h>
Index: /asp_wio_terminal/trunk/target/samd51_gcc/target_check.tf
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/target_check.tf	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/target_check.tf	(revision 460)
@@ -0,0 +1,8 @@
+$ 
+$     ãã¹3ã®ã¿ã¼ã²ããä¾å­ãã³ãã¬ã¼ãï¼SAMD51ç¨ï¼
+$ 
+
+$ 
+$  ãã¹3ã®ã³ã¢ä¾å­ã®ãã³ãã¬ã¼ãã®ã¤ã³ã¯ã«ã¼ã
+$ 
+$INCLUDE"arm_m_gcc/common/core_check.tf"$
Index: /asp_wio_terminal/trunk/target/samd51_gcc/target_config.c
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/target_config.c	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/target_config.c	(revision 460)
@@ -0,0 +1,199 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2015 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN  
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id: target_config.c 2697 2015-11-06 04:00:42Z ertl-honda $
+ */
+
+/*
+ * ãããä¾å­ã¢ã¸ã¥ã¼ã«ï¼SAMD51ç¨ï¼
+ */
+#include "kernel_impl.h"
+#include <sil.h>
+#include "target_serial.h"
+
+#include "plib_clock.h"
+
+volatile int poi;
+extern const FP vector_table[];
+
+/*
+ *  start.Sããå¼ã³åºããããã¼ãã¦ã§ã¢ã®åæåå¦ç
+ */
+ __attribute__((weak))
+void
+hardware_init_hook(void)
+{
+
+}
+
+
+extern void __libc_init_array(void);
+
+/*
+ *  start.Sããå¼ã³åºãããã½ããã¦ã§ã¢ç°å¢ã®åæåå¦ç
+ */
+ __attribute__((weak))
+void
+software_init_hook(void)
+{
+//	__libc_init_array();
+}
+
+/*
+ *  ã½ããã¦ã§ã¢ç°å¢ã®çµäºå¦ç
+ */
+ __attribute__((weak))
+void
+software_term_hook(void)
+{
+
+}
+
+void
+port_initialize(void) {
+	/* LED Enable */
+	PORT_REGS->GROUP[0].PORT_DIRSET = 1 << 15;
+
+	/* LED On */
+	PORT_REGS->GROUP[0].PORT_OUTSET = 1 << 15;
+
+	/* for SEMCOM2  */
+	PORT_REGS->GROUP[1].PORT_PINCFG[26] = 0x1;
+	PORT_REGS->GROUP[1].PORT_PINCFG[27] = 0x41;
+	PORT_REGS->GROUP[1].PORT_PMUX[13] = 0x22;
+}
+
+void
+led_on(void)
+{
+	PORT_REGS->GROUP[0].PORT_OUTSET = 1 << 15;
+}
+
+void
+led_off(void)
+{
+	PORT_REGS->GROUP[0].PORT_OUTCLR = 1 << 15;
+}
+
+/*
+ *  ã¿ã¼ã²ããä¾å­ã®åæå
+ */
+void
+target_initialize(void)
+{
+	/*
+	 *  -fdata-sectionsãä½¿ç¨ããã¨istkãåé¤ããï¼
+	 *  cfgã®ãã¹3ã®ãã§ãã¯ãã¨ã©ã¼ã¨ãªãããï¼
+	 *  åé¤ãããªãããã«ãã 
+	 */
+	poi = (uint32_t)istk;
+	poi = (uint32_t)vector_table[2];
+
+	/*
+	 * ã¯ã­ãã¯ã®åæå
+	 */
+	CLOCK_Initialize();
+
+	/*
+	 *  ãã¼ãã®åæå
+	 */
+	port_initialize();
+
+	/*
+	 *  target_fput_logãä½¿ããããã«UARTãåæå
+	 */
+	sercom_init_uart(1);
+	
+	/*
+	 *  ARMä¾å­ã®åæå
+	 */
+	core_initialize();
+}
+
+/*
+ *  ã¿ã¼ã²ããä¾å­ã®çµäºå¦ç
+ */
+void
+target_exit(void)
+{
+	extern void    software_term_hook(void);
+	void (*volatile fp)(void) = software_term_hook;
+
+	/*
+	 *  software_term_hookã¸ã®ãã¤ã³ã¿ãï¼ä¸æ¦volatileæå®ã®ããfpã«ä»£
+	 *  å
+¥ãã¦ããä½¿ãã®ã¯ï¼0ã¨ã®æ¯è¼ãæé©åã§åé¤ãããªãããã«ããã
+	 *  ãã§ããï¼
+	 */
+	if (fp != 0) {
+		(*fp)();
+	}
+
+	/*
+	 *  ARMä¾å­ã®çµäºå¦ç
+	 */
+	core_terminate();
+
+	while(1);
+}
+
+/*
+ *  ã·ã¹ãã ã­ã°ã®ä½ã¬ãã«åºåã®ããã®æå­åºå
+ */
+void
+target_fput_log(char c)
+{
+	if (c == '\n') {
+		sercom_putc(SIO_PORTID, '\r');
+	}
+	sercom_putc(SIO_PORTID, c);
+}
Index: /asp_wio_terminal/trunk/target/samd51_gcc/target_config.h
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/target_config.h	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/target_config.h	(revision 460)
@@ -0,0 +1,160 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2015 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN  
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id: target_config.h 2693 2015-11-04 03:55:57Z ertl-honda $
+ */
+
+/*
+ *  ã¿ã¼ã²ããä¾å­ã¢ã¸ã¥ã¼ã«ï¼SAMD51ç¨ï¼
+ *
+ *  ã«ã¼ãã«ã®ãããä¾å­é¨ã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«ï¼kernel_impl.hã®ã¿ã¼
+ *  ã²ããä¾å­é¨ã®ä½ç½®ä»ãã¨ãªãï¼
+ */
+
+#ifndef TOPPERS_TARGET_CONFIG_H
+#define TOPPERS_TARGET_CONFIG_H
+
+/*
+ *  ã¿ã¼ã²ããã®ãã¼ãã¦ã§ã¢è³æºã®å®ç¾©
+ */
+#include "samd51.h"
+
+/*
+ *  ãã¬ã¼ã¹ã­ã°ã«é¢ããè¨­å®
+ */
+#ifdef TOPPERS_ENABLE_TRACE
+#include "logtrace/trace_config.h"
+#endif /* TOPPERS_ENABLE_TRACE */
+
+/*
+ *  ããã©ã«ãã®éã¿ã¹ã¯ã³ã³ãã­ã¹ãç¨ã®ã¹ã¿ãã¯é åã®å®ç¾©
+ */
+#define DEFAULT_ISTKSZ			(1024 * 4)
+
+/*
+ * ã¹ã¿ã¼ãã¢ããã«ã¼ãã³ã§ã¹ã¿ãã¯ãåæåãã
+ */
+#define INIT_MSP
+
+/*
+ *  å¾®å°æéå¾
+ã¡ã®ããã®å®ç¾©ï¼æ¬æ¥ã¯SILã®ã¿ã¼ã²ããä¾å­é¨ï¼
+ *  (ToDo) èª¿æ´ãã
+ */
+#define SIL_DLY_TIM1    162
+#define SIL_DLY_TIM2    100
+
+/*
+ *  ä½¿ç¨ããã·ãªã¢ã«ãã¼ãID
+ */
+#define SIO_PORTID		(1)
+
+#define INDEX_INTNO(intno)	((uint_t)((intno) - 1))
+#define INDEX_INHNO(inhno)	((uint_t)((inhno) - 1))
+#define INDEX_EXCNO(excno)	((uint_t)((excno) - 1))
+
+/*
+ *  å²è¾¼ã¿çªå·ã¨å²è¾¼ã¿ãã³ãã©çªå·ãå¤æããããã®ãã¯ã­
+ */
+#define INTNO_INHNO(inhno)	((INTNO)(inhno))
+#define INHNO_INTNO(intno)	((INHNO)(intno))
+
+/*
+ *  å²è¾¼ã¿çªå·ã®ç¯å²ã®å¤å®
+ */
+#define VALID_INTNO_CFGINT(intno)	VALID_INTNO(intno)
+#define	VALID_INTNO_CREISR(intno)	VALID_INTNO(intno)
+#define	VALID_INTNO_DISINT(intno)	VALID_INTNO(intno)
+
+/*
+ *  å²è¾¼ã¿åªå
+åº¦ã®ç¯å²ã®å¤å®
+ */
+#define VALID_INTPRI_CFGINT(intpri)	(-1 >= (intpri) && (intpri) >= -7)
+
+/*
+ *  å²è¾¼ã¿ãã³ãã©çªå·ã¨CPUä¾å¤ãã³ãã©çªå·ã®ç¯å²ã®å¤å®
+ */
+#define VALID_INHNO_DEFINH(inhno)		VALID_INTNO((INTNO)(inhno))
+
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ *  ã¿ã¼ã²ããã·ã¹ãã ä¾å­ã®åæå
+ */
+extern void	target_initialize(void);
+
+/*
+ *  ã¿ã¼ã²ããã·ã¹ãã ã®çµäº
+ *
+ *  ã·ã¹ãã ãçµäºããæã«ä½¿ãï¼
+ */
+extern void	target_exit(void) NoReturn;
+
+/*
+ *  LEDã®æä½
+ */
+extern void led_on(void);
+extern void led_off(void);
+
+#endif /* TOPPERS_MACRO_ONLY */
+
+/*
+ *  ã³ã¢ä¾å­ã¢ã¸ã¥ã¼ã«ï¼ARM-Mç¨ï¼
+ */
+#ifndef ARDUINO_PASS
+#include "core_config.h"
+#else /* ARDUINO_PASS */
+#include "../asp_wo_cfg/arch/arm_m_gcc/common/core_config.h"
+#endif /* ARDUINO_PASS */
+#endif /* TOPPERS_TARGET_CONFIG_H */
Index: /asp_wio_terminal/trunk/target/samd51_gcc/target_kernel.h
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/target_kernel.h	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/target_kernel.h	(revision 460)
@@ -0,0 +1,98 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2015 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id: target_kernel.h 2693 2015-11-04 03:55:57Z ertl-honda $
+ */
+
+/*
+ *  kernel.hã®ãããä¾å­é¨ï¼SAMD51ç¨ï¼
+ *
+ *  ãã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«ã¯ï¼kernel.hã§ã¤ã³ã¯ã«ã¼ããããï¼ä»ã®ãã¡
+ *  ã¤ã«ããç´æ¥ã¤ã³ã¯ã«ã¼ããããã¨ã¯ãªãï¼ãã®ãã¡ã¤ã«ãã¤ã³ã¯ã«ã¼ã
+ *  ããåã«ï¼t_stddef.hãã¤ã³ã¯ã«ã¼ããããã®ã§ï¼ãããã«ä¾å­ãã¦ãã
+ *  ãï¼
+ */
+
+#ifndef TOPPERS_TARGET_KERNEL_H
+#define TOPPERS_TARGET_KERNEL_H
+
+/*
+ *  ã«ã¼ãã«ç®¡çã®å²è¾¼ã¿åªå
+åº¦ã®ç¯å²
+ *
+ *  TMIN_INTPRIã®å®ç¾©ãå¤æ´ãããã¨ã§ï¼ãã®ã¬ãã«ãããé«ãå²è¾¼ã¿åªå
+åº¦
+ *  ãæã¤ãã®ãã«ã¼ãã«ç®¡çå¤ã®å²è¾¼ã¿ã¨ããããå¤æ´ã§ããï¼
+ */
+#define TMIN_INTPRI		(-7)		/* å²è¾¼ã¿åªå
+åº¦ã®æå°å¤ï¼æé«å¤ï¼*/
+
+/*
+ *  ãµãã¼ãããæ©è½ã®å®ç¾©
+ */
+#define TOPPERS_TARGET_SUPPORT_ENA_INT		/* ena_intããµãã¼ããã */
+#define TOPPERS_TARGET_SUPPORT_DIS_INT		/* dis_intããµãã¼ããã */
+#define TOPPERS_TARGET_SUPPORT_GET_UTM		/* get_utmããµãã¼ããã */
+
+/*
+ *  ã¿ã¤ã ãã£ãã¯ã®å®ç¾©
+ */
+#define TIC_NUME		1U		/* ã¿ã¤ã ãã£ãã¯ã®å¨æã®åå­ */
+#define TIC_DENO		1U		/* ã¿ã¤ã ãã£ãã¯ã®å¨æã®åæ¯ */
+
+/*
+ *  ã³ã¢ä¾å­ã§å
+±éãªå®ç¾©ï¼ARM-Mç¨ï¼
+ */
+#include "arm_m_gcc/common/core_kernel.h"
+
+#endif /* TOPPERS_TARGET_KERNEL_H */
Index: /asp_wio_terminal/trunk/target/samd51_gcc/target_offset.tf
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/target_offset.tf	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/target_offset.tf	(revision 460)
@@ -0,0 +1,13 @@
+$
+$       ItZbgt@C¶¬pev[gt@Cistm32f4_discoverypj
+$
+
+$
+$  Wev[gt@CÌCN[h
+$
+$INCLUDE "kernel/genoffset.tf"$
+
+$ 
+$  RAË¶ev[gÌCN[hiARM-Mpj
+$ 
+$INCLUDE"../../arch/arm_m_gcc/common/core_offset.tf"$
Index: /asp_wio_terminal/trunk/target/samd51_gcc/target_rename.def
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/target_rename.def	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/target_rename.def	(revision 460)
@@ -0,0 +1,35 @@
+# kernel_cfg.c
+ipm_mask_tbl
+inh_tbl
+
+# target_config.c
+idf
+ipm
+inh_ipm_tbl
+bitpat_cfgint
+x_config_int
+target_exit
+target_initialize
+default_int_handler
+
+# target_support.S
+undef_handler
+swi_handler
+prefetch_handler
+data_abort_handler
+interrupt_handler
+fiq_handler
+
+# target_timer.c
+target_timer_get_current
+target_timer_probe_int
+
+# trace_config.c
+log_dsp_enter
+log_dsp_leave
+log_inh_enter
+log_inh_leave
+log_exc_enter
+log_exc_leave
+
+INCLUDE "arm_gcc/common/core"
Index: /asp_wio_terminal/trunk/target/samd51_gcc/target_rename.h
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/target_rename.h	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/target_rename.h	(revision 460)
@@ -0,0 +1,106 @@
+/* This file is generated from target_rename.def by genrename. */
+
+#ifndef TOPPERS_TARGET_RENAME_H
+#define TOPPERS_TARGET_RENAME_H
+
+/*
+ *  kernel_cfg.c
+ */
+#define ipm_mask_tbl				_kernel_ipm_mask_tbl
+#define inh_tbl						_kernel_inh_tbl
+
+/*
+ *  target_config.c
+ */
+#define idf							_kernel_idf
+#define ipm							_kernel_ipm
+#define inh_ipm_tbl					_kernel_inh_ipm_tbl
+#define bitpat_cfgint				_kernel_bitpat_cfgint
+#define x_config_int				_kernel_x_config_int
+#define target_exit					_kernel_target_exit
+#define target_initialize			_kernel_target_initialize
+#define default_int_handler			_kernel_default_int_handler
+
+/*
+ *  target_support.S
+ */
+#define undef_handler				_kernel_undef_handler
+#define swi_handler					_kernel_swi_handler
+#define prefetch_handler			_kernel_prefetch_handler
+#define data_abort_handler			_kernel_data_abort_handler
+#define interrupt_handler			_kernel_interrupt_handler
+#define fiq_handler					_kernel_fiq_handler
+
+/*
+ *  target_timer.c
+ */
+#define target_timer_get_current	_kernel_target_timer_get_current
+#define target_timer_probe_int		_kernel_target_timer_probe_int
+
+/*
+ *  trace_config.c
+ */
+#define log_dsp_enter				_kernel_log_dsp_enter
+#define log_dsp_leave				_kernel_log_dsp_leave
+#define log_inh_enter				_kernel_log_inh_enter
+#define log_inh_leave				_kernel_log_inh_leave
+#define log_exc_enter				_kernel_log_exc_enter
+#define log_exc_leave				_kernel_log_exc_leave
+
+
+#ifdef TOPPERS_LABEL_ASM
+
+/*
+ *  kernel_cfg.c
+ */
+#define _ipm_mask_tbl				__kernel_ipm_mask_tbl
+#define _inh_tbl					__kernel_inh_tbl
+
+/*
+ *  target_config.c
+ */
+#define _idf						__kernel_idf
+#define _ipm						__kernel_ipm
+#define _inh_ipm_tbl				__kernel_inh_ipm_tbl
+#define _bitpat_cfgint				__kernel_bitpat_cfgint
+#define _x_config_int				__kernel_x_config_int
+#define _target_exit				__kernel_target_exit
+#define _target_initialize			__kernel_target_initialize
+#define _default_int_handler		__kernel_default_int_handler
+
+/*
+ *  target_support.S
+ */
+#define _undef_handler				__kernel_undef_handler
+#define _swi_handler				__kernel_swi_handler
+#define _prefetch_handler			__kernel_prefetch_handler
+#define _data_abort_handler			__kernel_data_abort_handler
+#define _interrupt_handler			__kernel_interrupt_handler
+#define _fiq_handler				__kernel_fiq_handler
+
+/*
+ *  target_timer.c
+ */
+#define _target_timer_get_current	__kernel_target_timer_get_current
+#define _target_timer_probe_int		__kernel_target_timer_probe_int
+
+/*
+ *  trace_config.c
+ */
+#define _log_dsp_enter				__kernel_log_dsp_enter
+#define _log_dsp_leave				__kernel_log_dsp_leave
+#define _log_inh_enter				__kernel_log_inh_enter
+#define _log_inh_leave				__kernel_log_inh_leave
+#define _log_exc_enter				__kernel_log_exc_enter
+#define _log_exc_leave				__kernel_log_exc_leave
+
+
+#endif /* TOPPERS_LABEL_ASM */
+
+#ifndef ARDUINO_PASS
+#include "arm_m_gcc/common/core_rename.h"
+#else /* ARDUINO_PASS */
+#include "../asp_wo_cfg/arch/arm_m_gcc/common/core_rename.h"
+#endif /* ARDUINO_PASS */
+
+#endif /* TOPPERS_TARGET_RENAME_H */
Index: /asp_wio_terminal/trunk/target/samd51_gcc/target_serial.c
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/target_serial.c	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/target_serial.c	(revision 460)
@@ -0,0 +1,441 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2015 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id: target_serial.c 2708 2015-11-22 10:35:09Z ertl-honda $
+ */
+
+/*
+ *  ã·ãªã¢ã«I/Oããã¤ã¹ï¼SIOï¼ãã©ã¤ãï¼SAMD51ç¨ï¼
+ */
+#include <kernel.h>
+#include <t_syslog.h>
+//#undef assert
+//#include "samd55.h"
+#include "target_serial.h"
+//#include "hri_l11.h"
+//#include "peripheral_clk_config.h"
+//#include "hal_gpio.h"
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãåæåãã­ãã¯ã®å®ç¾©
+ */
+typedef struct sio_port_initialization_block 
+{
+//	Sercom*		p_sercom;		/* ä½¿ç¨ããSERCOMã¸ã®ãã¤ã³ã¿ */
+	uint32_t	bps;			/* ãã¼ã¬ã¼ã */
+}
+SIOPINIB;
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãç®¡çãã­ãã¯ã®å®ç¾©
+ */
+struct sio_port_control_block 
+{
+	const SIOPINIB*	p_siopinib;	/* åæåãã­ãã¯ */
+	intptr_t		exinf;		/* æ¡å¼µæ
+å ± */
+	bool_t			openflag;	/* ãªã¼ãã³æ¸ã¿ãã©ã° */
+	bool_t			devinitd;	/* ããã¤ã¹åæåæ¸ã¿ãã©ã° */
+	bool_t			sendflag;	/* éä¿¡å²è¾¼ã¿ã¤ãã¼ãã«ãã©ã° */
+	bool_t			getready;	/* æå­ãåä¿¡ããç¶æ
+ */
+	bool_t			putready;	/* æå­ãéä¿¡ã§ããç¶æ
+ */
+};
+
+/*
+ * ã·ãªã¢ã«I/Oãã¼ãåæåãã­ãã¯
+ */
+const SIOPINIB siopinib_table[TNUM_SIOP] = {
+//	{SERCOM2, 115200}
+	{115200}
+};
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãç®¡çãã­ãã¯ã®ã¨ãªã¢
+ */
+SIOPCB siopcb_table[TNUM_SIOP];
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãIDããç®¡çãã­ãã¯ãåãåºãããã®ãã¯ã­
+ */
+#define INDEX_SIOP(siopid)  ((uint_t)((siopid) - 1))
+#define get_siopcb(siopid)  (&(siopcb_table[INDEX_SIOP(siopid)]))
+
+
+/* SERCOM2 USART baud value for 115200 Hz baud rate */
+#define SERCOM2_USART_INT_BAUD_VALUE            (64328U)
+
+static void
+sercom_uart_devinit(SIOPCB *p_siopcb)
+{
+	/* ToDo */
+
+	/*
+	 * Configures USART Clock Mode
+	 * Configures TXPO and RXPO
+	 * Configures Data Order
+	 * Configures Standby Mode
+	 * Configures Sampling rate
+	 * Configures IBON
+	 */
+	SERCOM2_REGS->USART_INT.SERCOM_CTRLA = SERCOM_USART_INT_CTRLA_MODE_USART_INT_CLK | SERCOM_USART_INT_CTRLA_RXPO(0x1) | SERCOM_USART_INT_CTRLA_TXPO(0x2) | SERCOM_USART_INT_CTRLA_DORD_Msk | SERCOM_USART_INT_CTRLA_IBON_Msk | SERCOM_USART_INT_CTRLA_FORM(0x0) | SERCOM_USART_INT_CTRLA_SAMPR(0) ;
+
+	/* Configure Baud Rate */
+	SERCOM2_REGS->USART_INT.SERCOM_BAUD = SERCOM_USART_INT_BAUD_BAUD(SERCOM2_USART_INT_BAUD_VALUE);
+
+	/*
+	 * Configures RXEN
+	 * Configures TXEN
+	 * Configures CHSIZE
+	 * Configures Parity
+	 * Configures Stop bits
+	 */
+	SERCOM2_REGS->USART_INT.SERCOM_CTRLB = SERCOM_USART_INT_CTRLB_CHSIZE_8_BIT | SERCOM_USART_INT_CTRLB_SBMODE_1_BIT | SERCOM_USART_INT_CTRLB_RXEN_Msk | SERCOM_USART_INT_CTRLB_TXEN_Msk;
+
+	/* Wait for sync */
+	while(SERCOM2_REGS->USART_INT.SERCOM_SYNCBUSY);
+
+	/* Enable the UART after the configurations */
+	SERCOM2_REGS->USART_INT.SERCOM_CTRLA |= SERCOM_USART_INT_CTRLA_ENABLE_Msk;
+
+	/* Wait for sync */
+	while(SERCOM2_REGS->USART_INT.SERCOM_SYNCBUSY);
+
+	/* Enable error interrupt */
+	SERCOM2_REGS->USART_INT.SERCOM_INTENSET = SERCOM_USART_INT_INTENSET_ERROR_Msk;
+
+
+	/* Enable Receive Complete interrupt */
+	SERCOM2_REGS->USART_INT.SERCOM_INTENSET = SERCOM_USART_INT_INTENSET_RXC_Msk;
+}
+
+/*
+ * ã«ã¼ãã«èµ·åæã®ã­ã°åºåç¨ã®åæå
+ */
+void
+sercom_init_uart(uint32_t siopid)
+{
+	SIOPCB  *p_siopcb;
+
+	p_siopcb = get_siopcb(siopid);
+	p_siopcb->p_siopinib = &siopinib_table[INDEX_SIOP(siopid)];
+	sercom_uart_devinit(p_siopcb);
+}
+
+/*
+ *  UARTããã®ãã¼ãªã³ã°åºå
+ */
+void
+sercom_putc(uint32_t siopid, char c)
+{
+	while(!(SERCOM2_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk));
+	SERCOM2_REGS->USART_INT.SERCOM_DATA = c;
+}
+
+
+/*
+ * æå­ãåä¿¡ããã?
+ */ 
+Inline bool_t
+uart_getready(SIOPCB *p_siopcb)
+{
+	return(SERCOM2_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTENSET_RXC_Msk);
+}
+
+/*
+ * æå­ãéä¿¡ã§ããã?
+ */
+Inline bool_t
+uart_putready(SIOPCB *p_siopcb)
+{
+	return(SERCOM2_REGS->USART_INT.SERCOM_INTFLAG & SERCOM_USART_INT_INTFLAG_DRE_Msk);
+}
+
+/*
+ *  åä¿¡ããæå­ã®åãåºã
+ */
+Inline uint8_t
+uart_getchar(SIOPCB *p_siopcb)
+{
+	return  SERCOM2_REGS->USART_INT.SERCOM_DATA;
+}
+
+/*
+ *  éä¿¡ããæå­ã®æ¸ãè¾¼ã¿
+ */
+Inline void
+uart_putchar(SIOPCB *p_siopcb, uint8_t c)
+{
+	SERCOM2_REGS->USART_INT.SERCOM_DATA = c;
+}
+
+/*
+ *  éä¿¡å²è¾¼ã¿è¨±å¯
+ */
+Inline void
+uart_enable_send(SIOPCB *p_siopcb)
+{
+	SERCOM2_REGS->USART_INT.SERCOM_INTENSET = SERCOM_USART_INT_INTENSET_TXC_Msk;
+}
+
+/*
+ *  éä¿¡å²è¾¼ã¿ç¦æ­¢
+ */
+Inline void
+uart_disable_send(SIOPCB *p_siopcb)
+{
+	SERCOM2_REGS->USART_INT.SERCOM_INTENCLR = SERCOM_USART_INT_INTENCLR_TXC_Msk;
+}
+
+
+/*
+ *  åä¿¡å²è¾¼ã¿è¨±å¯
+ */
+Inline void
+uart_enable_rcv(SIOPCB *p_siopcb)
+{
+	SERCOM2_REGS->USART_INT.SERCOM_INTENSET = SERCOM_USART_INT_INTENSET_RXC_Msk;
+}
+
+/*
+ *  åä¿¡å²è¾¼ã¿ç¦æ­¢
+ */
+Inline void
+uart_disable_rcv(SIOPCB *p_siopcb)
+{
+	SERCOM2_REGS->USART_INT.SERCOM_INTENCLR = SERCOM_USART_INT_INTENCLR_RXC_Msk;
+}
+
+
+/*
+ *  SIOãã©ã¤ãã®åæå
+ */
+void
+sio_initialize(intptr_t exinf)
+{
+	SIOPCB  *p_siopcb;
+	uint_t  i;
+	ER	ercd;
+
+	/*
+	 *  ã·ãªã¢ã«I/Oãã¼ãç®¡çãã­ãã¯ã®åæå
+	 */
+	for (p_siopcb = siopcb_table, i = 0; i < TNUM_SIOP; p_siopcb++, i++) {
+		p_siopcb->p_siopinib = &(siopinib_table[i]);
+		p_siopcb->openflag = false;
+		p_siopcb->sendflag = false;
+	}
+}
+
+/*
+ *  SIOãã©ã¤ãã®çµäºå¦ç
+ */
+void
+sio_terminate(intptr_t exinf)
+{
+	SIOPCB	*p_siopcb;
+	uint_t	i;
+
+	/*
+	 *  ãªã¼ãã³ããã¦ããã·ãªã¢ã«I/Oãã¼ãã®ã¯ã­ã¼ãº
+	 */
+	for (i = 0; i < TNUM_SIOP; i++) {
+		p_siopcb = &(siopcb_table[i]);
+		if (p_siopcb->openflag) {
+			sio_cls_por(p_siopcb);
+		}
+	}
+}
+
+/*
+ * ã·ãªã¢ã«I/Oãã¼ãã®ãªã¼ãã³
+ */
+SIOPCB *
+sercom_uart_opn_por(SIOPCB *p_siopcb, intptr_t exinf)
+{
+	p_siopcb->exinf = exinf;
+	p_siopcb->getready = p_siopcb->putready = false;
+	p_siopcb->openflag = true;
+
+	sercom_uart_devinit(p_siopcb);
+
+	return(p_siopcb);
+}
+
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã®ãªã¼ãã³
+ */
+SIOPCB *
+sio_opn_por(ID siopid, intptr_t exinf)
+{
+	SIOPCB  *p_siopcb = get_siopcb(siopid);
+	bool_t    opnflg;
+
+	/*
+	 *  ãªã¼ãã³ãããã¼ããããããopnflgã«èª­ãã§ããï¼
+	 */
+	opnflg = p_siopcb->openflag;
+
+	/*
+	 *  ããã¤ã¹ä¾å­ã®ãªã¼ãã³å¦çï¼
+	 */
+	sercom_uart_opn_por(p_siopcb, exinf);
+
+	/*
+	 *  ã·ãªã¢ã«I/Oå²è¾¼ã¿ã®ãã¹ã¯ãè§£é¤ããï¼
+	 */
+	if (!opnflg) {
+		(void)ena_int(INTNO_SIO_RX);
+		(void)ena_int(INTNO_SIO_TX);
+	}
+	return(p_siopcb);
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã®ã¯ã­ã¼ãº
+ */
+void
+sio_cls_por(SIOPCB *p_siopcb)
+{
+	/*
+	 *  ããã¤ã¹ä¾å­ã®ã¯ã­ã¼ãºå¦çï¼
+	 */
+	p_siopcb->openflag = false;
+    
+	/*
+	 *  ã·ãªã¢ã«I/Oå²è¾¼ã¿ããã¹ã¯ããï¼
+	 */
+	dis_int(INTNO_SIO_RX);
+	dis_int(INTNO_SIO_TX);
+}
+
+/*
+ *  SIOã®å²è¾¼ã¿ãã³ãã©
+ */
+void
+sio_isr(intptr_t exinf)
+{
+	SIOPCB *p_siopcb = get_siopcb(exinf);
+
+	if (uart_getready(p_siopcb)) {
+		/*
+		 *  åä¿¡éç¥ã³ã¼ã«ããã¯ã«ã¼ãã³ãå¼ã³åºãï¼
+		 */
+		sio_irdy_rcv(p_siopcb->exinf);
+	}
+	if (uart_putready(p_siopcb)) {
+		/*
+		 *  éä¿¡å¯è½ã³ã¼ã«ããã¯ã«ã¼ãã³ãå¼ã³åºãï¼
+		 */
+		sio_irdy_snd(p_siopcb->exinf);
+	}
+}
+
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã¸ã®æå­éä¿¡
+ */
+bool_t
+sio_snd_chr(SIOPCB *siopcb, char c)
+{
+	if (uart_putready(siopcb)){
+		uart_putchar(siopcb, c);
+		return(true);
+	}
+	return(false);
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®æå­åä¿¡
+ */
+int_t
+sio_rcv_chr(SIOPCB *siopcb)
+{
+	if (uart_getready(siopcb)) {
+		return((int_t)(uint8_t) uart_getchar(siopcb));
+	}
+	return(-1);
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®è¨±å¯
+ */
+void
+sio_ena_cbr(SIOPCB *siopcb, uint_t cbrtn)
+{
+	switch (cbrtn) {
+		case SIO_RDY_SND:
+			uart_enable_send(siopcb);
+			break;
+		case SIO_RDY_RCV:
+			uart_enable_rcv(siopcb);
+			break;
+	}
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®ç¦æ­¢
+ */
+void
+sio_dis_cbr(SIOPCB *siopcb, uint_t cbrtn)
+{
+	switch (cbrtn) {
+		case SIO_RDY_SND:
+			uart_disable_send(siopcb);
+			break;
+		case SIO_RDY_RCV:
+			uart_disable_rcv(siopcb);
+			break;
+	}
+}
Index: /asp_wio_terminal/trunk/target/samd51_gcc/target_serial.cfg
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/target_serial.cfg	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/target_serial.cfg	(revision 460)
@@ -0,0 +1,13 @@
+/*
+ *  @(#) $Id: target_serial.cfg 367 2015-07-28 22:32:58Z roi $
+ */
+
+/*
+ *    SIOドライバのコンフィギュレーションファイル
+ */
+#include "target_serial.h"
+ATT_INI({ TA_NULL, 0, sio_initialize });
+ATT_ISR({ TA_NULL, 1, INTNO_SIO_RX, sio_isr, 1 });
+CFG_INT(INTNO_SIO_RX, { TA_ENAINT|INTATR_SIO, INTPRI_SIO});
+ATT_ISR({ TA_NULL, 1, INTNO_SIO_TX, sio_isr, 1 });
+CFG_INT(INTNO_SIO_TX, { TA_ENAINT|INTATR_SIO, INTPRI_SIO});
Index: /asp_wio_terminal/trunk/target/samd51_gcc/target_serial.h
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/target_serial.h	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/target_serial.h	(revision 460)
@@ -0,0 +1,166 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2015 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id: target_serial.h 2708 2015-11-22 10:35:09Z ertl-honda $
+ */
+
+/*
+ * ã·ãªã¢ã«I/Oããã¤ã¹ï¼SIOï¼ãã©ã¤ãï¼SAMD51ç¨ï¼
+ */
+
+#ifndef TOPPERS_TARGET_SERIAL_H
+#define TOPPERS_TARGET_SERIAL_H
+
+#ifndef TOPPERS_MACRO_ONLY
+#undef CCR
+#undef FPCCR
+#undef CPACR
+#include "atsamd51p19a.h"
+#endif /* TOPPERS_MACRO_ONLY */
+
+/*
+ *  SIOã®å²è¾¼ã¿ãã³ãã©ã®ãã¯ã¿çªå·
+ */
+#define INHNO_SIO_RX		(16 + SERCOM2_2_IRQn)	/* å²è¾¼ã¿ãã³ãã©çªå· */
+#define INTNO_SIO_RX		INHNO_SIO_RX			/* å²è¾¼ã¿çªå· */
+#define INHNO_SIO_TX		(16 + SERCOM2_1_IRQn)	/* å²è¾¼ã¿ãã³ãã©çªå· */
+#define INTNO_SIO_TX		INHNO_SIO_TX			/* å²è¾¼ã¿çªå· */
+#define INTPRI_SIO		-2							/* å²è¾¼ã¿åªå
+åº¦ */
+#define INTATR_SIO		0U							/* å²è¾¼ã¿å±æ§ */
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãæ°ã®å®ç¾©
+ */
+#define TNUM_SIOP		1		/* ãµãã¼ãããã·ãªã¢ã«I/Oãã¼ãã®æ° */
+
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãç®¡çãã­ãã¯ã®å®ç¾©
+ */
+typedef struct sio_port_control_block	SIOPCB;
+
+/*
+ *  ã³ã¼ã«ããã¯ã«ã¼ãã³ã®è­å¥çªå·
+ */
+#define SIO_RDY_SND	1U		/* éä¿¡å¯è½ã³ã¼ã«ããã¯ */
+#define SIO_RDY_RCV	2U		/* åä¿¡éç¥ã³ã¼ã«ããã¯ */
+
+/*
+ * ã«ã¼ãã«èµ·åæã®ã­ã°åºåç¨ã®åæå
+ */
+extern void sercom_init_uart(uint32_t siopid);
+
+/*
+ *  UARTããã®ãã¼ãªã³ã°åºå
+ */
+void sercom_putc(uint32_t siopid, char c);
+
+/*
+ *  SIOãã©ã¤ãã®åæå
+ */
+extern void sio_initialize(intptr_t exinf);
+
+/*
+ *  SIOãã©ã¤ãã®çµäºå¦ç
+ */
+extern void		sio_terminate(intptr_t exinf);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã®ãªã¼ãã³
+ */
+extern SIOPCB *sio_opn_por(ID siopid, intptr_t exinf);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã®ã¯ã­ã¼ãº
+ */
+extern void sio_cls_por(SIOPCB *p_siopcb);
+
+/*
+ *  å²è¾¼ã¿ãã³ãã©
+ */
+extern void sio_isr(intptr_t exinf);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã¸ã®æå­éä¿¡
+ */
+extern bool_t sio_snd_chr(SIOPCB *siopcb, char c);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®æå­åä¿¡
+ */
+extern int_t sio_rcv_chr(SIOPCB *siopcb);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®è¨±å¯
+ */
+extern void sio_ena_cbr(SIOPCB *siopcb, uint_t cbrtn);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®ç¦æ­¢
+ */
+extern void sio_dis_cbr(SIOPCB *siopcb, uint_t cbrtn);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®éä¿¡å¯è½ã³ã¼ã«ããã¯
+ */
+extern void sio_irdy_snd(intptr_t exinf);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®åä¿¡éç¥ã³ã¼ã«ããã¯
+ */
+extern void sio_irdy_rcv(intptr_t exinf);
+
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_TARGET_SERIAL_H */
Index: /asp_wio_terminal/trunk/target/samd51_gcc/target_sil.h
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/target_sil.h	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/target_sil.h	(revision 460)
@@ -0,0 +1,92 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2015 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id: target_sil.h 2693 2015-11-04 03:55:57Z ertl-honda $
+ */
+
+/*
+ *  sil.hã®ãããä¾å­é¨ï¼SAMD51ç¨ï¼
+ *
+ *  ãã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«ã¯ï¼sil.hã®å
+é ­ã§ã¤ã³ã¯ã«ã¼ããããï¼ä»ã®ãã¡
+ *  ã¤ã«ããã¯ç´æ¥ã¤ã³ã¯ã«ã¼ããããã¨ã¯ãªãï¼ãã®ãã¡ã¤ã«ãã¤ã³ã¯ã«ã¼
+ *  ãããåã«ï¼t_stddef.hãã¤ã³ã¯ã«ã¼ããããã®ã§ï¼ãããã«ä¾å­ãã¦ã
+ *  ããï¼
+ */
+
+#ifndef TOPPERS_TARGET_SIL_H
+#define TOPPERS_TARGET_SIL_H
+
+/*
+ *  ãããã®ã¨ã³ãã£ã¢ã³
+ */
+#define SIL_ENDIAN_LITTLE	/* ãªãã«ã¨ã³ãã£ã¢ã³ */
+
+/*
+ *  å²è¾¼ã¿åªå
+åº¦ã®ãããå¹
+(core_sil.hã§åç
+§ããããããã§å®ç¾©)
+ */
+#define TBITW_IPRI		3U
+
+/*
+ *  ARM-Mã§å
+±éãªå®ç¾©
+ */
+#ifndef ARDUINO_PASS
+#include "core_sil.h"
+#else /* ARDUINO_PASS */
+#include "../asp_wo_cfg/arch/arm_m_gcc/common/core_sil.h"
+#endif /* ARDUINO_PASS */
+
+#endif /* TOPPERS_TARGET_SIL_H */
Index: /asp_wio_terminal/trunk/target/samd51_gcc/target_stddef.h
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/target_stddef.h	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/target_stddef.h	(revision 460)
@@ -0,0 +1,111 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2015 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id: target_stddef.h 2693 2015-11-04 03:55:57Z ertl-honda $
+ */
+
+/*
+ *  t_stddef.hã®ãããä¾å­é¨ï¼SAMD51ç¨ï¼
+ *
+ *  ãã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«ã¯ï¼t_stddef.hã®å
+é ­ã§ã¤ã³ã¯ã«ã¼ããããï¼
+ *  ä»ã®ãã¡ã¤ã«ããã¯ç´æ¥ã¤ã³ã¯ã«ã¼ããããã¨ã¯ãªãï¼ä»ã®ã¤ã³ã¯ã«ã¼ã
+ *  ãã¡ã¤ã«ã«å
+ç«ã£ã¦å¦çãããããï¼ä»ã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«ã«ä¾å­ã
+ *  ã¦ã¯ãªããªãï¼
+ */
+
+#ifndef TOPPERS_TARGET_STDDEF_H
+#define TOPPERS_TARGET_STDDEF_H
+
+/*
+ *  ã¿ã¼ã²ãããè­å¥ããããã®ãã¯ã­ã®å®ç¾©
+ */
+#define TOPPERS_SAMD51		/* ã·ã¹ãã ç¥ç§° */
+
+/*
+ *  éçºç°å¢ã§å
+±éãªå®ç¾©
+ */
+#ifndef TOPPERS_MACRO_ONLY
+#include <stdint.h>
+#endif /* TOPPERS_MACRO_ONLY */
+
+#ifndef ARDUINO_PASS
+#include <tool_stddef.h>
+#else /* ARDUINO_PASS */
+#include "../asp_wo_cfg/arch/gcc/tool_stddef.h"
+#endif /* ARDUINO_PASS */
+
+
+/*
+ *  ã³ã¢ã§å
+±éãªå®ç¾©
+ */
+#ifndef ARDUINO_PASS
+#include <core_stddef.h>
+#else /* ARDUINO_PASS */
+#include "../asp_wo_cfg/arch/arm_m_gcc/common/core_stddef.h"
+#endif /* ARDUINO_PASS */
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ *  ã¢ãµã¼ã·ã§ã³ã®å¤±ææã®å®è¡ä¸­æ­å¦çï¼ToDoï¼
+ */
+Inline void
+TOPPERS_assert_abort(void)
+{    
+}
+
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_TARGET_STDDEF_H */
Index: /asp_wio_terminal/trunk/target/samd51_gcc/target_syssvc.h
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/target_syssvc.h	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/target_syssvc.h	(revision 460)
@@ -0,0 +1,105 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2015 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id: target_syssvc.h 2693 2015-11-04 03:55:57Z ertl-honda $
+ */
+
+/*
+ *  ã·ã¹ãã ãµã¼ãã¹ã®ãããä¾å­é¨ï¼SAMD51ç¨ï¼
+ *
+ *  ã·ã¹ãã ãµã¼ãã¹ã®ãããä¾å­é¨ã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«ï¼ãã®ãã¡ã¤ã«ã®
+ *  å
+å®¹ã¯ï¼ã³ã³ãã¼ãã³ãè¨è¿°ãã¡ã¤ã«ã«è¨è¿°ããï¼ãã®ãã¡ã¤ã«ã¯ç¡ããªã
+ *  è¦è¾¼ã¿ï¼
+ */
+
+#ifndef TOPPERS_TARGET_SYSSVC_H
+#define TOPPERS_TARGET_SYSSVC_H
+
+/*
+ *  ãã¬ã¼ã¹ã­ã°ã«é¢ããè¨­å®
+ */
+#ifdef TOPPERS_ENABLE_TRACE
+#include "logtrace/trace_config.h"
+#endif /* TOPPERS_ENABLE_TRACE */
+
+/*
+ *  èµ·åã¡ãã»ã¼ã¸ã®ã¿ã¼ã²ããã·ã¹ãã å
+ */
+#define TARGET_NAME		"SAMD51(Cortex-M4)"
+
+/*
+ *  ã·ã¹ãã ã­ã°ã®ä½ã¬ãã«åºåã®ããã®æå­åºå
+ *
+ *  ã¿ã¼ã²ããä¾å­ã®æ¹æ³ã§ï¼æå­cãè¡¨ç¤º/åºå/ä¿å­ããï¼
+ */
+extern void target_fput_log(char c);
+
+#ifdef TOPPERS_ENABLE_TRACE
+/*
+ *  ãã¬ã¼ã¹ã­ã°ã®ãã¡ã¤ã«åºå
+ */
+extern void target_fput_log_file(char c);
+#endif /* TOPPERS_ENABLE_TRACE */
+
+/*
+ *  ã·ãªã¢ã«ãã¼ãæ°ã®å®ç¾©
+ */
+#define TNUM_PORT		1		/* ãµãã¼ãããã·ãªã¢ã«ãã¼ãã®æ° */
+
+/*
+ *  ã·ã¹ãã ã­ã°ã¿ã¹ã¯é¢é£ã®å®æ°ã®å®ç¾©
+ *
+ *  ããã©ã«ãå¤ã®éãï¼
+ */
+
+#endif /* TOPPERS_TARGET_SYSSVC_H */
Index: /asp_wio_terminal/trunk/target/samd51_gcc/target_test.h
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/target_test.h	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/target_test.h	(revision 460)
@@ -0,0 +1,74 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2007-2010 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id: target_test.h 2694 2015-11-04 05:43:49Z ertl-honda $
+ */
+
+/*
+ *		ãã¹ããã­ã°ã©ã ã®ãããä¾å­å®ç¾©ï¼SAMD51ç¨ï¼
+ */
+
+#ifndef TOPPERS_TARGET_TEST_H
+#define TOPPERS_TARGET_TEST_H
+
+#define STACK_SIZE			(2048)
+
+/*
+ *  ã³ã¢ä¾å­ã¢ã¸ã¥ã¼ã«ï¼ARM-Mç¨ï¼
+ */
+#ifndef ARDUINO_PASS
+#include "arm_m_gcc/common/core_test.h"
+#else /* ARDUINO_PASS */
+#include "../asp_wo_cfg/arch/arm_m_gcc/common/core_test.h"
+#endif /* ARDUINO_PASS */
+
+#endif /* TOPPERS_TARGET_TEST_H */
Index: /asp_wio_terminal/trunk/target/samd51_gcc/target_timer.cfg
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/target_timer.cfg	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/target_timer.cfg	(revision 460)
@@ -0,0 +1,11 @@
+/*
+ *  @(#) $Id: target_timer.cfg 367 2015-07-28 22:39:51Z roi $
+ */
+
+/*
+ *    タイマドライバのコンフィギュレーションファイル
+ */
+
+#include "target_timer.h"
+
+INCLUDE("arm_m_gcc/common/core_timer.cfg");
Index: /asp_wio_terminal/trunk/target/samd51_gcc/target_timer.h
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/target_timer.h	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/target_timer.h	(revision 460)
@@ -0,0 +1,83 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2015 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id: target_timer.h 2693 2015-11-04 03:55:57Z ertl-honda $
+ */
+
+/*
+ *  ã¿ã¤ããã©ã¤ãï¼SAMD51ç¨ï¼
+ */
+
+#ifndef TOPPERS_TARGET_TIMER_H
+#define TOPPERS_TARGET_TIMER_H
+
+#include "samd51.h"
+
+/*
+ *  ã¿ã¤ãå¤ã®å
+é¨è¡¨ç¾ã¨ããªç§åä½ã¨ã®å¤æ
+ */
+#define TIMER_CLOCK		(CORE_CLOCK_HZ / 1000)
+
+/*
+ *  ã¿ã¤ãå²è¾¼ã¿ãã³ãã©ç»é²ã®ããã®å®æ°
+ */
+#define INTPRI_TIMER		(-1)		/* å²è¾¼ã¿åªå
+åº¦ */
+#define INTATR_TIMER		 0U			/* å²è¾¼ã¿å±æ§ */
+
+/*
+ *  ãã­ã»ããµä¾å­é¨ã§å®ç¾©ãã
+ */
+#include "arm_m_gcc/common/core_timer.h"
+
+#endif /* TOPPERS_TARGET_TIMER_H */
Index: /asp_wio_terminal/trunk/target/samd51_gcc/target_unrename.h
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/target_unrename.h	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/target_unrename.h	(revision 460)
@@ -0,0 +1,103 @@
+/* This file is generated from target_rename.def by genrename. */
+
+/* This file is included only when target_rename.h has been included. */
+#ifdef TOPPERS_TARGET_RENAME_H
+#undef TOPPERS_TARGET_RENAME_H
+
+/*
+ *  kernel_cfg.c
+ */
+#undef ipm_mask_tbl
+#undef inh_tbl
+
+/*
+ *  target_config.c
+ */
+#undef idf
+#undef ipm
+#undef inh_ipm_tbl
+#undef bitpat_cfgint
+#undef x_config_int
+#undef target_exit
+#undef target_initialize
+#undef default_int_handler
+
+/*
+ *  target_support.S
+ */
+#undef undef_handler
+#undef swi_handler
+#undef prefetch_handler
+#undef data_abort_handler
+#undef interrupt_handler
+#undef fiq_handler
+
+/*
+ *  target_timer.c
+ */
+#undef target_timer_get_current
+#undef target_timer_probe_int
+
+/*
+ *  trace_config.c
+ */
+#undef log_dsp_enter
+#undef log_dsp_leave
+#undef log_inh_enter
+#undef log_inh_leave
+#undef log_exc_enter
+#undef log_exc_leave
+
+
+#ifdef TOPPERS_LABEL_ASM
+
+/*
+ *  kernel_cfg.c
+ */
+#undef _ipm_mask_tbl
+#undef _inh_tbl
+
+/*
+ *  target_config.c
+ */
+#undef _idf
+#undef _ipm
+#undef _inh_ipm_tbl
+#undef _bitpat_cfgint
+#undef _x_config_int
+#undef _target_exit
+#undef _target_initialize
+#undef _default_int_handler
+
+/*
+ *  target_support.S
+ */
+#undef _undef_handler
+#undef _swi_handler
+#undef _prefetch_handler
+#undef _data_abort_handler
+#undef _interrupt_handler
+#undef _fiq_handler
+
+/*
+ *  target_timer.c
+ */
+#undef _target_timer_get_current
+#undef _target_timer_probe_int
+
+/*
+ *  trace_config.c
+ */
+#undef _log_dsp_enter
+#undef _log_dsp_leave
+#undef _log_inh_enter
+#undef _log_inh_leave
+#undef _log_exc_enter
+#undef _log_exc_leave
+
+
+#endif /* TOPPERS_LABEL_ASM */
+
+#include "arm_m_gcc/common/core_unrename.h"
+
+#endif /* TOPPERS_TARGET_RENAME_H */
Index: /asp_wio_terminal/trunk/target/samd51_gcc/target_user.txt
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/target_user.txt	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/target_user.txt	(revision 460)
@@ -0,0 +1,30 @@
+=====================================================================
+                     SAMD51 ã¿ã¼ã²ããä¾å­é¨
+                                  Last Modified:2020 Sep 21 16:19:44
+=====================================================================
+
+âæ¦è¦
+
+SAMD51 ã¿ã¼ã²ããä¾å­é¨ã¯ï¼MicroChip SAM D51	 ããµãã¼ããã¦ããï¼
+ãã¼ãã¨ãã¦ã¯ï¼Wio Terminal ããµãã¼ããã¦ããï¼
+
+âã«ã¼ãã«ã®ä½¿ç¨ãªã½ã¼ã¹
+
+ã«ã¼ãã«ã¯ä»¥ä¸ã®ãªã½ã¼ã¹ãä½¿ç¨ããï¼
+
+  ã»ROM/RAM
+     ã³ã¼ãã¨ãã¼ã¿ãé
+ç½®ããï¼
+     ä½¿ç¨éã¯ãªãã¸ã§ã¯ãæ°ã«ä¾å­ããï¼
+  
+  ã»SysTick
+     ã«ã¼ãã«å
+é¨ã®ãã£ãã¯ã®çæã«ç¨ããï¼
+     
+  ã»SERCOM2
+     ã³ã³ã½ã¼ã«ã®åºåã«ä½¿ç¨ï¼
+
+âå¤æ´å±¥æ­´
+
+2020/09/21
+ã»æ°è¦ä½æ
Index: /asp_wio_terminal/trunk/target/samd51_gcc/target_vector.c
===================================================================
--- /asp_wio_terminal/trunk/target/samd51_gcc/target_vector.c	(revision 460)
+++ /asp_wio_terminal/trunk/target/samd51_gcc/target_vector.c	(revision 460)
@@ -0,0 +1,223 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2015 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN  
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  @(#) $Id: target_config.c 2697 2015-11-06 04:00:42Z ertl-honda $
+ */
+
+/*
+ * ãããä¾å­ãã¯ã¿ã¼ãã¼ãã«ï¼SAMD51ç¨ï¼
+ */
+#include "kernel_impl.h"
+
+ /*
+  *  ãã¯ã¿ãã¼ãã«
+  */
+__attribute__ ((aligned(0x400U)))
+__attribute__((section(".rodata.vector")))
+const  FP _kernel_vector_table[] =      
+{                                    
+	(FP)(NULL), /* 0 The initial stack pointer */
+	(FP)_start,           /* 1 The reset handler */
+	(FP)(core_exc_entry), /* 2 */
+	(FP)(core_exc_entry), /* 3 */
+	(FP)(core_exc_entry), /* 4 */
+	(FP)(core_exc_entry), /* 5 */
+	(FP)(core_exc_entry), /* 6 */
+	(FP)(core_exc_entry), /* 7 */
+	(FP)(core_exc_entry), /* 8 */
+	(FP)(core_exc_entry), /* 9 */
+	(FP)(core_exc_entry), /* 10 */
+	(FP)(svc_handler),    /* 11 SVCall handler */
+	(FP)(core_exc_entry), /* 12 */
+	(FP)(core_exc_entry), /* 13 */
+	(FP)(core_exc_entry), /* 14 */
+	(FP)(core_int_entry), /* 15 */
+	(FP)(core_int_entry), /* 16 */
+	(FP)(core_int_entry), /* 17 */
+	(FP)(core_int_entry), /* 18 */
+	(FP)(core_int_entry), /* 19 */
+	(FP)(core_int_entry), /* 20 */
+	(FP)(core_int_entry), /* 21 */
+	(FP)(core_int_entry), /* 22 */
+	(FP)(core_int_entry), /* 23 */
+	(FP)(core_int_entry), /* 24 */
+	(FP)(core_int_entry), /* 25 */
+	(FP)(core_int_entry), /* 26 */
+	(FP)(core_int_entry), /* 27 */
+	(FP)(core_int_entry), /* 28 */
+	(FP)(core_int_entry), /* 29 */
+	(FP)(core_int_entry), /* 30 */
+	(FP)(core_int_entry), /* 31 */
+	(FP)(core_int_entry), /* 32 */
+	(FP)(core_int_entry), /* 33 */
+	(FP)(core_int_entry), /* 34 */
+	(FP)(core_int_entry), /* 35 */
+	(FP)(core_int_entry), /* 36 */
+	(FP)(core_int_entry), /* 37 */
+	(FP)(core_int_entry), /* 38 */
+	(FP)(core_int_entry), /* 39 */
+	(FP)(core_int_entry), /* 40 */
+	(FP)(core_int_entry), /* 41 */
+	(FP)(core_int_entry), /* 42 */
+	(FP)(core_int_entry), /* 43 */
+	(FP)(core_int_entry), /* 44 */
+	(FP)(core_int_entry), /* 45 */
+	(FP)(core_int_entry), /* 46 */
+	(FP)(core_int_entry), /* 47 */
+	(FP)(core_int_entry), /* 48 */
+	(FP)(core_int_entry), /* 49 */
+	(FP)(core_int_entry), /* 50 */
+	(FP)(core_int_entry), /* 51 */
+	(FP)(core_int_entry), /* 52 */
+	(FP)(core_int_entry), /* 53 */
+	(FP)(core_int_entry), /* 54 */
+	(FP)(core_int_entry), /* 55 */
+	(FP)(core_int_entry), /* 56 */
+	(FP)(core_int_entry), /* 57 */
+	(FP)(core_int_entry), /* 58 */
+	(FP)(core_int_entry), /* 59 */
+	(FP)(core_int_entry), /* 60 */
+	(FP)(core_int_entry), /* 61 */
+	(FP)(core_int_entry), /* 62 */
+	(FP)(core_int_entry), /* 63 */
+	(FP)(core_int_entry), /* 64 */
+	(FP)(core_int_entry), /* 65 */
+	(FP)(core_int_entry), /* 66 */
+	(FP)(core_int_entry), /* 67 */
+	(FP)(core_int_entry), /* 68 */
+	(FP)(core_int_entry), /* 69 */
+	(FP)(core_int_entry), /* 70 */
+	(FP)(core_int_entry), /* 71 */
+	(FP)(core_int_entry), /* 72 */
+	(FP)(core_int_entry), /* 73 */
+	(FP)(core_int_entry), /* 74 */
+	(FP)(core_int_entry), /* 75 */
+	(FP)(core_int_entry), /* 76 */
+	(FP)(core_int_entry), /* 77 */
+	(FP)(core_int_entry), /* 78 */
+	(FP)(core_int_entry), /* 79 */
+	(FP)(core_int_entry), /* 80 */
+	(FP)(core_int_entry), /* 81 */
+	(FP)(core_int_entry), /* 82 */
+	(FP)(core_int_entry), /* 83 */
+	(FP)(core_int_entry), /* 84 */
+	(FP)(core_int_entry), /* 85 */
+	(FP)(core_int_entry), /* 86 */
+	(FP)(core_int_entry), /* 87 */
+	(FP)(core_int_entry), /* 88 */
+	(FP)(core_int_entry), /* 89 */
+	(FP)(core_int_entry), /* 90 */
+	(FP)(core_int_entry), /* 91 */
+	(FP)(core_int_entry), /* 92 */
+	(FP)(core_int_entry), /* 93 */
+	(FP)(core_int_entry), /* 94 */
+	(FP)(core_int_entry), /* 95 */
+	(FP)(core_int_entry), /* 96 */
+	(FP)(core_int_entry), /* 97 */
+	(FP)(core_int_entry), /* 98 */
+	(FP)(core_int_entry), /* 99 */
+	(FP)(core_int_entry), /* 100 */
+	(FP)(core_int_entry), /* 101 */
+	(FP)(core_int_entry), /* 102 */
+	(FP)(core_int_entry), /* 103 */
+	(FP)(core_int_entry), /* 104 */
+	(FP)(core_int_entry), /* 105 */
+	(FP)(core_int_entry), /* 106 */
+	(FP)(core_int_entry), /* 107 */
+	(FP)(core_int_entry), /* 108 */
+	(FP)(core_int_entry), /* 109 */
+	(FP)(core_int_entry), /* 110 */
+	(FP)(core_int_entry), /* 111 */
+	(FP)(core_int_entry), /* 112 */
+	(FP)(core_int_entry), /* 113 */
+	(FP)(core_int_entry), /* 114 */
+	(FP)(core_int_entry), /* 115 */
+	(FP)(core_int_entry), /* 116 */
+	(FP)(core_int_entry), /* 117 */
+	(FP)(core_int_entry), /* 118 */
+	(FP)(core_int_entry), /* 119 */
+	(FP)(core_int_entry), /* 120 */
+	(FP)(core_int_entry), /* 121 */
+	(FP)(core_int_entry), /* 122 */
+	(FP)(core_int_entry), /* 123 */
+	(FP)(core_int_entry), /* 124 */
+	(FP)(core_int_entry), /* 125 */
+	(FP)(core_int_entry), /* 126 */
+	(FP)(core_int_entry), /* 127 */
+	(FP)(core_int_entry), /* 128 */
+	(FP)(core_int_entry), /* 129 */
+	(FP)(core_int_entry), /* 130 */
+	(FP)(core_int_entry), /* 131 */
+	(FP)(core_int_entry), /* 132 */
+	(FP)(core_int_entry), /* 133 */
+	(FP)(core_int_entry), /* 134 */
+	(FP)(core_int_entry), /* 135 */
+	(FP)(core_int_entry), /* 136 */
+	(FP)(core_int_entry), /* 137 */
+	(FP)(core_int_entry), /* 138 */
+	(FP)(core_int_entry), /* 139 */
+	(FP)(core_int_entry), /* 140 */
+	(FP)(core_int_entry), /* 141 */
+	(FP)(core_int_entry), /* 142 */
+	(FP)(core_int_entry), /* 143 */
+	(FP)(core_int_entry), /* 144 */
+	(FP)(core_int_entry), /* 145 */
+	(FP)(core_int_entry), /* 146 */
+	(FP)(core_int_entry), /* 147 */
+	(FP)(core_int_entry), /* 148 */
+	(FP)(core_int_entry), /* 149 */
+	(FP)(core_int_entry), /* 150 */
+	(FP)(core_int_entry), /* 151 */
+	(FP)(core_int_entry), /* 152 */
+	(FP)(core_int_entry), /* 153 */
+	(FP)(core_int_entry), /* 154 */
+};
