Index: /ssp_rpi3/trunk/arch/arm64_gcc/MANIFEST
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/MANIFEST	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/MANIFEST	(revision 384)
@@ -0,0 +1,28 @@
+PACKAGE ssp_arch_arm64_gcc
+VERSION 1.3.0
+
+MANIFEST
+common/Makefile.core
+common/arm64.h
+common/core_cfg1_out.h
+common/core_check.trb
+common/core_config.c
+common/core_config.h
+common/core_design.txt
+common/core_kernel.h
+common/core_kernel.trb
+common/core_rename.def
+common/core_rename.h
+common/core_sil.h
+common/core_stddef.h
+common/core_support.S
+common/core_sym.def
+common/core_test.h
+common/core_timer.c
+common/core_timer.cfg
+common/core_timer.h
+common/core_unrename.h
+common/core_user.txt
+
+INCLUDE bcm283x/MANIFEST
+INCLUDE ../../target/rpi_arm64_gcc/MANIFEST
Index: /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/MANIFEST
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/MANIFEST	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/MANIFEST	(revision 384)
@@ -0,0 +1,28 @@
+PACKAGE ssp_arch_arm64_gcc
+VERSION 1.3.0
+
+MANIFEST
+Makefile.chip
+bcm2837.h
+chip_cfg1_out.h
+chip_check.trb
+chip_config.c
+chip_config.h
+chip_design.txt
+chip_kernel.h
+chip_kernel.trb
+chip_rename.def
+chip_rename.h
+chip_serial.c
+chip_serial.cfg
+chip_serial.h
+chip_sil.h
+chip_stddef.h
+chip_support.S
+chip_sym.def
+chip_test.h
+chip_timer.cfg
+chip_timer.h
+chip_unrename.h
+chip_user.txt
+pl011.h
Index: /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/Makefile.chip
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/Makefile.chip	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/Makefile.chip	(revision 384)
@@ -0,0 +1,60 @@
+#
+#  Makefile ã®ãããä¾å­é¨ï¼BCM2837ç¨ï¼
+#
+
+#
+#  ãã£ã¬ã¯ããªåã®å®ç¾©
+#
+CHIPDIR = $(SRCDIR)/arch/$(CORE)_$(TOOL)/$(CHIP)
+
+#
+#  ã³ã³ãã¤ã«ãªãã·ã§ã³
+#
+COPTS := $(COPTS) -mtune=cortex-a53 -mcpu=cortex-a53
+CDEFS := $(CDEFS)
+INCLUDES := $(INCLUDES) -I$(CHIPDIR)
+LDFLAGS := $(LDFLAGS) -mcpu=cortex-a53
+LIBS := $(LIBS)
+
+#
+#  ã·ã¹ãã ãµã¼ãã¹ã«é¢ããå®ç¾©
+#
+SYSSVC_DIRS := $(SYSSVC_DIRS)
+SYSSVC_ASMOBJS := $(SYSSVC_ASMOBJS)
+SYSSVC_COBJS := $(SYSSVC_COBJS) chip_serial.o
+SYSSVC_CFLAGS := $(SYSSVC_CFLAGS)
+SYSSVC_LIBS := $(SYSSVC_LIBS)
+
+#
+#  ã«ã¼ãã«ã«é¢ããå®ç¾©
+#
+KERNEL_DIRS := $(KERNEL_DIRS) $(CHIPDIR)
+KERNEL_ASMOBJS := $(KERNEL_ASMOBJS) chip_support.o
+KERNEL_COBJS := $(KERNEL_COBJS) chip_config.o
+KERNEL_CFLAGS := $(KERNEL_CFLAGS)
+
+#
+#  ã³ã³ãã£ã®ã¥ã¬ã¼ã¿é¢ä¿ã®å¤æ°ã®å®ç¾©
+#
+CFG_TABS := $(CFG_TABS) --symval-table $(CHIPDIR)/chip_sym.def
+CFG1_OUT_LDFLAGS := $(CFG1_OUT_LDFLAGS)
+CFG_OBJS := $(CFG_OBJS)
+CFG2_OUT := $(CFG2_OUT)
+
+#
+#  ä¾å­é¢ä¿ã®å®ç¾©
+#
+cfg1_out.c: $(CHIPDIR)/chip_sym.def
+kernel_cfg.timestamp: $(CHIPDIR)/chip_kernel.trb
+check.timestamp: $(CHIPDIR)/chip_check.trb
+
+#
+#  ãã®ä»
+#
+CLEAN_FILES := $(CLEAN_FILES)
+REALCLEAN_FILES := $(REALCLEAN_FILES)
+
+#
+#  ARM64ä¾å­é¨ã®ã¤ã³ã¯ã«ã¼ã
+#
+include $(SRCDIR)/arch/$(CORE)_$(TOOL)/common/Makefile.core
Index: /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/bcm2837.h
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/bcm2837.h	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/bcm2837.h	(revision 384)
@@ -0,0 +1,252 @@
+/*
+ *  TOPPERS Software
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *
+ *  Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2018,2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  $Id$
+ */
+#ifndef TOPPERS_BCM2837_H
+#define TOPPERS_BCM2837_H
+
+#include <sil.h>
+
+/*
+ *  å²è¾¼ã¿çªå·ï¼intnoï¼ã®å®ç¾©
+ */
+// Core interrupts
+#define TINTNO_CNTPS        0    // CNTPSIRQ
+#define TINTNO_CNTPNS       1    // CNTPNSIRQ
+#define TINTNO_CNTHP        2    // CNTHPIRQ
+#define TINTNO_CNTV         3    // CNTVIRQ
+#define TINTNO_MBOX0        4    // Mailbox 0
+#define TINTNO_MBOX1        5    // Mailbox 1
+#define TINTNO_MBOX2        6    // Mailbox 2
+#define TINTNO_MBOX3        7    // Mailbox 3
+#define TINTNO_PMU          9    // PMU
+#define TINTNO_AXI         10    // AXI-outstanding
+#define TINTNO_LTIMER      11    // Local timer
+
+// Basic interrupts
+#define TINTNO_ARMTIMER    32    // ARM timer
+#define TINTNO_MBOX        33    // ARM mailbox
+#define TINTNO_ARMDRBELL0  34    // ARM doorbell 0
+#define TINTNO_ARMDRBELL1  35    // ARM doorbell 1
+#define TINTNO_GPU0HALTED  36    // GPU0 halted
+#define TINTNO_GPU1HALTED  37    // GPU1 halted
+#define TINTNO_ILACSS0     38    // Illegal access type 1
+#define TINTNO_ILACSS1     39    // Illegal access type 0
+
+// GPU0 interrupts
+#define TINTNO_AUX         93    // Aux
+
+// GPU1 interrupts
+#define TINTNO_I2CSPISLV  107
+#define TINTNO_PWA0       109
+#define TINTNO_PWA1       110
+#define TINTNO_SMI        112
+#define TINTNO_GPIO0      113
+#define TINTNO_GPIO1      114
+#define TINTNO_GPIO2      115
+#define TINTNO_GPIO3      116
+#define TINTNO_I2C        117
+#define TINTNO_SPI        118
+#define TINTNO_PCM        119
+#define TINTNO_UART       121
+
+
+/*
+ *  å²è¾¼ã¿çªå·ã®æå°å¤ã¨æå¤§å¤
+ */
+#define TMIN_INTNO              UINT_C(0)
+#define TMAX_INTNO              UINT_C(127)
+
+/*
+ *  ã¡ã¢ãªããããI/Oã®ãã¼ã¹ã¢ãã¬ã¹
+ */
+#define MMIO_BASE               0x3F000000
+
+/*
+ *  å²è¾¼ã¿é¢é£ã¬ã¸ã¹ã¿
+ */
+#define IRQ_PEND_B              0x3f00b200
+#define IRQ_PEND_1              0x3f00b204
+#define IRQ_PEND_2              0x3f00b208
+#define ENABLE_IRQ_1            0x3f00b210
+#define ENABLE_IRQ_2            0x3f00b214
+#define ENABLE_IRQ_B            0x3f00b218
+#define DISABLE_IRQ_1           0x3f00b21C
+#define DISABLE_IRQ_2           0x3f00b220
+#define DISABLE_IRQ_B           0x3f00b224
+
+#define CORE0_IRQ_SRC           0x40000060
+
+
+/*
+ * GPIO
+ */
+#define GPFSEL0         (MMIO_BASE+0x00200000)
+#define GPFSEL1         (MMIO_BASE+0x00200004)
+#define GPFSEL2         (MMIO_BASE+0x00200008)
+#define GPFSEL3         (MMIO_BASE+0x0020000C)
+#define GPFSEL4         (MMIO_BASE+0x00200010)
+#define GPFSEL5         (MMIO_BASE+0x00200014)
+#define GPSET0          (MMIO_BASE+0x0020001C)
+#define GPSET1          (MMIO_BASE+0x00200020)
+#define GPCLR0          (MMIO_BASE+0x00200028)
+#define GPLEV0          (MMIO_BASE+0x00200034)
+#define GPLEV1          (MMIO_BASE+0x00200038)
+#define GPEDS0          (MMIO_BASE+0x00200040)
+#define GPEDS1          (MMIO_BASE+0x00200044)
+#define GPHEN0          (MMIO_BASE+0x00200064)
+#define GPHEN1          (MMIO_BASE+0x00200068)
+#define GPPUD           (MMIO_BASE+0x00200094)
+#define GPPUDCLK0       (MMIO_BASE+0x00200098)
+#define GPPUDCLK1       (MMIO_BASE+0x0020009C)
+
+
+/*
+ *  UARTã¬ã¸ã¹ã¿ã®ãã¼ã¹ã¢ãã¬ã¹
+ */
+#define RPI_UART0_BASE  (MMIO_BASE + 0x00201000)
+
+/*
+ *  ãã¼ã¬ã¼ãè¨­å®
+ */
+#define RPI_UART_IBRD_38400     0x27U    // 38400bps
+#define RPI_UART_FBRD_38400     0x04U
+#define RPI_UART_IBRD_115200    0x2U    // 115200bps
+#define RPI_UART_FBRD_115200    0xbU
+
+/*
+ * ã¡ã¼ã«ããã¯ã¹é¢é£
+ *    https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface
+ */
+#define VIDEOCORE_MBOX  (MMIO_BASE+0x0000B880)
+
+#define MBOX_READ       (VIDEOCORE_MBOX+0x0)
+#define MBOX_POLL       (VIDEOCORE_MBOX+0x10)
+#define MBOX_SENDER     (VIDEOCORE_MBOX+0x14)
+#define MBOX_STATUS     (VIDEOCORE_MBOX+0x18)
+#define MBOX_CONFIG     (VIDEOCORE_MBOX+0x1C)
+#define MBOX_WRITE      (VIDEOCORE_MBOX+0x20)
+#define MBOX_RESPONSE   0x80000000
+#define MBOX_FULL       0x80000000
+#define MBOX_EMPTY      0x40000000
+
+#define MBOX_REQUEST    0
+
+/* ãã£ãã« */
+#define MBOX_CH_POWER   0
+#define MBOX_CH_FB      1
+#define MBOX_CH_VUART   2
+#define MBOX_CH_VCHIQ   3
+#define MBOX_CH_LEDS    4
+#define MBOX_CH_BTNS    5
+#define MBOX_CH_TOUCH   6
+#define MBOX_CH_COUNT   7
+#define MBOX_CH_PROP    8
+
+/* tags */
+#define MBOX_TAG_GETSERIAL      0x10004
+#define MBOX_TAG_LAST           0
+
+#define MBOX_REQUEST    0
+
+/* channels */
+#define MBOX_CH_POWER   0
+#define MBOX_CH_FB      1
+#define MBOX_CH_VUART   2
+#define MBOX_CH_VCHIQ   3
+#define MBOX_CH_LEDS    4
+#define MBOX_CH_BTNS    5
+#define MBOX_CH_TOUCH   6
+#define MBOX_CH_COUNT   7
+#define MBOX_CH_PROP    8
+
+/* tags */
+#define MBOX_TAG_GETSERIAL      0x10004
+#define MBOX_TAG_SETCLKRATE     0x38002
+#define MBOX_TAG_LAST           0
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ * mailbox å¼ã³åºã
+ *    æ³¨æï¼ç¬¬2å¼æ°ã®ã¢ãã¬ã¹ã¯16ãã¤ãã¢ã©ã¤ã¡ã³ãã§ãããã¨
+ */
+Inline int_t mbox_call(unsigned char ch, volatile uint32_t *mbox)
+{
+    uint32_t r = (((uint32_t)((uint64_t)mbox) & ~0xF) | (ch & 0xF));
+
+    // ä½¿ããããã«ãªãã¾ã§å¾
+ã¤
+    do{
+        Asm("nop");
+    } while(sil_rew_mem((uint32_t *)MBOX_STATUS) & MBOX_FULL);
+
+    // ãã£ãã«ã®è­å¥å­ãä»å ãã¦ã¡ãã»ã¼ã¸ã®ã¢ãã¬ã¹ãæ¸ãè¾¼ã¿
+    sil_wrw_mem((uint32_t *)MBOX_WRITE , r);
+
+    while(1) {
+        // å¿ç­ãããã¾ã§å¾
+ã¤
+        do{
+            Asm("nop");
+        } while(sil_rew_mem((uint32_t *)MBOX_STATUS) & MBOX_EMPTY);
+
+        if(r == sil_rew_mem((uint32_t *)MBOX_READ))
+            return mbox[1] == MBOX_RESPONSE;
+    }
+    return 0;
+}
+
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_BCM2837_H */
Index: /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_cfg1_out.h
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_cfg1_out.h	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_cfg1_out.h	(revision 384)
@@ -0,0 +1,9 @@
+/*
+ *  cfg1_out.cããªã³ã¯ããããã«å¿
+è¦ãªã¹ã¿ãã®å®ç¾©
+ */
+
+/*
+ *  ã³ã¢ä¾å­ã®ã¹ã¿ãã®å®ç¾©
+ */
+#include "arm64_gcc/common/core_cfg1_out.h"
Index: /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_check.trb
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_check.trb	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_check.trb	(revision 384)
@@ -0,0 +1,50 @@
+# -*- coding: utf-8 -*-
+# 
+#  ãã¹3ã®çæã¹ã¯ãªããã®ãããä¾å­é¨ï¼BCM2837ç¨ï¼
+# 
+IncludeTrb("arm64_gcc/common/core_check.trb")
+
+#
+#  å²è¾¼ã¿ãã³ãã©ãã¼ãã«ã«é¢ãããã§ãã¯
+#
+# DEF_INHã§ç»é²ããå²è¾¼ã¿ãã³ãã©ã®ã¿ãã§ãã¯ããï¼éã«è¨ãã¨ï¼ã³ã³ãã£
+# ã®ã¥ã¬ã¼ã¿ã§çæããå²è¾¼ã¿ãã³ãã©ãï¼default_int_handlerã®ãã§ãã¯ã¯
+# è¡ããªãï¼
+#
+inhinib_entry = SYMBOL("_kernel_inhinib_entry")
+$cfgData[:DEF_INH].each do |key, params|
+  inthdr = PEEK(inhinib_entry, $sizeof_FP)
+
+  #     å²è¾¼ã¿ãã³ãã©ã®å
+é ­çªå°ã®ãã§ãã¯
+  if (inthdr & ($CHECK_FUNC_ALIGN - 1)) != 0
+    error_wrong_id("E_PAR", params, :inthdr, :inhno, "not aligned")
+  end
+  if $CHECK_FUNC_NONNULL && inthdr == 0
+    error_wrong_id("E_PAR", params, :inthdr, :inhno, "null")
+  end
+
+  inhinib_entry += $sizeof_FP
+end
+
+#
+#  CPUä¾å¤ãã³ãã©ãã¼ãã«ã«é¢ãããã§ãã¯
+#
+# DEF_EXCã§ç»é²ããCPUä¾å¤ãã³ãã©ã®ã¿ãã§ãã¯ããï¼éã«è¨ãã¨ï¼
+# default_exc_handlerã®ãã§ãã¯ã¯è¡ããªãï¼
+#
+excinib_entry = SYMBOL("_kernel_excinib_entry")
+$cfgData[:DEF_EXC].each do |key, params|
+  exchdr = PEEK(excinib_entry, $sizeof_FP)
+
+  # CPUä¾å¤ãã³ãã©ã®å
+é ­çªå°ã®ãã§ãã¯
+  if (exchdr & ($CHECK_FUNC_ALIGN - 1)) != 0
+    error_wrong_id("E_PAR", params, :exchdr, :excno, "not aligned")
+  end
+  if $CHECK_FUNC_NONNULL && exchdr == 0
+    error_wrong_id("E_PAR", params, :exchdr, :excno, "null")
+  end
+
+  excinib_entry += $sizeof_FP
+end
Index: /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_config.c
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_config.c	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_config.c	(revision 384)
@@ -0,0 +1,239 @@
+/*
+ *  TOPPERS Software
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *
+ *  Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2018,2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ */
+/*
+ *  ãããä¾å­å¦çï¼BCM2837ç¨ï¼
+ */
+#include <sil.h>
+#include "kernel_impl.h"
+
+/*
+ *  ãã­ã»ããµã®å²è¾¼ã¿åªå
+åº¦
+ */
+PRI current_intpri;
+
+/*
+ *  ãããã®åæå
+ */
+void
+chip_initialize(void)
+{
+    uint32_t tmp;
+
+    /*
+     *  ARM64ä¾å­ã®åæå
+     */
+    core_initialize();
+
+    /*
+     *  ã¢ã©ã¤ã¡ã³ããã§ãã¯æå¹
+     */
+    tmp = (1<<3)|(1<<1);
+    Asm("msr sctlr_el1, %0"::"r"(tmp));
+
+    /*
+     *  å²è¾¼ã¿ãã¹ã¯ã®åæå
+     */
+    sil_wrw_mem((uint32_t *)(DISABLE_IRQ_B), 0xffffffff);  // basic interrupt
+    sil_wrw_mem((uint32_t *)(DISABLE_IRQ_1), 0xffffffff);  // gpu1
+    sil_wrw_mem((uint32_t *)(DISABLE_IRQ_2), 0xffffffff);  // gpu2
+
+    // ä½¿ç¨ããå²è¾¼ã¿ã®è¨±å¯
+    chip_unmask_interrupt(0);
+}
+
+/*
+ *  ãããã®çµäºå¦ç
+ */
+void
+chip_terminate(void)
+{
+    /*
+     *  å²è¾¼ã¿ç¦æ­¢
+     */
+    chip_mask_interrupt(INT_IPM(TMIN_INTPRI));
+
+    core_terminate();
+}
+
+/*
+ *  å²è¾¼ã¿è¦æ±ã©ã¤ã³å±æ§ã®è¨­å®
+ */
+void
+x_config_int(INTNO intno, ATR intatr, PRI intpri)
+{
+    // BCM283X ã¯ã¨ãã¸/ã¬ãã«ã®è¨­å®ãå²è¾¼ã¿åªå
+åº¦ã®è¨­å®æ©è½ãæããªã
+    assert(VALID_INTNO(intno));
+    assert(TMIN_INTPRI <= intpri && intpri <= TMAX_INTPRI);
+}
+
+/*
+ *  çºçããå²è¾¼ã¿ã®åªå
+åº¦ã«å¿ãã¦å²è¾¼ã¿ããã¹ã¯ãã
+ *  å²è¾¼ã¿ã®å
+¥å£å¦çããã³åæåå¦çããå¼ã³åºããã
+ *    priï¼å²è¾¼ã¿è¦å ã®å²è¾¼ã¿åªå
+åº¦(å
+é¨è¡¨ç¾)
+ */
+void
+chip_mask_interrupt(PRI pri)
+{
+    uint32_t reg;
+    uint32_t mask_c, mask_b, mask_1, mask_2;
+
+    current_intpri = pri;
+
+    mask_c = _kernel_iipm_mask_table[pri * 4];
+    mask_b = _kernel_iipm_mask_table[pri * 4 + 1];
+    mask_1 = _kernel_iipm_mask_table[pri * 4 + 2];
+    mask_2 = _kernel_iipm_mask_table[pri * 4 + 3];
+
+    /*
+     *  å²è¾¼ã¿ã®ãã¹ã¯
+     */
+    // core interrupt(core timers)
+    reg = sil_rew_mem((uint32_t *)(0x40000040)); // Core0 Timer interrupt control
+    reg &= ~(mask_c & 0xf);
+    sil_wrw_mem((uint32_t *)(0x40000040), reg);
+
+    // core interrupt(mailbox)
+    reg = sil_rew_mem((uint32_t *)(0x40000050)); // Core0 mailboxes interrupt control
+    reg &= ~((mask_c & 0xf0)>>4);
+    sil_wrw_mem((uint32_t *)(0x40000050), reg);
+
+    // core interrupt(PMU interrupt)
+    if((mask_c & (1<<9)) != 0) {
+        sil_wrw_mem((uint32_t *)(0x40000014), 1);    // PMU interrupt routing write-clear
+    }
+
+    // core interrupt(AXI outstanding interrupt)
+    reg = sil_rew_mem((uint32_t *)(0x40000030));    // AXI outstanding interrupt
+    if(((mask_c & (1 << 10)) != 0) && ((reg & (1<<20)) != 0)) {
+        reg &= ~(1<<20);
+        sil_wrw_mem((uint32_t *)(0x40000030), reg);
+    }
+
+    // core interrupt(local timer)
+    reg = sil_rew_mem((uint32_t *)(0x40000034));    // local timer control & status
+    if(((mask_c & (1 << 11)) != 0) && ((reg & (1<<29)) != 0)) {
+        reg &= ~(1<<29);
+        sil_wrw_mem((uint32_t *)(0x40000034), reg);
+    }
+
+    // basic interrupt, GPU pending 1 and 2
+    sil_wrw_mem((uint32_t *)(DISABLE_IRQ_B), mask_b);
+    sil_wrw_mem((uint32_t *)(DISABLE_IRQ_1), mask_1);
+    sil_wrw_mem((uint32_t *)(DISABLE_IRQ_2), mask_2);
+}
+
+/*
+ *  ãã¹ã¯ããå²è¾¼ã¿ãå²è¾¼ã¿çºçåã®ç¶æ
+ã«æ»ã
+ *  ãã³ãã©å®è¡å¾ï¼åºå£å¦çã®å®è¡åã«å¼ã³åºããã
+ *    priï¼å²è¾¼ã¿çºçåã®å²è¾¼ã¿åªå
+åº¦
+ */
+void
+chip_unmask_interrupt(PRI pri)
+{
+    uint32_t reg;
+    uint32_t mask_c, mask_b, mask_1, mask_2;
+
+    current_intpri = pri;
+
+    mask_c = ~(_kernel_iipm_mask_table[pri * 4]);
+    mask_b = ~(_kernel_iipm_mask_table[pri * 4 + 1]);
+    mask_1 = ~(_kernel_iipm_mask_table[pri * 4 + 2]);
+    mask_2 = ~(_kernel_iipm_mask_table[pri * 4 + 3]);
+
+    /*
+     *  ãã¹ã¯è§£é¤
+     */
+    // core interrupt(core timers)
+    reg = sil_rew_mem((uint32_t *)(0x40000040)); // Core0 Timer interrupt control
+    reg |= (mask_c & 0xf);
+    sil_wrw_mem((uint32_t *)(0x40000040), reg);
+
+    // core interrupt(mailbox)
+    reg = sil_rew_mem((uint32_t *)(0x40000050)); // Core0 mailboxes interrupt control
+    reg |= (mask_c & 0xf0)>>4;
+    sil_wrw_mem((uint32_t *)(0x40000050), reg);
+
+    // core interrupt(PMU interrupt)
+    if((mask_c & (1<<9)) != 0) {
+        sil_wrw_mem((uint32_t *)(0x40000010), 1);    // PMU interrupt routing write-set
+    }
+
+    // core interrupt(AXI outstanding interrupt)
+    reg = sil_rew_mem((uint32_t *)(0x40000030));    // AXI outstanding interrupt
+    if(((mask_c & (1 << 10)) != 0) && ((reg & (1<<20)) == 0)) {
+        reg |= (1<<20);
+        sil_wrw_mem((uint32_t *)(0x40000030), reg);
+    }
+
+    // core interrupt(local timer)
+    reg = sil_rew_mem((uint32_t *)(0x40000034));    // local timer control & status
+    if(((mask_c & (1 << 11)) != 0) && ((reg & (1<<29)) == 0)) {
+        reg |= (1<<29);
+        sil_wrw_mem((uint32_t *)(0x40000034), reg);
+    }
+
+    // basic interrupt, GPU pending 1 and 2
+    sil_wrw_mem((uint32_t *)(ENABLE_IRQ_B), mask_b);
+    sil_wrw_mem((uint32_t *)(ENABLE_IRQ_1), mask_1);
+    sil_wrw_mem((uint32_t *)(ENABLE_IRQ_2), mask_2);
+}
Index: /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_config.h
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_config.h	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_config.h	(revision 384)
@@ -0,0 +1,305 @@
+/*
+ *  TOPPERS Software
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *
+ *  Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2018,2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ */
+
+/*
+ *  ãããä¾å­å¦ç(BCM2837ç¨)
+ *
+ *  ãã®ããããã¡ã¤ã«ã¯ï¼target_config.hï¼ã¾ãã¯ï¼ããããã¤ã³ã¯ã«ã¼ã
+ *  ããããã¡ã¤ã«ï¼ã®ã¿ããã¤ã³ã¯ã«ã¼ããããï¼
+ *  ä»ã®ãã¡ã¤ã«ããç´æ¥ã¤ã³ã¯ã«ã¼ããã¦ã¯ãªããªãï¼
+ */
+
+#ifndef TOPPERS_CHIP_CONFIG_H
+#define TOPPERS_CHIP_CONFIG_H
+
+/*
+ *  ãã¼ãã¦ã§ã¢å®ç¾©
+ */
+#include "bcm2837.h"
+
+/*
+ *  å²è¾¼ã¿é¢é£
+ */
+
+/*
+ *  å²è¾¼ã¿åªå
+åº¦ã®å¤æ
+ */
+#define EXT_IPM(pri)  (-pri)    // å
+é¨è¡¨ç¾ããå¤é¨è¡¨ç¾ã¸
+#define INT_IPM(ipm)  (-ipm)    // å¤é¨è¡¨ç¾ããå
+é¨è¡¨ç¾ã¸
+
+/*
+ *  TIPM_ENAALLï¼å²è¾¼ã¿åªå
+åº¦ãã¹ã¯å
+¨è§£é¤ï¼ã®å
+é¨è¡¨ç¾
+ */
+#define IIPM_ENAALL  (0)
+
+/*
+ *  å²è¾¼ã¿çªå·ã®ç¯å²ã®å¤å®
+ */
+#define VALID_INTNO(intno)           ((TMIN_INTNO <= (intno)) && ((intno) <= TMAX_INTNO))
+#define VALID_INTNO_DISINT(intno)    VALID_INTNO(intno)
+
+/*
+ *  å²è¾¼ã¿ãã³ãã©ã®åºå
+¥å£å¦çã®çæãã¯ã­
+ */
+#define INT_ENTRY(inhno, inthdr)    inthdr
+#define INTHDR_ENTRY(inhno, inhno_num, inthdr) extern void inthdr(void);
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ *  CPUã­ãã¯ç¶æ
+ã¸ã®ç§»è¡
+ */
+Inline void
+x_lock_cpu(void)
+{
+    aarch64_set_daif_i();
+}
+
+#define t_lock_cpu()    x_lock_cpu()
+#define i_lock_cpu()    x_lock_cpu()
+
+/*
+ *  CPUã­ãã¯ç¶æ
+ã®è§£é¤
+ */
+Inline void
+x_unlock_cpu(void)
+{
+    aarch64_clear_daif_i();
+}
+
+#define t_unlock_cpu()    x_unlock_cpu()
+#define i_unlock_cpu()    x_unlock_cpu()
+
+/*
+ *  CPUã­ãã¯ç¶æ
+ã®åç
+§
+ */
+Inline bool_t
+x_sense_lock(void)
+{
+    bool_t state;
+
+    if(aarch64_sense_daif_irq()) {
+        state = true;
+    }
+    else {
+        state = false;
+    }
+
+    return state;
+}
+
+#define t_sense_lock()    x_sense_lock()
+#define i_sense_lock()    x_sense_lock()
+
+/*
+ *  ãã­ã»ããµã®å²è¾¼ã¿åªå
+åº¦
+ *    ãããã®å²è¾¼ã¿ã³ã³ãã­ã¼ã©ã«ã¯å²è¾¼ã¿åªå
+åº¦ã«ããå¶å¾¡æ©è½ã
+ *    å®è£
+ããã¦ããªãããï¼å²è¾¼ã¿åªå
+åº¦ãæ ¼ç´ããå¤æ°ãç¨æãã
+ */
+extern PRI current_intpri;
+
+/*
+ *  å²è¾¼ã¿ãã³ãã©ã®è¨­å®
+ */
+Inline void
+x_define_inh(INHNO inhno, FP int_entry)
+{
+}
+
+/*
+ *  å²è¾¼ã¿ãã³ãã©å
+¥å£ã§å¿
+è¦ãªIRCæä½
+ */
+Inline void
+i_begin_int(INTNO intno)
+{
+}
+
+/*
+ *  å²è¾¼ã¿ãã³ãã©ã®åºå£ã§å¿
+è¦ãªIRCæä½
+ */
+Inline void
+i_end_int(INTNO intno)
+{
+}
+
+/*
+ *  å²è¾¼ã¿è¦æ±ã©ã¤ã³ã®å±æ§ã®è¨­å®
+ */
+extern void x_config_int(INTNO intno, ATR intatr, PRI intpri);
+
+/*
+ *  å²è¾¼ã¿åªå
+åº¦ã«ãã¨ã¥ãå²è¾¼ã¿ã®ãã¹ã¯
+ *    å²è¾¼ã¿ã®å
+¥å£ã§ï¼åãä»ããå²è¾¼ã¿ã®å²è¾¼ã¿ã¬ãã«ã«å¿ãã¦
+ *    å²è¾¼ã¿ããã¹ã¯ãã
+ */
+extern void chip_mask_interrupt(PRI pri);
+
+/*
+ *  å²è¾¼ã¿ãã¹ã¯ã®è§£é¤
+ *    å²è¾¼ã¿ã®åºå£ã§ï¼åãä»ãç´åã®å²è¾¼ã¿ã¬ãã«ããã¨ã«
+ *    å²è¾¼ã¿ã®ãã¹ã¯ãè§£é¤ãã
+ */
+extern void chip_unmask_interrupt(PRI pri);
+
+/*
+ *  å²è¾¼ã¿å
+¥å£ã®å²è¾¼ã¿æä½ï¼chip_support.Sï¼
+ */
+extern void chip_int_entry(void);
+
+/*
+ *  å²è¾¼ã¿åªå
+åº¦ãã¼ãã«(kernel_cfg.c)
+ */
+extern const PRI intpri_table[];
+
+/*
+ *  å²è¾¼ã¿ãã¹ã¯ãã¼ãã«(kernel_cfg.c)
+ */
+extern const uint32_t iipm_mask_table[];
+
+/*
+ *  å²è¾¼ã¿ãã³ãã©ãã¼ãã«(kernel_cfg.c)
+ */
+extern const INTHDR inh_table[];
+
+#endif /* TOPPERS_MACRO_ONLY */
+
+
+
+/*
+ *  CPUä¾å¤é¢é£
+ */
+
+/*
+ *  CPUä¾å¤ãã³ãã©çªå·
+ */
+#define VALID_EXCNO_DEFEXC(excno)    (TMIN_EXCNO <= (excno) && (excno) <= TMAX_EXCNO)
+
+/*
+ *  CPUä¾å¤ãã³ãã©ã®å
+¥å£å¦çã®çæãã¯ã­
+ */
+#define EXC_ENTRY(excno, exchdr)    exchdr
+#define EXCHDR_ENTRY(excno, excno_num, exchdr) extern void exchdr(void *p_excinf);
+
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ *  CPUä¾å¤ãã³ãã©ã®è¨­å®
+ */
+Inline void
+x_define_exc(EXCNO excno, FP exc_entry)
+{
+}
+
+/*
+ *  ä¾å¤å
+¥å£ã®å²è¾¼ã¿æä½ï¼chip_support.Sï¼
+ */
+extern void chip_exc_entry(void);
+
+/*
+ *  ä¾å¤ãã³ãã©ãã¼ãã«(kernel_cfg.c)
+ */
+extern const EXCHDR exc_table[];
+
+#endif /* TOPPERS_MACRO_ONLY */
+
+/*
+ * ãã®ä»
+ */
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ *  ãããä¾å­ã®åæå
+ */
+extern void chip_initialize(void);
+
+/*
+ *  ãããä¾å­ã®çµäºå¦ç
+ */
+extern void chip_terminate(void) NoReturn;
+
+#endif /* TOPPERS_MACRO_ONLY */
+
+/*
+ *  ã³ã¢ä¾å­å®ç¾©
+ */
+#include "arm64_gcc/common/core_config.h"
+
+#endif /* TOPPERS_CHIP_CONFIG_H */
Index: /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_design.txt
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_design.txt	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_design.txt	(revision 384)
@@ -0,0 +1,262 @@
+=====================================================================
+                         BCM283x ãããä¾å­é¨è¨­è¨ã¡ã¢
+                                  Last Modified: 16 Apr 2019
+=====================================================================
+
+âãã®ãã­ã¥ã¡ã³ãã®ä½ç½®ã¥ã
+
+ãã®ãã­ã¥ã¡ã³ãã¯ï¼TOPPERS/SSPã«ã¼ãã«ãBCM283xã«ç§»æ¤ããéã®
+ãããåºæäºé 
+ã«é¢ããè¨­è¨ã¡ã¢ã§ããï¼
+
+(åè)
+
+(a) QA7(ARM Quad A7 core)
+https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/QA7_rev3.4.pdf
+
+(b) BCM2835 ARM Peripherals 
+https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2835/BCM2835-ARM-Peripherals.
+pdf
+
+
+[CPUã¢ã¼ã]
+
+âãªã»ããæã®ç¶æ
+
+
+ãªã»ããæï¼BCM283x (Cortex-A53) ã¯ï¼EL3h (ä½¿ç¨ã¹ã¿ãã¯ SP_EL3)ã§èµ·åããï¼
+
+
+[å²è¾¼ã¿]
+
+
+âå²è¾¼ã¿åªå
+åº¦
+
+BCM283x ã®å²è¾¼ã¿ã³ã³ãã­ã¼ã©ã¯åªå
+åº¦ãå®è£
+ããã¦ããªãï¼ãã®ãã
+åªå
+åº¦ã«åºã¥ãå²è¾¼ã¿ã®ãã¹ã¯ãã½ããã¦ã§ã¢ã§æ¬ä¼¼çã«å®è£
+ãã¦ããï¼
+å²è¾¼ã¿ã®å
+é¨åªå
+åº¦ã®å¤ã¯å¤é¨åªå
+åº¦ã®ç¬¦å·ãåè»¢ãããã®ãç¨ããããï¼
+å¤ã®å¤§ããæ¹ãé«åªå
+åº¦ã¨ãªãï¼
+
+åªå
+åº¦ã®ç¯å²ã¯èªç±ã«æ±ºãããã¨ãã§ããï¼æ¢å®ã®æé«å¤ã¯15ã¨ãªã£ã¦ããï¼
+
+
+âå²è¾¼ã¿/ä¾å¤ã®åä»
+
+å²è¾¼ã¿ä¿¡å·ãåä¿¡ããã¨ï¼BCM283xã®ãã³ãã£ã³ã°ã¬ã¸ã¹ã¿ã®è©²å½ããããããã»ãããããï¼
+å²è¾¼ã¿çªå·ã¯ãã®ã¬ã¸ã¹ã¿ã«ã»ãããããå¤ãä½¿ç¨ããï¼
+
+å²è¾¼ã¿ãã³ãã©çªå·ã¨å²è¾¼ã¿çªå·ã¯ï¼BCM2835åã³BCM2836ã®
+ããªãã§ã©ã«ããã¥ã¢ã«(ä¸è¨aåã³b)ããï¼ãã³ãã£ã³ã°ã¬ã¸ã¹ã¿ã®ãããä½ç½®ã«åºã¥ãã¦
+0ãã127ã®çªå·ãå²ãå½ã¦ãï¼(åã
+ã®å®ç¾©ã¯ bcm2837.h ãåç
+§)
+
+ 0 ... 31  Core interrupt (ä¸è¨aã®P16 ãCore0 interrupt sourceãã«å¯¾å¿)
+32 ... 63  ARM peripherals interrupt(bã®P113ãBasic pending registerãã«å¯¾å¿)
+64 ... 95  ARM peripherals interrupt(bã®P115ãGPU pending register 1ãã«å¯¾å¿)
+96 ...127  ARM peripherals interrupt(bã®P115ãGPU pending register 2ãã«å¯¾å¿)
+
+å²è¾¼ã¿ãåãä»ããã¨ä¾å¤ã¬ãã«ã¨ä¾å¤ã®ç¨®é¡ã«å¿ããæå®ã®ä½ç½®ãã
+å®è¡ãéå§ããç¹ã¯ã³ã¢ä¾å­é¨ã®èª¬æã¨åæ§ã§ãããï¼å²è¾¼ã¿ã®åªå
+åº¦ã®
+å¦çå
+å®¹ã«ã¤ãã¦ã¯ä»¥ä¸ã®ããã«ãªãï¼
+
+ã¾ãå²è¾¼ã¿ã®å
+¥å£å¦çã§ã¯ä»¥ä¸ã®å¦çãè¡ãï¼
+ã»å²è¾¼ã¿çºçæï¼å²è¾¼ã¿è¦å ãå
+ã«åªå
+åº¦ãåå¾ãã
+ã»åªå
+åº¦ãå
+ã«ï¼ãã®å²è¾¼ã¿åªå
+ã¬ãã«ã§å½è©²ã®å²è¾¼ã¿è¦å ããã¹ã¯ãããã©ãããæ±ºå®ããï¼
+ã»ãã®åªå
+åº¦ã§ãã¹ã¯ããå¿
+è¦ã®ããå²è¾¼ã¿ãå
+¨ã¦ãã¹ã¯ããï¼
+ã»CPUã­ãã¯ãè§£é¤ãï¼å²è¾¼ã¿ãã³ãã©ãå¼ã³åºãï¼
+
+å²è¾¼ã¿ãã³ãã©ããã®ãªã¿ã¼ã³å¾ï¼åºå£å¦çã«å
+¥ãåã«åªå
+åº¦ãå
+ã«æ»ãï¼
+ã»å²è¾¼ã¿çºçåã®å²è¾¼ã¿åªå
+åº¦ãã¹ã¿ãã¯ããåå¾ãã
+ã»å²è¾¼ã¿çºçåã®åªå
+åº¦ãå
+ã«ï¼ãã®å²è¾¼ã¿åªå
+åº¦ã§ãã¹ã¯è§£é¤ã®å¯¾è±¡ã¨ãªãå²è¾¼ã¿ãæ±ºãã
+ã»å¯¾è±¡ã¨ãªãå²è¾¼ã¿ã®å²è¾¼ã¿ãã¹ã¯ããã¹ã¦è§£é¤ããï¼
+
+å²è¾¼ã¿è¦å ã¨åªå
+åº¦ã¨ã®å¯¾å¿ï¼ããã³åªå
+åº¦ã¨ãã¹ã¯ãã¿ã¼ã³ã¨ã®å¯¾å¿ã«ã¯
+ãããã intpri_tableï¼åã³ iipm_mask_table ã¨ããé
+åãä½¿ç¨ããï¼
+ãããã¯ CFG_INT ã®è¨­å®å¤ããã¨ã«ã³ã³ãã£ã®ã¥ã¬ã¼ã¿ã kernel_cfg.c ã«åºåããï¼
+
+
+CPUä¾å¤ã®ä¾å¤çªå·ã«ã¤ãã¦ã¯ï¼ã³ã¢ä¾å­é¨ã¨åæ§ã®ããçç¥ããï¼
+
+
+âä¾å¤/å²è¾¼ã¿ã®åä»
+
+ã»ä¾å¤/å²è¾¼ã¿ãåä»ããã¨ï¼åä»ãæã«ã¢ã¯ãã£ããªã¹ã¿ãã¯ä¸ã«ä»¥ä¸ã®ã³
+  ã³ãã­ã¹ããä¿å­ããï¼
+
+   ---------------
+  |   GICC_PMR     |  <- new SP
+   ----------------
+  | å²è¾¼ã¿/ä¾å¤çªå·|
+   ----------------
+  |    ESR_ELx     |
+   ----------------
+  |    ELR_ELx     |
+   ----------------
+  |   SPSR_ELx     |
+   ----------------
+  |      X30       |
+   ----------------
+  |      X29       |
+   ----------------
+  |      ï¼        |
+  |      ï¼        |
+   ----------------
+  |      X1        |
+   ----------------
+  |      X0        |
+   ----------------
+  |                | <- old SP
+
+
+å²è¾¼ã¿/ä¾å¤çºçæã®ä¸»ãªã·ã¼ã±ã³ã¹ã¯æ¬¡ã®ããã«ãªãï¼é·ç§»å
+ã®ä¾å¤ã¬ãã«ãELxã¨è¡¨ç¾ããï¼
+
+ï¼ãã¼ãã¦ã§ã¢ã®å¦çï¼
+  ã»PSTATEãSPSR_ELxã«ä¿å­ãã
+  ã»ãªã¿ã¼ã³ã¢ãã¬ã¹ãELR_ELxã«ä¿å­ãã
+  ã»PSTATE.{D,A,I,F}ã1ã«ã»ãããã
+  ã»åæä¾å¤ããã³SErrorå²è¾¼ã¿ã®ã¨ãï¼ä¾å¤è¦å æ
+å ±ãESR_ELxã«ä¿å­ãã
+  ã»ã¹ã¿ãã¯ãã¤ã³ã¿ãSP_ELxã«åãæ¿ãã
+  ã»ï¼CPUä¾å¤ã®å ´åï¼ä¾å¤çªå·ãx22ã«æ ¼ç´
+  ã»ELxã¸é·ç§»ãã
+
+ï¼ã½ããã¦ã§ã¢ã§ã®å¦çï¼
+  ã»(çºçæã«SP_EL0ãä½¿ç¨ãã¦ããå ´å)ã¹ã¿ãã¯ãå²è¾¼ã¿çºçå(SP_EL0)ã«æ»ã
+  ã»æ±ç¨ã¬ã¸ã¹ã¿(X0-X30)ãã¹ã¿ãã¯ã«ä¿å­
+  ã»SPSR_ELx, ESR_ELx, ELR_ELxãã¹ã¿ãã¯ã«ä¿å­
+  ã»(å²è¾¼ã¿)ãã³ãã£ã³ã°ã¬ã¸ã¹ã¿ããå²è¾¼ã¿çªå·ãåå¾
+    (CPUä¾å¤)ä¾å¤çªå·ãx22ããåå¾
+  ã»å²è¾¼ã¿çªå·ï¼ä¾å¤çªå·ãã¹ã¿ãã¯ã«ä¿å­
+  ã»å²è¾¼ã¿çºçåã®å²è¾¼ã¿åªå
+åº¦ãã¹ã¯ãã¹ã¿ãã¯ã«ä¿å­
+  ã»åãä»ããå²è¾¼ã¿ã®å²è¾¼ã¿åªå
+åº¦ãå¤æ° current_intpri ã«ã»ãã
+  ã»(å²è¾¼ã¿ã®å ´å)å²è¾¼ã¿åªå
+åº¦ã®å¤ãå
+ã«ï¼å²è¾¼ã¿ããã¹ã¯ãã
+  ã»å²è¾¼ã¿/ä¾å¤ãã¹ãã«ã¦ã³ã¿ã®ã¤ã³ã¯ãªã¡ã³ã
+  ã»(å²è¾¼ã¿ã®å ´å)CPUã­ãã¯è§£é¤
+    (ã«ã¼ãã«ç®¡çã®CPUä¾å¤ã®å ´å)ä¾å¤çºçåã®PSTATEç¶æ
+ã«è¨­å®
+  ã»ãã³ãã©ã®é
+åããã¢ãã¬ã¹ãèª­ã¿è¾¼ã¿ãã³ãã©ãå®è¡ãã
+
+âä¾å¤/å²è¾¼ã¿ããã®ãªã¿ã¼ã³
+
+ï¼ã½ããã¦ã§ã¢ã§ã®å¦çï¼
+  ã»CPUã­ãã¯ç¶æ
+ã¸ç§»è¡
+  ã»å²è¾¼ã¿/ä¾å¤ãã¹ãã«ã¦ã³ã¿ã®ãã¯ãªã¡ã³ã
+  ã»(å²è¾¼ã¿ã®å ´å)å²è¾¼ã¿çºçåã®åªå
+åº¦ãã¹ã¯ãæ»ãï¼åªå
+åº¦ã«å¿ãã¦å²è¾¼ã¿ã®ãã¹ã¯ãè§£é¤ãã
+    (CPUä¾å¤ã®å ´å)CPUç®¡çå¤ã®ä¾å¤ã®å ´åï¼ä¾å¤çºçå
+ã¸ãªã¿ã¼ã³ãã
+  ã»æ»ãå
+ã®ã³ã³ãã­ã¹ããã·ã¹ãã ç¶æ
+ã«å¿ãã¦å²è¾¼ã¿/ä¾å¤çºçå
+ã¸ãªã¿ã¼ã³
+    ã¾ãã¯é
+å»¶ãã£ã¹ããããå®è¡ãã
+  ã»ELR_ELxã«æ»ãå
+ã¢ãã¬ã¹ï¼SPSR_ELxã«ãã­ã»ããµç¶æ
+ããããã
+    ã»ããããã¦ããç¶æ
+ã§eretå½ä»¤ãå®è¡ãï¼å²è¾¼ã¿/ä¾å¤ãããªã¿ã¼ã³
+
+
+â OSã®å®è£
+
+
+1.ãããä¾å­é¨åç§°: bcm283x
+
+ç¾ç¶ã§ã¯ Raspberry Pi3B ã«æ­è¼ãããBCM2837ã®ã¿ãµãã¼ããããï¼
+Raspberry Pi ã«æ­è¼ããããã­ã»ããµBCM283x (x=5,6,7)ã¯å¨è¾ºåè·¯ã«ã¤ãã¦
+å
+±éããé¨åãå¤ãï¼ã¾ã¨ãã¦æ±ããã¨ã«ããããä¾å­é¨åç§°ã bcm283x ã¨ãã
+
+
+2. å¤é¨åªå
+åº¦ã¨å
+é¨åªå
+åº¦
+
+å¤é¨åªå
+åº¦ã¨ã¯APIã§æå®ããå²è¾¼ã¿åªå
+åº¦(PRIå)ã®ãã¨ã§ããï¼å¤ãå°ãã
+ã»ã©åªå
+åº¦ãé«ãï¼å²è¾¼ã¿ãã³ãã©ã«ã¯ï¼-1ããé£ç¶ããè² ã®å¤ãè¨­å®å¯è½ã§
+ããï¼å
+é¨åªå
+åº¦ã¯å¤é¨åªå
+åº¦ã®ç¬¦å·ãåè»¢ããå¤ã¨ããï¼
+å¤é¨åªå
+åº¦ã¨å
+é¨åªå
+åº¦ã®å¤æã¯ä»¥ä¸ã®ãã¯ã­ã§è¡¨ç¾ãããï¼
+
+/* å¤é¨è¡¨ç¾ã¸ã®å¤æ */
+#define EXT_IPM(pri) (-pri)
+
+/* å
+é¨è¡¨ç¾ã¸ã®å¤æ */
+#define INT_IPM(ipm) (-ipm)
+
+
+3. ã«ã¼ãã«ç®¡çå
+ã®æé«åªå
+åº¦(CPUã­ãã¯ç¶æ
+ã§ã®åªå
+åº¦ãã¹ã¯)
+
+CPUã­ãã¯ç¶æ
+ã®å®è£
+ã«åªå
+åº¦ã¯ç¨ãã¦ããªãï¼
+ã¾ãåªå
+åº¦å¶å¾¡ã¯ã½ããã¦ã§ã¢ã§å®è£
+ãã¦ããããï¼
+ã«ã¼ãã«ç®¡çå
+ã®å²è¾¼ã¿ã®æé«åªå
+åº¦ã¯èªç±ã«è¨­å®å¯è½ã§ããï¼
+
+ãããä¾å­é¨ã§æ¢å®å¤ã¨ãã¦-15ã«å®ç¾©ãã¦ãããï¼å¿
+è¦ã«å¿ãã¦
+ã¿ã¼ã²ããæ¯ã«å¿
+è¦ãªå¤ãè¨­å®ãããã¨ãã§ããï¼
+
+
+ä»¥ä¸ï¼
Index: /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_kernel.h
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_kernel.h	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_kernel.h	(revision 384)
@@ -0,0 +1,91 @@
+/*
+ *  TOPPERS/SSP Kernel
+ *      Smallest Set Profile Kernel
+ *
+ *  Copyright (C) 2008 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ */
+
+/*
+ *    kernel.hã®ãããä¾å­é¨ï¼BCM2837ç¨ï¼
+ *
+ *  ãã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«ã¯ï¼target_kernel.hï¼ã¾ãã¯ï¼ããããã¤ã³ã¯
+ *  ã«ã¼ãããããã¡ã¤ã«ï¼ã®ã¿ããã¤ã³ã¯ã«ã¼ããããï¼ä»ã®ãã¡ã¤ã«ãã
+ *  ç´æ¥ã¤ã³ã¯ã«ã¼ããã¦ã¯ãªããªãï¼
+ */
+
+#ifndef TOPPERS_CHIP_KERNEL_H
+#define TOPPERS_CHIP_KERNEL_H
+
+/*
+ *  ARM64ä¾å­å®ç¾©
+ */
+#include "arm64_gcc/common/core_kernel.h"
+
+/*
+ *  ãµãã¼ãããæ©è½ã®å®ç¾©
+ */
+// dis_int, ena_int å
+±ã«ãµãã¼ãããªã
+
+/*
+ *  å²è¾¼ã¿åªå
+åº¦ã®ç¯å²
+ */
+#ifndef TMIN_INTPRI
+    #define TMIN_INTPRI             (-15)           /* å²è¾¼ã¿åªå
+åº¦ã®æå°å¤ï¼æé«å¤ï¼*/
+#endif
+#ifndef TMAX_INTPRI
+    #define TMAX_INTPRI             (-1)            /* å²è¾¼ã¿åªå
+åº¦ã®æå¤§å¤ï¼æä½å¤ï¼ */
+#endif
+
+#endif /* TOPPERS_CHIP_KERNEL_H */
Index: /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_kernel.trb
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_kernel.trb	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_kernel.trb	(revision 384)
@@ -0,0 +1,191 @@
+# -*- coding: utf-8 -*-
+#
+#   TOPPERS/SSP Kernel
+#       Toyohashi Open Platform for Embedded Real-Time Systems/
+#       Advanced Standard Profile Kernel
+# 
+#   Copyright (C) 2015 by FUJI SOFT INCORPORATED, JAPAN
+#   Copyright (C) 2015,2016 by Embedded and Real-Time Systems Laboratory
+#               Graduate School of Information Science, Nagoya Univ., JAPAN
+#   Copyright (C) 2017, 2019 by Naoki Saito
+#              Nagoya Municipal Industrial Research Institute, JAPAN
+#
+# 
+#   ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+#   ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+#   å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+#   (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+#       æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+#       ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+#   (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+#       è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+#       ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#   (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+#       ã¨ï¼
+#     (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+#         ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#     (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+#         å ±åãããã¨ï¼
+#   (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+#       å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+#       ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+#       ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+#       å
+è²¬ãããã¨ï¼
+# 
+#   æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+#   ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+#   ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+#   ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+#   ã®è²¬ä»»ãè² ããªãï¼
+# 
+#   $Id$
+# 
+
+#
+#  ãã¹2ã®çæã¹ã¯ãªããã®ãããä¾å­é¨ï¼BCM2837ç¨ï¼
+#
+
+#
+#  æå¹ãªå²è¾¼ã¿çªå·ï¼å²è¾¼ã¿ãã³ãã©çªå·
+#
+$INTNO_VALID = [ *($TMIN_INTNO..$TMAX_INTNO) ]
+$INHNO_VALID = $INTNO_VALID
+
+#
+#  æå¹ãªCPUä¾å¤ãã³ãã©çªå·
+#
+$EXCNO_VALID = [ *(0..7) ]
+
+#
+#  ATT_ISRã§ä½¿ç¨ã§ããå²è¾¼ã¿çªå·ã¨ããã«å¯¾å¿ããå²è¾¼ã¿ãã³ãã©çªå·
+#
+$INTNO_ATTISR_VALID = $INTNO_VALID
+$INHNO_ATTISR_VALID = $INHNO_VALID
+
+#
+#  DEF_INT/DEF_EXCã§ä½¿ç¨ã§ããå²è¾¼ã¿ãã³ãã©çªå·ï¼CPUä¾å¤ãã³ãã©çªå·
+#
+$INHNO_DEFINH_VALID = $INHNO_VALID
+$EXCNO_DEFEXC_VALID = $EXCNO_VALID
+
+#
+#  CFG_INTã§ä½¿ç¨ã§ããå²è¾¼ã¿çªå·ã¨å²è¾¼ã¿åªå
+åº¦
+#
+$INTNO_CFGINT_VALID = [*($TMIN_INTNO..11),*(32..39),93, 107,109,110,*(112..119),121] 
+$INTPRI_CFGINT_VALID = Array($TMIN_INTPRI..$TMAX_INTPRI)
+
+#
+#  å²è¾¼ã¿å±æ§ä¸­ã®ã¿ã¼ã²ããä¾å­ã«ç¨ããããã
+#
+#$TARGET_INTATR =
+
+#
+# ã³ã¢ä¾å­é¨ã®ã¤ã³ã¯ã«ã¼ã
+#
+IncludeTrb("arm64_gcc/common/core_kernel.trb")
+
+$kernelCfgC.comment_header("Target-dependent Definitions (BCM2837)")
+
+#
+#  å²è¾¼ã¿è¦æ±ã©ã¤ã³åªå
+åº¦ãã¼ãã«
+#
+
+$kernelCfgC.comment_header("Interrupt Priority Table")
+
+$kernelCfgC.add("const PRI _kernel_intpri_table[] = {")
+$INTNO_VALID.each_with_index do |intnoVal, index|
+    $kernelCfgC.add(",") if index > 0
+    $kernelCfgC.append("\t/* 0x#{sprintf("%03x", intnoVal)} */ ")
+    if $cfgData[:CFG_INT].has_key?(intnoVal)
+      $kernelCfgC.append("INT_IPM(#{$cfgData[:CFG_INT][intnoVal][:intpri]})")
+    else
+      $kernelCfgC.append("0U")
+    end
+end
+
+$kernelCfgC.add
+$kernelCfgC.add2("};")
+
+#
+#  å²è¾¼ã¿åªå
+åº¦ãã¹ã¯ãã¼ãã«
+#
+
+$kernelCfgC.comment_header("Interrupt Priority Mask Table")
+
+$kernelCfgC.add("const uint32_t _kernel_iipm_mask_table[(TNUM_INTPRI + 1) * 4] = {")
+[0,*$INTPRI_CFGINT_VALID].sort{|a,b|b<=>a}.each_with_index do |ipriMask, index|
+    masks = [0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff]
+
+    $cfgData[:CFG_INT].each_key {|intno|
+        intpri = "#{sprintf("%d", $cfgData[:CFG_INT][intno][:intpri])}".to_i
+        if(intpri < ipriMask) then
+            masks[intno/32] &= ~(1 << intno%32)
+        end
+    }
+
+    $kernelCfgC.add if index > 0
+    (0..3).each {|i|
+        $kernelCfgC.append("#{sprintf("\t0x%08x,", masks[i])}")
+    }
+    $kernelCfgC.append("\t/* #{sprintf("intpri mask(%3d)", ipriMask)} */ ")
+end
+
+$kernelCfgC.add
+$kernelCfgC.add2("};")
+
+
+#
+#  å²è¾¼ã¿ãã³ãã©ãã¼ãã«
+#
+$kernelCfgC.comment_header("Interrupt Handler Table")
+
+$kernelCfgC.add("const INTHDR _kernel_inh_table[] = {")
+$INHNO_VALID.each_with_index do |inhnoVal, index|
+  $kernelCfgC.add(",") if index > 0
+  $kernelCfgC.append("\t/* 0x#{sprintf("%03x", inhnoVal)} */ ")
+  if $cfgData[:DEF_INH].has_key?(inhnoVal)
+    $kernelCfgC.append("(INTHDR)(#{$cfgData[:DEF_INH][inhnoVal][:inthdr]})")
+  else
+    $kernelCfgC.append("(INTHDR)(_kernel_default_int_handler)")
+  end
+end
+$kernelCfgC.add
+$kernelCfgC.add2("};")
+
+#
+#  CPUä¾å¤ãã³ãã©ãã¼ãã«
+#
+$kernelCfgC.comment_header("CPU Exception Handler Table")
+
+$kernelCfgC.add("const EXCHDR _kernel_exc_table[] = {")
+$EXCNO_VALID.each_with_index do |excnoVal, index|
+  $kernelCfgC.add(",") if index > 0
+  $kernelCfgC.append("\t/* #{excnoVal} */ ")
+  if $cfgData[:DEF_EXC].has_key?(excnoVal)
+    $kernelCfgC.append("(EXCHDR)(#{$cfgData[:DEF_EXC][excnoVal][:exchdr]})")
+  else
+    $kernelCfgC.append("(EXCHDR)(_kernel_default_exc_handler)")
+  end
+end
+$kernelCfgC.add
+$kernelCfgC.add2("};")
Index: /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_rename.def
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_rename.def	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_rename.def	(revision 384)
@@ -0,0 +1,20 @@
+# chip_config.c
+current_intpri
+chip_initialize
+chip_terminate
+x_config_int
+chip_mask_interrupt
+chip_unmask_interrupt
+
+# chip_support.S
+chip_exc_entry
+chip_int_entry
+chip_fiq_entry
+
+# kernel_cfg.c
+intpri_table
+iipm_mask_table
+inh_table
+exc_table
+
+INCLUDE "arm64_gcc/common/core"
Index: /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_rename.h
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_rename.h	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_rename.h	(revision 384)
@@ -0,0 +1,64 @@
+/* This file is generated from chip_rename.def by genrename. */
+
+#ifndef TOPPERS_CHIP_RENAME_H
+#define TOPPERS_CHIP_RENAME_H
+
+/*
+ *  chip_config.c
+ */
+#define current_intpri				_kernel_current_intpri
+#define chip_initialize				_kernel_chip_initialize
+#define chip_terminate				_kernel_chip_terminate
+#define x_config_int				_kernel_x_config_int
+#define chip_mask_interrupt			_kernel_chip_mask_interrupt
+#define chip_unmask_interrupt		_kernel_chip_unmask_interrupt
+
+/*
+ *  chip_support.S
+ */
+#define chip_exc_entry				_kernel_chip_exc_entry
+#define chip_int_entry				_kernel_chip_int_entry
+#define chip_fiq_entry				_kernel_chip_fiq_entry
+
+/*
+ *  kernel_cfg.c
+ */
+#define intpri_table				_kernel_intpri_table
+#define iipm_mask_table				_kernel_iipm_mask_table
+#define inh_table					_kernel_inh_table
+#define exc_table					_kernel_exc_table
+
+
+#ifdef TOPPERS_LABEL_ASM
+
+/*
+ *  chip_config.c
+ */
+#define _current_intpri				__kernel_current_intpri
+#define _chip_initialize			__kernel_chip_initialize
+#define _chip_terminate				__kernel_chip_terminate
+#define _x_config_int				__kernel_x_config_int
+#define _chip_mask_interrupt		__kernel_chip_mask_interrupt
+#define _chip_unmask_interrupt		__kernel_chip_unmask_interrupt
+
+/*
+ *  chip_support.S
+ */
+#define _chip_exc_entry				__kernel_chip_exc_entry
+#define _chip_int_entry				__kernel_chip_int_entry
+#define _chip_fiq_entry				__kernel_chip_fiq_entry
+
+/*
+ *  kernel_cfg.c
+ */
+#define _intpri_table				__kernel_intpri_table
+#define _iipm_mask_table			__kernel_iipm_mask_table
+#define _inh_table					__kernel_inh_table
+#define _exc_table					__kernel_exc_table
+
+
+#endif /* TOPPERS_LABEL_ASM */
+
+#include "arm64_gcc/common/core_rename.h"
+
+#endif /* TOPPERS_CHIP_RENAME_H */
Index: /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_serial.c
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_serial.c	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_serial.c	(revision 384)
@@ -0,0 +1,321 @@
+/*
+ *  TOPPERS/SSP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2007 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2012 by Meika Sugimoto
+ *  Copyright (C) 2015, 2019 by Naoki Saito
+ *              Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ */
+
+/*
+ * ã·ãªã¢ã«ãã©ã¤ã
+ */
+
+#include <sil.h>
+#include "target_serial.h"
+#include "target_syssvc.h"
+#include "pl011.h"
+#include "bcm2837.h"
+
+/*
+ * ã¬ã¸ã¹ã¿è¨­å®å¤
+ */
+#define PORT2SIOPID(x)  ((x) + 1)
+#define INDEX_PORT(x)   ((x) - 1)
+#define GET_SIOPCB(x)   (&siopcb_table[INDEX_PORT(x)])
+
+const SIOPINIB siopinib_table[TNUM_PORT] = {
+    {
+        RPI_UART0_BASE,             /* baseAddress */
+        RPI_UART_IBRD_115200,       /* ibrd */
+        RPI_UART_FBRD_115200,       /* fbrd */
+        UART_LCR_H_WLEN8,           /* lcr_h */
+    },
+};
+
+SIOPCB siopcb_table[TNUM_PORT];
+
+/*
+ *  éä¿¡ãããã¡ã«ç©ºãããããï¼
+ */
+Inline bool_t
+sio_putready(SIOPCB* siopcb)
+{
+    return((sil_rew_mem(UART_FR(siopcb->inib->baseAddress)) & UART_FR_TXFF) == 0U);
+}
+
+/*
+ *  åä¿¡ãããã¡ã«æå­ããããï¼
+ */
+Inline bool_t
+sio_getready(SIOPCB* siopcb)
+{
+    return((sil_rew_mem(UART_FR(siopcb->inib->baseAddress)) & UART_FR_RXFE) == 0U);
+}
+
+/*
+ *  åä¿¡ããæå­ã®ååºã
+ */
+Inline char
+sio_getchar(SIOPCB *siopcb)
+{
+    return((char) sil_rew_mem(UART_DR(siopcb->inib->baseAddress)));
+}
+
+/*
+ *  éä¿¡ããæå­ã®æ¸è¾¼ã¿
+ */
+Inline void
+sio_putchar(SIOPCB *siopcb, char c)
+{
+    sil_wrw_mem(UART_DR(siopcb->inib->baseAddress), (uint32_t) c);
+}
+
+/*
+ *  ã¿ã¼ã²ããã®ã·ãªã¢ã«åæå
+ */
+void target_low_output_init(ID siopid)
+{
+    SIOPINIB *inib;
+    volatile uint32_t  __attribute__((aligned(16))) mbox[36];
+
+    inib = &siopinib_table[INDEX_PORT(siopid)];
+
+    /*
+     *  disable UART
+     */
+    sil_wrw_mem(UART_CR(inib->baseAddress), 0U);
+
+    // ã¯ã­ãã¯ã®ã»ããã¢ãã
+    mbox[0] = 9*4;
+    mbox[1] = MBOX_REQUEST;
+    mbox[2] = MBOX_TAG_SETCLKRATE;
+    mbox[3] = 12;
+    mbox[4] = 8;
+    mbox[5] = 2;
+    mbox[6] = 4000000;     // 4MHz
+    mbox[7] = 0;
+    mbox[8] = MBOX_TAG_LAST;
+    mbox_call(MBOX_CH_PROP, mbox);
+
+    /*
+     *  clear error flag
+     */
+    sil_wrw_mem(UART_ECR(inib->baseAddress), 0U);
+
+    /*
+     *  clear interrupt status
+     */
+    sil_wrw_mem(UART_ICR(inib->baseAddress), 0U);
+    sil_wrw_mem(UART_RIS(inib->baseAddress), 0U);
+    sil_wrw_mem(UART_MIS(inib->baseAddress), 0U);
+
+    /*
+     *  configure UART
+     */
+    sil_wrw_mem(UART_IBRD(inib->baseAddress), inib->ibrd);
+    sil_wrw_mem(UART_FBRD(inib->baseAddress), inib->fbrd);
+    sil_wrw_mem(UART_LCR_H(inib->baseAddress), inib->lcr_h);
+
+    /*
+     *  enable UART
+     */
+    sil_wrw_mem(UART_CR(inib->baseAddress),
+                    UART_CR_UARTEN|UART_CR_TXE|UART_CR_RXE);
+}
+
+/*
+ *  SIOåæå
+ */
+void sio_initialize(intptr_t exinf)
+{
+    int i;
+
+    for (i = 0; i < TNUM_PORT; i++) {
+        siopcb_table[i].inib = &(siopinib_table[i]);
+        siopcb_table[i].exinf = 0;
+    }
+}
+
+/*
+ *  ã·ãªã¢ã«ãªã¼ãã³
+ */
+SIOPCB *sio_opn_por(ID siopid, intptr_t exinf)
+{
+    SIOPCB* siopcb;
+
+    if (siopid > TNUM_PORT) {
+        return NULL;
+    }
+
+    siopcb = GET_SIOPCB(siopid);
+    siopcb->exinf = exinf;
+
+    target_low_output_init(siopid);
+
+    // åä¿¡ã³ã¼ã«ããã¯è¨±å¯
+    sio_ena_cbr(siopcb, SIO_RDY_RCV);
+
+    return siopcb;
+}
+
+/*
+ *  ã·ãªã¢ã«ã¯ã­ã¼ãº
+ */
+void sio_cls_por(SIOPCB *siopcb)
+{
+    /*
+     *  UARTããã£ã¹ã¨ã¼ãã«
+     */
+    sil_wrw_mem(UART_CR(siopcb->inib->baseAddress), 0U);
+}
+
+/*
+ *  å²è¾¼ã¿ãã³ãã©
+ */
+#include "target_syssvc.h"
+void sio_isr(intptr_t exinf)
+{
+    SIOPCB* siopcb = GET_SIOPCB(exinf);
+
+    if (sio_getready(siopcb)) {
+        /*
+         *  åä¿¡éç¥ã³ã¼ã«ããã¯ã«ã¼ãã³ãå¼ã³åºãï¼
+         */
+        sio_irdy_rcv(siopcb->exinf);
+    }
+    if (sio_putready(siopcb)) {
+        /*
+         *  éä¿¡å¯è½ã³ã¼ã«ããã¯ã«ã¼ãã³ãå¼ã³åºãï¼
+         */
+        sio_irdy_snd(siopcb->exinf);
+    }
+}
+
+/*
+ *  1æå­éä¿¡
+ */
+bool_t sio_snd_chr(SIOPCB *siopcb, char c)
+{
+    if (sio_putready(siopcb)){
+        sio_putchar(siopcb, c);
+        return(true);
+    }
+    return(false);
+}
+
+/*
+ *  1æå­åä¿¡
+ */
+int_t sio_rcv_chr(SIOPCB *siopcb)
+{
+    if (sio_getready(siopcb)) {
+        return((int_t)(uint8_t) sio_getchar(siopcb));
+    }
+    return(-1);
+}
+
+/*
+ *  ã³ã¼ã«ããã¯ã®è¨±å¯
+ */
+void sio_ena_cbr(SIOPCB *siopcb, uint_t cbrtn)
+{
+    SIOPINIB        *inib;
+    uint32_t        reg;
+
+    inib = siopcb->inib;
+    reg = sil_rew_mem(UART_IMSC(inib->baseAddress));
+
+    switch (cbrtn) {
+    case SIO_RDY_SND:
+        reg |= UART_IMSC_TXIM;
+        break;
+    case SIO_RDY_RCV:
+        reg |= UART_IMSC_RXIM;
+        break;
+    }
+    sil_wrw_mem(UART_IMSC(inib->baseAddress), reg);
+}
+
+/*
+ *  ã³ã¼ã«ããã¯ã®ç¦æ­¢
+ */
+void sio_dis_cbr(SIOPCB *siopcb, uint_t cbrtn)
+{
+    SIOPINIB    *inib;
+    uint32_t    reg;
+
+    inib = siopcb -> inib;
+    reg = sil_rew_mem(UART_IMSC(inib->baseAddress));
+
+    switch (cbrtn) {
+    case SIO_RDY_SND:
+        reg &= ~UART_IMSC_TXIM;
+        break;
+    case SIO_RDY_RCV:
+        reg &= ~UART_IMSC_RXIM;
+        break;
+    }
+    sil_wrw_mem(UART_IMSC(inib->baseAddress), reg);
+}
+
+/*
+ *  1æå­åºåï¼ãã¼ãªã³ã°ã§ã®åºåï¼
+ */
+void sio_pol_snd_chr(char c, ID siopid)
+{
+    SIOPCB *siopcb = GET_SIOPCB(siopid);
+
+    if(c == '\n'){
+        while(!sio_snd_chr(siopcb, '\r'));
+    }
+    while(!sio_snd_chr(siopcb, c));
+}
Index: /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_serial.cfg
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_serial.cfg	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_serial.cfg	(revision 384)
@@ -0,0 +1,7 @@
+/*
+ *  SIOãã©ã¤ãï¼CQ-FRK-FM3ç¨ï¼ã®ã³ã³ãã£ã°ã¬ã¼ã·ã§ã³ãã¡ã¤ã«
+ */
+
+ATT_INI({ TA_NULL, 0, sio_initialize });
+ATT_ISR({ TA_NULL, SIO_PORTID, INTNO_SIO, sio_isr, 1 });
+CFG_INT(INTNO_SIO, { TA_ENAINT|INTATR_SIO, INTPRI_SIO });
Index: /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_serial.h
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_serial.h	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_serial.h	(revision 384)
@@ -0,0 +1,164 @@
+/*
+ *  TOPPERS/SSP Kernel
+ *      Smallest Set Profile Kernel
+ *
+ *  Copyright (C) 2007 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2015,2018,2019 by Naoki Saito
+ *              Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ */
+
+/*
+ *  ã·ãªã¢ã«I/Oããã¤ã¹(SIO)ãã©ã¤ã
+ */
+
+#ifndef TOPPERS_CHIP_SERIAL_H
+#define TOPPERS_CHIP_SERIAL_H
+
+/*
+ *  SIOã®å²è¾¼ã¿è¨­å®
+ */
+#define INTNO_SIO     TINTNO_UART         // å²è¾¼ã¿çªå·
+
+#ifndef INTATR_SIO
+    #define INTATR_SIO    TA_NULL         // å²è¾¼ã¿å±æ§
+#endif
+
+#ifndef INTPRI_SIO
+    #define INTPRI_SIO    (-2)            // å²è¾¼ã¿åªå
+åº¦
+#endif
+
+/*
+ *  ã³ã¼ã«ããã¯ã«ã¼ãã³ã®è­å¥çªå·
+ */
+#define SIO_RDY_SND    1U        /* éä¿¡å¯è½ã³ã¼ã«ããã¯ */
+#define SIO_RDY_RCV    2U        /* åä¿¡éç¥ã³ã¼ã«ããã¯ */
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ *  ã·ãªã¢ã«ãã¼ãã®åæåãã­ãã¯
+ */
+typedef const struct tag_SIOPINIB {
+    uintptr_t      baseAddress;
+    uint8_t        ibrd;
+    uint8_t        fbrd;
+    uint8_t        lcr_h;
+}  SIOPINIB;
+
+/*
+ *  ã·ãªã¢ã«ãã¼ãã®ç®¡çãã­ãã¯
+ */
+typedef struct sio_port_control_block {
+    SIOPINIB *inib;
+    intptr_t exinf;
+} SIOPCB;
+
+/*
+ *  SIOåæå
+ */
+extern void sio_initialize(intptr_t exinf);
+
+/*
+ *  ã·ãªã¢ã«ãªã¼ãã³
+ */
+extern SIOPCB *sio_opn_por(ID siopid, intptr_t exinf);
+
+/*
+ *  ã·ãªã¢ã«ã¯ã­ã¼ãº
+ */
+extern void sio_cls_por(SIOPCB *p_siopcb);
+
+/*
+ *  å²è¾¼ã¿ãã³ãã©
+ */
+extern void sio_isr(intptr_t exinf);
+
+/*
+ *  1æå­éä¿¡
+ */
+extern bool_t sio_snd_chr(SIOPCB *siopcb, char c);
+
+/*
+ *  1æå­åä¿¡
+ */
+extern int_t sio_rcv_chr(SIOPCB *siopcb);
+
+/*
+ *  ã³ã¼ã«ããã¯ã®è¨±å¯
+ */
+extern void sio_ena_cbr(SIOPCB *siopcb, uint_t cbrtn);
+
+/*
+ *  ã³ã¼ã«ããã¯ã®ç¦æ­¢
+ */
+extern void sio_dis_cbr(SIOPCB *siopcb, uint_t cbrtn);
+
+/*
+ *  éä¿¡å¯è½ã³ã¼ã«ããã¯
+ */
+extern void sio_irdy_snd(intptr_t exinf);
+
+/*
+ *  åä¿¡éç¥ã³ã¼ã«ããã¯
+ */
+extern void sio_irdy_rcv(intptr_t exinf);
+
+/*
+ *  1æå­éä¿¡ï¼ãã¼ãªã³ã°ã§ã®åºåï¼
+ */
+extern void sio_pol_snd_chr(char c, ID siopid);
+
+/*
+ *  ä½ã¬ãã«åºååæå
+ */
+extern void target_low_output_init(ID siopid);
+
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_TARGET_SERIAL_H */
Index: /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_sil.h
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_sil.h	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_sil.h	(revision 384)
@@ -0,0 +1,70 @@
+/*
+ *  TOPPERS Software
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *
+ *  Copyright (C) 2008 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2018,2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  @(#) $Id$
+ */
+
+/*
+ *   sil.hã®ãããä¾å­é¨ï¼BCM2837ç¨ï¼
+ */
+
+#ifndef TOPPERS_CHIP_SIL_H
+#define TOPPERS_CHIP_SIL_H
+
+/*
+ *  ARMv8-A ã®å
+±éå®ç¾©
+ */
+#include "arm64_gcc/common/core_sil.h"
+
+#endif /* TOPPERS_CHIP_SIL_H */
Index: /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_stddef.h
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_stddef.h	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_stddef.h	(revision 384)
@@ -0,0 +1,78 @@
+/*
+ *  TOPPERS Software
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *
+ *  Copyright (C) 2008 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2018,2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  @(#) $Id$
+ */
+
+/*
+ *  t_stddef.hã®ãããä¾å­é¨ï¼BCM2837ç¨ï¼
+ *
+ *  ãã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«ã¯ï¼target_stddef.hï¼ã¾ãã¯ï¼ããããã¤ã³ã¯
+ *  ã«ã¼ãããããã¡ã¤ã«ï¼ã®ã¿ããã¤ã³ã¯ã«ã¼ããããï¼ä»ã®ãã¡ã¤ã«ãã
+ *  ç´æ¥ã¤ã³ã¯ã«ã¼ããã¦ã¯ãªããªãï¼
+ */
+
+#ifndef TOPPERS_CHIP_STDDEF_H
+#define TOPPERS_CHIP_STDDEF_H
+
+/*
+ *  ã¿ã¼ã²ãããè­å¥ããããã®ãã¯ã­ã®å®ç¾©
+ */
+#define TOPPERS_BCM283X           /* ãããç¥ç§° */
+
+/*
+ *  ã³ã¢ä¾å­é¨å®ç¾©
+ */
+#include "arm64_gcc/common/core_stddef.h"
+
+#endif /* TOPPERS_CHIP_STDDEF_H */
Index: /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_support.S
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_support.S	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_support.S	(revision 384)
@@ -0,0 +1,302 @@
+/*
+ *  TOPPERS/SSP Kernel
+ *      Smallest Set Profile Kernel
+ *
+ *  Copyright (C) 2018,2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ */
+
+/*
+ *  ãããä¾å­ã¢ã¸ã¥ã¼ã« ã¢ã»ã³ããªè¨èªé¨(BCM2837)
+ */
+
+#define TOPPERS_MACRO_ONLY
+#define UINT_C(val)	(val)		/* uint_tåã®å®æ°ãä½ããã¯ã­ */
+#define ULONG_C(val)	(val)		/* ulong_tåã®å®æ°ãä½ããã¯ã­ */
+#define UINT64_C(val)   (val)           /* uint64_tåã®å®æ°ãä½ããã¯ã­ */
+#define CAST(type, val)	(val)		/* åã­ã£ã¹ããè¡ããã¯ã­ */
+
+#include "kernel_impl.h"
+
+/*
+ *  ä¾å¤å
+¥å£ã®æä½
+ *    x22: excno(0..7)
+ */
+    .text
+    .align 2
+    .global chip_exc_entry
+chip_exc_entry:
+    mov   x0, sp
+    str   x22, [x0, #8]      // save excno in stack
+
+    adrp  x1, current_intpri // save int priority in stack
+    add   x1, x1, :lo12:current_intpri
+    ldr   w2, [x1]
+    str   w2, [x0]
+
+    mov   x1, x22            // arg: excno
+    bl    call_exc_handler
+
+    // ä¾å¤çºçç´åã®Iãã©ã°ã¾ãã¯Fãã©ã°ã1ãªãã«ã¼ãã«ç®¡çå¤ã®CPUä¾å¤ã¨ã¿ãªã
+    ldr   x3, [x0, #32]      // SPSR --> x1
+    tst   x3, #(3 << 6)
+    b.ne  ret_exc
+
+    // ã«ã¼ãã«ç®¡çã®CPUä¾å¤ã®å ´åã¯å²è¾¼ã¿ã®åºå£å¦çã¨å
+±é
+    msr   daifclr, #AARCH64_DAIF_FIQ
+    b     ret_int
+
+/*
+ *  FIQã®å
+¥å£å¦ç
+ */
+    .text
+    .align 2
+    .global chip_fiq_entry
+chip_fiq_entry:
+    ldr   x30, =ret_fiq      // return to ret_fiq
+    b     call_fiq_handler
+
+/*
+ *  å²è¾¼ã¿å
+¥å£ã®æä½
+ */
+    .text
+    .align 2
+    .global chip_int_entry
+chip_int_entry:
+    mov    x0,    sp
+    /*
+     *  å²è¾¼ã¿è¦å ã®ç¹å®ã¨ä¿å­
+     */
+find_int_src_core: // find a interrupt source from core(core 0)
+    movz  x1,#:abs_g1_nc:CORE0_IRQ_SRC
+    movk  x1,#:abs_g0_nc:CORE0_IRQ_SRC
+    ldr   w2, [x1]
+    mov   x9, xzr
+1:
+    tst   w2, #0x1
+    b.ne  2f
+    lsr   w2, w2, #1
+    add   w9, w9, #1
+    cmp   w9, #32
+    b.ne  1b
+2:
+    cmp   w9, #8    // pending interrupt is GPU interrupt
+    b.eq  find_int_src_basic
+    cmp   w9, #32   // pending interrupt is not found
+    b.eq  find_int_src_basic
+    b     find_int_src_exit
+
+find_int_src_basic: // basic pending register
+    mov   w9, #32
+    movz  x1,#:abs_g1_nc:IRQ_PEND_B
+    movk  x1,#:abs_g0_nc:IRQ_PEND_B
+    ldr   w2, [x1]
+1:
+    tst   w2, #0x1
+    b.ne  2f
+    lsr   w2, w2, #1
+    add   w9, w9, #1
+    cmp   w9, #64
+    b.ne  1b
+2:
+    cmp   w9, #(32+8) // GPU pending register 1
+    b.eq  find_int_src_gpu1
+    cmp   w9, #(32+9) // GPU pending register 2
+    b.eq  find_int_src_gpu2
+    cmp   w9, #(32+10)  // GPU irq 7
+    b.eq  gpu_irq_7
+    cmp   w9, #(32+11)  // GPU irq 9
+    b.eq  gpu_irq_9
+    cmp   w9, #(32+12)  // GPU irq 10
+    b.eq  gpu_irq_10
+    cmp   w9, #(32+13)  // GPU irq 18
+    b.eq  gpu_irq_18
+    cmp   w9, #(32+14)  // GPU irq 19
+    b.eq  gpu_irq_19
+    cmp   w9, #(32+15)  // GPU irq 53
+    b.eq  gpu_irq_53
+    cmp   w9, #(32+16)  // GPU irq 54
+    b.eq  gpu_irq_54
+    cmp   w9, #(32+17)  // GPU irq 55
+    b.eq  gpu_irq_55
+    cmp   w9, #(32+18)  // GPU irq 56
+    b.eq  gpu_irq_56
+    cmp   w9, #(32+19)  // GPU irq 57
+    b.eq  gpu_irq_57
+    cmp   w9, #(32+20)  // GPU irq 62
+    b.eq  gpu_irq_62
+    cmp   w9, #64     // pending interrupt is not found
+    b.eq  find_int_src_gpu1
+
+    b     find_int_src_exit // others
+
+gpu_irq_7:
+    mov  w9, #(64+7)
+    b    find_int_src_exit
+gpu_irq_9:
+    mov  w9, #(64+9)
+    b    find_int_src_exit
+gpu_irq_10:
+    mov  w9, #(64+10)
+    b    find_int_src_exit
+gpu_irq_18:
+    mov  w9, #(64+18)
+    b    find_int_src_exit
+gpu_irq_19:
+    mov  w9, #(64+19)
+    b    find_int_src_exit
+gpu_irq_53:
+    mov  w9, #(64+53)
+    b    find_int_src_exit
+gpu_irq_54:
+    mov  w9, #(64+54)
+    b    find_int_src_exit
+gpu_irq_55:
+    mov  w9, #(64+55)
+    b    find_int_src_exit
+gpu_irq_56:
+    mov  w9, #(64+56)
+    b    find_int_src_exit
+gpu_irq_57:
+    mov  w9, #(64+57)
+    b    find_int_src_exit
+gpu_irq_62:
+    mov  w9, #(64+62)
+    b    find_int_src_exit
+
+find_int_src_gpu1:    // GPU pending register 1
+    mov   w9, #64
+    movz  x1,#:abs_g1_nc:IRQ_PEND_1
+    movk  x1,#:abs_g0_nc:IRQ_PEND_1
+    ldr   w2, [x1]
+1:
+    tst   w2, #0x1
+    b.ne  2f
+    lsr   w2, w2, #1
+    add   w9, w9, #1
+    cmp   w9, #96
+    b.ne  1b
+2:
+    cmp   w9, #96    // pending interrupt is not found
+    b.eq  find_int_src_gpu2
+    b     find_int_src_exit
+
+find_int_src_gpu2:   // GPU pending register 2
+    mov   w9, #96
+    movz  x1,#:abs_g1_nc:IRQ_PEND_2
+    movk  x1,#:abs_g0_nc:IRQ_PEND_2
+    ldr   w2, [x1]
+1:
+    tst   w2, #0x1
+    b.ne  find_int_src_exit
+    lsr   w2, w2, #1
+    add   w9, w9, #1
+    cmp   w9, #128   // pending interrupt is not found (and interrupt source is unknown)
+    b.ne  1b
+
+find_int_src_exit:
+    cmp   w9, #128
+    b.eq  ret_int
+    str   w9, [x0, #8]    // save intno to (sp+8)
+
+    /*
+     *  å²è¾¼ã¿çºçç´åã®å²è¾¼ã¿åªå
+åº¦ï¼å
+é¨è¡¨ç¾ï¼ãä¿å­
+     */
+    adrp  x1, current_intpri
+    add   x1, x1, :lo12:current_intpri
+    ldr   w2, [x1]
+    str   w2, [x0]
+
+    /*
+     *  å²è¾¼ã¿è¦å ã®åªå
+åº¦ãåå¾
+     */
+    adrp  x3, _kernel_intpri_table
+    add   x3, x3, #:lo12:_kernel_intpri_table
+    ldr   w4, [x3, x9, lsl #2]
+
+    // çºçããå²è¾¼ã¿ã®åªå
+åº¦ããã¨ã«å²è¾¼ã¿ããã¹ã¯
+    mov   w0, w4        //  arg: intpri
+    bl    chip_mask_interrupt
+
+    // D,A,F ãã©ã°ãã¯ãªã¢ãã¦ãã(CPUã­ãã¯ç¸å½ã«ãã)
+    msr   daifclr, #(AARCH64_DAIF_DBG | AARCH64_DAIF_SERR | AARCH64_DAIF_FIQ)
+
+    // ãã³ãã©å¼ã³åºã
+    mov   x0, sp
+    ldr   w9, [x0, #8]
+    mov   w0, w9             // arg: intno
+    bl    call_int_handler
+    /* ãã®ã¾ã¾ chip_ret_int ã¸ */
+
+/*
+ *  å²è¾¼ã¿åºå£ã®GICæä½
+ */
+chip_ret_int:
+    // å²è¾¼ã¿çºçåã®åªå
+åº¦ã«æ»ã
+    mov   x0, sp
+    adrp  x1, current_intpri
+    add   x1, x1, :lo12:current_intpri
+    ldr   w2, [x0]     // previous int priority
+    str   w2, [x1]
+
+    // åªå
+åº¦ãå
+ã«å²è¾¼ã¿ã®ãã¹ã¯ãæ»ã
+    mov   w0, w2
+    bl    chip_unmask_interrupt
+
+    b     ret_int
Index: /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_sym.def
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_sym.def	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_sym.def	(revision 384)
@@ -0,0 +1,2 @@
+TMAX_INTNO
+TMIN_INTNO
Index: /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_test.h
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_test.h	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_test.h	(revision 384)
@@ -0,0 +1,70 @@
+/*
+ *  TOPPERS/SSP Kernel
+ *      Smallest Set Profile Kernel
+ *
+ *  Copyright (C) 2008 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2018,2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  @(#) $Id$
+ */
+
+/*
+ *  ãã¹ããã­ã°ã©ã ã®ãããä¾å­å®ç¾©ï¼BCM2837ç¨ï¼
+ */
+
+#ifndef TOPPERS_CHIP_TEST_H
+#define TOPPERS_CHIP_TEST_H
+
+/*
+ *  ã³ã¢å
+±éå®ç¾©
+ */
+#include "arm64_gcc/common/core_test.h"
+
+#endif /* TOPPERS_CHIP_TEST_H */
Index: /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_timer.cfg
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_timer.cfg	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_timer.cfg	(revision 384)
@@ -0,0 +1,5 @@
+/*
+ *    ã¿ã¤ããã©ã¤ãã®ã³ã³ãã£ã®ã¥ã¬ã¼ã·ã§ã³ãã¡ã¤ã«
+ */
+INCLUDE("arm64_gcc/common/core_timer.cfg");
+
Index: /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_timer.h
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_timer.h	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_timer.h	(revision 384)
@@ -0,0 +1,69 @@
+/*
+ *  TOPPERS/SSP Kernel
+ *      Smallest Set Profile Kernel
+ *
+ *  Copyright (C) 2013-2015 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2018,2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  $Id$
+ */
+
+/*
+ *  ã¿ã¤ããã©ã¤ãï¼BCM283Xç¨ï¼
+ */
+
+#ifndef TOPPERS_CHIP_TIMER_H
+#define TOPPERS_CHIP_TIMER_H
+
+/*
+ *  ARMv8-A ä¾å­å®ç¾©
+ */
+#include "arm64_gcc/common/core_timer.h"
+
+#endif /* TOPPERS_CHIP_TIMER_H */
Index: /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_unrename.h
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_unrename.h	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_unrename.h	(revision 384)
@@ -0,0 +1,65 @@
+/* This file is generated from chip_rename.def by genrename. */
+
+/* This file is included only when chip_rename.h has been included. */
+#ifdef TOPPERS_CHIP_RENAME_H
+#undef TOPPERS_CHIP_RENAME_H
+
+/*
+ *  chip_config.c
+ */
+#undef current_intpri
+#undef chip_initialize
+#undef chip_terminate
+#undef x_config_int
+#undef chip_mask_interrupt
+#undef chip_unmask_interrupt
+
+/*
+ *  chip_support.S
+ */
+#undef chip_exc_entry
+#undef chip_int_entry
+#undef chip_fiq_entry
+
+/*
+ *  kernel_cfg.c
+ */
+#undef intpri_table
+#undef iipm_mask_table
+#undef inh_table
+#undef exc_table
+
+
+#ifdef TOPPERS_LABEL_ASM
+
+/*
+ *  chip_config.c
+ */
+#undef _current_intpri
+#undef _chip_initialize
+#undef _chip_terminate
+#undef _x_config_int
+#undef _chip_mask_interrupt
+#undef _chip_unmask_interrupt
+
+/*
+ *  chip_support.S
+ */
+#undef _chip_exc_entry
+#undef _chip_int_entry
+#undef _chip_fiq_entry
+
+/*
+ *  kernel_cfg.c
+ */
+#undef _intpri_table
+#undef _iipm_mask_table
+#undef _inh_table
+#undef _exc_table
+
+
+#endif /* TOPPERS_LABEL_ASM */
+
+#include "arm64_gcc/common/core_unrename.h"
+
+#endif /* TOPPERS_CHIP_RENAME_H */
Index: /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_user.txt
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_user.txt	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/chip_user.txt	(revision 384)
@@ -0,0 +1,170 @@
+=====================================================================
+                         BCM283xãããä¾å­é¨
+                                  Last Modified: '19/04/16
+=====================================================================
+
+
+(1) å¯¾å¿ãã¦ããã¿ã¼ã²ããã·ã¹ãã ã®ç¨®é¡ã»æ§æ
+
+bcm283xãããä¾å­é¨ã¯ï¼ä¸»ã« Raspberry Pi ã§ä½¿ç¨ããã Broadcomè£½ãããã
+ã¿ã¼ã²ããã¨ããï¼ç¾æç¹ã§ã¯ Raspberru Pi 3B ã«æ­è¼ãããBCM2837 ããµãã¼ãããï¼
+
+(2) ä½¿ç¨ããéçºç°å¢ã¨åä½æ¤è¨¼ããæ¡ä»¶ï¼ãã¼ã¸ã§ã³ï¼ãªãã·ã§ã³ç­ï¼
+
+ã«ã¼ãã«ã¯GCCãç¨ãã¦ã³ã³ãã¤ã«ããï¼åä½ç¢ºèªãããã¼ã¸ã§ã³ã¯åã¿ã¼ã²
+ããä¾å­é¨ã®ãã­ã¥ã¡ã³ãã«è¨è¼ããï¼
+
+(3) ã¿ã¼ã²ããå®ç¾©äºé 
+ã®è¦å®
+
+(3-1) å²è¾¼ã¿å¦çã«é¢ããè¦å®
+
+(3-1-1) æ¦è¦
+
+BCM283x ã¯ç¬èªã®å²è¾¼ã¿ã³ã³ãã­ã¼ã©ãæ­è¼ãï¼ä»¥ä¸ã®ç¹å¾´ãæã¤ï¼
+ã»å²è¾¼ã¿åªå
+ã¬ãã«ã¯ãµãã¼ãããªãï¼
+ã»å²è¾¼ã¿ã¯å
+¨ã¦ã¬ãã«ããªã¬ã§ããï¼ãããã£ã¦å²è¾¼ã¿è¦æ±ãã©ã°ã¯
+  å²è¾¼ã¿çºçå
+ã®ããã¤ã¹ãç´æ¥æä½ãã¦ã¯ãªã¢ããå¿
+è¦ãããï¼
+
+BCM283xä¾å­é¨ã§ã¯ï¼IRQ ãã«ã¼ãã«ç®¡çã®å²è¾¼ã¿ï¼FIQãã«ã¼ãã«ç®¡çå¤ã®å²è¾¼ã¿ã¨ããï¼
+
+
+(3-1-2) å²è¾¼ã¿ãã³ãã©çªå·ã¨å²è¾¼ã¿çªå·ã®å²å½ã¦ï¼ä¸¡è
+ã®å¯¾å¿
+
+å²è¾¼ã¿ãã³ãã©çªå·ã¨å²è¾¼ã¿çªå·ã¯ï¼BCM2835åã³BCM2836ã®
+ããªãã§ã©ã«ããã¥ã¢ã«(ä¸è¨aåã³b)ããï¼ãã³ãã£ã³ã°ã¬ã¸ã¹ã¿ã®ãããä½ç½®ã«åºã¥ãã¦
+0ãã127ã®çªå·ãå²ãå½ã¦ãï¼(åã
+ã®å®ç¾©ã¯ bcm2837.h ãåç
+§)
+
+ 0 ... 31  Core interrupt (ä¸è¨aã®P16 ãCore0 interrupt sourceãã«å¯¾å¿)
+32 ... 63  ARM peripherals interrupt(bã®P113ãBasic pending registerãã«å¯¾å¿)
+64 ... 95  ARM peripherals interrupt(bã®P115ãGPU pending register 1ãã«å¯¾å¿)
+96 ...127  ARM peripherals interrupt(bã®P115ãGPU pending register 2ãã«å¯¾å¿)
+
+(a) QA7(ARM Quad A7 core)
+https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/QA7_rev3.4.pdf
+
+(b) BCM2835 ARM Peripherals 
+https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2835/BCM2835-ARM-Peripherals.pdf
+
+
+(3-1-3) å²è¾¼ã¿åªå
+åº¦ã®æ®µéæ°ï¼TMIN_INTPRIã®å¤ï¼ï¼ãã®è¨­å®æ¹æ³
+
+å²è¾¼ã¿åªå
+åº¦ã®æ®µéæ°ã¯ï¼ã¿ã¼ã²ããä¾å­é¨æ¯ã«ç°ãªãï¼
+BCM283x ã®å²è¾¼ã¿ã³ã³ãã­ã¼ã©ã¯åªå
+åº¦å¶å¾¡æ©è½ãæããªãããã½ããã¦ã§ã¢ã§å®ç¾ããï¼
+ãã®ããæ®µéæ°ãç¬èªã«è¨­å®ãããã¨ãå¯è½ã§ããï¼
+
+ã«ã¼ãã«ç®¡çå
+ã®å²è¾¼ã¿ã«å¯¾ããæé«åªå
+åº¦(TMIN_INTPRI)ã¯ãããä¾å­é¨ã§
+æ¢å®å¤ãå®ç¾©ãã¦ãããï¼ã¿ã¼ã²ããä¾å­é¨ã§è¨­å®ãããã¨ãå¯è½ã§ããï¼
+
+åå²è¾¼ã¿ã®å²è¾¼ã¿åªå
+åº¦ã¯ï¼CFG_INT ã§è¨­å®ããï¼åªå
+åº¦ã¯ TMIN_INTPRI ä»¥ä¸ã®å¤
+(åªå
+åº¦ã¨ãã¦ã¯ä½ãå¤)ãæå®ããï¼
+
+(3-1-4) dis_intã¨ena_intã®ãµãã¼ãã®æç¡ï¼ãã®å¶éäºé 
+
+
+dis_int ã¨ ena_int ã¯ãµãã¼ãããªã
+
+
+(3-1-5) CFG_INTã®å¶éäºé 
+ã¨æ¡å¼µï¼ã¿ã¼ã²ããå®ç¾©ã§ä½¿ç¨ã§ããå²è¾¼ã¿å±æ§ï¼
+
+ã¬ãã«å²è¾¼ã¿ãããµãã¼ãããªãããï¼ã¨ãã¸/ã¬ãã«ã®ããªã¬è¨­å®ã¯æå³ããããªãï¼
+ãã®ä»ï¼ã¿ã¼ã²ããç¬èªã«ä½¿ç¨å¯è½ãªå²è¾¼ã¿å±æ§ã¯ãªãï¼
+
+
+(3-1-6) ã«ã¼ãã«ç®¡çå¤ã®å²è¾¼ã¿
+
+FIQå²è¾¼ã¿ãã«ã¼ãã«ç®¡çå¤ã®å²è¾¼ã¿ã¨ãã¦æ±ãï¼
+
+FIQå²è¾¼ã¿ãçºçããã¨è©²å½ããå²è¾¼ã¿ãã¯ã¿ããã¬ã¸ã¹ã¿ã®éé¿ãè¡ãªã£ãå¾ã«
+call_fiq_handler (core_config.c) ãå¼ã³åºãããï¼ãã®é¢æ°ã¯ï¼
+ã³ã¢ã®å
+¨ã¦ã®ä¾å¤ããã¹ã¯ãããç¶æ
+(ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿ã®D,A,I,Fãå
+¨ã¦1)ã§
+å¼ã³åºãããï¼
+
+FIQãå©ç¨ããããã®è¨­å®ï¼çºçããFIQ å²è¾¼ã¿ã«å¯¾ããè¦å å¤å¥ï¼
+åã³å¯¾å¿ãããã³ãã©ç­ã®å¦çã¯ç¬èªã«å®è£
+ããå¿
+è¦ãããï¼
+
+ã«ã¼ãã«ç®¡çå¤ã®å²è¾¼ã¿ãè¨­å®ããããã®APIã¯ãµãã¼ãããªãï¼
+
+
+(3-2) CPUã­ãã¯ã»å²è¾¼ã¿ã­ãã¯
+
+CPUã­ãã¯ã¯ï¼ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿ã®Iãããã®å¤ã§å¤å¥ããï¼
+å
+¨å²è¾¼ã¿ã­ãã¯ãã©ã°ã®å®è£
+ã§ã¯ããã«å ãFããããä½¿ç¨ããï¼
+
+CPUã­ãã¯ãã©ã°ã¯å²è¾¼ã¿ã­ãã¯ãã©ã°ã¨ã¯ç¬ç«ãããã©ã°ã¨ãã¦ãµãã¼ãããï¼
+ãã®ããï¼SIL_LOC_INTå¼ã³åºãæã¯Iãã©ã°ã®ç¶æ
+ãè¨æ¶ãï¼
+SIL_UNL_INTå¼ã³åºãæã«å
+ã®ç¶æ
+ã«æ»ãã¦ããï¼
+
+
+(3-3) æ§è½è©ä¾¡ç¨ã·ã¹ãã æå»ã®åç
+§ã«é¢ããè¦å®
+
+get_utmããµãã¼ãããªãï¼
+
+
+(3-4) ã¹ã¿ã¼ãã¢ããã«ã¼ãã³ã§ã®åæåå
+å®¹
+
+ã¹ã¿ã¼ãã¢ããã«ã¼ãã³ã¯ã¿ã¼ã²ããä¾å­é¨ã®ãã­ã¥ã¡ã³ãã«è¨è¼ããï¼
+
+
+(4) ãã£ã¬ã¯ããªæ§æã»ãã¡ã¤ã«æ§æ
+  ./arch/arm64_gcc/bcm283x/
+    MANIFEST
+    Makefile.chip
+    bcm2837.h
+    chip_cfg1_out.h
+    chip_check.trb
+    chip_config.c
+    chip_config.h
+    chip_design.txt
+    chip_kernel.h
+    chip_kernel.trb
+    chip_rename.def
+    chip_rename.h
+    chip_serial.c
+    chip_serial.cfg
+    chip_serial.h
+    chip_sil.h
+    chip_stddef.h
+    chip_support.S
+    chip_sym.def
+    chip_test.h
+    chip_timer.cfg
+    chip_timer.h
+    chip_unrename.h
+    chip_user.txt
+    pl011.h
+
+(12) ãã¼ã¸ã§ã³å±¥æ­´
+
+2018/05/30
+ ã»æåã®ãªãªã¼ã¹
+2019/04/15
+ ã»BCM283xãããä¾å­é¨ã®åé¢ã«åããã¦ä¿®æ­£
Index: /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/pl011.h
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/pl011.h	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/bcm283x/pl011.h	(revision 384)
@@ -0,0 +1,115 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
+ *                              Toyohashi Univ. of Technology, JAPAN
+ *  Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2018,2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  $Id$
+ */
+
+/*
+ *  ARM PrimCell UARTï¼PL011ï¼ã«é¢ããå®ç¾©
+ */
+
+#ifndef TOPPERS_PL011_H
+#define TOPPERS_PL011_H
+
+/*
+ *  UARTã¬ã¸ã¹ã¿ã®çªå°ã®å®ç¾©
+ */
+#define UART_DR(base)		((uint32_t *)((base) + 0x00U))
+#define UART_RSR(base)		((uint32_t *)((base) + 0x04U))
+#define UART_ECR(base)		((uint32_t *)((base) + 0x04U))
+#define UART_FR(base)		((uint32_t *)((base) + 0x18U))
+#define UART_IBRD(base)		((uint32_t *)((base) + 0x24U))
+#define UART_FBRD(base)		((uint32_t *)((base) + 0x28U))
+#define UART_LCR_H(base)	((uint32_t *)((base) + 0x2cU))
+#define UART_CR(base)		((uint32_t *)((base) + 0x30U))
+#define UART_IFLS(base)		((uint32_t *)((base) + 0x34U))
+#define UART_IMSC(base)		((uint32_t *)((base) + 0x38U))
+#define UART_RIS(base)		((uint32_t *)((base) + 0x3cU))
+#define UART_MIS(base)		((uint32_t *)((base) + 0x40U))
+#define UART_ICR(base)		((uint32_t *)((base) + 0x44U))
+
+/*
+ *  ãã©ã°ã¬ã¸ã¹ã¿ï¼UART_FRï¼ã®åç
+§å¤
+ */
+#define UART_FR_RXFE		UINT_C(0x10)	/* åä¿¡ãããã¡ãç©º */
+#define UART_FR_TXFF		UINT_C(0x20)	/* éä¿¡ãããã¡ããã« */
+
+/*
+ *  ã©ã¤ã³å¶å¾¡ã¬ã¸ã¹ã¿ï¼UART_LCR_Hï¼ã®è¨­å®å¤
+ */
+#define UART_LCR_H_PEN		UINT_C(0x02)	/* ããªãã£ãç¨ãã */
+#define UART_LCR_H_EPS		UINT_C(0x04)	/* å¶æ°ããªãã£ã« */
+#define UART_LCR_H_STP2		UINT_C(0x08)	/* ã¹ããããããã2ãããã« */
+#define UART_LCR_H_FEN		UINT_C(0x10)	/* FIFOãæå¹ã« */
+#define UART_LCR_H_WLEN8	UINT_C(0x60)	/* ãã¼ã¿é·ã8ãããã« */
+
+/*
+ *  å¶å¾¡ã¬ã¸ã¹ã¿ï¼UART_CRï¼ã®è¨­å®å¤
+ */
+#define UART_CR_UARTEN	UINT_C(0x0001)		/* UARTãã¤ãã¼ãã«ã« */
+#define UART_CR_TXE		UINT_C(0x0100)		/* éä¿¡ãã¤ãã¼ãã«ã« */
+#define UART_CR_RXE		UINT_C(0x0200)		/* åä¿¡ãã¤ãã¼ãã«ã« */
+
+/*
+ *  å²è¾¼ã¿ãã¹ã¯ã»ããï¼ã¯ãªã¢ã¬ã¸ã¹ã¿ï¼UART_IMSCï¼ã®è¨­å®å¤
+ */
+#define UART_IMSC_RXIM	UINT_C(0x0010)		/* åä¿¡å²è¾¼ã¿ãã¹ã¯ */
+#define UART_IMSC_TXIM	UINT_C(0x0020)		/* éä¿¡å²è¾¼ã¿ãã¹ã¯ */
+
+#ifndef TOPPERS_MACRO_ONLY
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_PL011_H */
Index: /ssp_rpi3/trunk/arch/arm64_gcc/common/Makefile.core
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/common/Makefile.core	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/common/Makefile.core	(revision 384)
@@ -0,0 +1,47 @@
+#
+#  Makefile ã®ã³ã¢ä¾å­é¨ï¼ARMv8-Aç¨ï¼
+#
+
+#
+#  ãã£ã¬ã¯ããªåã®å®ç¾©
+#
+COREDIR = $(SRCDIR)/arch/$(CORE)_$(TOOL)/common
+
+#
+#  ã³ã³ãã¤ã«ãªãã·ã§ã³
+#
+COPTS := $(COPTS) -march=armv8-a -mlittle-endian -mstrict-align
+CDEFS := $(CDEFS)
+INCLUDES := $(INCLUDES) -I$(COREDIR)
+LDFLAGS := $(LDFLAGS)
+LIBS := $(LIBS)
+
+#
+#  ã«ã¼ãã«ã«é¢ããå®ç¾©
+#
+KERNEL_DIRS := $(KERNEL_DIRS) $(COREDIR)
+KERNEL_ASMOBJS := $(KERNEL_ASMOBJS) core_support.o
+KERNEL_COBJS := $(KERNEL_COBJS) core_config.o core_timer.o
+KERNEL_CFLAGS := $(KERNEL_CFLAGS)
+
+#
+#  ã³ã³ãã£ã®ã¥ã¬ã¼ã¿é¢ä¿ã®å¤æ°ã®å®ç¾©
+#
+CFG_TABS := $(CFG_TABS) --symval-table $(COREDIR)/core_sym.def
+CFG1_OUT_LDFLAGS := $(CFG1_OUT_LDFLAGS)
+CFG_OBJS := $(CFG_OBJS)
+CFG2_OUT := $(CFG2_OUT)
+
+#
+#  ä¾å­é¢ä¿ã®å®ç¾©
+#
+cfg1_out.c: $(COREDIR)/core_sym.def
+kernel_cfg.timestamp: $(COREDIR)/core_kernel.trb
+check.timestamp: $(COREDIR)/core_check.trb
+
+#
+#  ãã®ä»
+#
+CLEAN_FILES := $(CLEAN_FILES)
+REALCLEAN_FILES := $(REALCLEAN_FILES)
+
Index: /ssp_rpi3/trunk/arch/arm64_gcc/common/arm64.h
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/common/arm64.h	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/common/arm64.h	(revision 384)
@@ -0,0 +1,197 @@
+/*
+ *  TOPPERS Software
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *
+ *  Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2018,2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  $Id$
+ */
+#ifndef TOPPERS_ARM64_H
+#define TOPPERS_ARM64_H
+
+/*
+ *  PSTATE
+ */
+#define AARCH64_PSTATE_N         (1 << 31)
+#define AARCH64_PSTATE_Z         (1 << 30)
+#define AARCH64_PSTATE_C         (1 << 29)
+#define AARCH64_PSTATE_V         (1 << 28)
+#define AARCH64_PSTATE_SS        (1 << 21)
+#define AARCH64_PSTATE_IL        (1 << 20)
+#define AARCH64_PSTATE_D         (1 << 9)
+#define AARCH64_PSTATE_A         (1 << 8)
+#define AARCH64_PSTATE_I         (1 << 7)
+#define AARCH64_PSTATE_F         (1 << 6)
+#define AARCH64_PSTATE_MODE4     (1 << 4)
+#define AARCH64_PSTATE_MODE_MASK (AARCH64_PSTATE_MODE4 - 1)
+
+/*
+ *  DAIF
+ */
+#define AARCH64_DAIF_FIQ    UINT64_C(1)
+#define AARCH64_DAIF_IRQ    UINT64_C(2)
+#define AARCH64_DAIF_SERR   UINT64_C(4)
+#define AARCH64_DAIF_DBG    UINT64_C(8)
+#define AARCH64_DAIF_ALL    (AARCH64_DAIF_DBG|AARCH64_DAIF_SERR|AARCH64_DAIF_IRQ|AARCH64_DAIF_FIQ)
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ *  DAIFã®è¨­å®ããã³ç¶æ
+åç
+§
+ */
+Inline uint32_t
+aarch64_get_daif(void){
+    uint32_t daif;
+    Asm ("mrs %0, daif\n\t":"=r"(daif): : "memory");
+    return daif;
+}
+
+Inline void
+aarch64_set_daif(uint32_t daif) {
+
+    Asm ("msr daif, %0\n\t" : : "r"(daif): "cc", "memory");
+}
+
+/*
+ *  DAIF.I ã®ã»ãã/ã¯ãªã¢
+ */
+Inline void
+aarch64_set_daif_i(void) {
+    Asm ("msr daifset, %0\n\t"::"i"(AARCH64_DAIF_IRQ): "cc", "memory");
+}
+
+Inline void
+aarch64_clear_daif_i(void) {
+    Asm ("msr daifclr, %0\n\t"::"i"(AARCH64_DAIF_IRQ): "cc", "memory");
+}
+
+/*
+ *  DAIF.F ã®ã»ãã/ã¯ãªã¢
+ */
+Inline void
+aarch64_set_daif_f(void) {
+    Asm ("msr daifset, %0\n\t"::"i"(AARCH64_DAIF_FIQ): "cc", "memory");
+}
+
+Inline void
+aarch64_clear_daif_f(void) {
+    Asm ("msr daifclr, %0\n\t"::"i"(AARCH64_DAIF_FIQ): "cc", "memory");
+}
+
+/*
+ *  DAIF.F ããã³ DAIF.I ã®åæã»ãã/ã¯ãªã¢
+ */
+Inline void
+aarch64_set_daif_if(void) {
+    Asm ("msr daifset, %0\n\t"::"i"(AARCH64_DAIF_IRQ | AARCH64_DAIF_FIQ): "cc", "memory");
+}
+
+Inline void
+aarch64_clear_daif_if(void) {
+    Asm ("msr daifclr, %0\n\t"::"i"(AARCH64_DAIF_IRQ | AARCH64_DAIF_FIQ): "cc", "memory");
+}
+
+/*
+ *  DAIF.I ã®ç¶æ
+åç
+§
+ */
+Inline bool_t
+aarch64_sense_daif_irq(void) {
+    uint32_t daif;
+    bool_t state;
+
+    daif = aarch64_get_daif();
+
+    if(daif & AARCH64_PSTATE_I) {
+        state = true;
+    }
+    else {
+        state = false;
+    }
+
+    return state;
+}
+
+/*
+ *  DAIF.F ã®ç¶æ
+åç
+§
+ */
+Inline bool_t
+aarch64_sense_daif_fiq(void) {
+    uint32_t daif;
+    bool_t state;
+
+    daif = aarch64_get_daif();
+
+    if(daif & AARCH64_PSTATE_F) {
+        state = true;
+    }
+    else {
+        state = false;
+    }
+
+    return state;
+}
+
+/*
+ *  ã¯ãªãã£ã«ã«å¦çã®åºå£(æé©åé²æ­¢)
+ */
+Inline void
+aarch64_exit_critical(void)
+{
+    Asm("":::"memory");
+}
+
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_ARM64_H */
Index: /ssp_rpi3/trunk/arch/arm64_gcc/common/core_cfg1_out.h
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/common/core_cfg1_out.h	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/common/core_cfg1_out.h	(revision 384)
@@ -0,0 +1,12 @@
+/*
+ *  @(#) $Id$
+ */
+
+/*
+ *		cfg1_out.cããªã³ã¯ããããã«å¿
+è¦ãªã¹ã¿ãã®å®ç¾©
+ */
+
+void sta_ker(void){}
+STK_T *const	_kernel_istkpt = 0x00;
+void * _kernel_vectors = 0x00;
Index: /ssp_rpi3/trunk/arch/arm64_gcc/common/core_check.trb
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/common/core_check.trb	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/common/core_check.trb	(revision 384)
@@ -0,0 +1,9 @@
+# -*- coding: utf-8 -*-
+# 
+#		ãã¹3ã®çæã¹ã¯ãªããã®ã³ã¢ä¾å­é¨ï¼ARM64ç¨ï¼
+# 
+
+#
+#  ã¿ã¼ã²ããéä¾å­é¨ã®ã¤ã³ã¯ã«ã¼ã
+#
+IncludeTrb("kernel/kernel_check.trb")
Index: /ssp_rpi3/trunk/arch/arm64_gcc/common/core_config.c
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/common/core_config.c	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/common/core_config.c	(revision 384)
@@ -0,0 +1,200 @@
+/*
+ *  TOPPERS/SSP Kernel
+ *      Smallest Set Profile Kernel
+ *
+ *  Copyright (C) 2008 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2010 by Meika Sugimoto
+ *  Copyright (C) 2018, 2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  @(#) $Id$
+ */
+
+/*
+ *  ã³ã¢ä¾å­ã¢ã¸ã¥ã¼ã«ï¼ARMv8-Aç¨ï¼
+ */
+
+#include "kernel_impl.h"
+#include <t_syslog.h>
+
+/* å²è¾¼ã¿ãã¹ãæ°ã®ç®¡ç */
+uint8_t intnest;
+
+/*
+ *  ã³ã¢ä¾å­ã®åæå
+ */
+void
+core_initialize(void)
+{
+    /* å²è¾¼ã¿ãã¹ãæ°ã®åæå */
+    intnest = 0u;
+}
+
+/*
+ *  ã³ã¢ä¾å­ã®çµäºå¦ç
+ */
+void
+core_terminate(void)
+{
+    while(1)
+    ;
+}
+
+/*
+ *  å²è¾¼ã¿ãã³ãã©ã®å¼ã³åºã
+ */
+void
+call_int_handler(uint32_t intno)
+{
+    intnest++;
+
+    i_unlock_cpu();
+
+    // ãã³ãã©ã®å¼ã³åºã
+    inh_table[intno]();
+
+    i_lock_cpu();
+
+    intnest--;
+}
+
+/*
+ *  ã«ã¼ãã«ç®¡çã®CPUä¾å¤ãã³ãã©ã®å¼ã³åºã
+ */
+void
+call_exc_handler(void *p_excinf, uint32_t excno)
+{
+    uint64_t spsr = *(((uint64_t*)p_excinf) + 4);
+
+    intnest++;
+
+    /*
+     *  ãã­ã»ããµã®ç¶æ
+ãCPUä¾å¤çºçåã®ç¶æ
+ã«ãã
+     */
+    if((spsr & AARCH64_PSTATE_F) == 0) {
+        aarch64_clear_daif_f();
+    }
+
+    if((spsr & AARCH64_PSTATE_I) == 0) {
+        aarch64_clear_daif_i();
+    }
+
+    // ãã³ãã©ã®å¼ã³åºã
+    exc_table[excno](p_excinf);
+
+    /*
+     *  ãã­ã»ããµã®ç¶æ
+ãæ»ã
+     */
+    if((spsr & AARCH64_PSTATE_F) == 0) {
+        aarch64_set_daif_f();
+    }
+
+    if((spsr & AARCH64_PSTATE_I) == 0) {
+        aarch64_set_daif_i();
+    }
+
+    intnest--;
+}
+
+/*
+ *  FIQãã³ãã©ã®å¼ã³åºã
+ *    å
+¨ã¦ã®ä¾å¤ããã¹ã¯ãããç¶æ
+ã§å¼ã³åºããã
+ *    ä¾å¤è¦å ã®å¤å¥ãå«ããã(ãããã¯ããããå¼ã³åºãããã«ã¼ãã³)ã§è¡ã
+ */
+void
+call_fiq_handler(void)
+{
+}
+
+
+#ifndef OMIT_DEFAULT_EXC_HANDLER
+/*
+ *  ç»é²ããã¦ããªãä¾å¤ãçºçããã¨å¼ã³åºããã
+ */
+void
+default_exc_handler(void *p_excinf)
+{
+    uint64_t ipm = *(((uint64_t*)p_excinf) + 0);
+    uint64_t excno    = *(((uint64_t*)p_excinf) + 1);
+    uint64_t esr, pc, spsr, sp;
+
+    esr      = *(((uint64_t*)p_excinf) + 2);
+    pc       = *(((uint64_t*)p_excinf) + 3);
+    spsr     = *(((uint64_t*)p_excinf) + 4);
+    sp       = *(((uint64_t*)p_excinf) + 36);
+
+    syslog(LOG_EMERG, "\nUnregistered CPU Exception occured.");
+    syslog(LOG_EMERG, "EXCNO = %08x ESR = %08x iMASK = %08x ", excno, esr, ipm);
+    syslog(LOG_EMERG, "PC=%08x%08x SP = %08x%08x SPSR = %08x",
+        (uint32_t)((pc & UINT64_C(0xffffffff00000000))>>32), (uint32_t)(pc & UINT64_C(0xffffffff)),
+        (uint32_t)((sp & UINT64_C(0xffffffff00000000))>>32), (uint32_t)(sp & UINT64_C(0xffffffff)),
+        (uint32_t)spsr);
+
+    target_exit();
+}
+#endif /* OMIT_DEFAULT_EXC_HANDLER */
+
+#ifndef OMIT_DEFAULT_INT_HANDLER
+/*
+ *  æªç»é²ã®å²è¾¼ã¿ãçºçããå ´åã«å¼ã³åºããã
+ */
+void
+default_int_handler(void)
+{
+    syslog(LOG_EMERG, "\nUnregistered Interrupt occurs.");
+
+    target_exit();
+}
+#endif /* OMIT_DEFAULT_INT_HANDLER */
+
+
Index: /ssp_rpi3/trunk/arch/arm64_gcc/common/core_config.h
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/common/core_config.h	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/common/core_config.h	(revision 384)
@@ -0,0 +1,185 @@
+/*
+ *  TOPPERS/SSP Kernel
+ *      Smallest Set Profile Kernel
+ *
+ *  Copyright (C) 2008 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2015,2018,2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  @(#) $Id$
+ */
+
+/*
+ *    ã³ã¢ä¾å­ã¢ã¸ã¥ã¼ã«ï¼ARMv8-Aç¨ï¼
+ *
+ *  ãã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«ã¯ï¼target_config.hï¼ã¾ãã¯ï¼ããããã¤ã³ã¯
+ *  ã«ã¼ãããããã¡ã¤ã«ï¼ã®ã¿ããã¤ã³ã¯ã«ã¼ããããï¼ä»ã®ãã¡ã¤ã«ãã
+ *  ç´æ¥ã¤ã³ã¯ã«ã¼ããã¦ã¯ãªããªãï¼
+ */
+
+#ifndef TOPPERS_CORE_CONFIG_H
+#define TOPPERS_CORE_CONFIG_H
+
+/*
+ *  ãã¼ãã¦ã§ã¢å®ç¾©
+ */
+#include "arm64.h"
+
+/*
+ *  éã¿ã¹ã¯ã³ã³ãã­ã¹ãç¨ã®ã¹ã¿ãã¯åæå¤
+ */
+#define TOPPERS_ISTKPT(istk, istksz) ((STK_T *)((char *)(istk) + (istksz)))
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ *  å²è¾¼ã¿ãã¹ãæ°
+ */
+extern uint8_t intnest;
+
+/*
+ *  ã³ã³ãã­ã¹ãã®åç
+§
+ *
+ */
+Inline bool_t
+sense_context(void)
+{
+	bool_t ctx;
+
+	if (intnest > 0u){
+		ctx = true;
+	}
+	else {
+		ctx = false;
+	}
+
+	return ctx;
+}
+
+/*
+ *  ãã£ã¹ãããã£ã®åä½éå§ï¼core_support.Sï¼
+ *
+ *  start_dispatchã¯ï¼ã«ã¼ãã«èµ·åæã«å¼ã³åºãã¹ããã®ã§ï¼ãã¹ã¦ã®å²è¾¼
+ *  ã¿ãç¦æ­¢ããç¶æ
+ï¼å²è¾¼ã¿ã­ãã¯ç¶æ
+ã¨åç­ã®ç¶æ
+ï¼ã§å¼ã³åºããªããã°
+ *  ãªããªãï¼
+ */
+extern void start_dispatch(void) NoReturn;
+
+/*
+ *  ã«ã¼ãã«ã®çµäºå¦çã®å¼åºãï¼prc_support.Sï¼
+ *
+ *  call_exit_kernelã¯ï¼ã«ã¼ãã«ã®çµäºæã«å¼ã³åºãã¹ããã®ã§ï¼éã¿ã¹ã¯
+ *  ã³ã³ãã­ã¹ãã«åãæãã¦ï¼ã«ã¼ãã«ã®çµäºå¦çï¼exit_kernelï¼ãå¼ã³åº
+ *  ãï¼
+ */
+extern void call_exit_kernel(void) NoReturn;
+
+/*
+ *  ã¢ã¤ãã«ã«ã¼ãã®å®è£
+
+ *
+ *  åã«CPUã­ãã¯ç¶æ
+ã¨CPUã­ãã¯è§£é¤ç¶æ
+ãå¼ã³åºãå®è£
+ã¨ããï¼
+ *  ã¹ãªã¼ãã¢ã¼ãã«å
+¥ããå ´åã¯æ¬å¦çãwfiå½ä»¤ãç¨ãã¦æ¸ãæããã°è¯ãï¼
+ */
+Inline void
+idle_loop(void)
+{
+    x_unlock_cpu();
+    /* CPUã¢ã³ã­ãã¯ => CPUã­ãã¯  */
+    x_lock_cpu();
+}
+
+/*
+ *  ã³ã¢ä¾å­ã®åæå
+ */
+extern void core_initialize(void);
+
+/*
+ *  ã³ã¢ä¾å­ã®çµäºæå¦ç
+ */
+extern void core_terminate(void) NoReturn;
+
+/*
+ *  å²è¾¼ã¿ãã³ãã©ã®å¼ã³åºã
+ */
+extern void call_int_handler(uint32_t intno);
+
+/*
+ *  CPUä¾å¤ãã³ãã©ã®å¼ã³åºã
+ */
+extern void call_exc_handler(void *p_excinf, uint32_t excno);
+
+/*
+ *  FIQãã³ãã©ã®å¼ã³åºã
+ *    å
+¨ã¦ã®ä¾å¤ããã¹ã¯ãããç¶æ
+ã§å¼ã³åºããã
+ *    ä¾å¤è¦å ã®å¤å¥ãå«ããã(ãããã¯ããããå¼ã³åºãããã«ã¼ãã³)ã§è¡ã
+ */
+extern void call_fiq_handler(void);
+
+/*
+ * ç»é²ããã¦ããªãä¾å¤ãçºçããã¨å¼ã³åºããã
+ */
+extern void default_exc_handler(void *p_excinf);
+
+/*
+ * æªç»é²ã®å²è¾¼ã¿ãçºçããå ´åã«å¼ã³åºããã
+ */
+extern void default_int_handler(void);
+
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_CORE_CONFIG_H */
Index: /ssp_rpi3/trunk/arch/arm64_gcc/common/core_design.txt
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/common/core_design.txt	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/common/core_design.txt	(revision 384)
@@ -0,0 +1,430 @@
+=====================================================================
+                         ARM64ãã­ã»ããµä¾å­é¨è¨­è¨ã¡ã¢
+                                  Last Modified: 16 Apr 2019
+=====================================================================
+
+â ãã®ãã­ã¥ã¡ã³ãã®ä½ç½®ã¥ã
+
+ãã®ãã­ã¥ã¡ã³ãã¯ï¼TOPPERS/SSPã«ã¼ãã«ãARMv8-Aãã­ã»ããµã«ç§»æ¤ããé
+ã®è¨­è¨ã¡ã¢ã§ããï¼
+
+
+â ARMv8-Aã®ä»æ§ã¾ã¨ã
+
+ARMv8-Aã®ä»æ§ã®ãã¡ï¼ã«ã¼ãã«ã®è¨­è¨ã«é¢ä¿ããäºé 
+ã«ã¤ãã¦ã¾ã¨ããï¼
+
+â ã¬ã¸ã¹ã¿
+
+æ±ç¨ã¬ã¸ã¹ã¿ã¯r0ãr30 (ç¹ã«64ãããã¬ã¸ã¹ã¿ã¯X0..X30ã§è¡¨ç¾)ã®31ç¨®é¡ãããªãï¼
+ï¼åèï¼ãProcedure Call Standard for the ARM 64-bit Architectureã
+
+r0...r7    Parameter/result registers(å¼æ°ããã³è¿å¤ã®åãæ¸¡ãç¨)
+r8         Indirect result location register (å¤§ããªãã¼ã¿æ§é ã
+           è¿å¤ã¨ãã¦è¿ãå ´åãªã©ï¼å¼ã³åºãå´ãçµæãåãåºãããã«
+           éæ¥ã¢ãã¬ãã·ã³ã°ãå¤ç¨ããéï¼ãã®ãã¼ã¹ã¢ãã¬ã¹ãåãæ¸¡ã
+           ããããã«ä½¿ããã)
+r9..r15    Caller-saved Temporary registers(å¼ã³åºãå´ã§ä¿å­ãã¹ãã¬ã¸ã¹ã¿)
+r16(IP0)   The first intra-procedure-call scratch register
+           ãªã³ã«ã«ãã£ã¦ veneer(æ³¨1) ããã³ PLT(Procedure Linkage Table,æ³¨2) ã³ã¼ã
+           ã®å¼ã³åºãã§ä½¿ãããï¼ããä»¥å¤ã®æã¯ãã³ãã©ãªã¬ã¸ã¹ã¿ã¨ãã¦ä½¿ããããã¨ãããï¼
+           (æ³¨1)ãªã³ã«ã«ãã£ã¦æ¿å
+¥ãããå°ããªã³ã¼ãçã§ï¼
+                åå²å½ä»¤ã®ã¿ã¼ã²ãããç¯å²å¤ã®å ´åãªã©ã«ä½¿ããã
+           (æ³¨2)å
+±æã©ã¤ãã©ãªã®å¼ã³åºãã§ã·ã³ãã«è§£æ±ºãè¡ãããã«ä½¿ç¨ããã
+                é¢æ°ãã¼ãã«
+r17(IP1)   The second intra-procedure-call temporary register(r16ã¨å½¹å²ã¯åã)
+r18        The Platform Register(ãã©ãããã©ã¼ã ABIã§ä½¿ç¨ãããã¬ã¸ã¹ã¿ï¼
+           ABIã§ä½¿ãããªãå ´åã¯ãã³ãã©ãªã¬ã¸ã¹ã¿ã¨ãã¦ä½¿ããã)
+r19..r28   Callee-saved registers(å¼ã³åºãããå´ã§ä¿å­ãã¦ä½¿ãã¬ã¸ã¹ã¿)
+r29(FP)    The Frame Pointer(ãã¬ã¼ã ãã¤ã³ã¿)
+r30(LR)    The Link Register(ãªã³ã¯ã¬ã¸ã¹ã¿)
+
+SSPã«ã¼ãã«ã®ã¢ã»ã³ãã©ã«ããå®è£
+ã§ã¯r8, r16...r18ã¯ä½¿ç¨ãã¦ããªãï¼
+
+
+â ã³ã¼ãªã³ã°ã³ã³ãã³ã·ã§ã³
+
+r0...r7 ãå¼æ°ããã³è¿å¤ã«ä½¿ãããï¼
+ARMã«ããè¦å®ããã¦ããããï¼ã³ã³ãã¤ã©ã«ä¾å­ãããã®ã«ã¼ã«ã¨ãªã
+
+
+â PSTATE
+
+AArch64ã§ã¯ãã­ã»ããµã®ç¶æ
+ãè¡¨ããã©ã°ã®éã¾ããã¾ã¨ãã¦PSTATEã¨å¼ã³ï¼
+ããããã®ãã©ã°ã¸å¥ã
+ã«ã¢ã¯ã»ã¹ããããã®ç¹å¥ãªã¬ã¸ã¹ã¿åãå®ç¾©ããã¦ããï¼
+
+PSTATEã®è©³ç´°ã¯ï¼ARM Architecture Reference Manual
+ARMv8, for ARMv8-A architecture profile ã® D1.7 ãªã©ãåç
+§ã®ãã¨ï¼
+
+ã»spsel
+EL1ããä¸ã®ä¾å¤ã¬ãã«ã§ã¯ï¼spsel ã¨ããç¹å¥ãªåç§°ã®ã¬ã¸ã¹ã¿ã«ã¢ã¯ã»ã¹ãï¼
+PSTATE.SPãã©ã°ã®å¤ãã»ãããã¦ä½¿ç¨ã¹ã¿ãã¯ã®åãæ¿ããè¡ãï¼
+
+ã»daif
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+åç¨®ä¾å¤ããã³å²è¾¼ã¿ã®ç¦æ­¢/è¨±å¯ãå¶å¾¡ãã
+
+
+SSPã«ã¼ãã«ã®å®è£
+ã§ã¯ï¼ã¹ã¿ãã¯ã¯SP_EL1ã®ã¿ãä½¿ç¨ããï¼
+ã¾ãï¼CPUã­ãã¯ç¶æ
+ããã³å²è¾¼ã¿ã­ãã¯ç¶æ
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+ã«PSTATEã®Iããã³Fãã©ã°ã
+å©ç¨ãã¦ããï¼
+
+
+â å²è¾¼ã¿ãã¯ã¿
+
+ãã¯ã¿ãã¼ãã«ã®ã¢ãã¬ã¹ã¯ãªã»ããæã«ï¼ã·ã¹ãã ã¬ã¸ã¹ã¿ã®ä¸ã¤Vector Base
+Address Register(VBAR, ã·ã¹ãã ã¬ã¸ã¹ã¿)ã«ã¢ãã¬ã¹ãã»ãããããã¨ã§ï¼
+2048ãã¤ãå¢çã®ä»»æã®ã¢ãã¬ã¹ã«é
+ç½®å¯è½ã§ããï¼
+
+SSPã«ã¼ãã«ã®å®è£
+ã§ã¯ã¹ã¿ã¼ãã¢ããã«ã¼ãã³ã§è¨­å®ãã¦ããï¼
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+
+
+âå²è¾¼ã¿åªå
+åº¦
+
+GICã«ããã¦ã¯å²è¾¼ã¿åªå
+åº¦ã¯è¨­å®å¤ã®å°ããæ¹ãé«åªå
+åº¦ã¨ãªãï¼
+
+åªå
+åº¦ã¯æå¤§8bitã§ããï¼SoCæ¯ã«å®è£
+ããã¦ãããããå¹
+ãç°ãªãï¼å®è£
+ã
+ãããããã8bitä»¥ä¸ã®å ´åã¯ï¼LSBããç¡å¹ã«ãªãï¼ä¾ãã°ï¼å®è£
+ããã¦ã
+ããããå¹
+ã7bitã®å ´åã¯ï¼ããã0ãç¡å¹ã¨ãªãï¼
+
+åªå
+åº¦ã®ããããã£ã¼ã«ãã®LSBããæ°ãããããµãåªå
+åº¦ã¨å¼ã¶ãã£ã¼ã«ã
+ã«è¨­å®ãããã¨ãå¯è½ã§ããï¼æ®ãã®ä¸ä½ããããããªã¨ã³ãã·ã§ã³åªå
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+å¼ã¶ï¼ããªã¨ã³ãã·ã§ã³åªå
+åº¦ãåãã§ï¼ãµãåªå
+åº¦ãç°ãªãåªå
+åº¦ã®ã°ã«ã¼
+ãã¯ï¼ãäºããããªã¨ã³ãããããã¨ãã§ããªãï¼
+
+ä¾ã¨ãã¦ï¼QEMU Virtãã¼ãåãSSPã®å®è£
+ã§ã¯ Cortex-A53ãã­ã»ããµã
+ã¿ã¼ã²ããã¨ãã¦ããï¼åªå
+åº¦ã¯16æ®µé(4bit)ã§ããã0ãã3ãç¡å¹ã§ããï¼
+
+âå²è¾¼ã¿/ä¾å¤ã®åä»
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+GICã®å ´åï¼å²è¾¼ã¿ãåãä»ããã¨åãä»ããå²è¾¼ã¿ã®çªå·ãGICC_IARã«ã»ãããããï¼
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+
+ä¾å¤çªå·ã¯ï¼ä¾å¤çºçæã®ãã­ã»ããµç¶æ
+ã«å¿ãã¦æ±ºå®ãããï¼ãã¯ã¿ãã¼ãã«ä¸­ã®
+ã¸ã£ã³ãå
+ãªãã»ããæ¯ã«ç°ãªãçªå·ãå²ãæ¯ããã¨ã«ãã¦ããï¼
+
+  ä¾å¤çºçæã®ç¶æ
+             ä¾å¤ã®ç¨®é¡      ä¾å¤çªå· ãä¾å¤ãã¯ã¿å
+é ­ããã®ãªãã»ãã
+  AArch64, EL1t(EL1, SP_EL0)  Synchronous         0        0x0000
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+  AArch64, EL1h(EL1, SP_EL1)  Synchronous         2        0x0200
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+  AArch64, EL0 (EL0, SP_EL0)  Synchronous         4        0x0400
+  AArch64, EL0 (EL0, SP_EL0)  SError              5        0x0580
+  AArch32, EL0 (EL0, SP_EL0)  Synchronous         6        0x0600
+  AArch32, EL0 (EL0, SP_EL0)  SError              7        0x0780
+
+å²è¾¼ã¿ãåãä»ããéï¼åãä»ããå²è¾¼ã¿ã«è¨­å®ãããåªå
+åº¦ããä½ãå²è¾¼ã¿ã
+ç¦æ­¢ããããï¼GICC_RPRããåå¾ããå²è¾¼ã¿è¦å ã®å²è¾¼ã¿åªå
+åº¦ã GICC_PMRã¸
+ã»ãããã¦ããï¼ããã¦ãã³ãã©çµäºå¾ã«å²è¾¼ã¿çºçåã®å²ãè¾¼ã¿åªå
+åº¦ã«æ»ãï¼
+
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+[CPUã¢ã¼ã]
+
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+é¸æãããã¨ãã§ããï¼ãã ãï¼ããä¾å¤ã¬ãã«ã32ãããã¢ã¼ãã§åä½ããå ´åã¯
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+éã»ã­ã¥ã¢ã¢ã¼ããé¸æãããã¨ãã§ããï¼
+
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+
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+
+å²è¾¼ã¿ããã³ä¾å¤ãåãä»ãããã¨ã§çºçåã¨åãã¾ãã¯ããé«ãä¾å¤ã¬ãã«ã¸é·ç§»ããï¼
+ä¸æ¹ï¼åãã¾ãã¯ããä½ãä¾å¤ã¬ãã«ã¸ã®é·ç§»ã¯ä¾å¤ãªã¿ã¼ã³å½ä»¤(eret)ã«ããè¡ãï¼
+
+åä»æã®é·ç§»å
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+å²è¾¼ã¿/ä¾å¤ãªã¿ã¼ã³æã®é·ç§»å
+ã¨ãªãä¾å¤ã¬ãã«ã¯ï¼SPSR_ELxã®ããã2ããã³3ã§
+æå®ããï¼å²è¾¼ã¿/ä¾å¤åä»æï¼PSTATEã®ç¶æ
+ãSPSR_ELxã«ï¼ãªã¿ã¼ã³ã¢ãã¬ã¹ãELR_ELxã«ï¼
+ããããä¿å­ããeretå½ä»¤ã®å®è¡ã«ãããã®æ ¼ç´å¤ãå¾©å¸°ãããããï¼eretå®è¡åã«
+ãããããSPSR_ELxã«ã»ãããã¦ãããã¨ã§æå®ããä¾å¤ã¬ãã«ã¸é·ç§»ãããã¨ãå¯è½ã§ããï¼
+åãã¿ã¤ãã³ã°ã§ä½¿ç¨ã¹ã¿ãã¯ã64ããã/32ãããã¢ã¼ãã®æå®ãè¡ããã¨ãã§ããï¼
+
+QEMU VirtåãSSPã®å®è£
+ã§ã¯EL1ã®ã¿ãä½¿ç¨ããããï¼ä¾å¤ã¬ãã«éã®é·ç§»å¦çã¯è¡ã£ã¦ããªãï¼
+
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+    '11'ã®å ´åï¼EL3
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+è¨­å®å¯è½ãªæå¤§å¤ãè¨­å®ããã¨ï¼å
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+
+ã»ä¾å¤/å²è¾¼ã¿ãåä»ããã¨ï¼åä»ãæã«ã¢ã¯ãã£ããªã¹ã¿ãã¯ä¸ã«ä»¥ä¸ã®ã³
+  ã³ãã­ã¹ããä¿å­ããï¼
+
+   ---------------    <- new SP
+  |   GICC_PMR     |
+   ----------------
+  | å²è¾¼ã¿/ä¾å¤çªå·|
+   ----------------
+  |    ESR_ELx     |
+   ----------------
+  |    ELR_ELx     |
+   ----------------
+  |   SPSR_ELx     |
+   ----------------
+  |      X30       |
+   ----------------
+  |      X29       |
+   ----------------
+  |      ï¼        |
+  |      ï¼        |
+   ----------------
+  |      X1        |
+   ----------------
+  |      X0        |
+   ----------------  <- old SP
+  |                |
+
+
+å²è¾¼ã¿/ä¾å¤çºçæã®ä¸»ãªã·ã¼ã±ã³ã¹ã¯æ¬¡ã®ããã«ãªãï¼é·ç§»å
+ã®ä¾å¤ã¬ãã«ãELxã¨è¡¨ç¾ããï¼
+
+ï¼ãã¼ãã¦ã§ã¢ã®å¦çï¼
+  ã»PSTATEãSPSR_ELxã«ä¿å­ãã
+  ã»ãªã¿ã¼ã³ã¢ãã¬ã¹ãELR_ELxã«ä¿å­ãã
+  ã»PSTATE.{D,A,I,F}ã1ã«ã»ãããã
+  ã»åæä¾å¤ããã³SErrorå²è¾¼ã¿ã®ã¨ãï¼ä¾å¤è¦å æ
+å ±ãESR_ELxã«ä¿å­ãã
+  ã»ã¹ã¿ãã¯ãã¤ã³ã¿ãSP_ELxã«åãæ¿ãã
+  ã»ELxã¸é·ç§»ãã
+
+ï¼ã½ããã¦ã§ã¢ã§ã®å¦çï¼
+  ã»(çºçæã«SP_EL0ãä½¿ç¨ãã¦ããå ´å)ã¹ã¿ãã¯ãå²è¾¼ã¿çºçå(SP_EL0)ã«æ»ã
+  ã»æ±ç¨ã¬ã¸ã¹ã¿(X0-X30)ãã¹ã¿ãã¯ã«ä¿å­
+  ã»SPSR_ELx, ESR_ELx, ELR_ELxãã¹ã¿ãã¯ã«ä¿å­
+  ã»ã¹ã¿ãã¯ãã¤ã³ã¿ã®ã¢ã©ã¤ã¡ã³ããèª¿æ´
+  ã»å²è¾¼ã¿çªå·(GICC_IARããåå¾)ï¼ä¾å¤çªå·(ãªãã»ããæ¯ã«å®ç¾©ããå¤)ãã¹ã¿ãã¯ã«ä¿å­
+  ã»å²è¾¼ã¿çºçåã®å²è¾¼ã¿åªå
+åº¦ãã¹ã¯ãã¹ã¿ãã¯ã«ä¿å­
+  ã»GICC_PMRã«åãä»ããå²è¾¼ã¿ã®å²è¾¼ã¿åªå
+åº¦ãã»ãã
+  ã»å²è¾¼ã¿/ä¾å¤ãã¹ãã«ã¦ã³ã¿ã®ã¤ã³ã¯ãªã¡ã³ã
+  ã»(å²è¾¼ã¿ã®å ´å)CPUã­ãã¯è§£é¤
+  ã»ãã¯ã¿ãã¼ãã«ãèª­ã¿è¾¼ã¿ãã³ãã©ãå®è¡ãã
+
+âä¾å¤/å²è¾¼ã¿ããã®ãªã¿ã¼ã³
+
+ï¼ã½ããã¦ã§ã¢ã§ã®å¦çï¼
+  ã»CPUã­ãã¯ç¶æ
+ã¸ç§»è¡
+  ã»å²è¾¼ã¿/ä¾å¤ãã¹ã¨ã«ã¦ã³ã¿ã®ãã¯ãªã¡ã³ã
+  ã»GICC_PMRã«å²è¾¼ã¿çºçåã®åªå
+åº¦ãã¹ã¯ãæ»ã
+  ã»ã¹ã¿ãã¯ãã¤ã³ã¿ã®ã¢ã©ã¤ã¡ã³ãèª¿æ´åãæ»ã
+  ã»æ»ãå
+ã®ã³ã³ãã­ã¹ããã·ã¹ãã ç¶æ
+ã«å¿ãã¦å²è¾¼ã¿/ä¾å¤çºçå
+ã¸ãªã¿ã¼ã³
+    ã¾ãã¯é
+å»¶ãã£ã¹ããããå®è¡ãã
+  ã»ELR_ELxã«æ»ãå
+ã¢ãã¬ã¹ï¼SPSR_ELxã«ãã­ã»ããµç¶æ
+ããããã
+    ã»ããããã¦ããç¶æ
+ã§eretå½ä»¤ãå®è¡ãï¼å²è¾¼ã¿/ä¾å¤ãããªã¿ã¼ã³
+
+
+âOSã®å®è£
+
+
+1.ã³ã¢ä¾å­é¨åç§°: arm64
+
+ARMv8 ã§ã¯ï¼64ãããã¢ã¼ã(AArch64)ããã³32ãããã¢ã¼ã(AArch32)ã®ä¸¡æ¹ããµãã¼ãããã
+æ¬å®è£
+ã¯64ãããã¢ã¼ãã®ã¿ããµãã¼ããããã¨ãæç¤ºãããããã­ã»ããµä¾å­é¨åç§°ã arm64 ã¨ãã
+
+2. ä¾å¤ã¢ã¼ãã®ä½¿ãåã
+
+æ¬å®è£
+ã§ã¯ã¿ã¹ã¯ã³ã³ãã­ã¹ãï¼éã¿ã¹ã¯ã³ã³ãã­ã¹ãããããä¾å¤ã¬ãã«1(EL1)ã§åä½ããï¼
+ã¿ã¹ã¯ã³ã³ãã­ã¹ããEL0ã§åä½ããæ¡ãèããããï¼ãã®å ´åã¯å²è¾¼ã¿/ä¾å¤ã®åºå£å¦çã«ããã¦
+é
+å»¶ãã£ã¹ãããã®åã«ä¾å¤ã¬ãã«ã®åãæ¿ããå¿
+è¦ã¨ãªãï¼
+
+3.ãã£ã¹ãããã£ã®å®è¡ã¢ã¼ã
+
+æ¬å®è£
+ã§ã¯ãã¹ã¦ä¾å¤ã¬ãã«1ã§åä½ããããï¼ãã£ã¹ãããã£ã¯ä¾å¤ã¬ãã«1(EL1)ã§åä½ããï¼
+
+
+4.ã¹ã¿ãã¯ã®ä½¿ãåã
+
+SSPã§ã¯ã¿ã¹ã¯ã³ã³ãã­ã¹ãï¼éã¿ã¹ã¯ã³ã³ãã­ã¹ãå
+±ã«ä¸ã¤ã®ã¹ã¿ãã¯ãå
+±ç¨ããï¼
+æ¬å®è£
+ã§ã¯SP_ELxãä½¿ç¨ãã¦ããï¼
+ãã®ä»ã«SP_EL0ãä½¿ç¨ããå®è£
+ãèããããï¼ãã®å ´åã¯å²è¾¼ã¿/ä¾å¤ã®å
+¥å£å¦çã«ã¦
+ã¬ã¸ã¹ã¿ãä¿å­ããåã«SP_EL0ã¸ã®ã¹ã¿ãã¯åãæ¿ããè¡ãï¼
+
+5.ã³ã³ãã­ã¹ãã®å¤å®
+
+å²è¾¼ã¿/ä¾å¤ã®ãã¹ãåæ°ãä¿æããå¤æ°(intnest)ã0ãªãã¿ã¹ã¯ã¿ã¹ã¯ã³ã³ãã­ã¹ãï¼
+1ä»¥ä¸ãªãéã¿ã¹ã¯ã³ã³ãã­ã¹ãã¨ããï¼
+ã³ã³ãã­ã¹ãæ¯ã«ä¾å¤ã¬ãã«ãåããå®è£
+ãåãå ´åã¯PSTATEã®ããã2ããã³3ã§
+ä¾å¤ã¬ãã«ãèª­ã¿åºããã¨ã«ããå¤å¥ããã¨ããæ¹æ³ãèããããï¼
+æ¬å®è£
+ã§ã¯ã³ã³ãã­ã¹ãã«ãããåãä¾å¤ã¬ãã«ãä½¿ç¨ãï¼ãã­ã»ããµã®
+ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿ã§ã¯å¤å¥ãã§ããªãããå¤æ°ã§å¤å¥ããï¼
+
+6. CPUã­ãã¯
+
+CPUã­ãã¯PSTATE.Iã«ããCPUã­ãã¯ãå®ç¾ããï¼
+
+7. å²è¾¼ã¿ã­ãã¯ã¨CPUä¾å¤ã®é¢ä¿
+
+FIQãã«ã¼ãã«ç®¡çå¤ã®å²è¾¼ã¿ã¨ããããï¼å²è¾¼ã¿ã­ãã¯ã¯PSTATE.Iã«å ãã¦
+PSTATE.Fãç¨ãã¦å®ç¾ããï¼ãã ãï¼ãã©ã°ããäºãã«ç¬ç«ãããããï¼
+å²è¾¼ã¿ã­ãã¯ç¶æ
+ã®è¨­å®/è§£é¤ã®éã¯ï¼ã­ãã¯åã«CPUã­ãã¯ãã©ã°(=PSTATE.I)ã®
+ç¶æ
+ãä¿å­ãï¼è§£é¤åã«å
+ã®ç¶æ
+ã«æ»ãããã«ãã¦ããï¼
+
+8. å¤é¨åªå
+åº¦ã¨å
+é¨åªå
+åº¦
+
+å¤é¨åªå
+åº¦ã¨ã¯APIã§æå®ããå²è¾¼ã¿åªå
+åº¦(PRIå)ã®ãã¨ã§ããï¼å¤ãå°ãã
+ã»ã©åªå
+åº¦ãé«ãï¼å²è¾¼ã¿ãã³ãã©ã«ã¯ï¼-1ããé£ç¶ããè² ã®å¤ãè¨­å®å¯è½ã§
+ããï¼GICã®å ´åï¼å
+é¨åªå
+åº¦ã¯ï¼GICC_PMRã¬ã¸ã¹ã¿ã«è¨­å®ããå¤ã§ããï¼
+å¤é¨åªå
+åº¦ã¨å
+é¨åªå
+åº¦ã®å¤æã¯ä»¥ä¸ã®ãã¯ã­ã§è¡¨ç¾ãããï¼
+
+/* å¤é¨è¡¨ç¾ã¸ã®å¤æ */
+#define EXT_IPM(pri) \
+                        (((PRI)((pri) >> GIC_PRI_SHIFT)) - (GIC_PRI_LEVEL - 1))
+
+/* å
+é¨è¡¨ç¾ã¸ã®å¤æ */
+#define INT_IPM(ipm) \
+                        (((uint_t)((ipm) + (GIC_PRI_LEVEL - 1))) << GIC_PRI_SHIFT)
+
+ããã§GIC_PRI_LEVELã¯ãµãã¼ãããå²è¾¼ã¿åªå
+åº¦ã®æ°ï¼GIC_PRI_SHIFTã¯GICC_PMRã¬ã¸ã¹ã¿å
+
+ã®ï¼å
+é¨åªå
+åº¦ã®å¤ãæ ¼ç´ãããä½ç½®ï¼ããã0ããã®ãªãã»ããï¼ãè¡¨ãï¼
+
+
+9. ã«ã¼ãã«ç®¡çå
+ã®æé«åªå
+åº¦(CPUã­ãã¯ç¶æ
+ã§ã®åªå
+åº¦ãã¹ã¯)
+
+GICã®å ´åï¼ã«ã¼ãã«ç®¡çå
+ã®å²è¾¼ã¿ã®æé«åªå
+åº¦ã¯è¨­å®å¯è½ãªå¤é¨åªå
+åº¦ã®æé«å¤ã¨åãã¨ããï¼
+
+
+ä»¥ä¸ï¼
Index: /ssp_rpi3/trunk/arch/arm64_gcc/common/core_kernel.h
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/common/core_kernel.h	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/common/core_kernel.h	(revision 384)
@@ -0,0 +1,88 @@
+/*
+ *  TOPPERS/SSP Kernel
+ *      Smallest Set Profile Kernel
+ *
+ *  Copyright (C) 2008 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2018,2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  @(#) $Id$
+ */
+
+/*
+ *    kernel.hã®ãã­ã»ããµä¾å­é¨ï¼ARMv8-Aç¨ï¼
+ *
+ *  ãã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«ã¯ï¼target_kernel.hï¼ã¾ãã¯ï¼ããããã¤ã³ã¯
+ *  ã«ã¼ãããããã¡ã¤ã«ï¼ã®ã¿ããã¤ã³ã¯ã«ã¼ããããï¼ä»ã®ãã¡ã¤ã«ãã
+ *  ç´æ¥ã¤ã³ã¯ã«ã¼ããã¦ã¯ãªããªãï¼
+ */
+
+#ifndef TOPPERS_CORE_KERNEL_H
+#define TOPPERS_CORE_KERNEL_H
+
+/*
+ *  ã¿ã¤ã ãã£ãã¯ã®å®ç¾©
+ */
+#ifndef TIC_NUME
+    #define TIC_NUME                        1U              /* ã¿ã¤ã ãã£ãã¯ã®å¨æã®åå­ */
+#endif
+#ifndef TIC_DENO
+    #define TIC_DENO                        1U              /* ã¿ã¤ã ãã£ãã¯ã®å¨æã®åæ¯ */
+#endif
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ *  ã¹ã¿ãã¯ã®å
+ *    ã¹ã¿ãã¯ãã¤ã³ã¿ã®ã¢ã©ã¤ã¡ã³ãã¯ãã¤ã³ã¿ãµã¤ãºã®åã«ããå¿
+è¦ããã
+ */
+#define TOPPERS_STK_T  uint128_t
+
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_CORE_KERNEL_H */
Index: /ssp_rpi3/trunk/arch/arm64_gcc/common/core_kernel.trb
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/common/core_kernel.trb	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/common/core_kernel.trb	(revision 384)
@@ -0,0 +1,75 @@
+# -*- coding: utf-8 -*-
+#
+#   TOPPERS/SSP Kernel
+#       Toyohashi Open Platform for Embedded Real-Time Systems/
+#       Advanced Standard Profile Kernel
+# 
+#   Copyright (C) 2015 by FUJI SOFT INCORPORATED, JAPAN
+#   Copyright (C) 2015,2016 by Embedded and Real-Time Systems Laboratory
+#               Graduate School of Information Science, Nagoya Univ., JAPAN
+#   Copyright (C) 2017,2019 by Naoki Saito
+#              Nagoya Municipal Industrial Research Institute, JAPAN
+#
+# 
+#   ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+#   ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+#   å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+#   (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+#       æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+#       ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+#   (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+#       è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+#       ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#   (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+#       ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+#       ã¨ï¼
+#     (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+#         ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+#     (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+#         å ±åãããã¨ï¼
+#   (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+#       å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+#       ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+#       ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+#       å
+è²¬ãããã¨ï¼
+# 
+#   æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+#   ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+#   ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+#   ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+#   ã®è²¬ä»»ãè² ããªãï¼
+# 
+#   $Id$
+# 
+
+#
+#  ãã¹2ã®çæã¹ã¯ãªããã®ã³ã¢ä¾å­é¨ï¼ARMv8-Aç¨ï¼
+#
+
+#
+#  ãã§ãã¯æ¹æ³ã®æå®
+#
+$CHECK_STKSZ_ALIGN = 16
+
+#
+#  ã¿ã¼ã²ããéä¾å­é¨ã®ã¤ã³ã¯ã«ã¼ã
+#
+IncludeTrb("kernel/kernel.trb")
+
+$kernelCfgC.comment_header("Target-dependent Definitions (ARMv8-A)")
Index: /ssp_rpi3/trunk/arch/arm64_gcc/common/core_rename.def
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/common/core_rename.def	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/common/core_rename.def	(revision 384)
@@ -0,0 +1,17 @@
+# core_config.c
+intnest
+core_initialize
+core_terminate
+call_int_handler
+call_exc_handler
+call_fiq_handler
+default_exc_handler
+default_int_handler
+
+# core_support.S
+start_dispatch
+call_exit_kernel
+ret_int
+ret_exc
+ret_fiq
+vectors
Index: /ssp_rpi3/trunk/arch/arm64_gcc/common/core_rename.h
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/common/core_rename.h	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/common/core_rename.h	(revision 384)
@@ -0,0 +1,55 @@
+/* This file is generated from core_rename.def by genrename. */
+
+#ifndef TOPPERS_CORE_RENAME_H
+#define TOPPERS_CORE_RENAME_H
+
+/*
+ *  core_config.c
+ */
+#define intnest						_kernel_intnest
+#define core_initialize				_kernel_core_initialize
+#define core_terminate				_kernel_core_terminate
+#define call_int_handler			_kernel_call_int_handler
+#define call_exc_handler			_kernel_call_exc_handler
+#define call_fiq_handler			_kernel_call_fiq_handler
+#define default_exc_handler			_kernel_default_exc_handler
+#define default_int_handler			_kernel_default_int_handler
+
+/*
+ *  core_support.S
+ */
+#define start_dispatch				_kernel_start_dispatch
+#define call_exit_kernel			_kernel_call_exit_kernel
+#define ret_int						_kernel_ret_int
+#define ret_exc						_kernel_ret_exc
+#define ret_fiq						_kernel_ret_fiq
+#define vectors						_kernel_vectors
+
+#ifdef TOPPERS_LABEL_ASM
+
+/*
+ *  core_config.c
+ */
+#define _intnest					__kernel_intnest
+#define _core_initialize			__kernel_core_initialize
+#define _core_terminate				__kernel_core_terminate
+#define _call_int_handler			__kernel_call_int_handler
+#define _call_exc_handler			__kernel_call_exc_handler
+#define _call_fiq_handler			__kernel_call_fiq_handler
+#define _default_exc_handler		__kernel_default_exc_handler
+#define _default_int_handler		__kernel_default_int_handler
+
+/*
+ *  core_support.S
+ */
+#define _start_dispatch				__kernel_start_dispatch
+#define _call_exit_kernel			__kernel_call_exit_kernel
+#define _ret_int					__kernel_ret_int
+#define _ret_exc					__kernel_ret_exc
+#define _ret_fiq					__kernel_ret_fiq
+#define _vectors					__kernel_vectors
+
+#endif /* TOPPERS_LABEL_ASM */
+
+
+#endif /* TOPPERS_CORE_RENAME_H */
Index: /ssp_rpi3/trunk/arch/arm64_gcc/common/core_sil.h
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/common/core_sil.h	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/common/core_sil.h	(revision 384)
@@ -0,0 +1,120 @@
+/*
+ *  TOPPERS Software
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *
+ *  Copyright (C) 2008 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2018,2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  @(#) $Id$
+ */
+
+/*
+ *   sil.hã®ã³ã¢ä¾å­é¨ï¼ARMv8-Aç¨ï¼
+ */
+
+#ifndef TOPPERS_CORE_SIL_H
+#define TOPPERS_CORE_SIL_H
+
+#include "arm64.h"
+
+/*
+ *  ã¨ã³ãã£ã¢ã³ã®å®ç¾©
+ */
+#define SIL_ENDIAN_LITTLE
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ *  å
+¨å²è¾¼ã¿ã­ãã¯ãã©ã°ã®ã»ãã(NMIãé¤ããã¹ã¦ã®å²è¾¼ã¿ã®ç¦æ­¢)
+ */
+Inline bool_t
+TOPPERS_disint(void)
+{
+    bool_t locked;
+
+    if(aarch64_sense_daif_irq()) {
+        aarch64_set_daif_f();
+        locked = true;
+    }
+    else {
+        aarch64_set_daif_if();
+        locked = false;
+    }
+
+    return (locked);
+}
+
+/*
+ *  å
+¨å²è¾¼ã¿ã­ãã¯ãã©ã°ã®è§£é¤
+ */
+Inline void
+TOPPERS_enaint(uint32_t locked)
+{
+    if(locked) {
+        aarch64_clear_daif_f();
+    }
+    else {
+        aarch64_clear_daif_if();
+    }
+    aarch64_exit_critical();
+}
+
+/*
+ *  å
+¨å²è¾¼ã¿ã­ãã¯ç¶æ
+ã®å¶å¾¡
+ */
+#define SIL_PRE_LOC      bool_t  TOPPERS_locked
+#define SIL_LOC_INT()    ((TOPPERS_locked = TOPPERS_disint()))
+#define SIL_UNL_INT()    (TOPPERS_enaint(TOPPERS_locked))
+
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_CORE_SIL_H */
Index: /ssp_rpi3/trunk/arch/arm64_gcc/common/core_stddef.h
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/common/core_stddef.h	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/common/core_stddef.h	(revision 384)
@@ -0,0 +1,82 @@
+/*
+ *  TOPPERS Software
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *
+ *  Copyright (C) 2008 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2018,2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  @(#) $Id$
+ */
+
+/*
+ *  t_stddef.hã®ã³ã¢ä¾å­é¨ï¼ARMv8-Aç¨ï¼
+ *
+ *  ãã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«ã¯ï¼target_stddef.hï¼ã¾ãã¯ï¼ããããã¤ã³ã¯
+ *  ã«ã¼ãããããã¡ã¤ã«ï¼ã®ã¿ããã¤ã³ã¯ã«ã¼ããããï¼ä»ã®ãã¡ã¤ã«ãã
+ *  ç´æ¥ã¤ã³ã¯ã«ã¼ããã¦ã¯ãªããªãï¼
+ */
+
+#ifndef TOPPERS_CORE_STDDEF_H
+#define TOPPERS_CORE_STDDEF_H
+
+/*
+ *  ã¿ã¼ã²ãããè­å¥ããããã®ãã¯ã­ã®å®ç¾©
+ */
+#define TOPPERS_ARM64           /* ã³ã¢ç¥ç§° */
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ *  ãã¼ã¿åã®å®ç¾©
+ */
+typedef __int128_t    int128_t;
+typedef __uint128_t   uint128_t;
+
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_CORE_STDDEF_H */
Index: /ssp_rpi3/trunk/arch/arm64_gcc/common/core_support.S
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/common/core_support.S	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/common/core_support.S	(revision 384)
@@ -0,0 +1,423 @@
+/*
+ *  TOPPERS/SSP Kernel
+ *      Smallest Set Profile Kernel
+ *
+ *  Copyright (C) 2008 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2018,2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ */
+
+/*
+ *  ãã­ã»ããµä¾å­ã¢ã¸ã¥ã¼ã« ã¢ã»ã³ããªè¨èªé¨ï¼ARM64ç¨ï¼
+ */
+
+#define TOPPERS_MACRO_ONLY
+#define UINT_C(val)	(val)		/* uint_tåã®å®æ°ãä½ããã¯ã­ */
+#define ULONG_C(val)	(val)		/* ulong_tåã®å®æ°ãä½ããã¯ã­ */
+#define UINT64_C(val)   (val)           /* uint64_tåã®å®æ°ãä½ããã¯ã­ */
+#define CAST(type, val)	(val)		/* åã­ã£ã¹ããè¡ããã¯ã­ */
+
+#include "kernel_impl.h"
+
+/*
+ *  ãã£ã¹ãããã£ã®åä½éå§
+ */
+    .text
+    .align    2
+    .globl    start_dispatch
+    .type     start_dispatch, function
+start_dispatch:
+    /*
+     *  ãã®ã«ã¼ãã³ã¯ï¼ã«ã¼ãã«èµ·åæã«ï¼ä»¥ä¸ã®ç¶æ
+ã§å¼ã³åºãããï¼
+     *    ã»ãã¹ã¦ã®å²è¾¼ã¿ãç¦æ­¢ããç¶æ
+å²è¾¼ã¿ã­ãã¯ç¶æ
+ã¨åç­ï¼
+     *    ã»å²è¾¼ã¿åªå
+åº¦ãã¹ã¯å
+¨è§£é¤ç¶æ
+
+     *
+     *  ããã§ã¯ dispatcher ãå¼ã³åºãåã®åæè¨­å®ãè¡ãï¼
+     *  (1) ã·ã¹ãã ç¶æ
+ã®åæåï¼ä»¥ä¸ã®ç¶æ
+ã¸ç§»è¡ããï¼
+     *    ã»å
+¨å²è¾¼ã¿ã­ãã¯è§£é¤ç¶æ
+(ã«ã¼ãã«ç®¡çå¤ã®å²è¾¼ã¿è¨±å¯)
+     *    ã»CPUã­ãã¯ç¶æ
+(ã«ã¼ãã«ç®¡çã®å²è¾¼ã¿ç¦æ­¢)
+     *    ã»å²è¾¼ã¿åªå
+åº¦ãã¹ã¯å
+¨è§£é¤ç¶æ
+
+     *    ã»ãã£ã¹ãããè¨±å¯ç¶æ
+
+     *
+     *    (1-1) å²è¾¼ã¿åªå
+åº¦ãã¹ã¯ã¯åæãããã§ã«
+     *          ã¢ãã«ä¸ã®ï¼å²è¾¼ã¿åªå
+åº¦ãã¹ã¯å
+¨è§£é¤ç¶æ
+ã«ãªã£ã¦ããï¼
+     *    (1-2) ãã£ã¹ãããç¦æ­¢ãã©ã°ã¯ task_initialize ã§ disdsp ã false ã«
+     *          åæåãã¦ããããï¼ãã§ã«ãã£ã¹ãããè¨±å¯ç¶æ
+ã«ãªã£ã¦ããï¼
+     *    (1-3) ããã§ã¯å²è¾¼ã¿ã­ãã¯ç¶æ
+ãè§£é¤ãï¼CPUã­ãã¯ç¶æ
+ã®è¨­å®ãè¡ãï¼
+     *
+     *  (2) ã¹ã¿ãã¯ãã¤ã³ã¿ã®åæå
+     *      start_dispatch ãå¼ã³åºãããã¨ï¼ä»å¾ããã«æ»ã£ã¦ãããã¨ã¯ãªããã
+     *      ã¹ã¿ãã¯ãã¤ã³ã¿ãããã§åæåããï¼
+     */
+    ldr x0, =_kernel_istkpt // setup stack
+    ldr x0, [x0]
+    mov sp, x0
+
+    // F ãã©ã°ãã¯ãªã¢(å²è¾¼ã¿ã­ãã¯è§£é¤ï¼CPUã­ãã¯ç¸å½)
+    msr   daifclr, #AARCH64_DAIF_FIQ
+
+    // dispatcherå¼ã³åºã
+    b      dispatcher
+
+/*
+ *  ã«ã¼ãã«ã®çµäºå¦çã®å¼åºã
+ *
+ *  ã¹ã¿ãã¯ãéã¿ã¹ã¯ã³ã³ãã­ã¹ãç¨ã«åãæ¿ãï¼
+ *
+ */
+    .text
+    .align   2
+    .globl   call_exit_kernel
+    .type    call_exit_kernel, function
+call_exit_kernel:
+    /*
+     *  ã¹ã¿ãã¯ãã¤ã³ã¿ã®åæå
+     */
+    ldr    x0, =_kernel_istkpt
+    ldr    x0, [x0]
+    mov    sp, x0
+
+    // å
+¨ã¦ã®ä¾å¤ããã¹ã¯(å
+¨å²è¾¼ã¿ã­ãã¯ç¸å½)
+    msr    daifset, #(AARCH64_DAIF_ALL)
+
+    b      exit_kernel       /* ã«ã¼ãã«ã®çµäºå¦çãå¼ã¶ */
+
+
+/*
+ * å²è¾¼ã¿/ä¾å¤ã³ã³ãã­ã¹ãä¿å­å¦ç
+ */
+.macro __save_context
+    /*
+     *  x0 - x29 ã®ä¿å­(x0,x1ãã¢ããx28, x29ã¾ã§)
+     */
+    stp	   x1, x0, [sp, #-16]!
+    stp	   x3, x2, [sp, #-16]!
+    stp	   x5, x4, [sp, #-16]!
+    stp	   x7, x6, [sp, #-16]!
+    stp	   x9, x8, [sp, #-16]!
+    stp	   x11, x10, [sp, #-16]!
+    stp	   x13, x12, [sp, #-16]!
+    stp	   x15, x14, [sp, #-16]!
+    stp	   x17, x16, [sp, #-16]!
+    stp	   x19, x18, [sp, #-16]!
+    stp	   x21, x20, [sp, #-16]!
+    stp	   x23, x22, [sp, #-16]!
+    stp	   x25, x24, [sp, #-16]!
+    stp	   x27, x26, [sp, #-16]!
+    stp	   x29, x28, [sp, #-16]!
+
+    /*
+     * spsr_el1, x30ããã¢ã§ä¿å­
+     */
+    mrs	   x21, spsr_el1
+    stp	   x21, x30, [sp, #-16]!
+
+    /*
+     * esr_el1, elr_el1 ããã¢ã§ä¿å­
+     */
+    mrs	   x21, esr_el1
+    mrs	   x22, elr_el1
+    stp	   x21, x22, [sp, #-16]!
+
+    /*
+     * è¿½å ã®æ ¼ç´é åãç¢ºä¿ããããï¼SPãæ¸ç®ãã¦ãã
+     */
+    sub     sp, sp, #16
+.endm
+
+/*
+ * ã³ã³ãã­ã¹ãå¾©å¸°å¦ç
+ */
+.macro __restore_context
+    /*
+     * ã¹ã¿ãã¯ã«ä¿å­ããä¸é¨ãã¼ã¿ã®ç ´æ£
+     */
+    mov    x1, #16
+    add	   sp, sp, x1
+    /*
+     * ELR ã®å¾©å
+(ESRã¯ç ´æ£)
+     */
+    ldp    x21, x22, [sp], #16
+    msr    elr_el1, x22
+    /*
+     * SPSR/x30 ã®å¾©å
+
+     */
+    ldp    x21, x30, [sp], #16
+    msr    spsr_el1, x21
+
+    /*
+     * x0 - x29 ã®å¾©å
+
+     */
+    ldp    x29, x28, [sp], #16
+    ldp    x27, x26, [sp], #16
+    ldp    x25, x24, [sp], #16
+    ldp    x23, x22, [sp], #16
+    ldp    x21, x20, [sp], #16
+    ldp    x19, x18, [sp], #16
+    ldp    x17, x16, [sp], #16
+    ldp    x15, x14, [sp], #16
+    ldp    x13, x12, [sp], #16
+    ldp    x11, x10, [sp], #16
+    ldp    x9, x8, [sp], #16
+    ldp    x7, x6, [sp], #16
+    ldp    x5, x4, [sp], #16
+    ldp    x3, x2, [sp], #16
+    ldp    x1, x0, [sp], #16
+.endm
+
+/*
+ *  (ã«ã¼ãã«ç®¡çå¤ã®)CPUä¾å¤/FIQã®åºå£å¦ç
+ */
+    .text
+    .align 2
+    .global ret_exc
+    .global ret_fiq
+ret_exc:
+ret_fiq:
+    __restore_context    // ã¬ã¸ã¹ã¿å¾©å¸°
+    eret
+
+/*
+ *  å²è¾¼ã¿/(ã«ã¼ãã«ç®¡çã®)CPUä¾å¤ã®åºå£å¦ç
+ *    åæï¼CPUã­ãã¯ç¶æ
+, ãã¹ãã«ã¦ã³ã¿ãã¯ãªã¡ã³ãæ¸ã¿
+ */
+    .text
+    .align 2
+    .global ret_int
+ret_int:
+    // æ»ãå
+ã®ã³ã³ãã­ã¹ããç¢ºèªãï¼å¤æ®µå²è¾¼ã¿ãªããªã¿ã¼ã³
+    ldr    x1, =_kernel_intnest
+    ldrb   w3, [x1]
+    cbnz   w3, int_return
+
+ret_int_2:        // åæ®µã®å²è¾¼ã¿ã®å ´å
+    // reqflg ã false ãªãå¼ã³åºãå
+ã¸æ»ã
+    ldr    x0, =reqflg
+    ldr    w1, [x0]
+    cbz    w1, int_return
+
+ret_int_3:        // reqflg ã true ã®å ´å
+    mov    w1, #0        // reqflg = false
+    str    w1, [x0]
+
+    // ãã£ã¹ãããç¦æ­¢ãªãå¼ã³åºãå
+ã¸æ»ã
+    ldr    x0, =disdsp
+    ldr    w1, [x0]
+    cbnz   w1, int_return
+
+    /*
+     *  é
+å»¶ãã£ã¹ããã
+     *    search_schedtsk ã®è¿å¤(x0)ãå¼æ°ã¨ãã¦ run_task ãå¼ã³åºã
+     */
+    bl    search_schedtsk
+    bl    run_task
+
+    /*
+     *  å¼ã³åºãå
+ã¸ãªã¿ã¼ã³
+     */
+int_return:
+    __restore_context    // ã¬ã¸ã¹ã¿å¾©å¸°
+    eret
+
+/*
+ *  å²è¾¼ã¿ãã¯ã¿
+ *    æåã«å²è¾¼ã¿çºçåã®ã¹ã¿ãã¯ã«æ»ãã¦ããã¬ã¸ã¹ã¿ãä¿å­ãã
+ *    ãã¼ãã¦ã§ã¢ã«ãã£ã¦PSTATE.{I,F} ãã»ããæ¸ã§ãããã¨ãåæã¨ãã
+ */
+    .text
+    .global vectors
+    .align 11
+vectors:
+    /*
+     *  From EL1t
+     */
+
+    // Sync EL1
+    msr    spsel,  #0               // ä¾å¤çºçåã®ã¹ã¿ãã¯(SP_EL0)ã«æ»ã
+    __save_context
+    mov    x22, #0                  // ä¾å¤çªå·ãx22ã«ã»ãã
+    b      chip_exc_entry
+
+    // IRQ EL1
+    .align 7
+    msr    spsel,   #0              // ä¾å¤çºçåã®ã¹ã¿ãã¯(SP_EL0)ã«æ»ã
+    __save_context
+    b      chip_int_entry
+
+    // FIQ EL1
+    .align 7
+    msr    spsel, #0                // ä¾å¤çºçåã®ã¹ã¿ãã¯(SP_EL0)ã¸æ»ã
+    __save_context
+    b      chip_fiq_entry
+
+    // SError EL1
+    .align 7
+    msr    spsel, #0                // ä¾å¤çºçåã®ã¹ã¿ãã¯(SP_EL0)ã¸æ»ã
+    __save_context
+    mov    x22, #1                  // ä¾å¤çªå·ãx22ã«ã»ãã
+    b      chip_exc_entry
+
+    /*
+     *  From EL1h
+     */
+
+    // Sync EL1
+    .align 7
+    __save_context
+    mov    x22, #2                  // ä¾å¤çªå·ãx22ã«ã»ãã
+    b      chip_exc_entry
+
+    // IRQ EL1
+    .align 7
+    __save_context
+    b      chip_int_entry
+
+    // FIQ EL1
+    .align 7
+    __save_context
+    b      chip_fiq_entry
+
+    // Error EL1
+    .align 7
+    __save_context
+    mov    x22, #3                  // ä¾å¤çªå·ãx22ã«ã»ãã
+    b      chip_exc_entry
+
+    /*
+     *  From EL0t
+     */
+
+    // Sync EL0
+    .align 7
+    msr    spsel,  #0               // ä¾å¤çºçåã®ã¹ã¿ãã¯(SP_EL0)ã«æ»ã
+    __save_context
+    mov    x22, #4                  // ä¾å¤çªå·ãx22ã«ã»ãã
+    b      chip_exc_entry
+
+   // IRQ EL0
+    .align 7
+    msr    spsel,  #0               // ä¾å¤çºçåã®ã¹ã¿ãã¯(SP_EL0)ã«æ»ã
+    __save_context
+    b      chip_int_entry
+
+    // FIQ EL0
+    .align 7
+    msr    spsel,  #0               // ä¾å¤çºçåã®ã¹ã¿ãã¯(SP_EL0)ã«æ»ã
+    __save_context
+    b      chip_fiq_entry
+
+    // Error EL0
+    .align 7
+    msr    spsel,  #0               // ä¾å¤çºçåã®ã¹ã¿ãã¯(SP_EL0)ã«æ»ã
+    __save_context
+    mov    x22, #5                  // ä¾å¤çªå·ãx22ã«ã»ãã
+    b      chip_exc_entry
+
+    /*
+     *  From EL0 using AArch32
+     */
+
+    // AArch32 sync
+    .align 7
+    msr    spsel,  #0               // ä¾å¤çºçåã®ã¹ã¿ãã¯(SP_EL0)ã«æ»ã
+    __save_context
+    mov    x22, #6                  // ä¾å¤çªå·ãx22ã«ã»ãã
+    b      chip_exc_entry
+
+    // AArch32 IRQ
+    .align 7
+    msr    spsel,  #0               // ä¾å¤çºçåã®ã¹ã¿ãã¯(SP_EL0)ã«æ»ã
+    __save_context
+    b      chip_int_entry
+
+    // AArch32 FIQ
+    .align 7
+    msr    spsel,  #0               // ä¾å¤çºçåã®ã¹ã¿ãã¯(SP_EL0)ã«æ»ã
+    __save_context
+    b      chip_fiq_entry
+
+    // AArch32 Error
+    .align 7
+    msr    spsel,  #0               // ä¾å¤çºçåã®ã¹ã¿ãã¯(SP_EL0)ã«æ»ã
+    __save_context
+    mov    x22, #7                  // ä¾å¤çªå·ãx22ã«ã»ãã
+    b      chip_exc_entry
Index: /ssp_rpi3/trunk/arch/arm64_gcc/common/core_test.h
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/common/core_test.h	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/common/core_test.h	(revision 384)
@@ -0,0 +1,73 @@
+/*
+ *  TOPPERS/SSP Kernel
+ *      Smallest Set Profile Kernel
+ *
+ *  Copyright (C) 2008 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2018,2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  @(#) $Id$
+ */
+
+/*
+ *  ãã¹ããã­ã°ã©ã ã®ãããä¾å­å®ç¾©ï¼ARMv8-Aç¨ï¼
+ */
+
+#ifndef TOPPERS_CORE_TEST_H
+#define TOPPERS_CORE_TEST_H
+
+/*
+ *  ã³ã¢ã§å
+±éãªå®ç¾©
+ */
+
+#define CPUEXC1    2
+#define RAISE_CPU_EXCEPTION     { unsigned int r; r=*((volatile unsigned int*)0x0000000000000000); r++; }
+#define CANNOT_RETURN_CPUEXC
+
+#endif /* TOPPERS_CORE_TEST_H */
Index: /ssp_rpi3/trunk/arch/arm64_gcc/common/core_timer.c
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/common/core_timer.c	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/common/core_timer.c	(revision 384)
@@ -0,0 +1,198 @@
+/*
+ *  TOPPERS/SSP Kernel
+ *      Smallest Set Profile Kernel
+ *
+ *  Copyright (C) 2013-2015 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2018,2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  $Id$
+ */
+
+/*
+ *  ã¿ã¤ããã©ã¤ãï¼Generic Timerï¼
+ */
+#include "kernel_impl.h"
+#include "time_event.h"
+#include "target_timer.h"
+
+/*
+ *  ã¿ã¤ãã®å¨æ³¢æ°(åä½: kHz)
+ */
+static uint32_t timer_clock;
+
+/*
+ *  ã¿ã¤ãã®è¨­å®å¤(æ¯è¼å¯¾è±¡ã¨ããå¤)
+ */
+static uint64_t timer_cval;
+
+/*
+ *  ã¿ã¤ãã®éå§
+ */
+Inline void
+target_timer_start(void)
+{
+    uint32_t cntp_ctl;
+
+    cntp_ctl = clock_read_ctrl();
+    cntp_ctl |= ((uint32_t)CNTP_CTL_ENABLE);
+    clock_write_ctrl(cntp_ctl);
+}
+
+/*
+ *  ã¿ã¤ãã®åæ­¢
+ */
+Inline void
+target_timer_stop(void)
+{
+    uint32_t cntp_ctl;
+    cntp_ctl = clock_read_ctrl();
+    cntp_ctl &= ~CNTP_CTL_ENABLE;
+    clock_write_ctrl(cntp_ctl);
+}
+
+/*
+ *  ã¿ã¤ãã®èµ·åå¦ç
+ */
+void
+target_timer_initialize(intptr_t exinf)
+{
+    uint32_t cyc;
+    uint32_t timer_clock_hz;
+
+    /*
+     *  ã¿ã¤ãã®åæ­¢
+     */
+    target_timer_stop();
+
+    /*
+     *  ããªã¹ã±ã¼ã©(=2^31 --> divider=1)
+     */
+    sil_wrw_mem((uint32_t *)(0x40000008), 0x80000000);
+
+    timer_clock_hz = get_timer_freq();   // 19.2MHz
+    timer_clock = timer_clock_hz / 1000;
+
+    /*
+     *  1ãã£ãã¯ã®ã¯ã­ãã¯æ°
+     */
+    cyc = (timer_clock * (TIC_NUME) / (TIC_DENO));
+
+    /*
+     *  ã¿ã¤ãã®éå§
+     */
+    clock_write_tval((uint32_t)cyc);
+    target_timer_start();
+
+    /*
+     *  ã¿ã¤ãã®è¨­å®å¤
+     */
+    timer_cval = clock_read_cval();
+}
+
+/*
+ *  ã¿ã¤ãã®åæ­¢å¦ç
+ */
+void
+target_timer_terminate(intptr_t exinf)
+{
+    /*
+     *  ã¿ã¤ãã®åæ­¢
+     */
+    clock_write_ctrl((uint32_t)0);
+}
+
+/*
+ *  ã¿ã¤ãå²è¾¼ã¿ãã³ãã©
+ */
+void
+target_timer_handler(void)
+{
+    uint32_t cyc;
+    uint64_t pct;
+
+    /*
+     *  ã¿ã¤ãã®åæ­¢
+     */
+    target_timer_stop();
+
+    /*
+     *  1ãã£ãã¯ã®ã¯ã­ãã¯æ°
+     */
+    cyc = (timer_clock * (TIC_NUME) / (TIC_DENO));
+
+    /*
+     *  ã¿ã¤ãã®è¨­å®å¤
+     */
+    timer_cval = timer_cval + (uint64_t)cyc;
+
+
+    // ã«ã¦ã³ã¿ããèª­ã¿åºã
+    pct = clock_read_counter();
+
+    while (timer_cval > pct + cyc) {
+        timer_cval = timer_cval - (uint64_t)cyc;
+    }
+    while (timer_cval < pct) {
+        timer_cval = timer_cval + (uint64_t)cyc;
+    }
+
+    /*
+     *  ã¿ã¤ãã®è¨­å®
+     */
+    clock_write_cval((uint64_t)timer_cval);
+
+    /*
+     *  ã¿ã¤ãã®éå§
+     */
+    target_timer_start();
+
+    i_begin_int(INTNO_TIMER);
+    signal_time();              /* ã¿ã¤ã ãã£ãã¯ã®ä¾çµ¦ */
+    i_end_int(INTNO_TIMER);
+}
Index: /ssp_rpi3/trunk/arch/arm64_gcc/common/core_timer.cfg
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/common/core_timer.cfg	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/common/core_timer.cfg	(revision 384)
@@ -0,0 +1,11 @@
+/*
+ *  @(#) $Id$
+ */
+
+/*
+ *		ã¿ã¤ããã©ã¤ãã®ã³ã³ãã£ã®ã¥ã¬ã¼ã·ã§ã³ãã¡ã¤ã«
+ */
+ATT_INI({ TA_NULL, 0, target_timer_initialize });
+ATT_TER({ TA_NULL, 0, target_timer_terminate });
+DEF_INH(INHNO_TIMER, { TA_NULL, target_timer_handler });
+CFG_INT(INTNO_TIMER, { TA_ENAINT|INTATR_TIMER, INTPRI_TIMER });
Index: /ssp_rpi3/trunk/arch/arm64_gcc/common/core_timer.h
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/common/core_timer.h	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/common/core_timer.h	(revision 384)
@@ -0,0 +1,198 @@
+/*
+ *  TOPPERS/SSP Kernel
+ *      Smallest Set Profile Kernel
+ *
+ *  Copyright (C) 2013-2015 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2018,2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  $Id$
+ */
+
+/*
+ *  ã¿ã¤ããã©ã¤ãï¼Generic Timerï¼
+ */
+
+#ifndef TOPPERS_CORE_TIMER_H
+#define TOPPERS_CORE_TIMER_H
+
+#include <sil.h>
+
+/*
+ *  ã¿ã¤ãå²è¾¼ã¿ãã³ãã©ç»é²ã®ããã®å®æ°
+ */
+
+#define INTNO_TIMER     TINTNO_CNTPNS  /* å²è¾¼ã¿çªå· */
+#define INHNO_TIMER     INTNO_TIMER   /* å²è¾¼ã¿ãã³ãã©çªå· */
+
+#ifndef INTPRI_TIMER
+#define INTPRI_TIMER    (-3)            /* å²è¾¼ã¿åªå
+åº¦ */
+#endif
+
+#ifndef INTATR_TIMER
+#define INTATR_TIMER    TA_NULL            /* å²è¾¼ã¿å±æ§ */
+#endif
+
+/*
+ *  å¶å¾¡ã¬ã¸ã¹ã¿ã®ãããå®ç¾©
+ */
+#define CNTP_CTL_ENABLE     (1 << 0)
+#define CNTP_CTL_MASK       (1 << 1)
+#define CNTP_CTL_ISTATUS    (1 << 2)
+
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ *  ç©çã¿ã¤ãã®å¶å¾¡ã¬ã¸ã¹ã¿ããã®èª­ã¿åºã
+ */
+Inline uint32_t
+clock_read_ctrl(void) {
+    uint32_t cntv_ctrl;
+
+    Asm ("mrs %0, cntp_ctl_el0"
+        : "=r"(cntv_ctrl) :: "memory");
+
+    return cntv_ctrl;
+}
+
+/*
+ *  ç©çã¿ã¤ãã®å¶å¾¡ã¬ã¸ã¹ã¿ã¸ã®æ¸ãè¾¼ã¿
+ */
+Inline void
+clock_write_ctrl(uint32_t cntv_ctrl) {
+
+    Asm ("msr cntp_ctl_el0, %0"
+        :: "r"(cntv_ctrl) : "memory");
+}
+
+/*
+ *  ç©çã¿ã¤ã(ããªã¼ã«ã¦ã³ã¿)ã®ã«ã¦ã³ãå¤ã®èª­ã¿åºã
+ */
+Inline uint64_t
+clock_read_counter(void){
+    uint64_t cval;
+
+    Asm ("mrs %0, cntpct_el0" : "=r" (cval):: "memory");
+
+    return cval;
+}
+
+/*
+ *  ç©çã¿ã¤ãå¤ã®èª­ã¿åºã
+ */
+Inline uint32_t
+clock_read_tval(void){
+    uint32_t cntp_tval;
+
+    Asm ("mrs %0, cntp_tval_el0; isb;" : "=r"(cntp_tval)
+        :: "memory");
+    return cntp_tval;
+}
+
+/*
+ *  ç©çã¿ã¤ãå¤ã®æ¸ãè¾¼ã¿
+ */
+Inline void
+clock_write_tval(uint32_t cntv_tval){
+
+    Asm ("msr cntp_tval_el0, %0" :: "r"(cntv_tval): "memory");
+}
+
+/*
+ *  ã¿ã¤ãã®æ¯è¼å¤ã®èª­ã¿åºã
+ */
+Inline uint64_t
+clock_read_cval(void){
+    uint64_t cntp_cval;
+
+    Asm ("mrs %0, cntp_cval_el0" : "=r"(cntp_cval)
+        :: "memory");
+    return cntp_cval;
+}
+
+/*
+ *  ã¿ã¤ãã®æ¯è¼å¤ã®æ¸ãè¾¼ã¿
+ */
+Inline void
+clock_write_cval(uint64_t cntp_cval){
+
+    Asm ("msr cntp_cval_el0, %0" :: "r"(cntp_cval): "memory");
+}
+
+/*
+ *  ã·ã¹ãã ã«ã¦ã³ã¿ã®ã¯ã­ãã¯å¨æ³¢æ°ã®åå¾
+ */
+Inline uint32_t
+get_timer_freq(void) {
+    uint32_t freq_hz;
+
+    Asm ("mrs %0, cntfrq_el0" : "=r"(freq_hz) :: "memory");
+    return freq_hz;
+}
+
+/*
+ *  ã¿ã¤ãã®èµ·åå¦ç
+ *
+ *  ã¿ã¤ããåæåãï¼å¨æçãªã¿ã¤ãå²è¾¼ã¿è¦æ±ãçºçãããï¼
+ */
+extern void target_timer_initialize(intptr_t exinf);
+
+/*
+ *  ã¿ã¤ãã®åæ­¢å¦ç
+ */
+extern void target_timer_terminate(intptr_t exinf);
+
+/*
+ *  ã¿ã¤ãå²è¾¼ã¿ãã³ãã©
+ */
+extern void target_timer_handler(void);
+
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_PRC_TIMER_H */
Index: /ssp_rpi3/trunk/arch/arm64_gcc/common/core_unrename.h
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/common/core_unrename.h	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/common/core_unrename.h	(revision 384)
@@ -0,0 +1,56 @@
+/* This file is generated from core_rename.def by genrename. */
+
+/* This file is included only when core_rename.h has been included. */
+#ifdef TOPPERS_CORE_RENAME_H
+#undef TOPPERS_CORE_RENAME_H
+
+/*
+ *  core_config.c
+ */
+#undef intnest
+#undef core_initialize
+#undef core_terminate
+#undef call_int_handler
+#undef call_exc_handler
+#undef call_fiq_handler
+#undef default_exc_handler
+#undef default_int_handler
+
+/*
+ *  core_support.S
+ */
+#undef start_dispatch
+#undef call_exit_kernel
+#undef ret_int
+#undef ret_exc
+#undef ret_fiq
+#undef vectors
+
+#ifdef TOPPERS_LABEL_ASM
+
+/*
+ *  core_config.c
+ */
+#undef _intnest
+#undef _core_initialize
+#undef _core_terminate
+#undef _call_int_handler
+#undef _call_exc_handler
+#undef _call_fiq_handler
+#undef _default_exc_handler
+#undef _default_int_handler
+
+/*
+ *  core_support.S
+ */
+#undef _start_dispatch
+#undef _call_exit_kernel
+#undef _ret_int
+#undef _ret_exc
+#undef _ret_fiq
+#undef _vectors
+
+#endif /* TOPPERS_LABEL_ASM */
+
+
+#endif /* TOPPERS_CORE_RENAME_H */
Index: /ssp_rpi3/trunk/arch/arm64_gcc/common/core_user.txt
===================================================================
--- /ssp_rpi3/trunk/arch/arm64_gcc/common/core_user.txt	(revision 384)
+++ /ssp_rpi3/trunk/arch/arm64_gcc/common/core_user.txt	(revision 384)
@@ -0,0 +1,151 @@
+=====================================================================
+                         ARM64ãã­ã»ããµä¾å­é¨
+                                  Last Modified: '19/04/16
+=====================================================================
+
+
+(1) å¯¾å¿ãã¦ããã¿ã¼ã²ããã·ã¹ãã ã®ç¨®é¡ã»æ§æ
+
+ARM64ä¾å­é¨ã¯ï¼ARMv8-A ã¢ã¼ã­ãã¯ãã£ãã¿ã¼ã²ããã¨ãã¦ããï¼ARMv8-A ã¯
+64ãããã¢ã¼ã­ãã¯ãã£ã§ããå½ä»¤ã»ããã¬ãã«ã§ãARMã¨ã¯ç°ãªãããï¼
+ARMä¾å­é¨ã¨åãã¦ããï¼
+
+ã³ã¢ç¥ç§°ç­ã¯æ¬¡ã®éãï¼
+
+        ã³ã¢ç¥ç§°ï¼arm64
+        éçºç°å¢ç¥ç§°ï¼gcc
+
+(2) ä½¿ç¨ããéçºç°å¢ã¨åä½æ¤è¨¼ããæ¡ä»¶ï¼ãã¼ã¸ã§ã³ï¼ãªãã·ã§ã³ç­ï¼
+
+ã«ã¼ãã«ã¯GCCãç¨ãã¦ã³ã³ãã¤ã«ããï¼åä½ç¢ºèªãããã¼ã¸ã§ã³ã¯åã¿ã¼ã²
+ããä¾å­é¨ã®ãã­ã¥ã¡ã³ãã«è¨è¼ããï¼
+
+(3) ã¿ã¼ã²ããå®ç¾©äºé 
+ã®è¦å®
+
+(3-1) ãã¼ã¿åã«é¢ããè¦å®
+
+ãã¼ã¿åã¯ arch/gcc/tool_stddef.h ã§å®ç¾©ããã¦ããå
+å®¹ã§ï¼floatåã¨
+doubleåã¯ï¼ããããIEEE754æºæ ã®åç²¾åº¦æµ®åå°æ°ç¹æ°ã¨åç²¾åº¦æµ®åå°æ°ç¹
+æ°ã§ããï¼
+
+ãã®ã»ãï¼ã¹ã¿ãã¯é åãç¢ºä¿ããããã®ãã¼ã¿åã®ããã«
+int128_t ããã³ uint128_t ãå®ç¾©ãã¦ããï¼
+
+(3-2) å²è¾¼ã¿å¦çã«é¢ããè¦å®
+
+ãããã«æ­è¼ãããå²è¾¼ã¿ã³ã³ãã­ã¼ã©ã«ããç°ãªãï¼
+ãã®ããï¼ä»¥ä¸ã®äºé 
+ã«ã¤ãã¦ã¯ãããä¾å­é¨ã«è¨è¼ããï¼
+
+ã»å²è¾¼ã¿ãã³ãã©çªå·ã¨å²è¾¼ã¿çªå·ã®å²å½ã¦ï¼ä¸¡è
+ã®å¯¾å¿
+ã»å²è¾¼ã¿åªå
+åº¦ã®æ®µéæ°ï¼TMIN_INTPRIã®å¤ï¼ï¼ãã®è¨­å®æ¹æ³
+ã»dis_intã¨ena_intã®ãµãã¼ãã®æç¡ï¼ãã®å¶éäºé 
+
+ã»CFG_INTã®å¶éäºé 
+ã¨æ¡å¼µï¼ã¿ã¼ã²ããå®ç¾©ã§ä½¿ç¨ã§ããå²è¾¼ã¿å±æ§ï¼
+ã»ã«ã¼ãã«ç®¡çå¤ã®å²è¾¼ã¿
+
+(3-3) CPUä¾å¤å¦çã«é¢ããè¦å®
+
+ã»CPUä¾å¤ãã³ãã©çªå·
+
+Synchronousä¾å¤ããã³SErrorä¾å¤ãCPUä¾å¤ã¨ãã¦æ±ãï¼
+
+ARMv8ã§ã¯ï¼ä¾å¤çºçæã®ä¾å¤ã¬ãã«(EL)ï¼ä½¿ç¨ã¹ã¿ãã¯ï¼å®è¡ç¶æ
+(AArch32 or AArch64)ï¼
+çºçããä¾å¤ã®ç¨®é¡ã«ããï¼ã¸ã£ã³ãå
+ã¨ãªãä¾å¤ãã¯ã¿ä¸­ã®ãªãã»ããã¢ãã¬ã¹ãç°ãªãï¼
+CPUä¾å¤ãã³ãã©ã¯ãã®ã¸ã£ã³ãå
+ã®ãªãã»ããã¢ãã¬ã¹ã§åºå¥ãããã¨ã«ãï¼
+ããããç°ãªãCPUä¾å¤ãã³ãã©çªå·ãå²ãå½ã¦ãï¼
+
+  ä¾å¤çºçæã®ç¶æ
+             ä¾å¤ã®ç¨®é¡      ä¾å¤çªå· ãä¾å¤ãã¯ã¿å
+é ­ããã®ãªãã»ãã
+  AArch64, EL1t(EL1, SP_EL0)  Synchronous         0        0x0000
+  AArch64, EL1t(EL1, SP_EL0)  SError              1        0x0180
+  AArch64, EL1h(EL1, SP_EL1)  Synchronous         2        0x0200
+  AArch64, EL1h(EL1, SP_EL1)  SError              3        0x0380
+  AArch64, EL0 (EL0, SP_EL0)  Synchronous         4        0x0400
+  AArch64, EL0 (EL0, SP_EL0)  SError              5        0x0580
+  AArch32, EL0 (EL0, SP_EL0)  Synchronous         6        0x0600
+  AArch32, EL0 (EL0, SP_EL0)  SError              7        0x0780
+
+
+(3-4) CPUã­ãã¯ã»å²è¾¼ã¿ã­ãã¯
+
+ãããã«ããå®è£
+æ¹æ³ãç°ãªãããï¼ãããä¾å­é¨ã«è¨è¼ããï¼
+
+
+(3-5) æ§è½è©ä¾¡ç¨ã·ã¹ãã æå»ã®åç
+§ã«é¢ããè¦å®
+
+ã·ã¹ãã ã«ãã£ã¦ç°ãªããããããä¾å­é¨ã¾ãã¯ã¿ã¼ã²ããä¾å­é¨ã®ãã­ã¥ã¡ã³ãã§è¨è¼ããï¼
+
+
+(3-6) ã¹ã¿ã¼ãã¢ããã«ã¼ãã³ã§ã®åæåå
+å®¹
+
+ã¹ã¿ã¼ãã¢ããã«ã¼ãã³ãåæã¨ãããã­ã»ããµã®ç¶æ
+ã¯ã·ã¹ãã ã«ããç°ãªãããï¼
+ã¹ã¿ã¼ãã¢ããã«ã¼ãã³ã¯ã¿ã¼ã²ããä¾å­é¨ã®ãã­ã¥ã¡ã³ãã«è¨è¼ããï¼
+
+(4) ã¿ã¤ããã©ã¤ãé¢é£ã®æ
+å ±
+
+ã«ã¼ãã«ã®ã¿ã¤ã ãã£ãã¯ã¨ãã¦ï¼Generic Timer ãä½¿ç¨ããï¼
+ãã£ãã¯å¨æã¯1msecã¨ããï¼ã¾ãTIC_DENOåã³TIC_NUMEã®æ¢å®å¤ã¨ãã¦1ã«å®ç¾©ããï¼
+
+
+(5) ã¿ã¼ã²ããä¾å­é¨ã§ã®è¨­å®å¯è½é 
+ç®
+
+ã¿ã¼ã²ããä¾å­é¨ã§ã¯ä»¥ä¸ã®ãã¯ã­ãå®ç¾©ããï¼
+ããã¤ãã¯ãã­ã»ããµã®ä¾å­é¨ã«ããã¦æ¢å®å¤ãå®ç¾©ããã¦ããï¼
+
+   ã»TMIN_INTPRI    : å²è¾¼ã¿åªå
+åº¦ã®æå°å¤ï¼æé«å¤ï¼
+   ã»TIC_NUME       : ã¿ã¤ã ãã£ãã¯ã®å¨æã®åå­
+   ã»TIC_DENO       : ã¿ã¤ã ãã£ãã¯ã®å¨æã®åæ¯
+   ã»INTPRI_TIMER   : ã¿ã¤ãå²è¾¼ã¿åªå
+åº¦
+   ã»INTATR_TIMER   : ã¿ã¤ãå²è¾¼ã¿ã®å²è¾¼ã¿å±æ§
+   ã»DEFAULT_ISTKSZ : ã¹ã¿ãã¯ãµã¤ãºï¼16byteåä½ã§æå®ï¼
+
+
+(6) ãã£ã¬ã¯ããªæ§æã»ãã¡ã¤ã«æ§æ
+  ./arch/arm64_gcc/
+    MANIFEST
+    common/Makefile.core
+    common/arm64.h
+    common/core_cfg1_out.h
+    common/core_check.trb
+    common/core_config.c
+    common/core_config.h
+    common/core_design.txt
+    common/core_kernel.h
+    common/core_kernel.trb
+    common/core_rename.def
+    common/core_rename.h
+    common/core_sil.h
+    common/core_stddef.h
+    common/core_support.S
+    common/core_sym.def
+    common/core_test.h
+    common/core_timer.c
+    common/core_timer.cfg
+    common/core_timer.h
+    common/core_unrename.h
+    common/core_user.txt
+
+(12) ãã¼ã¸ã§ã³å±¥æ­´
+
+2018/05/30
+ ã»æåã®ãªãªã¼ã¹
+2019/04/15
+ ã»BCM283xãããä¾å­é¨ã®åé¢ã«åããã¦ä¿®æ­£
Index: /ssp_rpi3/trunk/build_ssp.sh
===================================================================
--- /ssp_rpi3/trunk/build_ssp.sh	(revision 384)
+++ /ssp_rpi3/trunk/build_ssp.sh	(revision 384)
@@ -0,0 +1,83 @@
+#!/usr/bin/env bash
+set -eu
+
+if [ ! -v SCRIPTS_DIR ]; then
+  SCRIPTS_DIR=$(cd $(dirname $0);pwd)
+fi
+
+if [ ! -v WORK_DIR ]; then
+  # if directory doesn't exist, it will be made
+  if [ ! -d $HOME/workdir ]; then
+    echo "$WORK_DIR doesn't exists. working directory 'toppers_workdir' will be made in current directory."
+    WORK_DIR=$(pwd)/toppers_workdir
+    mkdir -p $WORK_DIR
+  else
+    WORK_DIR=$HOME/workdir
+  fi
+fi
+
+SSP_DIR=$WORK_DIR/ssp
+SSP_PACKAGE=ssp-1.3.0.tar.gz
+SSP_DOWNLOAD_URL=http://www.toppers.jp/download.cgi/$SSP_PACKAGE
+SSP_RUBYCFG_FILES_URL=http://dev.toppers.jp/svn_user/contrib/rubycfg_ssp/trunk
+SSP_TARGET_NAME=rpi_arm64_gcc
+
+ASP3_DIR=$WORK_DIR/asp3
+ASP3_PACKAGE=asp3-3.1.0.tar.gz
+ASP3_DOWNLOAD_URL=https://www.toppers.jp/download.cgi/$ASP3_PACKAGE
+
+: "setup tools (compiler, emulator, etc.)" && {
+  $SCRIPTS_DIR/setup_tools.sh
+  . $HOME/.profile
+}
+
+: "Download TOPPERS/ASP3 package to get a configurator files"  && {
+  cd $WORK_DIR
+  if [ ! -e $ASP3_DIR ]; then
+    if [ ! -e $ASP3_PACKAGE ]; then
+      curl $ASP3_DOWNLOAD_URL -o $ASP3_PACKAGE
+    fi
+    tar xvf $ASP3_PACKAGE
+  fi
+}
+
+: "if ssp directory already exists, rename it and create new directory" && {
+  cd $WORK_DIR
+  if [ -e $SSP_DIR ]; then
+    mv $SSP_DIR $SSP_DIR.$(date +%Y%m%d_%H%M%S)
+  fi
+
+  if [ ! -e $SSP_PACKAGE ]; then
+    curl $SSP_DOWNLOAD_URL -o $SSP_PACKAGE
+  fi
+
+  mkdir $SSP_DIR
+  tar xvf $SSP_PACKAGE -C $SSP_DIR --strip-components 2
+}
+
+: "setup source code(convert to UTF8, patch, etc.)" && {
+  for i in `find $SSP_DIR -type f` ; do nkf --overwrite --oc=UTF-8 $i; done
+  cp -a $ASP3_DIR/sample/Makefile $SSP_DIR/sample
+
+  svn co $SSP_RUBYCFG_FILES_URL rubycfg_ssp
+  rubycfg_ssp/install.sh $SSP_DIR
+
+  $SCRIPTS_DIR/install.sh $SSP_DIR
+
+  cd $SSP_DIR
+  ln -s $ASP3_DIR/configure.rb configure.rb
+  ln -s $ASP3_DIR/cfg cfg
+}
+
+: "build a kernel" && {
+  cd $SSP_DIR
+  if [ -e build ]; then
+    mv build build.$(date +%Y%m%d_%H%M%S)
+  fi
+  mkdir build
+  cd build
+  ../configure.rb -T $SSP_TARGET_NAME -w
+  make
+}
+
+exit 0
Index: /ssp_rpi3/trunk/install.sh
===================================================================
--- /ssp_rpi3/trunk/install.sh	(revision 384)
+++ /ssp_rpi3/trunk/install.sh	(revision 384)
@@ -0,0 +1,17 @@
+#!/usr/bin/env bash
+set -eu
+
+SCRIPT_DIR=$(cd $(dirname $0);pwd)
+
+if [ $# -lt 1 ]; then
+  echo "usage: install.sh dest_ssp_dir"
+  exit 1
+else
+  SSPDIR=$1
+fi
+
+cp -a ${SCRIPT_DIR}/arch/arm64_gcc ${SSPDIR}/arch/
+cp -a ${SCRIPT_DIR}/target/rpi_arm64_gcc ${SSPDIR}/target/
+(cd ${SSPDIR} && patch -p1 < ${SCRIPT_DIR}/ssp_aarch64.patch)
+
+exit 0
Index: /ssp_rpi3/trunk/setup_tools.sh
===================================================================
--- /ssp_rpi3/trunk/setup_tools.sh	(revision 384)
+++ /ssp_rpi3/trunk/setup_tools.sh	(revision 384)
@@ -0,0 +1,49 @@
+#!/usr/bin/env bash
+set -eu
+
+# Variables
+GCC_COMMAND=aarch64-elf-gcc
+QEMU_COMMAND=qemu-system-aarch64
+GCC_PACKAGE_FILE=gcc-linaro-7.2.1-2017.11-x86_64_aarch64-elf.tar.xz
+GCC_DOWNLOAD_URL=https://releases.linaro.org/components/toolchain/binaries/7.2-2017.11/aarch64-elf/$GCC_PACKAGE_FILE
+
+if [ ! -v TOOLDIR ]; then
+  TOOLDIR=$HOME/MyTools
+fi
+
+GCC_INSTALL_DIR=$TOOLDIR/$GCC_COMMAND
+GCC_COMMAND_PATH=$GCC_INSTALL_DIR/bin/$GCC_COMMAND
+
+TMPDIR=/tmp
+
+: "install $GCC_COMMAND" && {
+  cd $TMPDIR
+
+  if type $GCC_COMMAND_PATH > /dev/null 2>&1; then 
+    echo "It seems $GCC_COMMAND exists in $GCC_COMMAND_PATH. skip install."
+  else
+    wget $GCC_DOWNLOAD_URL -O $GCC_PACKAGE_FILE
+    wget $GCC_DOWNLOAD_URL.asc -O $GCC_PACKAGE_FILE.asc
+    : "MD5 hash check" && {
+      if md5sum -c $GCC_PACKAGE_FILE.asc;then
+        mkdir -p $GCC_INSTALL_DIR
+        tar xvf $GCC_PACKAGE_FILE -C $GCC_INSTALL_DIR --strip-components 1
+        echo export PATH=\"$GCC_INSTALL_DIR/bin:'$PATH'\" >> ~/.profile
+      else
+        echo "MD5 hash check error. exit"
+        exit 1
+      fi
+    }
+  fi
+}
+
+: "install $QEMU_COMMAND" && {
+  if type $QEMU_COMMAND > /dev/null 2>&1; then
+    echo "$QEMU_COMMAND already exists. skip install."
+  else
+    sudo apt-get update
+    sudo apt-get install -y qemu-system-arm
+  fi
+}
+
+exit 0
Index: /ssp_rpi3/trunk/ssp_aarch64.patch
===================================================================
--- /ssp_rpi3/trunk/ssp_aarch64.patch	(revision 384)
+++ /ssp_rpi3/trunk/ssp_aarch64.patch	(revision 384)
@@ -0,0 +1,70 @@
+diff -x '.git*' -uprN ssp.orig/doc/porting.txt ssp/doc/porting.txt
+--- ssp.orig/doc/porting.txt	2015-05-19 18:45:26.000000000 +0900
++++ ssp/doc/porting.txt	2018-06-06 18:24:58.000000000 +0900
+@@ -408,7 +408,7 @@ KERNEL_CFLAGS := $(KERNEL_CFLAGS) -fno-s
+ また，アセンブリ言語レベルの識別名が，C言語レベルの識別名の先頭に"_"が
+ 付いたものになる場合には，CDEFSに-DTOPPERS_LABEL_ASMを追加する．
+ 
+-(2-4-6) SYSSVC_DIR			システムサービスのソースが置かれたディレクトリ
++(2-4-6) SYSSVC_DIRS			システムサービスのソースが置かれたディレクトリ
+ (2-4-7) SYSSVC_ASMOBJS		アセンブリ言語で記述されたシステムサービスの
+ 							オブジェクト
+ (2-4-8) SYSSVC_COBJS		C言語で記述されたシステムサービスのオブジェクト
+@@ -421,7 +421,7 @@ KERNEL_CFLAGS := $(KERNEL_CFLAGS) -fno-s
+ イルオプション，その構成に必要なライブラリリンク指定を追加する場合には，
+ 上に示した変数に定義する．
+ 
+-(2-4-11) KERNEL_DIR			カーネルのソースが置かれたディレクトリ
++(2-4-11) KERNEL_DIRS			カーネルのソースが置かれたディレクトリ
+ (2-4-12) KERNEL_ASMOBJS		アセンブリ言語で記述されたカーネルのオブジェクト
+ (2-4-13) KERNEL_COBJS		C言語で記述されたカーネルのオブジェクト
+ (2-4-14) KERNEL_CFLAGS		カーネルに対するコンパイルオプション
+@@ -450,7 +450,7 @@ KERNEL_COBJS := $(KERNEL_COBJS) target_c
+ 下の記述を含める必要がある．
+ 
+ ----------------------------------------
+-CFG_TABS := $(CFG_TABS) --cfg1-def-table $(TARGETDIR)/target_def.csv
++CFG_TABS := $(CFG_TABS) --symval-table $(TARGETDIR)/target_sym.def
+ ----------------------------------------
+ 
+ (2-4-16) CFG1_OUT_LDFLAGS	cfg1_out.cに対するリンクオプション
+@@ -595,9 +595,9 @@ LIBS := $(LIBS) -lgcc
+ 下の記述を含める必要がある．
+ 
+ ----------------------------------------
+-cfg1_out.c: $(TARGETDIR)/target_def.csv
+-kernel_cfg.timestamp: $(TARGETDIR)/target.tf
+-$(OBJFILE): $(TARGETDIR)/target_check.tf
++cfg1_out.c: $(TARGETDIR)/target_sym.def
++kernel_cfg.timestamp: $(TARGETDIR)/target_kernel.trb
++check.timestamp: $(TARGETDIR)/target_check.trb
+ ----------------------------------------
+ 
+ 2.7 その他の設定
+diff -x '.git*' -uprN ssp.orig/sample/Makefile ssp/sample/Makefile
+--- ssp.orig/sample/Makefile	2018-06-06 19:35:22.000000000 +0900
++++ ssp/sample/Makefile	2018-06-06 18:24:58.000000000 +0900
+@@ -256,14 +256,6 @@ else
+ 	KERNEL_COBJS := $(KERNEL_COBJS) \
+ 					$(foreach file,$(KERNEL_FCSRCS),$(file:.c=.o))
+ endif
+-ifdef OMIT_OFFSET_H
+-	OFFSET_H =
+-else
+-	OFFSET_H = offset.h
+-endif
+-ifndef TARGET_OFFSET_TRB
+-	TARGET_OFFSET_TRB := $(TARGETDIR)/target_offset.trb
+-endif
+ ifndef TARGET_KERNEL_TRB
+ 	TARGET_KERNEL_TRB := $(TARGETDIR)/target_kernel.trb
+ endif
+@@ -275,7 +267,7 @@ ifndef TARGET_KERNEL_CFG
+ endif
+ 
+ #
+-#  コンフィキﾞュレータに関する定義
++#  コンフィギュレータに関する定義
+ #
+ CFG_TABS := --api-table $(SRCDIR)/kernel/kernel_api.def \
+                         --symval-table $(SRCDIR)/kernel/kernel_sym.def \
Index: /ssp_rpi3/trunk/target/rpi_arm64_gcc/E_PACKAGE
===================================================================
--- /ssp_rpi3/trunk/target/rpi_arm64_gcc/E_PACKAGE	(revision 384)
+++ /ssp_rpi3/trunk/target/rpi_arm64_gcc/E_PACKAGE	(revision 384)
@@ -0,0 +1,5 @@
+E_PACKAGE ssp_rpi_arm64_gcc
+VERSION %date
+
+INCLUDE ../../MANIFEST
+INCLUDE ../../cfg/MANIFEST
Index: /ssp_rpi3/trunk/target/rpi_arm64_gcc/MANIFEST
===================================================================
--- /ssp_rpi3/trunk/target/rpi_arm64_gcc/MANIFEST	(revision 384)
+++ /ssp_rpi3/trunk/target/rpi_arm64_gcc/MANIFEST	(revision 384)
@@ -0,0 +1,29 @@
+PACKAGE ssp_arch_arm64_gcc
+VERSION 1.3.0
+
+E_PACKAGE
+MANIFEST
+Makefile.target
+rpi_arm64.h
+rpi_arm64.ld
+start.S
+target_cfg1_out.h
+target_check.trb
+target_config.c
+target_config.h
+target_kernel.cfg
+target_kernel.h
+target_kernel.trb
+target_rename.def
+target_rename.h
+target_serial.cfg
+target_serial.h
+target_sil.h
+target_stddef.h
+target_sym.def
+target_syssvc.h
+target_test.h
+target_timer.cfg
+target_timer.h
+target_unrename.h
+target_user.txt
Index: /ssp_rpi3/trunk/target/rpi_arm64_gcc/Makefile.target
===================================================================
--- /ssp_rpi3/trunk/target/rpi_arm64_gcc/Makefile.target	(revision 384)
+++ /ssp_rpi3/trunk/target/rpi_arm64_gcc/Makefile.target	(revision 384)
@@ -0,0 +1,127 @@
+#
+#  Makefile ã®ã¿ã¼ã²ããä¾å­é¨(RPI-ARM64ç¨)
+#
+
+#
+#  ãã¼ãåï¼ã³ã¢åï¼ãããåï¼éçºç°å¢åã®å®ç¾©
+#
+BOARD = rpi_arm64
+CHIP  = bcm283x
+CORE  = arm64
+TOOL  = gcc
+
+#
+#  GNUéçºç°å¢ã®ã¿ã¼ã²ããã¢ã¼ã­ãã¯ãã£ã®å®ç¾©
+#
+GCC_TARGET = aarch64-elf
+
+#
+#  ã³ã³ãã¤ã«ãªãã·ã§ã³
+#
+COPTS := $(COPTS) -Werror -ggdb3 -mgeneral-regs-only -fno-pic -fno-builtin -fno-omit-frame-pointer #-mfix-cortex-a53-835769 -mfix-cortex-a53-843419
+CDEFS := $(CDEFS)
+INCLUDES := $(INCLUDES) -I$(TARGETDIR)
+LDFLAGS := -nostdlib $(LDFLAGS)
+LIBS := $(LIBS) -lgcc
+
+#
+#  ã·ã¹ãã ãµã¼ãã¹ã«é¢ããå®ç¾©
+#
+SYSSVC_DIRS := $(SYSSVC_DIRS)
+SYSSVC_ASMOBJS := $(SYSSVC_ASMOBJS)
+SYSSVC_COBJS := $(SYSSVC_COBJS)
+SYSSVC_CFLAGS := $(SYSSVC_CFLAGS)
+SYSSVC_LIBS := $(SYSSVC_LIBS)
+
+#
+#  ã«ã¼ãã«ã«é¢ããå®ç¾©
+#
+KERNEL_DIRS := $(KERNEL_DIRS) $(TARGETDIR)
+KERNEL_ASMOBJS := $(KERNEL_ASMOBJS)
+KERNEL_COBJS := $(KERNEL_COBJS) target_config.o
+KERNEL_CFLAGS := $(KERNEL_CFLAGS)
+
+#
+#  ãã¬ã¼ã¹ã­ã°ã«é¢ããè¨­å®
+#
+ifeq ($(ENABLE_TRACE),true)
+	COPTS := $(COPTS) -DTOPPERS_ENABLE_TRACE
+	KERNEL_DIRS := $(KERNEL_DIRS) $(SRCDIR)/arch/logtrace
+	KERNEL_COBJS := $(KERNEL_COBJS) trace_config.o trace_dump.o
+endif
+
+#
+#  ã³ã³ãã£ã®ã¥ã¬ã¼ã¿é¢ä¿ã®å¤æ°ã®å®ç¾©
+#
+CFG_TABS := $(CFG_TABS) --symval-table $(TARGETDIR)/target_sym.def
+CFG1_OUT_LDFLAGS := $(CFG1_OUT_LDFLAGS)
+CFG_OBJS := $(CFG_OBJS)
+CFG2_OUT := $(CFG2_OUT)
+
+#
+#  -Wall ãªãã·ã§ã³ã®çç¥
+#    -Wallãè¿½å ããããªãå ´åã« true ã«å®ç¾©ãã
+#
+#OMIT_WARNING_ALL = true
+
+#
+#  æé©åãã©ã°ã®çç¥
+#    -O2ãè¿½å ããããªãå ´åã« true ã«å®ç¾©ãã
+#
+#OMIT_OPTIMIZATION = true
+
+#
+#  ãªã³ã«ã¹ã¯ãªããã®å®ç¾©
+#
+LDSCRIPT = $(SRCDIR)/target/$(BOARD)_$(TOOL)/$(BOARD).ld
+
+#
+#  åã»ã¯ã·ã§ã³ã®å
+é ­çªå°ã®æå®
+#
+TEXT_START_ADDRESS = 0x00000000
+
+#
+#  ã¹ã¿ã¼ãã¢ããã¢ã¸ã¥ã¼ã«ã«é¢ããå®ç¾©
+#
+
+#  ã¹ã¿ã¼ãã¢ããã¢ã¸ã¥ã¼ã«
+START_OBJS = start.o
+#  ãªã³ã«ã¹ã¯ãªããã«ãSTARTUP(start.o)ããè¨è¿°ããå ´åï¼
+#  ã¹ã¿ã¼ãã¢ããã¢ã¸ã¥ã¼ã«ã®ååãSTART_OBJS ã®ä»£ããã« HIDDEN_OBJS ã§å®ç¾©ããï¼
+HIDDEN_OBJS =
+
+
+# ã¹ã¿ã¼ãã¢ããã¢ã¸ã¥ã¼ã«ã®ã³ã³ãã¤ã«ã«ã¼ã«
+$(START_OBJS): %.o: %.S
+	$(CC) -c $(CFLAGS) $(KERNEL_CFLAGS) $<
+$(HIDDEN_OBJS): %.o: %.S
+	$(CC) -c $(CFLAGS) $(KERNEL_CFLAGS) $<
+
+
+# ã¹ã¿ã¼ãã¢ããã¢ã¸ã¥ã¼ã«ã®ä¾å­é¢ä¿ä½æã«ã¼ã«
+$(START_OBJS:.o=.d): %.d: %.S
+	@$(PERL) $(SRCDIR)/utils/makedep -C $(CC) $(MAKEDEP_OPTS) \
+                -O "$(CFLAGS) $(KERNEL_CFLAGS)" $< >> Makefile.depend
+$(HIDDEN_OBJS:.o=.d): %.d: %.S
+	@$(PERL) $(SRCDIR)/utils/makedep -C $(CC) $(MAKEDEP_OPTS) \
+                -O "$(CFLAGS) $(KERNEL_CFLAGS)" $< >> Makefile.depend
+
+#
+#  ä¾å­é¢ä¿ã®å®ç¾©
+#
+cfg1_out.c: $(TARGETDIR)/target_sym.def
+kernel_cfg.timestamp: $(TARGETDIR)/target_kernel.trb
+check.timestamp: $(TARGETDIR)/target_check.trb
+
+#
+#  ãã®ä»
+#
+CLEAN_FILES := $(CLEAN_FILES)
+REALCLEAN_FILES := $(REALCLEAN_FILES)
+
+
+#
+#  ãããä¾å­é¨ã®ã¤ã³ã¯ã«ã¼ã
+#
+include $(SRCDIR)/arch/$(CORE)_$(TOOL)/$(CHIP)/Makefile.chip
Index: /ssp_rpi3/trunk/target/rpi_arm64_gcc/rpi_arm64.h
===================================================================
--- /ssp_rpi3/trunk/target/rpi_arm64_gcc/rpi_arm64.h	(revision 384)
+++ /ssp_rpi3/trunk/target/rpi_arm64_gcc/rpi_arm64.h	(revision 384)
@@ -0,0 +1,67 @@
+/*
+ *  TOPPERS/SSP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2013-2014 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2018,2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  $Id$
+ */
+
+/*
+ *  RPI ARM64 ã¿ã¼ã²ãã(RPI3B)ã®ãã¼ãã¦ã§ã¢è³æºå®ç¾©
+ */
+
+#ifndef TOPPERS_RPI_ARM64_H
+#define TOPPERS_RPI_ARM64_H
+
+#ifndef  TOPPERS_MACRO_ONLY
+#endif  /*  TOPPERS_MACRO_ONLY  */
+#endif /* TOPPERS_QEMU_VIRT_H */
Index: /ssp_rpi3/trunk/target/rpi_arm64_gcc/rpi_arm64.ld
===================================================================
--- /ssp_rpi3/trunk/target/rpi_arm64_gcc/rpi_arm64.ld	(revision 384)
+++ /ssp_rpi3/trunk/target/rpi_arm64_gcc/rpi_arm64.ld	(revision 384)
@@ -0,0 +1,93 @@
+/*
+ *  $Id:$
+ */
+
+OUTPUT_FORMAT("elf64-littleaarch64", "elf64-bigaarch64",
+              "elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+
+PROVIDE(hardware_init_hook = 0);
+PROVIDE(software_init_hook = 0);
+PROVIDE(software_term_hook = 0);
+
+ENTRY(start)
+SECTIONS
+{
+	. = 0x40000000;
+	.text : {
+		__start_text = .;
+		 *(.text) 
+		__end_kernel = .;
+	}
+	_etext = .;
+	PROVIDE(etext = .);
+
+	. = ALIGN(8);
+	.rodata : {
+		__start_rodata = .;
+		*(.rodata)
+		__end_rodata = .;
+	}
+
+	. = ALIGN(8);
+	__start_idata = .;
+	.data : AT(__start_idata){
+		__start_data = .;
+		 *(.data) 
+		__end_data = .;
+	 }
+	__end_idata = __start_idata + SIZEOF(.data);
+	_edata = .;
+	PROVIDE(edata = .);
+	. = ALIGN(8);
+	.bss : {
+		__start_bss = .;
+		*(.bss)
+		*(COMMON)
+		__end_bss = .;
+	 }
+	. = ALIGN(8);
+	_end = .;
+	PROVIDE(end = .);
+	. = . + 0x1000; /* 4kB of stack memory */
+	stack_top = .;
+	.comment 0 : { *(.comment) }	
+
+	/*
+	 *  DWARF debug sections.
+	 *  Symbols in the DWARF debugging sections are relative to
+	 *  the beginning of the section so we begin them at 0.
+	 */
+
+	/* DWARF 1 */
+	.debug			0 : { *(.debug) }
+	.line			0 : { *(.line) }
+
+	/* GNU DWARF 1 extensions */
+	.debug_srcinfo	0 : { *(.debug_srcinfo) }
+	.debug_sfnames	0 : { *(.debug_sfnames) }
+
+	/* DWARF 1.1 and DWARF 2 */
+	.debug_aranges	0 : { *(.debug_aranges) }
+	.debug_pubnames	0 : { *(.debug_pubnames) }
+
+	/* DWARF 2 */
+	.debug_info		0 : { *(.debug_info) }
+	.debug_abbrev	0 : { *(.debug_abbrev) }
+	.debug_line		0 : { *(.debug_line) }
+	.debug_frame	0 : { *(.debug_frame) }
+	.debug_str		0 : { *(.debug_str) }
+	.debug_loc		0 : { *(.debug_loc) }
+	.debug_macinfo	0 : { *(.debug_macinfo) }
+
+	/* SGI/MIPS DWARF 2 extensions */
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames  0 : { *(.debug_varnames) }
+
+    /* Linker bugs ? */
+    .note.gnu.build-id : {
+        *(.note.gnu.build-id)
+    }
+}
Index: /ssp_rpi3/trunk/target/rpi_arm64_gcc/start.S
===================================================================
--- /ssp_rpi3/trunk/target/rpi_arm64_gcc/start.S	(revision 384)
+++ /ssp_rpi3/trunk/target/rpi_arm64_gcc/start.S	(revision 384)
@@ -0,0 +1,173 @@
+/*
+ *  TOPPERS Software
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *
+ *  Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
+ *                              Toyohashi Univ. of Technology, JAPAN
+ *  Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2018, 2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  $Id$
+ */
+
+#define TOPPERS_MACRO_ONLY
+#define UINT64_C(val)   (val)           /* uint64_tåã®å®æ°ãä½ããã¯ã­ */
+#include "kernel_impl.h"
+
+    .text
+    .align 4
+    .global start
+    .global vectors
+start:
+    // ã³ã¢0ã®ã¿å©ç¨
+    mrs x0, mpidr_el1
+    and x0, x0, #3
+    cbz x0, 2f
+1:
+    // ã³ã¢0ä»¥å¤
+    wfi
+    b   1b
+2:
+    // ããä»¥éã¯ã³ã¢0ã®ã¿
+    msr daifset, #(AARCH64_DAIF_IRQ | AARCH64_DAIF_FIQ)      // CPSR.{I,F}=1
+
+    /*
+     * ã¹ã¿ãã¯å
+é ­çªå°ãåãåºãã¦ãã
+     */
+    adrp x1, _kernel_istkpt
+    add  x1, x1, :lo12:_kernel_istkpt
+    ldr  x1, [x1]
+
+    /*
+     *  ELæ¯ã®å¦ç
+     */
+    mrs x0, CurrentEL
+    and x0, x0, #(0x3 << 2)
+    cmp x0, #(0x3 << 2)    //  EL3?
+    bne start_el2
+
+    /*
+     *  EL3
+     */
+start_el3:
+    mov x2, #0x5b1    // RW=1(EL2 is AArch64), HCE=1, SMD=1, NS=1(non-secure)
+    msr scr_el3, x2
+    isb
+
+    /* Set up CNTFRQ_EL0 */
+    ldr x0, =19200000 // 19.2MHz
+    msr CNTFRQ_EL0, x0
+
+    // EL2ã¸ç§»è¡
+    mov x2, #0x0c9    // I=F=1, MODE=1001 (EL2h)
+    msr spsr_el3, x2
+    adr x2, start_el2
+    msr elr_el3, x2
+    eret
+
+    /*
+     *  EL2
+     */
+start_el2:
+    cmp x0, #(0x1 << 2)    //  EL2?
+    beq start_el1
+
+    msr sp_el1, x1
+
+    mov x0, #(1 << 31)      // RW=1(EL1 is AArch64)
+    orr x0, x0, #(1 << 1)   // SWIO hardwired on Pi3
+    msr hcr_el2, x0         // TSC=0(SMC is not trapped)
+    isb
+
+    mrs x0, cnthctl_el2     // EL1PCTEN=1, EL1PCEN=1
+    orr x0, x0, #3
+    msr cnthctl_el2, x0
+    msr cntvoff_el2, xzr
+    isb
+
+    // EL1ã¸ç§»è¡
+    mov x2, #0x0c5         // I,F=1, mode=0101(EL1h)
+    msr spsr_el2, x2
+    adr x2, start_el1
+    msr elr_el2, x2
+    eret
+
+    /*
+     *  EL1h
+     */
+start_el1:
+    // ã¹ã¿ãã¯ãã¤ã³ã¿ã¨ãã¬ã¼ã ãã¤ã³ã¿ã®åæå
+    mov sp, x1
+    mov x29, xzr
+
+    /*
+     *  ä¾å¤ãã¯ã¿ãã¼ãã«ã®ãã¼ã¹ã¢ãã¬ã¹è¨­å®
+     */
+    ldr x0, =vectors
+    msr vbar_el1, x0
+
+    /*
+     *  bssã»ã¯ã·ã§ã³ã®ã¯ãªã¢
+     */
+    ldr   x1, =__start_bss
+    ldr   x2, =__end_bss
+    cmp   x1, x2
+    b.hs  4f
+3:
+    str   xzr, [x1], #8
+    cmp   x1, x2
+    b.lo  3b
+
+4:
+    /*
+     *  sta_kerå¼ã³åºã
+     */
+    bl sta_ker
+    b .
Index: /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_cfg1_out.h
===================================================================
--- /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_cfg1_out.h	(revision 384)
+++ /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_cfg1_out.h	(revision 384)
@@ -0,0 +1,9 @@
+/*
+ *  cfg1_out.cããªã³ã¯ããããã«å¿
+è¦ãªã¹ã¿ãã®å®ç¾©
+ */
+
+/*
+ *  ãããä¾å­ã®ã¹ã¿ãã®å®ç¾©
+ */
+#include "arm64_gcc/bcm283x/chip_cfg1_out.h"
Index: /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_check.trb
===================================================================
--- /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_check.trb	(revision 384)
+++ /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_check.trb	(revision 384)
@@ -0,0 +1,6 @@
+# -*- coding: utf-8 -*-
+#
+#  ãã¹3ã®çæã¹ã¯ãªããã®ã¿ã¼ã²ããä¾å­é¨
+#
+
+IncludeTrb("arm64_gcc/bcm283x/chip_check.trb")
Index: /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_config.c
===================================================================
--- /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_config.c	(revision 384)
+++ /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_config.c	(revision 384)
@@ -0,0 +1,121 @@
+/*
+ *  TOPPERS/SSP Kernel
+ *      Smallest Set Profile Kernel
+ *
+ *  Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
+ *                              Toyohashi Univ. of Technology, JAPAN
+ *  Copyright (C) 2005-2007 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2012 Meika Sugimoto
+ *  Copyright (C) 2015,2018,2019 by Naoki Saito
+ *              Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ */
+
+/*
+ * ã¿ã¼ã²ããä¾å­ã¢ã¸ã¥ã¼ã«(RPI_ARM64ç¨)
+ */
+#include "kernel_impl.h"
+#include <sil.h>
+#include "target_serial.h"
+#include "target_syssvc.h"
+
+/*
+ * ã¿ã¼ã²ããä¾å­é¨ãåæåå¦ç
+ */
+void target_initialize(void)
+{
+    volatile uint32_t tmp;
+
+    /*
+     *  GPIOãã³ãUART0ã¨ãã¦å©ç¨ããããã®è¨­å®
+     */
+    tmp = sil_rew_mem((uint32_t *)GPFSEL1);
+    tmp &= ~((7<<12)|(7<<15)); // gpio14, gpio15
+    tmp |= ((4<<12)|(4<<15));  // alt0
+    sil_wrw_mem((uint32_t *)GPFSEL1, tmp);
+
+    sil_wrw_mem((uint32_t *)GPPUD, 0);  // enable pins 14 and 15
+    for (tmp = 0; tmp < 150; tmp++) {
+        Asm("nop");
+    }
+    sil_wrw_mem((uint32_t *)GPPUDCLK0, (1<<14)|(1<<15));
+    for (tmp = 0; tmp < 150; tmp++) {
+        Asm("nop");
+    }
+    sil_wrw_mem((uint32_t *)GPPUDCLK0, 0);
+
+    /*
+     *  ä½ã¬ãã«åºåã®ããã®ã·ãªã¢ã«ãã¼ãã®åæå
+     */
+    target_low_output_init(1);
+
+    /*
+     *  ãããä¾å­é¨ã®åæå
+     */
+    chip_initialize();
+}
+
+/*
+ * ã¿ã¼ã²ããä¾å­é¨ çµäºå¦ç
+ */
+void target_exit(void)
+{
+    /* ãããä¾å­é¨ã®çµäºå¦ç */
+    chip_terminate();
+}
+
+/*
+ * ã·ã¹ãã ã­ã°ã®ä½ã¬ãã«åºåã®ããã®æå­åºå
+ */
+void target_fput_log(char c)
+{
+    if (c == '\n') {
+        sio_pol_snd_chr('\r', SIO_PORTID);
+    }
+    sio_pol_snd_chr(c, SIO_PORTID);
+}
Index: /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_config.h
===================================================================
--- /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_config.h	(revision 384)
+++ /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_config.h	(revision 384)
@@ -0,0 +1,108 @@
+/*
+ *  TOPPERS/SSP Kernel
+ *      Smallest Set Profile Kernel
+ *
+ *  Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
+ *                              Toyohashi Univ. of Technology, JAPAN
+ *  Copyright (C) 2005-2007 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2012 by Meika Sugimoto
+ *  Copyright (C) 2018, 2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ */
+
+#ifndef TOPPERS_TARGET_CONFIG_H
+#define TOPPERS_TARGET_CONFIG_H
+
+/*
+ * ã¿ã¼ã²ããä¾å­é¨ã¢ã¸ã¥ã¼ã«(RPI-ARM64ç¨)
+ *
+ * ã«ã¼ãã«ã®ã¿ã¼ã²ããä¾å­é¨ã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«ï¼
+ * kernel_impl.hã®ã¿ã¼ã²ããä¾å­é¨ã®ä½ç½®ä»ãã¨ãªãï¼
+ */
+
+/*
+ * ãã¼ãã¦ã§ã¢å®ç¾©
+ */
+#include "rpi_arm64.h"
+
+/*
+ *  ãã¬ã¼ã¹ã­ã°ã«é¢ããè¨­å®
+ */
+#ifdef TOPPERS_ENABLE_TRACE
+#include "logtrace/trace_config.h"
+#endif /* TOPPERS_ENABLE_TRACE */
+
+/*
+ *  ããã©ã«ãã®éã¿ã¹ã¯ã³ã³ãã­ã¹ãç¨ã®ã¹ã¿ãã¯é åã®å®ç¾©
+ *  16byteåä½ã§åå¾ãããï¼
+ */
+#define DEFAULT_ISTKSZ			(0x4000 / 16)		/* 16KByte */
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ *  ã¿ã¼ã²ããã·ã¹ãã ä¾å­ã®åæå
+ */
+extern void	target_initialize(void);
+
+/*
+ *  ã¿ã¼ã²ããã·ã¹ãã ã®çµäº
+ *
+ *  ã·ã¹ãã ãçµäºããæã«ä½¿ãï¼
+ */
+extern void	target_exit(void) NoReturn;
+
+#endif /* TOPPERS_MACRO_ONLY */
+
+/*
+ *  ãããä¾å­ã¢ã¸ã¥ã¼ã«
+ */
+#include "arm64_gcc/bcm283x/chip_config.h"
+
+#endif /* TOPPERS_TARGET_CONFIG_H */
Index: /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_kernel.cfg
===================================================================
--- /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_kernel.cfg	(revision 384)
+++ /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_kernel.cfg	(revision 384)
@@ -0,0 +1,1 @@
+INCLUDE("target_timer.cfg");
Index: /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_kernel.h
===================================================================
--- /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_kernel.h	(revision 384)
+++ /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_kernel.h	(revision 384)
@@ -0,0 +1,74 @@
+/*
+ *  TOPPERS/SSP Kernel
+ *      Smallest Set Profile Kernel
+ *
+ *  Copyright (C) 2007 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2018,2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ */
+
+/*
+ *  kernel.hã®ã¿ã¼ã²ããä¾å­é¨(RPI-ARM64ç¨)
+ *
+ *  ãã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«ã¯ï¼kernel.hã§ã¤ã³ã¯ã«ã¼ããããï¼ä»ã®ãã¡
+ *  ã¤ã«ããç´æ¥ã¤ã³ã¯ã«ã¼ããããã¨ã¯ãªãï¼ãã®ãã¡ã¤ã«ãã¤ã³ã¯ã«ã¼ã
+ *  ããåã«ï¼t_stddef.hãã¤ã³ã¯ã«ã¼ããããã®ã§ï¼ãããã«ä¾å­ãã¦ãã
+ *  ãï¼
+ */
+
+#ifndef TOPPERS_TARGET_KERNEL_H
+#define TOPPERS_TARGET_KERNEL_H
+
+/*
+ *  ãã­ã»ããµã§å
+±éãªå®ç¾©
+ */
+#include "arm64_gcc/bcm283x/chip_kernel.h"
+
+#endif /* TOPPERS_TARGET_KERNEL_H */
Index: /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_kernel.trb
===================================================================
--- /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_kernel.trb	(revision 384)
+++ /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_kernel.trb	(revision 384)
@@ -0,0 +1,9 @@
+# -*- coding: utf-8 -*-
+#
+#    ãã¹2ã®çæã¹ã¯ãªããã®ã¿ã¼ã²ããä¾å­é¨
+#
+
+IncludeTrb("arm64_gcc/bcm283x/chip_kernel.trb")
+IncludeTrb("syssvc/banner.trb")
+
+
Index: /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_rename.def
===================================================================
--- /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_rename.def	(revision 384)
+++ /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_rename.def	(revision 384)
@@ -0,0 +1,5 @@
+# target_config.c
+target_initialize
+target_exit
+
+INCLUDE	"arm64_gcc/bcm283x/chip"
Index: /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_rename.h
===================================================================
--- /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_rename.h	(revision 384)
+++ /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_rename.h	(revision 384)
@@ -0,0 +1,26 @@
+/* This file is generated from target_rename.def by genrename. */
+
+#ifndef TOPPERS_TARGET_RENAME_H
+#define TOPPERS_TARGET_RENAME_H
+
+/*
+ *  target_config.c
+ */
+#define target_initialize			_kernel_target_initialize
+#define target_exit					_kernel_target_exit
+
+
+#ifdef TOPPERS_LABEL_ASM
+
+/*
+ *  target_config.c
+ */
+#define _target_initialize			__kernel_target_initialize
+#define _target_exit				__kernel_target_exit
+
+
+#endif /* TOPPERS_LABEL_ASM */
+
+#include "arm64_gcc/bcm283x/chip_rename.h"
+
+#endif /* TOPPERS_TARGET_RENAME_H */
Index: /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_serial.cfg
===================================================================
--- /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_serial.cfg	(revision 384)
+++ /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_serial.cfg	(revision 384)
@@ -0,0 +1,7 @@
+/*
+ *  SIOãã©ã¤ãã®ã³ã³ãã£ã°ã¬ã¼ã·ã§ã³ãã¡ã¤ã«
+ */
+
+#include "target_serial.h"
+
+INCLUDE("arm64_gcc/bcm283x/chip_serial.cfg");
Index: /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_serial.h
===================================================================
--- /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_serial.h	(revision 384)
+++ /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_serial.h	(revision 384)
@@ -0,0 +1,68 @@
+/*
+ *  TOPPERS/SSP Kernel
+ *      Smallest Set Profile Kernel
+ *
+ *  Copyright (C) 2007 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2015,2018,2019 by Naoki Saito
+ *              Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ */
+
+/*
+ *  ã·ãªã¢ã«I/Oããã¤ã¹(SIO)ãã©ã¤ã
+ */
+
+#ifndef TOPPERS_TARGET_SERIAL_H
+#define TOPPERS_TARGET_SERIAL_H
+
+/*
+ *  ãããä¾å­é¨å®ç¾©
+ */
+#include "arm64_gcc/bcm283x/chip_serial.h"
+
+#endif /* TOPPERS_TARGET_SERIAL_H */
Index: /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_sil.h
===================================================================
--- /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_sil.h	(revision 384)
+++ /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_sil.h	(revision 384)
@@ -0,0 +1,75 @@
+/*
+ *  TOPPERS Software
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *
+ *  Copyright (C) 2007 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2018,2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ */
+
+/*
+ *  sil.hã®ã¿ã¼ã²ããä¾å­é¨ï¼RPI-ARM64ï¼
+ *
+ *  ãã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«ã¯ï¼sil.hã®å
+é ­ã§ã¤ã³ã¯ã«ã¼ããããï¼ä»ã®ãã¡
+ *  ã¤ã«ããã¯ç´æ¥ã¤ã³ã¯ã«ã¼ããããã¨ã¯ãªãï¼ãã®ãã¡ã¤ã«ãã¤ã³ã¯ã«ã¼
+ *  ãããåã«ï¼t_stddef.hãã¤ã³ã¯ã«ã¼ããããã®ã§ï¼ãããã«ä¾å­ãã¦ã
+ *  ããï¼
+ */
+
+#ifndef TOPPERS_TARGET_SIL_H
+#define TOPPERS_TARGET_SIL_H
+
+/*
+ *  ãããã®å
+±éå®ç¾©
+ */
+#include "arm64_gcc/bcm283x/chip_sil.h"
+
+#endif /* TOPPERS_TARGET_SIL_H */
Index: /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_stddef.h
===================================================================
--- /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_stddef.h	(revision 384)
+++ /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_stddef.h	(revision 384)
@@ -0,0 +1,103 @@
+/*
+ *  TOPPERS Software
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *
+ *  Copyright (C) 2007 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2018,2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ */
+
+/*
+ *  t_stddef.hã®ã¿ã¼ã²ããä¾å­é¨(RPI-ARM64)
+ *
+ *  ãã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«ã¯ï¼t_stddef.hã®å
+é ­ã§ã¤ã³ã¯ã«ã¼ããããï¼
+ *  ä»ã®ãã¡ã¤ã«ããã¯ç´æ¥ã¤ã³ã¯ã«ã¼ããããã¨ã¯ãªãï¼ä»ã®ã¤ã³ã¯ã«ã¼ã
+ *  ãã¡ã¤ã«ã«å
+ç«ã£ã¦å¦çãããããï¼ä»ã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«ã«ä¾å­ã
+ *  ã¦ã¯ãªããªãï¼
+ */
+
+#ifndef TOPPERS_TARGET_STDDEF_H
+#define TOPPERS_TARGET_STDDEF_H
+
+/*
+ *  ã¿ã¼ã²ãããè­å¥ããããã®ãã¯ã­ã®å®ç¾©
+ */
+#define TOPPERS_RPI_ARM64			/* ã·ã¹ãã ç¥ç§° */
+
+
+/*
+ *  éçºç°å¢ã§å
+±éãªå®ç¾©
+ */
+#define TOPPERS_STDFLOAT_TYPE1
+#include "gcc/tool_stddef.h"
+
+/*
+ *  ãã­ã»ããµã§å
+±éãªå®ç¾©
+ */
+#include "arm64_gcc/bcm283x/chip_stddef.h"
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ *  ã¢ãµã¼ã·ã§ã³ã®å¤±ææã®å®è¡ä¸­æ­å¦ç
+ */
+Inline void
+TOPPERS_assert_abort(void)
+{
+	while(1)
+	{
+	}
+}
+
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_TARGET_STDDEF_H */
Index: /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_sym.def
===================================================================
--- /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_sym.def	(revision 384)
+++ /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_sym.def	(revision 384)
@@ -0,0 +1,1 @@
+TMAX_INTPRI,,signed
Index: /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_syssvc.h
===================================================================
--- /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_syssvc.h	(revision 384)
+++ /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_syssvc.h	(revision 384)
@@ -0,0 +1,104 @@
+/*
+ *  TOPPERS/SSP Kernel
+ *      Smallest Set Profile Kernel
+ *
+ *  Copyright (C) 2007 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2015,2018,2019 by Naoki Saito
+ *              Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ */
+
+/*
+ *  ã·ã¹ãã ãµã¼ãã¹ã®ã¿ã¼ã²ããä¾å­é¨(RPI-ARM64ç¨)
+ *
+ *  ã·ã¹ãã ãµã¼ãã¹ã®ã¿ã¼ã²ããä¾å­é¨ã®ã¤ã³ã¯ã«ã¼ããã¡ã¤ã«ï¼
+ */
+
+#ifndef TOPPERS_TARGET_SYSSVC_H
+#define TOPPERS_TARGET_SYSSVC_H
+
+/*
+ *  ãã¬ã¼ã¹ã­ã°ã«é¢ããè¨­å®
+ */
+#ifdef TOPPERS_TRACE_ENABLE
+#include "logtrace/trace_config.h"
+#endif /* TOPPERS_TRACE_ENABLE */
+
+/*
+ *  èµ·åã¡ãã»ã¼ã¸ã®ã¿ã¼ã²ããã·ã¹ãã å
+ */
+#define TARGET_NAME    "RPI_ARM64"
+
+/*
+ *  èµ·åã¡ãã»ã¼ã¸ã«ã¿ã¼ã²ããä¾å­é¨ã®èä½æ¨©è¡¨ç¤ºã
+ *  è¿½å ããããã®ãã¯ã­ï¼
+ */
+#ifdef PRC_COPYRIGHT
+#define TARGET_COPYRIGHT	PRC_COPYRIGHT
+#endif /* PRC_COPYRIGHT */
+
+/*
+ *  ã·ã¹ãã ã­ã°ã®ä½ã¬ãã«åºåã®ããã®æå­åºå
+ *
+ *  ã¿ã¼ã²ããä¾å­ã®æ¹æ³ã§ï¼æå­cãè¡¨ç¤º/åºå/ä¿å­ããï¼
+ */
+extern void	target_fput_log(char c);
+
+/*
+ *  ãµãã¼ãããã·ãªã¢ã«ãã¼ãã®æ°
+ */
+#define TNUM_PORT        (1)
+#define TNUM_SIOP        (1)
+
+/*
+ *  ä½¿ç¨ããã·ãªã¢ã«ãã¼ãID
+ */
+#define SIO_PORTID		(1)
+
+
+#endif /* TOPPERS_TARGET_SYSSVC_H */
Index: /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_test.h
===================================================================
--- /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_test.h	(revision 384)
+++ /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_test.h	(revision 384)
@@ -0,0 +1,76 @@
+/*
+ *  TOPPERS/SSP Kernel
+ *      Smallest Set Profile Kernel
+ *
+ *  Copyright (C) 2007 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2015,2018,2019 by Naoki Saito
+ *              Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ */
+
+/*
+ *    ãã¹ããã­ã°ã©ã ã®ã¿ã¼ã²ããä¾å­å®ç¾©(RPI-ARM64)
+ */
+
+#ifndef TOPPERS_TARGET_TEST_H
+#define TOPPERS_TARGET_TEST_H
+
+#define STACK_SIZE       (1024U)
+#define ALL_STACKSIZE    (20480U)
+
+/*
+ *  ä½¿ç¨ããã·ãªã¢ã«ãã¼ãID
+ */
+#define TASK_PORTID      (1)
+
+/*
+ *  ãããä¾å­ã¢ã¸ã¥ã¼ã«(BCM2837ç¨)
+ */
+#include "arm64_gcc/bcm283x/chip_test.h"
+
+#endif /* TOPPERS_TARGET_TEST_H */
Index: /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_timer.cfg
===================================================================
--- /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_timer.cfg	(revision 384)
+++ /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_timer.cfg	(revision 384)
@@ -0,0 +1,7 @@
+/*
+ *  ã¿ã¤ããã©ã¤ãã®ã³ã³ãã£ã®ã¥ã¬ã¼ã·ã§ã³ãã¡ã¤ã«
+ */
+
+#include "target_timer.h"
+
+INCLUDE("arm64_gcc/bcm283x/chip_timer.cfg");
Index: /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_timer.h
===================================================================
--- /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_timer.h	(revision 384)
+++ /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_timer.h	(revision 384)
@@ -0,0 +1,75 @@
+/*
+ *  TOPPERS/SSP Kernel
+ *      Smallest Set Profile Kernel
+ *
+ *  Copyright (C) 2007 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2018,2019 by Naoki Saito
+ *             Nagoya Municipal Industrial Research Institute, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ */
+
+/*
+ *  ã¿ã¤ããã©ã¤ã(RPI-ARM64ç¨)
+ */
+
+#ifndef TOPPERS_TARGET_TIMER_H
+#define TOPPERS_TARGET_TIMER_H
+
+/*
+ *  ã¿ã¤ãå²è¾¼ã¿ãã³ãã©ç»é²ã®ããã®å®æ°
+ */
+#define INTPRI_TIMER    (-6)          /* å²è¾¼ã¿åªå
+åº¦ */
+#define INTATR_TIMER    TA_NULL       /* å²è¾¼ã¿å±æ§ */
+
+/*
+ *  ãããä¾å­é¨ã®å®ç¾©
+ */
+#include "arm64_gcc/bcm283x/chip_timer.h"
+
+#endif /* TOPPERS_TARGET_TIMER_H */
Index: /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_unrename.h
===================================================================
--- /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_unrename.h	(revision 384)
+++ /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_unrename.h	(revision 384)
@@ -0,0 +1,27 @@
+/* This file is generated from target_rename.def by genrename. */
+
+/* This file is included only when target_rename.h has been included. */
+#ifdef TOPPERS_TARGET_RENAME_H
+#undef TOPPERS_TARGET_RENAME_H
+
+/*
+ *  target_config.c
+ */
+#undef target_initialize
+#undef target_exit
+
+
+#ifdef TOPPERS_LABEL_ASM
+
+/*
+ *  target_config.c
+ */
+#undef _target_initialize
+#undef _target_exit
+
+
+#endif /* TOPPERS_LABEL_ASM */
+
+#include "arm64_gcc/bcm283x/chip_unrename.h"
+
+#endif /* TOPPERS_TARGET_RENAME_H */
Index: /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_user.txt
===================================================================
--- /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_user.txt	(revision 384)
+++ /ssp_rpi3/trunk/target/rpi_arm64_gcc/target_user.txt	(revision 384)
@@ -0,0 +1,252 @@
+=====================================================================
+                 RPI-ARM64ã¿ã¼ã²ããä¾å­é¨ (ssp-1.3.0å¯¾å¿ï¼
+                               Last Modified: '19/04/16
+=====================================================================
+
+(1) æ¦è¦
+
+RPI-ARM64ã¿ã¼ã²ããä¾å­é¨ã¯ï¼ãã­ã»ããµã«BCM2837(Cortex-A53ã³ã¢)ãæ­è¼ãã
+Raspberry Pi3B ãã¼ãããµãã¼ããã¦ããï¼
+
+
+(2) ã«ã¼ãã«ã®ä½¿ç¨ãªã½ã¼ã¹
+
+  ã»RAM
+     ã³ã¼ãããã³ãã¼ã¿ãé
+ç½®ããï¼
+     ä½¿ç¨éã¯ãªãã¸ã§ã¯ãæ°ã«ä¾å­ããï¼
+  ã»Generic Timer
+     ã«ã¼ãã«å
+é¨ã®ãã£ãã¯ã®çæã«ç¨ããï¼
+  ã»UART0 (PL011)
+     ã³ã³ã½ã¼ã«ã®åºåã«ä½¿ç¨
+
+
+(3) éçºç°å¢
+
+å®è¡ãã¡ã¤ã«ã®æ§ç¯ã«ã¯GCCéçºç°å¢ãç¨ãã(åä½ç¢ºèªãã¼ã¸ã§ã³: 7.2.1)
+GCC ã¯ä»¥ä¸ã®ãµã¤ããããã¤ããªããã±ã¼ã¸ããã¦ã³ã­ã¼ããããã¨ãã§ããï¼
+  https://releases.linaro.org/components/toolchain/binaries/
+
+
+(4) ãããã°ç°å¢
+
+ãããã°ç°å¢ã¨ãã¦ï¼QEMUã®GDBãµã¼ãæ©è½ãå©ç¨ãã¦ï¼GDBã«ãããããã°ãå¯è½.
+ãã ãRaspberry Pi3 ã®ã¨ãã¥ã¬ã¼ã·ã§ã³ããµãã¼ãããqemuã¯2.12ä»¥éãä½¿ç¨ããå¿
+è¦ãããï¼
+
+
+(5) å®è¡ç°å¢
+
+å®è¡ãã¡ã¤ã«ãå«ãï¼èµ·åã«å¿
+è¦ãªä»¥ä¸ã®ãã¡ã¤ã«ãFAT32ãã©ã¼ãããããã
+ãã¤ã¯ã­SDã«ã¼ãã®ã«ã¼ãç´ä¸ã«ã³ãã¼ãï¼Raspberry Pi ã§èµ·åããï¼
+
+(5-1) bootcode.bin, start.elf
+   ä»¥ä¸ãã¼ã¸ãã bootcode.binã¨start.elfããã¦ã³ã­ã¼ãããï¼
+   https://github.com/raspberrypi/firmware/tree/master/boot
+  (ä¸è¨ã¯masterãã©ã³ãä»å±ã®ãã¡ã¤ã«ã§ãããï¼å¥ãã©ã³ãã®ååãã¡ã¤ã«ãé¸æãã¦ããã)
+
+(5-2) å®è¡ãã¡ã¤ã«
+   å®è¡ãã¡ã¤ã«ã®ãã¤ããªã¤ã¡ã¼ã¸ãä½¿ç¨ããï¼
+   ãã¤ããªã¤ã¡ã¼ã¸ã¯ãmake ssp.binããå®è¡ããã¨çæãããï¼
+   ãã¡ã¤ã«åã kernel.img ã¾ãã¯ kernel8.img ã«ãã¦ããã¨èªåçã«èª­ã¿è¾¼ã¾ããï¼
+
+(5-3) config.txt
+   èµ·åè¨­å®ãæå®ããããã®ãã­ã¹ããã¡ã¤ã«ï¼
+   ãããããï¼ä»¥ä¸ã®3è¡ãå«ããã­ã¹ããã¡ã¤ã«ãä½æããã°è¯ã
+      rm_control=0x200
+      kernel_old=1
+      disable_commandline_tags=1
+   ããã«å ãï¼å®è¡ãã¡ã¤ã«åã kernel.img, kernel8.img ä»¥å¤ã§ã³ãã¼ããå ´åã¯
+   ãã¡ã¤ã«ãæå®ããããã®è¡ãè¿½å ãã¦ããï¼
+      kernel=ssp.bin
+
+  ãã®ä»ï¼config.txt ã®å
+å®¹ã«ã¤ãã¦è©³ããã¯ä»¥ä¸ãåç
+§ã®ãã¨ï¼
+  https://www.raspberrypi.org/documentation/configuration/config-txt/
+
+(6) QEMUãç¨ããåä½ç¢ºèª
+
+(6-1) QEMUãç¨ããå®è¡ç¢ºèª
+
+QEMUãç¨ãã¦å®è¡ãã¡ã¤ã«ãåããå ´åï¼ä»¥ä¸ã®ããã«ã³ãã³ããå®è¡ããï¼
+ããã§å®è¡ãã¡ã¤ã«åã ssp ã¨ãã
+
+(å®è¡ä¾)
+$ qemu-system-aarch64 -M raspi3 -display none -serial stdio -kernel ssp
+
+TOPPERS/SSP Kernel 1.3.0  for RPi ARM64 (May 29 2018 , 15:51:44)
+Copyright (C) 2010 by Meika Sugimoto
+Copyright (C) 2010 by Naoki Saito
+            Nagoya Municipal Industrial Research Institute, JAPAN
+
+System logging task is started on port 1.
+Sample program starts.
+
+(ããã§ï¼ã1ããaãã¨ã¿ã¤ããã)
+
+#act_tsk(1)
+task1 is running (001).   |
+task1 is running (002).   |
+(ä»¥ä¸ç¥)
+
+
+(6-2) GDBã«ãããããã°æé 
+
+GDBãç¨ãããããã°ãè¡ãå ´åï¼ã·ã§ã«ã2ã¤ç¨æããï¼
+ä¸ã¤ã¯qemuãèµ·åãGDBãµã¼ãã¨ãã¦èµ·åããï¼
+
+(1ã¤ç®ã®ã·ã§ã«)
+$ qemu-system-aarch64 -M raspi3 -display none -serial stdio -s -S
+
+ããã§ localhost:1234 ã§GDBãµã¼ããæ¥ç¶ãå¾
+ã¡åããç¶æ
+ã«ãªãï¼
+
+ããä¸ã¤ã®ã·ã§ã«ã§GDBãèµ·åãï¼GDBãµã¼ãã«æ¥ç¶ããï¼
+
+(2ã¤ç®ã®ã·ã§ã«)
+$ aarch-elf-gdb ssp
+(gdb)
+
+ããã§åç¨®ã®è¨­å®ï¼ãµã¼ãã¸ã®æ¥ç¶ï¼ã­ã¼ããè¡ãã¨ã¹ããããå®è¡ç­ã®
+ãããã°åä½ãè¡ããã¨ãã§ããï¼
+
+(gdb) set architecture aarch64
+The target architecture is assumed to be aarch64
+(gdb) set debug aarch64
+(gdb) target extended-remote localhost:1234
+Remote debugging using localhost:1234
+0x0000000000000000 in ?? ()
+(gdb) load
+Loading section .note.gnu.build-id, size 0x24 lma 0x0
+Loading section .text, size 0x5040 lma 0x40000000
+Loading section .rodata, size 0x650 lma 0x40005040
+Loading section .rodata.str1.8, size 0x5b8 lma 0x40005690
+Loading section .data, size 0x8 lma 0x40005c48
+Start address 0x40000000, load size 23668
+Transfer rate: 11556 KB/sec, 1577 bytes/write.
+(gdb) s
+aarch64: prologue analysis gave up addr=0x0x40000000 opcode=0xd50343df
+58	    ldr x0, =vectors
+(gdb) c
+Continuing.
+
+'c' ã³ãã³ãã§å®è¡ãç¶ç¶ããã¨ï¼GDBãµã¼ãå´ã®ç»é¢ã«ã·ãªã¢ã«ã¡ãã»ã¼ã¸ãè¡¨ç¤ºãããï¼
+ã­ã¼å
+¥åããµã¼ãå´ã®ã·ã§ã«ç»é¢ã§è¡ãï¼
+
+'c' ã³ãã³ãã«ããç¶ç¶ä¸­ã®å®è¡ãåæ­¢ããå ´åã¯Ctrl-Cã§çµäºããï¼
+gdb ãçµäºããå ´åã¯ãã­ã³ããã§'q'ã³ãã³ããå®è¡ãã¦çµäºããï¼
+
+
+(7) ã¿ã¼ã²ããä¾å­é¨ã®å®è£
+
+
+(7-1) ã¿ã¼ã²ããç¥ç§°
+
+ã·ã¹ãã ç¥ç§°åã³ã¿ã¼ã²ããç¥ç§°ã¯ä»¥ä¸ã®éãï¼
+
+ã·ã¹ãã ç¥ç§°: rpi_arm64
+ã¿ã¼ã²ããç¥ç§°: rpi_arm64_gcc ã§ãã
+
+
+(7-2) å²è¾¼ã¿åªå
+åº¦ã®ç¯å²
+
+BCM2837ã®å²è¾¼ã¿ã³ã³ãã­ã¼ã©ã¯åªå
+åº¦å¶å¾¡ã®æ©è½ãæããªããã
+ã½ããã¦ã§ã¢ã§æ¬ä¼¼çã«å®è£
+ãã¦ããï¼ãã®ãã
+å²è¾¼ã¿åªå
+åº¦ã¯ç¬èªã«æå®å¯è½ã§ããï¼ãããä¾å­é¨ã§ã¯æ¢å®å¤ã¨ãã¦ -15 ã -1 ã«å®ç¾©ãã¦ããï¼
+
+å²è¾¼ã¿åªå
+åº¦ã®æé«å¤(å¤ã¨ãã¦ã¯æå°å¤)ãã¿ã¼ã²ããä¾å­é¨ã§ç¬èªã«å®ç¾©ããå ´åï¼
+target_kernel.h ã« TMIN_INTPRI ããã¯ã­å®ç¾©ããï¼
+
+
+(7-3) ã¿ã¤ã ãã£ãã¯ã®å®ç¾©
+
+TIC_NUMEããã³TIC_DENOã®å¤ã¯æ¢å®å¤ã¨ãã¦ã³ã¢ä¾å­é¨ã§å
+±ã«1ã«å®ç¾©ãã¦ããï¼
+ã¿ã¼ã²ããä¾å­é¨ã§ç¬èªã«å®ç¾©ããå ´åã¯ target_kernel.h ã«ãã¯ã­å®ç¾©ããï¼
+
+(7-4) ã¹ã¿ã¼ãã¢ããã«ã¼ãã³ã§ã®åæåå
+å®¹
+
+Raspberry Pi ã®å ´åï¼ä»¥ä¸ã®ç¶æ
+ã§ã·ã¹ãã ãéå§ããï¼
+ã»ä¾å¤ã¬ãã«ï¼EL3
+ã»ä½¿ç¨ã¹ã¿ãã¯: SP_EL3 (EL3h)
+ã»ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿ã®Fãããåã³Iãããã¯1ï¼IRQ,FIQç¦æ­¢ï¼
+
+ãã®ããã¹ã¿ã¼ãã¢ããã«ã¼ãã³ã§ã¯ï¼ä»¥ä¸ã®å¦çãè¡ãªã£ãå¾ï¼sta_ker ãå¼ã³åºãï¼
+ã»EL3h(AArch64)ããEL1h(AArch64)ã¸ã®ç§»è¡
+ã»ã¹ã¿ãã¯ãã¤ã³ã¿åã³ãã¬ã¼ã ãã¤ã³ã¿ã®åæå
+ã»ãã¯ã¿ãã¼ãã«ã¢ãã¬ã¹ã®è¨­å®
+ã»bssã»ã¯ã·ã§ã³ã®ã¯ãªã¢
+
+
+(7-5) ã³ã³ã½ã¼ã«åºå
+
+ã³ã³ã½ã¼ã«åºåã«ã¯ PrimeCell UART (PL011)ãä½¿ç¨ããï¼
+ä»¥ä¸ã®éä¿¡ãã©ã¼ããããä½¿ç¨ããï¼
+  ã»115200bps, Data 8bit, Parity none, Stop 1bit, Flowå¶å¾¡ãªã
+
+
+(8) åãã¡ã¤ã«ã§ã®è¨­å®é 
+ç®(å¿
+è¦ã«å¿ãã¦ï¼å®ç¾©ãç·¨éãã)
+
+(8-1) Makefile.target
+
+ã»GCC_TARGET
+    GCCã® target triplet ãå®ç¾©
+ã»COPTS
+    Cã³ã³ãã¤ã©ã¸ã®ãªãã·ã§ã³
+ã»CDEFS
+    è¿½å ã®ãã¯ã­å®ç¾©
+ã»INCLUDES
+    ã¤ã³ã¯ã«ã¼ãæå®
+ã»LDFLAGS
+    ãªã³ã«ã¸ã®ãªãã·ã§ã³
+ã»LIBS
+    ãªã³ã¯ããã©ã¤ãã©ãª
+
+ã»TEXT_START_ADDRESS
+    ãã­ã¹ãã»ã¯ã·ã§ã³ã®éå§ã¢ãã¬ã¹
+
+(8-2) target_config.h
+
+ã»DEFAULT_ISTKSZ
+    ããã©ã«ãã®éã¿ã¹ã¯ã³ã³ãã­ã¹ãç¨ã®ã¹ã¿ãã¯ãµã¤ãº
+
+(8-4) target_kernel.h
+
+ã»TMIN_INTPRI
+    å²è¾¼ã¿åªå
+åº¦ã®æé«å¤(æå°å¤)
+ã»TIC_NUME, TIC_DENO
+    ã¿ã¤ã ãã£ãã¯ã®å¨æã®åå­ï¼åæ¯
+
+(8-3) target_test.h
+
+ã»STACK_SIZE
+    ãµã³ãã«ãã­ã°ã©ã ã®ã¿ã¹ã¯ã®ã¹ã¿ãã¯ãµã¤ãº
+ã»ALL_STACKSIZE
+    å
+±æã¹ã¿ãã¯é åã®ãµã¤ãº
+
+(8-4) target_timer.h
+ã»INTPRI_TIMER
+    ã¿ã¤ãã¼ã®å²è¾¼ã¿åªå
+åº¦
+ã»INTATR_TIMER
+    ã¿ã¤ãã¼ã®å²è¾¼ã¿å±æ§
+
+âå¤æ´å±¥æ­´
+ ã»2019/04/16
+ããæ°è¦ä½æ
