Changeset 374 for asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/us_ticker.c
- Timestamp:
- Apr 5, 2019, 9:26:53 PM (5 years ago)
- Location:
- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX
- Files:
-
- 1 added
- 1 copied
Legend:
- Unmodified
- Added
- Removed
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asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/us_ticker.c
r373 r374 14 14 * limitations under the License. 15 15 */ 16 #include <stddef.h>17 16 #include "us_ticker_api.h" 18 #include "PeripheralNames.h" 19 #include "ostm_iodefine.h" 17 #include "mbed_drv_cfg.h" 20 18 21 #include "RZ_A1_Init.h" 22 #include "MBRZA1H.h" 23 #include "vfp_neon_push_pop.h" 19 #define SHIFT_NUM 5 /* P0/32 */ 24 20 25 #define US_TICKER_TIMER_IRQn (OSTMI1TINT_IRQn) 26 #define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */ 21 static int us_ticker_inited = 0; 27 22 28 #define US_TICKER_CLOCK_US_DEV (1000000) 29 30 int us_ticker_inited = 0; 31 static double count_clock = 0; 32 static uint32_t last_read = 0; 33 static uint32_t wrap_arround = 0; 34 static uint64_t ticker_us_last64 = 0; 35 static uint64_t set_cmp_val64 = 0; 36 static uint64_t timestamp64 = 0; 37 38 void us_ticker_interrupt(void) { 39 us_ticker_irq_handler(); 40 } 41 42 void us_ticker_init(void) { 43 if (us_ticker_inited) return; 44 us_ticker_inited = 1; 45 46 /* set Counter Clock(us) */ 47 if (false == RZ_A1_IsClockMode0()) { 48 count_clock = ((double)CM1_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV); 49 } else { 50 count_clock = ((double)CM0_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV); 51 } 23 void us_ticker_init(void) 24 { 25 GIC_DisableIRQ(OSTMI1TINT_IRQn); 26 GIC_ClearPendingIRQ(OSTMI1TINT_IRQn); 52 27 53 28 /* Power Control for Peripherals */ 54 29 CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP50); /* enable OSTM1 clock */ 30 31 if (us_ticker_inited) return; 32 us_ticker_inited = 1; 55 33 56 34 // timer settings … … 58 36 OSTM1CTL = 0x02; /* Free running timer mode. Interrupt disabled when star counter */ 59 37 60 OSTM1TS = 0x1; /* Start the counter and sets the OSTM0TE bit. */38 OSTM1TS = 0x1; /* Start the counter and sets the OSTM0TE bit. */ 61 39 62 40 // INTC settings 63 InterruptHandlerRegister( US_TICKER_TIMER_IRQn, (void (*)(uint32_t))us_ticker_interrupt);64 GIC_SetPriority( US_TICKER_TIMER_IRQn, 5);65 GIC_ EnableIRQ(US_TICKER_TIMER_IRQn);41 InterruptHandlerRegister(OSTMI1TINT_IRQn, (void (*)(uint32_t))us_ticker_irq_handler); 42 GIC_SetPriority(OSTMI1TINT_IRQn, 5); 43 GIC_SetConfiguration(OSTMI1TINT_IRQn, 3); 66 44 } 67 45 68 static uint64_t ticker_read_counter64(void) { 69 uint32_t cnt_val; 70 uint64_t cnt_val64; 46 void us_ticker_free(void) 47 { 48 GIC_DisableIRQ(OSTMI1TINT_IRQn); 49 GIC_ClearPendingIRQ(OSTMI1TINT_IRQn); 71 50 72 if (!us_ticker_inited) 73 us_ticker_init(); 74 75 /* read counter */ 76 cnt_val = OSTM1CNT; 77 if (last_read > cnt_val) { 78 wrap_arround++; 79 } 80 last_read = cnt_val; 81 cnt_val64 = ((uint64_t)wrap_arround << 32) + cnt_val; 82 83 return cnt_val64; 51 /* Power Control for Peripherals */ 52 CPGSTBCR5 |= (CPG_STBCR5_BIT_MSTP50); /* disable OSTM1 clock */ 84 53 } 85 54 86 static void us_ticker_read_last(void) { 87 uint64_t cnt_val64; 88 89 cnt_val64 = ticker_read_counter64(); 90 91 ticker_us_last64 = (cnt_val64 / count_clock); 55 uint32_t us_ticker_read() 56 { 57 return (uint32_t)(OSTM1CNT >> SHIFT_NUM); 92 58 } 93 59 94 uint32_t us_ticker_read() { 95 int check_irq_masked; 96 97 #if defined ( __ICCARM__) 98 check_irq_masked = __disable_irq_iar(); 99 #else 100 check_irq_masked = __disable_irq(); 101 #endif /* __ICCARM__ */ 102 103 __vfp_neon_push(); 104 us_ticker_read_last(); 105 __vfp_neon_pop(); 106 107 if (!check_irq_masked) { 108 __enable_irq(); 109 } 110 111 /* clock to us */ 112 return (uint32_t)ticker_us_last64; 60 void us_ticker_set_interrupt(timestamp_t timestamp) 61 { 62 OSTM1CMP = (uint32_t)(timestamp << SHIFT_NUM); 63 GIC_EnableIRQ(OSTMI1TINT_IRQn); 113 64 } 114 65 115 static void us_ticker_calc_compare_match(void) { 116 set_cmp_val64 = timestamp64 * count_clock; 66 void us_ticker_fire_interrupt(void) 67 { 68 GIC_SetPendingIRQ(OSTMI1TINT_IRQn); 69 GIC_EnableIRQ(OSTMI1TINT_IRQn); 117 70 } 118 71 119 void us_ticker_set_interrupt(timestamp_t timestamp) { 120 // set match value 121 volatile uint32_t set_cmp_val; 122 uint64_t count_val_64; 123 124 /* calc compare mach timestamp */ 125 timestamp64 = (ticker_us_last64 & 0xFFFFFFFF00000000) + timestamp; 126 if (timestamp < (ticker_us_last64 & 0x00000000FFFFFFFF)) { 127 /* This event is wrap arround */ 128 timestamp64 += 0x100000000; 129 } 130 131 /* calc compare mach timestamp */ 132 __vfp_neon_push(); 133 us_ticker_calc_compare_match(); 134 __vfp_neon_pop(); 135 136 set_cmp_val = (uint32_t)(set_cmp_val64 & 0x00000000FFFFFFFF); 137 count_val_64 = ticker_read_counter64(); 138 if (set_cmp_val64 <= (count_val_64 + 500)) { 139 GIC_SetPendingIRQ(US_TICKER_TIMER_IRQn); 140 GIC_EnableIRQ(US_TICKER_TIMER_IRQn); 141 return; 142 } 143 OSTM1CMP = set_cmp_val; 144 GIC_EnableIRQ(US_TICKER_TIMER_IRQn); 72 void us_ticker_disable_interrupt(void) 73 { 74 GIC_DisableIRQ(OSTMI1TINT_IRQn); 145 75 } 146 76 147 void us_ticker_disable_interrupt(void) { 148 GIC_DisableIRQ(US_TICKER_TIMER_IRQn); 77 void us_ticker_clear_interrupt(void) 78 { 79 GIC_ClearPendingIRQ(OSTMI1TINT_IRQn); 149 80 } 150 81 151 void us_ticker_clear_interrupt(void) { 152 GIC_ClearPendingIRQ(US_TICKER_TIMER_IRQn); 82 const ticker_info_t* us_ticker_get_info() 83 { 84 static const ticker_info_t info = { 85 (uint32_t)((float)RENESAS_RZ_A1_P0_CLK / (float)(1 << SHIFT_NUM) + 0.5f), 86 (32 - SHIFT_NUM) 87 }; 88 return &info; 153 89 } 90
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