Index: asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/scux_iodefine.h
===================================================================
--- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/scux_iodefine.h	(revision 352)
+++ asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/scux_iodefine.h	(revision 374)
@@ -19,5 +19,5 @@
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
@@ -25,53 +25,419 @@
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef SCUX_IODEFINE_H
 #define SCUX_IODEFINE_H
 /* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_scux
-{                                                          /* SCUX             */
+#define SCUX    (*(struct st_scux    *)0xE8208000uL) /* SCUX */
+
+
+/* Start of channel array defines of SCUX */
+
+/* Channel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */
+#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT  (4)
+#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */
+#define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */
+#define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */
+#define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */
+
+
+/* Channel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */
+#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT  (2)
+#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */
+#define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */
+
+
+/* Channel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */
+#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT  (4)
+#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */
+#define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */
+#define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */
+#define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */
+
+
+/* Channel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */
+#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT  (4)
+#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */
+#define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */
+#define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */
+#define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */
+
+
+/* Channel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */
+#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT  (4)
+#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */
+#define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */
+#define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */
+#define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */
+
+
+/* Channel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */
+#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT  (4)
+#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */
+#define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */
+#define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */
+#define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */
+
+/* End of channel array defines of SCUX */
+
+
+#define SCUXIPCIR_IPC0_0 (SCUX.IPCIR_IPC0_0)
+#define SCUXIPSLR_IPC0_0 (SCUX.IPSLR_IPC0_0)
+#define SCUXIPCIR_IPC0_1 (SCUX.IPCIR_IPC0_1)
+#define SCUXIPSLR_IPC0_1 (SCUX.IPSLR_IPC0_1)
+#define SCUXIPCIR_IPC0_2 (SCUX.IPCIR_IPC0_2)
+#define SCUXIPSLR_IPC0_2 (SCUX.IPSLR_IPC0_2)
+#define SCUXIPCIR_IPC0_3 (SCUX.IPCIR_IPC0_3)
+#define SCUXIPSLR_IPC0_3 (SCUX.IPSLR_IPC0_3)
+#define SCUXOPCIR_OPC0_0 (SCUX.OPCIR_OPC0_0)
+#define SCUXOPSLR_OPC0_0 (SCUX.OPSLR_OPC0_0)
+#define SCUXOPCIR_OPC0_1 (SCUX.OPCIR_OPC0_1)
+#define SCUXOPSLR_OPC0_1 (SCUX.OPSLR_OPC0_1)
+#define SCUXOPCIR_OPC0_2 (SCUX.OPCIR_OPC0_2)
+#define SCUXOPSLR_OPC0_2 (SCUX.OPSLR_OPC0_2)
+#define SCUXOPCIR_OPC0_3 (SCUX.OPCIR_OPC0_3)
+#define SCUXOPSLR_OPC0_3 (SCUX.OPSLR_OPC0_3)
+#define SCUXFFDIR_FFD0_0 (SCUX.FFDIR_FFD0_0)
+#define SCUXFDAIR_FFD0_0 (SCUX.FDAIR_FFD0_0)
+#define SCUXDRQSR_FFD0_0 (SCUX.DRQSR_FFD0_0)
+#define SCUXFFDPR_FFD0_0 (SCUX.FFDPR_FFD0_0)
+#define SCUXFFDBR_FFD0_0 (SCUX.FFDBR_FFD0_0)
+#define SCUXDEVMR_FFD0_0 (SCUX.DEVMR_FFD0_0)
+#define SCUXDEVCR_FFD0_0 (SCUX.DEVCR_FFD0_0)
+#define SCUXFFDIR_FFD0_1 (SCUX.FFDIR_FFD0_1)
+#define SCUXFDAIR_FFD0_1 (SCUX.FDAIR_FFD0_1)
+#define SCUXDRQSR_FFD0_1 (SCUX.DRQSR_FFD0_1)
+#define SCUXFFDPR_FFD0_1 (SCUX.FFDPR_FFD0_1)
+#define SCUXFFDBR_FFD0_1 (SCUX.FFDBR_FFD0_1)
+#define SCUXDEVMR_FFD0_1 (SCUX.DEVMR_FFD0_1)
+#define SCUXDEVCR_FFD0_1 (SCUX.DEVCR_FFD0_1)
+#define SCUXFFDIR_FFD0_2 (SCUX.FFDIR_FFD0_2)
+#define SCUXFDAIR_FFD0_2 (SCUX.FDAIR_FFD0_2)
+#define SCUXDRQSR_FFD0_2 (SCUX.DRQSR_FFD0_2)
+#define SCUXFFDPR_FFD0_2 (SCUX.FFDPR_FFD0_2)
+#define SCUXFFDBR_FFD0_2 (SCUX.FFDBR_FFD0_2)
+#define SCUXDEVMR_FFD0_2 (SCUX.DEVMR_FFD0_2)
+#define SCUXDEVCR_FFD0_2 (SCUX.DEVCR_FFD0_2)
+#define SCUXFFDIR_FFD0_3 (SCUX.FFDIR_FFD0_3)
+#define SCUXFDAIR_FFD0_3 (SCUX.FDAIR_FFD0_3)
+#define SCUXDRQSR_FFD0_3 (SCUX.DRQSR_FFD0_3)
+#define SCUXFFDPR_FFD0_3 (SCUX.FFDPR_FFD0_3)
+#define SCUXFFDBR_FFD0_3 (SCUX.FFDBR_FFD0_3)
+#define SCUXDEVMR_FFD0_3 (SCUX.DEVMR_FFD0_3)
+#define SCUXDEVCR_FFD0_3 (SCUX.DEVCR_FFD0_3)
+#define SCUXFFUIR_FFU0_0 (SCUX.FFUIR_FFU0_0)
+#define SCUXFUAIR_FFU0_0 (SCUX.FUAIR_FFU0_0)
+#define SCUXURQSR_FFU0_0 (SCUX.URQSR_FFU0_0)
+#define SCUXFFUPR_FFU0_0 (SCUX.FFUPR_FFU0_0)
+#define SCUXUEVMR_FFU0_0 (SCUX.UEVMR_FFU0_0)
+#define SCUXUEVCR_FFU0_0 (SCUX.UEVCR_FFU0_0)
+#define SCUXFFUIR_FFU0_1 (SCUX.FFUIR_FFU0_1)
+#define SCUXFUAIR_FFU0_1 (SCUX.FUAIR_FFU0_1)
+#define SCUXURQSR_FFU0_1 (SCUX.URQSR_FFU0_1)
+#define SCUXFFUPR_FFU0_1 (SCUX.FFUPR_FFU0_1)
+#define SCUXUEVMR_FFU0_1 (SCUX.UEVMR_FFU0_1)
+#define SCUXUEVCR_FFU0_1 (SCUX.UEVCR_FFU0_1)
+#define SCUXFFUIR_FFU0_2 (SCUX.FFUIR_FFU0_2)
+#define SCUXFUAIR_FFU0_2 (SCUX.FUAIR_FFU0_2)
+#define SCUXURQSR_FFU0_2 (SCUX.URQSR_FFU0_2)
+#define SCUXFFUPR_FFU0_2 (SCUX.FFUPR_FFU0_2)
+#define SCUXUEVMR_FFU0_2 (SCUX.UEVMR_FFU0_2)
+#define SCUXUEVCR_FFU0_2 (SCUX.UEVCR_FFU0_2)
+#define SCUXFFUIR_FFU0_3 (SCUX.FFUIR_FFU0_3)
+#define SCUXFUAIR_FFU0_3 (SCUX.FUAIR_FFU0_3)
+#define SCUXURQSR_FFU0_3 (SCUX.URQSR_FFU0_3)
+#define SCUXFFUPR_FFU0_3 (SCUX.FFUPR_FFU0_3)
+#define SCUXUEVMR_FFU0_3 (SCUX.UEVMR_FFU0_3)
+#define SCUXUEVCR_FFU0_3 (SCUX.UEVCR_FFU0_3)
+#define SCUXSRCIR0_2SRC0_0 (SCUX.SRCIR0_2SRC0_0)
+#define SCUXSADIR0_2SRC0_0 (SCUX.SADIR0_2SRC0_0)
+#define SCUXSRCBR0_2SRC0_0 (SCUX.SRCBR0_2SRC0_0)
+#define SCUXIFSCR0_2SRC0_0 (SCUX.IFSCR0_2SRC0_0)
+#define SCUXIFSVR0_2SRC0_0 (SCUX.IFSVR0_2SRC0_0)
+#define SCUXSRCCR0_2SRC0_0 (SCUX.SRCCR0_2SRC0_0)
+#define SCUXMNFSR0_2SRC0_0 (SCUX.MNFSR0_2SRC0_0)
+#define SCUXBFSSR0_2SRC0_0 (SCUX.BFSSR0_2SRC0_0)
+#define SCUXSC2SR0_2SRC0_0 (SCUX.SC2SR0_2SRC0_0)
+#define SCUXWATSR0_2SRC0_0 (SCUX.WATSR0_2SRC0_0)
+#define SCUXSEVMR0_2SRC0_0 (SCUX.SEVMR0_2SRC0_0)
+#define SCUXSEVCR0_2SRC0_0 (SCUX.SEVCR0_2SRC0_0)
+#define SCUXSRCIR1_2SRC0_0 (SCUX.SRCIR1_2SRC0_0)
+#define SCUXSADIR1_2SRC0_0 (SCUX.SADIR1_2SRC0_0)
+#define SCUXSRCBR1_2SRC0_0 (SCUX.SRCBR1_2SRC0_0)
+#define SCUXIFSCR1_2SRC0_0 (SCUX.IFSCR1_2SRC0_0)
+#define SCUXIFSVR1_2SRC0_0 (SCUX.IFSVR1_2SRC0_0)
+#define SCUXSRCCR1_2SRC0_0 (SCUX.SRCCR1_2SRC0_0)
+#define SCUXMNFSR1_2SRC0_0 (SCUX.MNFSR1_2SRC0_0)
+#define SCUXBFSSR1_2SRC0_0 (SCUX.BFSSR1_2SRC0_0)
+#define SCUXSC2SR1_2SRC0_0 (SCUX.SC2SR1_2SRC0_0)
+#define SCUXWATSR1_2SRC0_0 (SCUX.WATSR1_2SRC0_0)
+#define SCUXSEVMR1_2SRC0_0 (SCUX.SEVMR1_2SRC0_0)
+#define SCUXSEVCR1_2SRC0_0 (SCUX.SEVCR1_2SRC0_0)
+#define SCUXSRCIRR_2SRC0_0 (SCUX.SRCIRR_2SRC0_0)
+#define SCUXSRCIR0_2SRC0_1 (SCUX.SRCIR0_2SRC0_1)
+#define SCUXSADIR0_2SRC0_1 (SCUX.SADIR0_2SRC0_1)
+#define SCUXSRCBR0_2SRC0_1 (SCUX.SRCBR0_2SRC0_1)
+#define SCUXIFSCR0_2SRC0_1 (SCUX.IFSCR0_2SRC0_1)
+#define SCUXIFSVR0_2SRC0_1 (SCUX.IFSVR0_2SRC0_1)
+#define SCUXSRCCR0_2SRC0_1 (SCUX.SRCCR0_2SRC0_1)
+#define SCUXMNFSR0_2SRC0_1 (SCUX.MNFSR0_2SRC0_1)
+#define SCUXBFSSR0_2SRC0_1 (SCUX.BFSSR0_2SRC0_1)
+#define SCUXSC2SR0_2SRC0_1 (SCUX.SC2SR0_2SRC0_1)
+#define SCUXWATSR0_2SRC0_1 (SCUX.WATSR0_2SRC0_1)
+#define SCUXSEVMR0_2SRC0_1 (SCUX.SEVMR0_2SRC0_1)
+#define SCUXSEVCR0_2SRC0_1 (SCUX.SEVCR0_2SRC0_1)
+#define SCUXSRCIR1_2SRC0_1 (SCUX.SRCIR1_2SRC0_1)
+#define SCUXSADIR1_2SRC0_1 (SCUX.SADIR1_2SRC0_1)
+#define SCUXSRCBR1_2SRC0_1 (SCUX.SRCBR1_2SRC0_1)
+#define SCUXIFSCR1_2SRC0_1 (SCUX.IFSCR1_2SRC0_1)
+#define SCUXIFSVR1_2SRC0_1 (SCUX.IFSVR1_2SRC0_1)
+#define SCUXSRCCR1_2SRC0_1 (SCUX.SRCCR1_2SRC0_1)
+#define SCUXMNFSR1_2SRC0_1 (SCUX.MNFSR1_2SRC0_1)
+#define SCUXBFSSR1_2SRC0_1 (SCUX.BFSSR1_2SRC0_1)
+#define SCUXSC2SR1_2SRC0_1 (SCUX.SC2SR1_2SRC0_1)
+#define SCUXWATSR1_2SRC0_1 (SCUX.WATSR1_2SRC0_1)
+#define SCUXSEVMR1_2SRC0_1 (SCUX.SEVMR1_2SRC0_1)
+#define SCUXSEVCR1_2SRC0_1 (SCUX.SEVCR1_2SRC0_1)
+#define SCUXSRCIRR_2SRC0_1 (SCUX.SRCIRR_2SRC0_1)
+#define SCUXDVUIR_DVU0_0 (SCUX.DVUIR_DVU0_0)
+#define SCUXVADIR_DVU0_0 (SCUX.VADIR_DVU0_0)
+#define SCUXDVUBR_DVU0_0 (SCUX.DVUBR_DVU0_0)
+#define SCUXDVUCR_DVU0_0 (SCUX.DVUCR_DVU0_0)
+#define SCUXZCMCR_DVU0_0 (SCUX.ZCMCR_DVU0_0)
+#define SCUXVRCTR_DVU0_0 (SCUX.VRCTR_DVU0_0)
+#define SCUXVRPDR_DVU0_0 (SCUX.VRPDR_DVU0_0)
+#define SCUXVRDBR_DVU0_0 (SCUX.VRDBR_DVU0_0)
+#define SCUXVRWTR_DVU0_0 (SCUX.VRWTR_DVU0_0)
+#define SCUXVOL0R_DVU0_0 (SCUX.VOL0R_DVU0_0)
+#define SCUXVOL1R_DVU0_0 (SCUX.VOL1R_DVU0_0)
+#define SCUXVOL2R_DVU0_0 (SCUX.VOL2R_DVU0_0)
+#define SCUXVOL3R_DVU0_0 (SCUX.VOL3R_DVU0_0)
+#define SCUXVOL4R_DVU0_0 (SCUX.VOL4R_DVU0_0)
+#define SCUXVOL5R_DVU0_0 (SCUX.VOL5R_DVU0_0)
+#define SCUXVOL6R_DVU0_0 (SCUX.VOL6R_DVU0_0)
+#define SCUXVOL7R_DVU0_0 (SCUX.VOL7R_DVU0_0)
+#define SCUXDVUER_DVU0_0 (SCUX.DVUER_DVU0_0)
+#define SCUXDVUSR_DVU0_0 (SCUX.DVUSR_DVU0_0)
+#define SCUXVEVMR_DVU0_0 (SCUX.VEVMR_DVU0_0)
+#define SCUXVEVCR_DVU0_0 (SCUX.VEVCR_DVU0_0)
+#define SCUXDVUIR_DVU0_1 (SCUX.DVUIR_DVU0_1)
+#define SCUXVADIR_DVU0_1 (SCUX.VADIR_DVU0_1)
+#define SCUXDVUBR_DVU0_1 (SCUX.DVUBR_DVU0_1)
+#define SCUXDVUCR_DVU0_1 (SCUX.DVUCR_DVU0_1)
+#define SCUXZCMCR_DVU0_1 (SCUX.ZCMCR_DVU0_1)
+#define SCUXVRCTR_DVU0_1 (SCUX.VRCTR_DVU0_1)
+#define SCUXVRPDR_DVU0_1 (SCUX.VRPDR_DVU0_1)
+#define SCUXVRDBR_DVU0_1 (SCUX.VRDBR_DVU0_1)
+#define SCUXVRWTR_DVU0_1 (SCUX.VRWTR_DVU0_1)
+#define SCUXVOL0R_DVU0_1 (SCUX.VOL0R_DVU0_1)
+#define SCUXVOL1R_DVU0_1 (SCUX.VOL1R_DVU0_1)
+#define SCUXVOL2R_DVU0_1 (SCUX.VOL2R_DVU0_1)
+#define SCUXVOL3R_DVU0_1 (SCUX.VOL3R_DVU0_1)
+#define SCUXVOL4R_DVU0_1 (SCUX.VOL4R_DVU0_1)
+#define SCUXVOL5R_DVU0_1 (SCUX.VOL5R_DVU0_1)
+#define SCUXVOL6R_DVU0_1 (SCUX.VOL6R_DVU0_1)
+#define SCUXVOL7R_DVU0_1 (SCUX.VOL7R_DVU0_1)
+#define SCUXDVUER_DVU0_1 (SCUX.DVUER_DVU0_1)
+#define SCUXDVUSR_DVU0_1 (SCUX.DVUSR_DVU0_1)
+#define SCUXVEVMR_DVU0_1 (SCUX.VEVMR_DVU0_1)
+#define SCUXVEVCR_DVU0_1 (SCUX.VEVCR_DVU0_1)
+#define SCUXDVUIR_DVU0_2 (SCUX.DVUIR_DVU0_2)
+#define SCUXVADIR_DVU0_2 (SCUX.VADIR_DVU0_2)
+#define SCUXDVUBR_DVU0_2 (SCUX.DVUBR_DVU0_2)
+#define SCUXDVUCR_DVU0_2 (SCUX.DVUCR_DVU0_2)
+#define SCUXZCMCR_DVU0_2 (SCUX.ZCMCR_DVU0_2)
+#define SCUXVRCTR_DVU0_2 (SCUX.VRCTR_DVU0_2)
+#define SCUXVRPDR_DVU0_2 (SCUX.VRPDR_DVU0_2)
+#define SCUXVRDBR_DVU0_2 (SCUX.VRDBR_DVU0_2)
+#define SCUXVRWTR_DVU0_2 (SCUX.VRWTR_DVU0_2)
+#define SCUXVOL0R_DVU0_2 (SCUX.VOL0R_DVU0_2)
+#define SCUXVOL1R_DVU0_2 (SCUX.VOL1R_DVU0_2)
+#define SCUXVOL2R_DVU0_2 (SCUX.VOL2R_DVU0_2)
+#define SCUXVOL3R_DVU0_2 (SCUX.VOL3R_DVU0_2)
+#define SCUXVOL4R_DVU0_2 (SCUX.VOL4R_DVU0_2)
+#define SCUXVOL5R_DVU0_2 (SCUX.VOL5R_DVU0_2)
+#define SCUXVOL6R_DVU0_2 (SCUX.VOL6R_DVU0_2)
+#define SCUXVOL7R_DVU0_2 (SCUX.VOL7R_DVU0_2)
+#define SCUXDVUER_DVU0_2 (SCUX.DVUER_DVU0_2)
+#define SCUXDVUSR_DVU0_2 (SCUX.DVUSR_DVU0_2)
+#define SCUXVEVMR_DVU0_2 (SCUX.VEVMR_DVU0_2)
+#define SCUXVEVCR_DVU0_2 (SCUX.VEVCR_DVU0_2)
+#define SCUXDVUIR_DVU0_3 (SCUX.DVUIR_DVU0_3)
+#define SCUXVADIR_DVU0_3 (SCUX.VADIR_DVU0_3)
+#define SCUXDVUBR_DVU0_3 (SCUX.DVUBR_DVU0_3)
+#define SCUXDVUCR_DVU0_3 (SCUX.DVUCR_DVU0_3)
+#define SCUXZCMCR_DVU0_3 (SCUX.ZCMCR_DVU0_3)
+#define SCUXVRCTR_DVU0_3 (SCUX.VRCTR_DVU0_3)
+#define SCUXVRPDR_DVU0_3 (SCUX.VRPDR_DVU0_3)
+#define SCUXVRDBR_DVU0_3 (SCUX.VRDBR_DVU0_3)
+#define SCUXVRWTR_DVU0_3 (SCUX.VRWTR_DVU0_3)
+#define SCUXVOL0R_DVU0_3 (SCUX.VOL0R_DVU0_3)
+#define SCUXVOL1R_DVU0_3 (SCUX.VOL1R_DVU0_3)
+#define SCUXVOL2R_DVU0_3 (SCUX.VOL2R_DVU0_3)
+#define SCUXVOL3R_DVU0_3 (SCUX.VOL3R_DVU0_3)
+#define SCUXVOL4R_DVU0_3 (SCUX.VOL4R_DVU0_3)
+#define SCUXVOL5R_DVU0_3 (SCUX.VOL5R_DVU0_3)
+#define SCUXVOL6R_DVU0_3 (SCUX.VOL6R_DVU0_3)
+#define SCUXVOL7R_DVU0_3 (SCUX.VOL7R_DVU0_3)
+#define SCUXDVUER_DVU0_3 (SCUX.DVUER_DVU0_3)
+#define SCUXDVUSR_DVU0_3 (SCUX.DVUSR_DVU0_3)
+#define SCUXVEVMR_DVU0_3 (SCUX.VEVMR_DVU0_3)
+#define SCUXVEVCR_DVU0_3 (SCUX.VEVCR_DVU0_3)
+#define SCUXMIXIR_MIX0_0 (SCUX.MIXIR_MIX0_0)
+#define SCUXMADIR_MIX0_0 (SCUX.MADIR_MIX0_0)
+#define SCUXMIXBR_MIX0_0 (SCUX.MIXBR_MIX0_0)
+#define SCUXMIXMR_MIX0_0 (SCUX.MIXMR_MIX0_0)
+#define SCUXMVPDR_MIX0_0 (SCUX.MVPDR_MIX0_0)
+#define SCUXMDBAR_MIX0_0 (SCUX.MDBAR_MIX0_0)
+#define SCUXMDBBR_MIX0_0 (SCUX.MDBBR_MIX0_0)
+#define SCUXMDBCR_MIX0_0 (SCUX.MDBCR_MIX0_0)
+#define SCUXMDBDR_MIX0_0 (SCUX.MDBDR_MIX0_0)
+#define SCUXMDBER_MIX0_0 (SCUX.MDBER_MIX0_0)
+#define SCUXMIXSR_MIX0_0 (SCUX.MIXSR_MIX0_0)
+#define SCUXSWRSR_CIM (SCUX.SWRSR_CIM)
+#define SCUXDMACR_CIM (SCUX.DMACR_CIM)
+#define SCUXDMATD0_CIM (SCUX.DMATD0_CIM.UINT32)
+#define SCUXDMATD0_CIML (SCUX.DMATD0_CIM.UINT16[R_IO_L])
+#define SCUXDMATD0_CIMH (SCUX.DMATD0_CIM.UINT16[R_IO_H])
+#define SCUXDMATD1_CIM (SCUX.DMATD1_CIM.UINT32)
+#define SCUXDMATD1_CIML (SCUX.DMATD1_CIM.UINT16[R_IO_L])
+#define SCUXDMATD1_CIMH (SCUX.DMATD1_CIM.UINT16[R_IO_H])
+#define SCUXDMATD2_CIM (SCUX.DMATD2_CIM.UINT32)
+#define SCUXDMATD2_CIML (SCUX.DMATD2_CIM.UINT16[R_IO_L])
+#define SCUXDMATD2_CIMH (SCUX.DMATD2_CIM.UINT16[R_IO_H])
+#define SCUXDMATD3_CIM (SCUX.DMATD3_CIM.UINT32)
+#define SCUXDMATD3_CIML (SCUX.DMATD3_CIM.UINT16[R_IO_L])
+#define SCUXDMATD3_CIMH (SCUX.DMATD3_CIM.UINT16[R_IO_H])
+#define SCUXDMATU0_CIM (SCUX.DMATU0_CIM.UINT32)
+#define SCUXDMATU0_CIML (SCUX.DMATU0_CIM.UINT16[R_IO_L])
+#define SCUXDMATU0_CIMH (SCUX.DMATU0_CIM.UINT16[R_IO_H])
+#define SCUXDMATU1_CIM (SCUX.DMATU1_CIM.UINT32)
+#define SCUXDMATU1_CIML (SCUX.DMATU1_CIM.UINT16[R_IO_L])
+#define SCUXDMATU1_CIMH (SCUX.DMATU1_CIM.UINT16[R_IO_H])
+#define SCUXDMATU2_CIM (SCUX.DMATU2_CIM.UINT32)
+#define SCUXDMATU2_CIML (SCUX.DMATU2_CIM.UINT16[R_IO_L])
+#define SCUXDMATU2_CIMH (SCUX.DMATU2_CIM.UINT16[R_IO_H])
+#define SCUXDMATU3_CIM (SCUX.DMATU3_CIM.UINT32)
+#define SCUXDMATU3_CIML (SCUX.DMATU3_CIM.UINT16[R_IO_L])
+#define SCUXDMATU3_CIMH (SCUX.DMATU3_CIM.UINT16[R_IO_H])
+#define SCUXSSIRSEL_CIM (SCUX.SSIRSEL_CIM)
+#define SCUXFDTSEL0_CIM (SCUX.FDTSEL0_CIM)
+#define SCUXFDTSEL1_CIM (SCUX.FDTSEL1_CIM)
+#define SCUXFDTSEL2_CIM (SCUX.FDTSEL2_CIM)
+#define SCUXFDTSEL3_CIM (SCUX.FDTSEL3_CIM)
+#define SCUXFUTSEL0_CIM (SCUX.FUTSEL0_CIM)
+#define SCUXFUTSEL1_CIM (SCUX.FUTSEL1_CIM)
+#define SCUXFUTSEL2_CIM (SCUX.FUTSEL2_CIM)
+#define SCUXFUTSEL3_CIM (SCUX.FUTSEL3_CIM)
+#define SCUXSSIPMD_CIM (SCUX.SSIPMD_CIM)
+#define SCUXSSICTRL_CIM (SCUX.SSICTRL_CIM)
+#define SCUXSRCRSEL0_CIM (SCUX.SRCRSEL0_CIM)
+#define SCUXSRCRSEL1_CIM (SCUX.SRCRSEL1_CIM)
+#define SCUXSRCRSEL2_CIM (SCUX.SRCRSEL2_CIM)
+#define SCUXSRCRSEL3_CIM (SCUX.SRCRSEL3_CIM)
+#define SCUXMIXRSEL_CIM (SCUX.MIXRSEL_CIM)
+
+#define SCUX_DMATDnCIM_COUNT (4)
+#define SCUX_DMATUnCIM_COUNT (4)
+#define SCUX_FDTSELnCIM_COUNT (4)
+#define SCUX_FUTSELnCIM_COUNT (4)
+#define SCUX_SRCRSELnCIM_COUNT (4)
+
+
+typedef struct st_scux
+{
+                                                           /* SCUX             */
+
 /* start of struct st_scux_from_ipcir_ipc0_n */
     volatile uint32_t  IPCIR_IPC0_0;                           /*  IPCIR_IPC0_0    */
     volatile uint32_t  IPSLR_IPC0_0;                           /*  IPSLR_IPC0_0    */
     volatile uint8_t   dummy259[248];                          /*                  */
+
 /* end of struct st_scux_from_ipcir_ipc0_n */
+
 /* start of struct st_scux_from_ipcir_ipc0_n */
     volatile uint32_t  IPCIR_IPC0_1;                           /*  IPCIR_IPC0_1    */
     volatile uint32_t  IPSLR_IPC0_1;                           /*  IPSLR_IPC0_1    */
     volatile uint8_t   dummy260[248];                          /*                  */
+
 /* end of struct st_scux_from_ipcir_ipc0_n */
+
 /* start of struct st_scux_from_ipcir_ipc0_n */
     volatile uint32_t  IPCIR_IPC0_2;                           /*  IPCIR_IPC0_2    */
     volatile uint32_t  IPSLR_IPC0_2;                           /*  IPSLR_IPC0_2    */
     volatile uint8_t   dummy261[248];                          /*                  */
+
 /* end of struct st_scux_from_ipcir_ipc0_n */
+
 /* start of struct st_scux_from_ipcir_ipc0_n */
     volatile uint32_t  IPCIR_IPC0_3;                           /*  IPCIR_IPC0_3    */
     volatile uint32_t  IPSLR_IPC0_3;                           /*  IPSLR_IPC0_3    */
     volatile uint8_t   dummy262[248];                          /*                  */
+
 /* end of struct st_scux_from_ipcir_ipc0_n */
+
 /* start of struct st_scux_from_opcir_opc0_n */
     volatile uint32_t  OPCIR_OPC0_0;                           /*  OPCIR_OPC0_0    */
     volatile uint32_t  OPSLR_OPC0_0;                           /*  OPSLR_OPC0_0    */
     volatile uint8_t   dummy263[248];                          /*                  */
+
 /* end of struct st_scux_from_opcir_opc0_n */
+
 /* start of struct st_scux_from_opcir_opc0_n */
     volatile uint32_t  OPCIR_OPC0_1;                           /*  OPCIR_OPC0_1    */
     volatile uint32_t  OPSLR_OPC0_1;                           /*  OPSLR_OPC0_1    */
     volatile uint8_t   dummy264[248];                          /*                  */
+
 /* end of struct st_scux_from_opcir_opc0_n */
+
 /* start of struct st_scux_from_opcir_opc0_n */
     volatile uint32_t  OPCIR_OPC0_2;                           /*  OPCIR_OPC0_2    */
     volatile uint32_t  OPSLR_OPC0_2;                           /*  OPSLR_OPC0_2    */
     volatile uint8_t   dummy265[248];                          /*                  */
+
 /* end of struct st_scux_from_opcir_opc0_n */
+
 /* start of struct st_scux_from_opcir_opc0_n */
     volatile uint32_t  OPCIR_OPC0_3;                           /*  OPCIR_OPC0_3    */
     volatile uint32_t  OPSLR_OPC0_3;                           /*  OPSLR_OPC0_3    */
     volatile uint8_t   dummy266[248];                          /*                  */
+
 /* end of struct st_scux_from_opcir_opc0_n */
+
 /* start of struct st_scux_from_ffdir_ffd0_n */
     volatile uint32_t  FFDIR_FFD0_0;                           /*  FFDIR_FFD0_0    */
@@ -83,6 +449,8 @@
     volatile uint8_t   dummy267[4];                            /*                  */
     volatile uint32_t  DEVCR_FFD0_0;                           /*  DEVCR_FFD0_0    */
+
 /* end of struct st_scux_from_ffdir_ffd0_n */
     volatile uint8_t   dummy268[224];                          /*                  */
+
 /* start of struct st_scux_from_ffdir_ffd0_n */
     volatile uint32_t  FFDIR_FFD0_1;                           /*  FFDIR_FFD0_1    */
@@ -94,6 +462,8 @@
     volatile uint8_t   dummy269[4];                            /*                  */
     volatile uint32_t  DEVCR_FFD0_1;                           /*  DEVCR_FFD0_1    */
+
 /* end of struct st_scux_from_ffdir_ffd0_n */
     volatile uint8_t   dummy270[224];                          /*                  */
+
 /* start of struct st_scux_from_ffdir_ffd0_n */
     volatile uint32_t  FFDIR_FFD0_2;                           /*  FFDIR_FFD0_2    */
@@ -105,6 +475,8 @@
     volatile uint8_t   dummy271[4];                            /*                  */
     volatile uint32_t  DEVCR_FFD0_2;                           /*  DEVCR_FFD0_2    */
+
 /* end of struct st_scux_from_ffdir_ffd0_n */
     volatile uint8_t   dummy272[224];                          /*                  */
+
 /* start of struct st_scux_from_ffdir_ffd0_n */
     volatile uint32_t  FFDIR_FFD0_3;                           /*  FFDIR_FFD0_3    */
@@ -116,6 +488,8 @@
     volatile uint8_t   dummy273[4];                            /*                  */
     volatile uint32_t  DEVCR_FFD0_3;                           /*  DEVCR_FFD0_3    */
+
 /* end of struct st_scux_from_ffdir_ffd0_n */
     volatile uint8_t   dummy274[224];                          /*                  */
+
 /* start of struct st_scux_from_ffuir_ffu0_n */
     volatile uint32_t  FFUIR_FFU0_0;                           /*  FFUIR_FFU0_0    */
@@ -126,6 +500,8 @@
     volatile uint8_t   dummy275[4];                            /*                  */
     volatile uint32_t  UEVCR_FFU0_0;                           /*  UEVCR_FFU0_0    */
+
 /* end of struct st_scux_from_ffuir_ffu0_n */
     volatile uint8_t   dummy276[228];                          /*                  */
+
 /* start of struct st_scux_from_ffuir_ffu0_n */
     volatile uint32_t  FFUIR_FFU0_1;                           /*  FFUIR_FFU0_1    */
@@ -136,6 +512,8 @@
     volatile uint8_t   dummy277[4];                            /*                  */
     volatile uint32_t  UEVCR_FFU0_1;                           /*  UEVCR_FFU0_1    */
+
 /* end of struct st_scux_from_ffuir_ffu0_n */
     volatile uint8_t   dummy278[228];                          /*                  */
+
 /* start of struct st_scux_from_ffuir_ffu0_n */
     volatile uint32_t  FFUIR_FFU0_2;                           /*  FFUIR_FFU0_2    */
@@ -146,6 +524,8 @@
     volatile uint8_t   dummy279[4];                            /*                  */
     volatile uint32_t  UEVCR_FFU0_2;                           /*  UEVCR_FFU0_2    */
+
 /* end of struct st_scux_from_ffuir_ffu0_n */
     volatile uint8_t   dummy280[228];                          /*                  */
+
 /* start of struct st_scux_from_ffuir_ffu0_n */
     volatile uint32_t  FFUIR_FFU0_3;                           /*  FFUIR_FFU0_3    */
@@ -156,6 +536,8 @@
     volatile uint8_t   dummy281[4];                            /*                  */
     volatile uint32_t  UEVCR_FFU0_3;                           /*  UEVCR_FFU0_3    */
+
 /* end of struct st_scux_from_ffuir_ffu0_n */
     volatile uint8_t   dummy282[228];                          /*                  */
+
 /* start of struct st_scux_from_srcir0_2src0_n */
     volatile uint32_t  SRCIR0_2SRC0_0;                         /*  SRCIR0_2SRC0_0  */
@@ -186,6 +568,8 @@
     volatile uint32_t  SEVCR1_2SRC0_0;                         /*  SEVCR1_2SRC0_0  */
     volatile uint32_t  SRCIRR_2SRC0_0;                         /*  SRCIRR_2SRC0_0  */
+
 /* end of struct st_scux_from_srcir0_2src0_n */
     volatile uint8_t   dummy285[148];                          /*                  */
+
 /* start of struct st_scux_from_srcir0_2src0_n */
     volatile uint32_t  SRCIR0_2SRC0_1;                         /*  SRCIR0_2SRC0_1  */
@@ -216,6 +600,8 @@
     volatile uint32_t  SEVCR1_2SRC0_1;                         /*  SEVCR1_2SRC0_1  */
     volatile uint32_t  SRCIRR_2SRC0_1;                         /*  SRCIRR_2SRC0_1  */
+
 /* end of struct st_scux_from_srcir0_2src0_n */
     volatile uint8_t   dummy288[148];                          /*                  */
+
 /* start of struct st_scux_from_dvuir_dvu0_n */
     volatile uint32_t  DVUIR_DVU0_0;                           /*  DVUIR_DVU0_0    */
@@ -241,6 +627,8 @@
     volatile uint8_t   dummy289[4];                            /*                  */
     volatile uint32_t  VEVCR_DVU0_0;                           /*  VEVCR_DVU0_0    */
+
 /* end of struct st_scux_from_dvuir_dvu0_n */
     volatile uint8_t   dummy290[168];                          /*                  */
+
 /* start of struct st_scux_from_dvuir_dvu0_n */
     volatile uint32_t  DVUIR_DVU0_1;                           /*  DVUIR_DVU0_1    */
@@ -266,6 +654,8 @@
     volatile uint8_t   dummy291[4];                            /*                  */
     volatile uint32_t  VEVCR_DVU0_1;                           /*  VEVCR_DVU0_1    */
+
 /* end of struct st_scux_from_dvuir_dvu0_n */
     volatile uint8_t   dummy292[168];                          /*                  */
+
 /* start of struct st_scux_from_dvuir_dvu0_n */
     volatile uint32_t  DVUIR_DVU0_2;                           /*  DVUIR_DVU0_2    */
@@ -291,6 +681,8 @@
     volatile uint8_t   dummy293[4];                            /*                  */
     volatile uint32_t  VEVCR_DVU0_2;                           /*  VEVCR_DVU0_2    */
+
 /* end of struct st_scux_from_dvuir_dvu0_n */
     volatile uint8_t   dummy294[168];                          /*                  */
+
 /* start of struct st_scux_from_dvuir_dvu0_n */
     volatile uint32_t  DVUIR_DVU0_3;                           /*  DVUIR_DVU0_3    */
@@ -316,4 +708,5 @@
     volatile uint8_t   dummy295[4];                            /*                  */
     volatile uint32_t  VEVCR_DVU0_3;                           /*  VEVCR_DVU0_3    */
+
 /* end of struct st_scux_from_dvuir_dvu0_n */
     volatile uint8_t   dummy296[168];                          /*                  */
@@ -332,10 +725,12 @@
     volatile uint32_t  SWRSR_CIM;                              /*  SWRSR_CIM       */
     volatile uint32_t  DMACR_CIM;                              /*  DMACR_CIM       */
-#define SCUX_DMATDn_CIM_COUNT 4
+
+/* #define SCUX_DMATDnCIM_COUNT (4) */
     union iodefine_reg32_16_t  DMATD0_CIM;                 /*  DMATD0_CIM      */
     union iodefine_reg32_16_t  DMATD1_CIM;                 /*  DMATD1_CIM      */
     union iodefine_reg32_16_t  DMATD2_CIM;                 /*  DMATD2_CIM      */
     union iodefine_reg32_16_t  DMATD3_CIM;                 /*  DMATD3_CIM      */
-#define SCUX_DMATUn_CIM_COUNT 4
+
+/* #define SCUX_DMATUnCIM_COUNT (4) */
     union iodefine_reg32_16_t  DMATU0_CIM;                 /*  DMATU0_CIM      */
     union iodefine_reg32_16_t  DMATU1_CIM;                 /*  DMATU1_CIM      */
@@ -345,10 +740,12 @@
     volatile uint8_t   dummy298[16];                           /*                  */
     volatile uint32_t  SSIRSEL_CIM;                            /*  SSIRSEL_CIM     */
-#define SCUX_FDTSELn_CIM_COUNT 4
+
+/* #define SCUX_FDTSELnCIM_COUNT (4) */
     volatile uint32_t  FDTSEL0_CIM;                            /*  FDTSEL0_CIM     */
     volatile uint32_t  FDTSEL1_CIM;                            /*  FDTSEL1_CIM     */
     volatile uint32_t  FDTSEL2_CIM;                            /*  FDTSEL2_CIM     */
     volatile uint32_t  FDTSEL3_CIM;                            /*  FDTSEL3_CIM     */
-#define SCUX_FUTSELn_CIM_COUNT 4
+
+/* #define SCUX_FUTSELnCIM_COUNT (4) */
     volatile uint32_t  FUTSEL0_CIM;                            /*  FUTSEL0_CIM     */
     volatile uint32_t  FUTSEL1_CIM;                            /*  FUTSEL1_CIM     */
@@ -357,5 +754,6 @@
     volatile uint32_t  SSIPMD_CIM;                             /*  SSIPMD_CIM      */
     volatile uint32_t  SSICTRL_CIM;                            /*  SSICTRL_CIM     */
-#define SCUX_SRCRSELn_CIM_COUNT 4
+
+/* #define SCUX_SRCRSELnCIM_COUNT (4) */
     volatile uint32_t  SRCRSEL0_CIM;                           /*  SRCRSEL0_CIM    */
     volatile uint32_t  SRCRSEL1_CIM;                           /*  SRCRSEL1_CIM    */
@@ -363,25 +761,28 @@
     volatile uint32_t  SRCRSEL3_CIM;                           /*  SRCRSEL3_CIM    */
     volatile uint32_t  MIXRSEL_CIM;                            /*  MIXRSEL_CIM     */
-};
-
-
-struct st_scux_from_ipcir_ipc0_n
+} r_io_scux_t;
+
+
+typedef struct st_scux_from_ipcir_ipc0_n
 {
+ 
     volatile uint32_t  IPCIR_IPC0_0;                           /*  IPCIR_IPC0_0    */
     volatile uint32_t  IPSLR_IPC0_0;                           /*  IPSLR_IPC0_0    */
     volatile uint8_t   dummy1[248];                            /*                  */
-};
-
-
-struct st_scux_from_opcir_opc0_n
+} r_io_scux_from_ipcir_ipc0_n_t;
+
+
+typedef struct st_scux_from_opcir_opc0_n
 {
+ 
     volatile uint32_t  OPCIR_OPC0_0;                           /*  OPCIR_OPC0_0    */
     volatile uint32_t  OPSLR_OPC0_0;                           /*  OPSLR_OPC0_0    */
     volatile uint8_t   dummy1[248];                            /*                  */
-};
-
-
-struct st_scux_from_ffdir_ffd0_n
+} r_io_scux_from_opcir_opc0_n_t;
+
+
+typedef struct st_scux_from_ffdir_ffd0_n
 {
+ 
     volatile uint32_t  FFDIR_FFD0_0;                           /*  FFDIR_FFD0_0    */
     volatile uint32_t  FDAIR_FFD0_0;                           /*  FDAIR_FFD0_0    */
@@ -392,9 +793,10 @@
     volatile uint8_t   dummy1[4];                              /*                  */
     volatile uint32_t  DEVCR_FFD0_0;                           /*  DEVCR_FFD0_0    */
-};
-
-
-struct st_scux_from_ffuir_ffu0_n
+} r_io_scux_from_ffdir_ffd0_n_t;
+
+
+typedef struct st_scux_from_ffuir_ffu0_n
 {
+ 
     volatile uint32_t  FFUIR_FFU0_0;                           /*  FFUIR_FFU0_0    */
     volatile uint32_t  FUAIR_FFU0_0;                           /*  FUAIR_FFU0_0    */
@@ -404,9 +806,10 @@
     volatile uint8_t   dummy1[4];                              /*                  */
     volatile uint32_t  UEVCR_FFU0_0;                           /*  UEVCR_FFU0_0    */
-};
-
-
-struct st_scux_from_srcir0_2src0_n
+} r_io_scux_from_ffuir_ffu0_n_t;
+
+
+typedef struct st_scux_from_srcir0_2src0_n
 {
+ 
     volatile uint32_t  SRCIR0_2SRC0_0;                         /*  SRCIR0_2SRC0_0  */
     volatile uint32_t  SADIR0_2SRC0_0;                         /*  SADIR0_2SRC0_0  */
@@ -436,9 +839,10 @@
     volatile uint32_t  SEVCR1_2SRC0_0;                         /*  SEVCR1_2SRC0_0  */
     volatile uint32_t  SRCIRR_2SRC0_0;                         /*  SRCIRR_2SRC0_0  */
-};
-
-
-struct st_scux_from_dvuir_dvu0_n
+} r_io_scux_from_srcir0_2src0_n_t;
+
+
+typedef struct st_scux_from_dvuir_dvu0_n
 {
+ 
     volatile uint32_t  DVUIR_DVU0_0;                           /*  DVUIR_DVU0_0    */
     volatile uint32_t  VADIR_DVU0_0;                           /*  VADIR_DVU0_0    */
@@ -463,346 +867,55 @@
     volatile uint8_t   dummy1[4];                              /*                  */
     volatile uint32_t  VEVCR_DVU0_0;                           /*  VEVCR_DVU0_0    */
-};
-
-
-#define SCUX    (*(struct st_scux    *)0xE8208000uL) /* SCUX */
-
-
-/* Start of channnel array defines of SCUX */
-
-/* Channnel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */
-/*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */
-#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT  4
-#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */
-#define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */
-#define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */
-#define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */
-
-
-/* Channnel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */
-/*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */
-#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT  2
-#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */
-#define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */
-
-
-/* Channnel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */
-/*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */
-#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT  4
-#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */
-#define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */
-#define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */
-#define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */
-
-
-/* Channnel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */
-/*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */
-#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT  4
-#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */
-#define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */
-#define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */
-#define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */
-
-
-/* Channnel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */
-/*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */
-#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT  4
-#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */
-#define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */
-#define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */
-#define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */
-
-
-/* Channnel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */
-/*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */
-#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT  4
-#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */
-#define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */
-#define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */
-#define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */
-
-/* End of channnel array defines of SCUX */
-
-
-#define SCUXIPCIR_IPC0_0 SCUX.IPCIR_IPC0_0
-#define SCUXIPSLR_IPC0_0 SCUX.IPSLR_IPC0_0
-#define SCUXIPCIR_IPC0_1 SCUX.IPCIR_IPC0_1
-#define SCUXIPSLR_IPC0_1 SCUX.IPSLR_IPC0_1
-#define SCUXIPCIR_IPC0_2 SCUX.IPCIR_IPC0_2
-#define SCUXIPSLR_IPC0_2 SCUX.IPSLR_IPC0_2
-#define SCUXIPCIR_IPC0_3 SCUX.IPCIR_IPC0_3
-#define SCUXIPSLR_IPC0_3 SCUX.IPSLR_IPC0_3
-#define SCUXOPCIR_OPC0_0 SCUX.OPCIR_OPC0_0
-#define SCUXOPSLR_OPC0_0 SCUX.OPSLR_OPC0_0
-#define SCUXOPCIR_OPC0_1 SCUX.OPCIR_OPC0_1
-#define SCUXOPSLR_OPC0_1 SCUX.OPSLR_OPC0_1
-#define SCUXOPCIR_OPC0_2 SCUX.OPCIR_OPC0_2
-#define SCUXOPSLR_OPC0_2 SCUX.OPSLR_OPC0_2
-#define SCUXOPCIR_OPC0_3 SCUX.OPCIR_OPC0_3
-#define SCUXOPSLR_OPC0_3 SCUX.OPSLR_OPC0_3
-#define SCUXFFDIR_FFD0_0 SCUX.FFDIR_FFD0_0
-#define SCUXFDAIR_FFD0_0 SCUX.FDAIR_FFD0_0
-#define SCUXDRQSR_FFD0_0 SCUX.DRQSR_FFD0_0
-#define SCUXFFDPR_FFD0_0 SCUX.FFDPR_FFD0_0
-#define SCUXFFDBR_FFD0_0 SCUX.FFDBR_FFD0_0
-#define SCUXDEVMR_FFD0_0 SCUX.DEVMR_FFD0_0
-#define SCUXDEVCR_FFD0_0 SCUX.DEVCR_FFD0_0
-#define SCUXFFDIR_FFD0_1 SCUX.FFDIR_FFD0_1
-#define SCUXFDAIR_FFD0_1 SCUX.FDAIR_FFD0_1
-#define SCUXDRQSR_FFD0_1 SCUX.DRQSR_FFD0_1
-#define SCUXFFDPR_FFD0_1 SCUX.FFDPR_FFD0_1
-#define SCUXFFDBR_FFD0_1 SCUX.FFDBR_FFD0_1
-#define SCUXDEVMR_FFD0_1 SCUX.DEVMR_FFD0_1
-#define SCUXDEVCR_FFD0_1 SCUX.DEVCR_FFD0_1
-#define SCUXFFDIR_FFD0_2 SCUX.FFDIR_FFD0_2
-#define SCUXFDAIR_FFD0_2 SCUX.FDAIR_FFD0_2
-#define SCUXDRQSR_FFD0_2 SCUX.DRQSR_FFD0_2
-#define SCUXFFDPR_FFD0_2 SCUX.FFDPR_FFD0_2
-#define SCUXFFDBR_FFD0_2 SCUX.FFDBR_FFD0_2
-#define SCUXDEVMR_FFD0_2 SCUX.DEVMR_FFD0_2
-#define SCUXDEVCR_FFD0_2 SCUX.DEVCR_FFD0_2
-#define SCUXFFDIR_FFD0_3 SCUX.FFDIR_FFD0_3
-#define SCUXFDAIR_FFD0_3 SCUX.FDAIR_FFD0_3
-#define SCUXDRQSR_FFD0_3 SCUX.DRQSR_FFD0_3
-#define SCUXFFDPR_FFD0_3 SCUX.FFDPR_FFD0_3
-#define SCUXFFDBR_FFD0_3 SCUX.FFDBR_FFD0_3
-#define SCUXDEVMR_FFD0_3 SCUX.DEVMR_FFD0_3
-#define SCUXDEVCR_FFD0_3 SCUX.DEVCR_FFD0_3
-#define SCUXFFUIR_FFU0_0 SCUX.FFUIR_FFU0_0
-#define SCUXFUAIR_FFU0_0 SCUX.FUAIR_FFU0_0
-#define SCUXURQSR_FFU0_0 SCUX.URQSR_FFU0_0
-#define SCUXFFUPR_FFU0_0 SCUX.FFUPR_FFU0_0
-#define SCUXUEVMR_FFU0_0 SCUX.UEVMR_FFU0_0
-#define SCUXUEVCR_FFU0_0 SCUX.UEVCR_FFU0_0
-#define SCUXFFUIR_FFU0_1 SCUX.FFUIR_FFU0_1
-#define SCUXFUAIR_FFU0_1 SCUX.FUAIR_FFU0_1
-#define SCUXURQSR_FFU0_1 SCUX.URQSR_FFU0_1
-#define SCUXFFUPR_FFU0_1 SCUX.FFUPR_FFU0_1
-#define SCUXUEVMR_FFU0_1 SCUX.UEVMR_FFU0_1
-#define SCUXUEVCR_FFU0_1 SCUX.UEVCR_FFU0_1
-#define SCUXFFUIR_FFU0_2 SCUX.FFUIR_FFU0_2
-#define SCUXFUAIR_FFU0_2 SCUX.FUAIR_FFU0_2
-#define SCUXURQSR_FFU0_2 SCUX.URQSR_FFU0_2
-#define SCUXFFUPR_FFU0_2 SCUX.FFUPR_FFU0_2
-#define SCUXUEVMR_FFU0_2 SCUX.UEVMR_FFU0_2
-#define SCUXUEVCR_FFU0_2 SCUX.UEVCR_FFU0_2
-#define SCUXFFUIR_FFU0_3 SCUX.FFUIR_FFU0_3
-#define SCUXFUAIR_FFU0_3 SCUX.FUAIR_FFU0_3
-#define SCUXURQSR_FFU0_3 SCUX.URQSR_FFU0_3
-#define SCUXFFUPR_FFU0_3 SCUX.FFUPR_FFU0_3
-#define SCUXUEVMR_FFU0_3 SCUX.UEVMR_FFU0_3
-#define SCUXUEVCR_FFU0_3 SCUX.UEVCR_FFU0_3
-#define SCUXSRCIR0_2SRC0_0 SCUX.SRCIR0_2SRC0_0
-#define SCUXSADIR0_2SRC0_0 SCUX.SADIR0_2SRC0_0
-#define SCUXSRCBR0_2SRC0_0 SCUX.SRCBR0_2SRC0_0
-#define SCUXIFSCR0_2SRC0_0 SCUX.IFSCR0_2SRC0_0
-#define SCUXIFSVR0_2SRC0_0 SCUX.IFSVR0_2SRC0_0
-#define SCUXSRCCR0_2SRC0_0 SCUX.SRCCR0_2SRC0_0
-#define SCUXMNFSR0_2SRC0_0 SCUX.MNFSR0_2SRC0_0
-#define SCUXBFSSR0_2SRC0_0 SCUX.BFSSR0_2SRC0_0
-#define SCUXSC2SR0_2SRC0_0 SCUX.SC2SR0_2SRC0_0
-#define SCUXWATSR0_2SRC0_0 SCUX.WATSR0_2SRC0_0
-#define SCUXSEVMR0_2SRC0_0 SCUX.SEVMR0_2SRC0_0
-#define SCUXSEVCR0_2SRC0_0 SCUX.SEVCR0_2SRC0_0
-#define SCUXSRCIR1_2SRC0_0 SCUX.SRCIR1_2SRC0_0
-#define SCUXSADIR1_2SRC0_0 SCUX.SADIR1_2SRC0_0
-#define SCUXSRCBR1_2SRC0_0 SCUX.SRCBR1_2SRC0_0
-#define SCUXIFSCR1_2SRC0_0 SCUX.IFSCR1_2SRC0_0
-#define SCUXIFSVR1_2SRC0_0 SCUX.IFSVR1_2SRC0_0
-#define SCUXSRCCR1_2SRC0_0 SCUX.SRCCR1_2SRC0_0
-#define SCUXMNFSR1_2SRC0_0 SCUX.MNFSR1_2SRC0_0
-#define SCUXBFSSR1_2SRC0_0 SCUX.BFSSR1_2SRC0_0
-#define SCUXSC2SR1_2SRC0_0 SCUX.SC2SR1_2SRC0_0
-#define SCUXWATSR1_2SRC0_0 SCUX.WATSR1_2SRC0_0
-#define SCUXSEVMR1_2SRC0_0 SCUX.SEVMR1_2SRC0_0
-#define SCUXSEVCR1_2SRC0_0 SCUX.SEVCR1_2SRC0_0
-#define SCUXSRCIRR_2SRC0_0 SCUX.SRCIRR_2SRC0_0
-#define SCUXSRCIR0_2SRC0_1 SCUX.SRCIR0_2SRC0_1
-#define SCUXSADIR0_2SRC0_1 SCUX.SADIR0_2SRC0_1
-#define SCUXSRCBR0_2SRC0_1 SCUX.SRCBR0_2SRC0_1
-#define SCUXIFSCR0_2SRC0_1 SCUX.IFSCR0_2SRC0_1
-#define SCUXIFSVR0_2SRC0_1 SCUX.IFSVR0_2SRC0_1
-#define SCUXSRCCR0_2SRC0_1 SCUX.SRCCR0_2SRC0_1
-#define SCUXMNFSR0_2SRC0_1 SCUX.MNFSR0_2SRC0_1
-#define SCUXBFSSR0_2SRC0_1 SCUX.BFSSR0_2SRC0_1
-#define SCUXSC2SR0_2SRC0_1 SCUX.SC2SR0_2SRC0_1
-#define SCUXWATSR0_2SRC0_1 SCUX.WATSR0_2SRC0_1
-#define SCUXSEVMR0_2SRC0_1 SCUX.SEVMR0_2SRC0_1
-#define SCUXSEVCR0_2SRC0_1 SCUX.SEVCR0_2SRC0_1
-#define SCUXSRCIR1_2SRC0_1 SCUX.SRCIR1_2SRC0_1
-#define SCUXSADIR1_2SRC0_1 SCUX.SADIR1_2SRC0_1
-#define SCUXSRCBR1_2SRC0_1 SCUX.SRCBR1_2SRC0_1
-#define SCUXIFSCR1_2SRC0_1 SCUX.IFSCR1_2SRC0_1
-#define SCUXIFSVR1_2SRC0_1 SCUX.IFSVR1_2SRC0_1
-#define SCUXSRCCR1_2SRC0_1 SCUX.SRCCR1_2SRC0_1
-#define SCUXMNFSR1_2SRC0_1 SCUX.MNFSR1_2SRC0_1
-#define SCUXBFSSR1_2SRC0_1 SCUX.BFSSR1_2SRC0_1
-#define SCUXSC2SR1_2SRC0_1 SCUX.SC2SR1_2SRC0_1
-#define SCUXWATSR1_2SRC0_1 SCUX.WATSR1_2SRC0_1
-#define SCUXSEVMR1_2SRC0_1 SCUX.SEVMR1_2SRC0_1
-#define SCUXSEVCR1_2SRC0_1 SCUX.SEVCR1_2SRC0_1
-#define SCUXSRCIRR_2SRC0_1 SCUX.SRCIRR_2SRC0_1
-#define SCUXDVUIR_DVU0_0 SCUX.DVUIR_DVU0_0
-#define SCUXVADIR_DVU0_0 SCUX.VADIR_DVU0_0
-#define SCUXDVUBR_DVU0_0 SCUX.DVUBR_DVU0_0
-#define SCUXDVUCR_DVU0_0 SCUX.DVUCR_DVU0_0
-#define SCUXZCMCR_DVU0_0 SCUX.ZCMCR_DVU0_0
-#define SCUXVRCTR_DVU0_0 SCUX.VRCTR_DVU0_0
-#define SCUXVRPDR_DVU0_0 SCUX.VRPDR_DVU0_0
-#define SCUXVRDBR_DVU0_0 SCUX.VRDBR_DVU0_0
-#define SCUXVRWTR_DVU0_0 SCUX.VRWTR_DVU0_0
-#define SCUXVOL0R_DVU0_0 SCUX.VOL0R_DVU0_0
-#define SCUXVOL1R_DVU0_0 SCUX.VOL1R_DVU0_0
-#define SCUXVOL2R_DVU0_0 SCUX.VOL2R_DVU0_0
-#define SCUXVOL3R_DVU0_0 SCUX.VOL3R_DVU0_0
-#define SCUXVOL4R_DVU0_0 SCUX.VOL4R_DVU0_0
-#define SCUXVOL5R_DVU0_0 SCUX.VOL5R_DVU0_0
-#define SCUXVOL6R_DVU0_0 SCUX.VOL6R_DVU0_0
-#define SCUXVOL7R_DVU0_0 SCUX.VOL7R_DVU0_0
-#define SCUXDVUER_DVU0_0 SCUX.DVUER_DVU0_0
-#define SCUXDVUSR_DVU0_0 SCUX.DVUSR_DVU0_0
-#define SCUXVEVMR_DVU0_0 SCUX.VEVMR_DVU0_0
-#define SCUXVEVCR_DVU0_0 SCUX.VEVCR_DVU0_0
-#define SCUXDVUIR_DVU0_1 SCUX.DVUIR_DVU0_1
-#define SCUXVADIR_DVU0_1 SCUX.VADIR_DVU0_1
-#define SCUXDVUBR_DVU0_1 SCUX.DVUBR_DVU0_1
-#define SCUXDVUCR_DVU0_1 SCUX.DVUCR_DVU0_1
-#define SCUXZCMCR_DVU0_1 SCUX.ZCMCR_DVU0_1
-#define SCUXVRCTR_DVU0_1 SCUX.VRCTR_DVU0_1
-#define SCUXVRPDR_DVU0_1 SCUX.VRPDR_DVU0_1
-#define SCUXVRDBR_DVU0_1 SCUX.VRDBR_DVU0_1
-#define SCUXVRWTR_DVU0_1 SCUX.VRWTR_DVU0_1
-#define SCUXVOL0R_DVU0_1 SCUX.VOL0R_DVU0_1
-#define SCUXVOL1R_DVU0_1 SCUX.VOL1R_DVU0_1
-#define SCUXVOL2R_DVU0_1 SCUX.VOL2R_DVU0_1
-#define SCUXVOL3R_DVU0_1 SCUX.VOL3R_DVU0_1
-#define SCUXVOL4R_DVU0_1 SCUX.VOL4R_DVU0_1
-#define SCUXVOL5R_DVU0_1 SCUX.VOL5R_DVU0_1
-#define SCUXVOL6R_DVU0_1 SCUX.VOL6R_DVU0_1
-#define SCUXVOL7R_DVU0_1 SCUX.VOL7R_DVU0_1
-#define SCUXDVUER_DVU0_1 SCUX.DVUER_DVU0_1
-#define SCUXDVUSR_DVU0_1 SCUX.DVUSR_DVU0_1
-#define SCUXVEVMR_DVU0_1 SCUX.VEVMR_DVU0_1
-#define SCUXVEVCR_DVU0_1 SCUX.VEVCR_DVU0_1
-#define SCUXDVUIR_DVU0_2 SCUX.DVUIR_DVU0_2
-#define SCUXVADIR_DVU0_2 SCUX.VADIR_DVU0_2
-#define SCUXDVUBR_DVU0_2 SCUX.DVUBR_DVU0_2
-#define SCUXDVUCR_DVU0_2 SCUX.DVUCR_DVU0_2
-#define SCUXZCMCR_DVU0_2 SCUX.ZCMCR_DVU0_2
-#define SCUXVRCTR_DVU0_2 SCUX.VRCTR_DVU0_2
-#define SCUXVRPDR_DVU0_2 SCUX.VRPDR_DVU0_2
-#define SCUXVRDBR_DVU0_2 SCUX.VRDBR_DVU0_2
-#define SCUXVRWTR_DVU0_2 SCUX.VRWTR_DVU0_2
-#define SCUXVOL0R_DVU0_2 SCUX.VOL0R_DVU0_2
-#define SCUXVOL1R_DVU0_2 SCUX.VOL1R_DVU0_2
-#define SCUXVOL2R_DVU0_2 SCUX.VOL2R_DVU0_2
-#define SCUXVOL3R_DVU0_2 SCUX.VOL3R_DVU0_2
-#define SCUXVOL4R_DVU0_2 SCUX.VOL4R_DVU0_2
-#define SCUXVOL5R_DVU0_2 SCUX.VOL5R_DVU0_2
-#define SCUXVOL6R_DVU0_2 SCUX.VOL6R_DVU0_2
-#define SCUXVOL7R_DVU0_2 SCUX.VOL7R_DVU0_2
-#define SCUXDVUER_DVU0_2 SCUX.DVUER_DVU0_2
-#define SCUXDVUSR_DVU0_2 SCUX.DVUSR_DVU0_2
-#define SCUXVEVMR_DVU0_2 SCUX.VEVMR_DVU0_2
-#define SCUXVEVCR_DVU0_2 SCUX.VEVCR_DVU0_2
-#define SCUXDVUIR_DVU0_3 SCUX.DVUIR_DVU0_3
-#define SCUXVADIR_DVU0_3 SCUX.VADIR_DVU0_3
-#define SCUXDVUBR_DVU0_3 SCUX.DVUBR_DVU0_3
-#define SCUXDVUCR_DVU0_3 SCUX.DVUCR_DVU0_3
-#define SCUXZCMCR_DVU0_3 SCUX.ZCMCR_DVU0_3
-#define SCUXVRCTR_DVU0_3 SCUX.VRCTR_DVU0_3
-#define SCUXVRPDR_DVU0_3 SCUX.VRPDR_DVU0_3
-#define SCUXVRDBR_DVU0_3 SCUX.VRDBR_DVU0_3
-#define SCUXVRWTR_DVU0_3 SCUX.VRWTR_DVU0_3
-#define SCUXVOL0R_DVU0_3 SCUX.VOL0R_DVU0_3
-#define SCUXVOL1R_DVU0_3 SCUX.VOL1R_DVU0_3
-#define SCUXVOL2R_DVU0_3 SCUX.VOL2R_DVU0_3
-#define SCUXVOL3R_DVU0_3 SCUX.VOL3R_DVU0_3
-#define SCUXVOL4R_DVU0_3 SCUX.VOL4R_DVU0_3
-#define SCUXVOL5R_DVU0_3 SCUX.VOL5R_DVU0_3
-#define SCUXVOL6R_DVU0_3 SCUX.VOL6R_DVU0_3
-#define SCUXVOL7R_DVU0_3 SCUX.VOL7R_DVU0_3
-#define SCUXDVUER_DVU0_3 SCUX.DVUER_DVU0_3
-#define SCUXDVUSR_DVU0_3 SCUX.DVUSR_DVU0_3
-#define SCUXVEVMR_DVU0_3 SCUX.VEVMR_DVU0_3
-#define SCUXVEVCR_DVU0_3 SCUX.VEVCR_DVU0_3
-#define SCUXMIXIR_MIX0_0 SCUX.MIXIR_MIX0_0
-#define SCUXMADIR_MIX0_0 SCUX.MADIR_MIX0_0
-#define SCUXMIXBR_MIX0_0 SCUX.MIXBR_MIX0_0
-#define SCUXMIXMR_MIX0_0 SCUX.MIXMR_MIX0_0
-#define SCUXMVPDR_MIX0_0 SCUX.MVPDR_MIX0_0
-#define SCUXMDBAR_MIX0_0 SCUX.MDBAR_MIX0_0
-#define SCUXMDBBR_MIX0_0 SCUX.MDBBR_MIX0_0
-#define SCUXMDBCR_MIX0_0 SCUX.MDBCR_MIX0_0
-#define SCUXMDBDR_MIX0_0 SCUX.MDBDR_MIX0_0
-#define SCUXMDBER_MIX0_0 SCUX.MDBER_MIX0_0
-#define SCUXMIXSR_MIX0_0 SCUX.MIXSR_MIX0_0
-#define SCUXSWRSR_CIM SCUX.SWRSR_CIM
-#define SCUXDMACR_CIM SCUX.DMACR_CIM
-#define SCUXDMATD0_CIM SCUX.DMATD0_CIM.UINT32
-#define SCUXDMATD0_CIML SCUX.DMATD0_CIM.UINT16[L]
-#define SCUXDMATD0_CIMH SCUX.DMATD0_CIM.UINT16[H]
-#define SCUXDMATD1_CIM SCUX.DMATD1_CIM.UINT32
-#define SCUXDMATD1_CIML SCUX.DMATD1_CIM.UINT16[L]
-#define SCUXDMATD1_CIMH SCUX.DMATD1_CIM.UINT16[H]
-#define SCUXDMATD2_CIM SCUX.DMATD2_CIM.UINT32
-#define SCUXDMATD2_CIML SCUX.DMATD2_CIM.UINT16[L]
-#define SCUXDMATD2_CIMH SCUX.DMATD2_CIM.UINT16[H]
-#define SCUXDMATD3_CIM SCUX.DMATD3_CIM.UINT32
-#define SCUXDMATD3_CIML SCUX.DMATD3_CIM.UINT16[L]
-#define SCUXDMATD3_CIMH SCUX.DMATD3_CIM.UINT16[H]
-#define SCUXDMATU0_CIM SCUX.DMATU0_CIM.UINT32
-#define SCUXDMATU0_CIML SCUX.DMATU0_CIM.UINT16[L]
-#define SCUXDMATU0_CIMH SCUX.DMATU0_CIM.UINT16[H]
-#define SCUXDMATU1_CIM SCUX.DMATU1_CIM.UINT32
-#define SCUXDMATU1_CIML SCUX.DMATU1_CIM.UINT16[L]
-#define SCUXDMATU1_CIMH SCUX.DMATU1_CIM.UINT16[H]
-#define SCUXDMATU2_CIM SCUX.DMATU2_CIM.UINT32
-#define SCUXDMATU2_CIML SCUX.DMATU2_CIM.UINT16[L]
-#define SCUXDMATU2_CIMH SCUX.DMATU2_CIM.UINT16[H]
-#define SCUXDMATU3_CIM SCUX.DMATU3_CIM.UINT32
-#define SCUXDMATU3_CIML SCUX.DMATU3_CIM.UINT16[L]
-#define SCUXDMATU3_CIMH SCUX.DMATU3_CIM.UINT16[H]
-#define SCUXSSIRSEL_CIM SCUX.SSIRSEL_CIM
-#define SCUXFDTSEL0_CIM SCUX.FDTSEL0_CIM
-#define SCUXFDTSEL1_CIM SCUX.FDTSEL1_CIM
-#define SCUXFDTSEL2_CIM SCUX.FDTSEL2_CIM
-#define SCUXFDTSEL3_CIM SCUX.FDTSEL3_CIM
-#define SCUXFUTSEL0_CIM SCUX.FUTSEL0_CIM
-#define SCUXFUTSEL1_CIM SCUX.FUTSEL1_CIM
-#define SCUXFUTSEL2_CIM SCUX.FUTSEL2_CIM
-#define SCUXFUTSEL3_CIM SCUX.FUTSEL3_CIM
-#define SCUXSSIPMD_CIM SCUX.SSIPMD_CIM
-#define SCUXSSICTRL_CIM SCUX.SSICTRL_CIM
-#define SCUXSRCRSEL0_CIM SCUX.SRCRSEL0_CIM
-#define SCUXSRCRSEL1_CIM SCUX.SRCRSEL1_CIM
-#define SCUXSRCRSEL2_CIM SCUX.SRCRSEL2_CIM
-#define SCUXSRCRSEL3_CIM SCUX.SRCRSEL3_CIM
-#define SCUXMIXRSEL_CIM SCUX.MIXRSEL_CIM
+} r_io_scux_from_dvuir_dvu0_n_t;
+
+
+/* Channel array defines of SCUX (2)*/
+#ifdef  DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS
+volatile struct st_scux_from_dvuir_dvu0_n*  SCUX_FROM_DVUIR_DVU0_0_ARRAY[ SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS
+volatile struct st_scux_from_srcir0_2src0_n*  SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS
+volatile struct st_scux_from_ffuir_ffu0_n*  SCUX_FROM_FFUIR_FFU0_0_ARRAY[ SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS
+volatile struct st_scux_from_ffdir_ffd0_n*  SCUX_FROM_FFDIR_FFD0_0_ARRAY[ SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS
+volatile struct st_scux_from_opcir_opc0_n*  SCUX_FROM_OPCIR_OPC0_0_ARRAY[ SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS
+volatile struct st_scux_from_ipcir_ipc0_n*  SCUX_FROM_IPCIR_IPC0_0_ARRAY[ SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS */
+/* End of channel array defines of SCUX (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
 /* <-QAC 0639 */
 #endif
