Changeset 374 for asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/rspi_iodefine.h
- Timestamp:
- Apr 5, 2019, 9:26:53 PM (5 years ago)
- Location:
- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX
- Files:
-
- 1 added
- 1 edited
- 1 moved
Legend:
- Unmodified
- Added
- Removed
-
asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/rspi_iodefine.h
r352 r374 19 19 * following link: 20 20 * http://www.renesas.com/disclaimer* 21 * Copyright (C) 2013-201 4Renesas Electronics Corporation. All rights reserved.21 * Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. 22 22 *******************************************************************************/ 23 23 /******************************************************************************* … … 25 25 * $Rev: $ 26 26 * $Date:: $ 27 * Description : Definition of I/O Register (V1.00a)27 * Description : Definition of I/O Register for RZ/A1H,M (V2.00h) 28 28 ******************************************************************************/ 29 29 #ifndef RSPI_IODEFINE_H 30 30 #define RSPI_IODEFINE_H 31 /* ->QAC 0639 : Over 127 members (C90) */ 32 /* ->QAC 0857 : Over 1024 #define (C90) */ 33 /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ 31 34 /* ->SEC M1.10.1 : Not magic number */ 32 35 33 #include "reg32_t.h" 34 35 struct st_rspi 36 { /* RSPI */ 36 #define RSPI0 (*(struct st_rspi *)0xE800C800uL) /* RSPI0 */ 37 #define RSPI1 (*(struct st_rspi *)0xE800D000uL) /* RSPI1 */ 38 #define RSPI2 (*(struct st_rspi *)0xE800D800uL) /* RSPI2 */ 39 #define RSPI3 (*(struct st_rspi *)0xE800E000uL) /* RSPI3 */ 40 #define RSPI4 (*(struct st_rspi *)0xE800E800uL) /* RSPI4 */ 41 42 43 /* Start of channel array defines of RSPI */ 44 45 /* Channel array defines of RSPI */ 46 /*(Sample) value = RSPI[ channel ]->SPCR; */ 47 #define RSPI_COUNT (5) 48 #define RSPI_ADDRESS_LIST \ 49 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ 50 &RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \ 51 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ 52 53 /* End of channel array defines of RSPI */ 54 55 56 #define SPCR_0 (RSPI0.SPCR) 57 #define SSLP_0 (RSPI0.SSLP) 58 #define SPPCR_0 (RSPI0.SPPCR) 59 #define SPSR_0 (RSPI0.SPSR) 60 #define SPDR_0 (RSPI0.SPDR.UINT32) 61 #define SPDR_0L (RSPI0.SPDR.UINT16[R_IO_L]) 62 #define SPDR_0H (RSPI0.SPDR.UINT16[R_IO_H]) 63 #define SPDR_0LL (RSPI0.SPDR.UINT8[R_IO_LL]) 64 #define SPDR_0LH (RSPI0.SPDR.UINT8[R_IO_LH]) 65 #define SPDR_0HL (RSPI0.SPDR.UINT8[R_IO_HL]) 66 #define SPDR_0HH (RSPI0.SPDR.UINT8[R_IO_HH]) 67 #define SPSCR_0 (RSPI0.SPSCR) 68 #define SPSSR_0 (RSPI0.SPSSR) 69 #define SPBR_0 (RSPI0.SPBR) 70 #define SPDCR_0 (RSPI0.SPDCR) 71 #define SPCKD_0 (RSPI0.SPCKD) 72 #define SSLND_0 (RSPI0.SSLND) 73 #define SPND_0 (RSPI0.SPND) 74 #define SPCMD0_0 (RSPI0.SPCMD0) 75 #define SPCMD1_0 (RSPI0.SPCMD1) 76 #define SPCMD2_0 (RSPI0.SPCMD2) 77 #define SPCMD3_0 (RSPI0.SPCMD3) 78 #define SPBFCR_0 (RSPI0.SPBFCR) 79 #define SPBFDR_0 (RSPI0.SPBFDR) 80 #define SPCR_1 (RSPI1.SPCR) 81 #define SSLP_1 (RSPI1.SSLP) 82 #define SPPCR_1 (RSPI1.SPPCR) 83 #define SPSR_1 (RSPI1.SPSR) 84 #define SPDR_1 (RSPI1.SPDR.UINT32) 85 #define SPDR_1L (RSPI1.SPDR.UINT16[R_IO_L]) 86 #define SPDR_1H (RSPI1.SPDR.UINT16[R_IO_H]) 87 #define SPDR_1LL (RSPI1.SPDR.UINT8[R_IO_LL]) 88 #define SPDR_1LH (RSPI1.SPDR.UINT8[R_IO_LH]) 89 #define SPDR_1HL (RSPI1.SPDR.UINT8[R_IO_HL]) 90 #define SPDR_1HH (RSPI1.SPDR.UINT8[R_IO_HH]) 91 #define SPSCR_1 (RSPI1.SPSCR) 92 #define SPSSR_1 (RSPI1.SPSSR) 93 #define SPBR_1 (RSPI1.SPBR) 94 #define SPDCR_1 (RSPI1.SPDCR) 95 #define SPCKD_1 (RSPI1.SPCKD) 96 #define SSLND_1 (RSPI1.SSLND) 97 #define SPND_1 (RSPI1.SPND) 98 #define SPCMD0_1 (RSPI1.SPCMD0) 99 #define SPCMD1_1 (RSPI1.SPCMD1) 100 #define SPCMD2_1 (RSPI1.SPCMD2) 101 #define SPCMD3_1 (RSPI1.SPCMD3) 102 #define SPBFCR_1 (RSPI1.SPBFCR) 103 #define SPBFDR_1 (RSPI1.SPBFDR) 104 #define SPCR_2 (RSPI2.SPCR) 105 #define SSLP_2 (RSPI2.SSLP) 106 #define SPPCR_2 (RSPI2.SPPCR) 107 #define SPSR_2 (RSPI2.SPSR) 108 #define SPDR_2 (RSPI2.SPDR.UINT32) 109 #define SPDR_2L (RSPI2.SPDR.UINT16[R_IO_L]) 110 #define SPDR_2H (RSPI2.SPDR.UINT16[R_IO_H]) 111 #define SPDR_2LL (RSPI2.SPDR.UINT8[R_IO_LL]) 112 #define SPDR_2LH (RSPI2.SPDR.UINT8[R_IO_LH]) 113 #define SPDR_2HL (RSPI2.SPDR.UINT8[R_IO_HL]) 114 #define SPDR_2HH (RSPI2.SPDR.UINT8[R_IO_HH]) 115 #define SPSCR_2 (RSPI2.SPSCR) 116 #define SPSSR_2 (RSPI2.SPSSR) 117 #define SPBR_2 (RSPI2.SPBR) 118 #define SPDCR_2 (RSPI2.SPDCR) 119 #define SPCKD_2 (RSPI2.SPCKD) 120 #define SSLND_2 (RSPI2.SSLND) 121 #define SPND_2 (RSPI2.SPND) 122 #define SPCMD0_2 (RSPI2.SPCMD0) 123 #define SPCMD1_2 (RSPI2.SPCMD1) 124 #define SPCMD2_2 (RSPI2.SPCMD2) 125 #define SPCMD3_2 (RSPI2.SPCMD3) 126 #define SPBFCR_2 (RSPI2.SPBFCR) 127 #define SPBFDR_2 (RSPI2.SPBFDR) 128 #define SPCR_3 (RSPI3.SPCR) 129 #define SSLP_3 (RSPI3.SSLP) 130 #define SPPCR_3 (RSPI3.SPPCR) 131 #define SPSR_3 (RSPI3.SPSR) 132 #define SPDR_3 (RSPI3.SPDR.UINT32) 133 #define SPDR_3L (RSPI3.SPDR.UINT16[R_IO_L]) 134 #define SPDR_3H (RSPI3.SPDR.UINT16[R_IO_H]) 135 #define SPDR_3LL (RSPI3.SPDR.UINT8[R_IO_LL]) 136 #define SPDR_3LH (RSPI3.SPDR.UINT8[R_IO_LH]) 137 #define SPDR_3HL (RSPI3.SPDR.UINT8[R_IO_HL]) 138 #define SPDR_3HH (RSPI3.SPDR.UINT8[R_IO_HH]) 139 #define SPSCR_3 (RSPI3.SPSCR) 140 #define SPSSR_3 (RSPI3.SPSSR) 141 #define SPBR_3 (RSPI3.SPBR) 142 #define SPDCR_3 (RSPI3.SPDCR) 143 #define SPCKD_3 (RSPI3.SPCKD) 144 #define SSLND_3 (RSPI3.SSLND) 145 #define SPND_3 (RSPI3.SPND) 146 #define SPCMD0_3 (RSPI3.SPCMD0) 147 #define SPCMD1_3 (RSPI3.SPCMD1) 148 #define SPCMD2_3 (RSPI3.SPCMD2) 149 #define SPCMD3_3 (RSPI3.SPCMD3) 150 #define SPBFCR_3 (RSPI3.SPBFCR) 151 #define SPBFDR_3 (RSPI3.SPBFDR) 152 #define SPCR_4 (RSPI4.SPCR) 153 #define SSLP_4 (RSPI4.SSLP) 154 #define SPPCR_4 (RSPI4.SPPCR) 155 #define SPSR_4 (RSPI4.SPSR) 156 #define SPDR_4 (RSPI4.SPDR.UINT32) 157 #define SPDR_4L (RSPI4.SPDR.UINT16[R_IO_L]) 158 #define SPDR_4H (RSPI4.SPDR.UINT16[R_IO_H]) 159 #define SPDR_4LL (RSPI4.SPDR.UINT8[R_IO_LL]) 160 #define SPDR_4LH (RSPI4.SPDR.UINT8[R_IO_LH]) 161 #define SPDR_4HL (RSPI4.SPDR.UINT8[R_IO_HL]) 162 #define SPDR_4HH (RSPI4.SPDR.UINT8[R_IO_HH]) 163 #define SPSCR_4 (RSPI4.SPSCR) 164 #define SPSSR_4 (RSPI4.SPSSR) 165 #define SPBR_4 (RSPI4.SPBR) 166 #define SPDCR_4 (RSPI4.SPDCR) 167 #define SPCKD_4 (RSPI4.SPCKD) 168 #define SSLND_4 (RSPI4.SSLND) 169 #define SPND_4 (RSPI4.SPND) 170 #define SPCMD0_4 (RSPI4.SPCMD0) 171 #define SPCMD1_4 (RSPI4.SPCMD1) 172 #define SPCMD2_4 (RSPI4.SPCMD2) 173 #define SPCMD3_4 (RSPI4.SPCMD3) 174 #define SPBFCR_4 (RSPI4.SPBFCR) 175 #define SPBFDR_4 (RSPI4.SPBFDR) 176 177 #define SPCMD_COUNT (4) 178 179 180 typedef struct st_rspi 181 { 182 /* RSPI */ 37 183 volatile uint8_t SPCR; /* SPCR */ 38 184 volatile uint8_t SSLP; /* SSLP */ 39 185 volatile uint8_t SPPCR; /* SPPCR */ 40 186 volatile uint8_t SPSR; /* SPSR */ 41 union reg32_t SPDR; /* SPDR */187 union iodefine_reg32_t SPDR; /* SPDR */ 42 188 43 189 volatile uint8_t SPSCR; /* SPSCR */ … … 49 195 volatile uint8_t SPND; /* SPND */ 50 196 volatile uint8_t dummy1[1]; /* */ 51 #define SPCMD_COUNT 4 197 198 /* #define SPCMD_COUNT (4) */ 52 199 volatile uint16_t SPCMD0; /* SPCMD0 */ 53 200 volatile uint16_t SPCMD1; /* SPCMD1 */ … … 58 205 volatile uint8_t dummy3[1]; /* */ 59 206 volatile uint16_t SPBFDR; /* SPBFDR */ 60 }; 61 62 63 #define RSPI0 (*(struct st_rspi *)0xE800C800uL) /* RSPI0 */ 64 #define RSPI1 (*(struct st_rspi *)0xE800D000uL) /* RSPI1 */ 65 #define RSPI2 (*(struct st_rspi *)0xE800D800uL) /* RSPI2 */ 66 #define RSPI3 (*(struct st_rspi *)0xE800E000uL) /* RSPI3 */ 67 #define RSPI4 (*(struct st_rspi *)0xE800E800uL) /* RSPI4 */ 68 69 70 /* Start of channnel array defines of RSPI */ 71 72 /* Channnel array defines of RSPI */ 73 /*(Sample) value = RSPI[ channel ]->SPCR; */ 74 #define RSPI_COUNT 5 75 #define RSPI_ADDRESS_LIST \ 76 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ 77 &RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \ 78 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ 79 80 /* End of channnel array defines of RSPI */ 81 82 83 #define SPCR_0 RSPI0.SPCR 84 #define SSLP_0 RSPI0.SSLP 85 #define SPPCR_0 RSPI0.SPPCR 86 #define SPSR_0 RSPI0.SPSR 87 #define SPDR_0 RSPI0.SPDR.UINT32 88 #define SPDR_0L RSPI0.SPDR.UINT16[L] 89 #define SPDR_0H RSPI0.SPDR.UINT16[H] 90 #define SPDR_0LL RSPI0.SPDR.UINT8[LL] 91 #define SPDR_0LH RSPI0.SPDR.UINT8[LH] 92 #define SPDR_0HL RSPI0.SPDR.UINT8[HL] 93 #define SPDR_0HH RSPI0.SPDR.UINT8[HH] 94 #define SPSCR_0 RSPI0.SPSCR 95 #define SPSSR_0 RSPI0.SPSSR 96 #define SPBR_0 RSPI0.SPBR 97 #define SPDCR_0 RSPI0.SPDCR 98 #define SPCKD_0 RSPI0.SPCKD 99 #define SSLND_0 RSPI0.SSLND 100 #define SPND_0 RSPI0.SPND 101 #define SPCMD0_0 RSPI0.SPCMD0 102 #define SPCMD1_0 RSPI0.SPCMD1 103 #define SPCMD2_0 RSPI0.SPCMD2 104 #define SPCMD3_0 RSPI0.SPCMD3 105 #define SPBFCR_0 RSPI0.SPBFCR 106 #define SPBFDR_0 RSPI0.SPBFDR 107 #define SPCR_1 RSPI1.SPCR 108 #define SSLP_1 RSPI1.SSLP 109 #define SPPCR_1 RSPI1.SPPCR 110 #define SPSR_1 RSPI1.SPSR 111 #define SPDR_1 RSPI1.SPDR.UINT32 112 #define SPDR_1L RSPI1.SPDR.UINT16[L] 113 #define SPDR_1H RSPI1.SPDR.UINT16[H] 114 #define SPDR_1LL RSPI1.SPDR.UINT8[LL] 115 #define SPDR_1LH RSPI1.SPDR.UINT8[LH] 116 #define SPDR_1HL RSPI1.SPDR.UINT8[HL] 117 #define SPDR_1HH RSPI1.SPDR.UINT8[HH] 118 #define SPSCR_1 RSPI1.SPSCR 119 #define SPSSR_1 RSPI1.SPSSR 120 #define SPBR_1 RSPI1.SPBR 121 #define SPDCR_1 RSPI1.SPDCR 122 #define SPCKD_1 RSPI1.SPCKD 123 #define SSLND_1 RSPI1.SSLND 124 #define SPND_1 RSPI1.SPND 125 #define SPCMD0_1 RSPI1.SPCMD0 126 #define SPCMD1_1 RSPI1.SPCMD1 127 #define SPCMD2_1 RSPI1.SPCMD2 128 #define SPCMD3_1 RSPI1.SPCMD3 129 #define SPBFCR_1 RSPI1.SPBFCR 130 #define SPBFDR_1 RSPI1.SPBFDR 131 #define SPCR_2 RSPI2.SPCR 132 #define SSLP_2 RSPI2.SSLP 133 #define SPPCR_2 RSPI2.SPPCR 134 #define SPSR_2 RSPI2.SPSR 135 #define SPDR_2 RSPI2.SPDR.UINT32 136 #define SPDR_2L RSPI2.SPDR.UINT16[L] 137 #define SPDR_2H RSPI2.SPDR.UINT16[H] 138 #define SPDR_2LL RSPI2.SPDR.UINT8[LL] 139 #define SPDR_2LH RSPI2.SPDR.UINT8[LH] 140 #define SPDR_2HL RSPI2.SPDR.UINT8[HL] 141 #define SPDR_2HH RSPI2.SPDR.UINT8[HH] 142 #define SPSCR_2 RSPI2.SPSCR 143 #define SPSSR_2 RSPI2.SPSSR 144 #define SPBR_2 RSPI2.SPBR 145 #define SPDCR_2 RSPI2.SPDCR 146 #define SPCKD_2 RSPI2.SPCKD 147 #define SSLND_2 RSPI2.SSLND 148 #define SPND_2 RSPI2.SPND 149 #define SPCMD0_2 RSPI2.SPCMD0 150 #define SPCMD1_2 RSPI2.SPCMD1 151 #define SPCMD2_2 RSPI2.SPCMD2 152 #define SPCMD3_2 RSPI2.SPCMD3 153 #define SPBFCR_2 RSPI2.SPBFCR 154 #define SPBFDR_2 RSPI2.SPBFDR 155 #define SPCR_3 RSPI3.SPCR 156 #define SSLP_3 RSPI3.SSLP 157 #define SPPCR_3 RSPI3.SPPCR 158 #define SPSR_3 RSPI3.SPSR 159 #define SPDR_3 RSPI3.SPDR.UINT32 160 #define SPDR_3L RSPI3.SPDR.UINT16[L] 161 #define SPDR_3H RSPI3.SPDR.UINT16[H] 162 #define SPDR_3LL RSPI3.SPDR.UINT8[LL] 163 #define SPDR_3LH RSPI3.SPDR.UINT8[LH] 164 #define SPDR_3HL RSPI3.SPDR.UINT8[HL] 165 #define SPDR_3HH RSPI3.SPDR.UINT8[HH] 166 #define SPSCR_3 RSPI3.SPSCR 167 #define SPSSR_3 RSPI3.SPSSR 168 #define SPBR_3 RSPI3.SPBR 169 #define SPDCR_3 RSPI3.SPDCR 170 #define SPCKD_3 RSPI3.SPCKD 171 #define SSLND_3 RSPI3.SSLND 172 #define SPND_3 RSPI3.SPND 173 #define SPCMD0_3 RSPI3.SPCMD0 174 #define SPCMD1_3 RSPI3.SPCMD1 175 #define SPCMD2_3 RSPI3.SPCMD2 176 #define SPCMD3_3 RSPI3.SPCMD3 177 #define SPBFCR_3 RSPI3.SPBFCR 178 #define SPBFDR_3 RSPI3.SPBFDR 179 #define SPCR_4 RSPI4.SPCR 180 #define SSLP_4 RSPI4.SSLP 181 #define SPPCR_4 RSPI4.SPPCR 182 #define SPSR_4 RSPI4.SPSR 183 #define SPDR_4 RSPI4.SPDR.UINT32 184 #define SPDR_4L RSPI4.SPDR.UINT16[L] 185 #define SPDR_4H RSPI4.SPDR.UINT16[H] 186 #define SPDR_4LL RSPI4.SPDR.UINT8[LL] 187 #define SPDR_4LH RSPI4.SPDR.UINT8[LH] 188 #define SPDR_4HL RSPI4.SPDR.UINT8[HL] 189 #define SPDR_4HH RSPI4.SPDR.UINT8[HH] 190 #define SPSCR_4 RSPI4.SPSCR 191 #define SPSSR_4 RSPI4.SPSSR 192 #define SPBR_4 RSPI4.SPBR 193 #define SPDCR_4 RSPI4.SPDCR 194 #define SPCKD_4 RSPI4.SPCKD 195 #define SSLND_4 RSPI4.SSLND 196 #define SPND_4 RSPI4.SPND 197 #define SPCMD0_4 RSPI4.SPCMD0 198 #define SPCMD1_4 RSPI4.SPCMD1 199 #define SPCMD2_4 RSPI4.SPCMD2 200 #define SPCMD3_4 RSPI4.SPCMD3 201 #define SPBFCR_4 RSPI4.SPBFCR 202 #define SPBFDR_4 RSPI4.SPBFDR 207 } r_io_rspi_t; 208 209 210 /* Channel array defines of RSPI (2)*/ 211 #ifdef DECLARE_RSPI_CHANNELS 212 volatile struct st_rspi* RSPI[ RSPI_COUNT ] = 213 /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ 214 RSPI_ADDRESS_LIST; 215 /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ 216 #endif /* DECLARE_RSPI_CHANNELS */ 217 /* End of channel array defines of RSPI (2)*/ 218 219 203 220 /* <-SEC M1.10.1 */ 221 /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ 222 /* <-QAC 0857 */ 223 /* <-QAC 0639 */ 204 224 #endif
Note:
See TracChangeset
for help on using the changeset viewer.