Changeset 374 for asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/inb_iodefine.h
- Timestamp:
- Apr 5, 2019, 9:26:53 PM (5 years ago)
- Location:
- asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX
- Files:
-
- 1 added
- 1 edited
- 1 moved
Legend:
- Unmodified
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asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/inb_iodefine.h
r352 r374 19 19 * following link: 20 20 * http://www.renesas.com/disclaimer* 21 * Copyright (C) 2013-201 4Renesas Electronics Corporation. All rights reserved.21 * Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. 22 22 *******************************************************************************/ 23 23 /******************************************************************************* … … 25 25 * $Rev: $ 26 26 * $Date:: $ 27 * Description : Definition of I/O Register (V1.00a)27 * Description : Definition of I/O Register for RZ/A1H,M (V2.00h) 28 28 ******************************************************************************/ 29 29 #ifndef INB_IODEFINE_H 30 30 #define INB_IODEFINE_H 31 /* ->QAC 0639 : Over 127 members (C90) */ 32 /* ->QAC 0857 : Over 1024 #define (C90) */ 33 /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ 34 /* ->SEC M1.10.1 : Not magic number */ 31 35 32 struct st_inb 33 { /* INB */ 36 #define INB (*(struct st_inb *)0xFCFE1A00uL) /* INB */ 37 38 39 #define INBRMPR (INB.RMPR) 40 #define INBAXIBUSCTL0 (INB.AXIBUSCTL0) 41 #define INBAXIBUSCTL1 (INB.AXIBUSCTL1) 42 #define INBAXIBUSCTL2 (INB.AXIBUSCTL2) 43 #define INBAXIBUSCTL3 (INB.AXIBUSCTL3) 44 #define INBAXIBUSCTL4 (INB.AXIBUSCTL4) 45 #define INBAXIBUSCTL5 (INB.AXIBUSCTL5) 46 #define INBAXIBUSCTL6 (INB.AXIBUSCTL6) 47 #define INBAXIBUSCTL7 (INB.AXIBUSCTL7) 48 #define INBAXIBUSCTL8 (INB.AXIBUSCTL8) 49 #define INBAXIBUSCTL9 (INB.AXIBUSCTL9) 50 #define INBAXIBUSCTL10 (INB.AXIBUSCTL10) 51 #define INBAXIRERRCTL0 (INB.AXIRERRCTL0) 52 #define INBAXIRERRCTL1 (INB.AXIRERRCTL1) 53 #define INBAXIRERRCTL2 (INB.AXIRERRCTL2) 54 #define INBAXIRERRCTL3 (INB.AXIRERRCTL3) 55 #define INBAXIRERRST0 (INB.AXIRERRST0) 56 #define INBAXIRERRST1 (INB.AXIRERRST1) 57 #define INBAXIRERRST2 (INB.AXIRERRST2) 58 #define INBAXIRERRST3 (INB.AXIRERRST3) 59 #define INBAXIRERRCLR0 (INB.AXIRERRCLR0) 60 #define INBAXIRERRCLR1 (INB.AXIRERRCLR1) 61 #define INBAXIRERRCLR2 (INB.AXIRERRCLR2) 62 #define INBAXIRERRCLR3 (INB.AXIRERRCLR3) 63 64 #define INB_AXIBUSCTLn_COUNT (11) 65 #define INB_AXIRERRCTLn_COUNT (4) 66 #define INB_AXIRERRSTn_COUNT (4) 67 #define INB_AXIRERRCLRn_COUNT (4) 68 69 70 typedef struct st_inb 71 { 72 /* INB */ 34 73 volatile uint32_t RMPR; /* RMPR */ 35 #define INB_AXIBUSCTLn_COUNT 11 74 75 /* #define INB_AXIBUSCTLn_COUNT (11) */ 36 76 volatile uint32_t AXIBUSCTL0; /* AXIBUSCTL0 */ 37 77 volatile uint32_t AXIBUSCTL1; /* AXIBUSCTL1 */ … … 45 85 volatile uint32_t AXIBUSCTL9; /* AXIBUSCTL9 */ 46 86 volatile uint32_t AXIBUSCTL10; /* AXIBUSCTL10 */ 47 #define INB_AXIRERRCTLn_COUNT 4 87 88 /* #define INB_AXIRERRCTLn_COUNT (4) */ 48 89 volatile uint32_t AXIRERRCTL0; /* AXIRERRCTL0 */ 49 90 volatile uint32_t AXIRERRCTL1; /* AXIRERRCTL1 */ 50 91 volatile uint32_t AXIRERRCTL2; /* AXIRERRCTL2 */ 51 92 volatile uint32_t AXIRERRCTL3; /* AXIRERRCTL3 */ 52 #define INB_AXIRERRSTn_COUNT 4 93 94 /* #define INB_AXIRERRSTn_COUNT (4) */ 53 95 volatile uint32_t AXIRERRST0; /* AXIRERRST0 */ 54 96 volatile uint32_t AXIRERRST1; /* AXIRERRST1 */ 55 97 volatile uint32_t AXIRERRST2; /* AXIRERRST2 */ 56 98 volatile uint32_t AXIRERRST3; /* AXIRERRST3 */ 57 #define INB_AXIRERRCLRn_COUNT 4 99 100 /* #define INB_AXIRERRCLRn_COUNT (4) */ 58 101 volatile uint32_t AXIRERRCLR0; /* AXIRERRCLR0 */ 59 102 volatile uint32_t AXIRERRCLR1; /* AXIRERRCLR1 */ 60 103 volatile uint32_t AXIRERRCLR2; /* AXIRERRCLR2 */ 61 104 volatile uint32_t AXIRERRCLR3; /* AXIRERRCLR3 */ 62 } ;105 } r_io_inb_t; 63 106 64 107 65 #define INB (*(struct st_inb *)0xFCFE1A00uL) /* INB */ 66 67 68 #define INBRMPR INB.RMPR 69 #define INBAXIBUSCTL0 INB.AXIBUSCTL0 70 #define INBAXIBUSCTL1 INB.AXIBUSCTL1 71 #define INBAXIBUSCTL2 INB.AXIBUSCTL2 72 #define INBAXIBUSCTL3 INB.AXIBUSCTL3 73 #define INBAXIBUSCTL4 INB.AXIBUSCTL4 74 #define INBAXIBUSCTL5 INB.AXIBUSCTL5 75 #define INBAXIBUSCTL6 INB.AXIBUSCTL6 76 #define INBAXIBUSCTL7 INB.AXIBUSCTL7 77 #define INBAXIBUSCTL8 INB.AXIBUSCTL8 78 #define INBAXIBUSCTL9 INB.AXIBUSCTL9 79 #define INBAXIBUSCTL10 INB.AXIBUSCTL10 80 #define INBAXIRERRCTL0 INB.AXIRERRCTL0 81 #define INBAXIRERRCTL1 INB.AXIRERRCTL1 82 #define INBAXIRERRCTL2 INB.AXIRERRCTL2 83 #define INBAXIRERRCTL3 INB.AXIRERRCTL3 84 #define INBAXIRERRST0 INB.AXIRERRST0 85 #define INBAXIRERRST1 INB.AXIRERRST1 86 #define INBAXIRERRST2 INB.AXIRERRST2 87 #define INBAXIRERRST3 INB.AXIRERRST3 88 #define INBAXIRERRCLR0 INB.AXIRERRCLR0 89 #define INBAXIRERRCLR1 INB.AXIRERRCLR1 90 #define INBAXIRERRCLR2 INB.AXIRERRCLR2 91 #define INBAXIRERRCLR3 INB.AXIRERRCLR3 108 /* <-SEC M1.10.1 */ 109 /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ 110 /* <-QAC 0857 */ 111 /* <-QAC 0639 */ 92 112 #endif
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