Ignore:
Timestamp:
Apr 5, 2019, 9:26:53 PM (5 years ago)
Author:
coas-nagasima
Message:

mbed関連を更新
シリアルドライバをmbedのHALを使うよう変更
ファイルディスクリプタの処理を更新

Location:
asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX
Files:
9 added
33 deleted
47 edited
3 copied
1 moved

Legend:

Unmodified
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  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/PeripheralNames.h

    r352 r374  
    3535} UARTName;
    3636
    37 // PWMType & 1 == 1 then have to use PWDTR[12] == 1
    3837typedef enum {
    39     PWM1A  = 0,
    40     PWM1B,
    41     PWM1C,
    42     PWM1D,
    43     PWM1E,
    44     PWM1F,
    45     PWM1G,
    46     PWM1H,
    47     PWM2A  = 0x10,
    48     PWM2B,
    49     PWM2C,
    50     PWM2D,
    51     PWM2E,
    52     PWM2F,
    53     PWM2G,
    54     PWM2H,
    55 } PWMType;
    56 
    57 typedef enum {
    58     TIOC0A  = 0,
    59     TIOC0B,
    60     TIOC0C,
    61     TIOC0D,
    62     TIOC1A = 0x10,
    63     TIOC1B,
    64     TIOC2A = 0x20,
    65     TIOC2B,
    66     TIOC3A = 0x30,
    67     TIOC3B,
    68     TIOC3C,
    69     TIOC3D,
    70     TIOC4A = 0x40,
    71     TIOC4B,
    72     TIOC4C,
    73     TIOC4D,
    74 } MTU2_PWMType;
    75 
    76 typedef enum {
    77     PWM0_PIN  = 0,
    78     PWM1_PIN,
    79     PWM2_PIN,
    80     PWM3_PIN,
    81     PWM4_PIN,
    82     PWM5_PIN,
    83     PWM6_PIN,
    84     PWM7_PIN,
    85     PWM8_PIN,
    86     PWM9_PIN,
    87     PWM10_PIN,
    88     PWM11_PIN,
    89     PWM12_PIN,
    90     PWM13_PIN,
    91     MTU2_PWM0_PIN = 0x20,
    92     MTU2_PWM1_PIN,
    93     MTU2_PWM2_PIN,
    94     MTU2_PWM3_PIN,
    95     MTU2_PWM4_PIN,
    96     MTU2_PWM5_PIN,
    97     MTU2_PWM6_PIN,
    98     MTU2_PWM7_PIN,
    99     MTU2_PWM8_PIN,
    100     MTU2_PWM9_PIN,
    101     MTU2_PWM10_PIN,
    102     MTU2_PWM11_PIN,
    103     MTU2_PWM12_PIN,
    104     MTU2_PWM13_PIN,
    105     MTU2_PWM14_PIN,
    106     MTU2_PWM15_PIN,
    107     MTU2_PWM16_PIN,
    108     MTU2_PWM17_PIN,
    109     MTU2_PWM18_PIN,
    110     MTU2_PWM19_PIN,
    111     MTU2_PWM20_PIN,
    112     MTU2_PWM21_PIN,
     38    PWM_PWM1A  = 0,
     39    PWM_PWM1B,
     40    PWM_PWM1C,
     41    PWM_PWM1D,
     42    PWM_PWM1E,
     43    PWM_PWM1F,
     44    PWM_PWM1G,
     45    PWM_PWM1H,
     46    PWM_PWM2A,
     47    PWM_PWM2B,
     48    PWM_PWM2C,
     49    PWM_PWM2D,
     50    PWM_PWM2E,
     51    PWM_PWM2F,
     52    PWM_PWM2G,
     53    PWM_PWM2H,
     54    PWM_TIOC0A = 0x20,
     55    PWM_TIOC0C,
     56    PWM_TIOC1A,
     57    PWM_TIOC2A,
     58    PWM_TIOC3A,
     59    PWM_TIOC3C,
     60    PWM_TIOC4A,
     61    PWM_TIOC4C,
    11362} PWMName;
    11463
    … …  
    12978    SPI_2,
    13079    SPI_3,
     80    SPI_4,
    13181} SPIName;
    13282
    … …  
    13585    I2C_1,
    13686    I2C_2,
    137     I2C_3 
     87    I2C_3,
    13888} I2CName;
    13989
    … …  
    14292    CAN_1,
    14393    CAN_2,
    144     CAN_3, 
    145     CAN_4
     94    CAN_3,
     95    CAN_4,
    14696} CANName;
    14797

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/PortNames.h

    r352 r374  
    2626    Port2 = 2,
    2727    Port3 = 3,
    28     Port4 = 4
     28    Port4 = 4,
     29    Port5 = 5,
     30    Port6 = 6,
     31    Port7 = 7,
     32    Port8 = 8,
     33    Port9 = 9,
     34    Port10 = 10,
     35    Port11 = 11
    2936} PortName;
    3037

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device.h

    r352 r374  
    4646
    4747#include "objects.h"
    48 #include "dma_api.h"
     48#include "hal/dma_api.h"
    4949
    5050#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/MBRZA1H.h

    r352 r374  
    1 /*******************************************************************************
    2 * DISCLAIMER
    3 * This software is supplied by Renesas Electronics Corporation and is only
    4 * intended for use with Renesas products. No other uses are authorized. This
    5 * software is owned by Renesas Electronics Corporation and is protected under
    6 * all applicable laws, including copyright laws.
    7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
    8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
    9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
    10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
    11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
    12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
    13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
    14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
    15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
    16 * Renesas reserves the right, without notice, to make changes to this software
    17 * and to discontinue the availability of this software. By using this software,
    18 * you agree to the additional terms and conditions found by accessing the
    19 * following link:
    20 * http://www.renesas.com/disclaimer
    21 * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
    22 *******************************************************************************/
    23 /**************************************************************************//**
    24  * @file     MBRZA1H.h
    25  * @brief    CMSIS Cortex-A9 Core Peripheral Access Layer Header File for
    26  *           Renesas MBRZA1H Device Series
    27  * @version
    28  * @date     19 Sept 2013
    29  *
    30  * @note
    31  *
    32  ******************************************************************************/
    33 
    34 #ifndef __MBRZA1H_H__
    35 #define __MBRZA1H_H__
    36 
    37 #ifdef __cplusplus
    38 extern "C" {
    39 #endif
    40 
    41 
    42 /* -------------------------  Interrupt Number Definition  ------------------------ */
    43 
    44 typedef enum IRQn
    45 {
    46 /******  SGI Interrupts Numbers                 ****************************************/
    47   SGI0_IRQn           =  0,
    48   SGI1_IRQn           =  1,
    49   SGI2_IRQn           =  2,
    50   SGI3_IRQn           =  3,
    51   SGI4_IRQn           =  4,
    52   SGI5_IRQn           =  5,
    53   SGI6_IRQn           =  6,
    54   SGI7_IRQn           =  7,
    55   SGI8_IRQn           =  8,
    56   SGI9_IRQn           =  9,
    57   SGI10_IRQn          = 10,
    58   SGI11_IRQn          = 11,
    59   SGI12_IRQn          = 12,
    60   SGI13_IRQn          = 13,
    61   SGI14_IRQn          = 14,
    62   SGI15_IRQn          = 15,
    63 
    64 /******  Cortex-A9 Processor Exceptions Numbers ****************************************/
    65   /* 16 - 578 */
    66   PMUIRQ0_IRQn         = 16,
    67   COMMRX0_IRQn         = 17,
    68   COMMTX0_IRQn         = 18,
    69   CTIIRQ0_IRQn         = 19,
    70 
    71   IRQ0_IRQn            = 32,
    72   IRQ1_IRQn            = 33,
    73   IRQ2_IRQn            = 34,
    74   IRQ3_IRQn            = 35,
    75   IRQ4_IRQn            = 36,
    76   IRQ5_IRQn            = 37,
    77   IRQ6_IRQn            = 38,
    78   IRQ7_IRQn            = 39,
    79 
    80   PL310ERR_IRQn        = 40,
    81 
    82   DMAINT0_IRQn         = 41,        /*!< DMAC Interrupt         */
    83   DMAINT1_IRQn         = 42,        /*!< DMAC Interrupt         */
    84   DMAINT2_IRQn         = 43,        /*!< DMAC Interrupt         */
    85   DMAINT3_IRQn         = 44,        /*!< DMAC Interrupt         */
    86   DMAINT4_IRQn         = 45,        /*!< DMAC Interrupt         */
    87   DMAINT5_IRQn         = 46,        /*!< DMAC Interrupt         */
    88   DMAINT6_IRQn         = 47,        /*!< DMAC Interrupt         */
    89   DMAINT7_IRQn         = 48,        /*!< DMAC Interrupt         */
    90   DMAINT8_IRQn         = 49,        /*!< DMAC Interrupt         */
    91   DMAINT9_IRQn         = 50,        /*!< DMAC Interrupt         */
    92   DMAINT10_IRQn        = 51,        /*!< DMAC Interrupt         */
    93   DMAINT11_IRQn        = 52,        /*!< DMAC Interrupt         */
    94   DMAINT12_IRQn        = 53,        /*!< DMAC Interrupt         */
    95   DMAINT13_IRQn        = 54,        /*!< DMAC Interrupt         */
    96   DMAINT14_IRQn        = 55,        /*!< DMAC Interrupt         */
    97   DMAINT15_IRQn        = 56,        /*!< DMAC Interrupt         */
    98   DMAERR_IRQn          = 57,        /*!< DMAC Interrupt         */
    99 
    100   /* 58-72 Reserved */
    101 
    102   USBI0_IRQn           = 73,
    103   USBI1_IRQn           = 74,
    104 
    105   S0_VI_VSYNC0_IRQn    = 75,
    106   S0_LO_VSYNC0_IRQn    = 76,
    107   S0_VSYNCERR0_IRQn    = 77,
    108   GR3_VLINE0_IRQn      = 78,
    109   S0_VFIELD0_IRQn      = 79,
    110   IV1_VBUFERR0_IRQn    = 80,
    111   IV3_VBUFERR0_IRQn    = 81,
    112   IV5_VBUFERR0_IRQn    = 82,
    113   IV6_VBUFERR0_IRQn    = 83,
    114   S0_WLINE0_IRQn       = 84,
    115   S1_VI_VSYNC0_IRQn    = 85,
    116   S1_LO_VSYNC0_IRQn    = 86,
    117   S1_VSYNCERR0_IRQn    = 87,
    118   S1_VFIELD0_IRQn      = 88,
    119   IV2_VBUFERR0_IRQn    = 89,
    120   IV4_VBUFERR0_IRQn    = 90,
    121   S1_WLINE0_IRQn       = 91,
    122   OIR_VI_VSYNC0_IRQn   = 92,
    123   OIR_LO_VSYNC0_IRQn   = 93,
    124   OIR_VSYNCERR0_IRQn   = 94,
    125   OIR_VFIELD0_IRQn     = 95,
    126   IV7_VBUFERR0_IRQn    = 96,
    127   IV8_VBUFERR0_IRQn    = 97,
    128   /* 98 Reserved */
    129   S0_VI_VSYNC1_IRQn    = 99,
    130   S0_LO_VSYNC1_IRQn    = 100,
    131   S0_VSYNCERR1_IRQn    = 101,
    132   GR3_VLINE1_IRQn      = 102,
    133   S0_VFIELD1_IRQn      = 103,
    134   IV1_VBUFERR1_IRQn    = 104,
    135   IV3_VBUFERR1_IRQn    = 105,
    136   IV5_VBUFERR1_IRQn    = 106,
    137   IV6_VBUFERR1_IRQn    = 107,
    138   S0_WLINE1_IRQn       = 108,
    139   S1_VI_VSYNC1_IRQn    = 109,
    140   S1_LO_VSYNC1_IRQn    = 110,
    141   S1_VSYNCERR1_IRQn    = 111,
    142   S1_VFIELD1_IRQn      = 112,
    143   IV2_VBUFERR1_IRQn    = 113,
    144   IV4_VBUFERR1_IRQn    = 114,
    145   S1_WLINE1_IRQn       = 115,
    146   OIR_VI_VSYNC1_IRQn   = 116,
    147   OIR_LO_VSYNC1_IRQn   = 117,
    148   OIR_VSYNCERR1_IRQn   = 118,
    149   OIR_VFIELD1_IRQn     = 119,
    150   IV7_VBUFERR1_IRQn    = 120,
    151   IV8_VBUFERR1_IRQn    = 121,
    152   /* Reserved = 122 */
    153 
    154   IMRDI_IRQn           = 123,
    155   IMR2I0_IRQn          = 124,
    156   IMR2I1_IRQn          = 125,
    157 
    158   JEDI_IRQn            = 126,
    159   JDTI_IRQn            = 127,
    160 
    161   CMP0_IRQn            = 128,
    162   CMP1_IRQn            = 129,
    163 
    164   INT0_IRQn            = 130,
    165   INT1_IRQn            = 131,
    166   INT2_IRQn            = 132,
    167   INT3_IRQn            = 133,
    168 
    169   OSTMI0TINT_IRQn      = 134,       /*!< OSTM Interrupt         */
    170   OSTMI1TINT_IRQn      = 135,       /*!< OSTM Interrupt         */
    171 
    172   CMI_IRQn             = 136,
    173   WTOUT_IRQn           = 137,
    174 
    175   ITI_IRQn             = 138,
    176 
    177   TGI0A_IRQn           = 139,
    178   TGI0B_IRQn           = 140,
    179   TGI0C_IRQn           = 141,
    180   TGI0D_IRQn           = 142,
    181   TGI0V_IRQn           = 143,
    182   TGI0E_IRQn           = 144,
    183   TGI0F_IRQn           = 145,
    184   TGI1A_IRQn           = 146,
    185   TGI1B_IRQn           = 147,
    186   TGI1V_IRQn           = 148,
    187   TGI1U_IRQn           = 149,
    188   TGI2A_IRQn           = 150,
    189   TGI2B_IRQn           = 151,
    190   TGI2V_IRQn           = 152,
    191   TGI2U_IRQn           = 153,
    192   TGI3A_IRQn           = 154,
    193   TGI3B_IRQn           = 155,
    194   TGI3C_IRQn           = 156,
    195   TGI3D_IRQn           = 157,
    196   TGI3V_IRQn           = 158,
    197   TGI4A_IRQn           = 159,
    198   TGI4B_IRQn           = 160,
    199   TGI4C_IRQn           = 161,
    200   TGI4D_IRQn           = 162,
    201   TGI4V_IRQn           = 163,
    202 
    203   CMI1_IRQn            = 164,
    204   CMI2_IRQn            = 165,
    205 
    206   SGDEI0_IRQn          = 166,
    207   SGDEI1_IRQn          = 167,
    208   SGDEI2_IRQn          = 168,
    209   SGDEI3_IRQn          = 169,
    210 
    211   ADI_IRQn             = 170,
    212   LMTI_IRQn            = 171,
    213 
    214   SSII0_IRQn           = 172,       /*!< SSIF Interrupt         */
    215   SSIRXI0_IRQn         = 173,       /*!< SSIF Interrupt         */
    216   SSITXI0_IRQn         = 174,       /*!< SSIF Interrupt         */
    217   SSII1_IRQn           = 175,       /*!< SSIF Interrupt         */
    218   SSIRXI1_IRQn         = 176,       /*!< SSIF Interrupt         */
    219   SSITXI1_IRQn         = 177,       /*!< SSIF Interrupt         */
    220   SSII2_IRQn           = 178,       /*!< SSIF Interrupt         */
    221   SSIRTI2_IRQn         = 179,       /*!< SSIF Interrupt         */
    222   SSII3_IRQn           = 180,       /*!< SSIF Interrupt         */
    223   SSIRXI3_IRQn         = 181,       /*!< SSIF Interrupt         */
    224   SSITXI3_IRQn         = 182,       /*!< SSIF Interrupt         */
    225   SSII4_IRQn           = 183,       /*!< SSIF Interrupt         */
    226   SSIRTI4_IRQn         = 184,       /*!< SSIF Interrupt         */
    227   SSII5_IRQn           = 185,       /*!< SSIF Interrupt         */
    228   SSIRXI5_IRQn         = 186,       /*!< SSIF Interrupt         */
    229   SSITXI5_IRQn         = 187,       /*!< SSIF Interrupt         */
    230 
    231   SPDIFI_IRQn          = 188,
    232 
    233   INTIICTEI0_IRQn      = 189,       /*!< RIIC Interrupt         */
    234   INTIICRI0_IRQn       = 190,       /*!< RIIC Interrupt         */
    235   INTIICTI0_IRQn       = 191,       /*!< RIIC Interrupt         */
    236   INTIICSPI0_IRQn      = 192,       /*!< RIIC Interrupt         */
    237   INTIICSTI0_IRQn      = 193,       /*!< RIIC Interrupt         */
    238   INTIICNAKI0_IRQn     = 194,       /*!< RIIC Interrupt         */
    239   INTIICALI0_IRQn      = 195,       /*!< RIIC Interrupt         */
    240   INTIICTMOI0_IRQn     = 196,       /*!< RIIC Interrupt         */
    241   INTIICTEI1_IRQn      = 197,       /*!< RIIC Interrupt         */
    242   INTIICRI1_IRQn       = 198,       /*!< RIIC Interrupt         */
    243   INTIICTI1_IRQn       = 199,       /*!< RIIC Interrupt         */
    244   INTIICSPI1_IRQn      = 200,       /*!< RIIC Interrupt         */
    245   INTIICSTI1_IRQn      = 201,       /*!< RIIC Interrupt         */
    246   INTIICNAKI1_IRQn     = 202,       /*!< RIIC Interrupt         */
    247   INTIICALI1_IRQn      = 203,       /*!< RIIC Interrupt         */
    248   INTIICTMOI1_IRQn     = 204,       /*!< RIIC Interrupt         */
    249   INTIICTEI2_IRQn      = 205,       /*!< RIIC Interrupt         */
    250   INTIICRI2_IRQn       = 206,       /*!< RIIC Interrupt         */
    251   INTIICTI2_IRQn       = 207,       /*!< RIIC Interrupt         */
    252   INTIICSPI2_IRQn      = 208,       /*!< RIIC Interrupt         */
    253   INTIICSTI2_IRQn      = 209,       /*!< RIIC Interrupt         */
    254   INTIICNAKI2_IRQn     = 210,       /*!< RIIC Interrupt         */
    255   INTIICALI2_IRQn      = 211,       /*!< RIIC Interrupt         */
    256   INTIICTMOI2_IRQn     = 212,       /*!< RIIC Interrupt         */
    257   INTIICTEI3_IRQn      = 213,       /*!< RIIC Interrupt         */
    258   INTIICRI3_IRQn       = 214,       /*!< RIIC Interrupt         */
    259   INTIICTI3_IRQn       = 215,       /*!< RIIC Interrupt         */
    260   INTIICSPI3_IRQn      = 216,       /*!< RIIC Interrupt         */
    261   INTIICSTI3_IRQn      = 217,       /*!< RIIC Interrupt         */
    262   INTIICNAKI3_IRQn     = 218,       /*!< RIIC Interrupt         */
    263   INTIICALI3_IRQn      = 219,       /*!< RIIC Interrupt         */
    264   INTIICTMOI3_IRQn     = 220,       /*!< RIIC Interrupt         */
    265 
    266   SCIFBRI0_IRQn        = 221,       /*!< SCIF Interrupt         */
    267   SCIFERI0_IRQn        = 222,       /*!< SCIF Interrupt         */
    268   SCIFRXI0_IRQn        = 223,       /*!< SCIF Interrupt         */
    269   SCIFTXI0_IRQn        = 224,       /*!< SCIF Interrupt         */
    270   SCIFBRI1_IRQn        = 225,       /*!< SCIF Interrupt         */
    271   SCIFERI1_IRQn        = 226,       /*!< SCIF Interrupt         */
    272   SCIFRXI1_IRQn        = 227,       /*!< SCIF Interrupt         */
    273   SCIFTXI1_IRQn        = 228,       /*!< SCIF Interrupt         */
    274   SCIFBRI2_IRQn        = 229,       /*!< SCIF Interrupt         */
    275   SCIFERI2_IRQn        = 230,       /*!< SCIF Interrupt         */
    276   SCIFRXI2_IRQn        = 231,       /*!< SCIF Interrupt         */
    277   SCIFTXI2_IRQn        = 232,       /*!< SCIF Interrupt         */
    278   SCIFBRI3_IRQn        = 233,       /*!< SCIF Interrupt         */
    279   SCIFERI3_IRQn        = 234,       /*!< SCIF Interrupt         */
    280   SCIFRXI3_IRQn        = 235,       /*!< SCIF Interrupt         */
    281   SCIFTXI3_IRQn        = 236,       /*!< SCIF Interrupt         */
    282   SCIFBRI4_IRQn        = 237,       /*!< SCIF Interrupt         */
    283   SCIFERI4_IRQn        = 238,       /*!< SCIF Interrupt         */
    284   SCIFRXI4_IRQn        = 239,       /*!< SCIF Interrupt         */
    285   SCIFTXI4_IRQn        = 240,       /*!< SCIF Interrupt         */
    286   SCIFBRI5_IRQn        = 241,       /*!< SCIF Interrupt         */
    287   SCIFERI5_IRQn        = 242,       /*!< SCIF Interrupt         */
    288   SCIFRXI5_IRQn        = 243,       /*!< SCIF Interrupt         */
    289   SCIFTXI5_IRQn        = 244,       /*!< SCIF Interrupt         */
    290   SCIFBRI6_IRQn        = 245,       /*!< SCIF Interrupt         */
    291   SCIFERI6_IRQn        = 246,       /*!< SCIF Interrupt         */
    292   SCIFRXI6_IRQn        = 247,       /*!< SCIF Interrupt         */
    293   SCIFTXI6_IRQn        = 248,       /*!< SCIF Interrupt         */
    294   SCIFBRI7_IRQn        = 249,       /*!< SCIF Interrupt         */
    295   SCIFERI7_IRQn        = 250,       /*!< SCIF Interrupt         */
    296   SCIFRXI7_IRQn        = 251,       /*!< SCIF Interrupt         */
    297   SCIFTXI7_IRQn        = 252,       /*!< SCIF Interrupt         */
    298 
    299   INTRCANGERR_IRQn     = 253,
    300   INTRCANGRECC_IRQn    = 254,
    301   INTRCAN0REC_IRQn     = 255,
    302   INTRCAN0ERR_IRQn     = 256,
    303   INTRCAN0TRX_IRQn     = 257,
    304   INTRCAN1REC_IRQn     = 258,
    305   INTRCAN1ERR_IRQn     = 259,
    306   INTRCAN1TRX_IRQn     = 260,
    307   INTRCAN2REC_IRQn     = 261,
    308   INTRCAN2ERR_IRQn     = 262,
    309   INTRCAN2TRX_IRQn     = 263,
    310   INTRCAN3REC_IRQn     = 264,
    311   INTRCAN3ERR_IRQn     = 265,
    312   INTRCAN3TRX_IRQn     = 266,
    313   INTRCAN4REC_IRQn     = 267,
    314   INTRCAN4ERR_IRQn     = 268,
    315   INTRCAN4TRX_IRQn     = 269,
    316 
    317   RSPISPEI0_IRQn       = 270,       /*!< RSPI Interrupt         */
    318   RSPISPRI0_IRQn       = 271,       /*!< RSPI Interrupt         */
    319   RSPISPTI0_IRQn       = 272,       /*!< RSPI Interrupt         */
    320   RSPISPEI1_IRQn       = 273,       /*!< RSPI Interrupt         */
    321   RSPISPRI1_IRQn       = 274,       /*!< RSPI Interrupt         */
    322   RSPISPTI1_IRQn       = 275,       /*!< RSPI Interrupt         */
    323   RSPISPEI2_IRQn       = 276,       /*!< RSPI Interrupt         */
    324   RSPISPRI2_IRQn       = 277,       /*!< RSPI Interrupt         */
    325   RSPISPTI2_IRQn       = 278,       /*!< RSPI Interrupt         */
    326   RSPISPEI3_IRQn       = 279,       /*!< RSPI Interrupt         */
    327   RSPISPRI3_IRQn       = 280,       /*!< RSPI Interrupt         */
    328   RSPISPTI3_IRQn       = 281,       /*!< RSPI Interrupt         */
    329   RSPISPEI4_IRQn       = 282,       /*!< RSPI Interrupt         */
    330   RSPISPRI4_IRQn       = 283,       /*!< RSPI Interrupt         */
    331   RSPISPTI4_IRQn       = 284,       /*!< RSPI Interrupt         */
    332 
    333   IEBBTD_IRQn          = 285,
    334   IEBBTERR_IRQn        = 286,
    335   IEBBTSTA_IRQn        = 287,
    336   IEBBTV_IRQn          = 288,
    337 
    338   ISY_IRQn             = 289,
    339   IERR_IRQn            = 290,
    340   ITARG_IRQn           = 291,
    341   ISEC_IRQn            = 292,
    342   IBUF_IRQn            = 293,
    343   IREADY_IRQn          = 294,
    344 
    345   STERB_IRQn           = 295,
    346   FLTENDI_IRQn         = 296,
    347   FLTREQ0I_IRQn        = 297,
    348   FLTREQ1I_IRQn        = 298,
    349 
    350   MMC0_IRQn            = 299,
    351   MMC1_IRQn            = 300,
    352   MMC2_IRQn            = 301,
    353 
    354   SCHI0_3_IRQn         = 302,
    355   SDHI0_0_IRQn         = 303,
    356   SDHI0_1_IRQn         = 304,
    357   SCHI1_3_IRQn         = 305,
    358   SDHI1_0_IRQn         = 306,
    359   SDHI1_1_IRQn         = 307,
    360 
    361   ARM_IRQn             = 308,
    362   PRD_IRQn             = 309,
    363   CUP_IRQn             = 310,
    364 
    365   SCUAI0_IRQn          = 311,
    366   SCUAI1_IRQn          = 312,
    367   SCUFDI0_IRQn         = 313,
    368   SCUFDI1_IRQn         = 314,
    369   SCUFDI2_IRQn         = 315,
    370   SCUFDI3_IRQn         = 316,
    371   SCUFUI0_IRQn         = 317,
    372   SCUFUI1_IRQn         = 318,
    373   SCUFUI2_IRQn         = 319,
    374   SCUFUI3_IRQn         = 320,
    375   SCUDVI0_IRQn         = 321,
    376   SCUDVI1_IRQn         = 322,
    377   SCUDVI2_IRQn         = 323,
    378   SCUDVI3_IRQn         = 324,
    379 
    380   MLB_CINT_IRQn        = 325,
    381   MLB_SINT_IRQn        = 326,
    382 
    383   DRC10_IRQn           = 327,
    384   DRC11_IRQn           = 328,
    385 
    386   /* 329-330 Reserved  */
    387 
    388   LINI0_INT_T_IRQn     = 331,
    389   LINI0_INT_R_IRQn     = 332,
    390   LINI0_INT_S_IRQn     = 333,
    391   LINI0_INT_M_IRQn     = 334,
    392   LINI1_INT_T_IRQn     = 335,
    393   LINI1_INT_R_IRQn     = 336,
    394   LINI1_INT_S_IRQn     = 337,
    395   LINI1_INT_M_IRQn     = 338,
    396 
    397   /* 339-346 Reserved */
    398 
    399   SCIERI0_IRQn         = 347,
    400   SCIRXI0_IRQn         = 348,
    401   SCITXI0_IRQn         = 349,
    402   SCITEI0_IRQn         = 350,
    403   SCIERI1_IRQn         = 351,
    404   SCIRXI1_IRQn         = 352,
    405   SCITXI1_IRQn         = 353,
    406   SCITEI1_IRQn         = 354,
    407 
    408   AVBI_DATA            = 355,
    409   AVBI_ERROR           = 356,
    410   AVBI_MANAGE          = 357,
    411   AVBI_MAC             = 358,
    412 
    413   ETHERI_IRQn          = 359,
    414 
    415   /* 360-363 Reserved */
    416 
    417   CEUI_IRQn            = 364,
    418 
    419   /* 365-380 Reserved */
    420 
    421 
    422   H2XMLB_ERRINT_IRQn   = 381,
    423   H2XIC1_ERRINT_IRQn   = 382,
    424   X2HPERI1_ERRINT_IRQn = 383,
    425   X2HPERR2_ERRINT_IRQn = 384,
    426   X2HPERR34_ERRINT_IRQn= 385,
    427   X2HPERR5_ERRINT_IRQn = 386,
    428   X2HPERR67_ERRINT_IRQn= 387,
    429   X2HDBGR_ERRINT_IRQn  = 388,
    430   X2HBSC_ERRINT_IRQn   = 389,   
    431   X2HSPI1_ERRINT_IRQn  = 390,   
    432   X2HSPI2_ERRINT_IRQn  = 391,   
    433   PRRI_IRQn            = 392,
    434 
    435   IFEI0_IRQn           = 393,
    436   OFFI0_IRQn           = 394,
    437   PFVEI0_IRQn          = 395,
    438   IFEI1_IRQn           = 396,
    439   OFFI1_IRQn           = 397,
    440   PFVEI1_IRQn          = 398,
    441 
    442   /* 399-415 Reserved */
    443   TINT0_IRQn           = 416,
    444   TINT1_IRQn           = 417,
    445   TINT2_IRQn           = 418,
    446   TINT3_IRQn           = 419,
    447   TINT4_IRQn           = 420,
    448   TINT5_IRQn           = 421,
    449   TINT6_IRQn           = 422,
    450   TINT7_IRQn           = 423,
    451   TINT8_IRQn           = 424,
    452   TINT9_IRQn           = 425,
    453   TINT10_IRQn          = 426,
    454   TINT11_IRQn          = 427,
    455   TINT12_IRQn          = 428,
    456   TINT13_IRQn          = 429,
    457   TINT14_IRQn          = 430,
    458   TINT15_IRQn          = 431,
    459   TINT16_IRQn          = 432,
    460   TINT17_IRQn          = 433,
    461   TINT18_IRQn          = 434,
    462   TINT19_IRQn          = 435,
    463   TINT20_IRQn          = 436,
    464   TINT21_IRQn          = 437,
    465   TINT22_IRQn          = 438,
    466   TINT23_IRQn          = 439,
    467   TINT24_IRQn          = 440,
    468   TINT25_IRQn          = 441,
    469   TINT26_IRQn          = 442,
    470   TINT27_IRQn          = 443,
    471   TINT28_IRQn          = 444,
    472   TINT29_IRQn          = 445,
    473   TINT30_IRQn          = 446,
    474   TINT31_IRQn          = 447,
    475   TINT32_IRQn          = 448,
    476   TINT33_IRQn          = 449,
    477   TINT34_IRQn          = 450,
    478   TINT35_IRQn          = 451,
    479   TINT36_IRQn          = 452,
    480   TINT37_IRQn          = 453,
    481   TINT38_IRQn          = 454,
    482   TINT39_IRQn          = 455,
    483   TINT40_IRQn          = 456,
    484   TINT41_IRQn          = 457,
    485   TINT42_IRQn          = 458,
    486   TINT43_IRQn          = 459,
    487   TINT44_IRQn          = 460,
    488   TINT45_IRQn          = 461,
    489   TINT46_IRQn          = 462,
    490   TINT47_IRQn          = 463,
    491   TINT48_IRQn          = 464,
    492   TINT49_IRQn          = 465,
    493   TINT50_IRQn          = 466,
    494   TINT51_IRQn          = 467,
    495   TINT52_IRQn          = 468,
    496   TINT53_IRQn          = 469,
    497   TINT54_IRQn          = 470,
    498   TINT55_IRQn          = 471,
    499   TINT56_IRQn          = 472,
    500   TINT57_IRQn          = 473,
    501   TINT58_IRQn          = 474,
    502   TINT59_IRQn          = 475,
    503   TINT60_IRQn          = 476,
    504   TINT61_IRQn          = 477,
    505   TINT62_IRQn          = 478,
    506   TINT63_IRQn          = 479,
    507   TINT64_IRQn          = 480,
    508   TINT65_IRQn          = 481,
    509   TINT66_IRQn          = 482,
    510   TINT67_IRQn          = 483,
    511   TINT68_IRQn          = 484,
    512   TINT69_IRQn          = 485,
    513   TINT70_IRQn          = 486,
    514   TINT71_IRQn          = 487,
    515   TINT72_IRQn          = 488,
    516   TINT73_IRQn          = 489,
    517   TINT74_IRQn          = 490,
    518   TINT75_IRQn          = 491,
    519   TINT76_IRQn          = 492,
    520   TINT77_IRQn          = 493,
    521   TINT78_IRQn          = 494,
    522   TINT79_IRQn          = 495,
    523   TINT80_IRQn          = 496,
    524   TINT81_IRQn          = 497,
    525   TINT82_IRQn          = 498,
    526   TINT83_IRQn          = 499,
    527   TINT84_IRQn          = 500,
    528   TINT85_IRQn          = 501,
    529   TINT86_IRQn          = 502,
    530   TINT87_IRQn          = 503,
    531   TINT88_IRQn          = 504,
    532   TINT89_IRQn          = 505,
    533   TINT90_IRQn          = 506,
    534   TINT91_IRQn          = 507,
    535   TINT92_IRQn          = 508,
    536   TINT93_IRQn          = 509,
    537   TINT94_IRQn          = 510,
    538   TINT95_IRQn          = 511,
    539   TINT96_IRQn          = 512,
    540   TINT97_IRQn          = 513,
    541   TINT98_IRQn          = 514,
    542   TINT99_IRQn          = 515,
    543   TINT100_IRQn         = 516,
    544   TINT101_IRQn         = 517,
    545   TINT102_IRQn         = 518,
    546   TINT103_IRQn         = 519,
    547   TINT104_IRQn         = 520,
    548   TINT105_IRQn         = 521,
    549   TINT106_IRQn         = 522,
    550   TINT107_IRQn         = 523,
    551   TINT108_IRQn         = 524,
    552   TINT109_IRQn         = 525,
    553   TINT110_IRQn         = 526,
    554   TINT111_IRQn         = 527,
    555   TINT112_IRQn         = 528,
    556   TINT113_IRQn         = 529,
    557   TINT114_IRQn         = 530,
    558   TINT115_IRQn         = 531,
    559   TINT116_IRQn         = 532,
    560   TINT117_IRQn         = 533,
    561   TINT118_IRQn         = 534,
    562   TINT119_IRQn         = 535,
    563   TINT120_IRQn         = 536,
    564   TINT121_IRQn         = 537,
    565   TINT122_IRQn         = 538,
    566   TINT123_IRQn         = 539,
    567   TINT124_IRQn         = 540,
    568   TINT125_IRQn         = 541,
    569   TINT126_IRQn         = 542,
    570   TINT127_IRQn         = 543,
    571   TINT128_IRQn         = 544,
    572   TINT129_IRQn         = 545,
    573   TINT130_IRQn         = 546,
    574   TINT131_IRQn         = 547,
    575   TINT132_IRQn         = 548,
    576   TINT133_IRQn         = 549,
    577   TINT134_IRQn         = 550,
    578   TINT135_IRQn         = 551,
    579   TINT136_IRQn         = 552,
    580   TINT137_IRQn         = 553,
    581   TINT138_IRQn         = 554,
    582   TINT139_IRQn         = 555,
    583   TINT140_IRQn         = 556,
    584   TINT141_IRQn         = 557,
    585   TINT142_IRQn         = 558,
    586   TINT143_IRQn         = 559,
    587   TINT144_IRQn         = 560,
    588   TINT145_IRQn         = 561,
    589   TINT146_IRQn         = 562,
    590   TINT147_IRQn         = 563,
    591   TINT148_IRQn         = 564,
    592   TINT149_IRQn         = 565,
    593   TINT150_IRQn         = 566,
    594   TINT151_IRQn         = 567,
    595   TINT152_IRQn         = 568,
    596   TINT153_IRQn         = 569,
    597   TINT154_IRQn         = 570,
    598   TINT155_IRQn         = 571,
    599   TINT156_IRQn         = 572,
    600   TINT157_IRQn         = 573,
    601   TINT158_IRQn         = 574,
    602   TINT159_IRQn         = 575,
    603   TINT160_IRQn         = 576,
    604   TINT161_IRQn         = 577,
    605   TINT162_IRQn         = 578,
    606   TINT163_IRQn         = 579,
    607   TINT164_IRQn         = 580,
    608   TINT165_IRQn         = 581,
    609   TINT166_IRQn         = 582,
    610   TINT167_IRQn         = 583,
    611   TINT168_IRQn         = 584,
    612   TINT169_IRQn         = 585,
    613   TINT170_IRQn         = 586
    614 
    615 } IRQn_Type;
    616 
    617 #define Renesas_RZ_A1_IRQ_MAX  TINT170_IRQn
    618 
    619 /* --------  Configuration of the Cortex-A9 Processor and Core Peripherals  ------- */
    620 #define __CA9_REV                 0x0000    /*!< Core revision r0                                */
    621 
    622 #define __MPU_PRESENT             1         /*!< MPU present or not                               */
    623 
    624 #define __FPU_PRESENT             1         /*!< FPU present or not                               */
    625 
    626 #define __NVIC_PRIO_BITS          5         /*!< Number of Bits used for Priority Levels          */
    627 #define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
    628 
    629 #include <core_ca9.h>
    630 #include "system_MBRZA1H.h"
    631 
    632 
    633 /******************************************************************************/
    634 /*                Device Specific Peripheral Section                          */
    635 /******************************************************************************/
    636 /** @addtogroup Renesas_RZ_A1_Peripherals Renesas_RZ_A1 Peripherals
    637   Renesas_RZ_A1 Device Specific Peripheral registers structures
    638   @{
    639 */
    640 
    641 #if defined ( __CC_ARM   )
    642 #pragma anon_unions
    643 #endif
    644 
    645 #include "pl310.h"
    646 #include "gic.h"
    647 #include "nvic_wrapper.h"
    648 #include "cmsis_nvic.h"
    649 
    650 #include "ostm_iodefine.h"
    651 #include "gpio_iodefine.h"
    652 #include "cpg_iodefine.h"
    653 #include "l2c_iodefine.h"
    654 
    655 #if defined ( __CC_ARM   )
    656 #pragma no_anon_unions
    657 #endif
    658 
    659 /*@}*/ /* end of group Renesas_RZ_A1_Peripherals */
    660 
    661 
    662 /******************************************************************************/
    663 /*                         Peripheral memory map                              */
    664 /******************************************************************************/
    665 /** @addtogroup Renesas_RZ_A1_MemoryMap Renesas_RZ_A1 Memory Mapping
    666   @{
    667 */
    668 
    669 /* R7S72100 CPU board  */
    670 #define Renesas_RZ_A1_NORFLASH_BASE0               (0x00000000UL)                        /*!< (FLASH0    ) Base Address */
    671 #define Renesas_RZ_A1_NORFLASH_BASE1               (0x04000000UL)                        /*!< (FLASH1    ) Base Address */
    672 #define Renesas_RZ_A1_SDRAM_BASE0                  (0x08000000UL)                        /*!< (SDRAM0    ) Base Address */
    673 #define Renesas_RZ_A1_SDRAM_BASE1                  (0x0C000000UL)                        /*!< (SDRAM1    ) Base Address */
    674 #define Renesas_RZ_A1_USER_AREA0                   (0x10000000UL)                        /*!< (USER0     ) Base Address */
    675 #define Renesas_RZ_A1_USER_AREA1                   (0x14000000UL)                        /*!< (USER1     ) Base Address */
    676 #define Renesas_RZ_A1_SPI_IO0                      (0x18000000UL)                        /*!< (SPI_IO0   ) Base Address */
    677 #define Renesas_RZ_A1_SPI_IO1                      (0x1C000000UL)                        /*!< (SPI_IO1   ) Base Address */
    678 #define Renesas_RZ_A1_ONCHIP_SRAM_BASE             (0x20000000UL)                        /*!< (SRAM_OC   ) Base Address */
    679 #define Renesas_RZ_A1_SPI_MIO_BASE                 (0x3fe00000UL)                        /*!< (SPI_MIO   ) Base Address */
    680 #define Renesas_RZ_A1_BSC_BASE                     (0x3ff00000UL)                        /*!< (BSC       ) Base Address */
    681 #define Renesas_RZ_A1_PERIPH_BASE0                 (0xe8000000UL)                        /*!< (PERIPH0   ) Base Address */
    682 #define Renesas_RZ_A1_PERIPH_BASE1                 (0xfcf00000UL)                        /*!< (PERIPH1   ) Base Address */
    683 #define Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE         (0xe8201000UL)                        /*!< (GIC DIST  ) Base Address */
    684 #define Renesas_RZ_A1_GIC_INTERFACE_BASE           (0xe8202000UL)                        /*!< (GIC CPU IF) Base Address */
    685 #define Renesas_RZ_A1_PL310_BASE                   (0x3ffff000UL)                        /*!< (PL310     ) Base Address */
    686 #define Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE          (0x60000000UL)                        /*!< (SRAM_OC   ) Base Address */
    687 
    688 //Following macros define the descriptors and attributes used to define the Renesas_RZ_A1 MMU flat-map
    689 //Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0.
    690 #define section_normal(descriptor_l1, region)     region.rg_t = SECTION; \
    691                                    region.domain = 0x0; \
    692                                    region.e_t = ECC_DISABLED; \
    693                                    region.g_t = GLOBAL; \
    694                                    region.inner_norm_t = WB_WA; \
    695                                    region.outer_norm_t = WB_WA; \
    696                                    region.mem_t = NORMAL; \
    697                                    region.sec_t = NON_SECURE; \
    698                                    region.xn_t = EXECUTE; \
    699                                    region.priv_t = RW; \
    700                                    region.user_t = RW; \
    701                                    region.sh_t = NON_SHARED; \
    702                                    __get_section_descriptor(&descriptor_l1, region);
    703 
    704 #define section_normal_nc(descriptor_l1, region)     region.rg_t = SECTION; \
    705                                    region.domain = 0x0; \
    706                                    region.e_t = ECC_DISABLED; \
    707                                    region.g_t = GLOBAL; \
    708                                    region.inner_norm_t = NON_CACHEABLE; \
    709                                    region.outer_norm_t = NON_CACHEABLE; \
    710                                    region.mem_t = NORMAL; \
    711                                    region.sec_t = SECURE; \
    712                                    region.xn_t = EXECUTE; \
    713                                    region.priv_t = RW; \
    714                                    region.user_t = RW; \
    715                                    region.sh_t = NON_SHARED; \
    716                                    __get_section_descriptor(&descriptor_l1, region);
    717 
    718 //Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0.
    719 #define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
    720                                    region.domain = 0x0; \
    721                                    region.e_t = ECC_DISABLED; \
    722                                    region.g_t = GLOBAL; \
    723                                    region.inner_norm_t = WB_WA; \
    724                                    region.outer_norm_t = WB_WA; \
    725                                    region.mem_t = NORMAL; \
    726                                    region.sec_t = NON_SECURE; \
    727                                    region.xn_t = EXECUTE; \
    728                                    region.priv_t = READ; \
    729                                    region.user_t = READ; \
    730                                    region.sh_t = NON_SHARED; \
    731                                    __get_section_descriptor(&descriptor_l1, region);
    732 
    733 //Sect_Normal_RO. Sect_Normal_Cod, but not executable
    734 #define section_normal_ro(descriptor_l1, region)  region.rg_t = SECTION; \
    735                                    region.domain = 0x0; \
    736                                    region.e_t = ECC_DISABLED; \
    737                                    region.g_t = GLOBAL; \
    738                                    region.inner_norm_t = WB_WA; \
    739                                    region.outer_norm_t = WB_WA; \
    740                                    region.mem_t = NORMAL; \
    741                                    region.sec_t = NON_SECURE; \
    742                                    region.xn_t = NON_EXECUTE; \
    743                                    region.priv_t = READ; \
    744                                    region.user_t = READ; \
    745                                    region.sh_t = NON_SHARED; \
    746                                    __get_section_descriptor(&descriptor_l1, region);
    747 
    748 //Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
    749 #define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
    750                                    region.domain = 0x0; \
    751                                    region.e_t = ECC_DISABLED; \
    752                                    region.g_t = GLOBAL; \
    753                                    region.inner_norm_t = WB_WA; \
    754                                    region.outer_norm_t = WB_WA; \
    755                                    region.mem_t = NORMAL; \
    756                                    region.sec_t = NON_SECURE; \
    757                                    region.xn_t = EXECUTE; \
    758                                    region.priv_t = RW; \
    759                                    region.user_t = RW; \
    760                                    region.sh_t = NON_SHARED; \
    761                                    __get_section_descriptor(&descriptor_l1, region);
    762 
    763 //Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
    764 #define section_so(descriptor_l1, region) region.rg_t = SECTION; \
    765                                    region.domain = 0x0; \
    766                                    region.e_t = ECC_DISABLED; \
    767                                    region.g_t = GLOBAL; \
    768                                    region.inner_norm_t = NON_CACHEABLE; \
    769                                    region.outer_norm_t = NON_CACHEABLE; \
    770                                    region.mem_t = STRONGLY_ORDERED; \
    771                                    region.sec_t = SECURE; \
    772                                    region.xn_t = NON_EXECUTE; \
    773                                    region.priv_t = RW; \
    774                                    region.user_t = RW; \
    775                                    region.sh_t = NON_SHARED; \
    776                                    __get_section_descriptor(&descriptor_l1, region);
    777 
    778 //Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
    779 #define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
    780                                    region.domain = 0x0; \
    781                                    region.e_t = ECC_DISABLED; \
    782                                    region.g_t = GLOBAL; \
    783                                    region.inner_norm_t = NON_CACHEABLE; \
    784                                    region.outer_norm_t = NON_CACHEABLE; \
    785                                    region.mem_t = STRONGLY_ORDERED; \
    786                                    region.sec_t = SECURE; \
    787                                    region.xn_t = NON_EXECUTE; \
    788                                    region.priv_t = READ; \
    789                                    region.user_t = READ; \
    790                                    region.sh_t = NON_SHARED; \
    791                                    __get_section_descriptor(&descriptor_l1, region);
    792    
    793 //Sect_Device_RW. Sect_Device_RO, but writeable
    794 #define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
    795                                    region.domain = 0x0; \
    796                                    region.e_t = ECC_DISABLED; \
    797                                    region.g_t = GLOBAL; \
    798                                    region.inner_norm_t = NON_CACHEABLE; \
    799                                    region.outer_norm_t = NON_CACHEABLE; \
    800                                    region.mem_t = STRONGLY_ORDERED; \
    801                                    region.sec_t = SECURE; \
    802                                    region.xn_t = NON_EXECUTE; \
    803                                    region.priv_t = RW; \
    804                                    region.user_t = RW; \
    805                                    region.sh_t = NON_SHARED; \
    806                                    __get_section_descriptor(&descriptor_l1, region);
    807 //Page_4k_Device_RW.  Shared device, not executable, rw, domain 0
    808 #define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
    809                                    region.domain = 0x0; \
    810                                    region.e_t = ECC_DISABLED; \
    811                                    region.g_t = GLOBAL; \
    812                                    region.inner_norm_t = NON_CACHEABLE; \
    813                                    region.outer_norm_t = NON_CACHEABLE; \
    814                                    region.mem_t = SHARED_DEVICE; \
    815                                    region.sec_t = SECURE; \
    816                                    region.xn_t = NON_EXECUTE; \
    817                                    region.priv_t = RW; \
    818                                    region.user_t = RW; \
    819                                    region.sh_t = NON_SHARED; \
    820                                    __get_page_descriptor(&descriptor_l1, &descriptor_l2, region);
    821 
    822 //Page_64k_Device_RW.  Shared device, not executable, rw, domain 0
    823 #define page64k_device_rw(descriptor_l1, descriptor_l2, region)  region.rg_t = PAGE_64k; \
    824                                    region.domain = 0x0; \
    825                                    region.e_t = ECC_DISABLED; \
    826                                    region.g_t = GLOBAL; \
    827                                    region.inner_norm_t = NON_CACHEABLE; \
    828                                    region.outer_norm_t = NON_CACHEABLE; \
    829                                    region.mem_t = SHARED_DEVICE; \
    830                                    region.sec_t = SECURE; \
    831                                    region.xn_t = NON_EXECUTE; \
    832                                    region.priv_t = RW; \
    833                                    region.user_t = RW; \
    834                                    region.sh_t = NON_SHARED; \
    835                                    __get_page_descriptor(&descriptor_l1, &descriptor_l2, region);
    836    
    837 
    838 /*@}*/ /* end of group Renesas_RZ_A1_MemoryMap */
    839 
    840 /******************************************************************************/
    841 /*                         Clock Settings                                     */
    842 /******************************************************************************/
    843 /** @addtogroup Renesas_RZ_A1_H_Clocks Renesas_RZ_A1 Clock definitions
    844   @{
    845 */
    846 
    847 /*
    848  * Clock Mode 0 settings
    849  * SW1-4(MD_CLK):ON
    850  * SW1-5(MD_CLKS):ON
    851  * FRQCR=0x1035
    852  *   CLKEN2    = 0b - unstable
    853  *   CLKEN[1:0]=01b - Output, Low, Low
    854  *   IFC[1:0]  =00b - CPU clock is 1/1 PLL clock
    855  * FRQCR2=0x0001
    856  *   GFC[1:0]  =01b - Graphic clock is 2/3 bus clock
    857  */
    858 #define CM0_RENESAS_RZ_A1_CLKIN  ( 13333333u)
    859 #define CM0_RENESAS_RZ_A1_CLKO   ( 66666666u)
    860 #define CM0_RENESAS_RZ_A1_I_CLK  (400000000u)
    861 #define CM0_RENESAS_RZ_A1_G_CLK  (266666666u)
    862 #define CM0_RENESAS_RZ_A1_B_CLK  (133333333u)
    863 #define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u)
    864 #define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u)
    865 
    866 /*
    867  * Clock Mode 1 settings
    868  * SW1-4(MD_CLK):OFF
    869  * SW1-5(MD_CLKS):ON
    870  * FRQCR=0x1335
    871  *   CLKEN2    = 0b - unstable
    872  *   CLKEN[1:0]=01b - Output, Low, Low
    873  *   IFC[1:0]  =11b - CPU clock is 1/3 PLL clock
    874  * FRQCR2=0x0003
    875  *   GFC[1:0]  =11b - graphic clock is 1/3 bus clock
    876  */
    877 #define CM1_RENESAS_RZ_A1_CLKIN  ( 48000000u)
    878 #define CM1_RENESAS_RZ_A1_CLKO   ( 64000000u)
    879 #define CM1_RENESAS_RZ_A1_I_CLK  (128000000u)
    880 #define CM1_RENESAS_RZ_A1_G_CLK  (128000000u)
    881 #define CM1_RENESAS_RZ_A1_B_CLK  (128000000u)
    882 #define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u)
    883 #define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u)
    884 
    885 /*@}*/ /* end of group Renesas_RZ_A1_Clocks */
    886 
    887 /******************************************************************************/
    888 /*                         CPG   Settings                                     */
    889 /******************************************************************************/
    890 /** @addtogroup Renesas_RZ_A1_H_CPG Renesas_RZ_A1 CPG Bit definitions
    891   @{
    892 */
    893 
    894 #define CPG_FRQCR_SHIFT_CKOEN2  (14)
    895 #define CPG_FRQCR_BIT_CKOEN2    (0x1 << CPG_FRQCR_SHIFT_CKOEN2)
    896 #define CPG_FRQCR_SHIFT_CKOEN0  (12)
    897 #define CPG_FRQCR_BITS_CKOEN0   (0x3 << CPG_FRQCR_SHIFT_CKOEN0)
    898 #define CPG_FRQCR_SHIFT_IFC     (8)
    899 #define CPG_FRQCR_BITS_IFC      (0x3 << CPG_FRQCR_SHIFT_IFC)
    900 
    901 #define CPG_FRQCR2_SHIFT_GFC    (0)
    902 #define CPG_FRQCR2_BITS_GFC     (0x3 << CPG_FRQCR2_SHIFT_GFC)
    903 
    904 
    905 #define CPG_STBCR1_BIT_STBY     (0x80u)
    906 #define CPG_STBCR1_BIT_DEEP     (0x40u)
    907 #define CPG_STBCR2_BIT_HIZ      (0x80u)
    908 #define CPG_STBCR2_BIT_MSTP20   (0x01u) /* CoreSight */
    909 #define CPG_STBCR3_BIT_MSTP37   (0x80u) /* IEBus */
    910 #define CPG_STBCR3_BIT_MSTP36   (0x40u) /* IrDA */
    911 #define CPG_STBCR3_BIT_MSTP35   (0x20u) /* LIN0 */
    912 #define CPG_STBCR3_BIT_MSTP34   (0x10u) /* LIN1 */
    913 #define CPG_STBCR3_BIT_MSTP33   (0x08u) /* Multi-Function Timer */
    914 #define CPG_STBCR3_BIT_MSTP32   (0x04u) /* CAN */
    915 #define CPG_STBCR3_BIT_MSTP30   (0x01u) /* Motor Control PWM Timer */
    916 #define CPG_STBCR4_BIT_MSTP47   (0x80u) /* SCIF0 */
    917 #define CPG_STBCR4_BIT_MSTP46   (0x40u) /* SCIF1 */
    918 #define CPG_STBCR4_BIT_MSTP45   (0x20u) /* SCIF2 */
    919 #define CPG_STBCR4_BIT_MSTP44   (0x10u) /* SCIF3 */
    920 #define CPG_STBCR4_BIT_MSTP43   (0x08u) /* SCIF4 */
    921 #define CPG_STBCR4_BIT_MSTP42   (0x04u) /* SCIF5 */
    922 #define CPG_STBCR4_BIT_MSTP41   (0x02u) /* SCIF6 */
    923 #define CPG_STBCR4_BIT_MSTP40   (0x01u) /* SCIF7 */
    924 #define CPG_STBCR5_BIT_MSTP57   (0x80u) /* SCI0 */
    925 #define CPG_STBCR5_BIT_MSTP56   (0x40u) /* SCI1 */
    926 #define CPG_STBCR5_BIT_MSTP55   (0x20u) /* Sound Generator0 */
    927 #define CPG_STBCR5_BIT_MSTP54   (0x10u) /* Sound Generator1 */
    928 #define CPG_STBCR5_BIT_MSTP53   (0x08u) /* Sound Generator2 */
    929 #define CPG_STBCR5_BIT_MSTP52   (0x04u) /* Sound Generator3 */
    930 #define CPG_STBCR5_BIT_MSTP51   (0x02u) /* OSTM0 */
    931 #define CPG_STBCR5_BIT_MSTP50   (0x01u) /* OSTM1 */
    932 #define CPG_STBCR6_BIT_MSTP67   (0x80u) /* General A/D Comvertor */
    933 #define CPG_STBCR6_BIT_MSTP66   (0x40u) /* Capture Engine */
    934 #define CPG_STBCR6_BIT_MSTP65   (0x20u) /* Display out comparison0 */
    935 #define CPG_STBCR6_BIT_MSTP64   (0x10u) /* Display out comparison1 */   
    936 #define CPG_STBCR6_BIT_MSTP63   (0x08u) /* Dynamic Range Compalator0 */
    937 #define CPG_STBCR6_BIT_MSTP62   (0x04u) /* Dynamic Range Compalator1 */
    938 #define CPG_STBCR6_BIT_MSTP61   (0x02u) /* JPEG Decoder */
    939 #define CPG_STBCR6_BIT_MSTP60   (0x01u) /* Realtime Clock */
    940 #define CPG_STBCR7_BIT_MSTP77   (0x80u) /* Video Decoder0 */
    941 #define CPG_STBCR7_BIT_MSTP76   (0x40u) /* Video Decoder1 */
    942 #define CPG_STBCR7_BIT_MSTP74   (0x10u) /* Ether */
    943 #define CPG_STBCR7_BIT_MSTP73   (0x04u) /* NAND Flash Memory Controller */
    944 #define CPG_STBCR7_BIT_MSTP71   (0x02u) /* USB0 */
    945 #define CPG_STBCR7_BIT_MSTP70   (0x01u) /* USB1 */
    946 #define CPG_STBCR8_BIT_MSTP87   (0x80u) /* IMR-LS2_0 */
    947 #define CPG_STBCR8_BIT_MSTP86   (0x40u) /* IMR-LS2_1 */
    948 #define CPG_STBCR8_BIT_MSTP85   (0x20u) /* IMR-LSD */
    949 #define CPG_STBCR8_BIT_MSTP84   (0x10u) /* MMC Host Interface */
    950 #define CPG_STBCR8_BIT_MSTP83   (0x08u) /* MediaLB */
    951 #define CPG_STBCR8_BIT_MSTP81   (0x02u) /* SCUX */
    952 #define CPG_STBCR9_BIT_MSTP97   (0x80u) /* RIIC0 */
    953 #define CPG_STBCR9_BIT_MSTP96   (0x40u) /* RIIC1 */
    954 #define CPG_STBCR9_BIT_MSTP95   (0x20u) /* RIIC2 */
    955 #define CPG_STBCR9_BIT_MSTP94   (0x10u) /* RIIC3 */
    956 #define CPG_STBCR9_BIT_MSTP93   (0x08u) /* SPI Multi I/O Bus Controller0 */
    957 #define CPG_STBCR9_BIT_MSTP92   (0x04u) /* SPI Multi I/O Bus Controller1 */
    958 #define CPG_STBCR9_BIT_MSTP91   (0x02u) /* VDC5_0 */
    959 #define CPG_STBCR9_BIT_MSTP90   (0x01u) /* VDC5_1 */
    960 #define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */
    961 #define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */
    962 #define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */
    963 #define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */
    964 #define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */
    965 #define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */
    966 #define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */
    967 #define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */
    968 #define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */
    969 #define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */
    970 #define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */
    971 #define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */
    972 #define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */
    973 #define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */
    974 #define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */
    975 #define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */
    976 #define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */
    977 #define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */
    978 #define CPG_CSTBCR1_BIT_CMSTP11 (0x02u) /* PFV */
    979 #define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */
    980 #define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */
    981 #define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */
    982 #define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */
    983 #define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */
    984 #define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */
    985 #define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */
    986 #define CPG_SWRSTCR2_BIT_SRST27 (0x80u) /* Display out comparison0 */
    987 #define CPG_SWRSTCR2_BIT_SRST26 (0x40u) /* Display out comparison1 */
    988 #define CPG_SWRSTCR2_BIT_SRST25 (0x20u) /* Dynamic Range Compalator0 */
    989 #define CPG_SWRSTCR2_BIT_SRST24 (0x10u) /* Dynamic Range Compalator1 */
    990 #define CPG_SWRSTCR2_BIT_SRST23 (0x08u) /* VDC5_0 */
    991 #define CPG_SWRSTCR2_BIT_SRST22 (0x04u) /* VDC5_1 */
    992 #define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */
    993 #define CPG_SWRSTCR3_BIT_SRST36 (0x40u) /* DMA */
    994 #define CPG_SWRSTCR3_BIT_SRST35 (0x20u) /* IMR-LS2_0 */
    995 #define CPG_SWRSTCR3_BIT_SRST34 (0x10u) /* IMR-LS2_1 */
    996 #define CPG_SWRSTCR3_BIT_SRST33 (0x08u) /* IMR-LSD? */
    997 #define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */
    998 #define CPG_SWRSTCR3_BIT_SRST31 (0x02u) /* Capture Engine */
    999 #define CPG_SWRSTCR4_BIT_SRST41 (0x02u) /* Video Decoder0 */
    1000 #define CPG_SWRSTCR4_BIT_SRST40 (0x01u) /* Video Decoder1 */
    1001 #define CPG_SYSCR1_BIT_VRAME4   (0x10u) /* VRAM E Page4 */
    1002 #define CPG_SYSCR1_BIT_VRAME3   (0x08u) /* VRAM E Page3 */
    1003 #define CPG_SYSCR1_BIT_VRAME2   (0x04u) /* VRAM E Page2 */
    1004 #define CPG_SYSCR1_BIT_VRAME1   (0x02u) /* VRAM E Page1 */
    1005 #define CPG_SYSCR1_BIT_VRAME0   (0x01u) /* VRAM E Page0 */
    1006 #define CPG_SYSCR2_BIT_VRAMWE4  (0x10u) /* VRAM WE Page4 */
    1007 #define CPG_SYSCR2_BIT_VRAMWE3  (0x08u) /* VRAM WE Page3 */
    1008 #define CPG_SYSCR2_BIT_VRAMWE2  (0x04u) /* VRAM WE Page2 */
    1009 #define CPG_SYSCR2_BIT_VRAMWE1  (0x02u) /* VRAM WE Page1 */
    1010 #define CPG_SYSCR2_BIT_VRAMWE0  (0x01u) /* VRAM WE Page0 */
    1011 #define CPG_SYSCR3_BIT_RRAMWE3  (0x08u) /* RRAM WE Page3 */
    1012 #define CPG_SYSCR3_BIT_RRAMWE2  (0x04u) /* RRAM WE Page2 */
    1013 #define CPG_SYSCR3_BIT_RRAMWE1  (0x02u) /* RRAM WE Page1 */
    1014 #define CPG_SYSCR3_BIT_RRAMWE0  (0x01u) /* RRAM WE Page0 */
    1015 
    1016 /*@}*/ /* end of group Renesas_RZ_A1_CPG */
    1017 
    1018 /******************************************************************************/
    1019 /*                        GPIO   Settings                                     */
    1020 /******************************************************************************/
    1021 /** @addtogroup Renesas_RZ_A1_H_GPIO Renesas_RZ_A1 GPIO Bit definitions
    1022   @{
    1023 */
    1024 
    1025 #define GPIO_BIT_N0  (1u <<  0)
    1026 #define GPIO_BIT_N1  (1u <<  1)
    1027 #define GPIO_BIT_N2  (1u <<  2)
    1028 #define GPIO_BIT_N3  (1u <<  3)
    1029 #define GPIO_BIT_N4  (1u <<  4)
    1030 #define GPIO_BIT_N5  (1u <<  5)
    1031 #define GPIO_BIT_N6  (1u <<  6)
    1032 #define GPIO_BIT_N7  (1u <<  7)
    1033 #define GPIO_BIT_N8  (1u <<  8)
    1034 #define GPIO_BIT_N9  (1u <<  9)
    1035 #define GPIO_BIT_N10 (1u << 10)
    1036 #define GPIO_BIT_N11 (1u << 11)
    1037 #define GPIO_BIT_N12 (1u << 12)
    1038 #define GPIO_BIT_N13 (1u << 13)
    1039 #define GPIO_BIT_N14 (1u << 14)
    1040 #define GPIO_BIT_N15 (1u << 15)
    1041 
    1042 
    1043 #define MD_BOOT10_MASK    (0x3)
    1044 
    1045 #define MD_BOOT10_BM0     (0x0)
    1046 #define MD_BOOT10_BM1     (0x2)
    1047 #define MD_BOOT10_BM3     (0x1)
    1048 #define MD_BOOT10_BM4_5   (0x3)
    1049 
    1050 #define MD_CLK        (1u << 2)
    1051 #define MD_CLKS       (1u << 3)
    1052 
    1053 /*@}*/ /* end of group Renesas_RZ_A1_GPIO */
    1054 
    1055 #ifdef __cplusplus
    1056 }
    1057 #endif
    1058 
    1059 #endif  // __MBRZA1H_H__
     1#include "RZ_A1H.h"

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/RZA1H.ld

    r352 r374  
    44PROVIDE(software_term_hook = 0);
    55PROVIDE(IRQTable = _kernel_inh_table);
    6 PROVIDE(IRQNestLevel = _kernel_excpt_nest_count);
     6PROVIDE(IRQ_NestLevel = _kernel_excpt_nest_count);
    77
    88/* Linker script to configure memory regions. */
    … …  
    5757        Image$$VECTORS$$Base = .;
    5858        * (RESET)
    59         . += 0x00000400;
    6059
    6160        KEEP(*(.isr_vector))
    … …  
    111110        LONG (__nc_data_start)
    112111        LONG (__nc_data_end - __nc_data_start)
     112        LONG (LOADADDR(.ram_code))
     113        LONG (ADDR(.ram_code))
     114        LONG (SIZEOF(.ram_code))
    113115        __copy_table_end__ = .;
    114116    } > SFLASH
    … …  
    125127    } > SFLASH
    126128
    127     __etext = .;
    128        
     129    .ram_code : ALIGN( 0x4 ) {
     130        __ram_code_load  = .;
     131        __ram_code_start = LOADADDR(.ram_code) + ( __ram_code_load - ADDR(.ram_code) );
     132
     133        *(RAM_CODE)
     134
     135        *(RAM_CONST)
     136
     137        . = ALIGN( 0x4 );
     138        __ram_code_end = LOADADDR(.ram_code) + ( . - ADDR(.ram_code) );
     139    } > RAM AT > SFLASH
     140
     141    Load$$SEC_RAM_CODE$$Base    = LOADADDR(.ram_code);
     142    Image$$SEC_RAM_CODE$$Base   = ADDR(.ram_code);
     143    Load$$SEC_RAM_CODE$$Length  = SIZEOF(.ram_code);
     144
    129145    .ttb :
    130146    {
    … …  
    133149        Image$$TTB$$ZI$$Limit = .;
    134150    } > L_TTB
     151
     152    __etext = Load$$SEC_RAM_CODE$$Base + SIZEOF(.ram_code);
    135153
    136154    .data : AT (__etext)
    … …  
    154172        KEEP(*(.init_array))
    155173        PROVIDE (__init_array_end = .);
     174
    156175
    157176        . = ALIGN(4);

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_RZ1AH.S

    r352 r374  
    2020 
    2121@ Standard definitions of mode bits and interrupt (I & F) flags in PSRs
    22     .equ    USR_MODE        ,   0x10
    23     .equ    FIQ_MODE        ,   0x11
    24     .equ    IRQ_MODE        ,   0x12
    25     .equ    SVC_MODE        ,   0x13
    26     .equ    ABT_MODE        ,   0x17
    27     .equ    UND_MODE        ,   0x1b
    28     .equ    SYS_MODE        ,   0x1f
    29     .equ    Thum_bit        ,   0x20            @ CPSR/SPSR Thumb bit
    30 
    31     .equ    GICI_BASE       ,   0xe8202000
    32     .equ    ICCIAR_OFFSET   ,   0x0000000C
    33     .equ    ICCEOIR_OFFSET  ,   0x00000010
    34     .equ    ICCHPIR_OFFSET  ,   0x00000018
    35     .equ    GICD_BASE       ,   0xe8201000
    36     .equ    ICDISER0_OFFSET ,   0x00000100
    37     .equ    ICDICER0_OFFSET ,   0x00000180
    38     .equ    ICDISPR0_OFFSET ,   0x00000200
    39     .equ    ICDABR0_OFFSET  ,   0x00000300
    40     .equ    ICDIPR0_OFFSET  ,   0x00000400
    41 
    4222    .equ    Mode_USR        ,   0x10
    4323    .equ    Mode_FIQ        ,   0x11
    … …  
    5131    .equ    F_Bit           ,   0x40            @ when F bit is set, FIQ is disabled
    5232    .equ    T_Bit           ,   0x20            @ when T bit is set, core is in Thumb state
    53 
    54     .equ    GIC_ERRATA_CHECK_1, 0x000003FE
    55     .equ    GIC_ERRATA_CHECK_2, 0x000003FF
    56 
    57     .equ    Sect_Normal     , 0x00005c06        @ outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
    58     .equ    Sect_Normal_Cod , 0x0000dc06        @ outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
    59     .equ    Sect_Normal_RO  , 0x0000dc16        @ as Sect_Normal_Cod, but not executable
    60     .equ    Sect_Normal_RW  , 0x00005c16        @ as Sect_Normal_Cod, but writeable and not executable
    61     .equ    Sect_SO         , 0x00000c12        @ strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
    62     .equ    Sect_Device_RO  , 0x00008c12        @ device, non-shareable, non-executable, ro, domain 0, base addr 0
    63     .equ    Sect_Device_RW  , 0x00000c12        @ as Sect_Device_RO, but writeable
    64     .equ    Sect_Fault      , 0x00000000        @ this translation will fault (the bottom 2 bits are important, the rest are ignored)
    65 
    66     .equ    RAM_BASE        , 0x80000000
    67     .equ    VRAM_BASE       , 0x18000000
    68     .equ    SRAM_BASE       , 0x2e000000
    69     .equ    ETHERNET        , 0x1a000000
    70     .equ    CS3_PERIPHERAL_BASE, 0x1c000000
    71 
    7233
    7334@ Stack Configuration
    … …  
    9758@ Heap Configuration
    9859
    99     .EQU    Heap_Size       , 0x00020000
     60    .EQU    Heap_Size       , 0x00080000
    10061
    10162    .section .heap
    … …  
    140101    .type          Reset_Handler, %function
    141102Reset_Handler:
     103    @ Mask interrupts
     104    CPSID   if                           
     105
    142106    @ Put any cores other than 0 to sleep
    143107    mrc     p15, 0, r0, c0, c0, 5   @ Read MPIDR
    144108    ands    r0, r0, #3
    145 
    146109goToSleep:
    147110    wfine
    148111    bne     goToSleep
    149112
    150 @ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11.
    151 @ Enables Full Access i.e. in both privileged and non privileged modes
    152     mrc     p15, 0, r0, c1, c0, 2       @ Read Coprocessor Access Control Register (CPACR)
    153     orr     r0, r0, #(0xF << 20)        @ Enable access to CP 10 & 11
    154     mcr     p15, 0, r0, c1, c0, 2       @ Write Coprocessor Access Control Register (CPACR)
    155     isb
    156 
    157 @ Switch on the VFP and NEON hardware
    158     mov     r0, #0x40000000
    159     vmsr    fpexc, r0                   @ Write FPEXC register, EN bit set
    160 
     113    @ Reset SCTLR Settings
    161114    mrc     p15, 0, r0, c1, c0, 0       @ Read CP15 System Control register
    162115    bic     r0, r0, #(0x1 << 12)        @ Clear I bit 12 to disable I Cache
    … …  
    168121    isb
    169122
     123    @ Configure ACTLR
     124    MRC     p15, 0, r0, c1, c0, 1       @ Read CP15 Auxiliary Control Register
     125    ORR     r0, r0, #(1 <<  1)          @ Enable L2 prefetch hint (UNK/WI since r4p1)
     126    MCR     p15, 0, r0, c1, c0, 1       @ Write CP15 Auxiliary Control Register
     127
    170128@ Set Vector Base Address Register (VBAR) to point to this application's vector table
    171129    ldr     r0, =__isr_vector
    … …  
    205163    mov     sp, r0
    206164
    207     isb
    208     ldr     r0, =RZ_A1_SetSramWriteEnable
    209     blx     r0
    210 
    211     .extern  create_translation_table
    212     bl      create_translation_table
    213 
    214165@  USR/SYS stack pointer will be set during kernel init
    215166    ldr     r0, =SystemInit
    216167    blx     r0
    217     ldr     r0, =InitMemorySubsystem
    218     blx     r0
    219 
    220 @ fp_init
    221     mov      r0, #0x3000000
    222     vmsr     fpscr, r0
    223 
     168
     169    @ Unmask interrupts
     170    CPSIE  if
    224171
    225172@ data sections copy
    … …  
    283230
    284231    .text
    285 
    286 Undef_Handler:
    287                 .global Undef_Handler
    288                 .func   Undef_Handler
    289                 .extern CUndefHandler
    290                 SRSDB   SP!, #Mode_UND
    291                 PUSH    {R0-R4, R12}              /* Save APCS corruptible registers to UND mode stack */
    292 
    293                 MRS     R0, SPSR
    294                 TST     R0, #T_Bit                /* Check mode */
    295                 MOVEQ   R1, #4                    /* R1 = 4 ARM mode */
    296                 MOVNE   R1, #2                    /* R1 = 2 Thumb mode */
    297                 SUB     R0, LR, R1
    298                 LDREQ   R0, [R0]                  /* ARM mode - R0 points to offending instruction */
    299                 BEQ     undef_cont
    300 
    301                 /* Thumb instruction */
    302                 /* Determine if it is a 32-bit Thumb instruction */
    303                 LDRH    R0, [R0]
    304                 MOV     R2, #0x1c
    305                 CMP     R2, R0, LSR #11
    306                 BHS     undef_cont                /* 16-bit Thumb instruction */
    307 
    308                 /* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */
    309                 LDRH    R2, [LR]
    310                 ORR     R0, R2, R0, LSL #16
    311 undef_cont:
    312                 MOV     R2, LR                    /* Set LR to third argument */
    313                
    314 /*              AND     R12, SP, #4 */            /* Ensure stack is 8-byte aligned */
    315                 MOV     R3, SP                    /* Ensure stack is 8-byte aligned */
    316                 AND     R12, R3, #4
    317                 SUB     SP, SP, R12               /* Adjust stack */
    318                 PUSH    {R12, LR}                 /* Store stack adjustment and dummy LR */
    319 
    320                 /* R0 Offending instruction */
    321                 /* R1 =2 (Thumb) or =4 (ARM) */
    322                 BL      CUndefHandler
    323 
    324                 POP     {R12, LR}                 /* Get stack adjustment & discard dummy LR */
    325                 ADD     SP, SP, R12               /* Unadjust stack */
    326 
    327                 LDR     LR, [SP, #24]             /* Restore stacked LR and possibly adjust for retry */
    328                 SUB     LR, LR, R0
    329                 LDR     R0, [SP, #28]             /* Restore stacked SPSR */
    330                 MSR     SPSR_cxsf, R0
    331                 POP     {R0-R4, R12}              /* Restore stacked APCS registers */
    332                 ADD     SP, SP, #8                /* Adjust SP for already-restored banked registers */
    333                 MOVS    PC, LR
    334                 .endfunc
    335  
    336 PAbt_Handler:
    337                 .global PAbt_Handler
    338                 .func   PAbt_Handler
    339                 .extern CPAbtHandler
    340                 SUB     LR, LR, #4                /* Pre-adjust LR */
    341                 SRSDB   SP!, #Mode_ABT            /* Save LR and SPRS to ABT mode stack */
    342                 PUSH    {R0-R4, R12}              /* Save APCS corruptible registers to ABT mode stack */
    343                 MRC     p15, 0, R0, c5, c0, 1     /* IFSR */
    344                 MRC     p15, 0, R1, c6, c0, 2     /* IFAR */
    345 
    346                 MOV     R2, LR                    /* Set LR to third argument */
    347 
    348 /*              AND     R12, SP, #4 */            /* Ensure stack is 8-byte aligned */
    349                 MOV     R3, SP                    /* Ensure stack is 8-byte aligned */
    350                 AND     R12, R3, #4
    351                 SUB     SP, SP, R12               /* Adjust stack */
    352                 PUSH    {R12, LR}                 /* Store stack adjustment and dummy LR */
    353 
    354                 BL      CPAbtHandler
    355 
    356                 POP     {R12, LR}                 /* Get stack adjustment & discard dummy LR */
    357                 ADD     SP, SP, R12               /* Unadjust stack */
    358 
    359                 POP     {R0-R4, R12}              /* Restore stack APCS registers */
    360                 RFEFD   SP!                       /* Return from exception */
    361                 .endfunc
    362 
    363 DAbt_Handler:
    364                 .global DAbt_Handler
    365                 .func   DAbt_Handler
    366                 .extern CDAbtHandler
    367                 SUB     LR, LR, #8                /* Pre-adjust LR */
    368                 SRSDB   SP!, #Mode_ABT            /* Save LR and SPRS to ABT mode stack */
    369                 PUSH    {R0-R4, R12}              /* Save APCS corruptible registers to ABT mode stack */
    370                 CLREX                             /* State of exclusive monitors unknown after taken data abort */
    371                 MRC     p15, 0, R0, c5, c0, 0     /* DFSR */
    372                 MRC     p15, 0, R1, c6, c0, 0     /* DFAR */
    373 
    374                 MOV     R2, LR                    /* Set LR to third argument */
    375 
    376 /*              AND     R12, SP, #4 */            /* Ensure stack is 8-byte aligned */
    377                 MOV     R3, SP                    /* Ensure stack is 8-byte aligned */
    378                 AND     R12, R3, #4
    379                 SUB     SP, SP, R12               /* Adjust stack */
    380                 PUSH    {R12, LR}                 /* Store stack adjustment and dummy LR */
    381 
    382                 BL      CDAbtHandler
    383 
    384                 POP     {R12, LR}                 /* Get stack adjustment & discard dummy LR */
    385                 ADD     SP, SP, R12               /* Unadjust stack */
    386 
    387                 POP     {R0-R4, R12}              /* Restore stacked APCS registers */
    388                 RFEFD   SP!                       /* Return from exception */
    389                 .endfunc
    390  
    391 FIQ_Handler:
    392                 .global FIQ_Handler
    393                 .func   FIQ_Handler
    394                 /* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler,
    395                  * so if a real FIQ Handler is implemented, this will be needed before returning:
    396                  */
    397                 /* LDR     R1, =GICI_BASE
    398                    LDR     R0, [R1, #ICCHPIR_OFFSET]   ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
    399                  */
    400                 B       .
    401                 .endfunc
    402  
    403                 .extern SVC_Handler                 /* refer RTX function */
    404 
    405 IRQ_Handler:
    406                 .global IRQ_Handler
    407                 .func   IRQ_Handler
    408                 .extern IRQCount
    409                 .extern IRQTable
    410                 .extern IRQNestLevel
    411 
    412                 /* prologue */
    413                 SUB     LR, LR, #4                  /* Pre-adjust LR */
    414                 SRSDB   SP!, #Mode_IRQ              /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */
    415                 CPS     #Mode_IRQ                   /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */
    416                 PUSH    {R0-R3, R12}                /* Save remaining APCS corruptible registers to SVC stack */
    417 
    418 /*              AND     R1, SP, #4 */               /* Ensure stack is 8-byte aligned */
    419                 MOV     R3, SP                      /* Ensure stack is 8-byte aligned */
    420                 AND     R1, R3, #4
    421                 SUB     SP, SP, R1                  /* Adjust stack */
    422                 PUSH    {R1, LR}                    /* Store stack adjustment and LR_SVC to SVC stack */
    423 
    424                 LDR     R0, =IRQNestLevel           /* Get address of nesting counter */
    425                 LDR     R1, [R0]
    426                 ADD     R1, R1, #1                  /* Increment nesting counter */
    427                 STR     R1, [R0]
    428 
    429                 /* identify and acknowledge interrupt */
    430                 LDR     R1, =GICI_BASE
    431                 LDR     R0, [R1, #ICCHPIR_OFFSET]   /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */
    432                 LDR     R0, [R1, #ICCIAR_OFFSET]    /* Read ICCIAR (GIC CPU Interface register) */
    433                 DSB                                 /* Ensure that interrupt acknowledge completes before re-enabling interrupts */
    434 
    435                 /* Workaround GIC 390 errata 733075
    436                  * If the ID is not 0, then service the interrupt as normal.
    437                  * If the ID is 0 and active, then service interrupt ID 0 as normal.
    438                  * If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it
    439                  *   with a dummy write to ICDIPR0.  This interrupt should be treated as spurious and not serviced.
    440                  */
    441                 LDR     R2, =GICD_BASE
    442                 LDR     R3, =GIC_ERRATA_CHECK_1
    443                 CMP     R0, R3
    444                 BEQ     unlock_cpu
    445                 LDR     R3, =GIC_ERRATA_CHECK_2
    446                 CMP     R0, R3
    447                 BEQ     unlock_cpu
    448                 CMP     R0, #0
    449                 BNE     int_active                  /* If the ID is not 0, then service the interrupt */
    450                 LDR     R3, [R2, #ICDABR0_OFFSET]   /* Get the interrupt state */
    451                 TST     R3, #1
    452                 BNE     int_active                  /* If active, then service the interrupt */
    453 unlock_cpu:
    454                 LDR     R3, [R2, #ICDIPR0_OFFSET]   /* Not active, so unlock the CPU interface */
    455                 STR     R3, [R2, #ICDIPR0_OFFSET]   /*   with a dummy write */
    456                 DSB                                 /* Ensure the write completes before continuing */
    457                 B       ret_irq                     /* Do not service the spurious interrupt */
    458                 /* End workaround */
    459 
    460 int_active:
    461                 LDR     R2, =IRQCount               /* Read number of IRQs */
    462                 LDR     R2, [R2]
    463                 CMP     R0, R2                      /* Clean up and return if no handler */
    464                 BHS     ret_irq                     /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */
    465                 LDR     R2, =IRQTable               /* Get address of handler */
    466                 LDR     R2, [R2, R0, LSL #2]
    467                 CMP     R2, #0                      /* Clean up and return if handler address is 0 */
    468                 BEQ     ret_irq
    469                 PUSH    {R0,R1}
    470 
    471                 CPSIE   i                           /* Now safe to re-enable interrupts */
    472                 BLX     R2                          /* Call handler. R0 will be IRQ number */
    473                 CPSID   i                           /* Disable interrupts again */
    474 
    475                 /* write EOIR (GIC CPU Interface register) */
    476                 POP     {R0,R1}
    477                 DSB                                 /* Ensure that interrupt source is cleared before we write the EOIR */
    478 ret_irq:
    479                 /* epilogue */
    480                 STR     R0, [R1, #ICCEOIR_OFFSET]
    481 
    482                 LDR     R0, =IRQNestLevel           /* Get address of nesting counter */
    483                 LDR     R1, [R0]
    484                 SUB     R1, R1, #1                  /* Decrement nesting counter */
    485                 STR     R1, [R0]
    486 
    487                 POP     {R1, LR}                    /* Get stack adjustment and restore LR_SVC */
    488                 ADD     SP, SP, R1                  /* Unadjust stack */
    489 
    490                 POP     {R0-R3,R12}                 /* Restore stacked APCS registers */
    491                 RFEFD   SP!                         /* Return from exception */
    492                 .endfunc
    493232
    494233/*    Macro to define default handlers. Default handler
    … …  
    505244                .endm
    506245
     246                def_default_handler    Undef_Handler
    507247                def_default_handler    SVC_Handler
    508 
    509 
    510 /* User Initial Stack & Heap */
    511 
    512                 .ifdef __MICROLIB
    513                
    514                 .global __initial_sp
    515                 .global __heap_base
    516                 .global __heap_limit
    517 
    518                 .else
    519 
    520                 .extern __use_two_region_memory
    521                 .global __user_initial_stackheap
    522 __user_initial_stackheap:
    523 
    524                 LDR     R0, =  __HeapBase
    525                 LDR     R1, =(__StackTop)
    526                 LDR     R2, = (__HeapBase +  Heap_Size)
    527                 LDR     R3, = (__StackTop - USR_Stack_Size)
    528                 BX      LR
    529 
    530                 .endif
    531 
     248                def_default_handler    PAbt_Handler
     249                def_default_handler    DAbt_Handler
     250                def_default_handler    IRQ_Handler
     251                def_default_handler    FIQ_Handler
    532252
    533253                .END

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/cmsis.h

    r352 r374  
    99
    1010#include "MBRZA1H.h"
     11#include "cmsis_nvic.h"
    1112
    1213#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    29 #ifndef R7S72100_IODEFINE_H
    30 #define R7S72100_IODEFINE_H
    31 #define IODEFINE_H_VERSION  100
     29#ifndef R7S721000_IODEFINE_H
     30#define R7S721000_IODEFINE_H
    3231
    3332#define H H_BYTE
    3433
    35 enum iodefine_byte_select_t
    36 {
    37     L = 0, H = 1,
    38     LL= 0, LH = 1, HL = 2, HH = 3
    39 };
     34#include "iodefines/iodefine_typedef.h"                         /* (V2.00h) */
    4035
    41 /***********************************************************************
    42   <<< [iodefine_reg32_t] >>>
    43 - Padding : sizeof(iodefine_reg32_t) == 4
    44 - Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
    45 -                     &UINT8[0]==0, &UINT8[1]==1, &UINT8[2]==2, &UINT8[3]==3
    46 - Endian : Independent (Same as CPU endian as register endian)
    47 - Bit-Order : Independent
    48 ************************************************************************/
    49 /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    50 /* ->SEC M1.10.1 : Not magic number */
    51 union iodefine_reg32_t
    52 {
    53     volatile uint32_t  UINT32;                                  /*  32-bit Access   */
    54     volatile uint16_t  UINT16[2];                               /*  16-bit Access   */
    55     volatile uint8_t   UINT8[4];                                /*  8-bit Access    */
    56 };
    57 /* <-SEC M1.10.1 */
    58 /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
    59 
    60 /***********************************************************************
    61   <<< [iodefine_reg32_16_t] >>>
    62 - Padding : sizeof(iodefine_reg32_16_t) == 4
    63 - Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
    64 - Endian : Independent (Same as CPU endian as register endian)
    65 - Bit-Order : Independent
    66 ************************************************************************/
    67 /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    68 /* ->SEC M1.10.1 : Not magic number */
    69 union iodefine_reg32_16_t
    70 {
    71     volatile uint32_t  UINT32;                                  /*  32-bit Access   */
    72     volatile uint16_t  UINT16[2];                               /*  16-bit Access   */
    73 };
    74 /* <-SEC M1.10.1 */
    75 /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
    76 
    77 /***********************************************************************
    78   <<< [iodefine_reg16_8_t] >>>
    79 - Padding : sizeof(iodefine_reg16_8_t) == 2
    80 - Alignment(Offset) : &UINT16==0, &UINT8[0]==0, &UINT8[1]==1
    81 - Endian : Independent (Same as CPU endian as register endian)
    82 - Bit-Order : Independent
    83 ************************************************************************/
    84 /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    85 /* ->SEC M1.10.1 : Not magic number */
    86 union iodefine_reg16_8_t
    87 {
    88     volatile uint16_t  UINT16;                                  /*  16-bit Access   */
    89     volatile uint8_t   UINT8[2];                                /*  8-bit Access    */
    90 };
    91 /* <-SEC M1.10.1 */
    92 /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
    93 
    94 
    95 
    96 
    97 
    98 
    99 #include "adc_iodefine.h"                             /* (V1.00a) */
    100 #include "bsc_iodefine.h"                             /* (V1.00a) */
    101 #include "ceu_iodefine.h"                             /* (V1.00a) */
    102 #include "cpg_iodefine.h"                             /* (V1.00a) */
    103 #include "disc_iodefine.h"                            /* (V1.00a) */
    104 #include "dmac_iodefine.h"                            /* (V1.00a) */
    105 #include "dvdec_iodefine.h"                           /* (V1.00a) */
    106 #include "ether_iodefine.h"                           /* (V1.00a) */
    107 #include "flctl_iodefine.h"                           /* (V1.00a) */
    108 #include "gpio_iodefine.h"                            /* (V1.00a) */
    109 #include "ieb_iodefine.h"                             /* (V1.00a) */
    110 #include "inb_iodefine.h"                             /* (V1.00a) */
    111 #include "intc_iodefine.h"                            /* (V1.00a) */
    112 #include "irda_iodefine.h"                            /* (V1.00a) */
    113 #include "jcu_iodefine.h"                             /* (V1.00a) */
    114 #include "l2c_iodefine.h"                             /* (V1.00a) */
    115 #include "lin_iodefine.h"                             /* (V1.00a) */
    116 #include "lvds_iodefine.h"                            /* (V1.00a) */
    117 #include "mlb_iodefine.h"                             /* (V1.00a) */
    118 #include "mmc_iodefine.h"                             /* (V1.00a) */
    119 #include "mtu2_iodefine.h"                            /* (V1.00a) */
    120 #include "ostm_iodefine.h"                            /* (V1.00a) */
    121 #include "pfv_iodefine.h"                             /* (V1.00a) */
    122 #include "pwm_iodefine.h"                             /* (V1.00a) */
    123 #include "riic_iodefine.h"                            /* (V1.00a) */
    124 #include "romdec_iodefine.h"                          /* (V1.00a) */
    125 #include "rscan0_iodefine.h"                          /* (V1.00a) */
    126 #include "rspi_iodefine.h"                            /* (V1.00a) */
    127 #include "rtc_iodefine.h"                             /* (V1.00a) */
    128 #include "scif_iodefine.h"                            /* (V1.00a) */
    129 #include "scim_iodefine.h"                            /* (V1.00a) */
    130 #include "scux_iodefine.h"                            /* (V1.00a) */
    131 #include "sdg_iodefine.h"                             /* (V1.00a) */
    132 #include "spdif_iodefine.h"                           /* (V1.00a) */
    133 #include "spibsc_iodefine.h"                          /* (V1.00a) */
    134 #include "ssif_iodefine.h"                            /* (V1.00a) */
    135 #include "usb20_iodefine.h"                           /* (V1.00a) */
    136 #include "vdc5_iodefine.h"                            /* (V1.00a) */
    137 #include "wdt_iodefine.h"                             /* (V1.00a) */
     36#include "iodefines/adc_iodefine.h"                             /* (V2.00h) */
     37#include "iodefines/bsc_iodefine.h"                             /* (V2.00h) */
     38#include "iodefines/ceu_iodefine.h"                             /* (V2.00h) */
     39#include "iodefines/cpg_iodefine.h"                             /* (V2.00h) */
     40#include "iodefines/disc_iodefine.h"                            /* (V2.00h) */
     41#include "iodefines/dmac_iodefine.h"                            /* (V2.00h) */
     42#include "iodefines/dvdec_iodefine.h"                           /* (V2.00h) */
     43#include "iodefines/ether_iodefine.h"                           /* (V2.00h) */
     44#include "iodefines/flctl_iodefine.h"                           /* (V2.00h) */
     45#include "iodefines/gpio_iodefine.h"                            /* (V2.00h) */
     46#include "iodefines/ieb_iodefine.h"                             /* (V2.00h) */
     47#include "iodefines/inb_iodefine.h"                             /* (V2.00h) */
     48#include "iodefines/intc_iodefine.h"                            /* (V2.00h) */
     49#include "iodefines/irda_iodefine.h"                            /* (V2.00h) */
     50#include "iodefines/jcu_iodefine.h"                             /* (V2.00h) */
     51#include "iodefines/l2c_iodefine.h"                             /* (V2.00h) */
     52#include "iodefines/lin_iodefine.h"                             /* (V2.00h) */
     53#include "iodefines/lvds_iodefine.h"                            /* (V2.00h) */
     54#include "iodefines/mlb_iodefine.h"                             /* (V2.00h) */
     55#include "iodefines/mmc_iodefine.h"                             /* (V2.00h) */
     56#include "iodefines/mtu2_iodefine.h"                            /* (V2.00h) */
     57#include "iodefines/ostm_iodefine.h"                            /* (V2.00h) */
     58#include "iodefines/pfv_iodefine.h"                             /* (V2.00h) */
     59#include "iodefines/pwm_iodefine.h"                             /* (V2.00h) */
     60#include "iodefines/riic_iodefine.h"                            /* (V2.00h) */
     61#include "iodefines/romdec_iodefine.h"                          /* (V2.00h) */
     62#include "iodefines/rscan0_iodefine.h"                          /* (V2.00h) */
     63#include "iodefines/rspi_iodefine.h"                            /* (V2.00h) */
     64#include "iodefines/rtc_iodefine.h"                             /* (V2.00h) */
     65#include "iodefines/scif_iodefine.h"                            /* (V2.00h) */
     66#include "iodefines/scim_iodefine.h"                            /* (V2.00h) */
     67#include "iodefines/scux_iodefine.h"                            /* (V2.00h) */
     68#include "iodefines/sdg_iodefine.h"                             /* (V2.00h) */
     69#include "iodefines/spdif_iodefine.h"                           /* (V2.00h) */
     70#include "iodefines/spibsc_iodefine.h"                          /* (V2.00h) */
     71#include "iodefines/ssif_iodefine.h"                            /* (V2.00h) */
     72#include "iodefines/usb20_iodefine.h"                           /* (V2.00h) */
     73#include "iodefines/vdc5_iodefine.h"                            /* (V2.00h) */
     74#include "iodefines/wdt_iodefine.h"                             /* (V2.00h) */
    13875
    13976#undef H

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/adc_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef ADC_IODEFINE_H
    3030#define ADC_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3134/* ->SEC M1.10.1 : Not magic number */
    3235
    33 struct st_adc
    34 {                                                          /* ADC              */
     36#define ADC     (*(struct st_adc     *)0xE8005800uL) /* ADC */
     37
     38
     39#define ADCADDRA (ADC.ADDRA)
     40#define ADCADDRB (ADC.ADDRB)
     41#define ADCADDRC (ADC.ADDRC)
     42#define ADCADDRD (ADC.ADDRD)
     43#define ADCADDRE (ADC.ADDRE)
     44#define ADCADDRF (ADC.ADDRF)
     45#define ADCADDRG (ADC.ADDRG)
     46#define ADCADDRH (ADC.ADDRH)
     47#define ADCADCMPHA (ADC.ADCMPHA)
     48#define ADCADCMPLA (ADC.ADCMPLA)
     49#define ADCADCMPHB (ADC.ADCMPHB)
     50#define ADCADCMPLB (ADC.ADCMPLB)
     51#define ADCADCMPHC (ADC.ADCMPHC)
     52#define ADCADCMPLC (ADC.ADCMPLC)
     53#define ADCADCMPHD (ADC.ADCMPHD)
     54#define ADCADCMPLD (ADC.ADCMPLD)
     55#define ADCADCMPHE (ADC.ADCMPHE)
     56#define ADCADCMPLE (ADC.ADCMPLE)
     57#define ADCADCMPHF (ADC.ADCMPHF)
     58#define ADCADCMPLF (ADC.ADCMPLF)
     59#define ADCADCMPHG (ADC.ADCMPHG)
     60#define ADCADCMPLG (ADC.ADCMPLG)
     61#define ADCADCMPHH (ADC.ADCMPHH)
     62#define ADCADCMPLH (ADC.ADCMPLH)
     63#define ADCADCSR (ADC.ADCSR)
     64#define ADCADCMPER (ADC.ADCMPER)
     65#define ADCADCMPSR (ADC.ADCMPSR)
     66
     67
     68typedef struct st_adc
     69{
     70                                                           /* ADC              */
    3571    volatile uint16_t ADDRA;                                  /*  ADDRA           */
    3672    volatile uint16_t ADDRB;                                  /*  ADDRB           */
    … …  
    6298    volatile uint16_t ADCMPER;                                /*  ADCMPER         */
    6399    volatile uint16_t ADCMPSR;                                /*  ADCMPSR         */
    64 };
     100} r_io_adc_t;
    65101
    66102
    67 #define ADC     (*(struct st_adc     *)0xE8005800uL) /* ADC */
    68 
    69 
    70 #define ADCADDRA ADC.ADDRA
    71 #define ADCADDRB ADC.ADDRB
    72 #define ADCADDRC ADC.ADDRC
    73 #define ADCADDRD ADC.ADDRD
    74 #define ADCADDRE ADC.ADDRE
    75 #define ADCADDRF ADC.ADDRF
    76 #define ADCADDRG ADC.ADDRG
    77 #define ADCADDRH ADC.ADDRH
    78 #define ADCADCMPHA ADC.ADCMPHA
    79 #define ADCADCMPLA ADC.ADCMPLA
    80 #define ADCADCMPHB ADC.ADCMPHB
    81 #define ADCADCMPLB ADC.ADCMPLB
    82 #define ADCADCMPHC ADC.ADCMPHC
    83 #define ADCADCMPLC ADC.ADCMPLC
    84 #define ADCADCMPHD ADC.ADCMPHD
    85 #define ADCADCMPLD ADC.ADCMPLD
    86 #define ADCADCMPHE ADC.ADCMPHE
    87 #define ADCADCMPLE ADC.ADCMPLE
    88 #define ADCADCMPHF ADC.ADCMPHF
    89 #define ADCADCMPLF ADC.ADCMPLF
    90 #define ADCADCMPHG ADC.ADCMPHG
    91 #define ADCADCMPLG ADC.ADCMPLG
    92 #define ADCADCMPHH ADC.ADCMPHH
    93 #define ADCADCMPLH ADC.ADCMPLH
    94 #define ADCADCSR ADC.ADCSR
    95 #define ADCADCMPER ADC.ADCMPER
    96 #define ADCADCMPSR ADC.ADCMPSR
    97103/* <-SEC M1.10.1 */
     104/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     105/* <-QAC 0857 */
     106/* <-QAC 0639 */
    98107#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/bsc_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef BSC_IODEFINE_H
    3030#define BSC_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3134/* ->SEC M1.10.1 : Not magic number */
    3235
    33 struct st_bsc
    34 {                                                          /* BSC              */
     36#define BSC     (*(struct st_bsc     *)0x3FFFC000uL) /* BSC */
     37
     38
     39#define BSCCMNCR (BSC.CMNCR)
     40#define BSCCS0BCR (BSC.CS0BCR)
     41#define BSCCS1BCR (BSC.CS1BCR)
     42#define BSCCS2BCR (BSC.CS2BCR)
     43#define BSCCS3BCR (BSC.CS3BCR)
     44#define BSCCS4BCR (BSC.CS4BCR)
     45#define BSCCS5BCR (BSC.CS5BCR)
     46#define BSCCS0WCR (BSC.CS0WCR)
     47#define BSCCS1WCR (BSC.CS1WCR)
     48#define BSCCS2WCR (BSC.CS2WCR)
     49#define BSCCS3WCR (BSC.CS3WCR)
     50#define BSCCS4WCR (BSC.CS4WCR)
     51#define BSCCS5WCR (BSC.CS5WCR)
     52#define BSCSDCR (BSC.SDCR)
     53#define BSCRTCSR (BSC.RTCSR)
     54#define BSCRTCNT (BSC.RTCNT)
     55#define BSCRTCOR (BSC.RTCOR)
     56#define BSCTOSCOR0 (BSC.TOSCOR0)
     57#define BSCTOSCOR1 (BSC.TOSCOR1)
     58#define BSCTOSCOR2 (BSC.TOSCOR2)
     59#define BSCTOSCOR3 (BSC.TOSCOR3)
     60#define BSCTOSCOR4 (BSC.TOSCOR4)
     61#define BSCTOSCOR5 (BSC.TOSCOR5)
     62#define BSCTOSTR (BSC.TOSTR)
     63#define BSCTOENR (BSC.TOENR)
     64
     65#define BSC_CSnBCR_COUNT (6)
     66#define BSC_CSnWCR_COUNT (6)
     67#define BSC_TOSCORn_COUNT (6)
     68
     69
     70typedef struct st_bsc
     71{
     72                                                           /* BSC              */
    3573    volatile uint32_t  CMNCR;                                  /*  CMNCR           */
    36 #define BSC_CSnBCR_COUNT 6
     74
     75/* #define BSC_CSnBCR_COUNT (6) */
    3776    volatile uint32_t  CS0BCR;                                 /*  CS0BCR          */
    3877    volatile uint32_t  CS1BCR;                                 /*  CS1BCR          */
    … …  
    4281    volatile uint32_t  CS5BCR;                                 /*  CS5BCR          */
    4382    volatile uint8_t   dummy4[12];                             /*                  */
    44 #define BSC_CSnWCR_COUNT 6
     83
     84/* #define BSC_CSnWCR_COUNT (6) */
    4585    volatile uint32_t  CS0WCR;                                 /*  CS0WCR          */
    4686    volatile uint32_t  CS1WCR;                                 /*  CS1WCR          */
    … …  
    5595    volatile uint32_t  RTCOR;                                  /*  RTCOR           */
    5696    volatile uint8_t   dummy6[4];                              /*                  */
    57 #define BSC_TOSCORn_COUNT 6
     97
     98/* #define BSC_TOSCORn_COUNT (6) */
    5899    volatile uint32_t  TOSCOR0;                                /*  TOSCOR0         */
    59100    volatile uint32_t  TOSCOR1;                                /*  TOSCOR1         */
    … …  
    65106    volatile uint32_t  TOSTR;                                  /*  TOSTR           */
    66107    volatile uint32_t  TOENR;                                  /*  TOENR           */
    67 };
     108} r_io_bsc_t;
    68109
    69110
    70 #define BSC     (*(struct st_bsc     *)0x3FFFC000uL) /* BSC */
    71 
    72 
    73 #define BSCCMNCR BSC.CMNCR
    74 #define BSCCS0BCR BSC.CS0BCR
    75 #define BSCCS1BCR BSC.CS1BCR
    76 #define BSCCS2BCR BSC.CS2BCR
    77 #define BSCCS3BCR BSC.CS3BCR
    78 #define BSCCS4BCR BSC.CS4BCR
    79 #define BSCCS5BCR BSC.CS5BCR
    80 #define BSCCS0WCR BSC.CS0WCR
    81 #define BSCCS1WCR BSC.CS1WCR
    82 #define BSCCS2WCR BSC.CS2WCR
    83 #define BSCCS3WCR BSC.CS3WCR
    84 #define BSCCS4WCR BSC.CS4WCR
    85 #define BSCCS5WCR BSC.CS5WCR
    86 #define BSCSDCR BSC.SDCR
    87 #define BSCRTCSR BSC.RTCSR
    88 #define BSCRTCNT BSC.RTCNT
    89 #define BSCRTCOR BSC.RTCOR
    90 #define BSCTOSCOR0 BSC.TOSCOR0
    91 #define BSCTOSCOR1 BSC.TOSCOR1
    92 #define BSCTOSCOR2 BSC.TOSCOR2
    93 #define BSCTOSCOR3 BSC.TOSCOR3
    94 #define BSCTOSCOR4 BSC.TOSCOR4
    95 #define BSCTOSCOR5 BSC.TOSCOR5
    96 #define BSCTOSTR BSC.TOSTR
    97 #define BSCTOENR BSC.TOENR
    98111/* <-SEC M1.10.1 */
     112/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     113/* <-QAC 0857 */
     114/* <-QAC 0639 */
    99115#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/ceu_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef CEU_IODEFINE_H
    3030#define CEU_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3134/* ->SEC M1.10.1 : Not magic number */
    3235
    33 struct st_ceu
    34 {                                                          /* CEU              */
     36#define CEU     (*(struct st_ceu     *)0xE8210000uL) /* CEU */
     37
     38
     39/* Start of channel array defines of CEU */
     40
     41/* Channel array defines of CEUn */
     42/*(Sample) value = CEUn[ channel ]->CAMOR; */
     43#define CEUn_COUNT  (3)
     44#define CEUn_ADDRESS_LIST \
     45{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     46    (volatile struct st_ceu_n*)&CEU_A, \
     47    (volatile struct st_ceu_n*)&CEU_B, \
     48    (volatile struct st_ceu_n*)&CEU_M \
     49}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     50#define CEU_A   (*(struct st_ceu_n *)&CEU.CAPSR)                 /* CEU_A */
     51#define CEU_B   (*(struct st_ceu_n *)&CEU.dummy3111)             /* CEU_B */
     52#define CEU_M   (*(struct st_ceu_n *)&CEU.dummy3151)             /* CEU_M */
     53
     54/* End of channel array defines of CEU */
     55
     56
     57#define CEUCAPSR (CEU.CAPSR)
     58#define CEUCAPCR (CEU.CAPCR)
     59#define CEUCAMCR (CEU.CAMCR)
     60#define CEUCMCYR (CEU.CMCYR)
     61#define CEUCAMOR_A (CEU.CAMOR_A)
     62#define CEUCAPWR_A (CEU.CAPWR_A)
     63#define CEUCAIFR (CEU.CAIFR)
     64#define CEUCRCNTR (CEU.CRCNTR)
     65#define CEUCRCMPR (CEU.CRCMPR)
     66#define CEUCFLCR_A (CEU.CFLCR_A)
     67#define CEUCFSZR_A (CEU.CFSZR_A)
     68#define CEUCDWDR_A (CEU.CDWDR_A)
     69#define CEUCDAYR_A (CEU.CDAYR_A)
     70#define CEUCDACR_A (CEU.CDACR_A)
     71#define CEUCDBYR_A (CEU.CDBYR_A)
     72#define CEUCDBCR_A (CEU.CDBCR_A)
     73#define CEUCBDSR_A (CEU.CBDSR_A)
     74#define CEUCFWCR (CEU.CFWCR)
     75#define CEUCLFCR_A (CEU.CLFCR_A)
     76#define CEUCDOCR_A (CEU.CDOCR_A)
     77#define CEUCEIER (CEU.CEIER)
     78#define CEUCETCR (CEU.CETCR)
     79#define CEUCSTSR (CEU.CSTSR)
     80#define CEUCDSSR (CEU.CDSSR)
     81#define CEUCDAYR2_A (CEU.CDAYR2_A)
     82#define CEUCDACR2_A (CEU.CDACR2_A)
     83#define CEUCDBYR2_A (CEU.CDBYR2_A)
     84#define CEUCDBCR2_A (CEU.CDBCR2_A)
     85#define CEUCAMOR_B (CEU.CAMOR_B)
     86#define CEUCAPWR_B (CEU.CAPWR_B)
     87#define CEUCFLCR_B (CEU.CFLCR_B)
     88#define CEUCFSZR_B (CEU.CFSZR_B)
     89#define CEUCDWDR_B (CEU.CDWDR_B)
     90#define CEUCDAYR_B (CEU.CDAYR_B)
     91#define CEUCDACR_B (CEU.CDACR_B)
     92#define CEUCDBYR_B (CEU.CDBYR_B)
     93#define CEUCDBCR_B (CEU.CDBCR_B)
     94#define CEUCBDSR_B (CEU.CBDSR_B)
     95#define CEUCLFCR_B (CEU.CLFCR_B)
     96#define CEUCDOCR_B (CEU.CDOCR_B)
     97#define CEUCDAYR2_B (CEU.CDAYR2_B)
     98#define CEUCDACR2_B (CEU.CDACR2_B)
     99#define CEUCDBYR2_B (CEU.CDBYR2_B)
     100#define CEUCDBCR2_B (CEU.CDBCR2_B)
     101#define CEUCAMOR_M (CEU.CAMOR_M)
     102#define CEUCAPWR_M (CEU.CAPWR_M)
     103#define CEUCFLCR_M (CEU.CFLCR_M)
     104#define CEUCFSZR_M (CEU.CFSZR_M)
     105#define CEUCDWDR_M (CEU.CDWDR_M)
     106#define CEUCDAYR_M (CEU.CDAYR_M)
     107#define CEUCDACR_M (CEU.CDACR_M)
     108#define CEUCDBYR_M (CEU.CDBYR_M)
     109#define CEUCDBCR_M (CEU.CDBCR_M)
     110#define CEUCBDSR_M (CEU.CBDSR_M)
     111#define CEUCLFCR_M (CEU.CLFCR_M)
     112#define CEUCDOCR_M (CEU.CDOCR_M)
     113#define CEUCDAYR2_M (CEU.CDAYR2_M)
     114#define CEUCDACR2_M (CEU.CDACR2_M)
     115#define CEUCDBYR2_M (CEU.CDBYR2_M)
     116#define CEUCDBCR2_M (CEU.CDBCR2_M)
     117
     118
     119typedef struct st_ceu
     120{
     121                                                           /* CEU              */
     122
    35123/* start of struct st_ceu_n */
    36124    volatile uint32_t  CAPSR;                                  /*  CAPSR           */
    … …  
    68156    volatile uint32_t  CDBYR2_A;                               /*  CDBYR2_A        */
    69157    volatile uint32_t  CDBCR2_A;                               /*  CDBCR2_A        */
     158
    70159/* end of struct st_ceu_n */
    71160    volatile uint8_t   dummy3110[3936];                        /*                  */
     161
    72162/* start of struct st_ceu_n */
    73163    volatile uint8_t   dummy3111[4];                           /*                  */
    … …  
    105195    volatile uint32_t  CDBYR2_B;                               /*  CDBYR2_B        */
    106196    volatile uint32_t  CDBCR2_B;                               /*  CDBCR2_B        */
     197
    107198/* end of struct st_ceu_n */
    108199    volatile uint8_t   dummy3150[3936];                        /*                  */
     200
    109201/* start of struct st_ceu_n */
    110202    volatile uint8_t   dummy3151[4];                           /*                  */
    … …  
    142234    volatile uint32_t  CDBYR2_M;                               /*  CDBYR2_M        */
    143235    volatile uint32_t  CDBCR2_M;                               /*  CDBCR2_M        */
     236
    144237/* end of struct st_ceu_n */
    145 };
    146 
    147 
    148 struct st_ceu_n
     238} r_io_ceu_t;
     239
     240
     241typedef struct st_ceu_n
    149242{
     243 
    150244    volatile uint32_t  not_common1;                            /*                  */
    151245    volatile uint32_t  not_common2;                            /*                  */
    … …  
    182276    volatile uint32_t  CDBYR2;                                 /*  CDBYR2          */
    183277    volatile uint32_t  CDBCR2;                                 /*  CDBCR2          */
    184 };
    185 
    186 
    187 #define CEU     (*(struct st_ceu     *)0xE8210000uL) /* CEU */
    188 
    189 
    190 /* Start of channnel array defines of CEU */
    191 
    192 /* Channnel array defines of CEUn */
    193 /*(Sample) value = CEUn[ channel ]->CAMOR; */
    194 #define CEUn_COUNT  3
    195 #define CEUn_ADDRESS_LIST \
    196 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    197     (volatile struct st_ceu_n*)&CEU_A, \
    198     (volatile struct st_ceu_n*)&CEU_B, \
    199     (volatile struct st_ceu_n*)&CEU_M \
    200 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    201 #define CEU_A   (*(struct st_ceu_n *)&CEU.CAPSR)                 /* CEU_A */
    202 #define CEU_B   (*(struct st_ceu_n *)&CEU.dummy3111)             /* CEU_B */
    203 #define CEU_M   (*(struct st_ceu_n *)&CEU.dummy3151)             /* CEU_M */
    204 
    205 /* End of channnel array defines of CEU */
    206 
    207 
    208 #define CEUCAPSR CEU.CAPSR
    209 #define CEUCAPCR CEU.CAPCR
    210 #define CEUCAMCR CEU.CAMCR
    211 #define CEUCMCYR CEU.CMCYR
    212 #define CEUCAMOR_A CEU.CAMOR_A
    213 #define CEUCAPWR_A CEU.CAPWR_A
    214 #define CEUCAIFR CEU.CAIFR
    215 #define CEUCRCNTR CEU.CRCNTR
    216 #define CEUCRCMPR CEU.CRCMPR
    217 #define CEUCFLCR_A CEU.CFLCR_A
    218 #define CEUCFSZR_A CEU.CFSZR_A
    219 #define CEUCDWDR_A CEU.CDWDR_A
    220 #define CEUCDAYR_A CEU.CDAYR_A
    221 #define CEUCDACR_A CEU.CDACR_A
    222 #define CEUCDBYR_A CEU.CDBYR_A
    223 #define CEUCDBCR_A CEU.CDBCR_A
    224 #define CEUCBDSR_A CEU.CBDSR_A
    225 #define CEUCFWCR CEU.CFWCR
    226 #define CEUCLFCR_A CEU.CLFCR_A
    227 #define CEUCDOCR_A CEU.CDOCR_A
    228 #define CEUCEIER CEU.CEIER
    229 #define CEUCETCR CEU.CETCR
    230 #define CEUCSTSR CEU.CSTSR
    231 #define CEUCDSSR CEU.CDSSR
    232 #define CEUCDAYR2_A CEU.CDAYR2_A
    233 #define CEUCDACR2_A CEU.CDACR2_A
    234 #define CEUCDBYR2_A CEU.CDBYR2_A
    235 #define CEUCDBCR2_A CEU.CDBCR2_A
    236 #define CEUCAMOR_B CEU.CAMOR_B
    237 #define CEUCAPWR_B CEU.CAPWR_B
    238 #define CEUCFLCR_B CEU.CFLCR_B
    239 #define CEUCFSZR_B CEU.CFSZR_B
    240 #define CEUCDWDR_B CEU.CDWDR_B
    241 #define CEUCDAYR_B CEU.CDAYR_B
    242 #define CEUCDACR_B CEU.CDACR_B
    243 #define CEUCDBYR_B CEU.CDBYR_B
    244 #define CEUCDBCR_B CEU.CDBCR_B
    245 #define CEUCBDSR_B CEU.CBDSR_B
    246 #define CEUCLFCR_B CEU.CLFCR_B
    247 #define CEUCDOCR_B CEU.CDOCR_B
    248 #define CEUCDAYR2_B CEU.CDAYR2_B
    249 #define CEUCDACR2_B CEU.CDACR2_B
    250 #define CEUCDBYR2_B CEU.CDBYR2_B
    251 #define CEUCDBCR2_B CEU.CDBCR2_B
    252 #define CEUCAMOR_M CEU.CAMOR_M
    253 #define CEUCAPWR_M CEU.CAPWR_M
    254 #define CEUCFLCR_M CEU.CFLCR_M
    255 #define CEUCFSZR_M CEU.CFSZR_M
    256 #define CEUCDWDR_M CEU.CDWDR_M
    257 #define CEUCDAYR_M CEU.CDAYR_M
    258 #define CEUCDACR_M CEU.CDACR_M
    259 #define CEUCDBYR_M CEU.CDBYR_M
    260 #define CEUCDBCR_M CEU.CDBCR_M
    261 #define CEUCBDSR_M CEU.CBDSR_M
    262 #define CEUCLFCR_M CEU.CLFCR_M
    263 #define CEUCDOCR_M CEU.CDOCR_M
    264 #define CEUCDAYR2_M CEU.CDAYR2_M
    265 #define CEUCDACR2_M CEU.CDACR2_M
    266 #define CEUCDBYR2_M CEU.CDBYR2_M
    267 #define CEUCDBCR2_M CEU.CDBCR2_M
     278} r_io_ceu_n_t;
     279
     280
     281/* Channel array defines of CEUn (2)*/
     282#ifdef  DECLARE_CEUn_CHANNELS
     283volatile struct st_ceu_n*  CEUn[ CEUn_COUNT ] =
     284    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     285    CEUn_ADDRESS_LIST;
     286    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     287#endif  /* DECLARE_CEUn_CHANNELS */
     288/* End of channel array defines of CEUn (2)*/
     289
     290
    268291/* <-SEC M1.10.1 */
     292/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     293/* <-QAC 0857 */
     294/* <-QAC 0639 */
    269295#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/cpg_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef CPG_IODEFINE_H
    3030#define CPG_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3134/* ->SEC M1.10.1 : Not magic number */
    3235
    33 struct st_cpg
    34 {                                                          /* CPG              */
     36#define CPG     (*(struct st_cpg     *)0xFCFE0010uL) /* CPG */
     37
     38
     39/* Start of channel array defines of CPG */
     40
     41/* Channel array defines of CPG_FROM_SWRSTCR1_ARRAY */
     42/*(Sample) value = CPG_FROM_SWRSTCR1_ARRAY[ channel ]->SWRSTCR1; */
     43#define CPG_FROM_SWRSTCR1_ARRAY_COUNT  (3)
     44#define CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST \
     45{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     46    &CPG_FROM_SWRSTCR1, &CPG_FROM_SWRSTCR2, &CPG_FROM_SWRSTCR3 \
     47}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     48#define CPG_FROM_SWRSTCR1 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR1) /* CPG_FROM_SWRSTCR1 */
     49#define CPG_FROM_SWRSTCR2 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR2) /* CPG_FROM_SWRSTCR2 */
     50#define CPG_FROM_SWRSTCR3 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR3) /* CPG_FROM_SWRSTCR3 */
     51
     52
     53/* Channel array defines of CPG_FROM_STBCR3_ARRAY */
     54/*(Sample) value = CPG_FROM_STBCR3_ARRAY[ channel ]->STBCR3; */
     55#define CPG_FROM_STBCR3_ARRAY_COUNT  (10)
     56#define CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST \
     57{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     58    &CPG_FROM_STBCR3, &CPG_FROM_STBCR4, &CPG_FROM_STBCR5, &CPG_FROM_STBCR6, &CPG_FROM_STBCR7, &CPG_FROM_STBCR8, &CPG_FROM_STBCR9, &CPG_FROM_STBCR10, \
     59    &CPG_FROM_STBCR11, &CPG_FROM_STBCR12 \
     60}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     61#define CPG_FROM_STBCR3 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR3) /* CPG_FROM_STBCR3 */
     62#define CPG_FROM_STBCR4 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR4) /* CPG_FROM_STBCR4 */
     63#define CPG_FROM_STBCR5 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR5) /* CPG_FROM_STBCR5 */
     64#define CPG_FROM_STBCR6 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR6) /* CPG_FROM_STBCR6 */
     65#define CPG_FROM_STBCR7 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR7) /* CPG_FROM_STBCR7 */
     66#define CPG_FROM_STBCR8 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR8) /* CPG_FROM_STBCR8 */
     67#define CPG_FROM_STBCR9 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR9) /* CPG_FROM_STBCR9 */
     68#define CPG_FROM_STBCR10 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR10) /* CPG_FROM_STBCR10 */
     69#define CPG_FROM_STBCR11 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR11) /* CPG_FROM_STBCR11 */
     70#define CPG_FROM_STBCR12 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR12) /* CPG_FROM_STBCR12 */
     71
     72
     73/* Channel array defines of CPG_FROM_SYSCR1_ARRAY */
     74/*(Sample) value = CPG_FROM_SYSCR1_ARRAY[ channel ]->SYSCR1; */
     75#define CPG_FROM_SYSCR1_ARRAY_COUNT  (3)
     76#define CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST \
     77{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     78    &CPG_FROM_SYSCR1, &CPG_FROM_SYSCR2, &CPG_FROM_SYSCR3 \
     79}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     80#define CPG_FROM_SYSCR1 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR1) /* CPG_FROM_SYSCR1 */
     81#define CPG_FROM_SYSCR2 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR2) /* CPG_FROM_SYSCR2 */
     82#define CPG_FROM_SYSCR3 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR3) /* CPG_FROM_SYSCR3 */
     83
     84/* End of channel array defines of CPG */
     85
     86
     87#define CPGFRQCR (CPG.FRQCR)
     88#define CPGFRQCR2 (CPG.FRQCR2)
     89#define CPGCPUSTS (CPG.CPUSTS)
     90#define CPGSTBCR1 (CPG.STBCR1)
     91#define CPGSTBCR2 (CPG.STBCR2)
     92#define CPGSTBREQ1 (CPG.STBREQ1)
     93#define CPGSTBREQ2 (CPG.STBREQ2)
     94#define CPGSTBACK1 (CPG.STBACK1)
     95#define CPGSTBACK2 (CPG.STBACK2)
     96#define CPGSYSCR1 (CPG.SYSCR1)
     97#define CPGSYSCR2 (CPG.SYSCR2)
     98#define CPGSYSCR3 (CPG.SYSCR3)
     99#define CPGSTBCR3 (CPG.STBCR3)
     100#define CPGSTBCR4 (CPG.STBCR4)
     101#define CPGSTBCR5 (CPG.STBCR5)
     102#define CPGSTBCR6 (CPG.STBCR6)
     103#define CPGSTBCR7 (CPG.STBCR7)
     104#define CPGSTBCR8 (CPG.STBCR8)
     105#define CPGSTBCR9 (CPG.STBCR9)
     106#define CPGSTBCR10 (CPG.STBCR10)
     107#define CPGSTBCR11 (CPG.STBCR11)
     108#define CPGSTBCR12 (CPG.STBCR12)
     109#define CPGSWRSTCR1 (CPG.SWRSTCR1)
     110#define CPGSWRSTCR2 (CPG.SWRSTCR2)
     111#define CPGSWRSTCR3 (CPG.SWRSTCR3)
     112#define CPGSTBCR13 (CPG.STBCR13)
     113#define CPGRRAMKP (CPG.RRAMKP)
     114#define CPGDSCTR (CPG.DSCTR)
     115#define CPGDSSSR (CPG.DSSSR)
     116#define CPGDSESR (CPG.DSESR)
     117#define CPGDSFR (CPG.DSFR)
     118#define CPGXTALCTR (CPG.XTALCTR)
     119
     120
     121typedef struct st_cpg
     122{
     123                                                           /* CPG              */
    35124    volatile uint16_t FRQCR;                                  /*  FRQCR           */
    36125    volatile uint8_t   dummy319[2];                            /*                  */
    … …  
    51140    volatile uint8_t   STBACK2;                                /*  STBACK2         */
    52141    volatile uint8_t   dummy327[955];                          /*                  */
     142
    53143/* start of struct st_cpg_from_syscr1 */
    54144    volatile uint8_t   SYSCR1;                                 /*  SYSCR1          */
    55145    volatile uint8_t   dummy328[3];                            /*                  */
     146
    56147/* end of struct st_cpg_from_syscr1 */
     148
    57149/* start of struct st_cpg_from_syscr1 */
    58150    volatile uint8_t   SYSCR2;                                 /*  SYSCR2          */
    59151    volatile uint8_t   dummy329[3];                            /*                  */
     152
    60153/* end of struct st_cpg_from_syscr1 */
     154
    61155/* start of struct st_cpg_from_syscr1 */
    62156    volatile uint8_t   SYSCR3;                                 /*  SYSCR3          */
    63157    volatile uint8_t   dummy3300[3];                           /*                  */
     158
    64159/* end of struct st_cpg_from_syscr1 */
    65160    volatile uint8_t   dummy3301[20];                          /*                  */
     161
    66162/* start of struct st_cpg_from_stbcr3 */
    67163    volatile uint8_t   STBCR3;                                 /*  STBCR3          */
    68164    volatile uint8_t   dummy331[3];                            /*                  */
    69 /* end of struct st_cpg_from_stbcr3 */
     165
     166/* end of struct st_cpg_from_stbcr3 */
     167
    70168/* start of struct st_cpg_from_stbcr3 */
    71169    volatile uint8_t   STBCR4;                                 /*  STBCR4          */
    72170    volatile uint8_t   dummy332[3];                            /*                  */
    73 /* end of struct st_cpg_from_stbcr3 */
     171
     172/* end of struct st_cpg_from_stbcr3 */
     173
    74174/* start of struct st_cpg_from_stbcr3 */
    75175    volatile uint8_t   STBCR5;                                 /*  STBCR5          */
    76176    volatile uint8_t   dummy333[3];                            /*                  */
    77 /* end of struct st_cpg_from_stbcr3 */
     177
     178/* end of struct st_cpg_from_stbcr3 */
     179
    78180/* start of struct st_cpg_from_stbcr3 */
    79181    volatile uint8_t   STBCR6;                                 /*  STBCR6          */
    80182    volatile uint8_t   dummy334[3];                            /*                  */
    81 /* end of struct st_cpg_from_stbcr3 */
     183
     184/* end of struct st_cpg_from_stbcr3 */
     185
    82186/* start of struct st_cpg_from_stbcr3 */
    83187    volatile uint8_t   STBCR7;                                 /*  STBCR7          */
    84188    volatile uint8_t   dummy335[3];                            /*                  */
    85 /* end of struct st_cpg_from_stbcr3 */
     189
     190/* end of struct st_cpg_from_stbcr3 */
     191
    86192/* start of struct st_cpg_from_stbcr3 */
    87193    volatile uint8_t   STBCR8;                                 /*  STBCR8          */
    88194    volatile uint8_t   dummy336[3];                            /*                  */
    89 /* end of struct st_cpg_from_stbcr3 */
     195
     196/* end of struct st_cpg_from_stbcr3 */
     197
    90198/* start of struct st_cpg_from_stbcr3 */
    91199    volatile uint8_t   STBCR9;                                 /*  STBCR9          */
    92200    volatile uint8_t   dummy337[3];                            /*                  */
    93 /* end of struct st_cpg_from_stbcr3 */
     201
     202/* end of struct st_cpg_from_stbcr3 */
     203
    94204/* start of struct st_cpg_from_stbcr3 */
    95205    volatile uint8_t   STBCR10;                                /*  STBCR10         */
    96206    volatile uint8_t   dummy338[3];                            /*                  */
    97 /* end of struct st_cpg_from_stbcr3 */
     207
     208/* end of struct st_cpg_from_stbcr3 */
     209
    98210/* start of struct st_cpg_from_stbcr3 */
    99211    volatile uint8_t   STBCR11;                                /*  STBCR11         */
    100212    volatile uint8_t   dummy339[3];                            /*                  */
    101 /* end of struct st_cpg_from_stbcr3 */
     213
     214/* end of struct st_cpg_from_stbcr3 */
     215
    102216/* start of struct st_cpg_from_stbcr3 */
    103217    volatile uint8_t   STBCR12;                                /*  STBCR12         */
    104218    volatile uint8_t   dummy3400[3];                           /*                  */
     219
    105220/* end of struct st_cpg_from_stbcr3 */
    106221    volatile uint8_t   dummy3401[24];                          /*                  */
     222
    107223/* start of struct st_cpg_from_swrstcr1 */
    108224    volatile uint8_t   SWRSTCR1;                               /*  SWRSTCR1        */
    109225    volatile uint8_t   dummy341[3];                            /*                  */
     226
    110227/* end of struct st_cpg_from_swrstcr1 */
     228
    111229/* start of struct st_cpg_from_swrstcr1 */
    112230    volatile uint8_t   SWRSTCR2;                               /*  SWRSTCR2        */
    113231    volatile uint8_t   dummy342[3];                            /*                  */
     232
    114233/* end of struct st_cpg_from_swrstcr1 */
     234
    115235/* start of struct st_cpg_from_swrstcr1 */
    116236    volatile uint8_t   SWRSTCR3;                               /*  SWRSTCR3        */
    117237    volatile uint8_t   dummy3430[3];                           /*                  */
     238
    118239/* end of struct st_cpg_from_swrstcr1 */
    119240    volatile uint8_t   dummy3431[4];                           /*                  */
    … …  
    129250    volatile uint8_t   dummy347[6];                            /*                  */
    130251    volatile uint8_t   XTALCTR;                                /*  XTALCTR         */
    131 };
    132 
    133 
    134 struct st_cpg_from_syscr1
     252} r_io_cpg_t;
     253
     254
     255typedef struct st_cpg_from_syscr1
    135256{
     257 
    136258    volatile uint8_t   SYSCR1;                                 /*  SYSCR1          */
    137259    volatile uint8_t   dummy1[3];                              /*                  */
    138 };
    139 
    140 
    141 struct st_cpg_from_stbcr3
     260} r_io_cpg_from_syscr1_t;
     261
     262
     263typedef struct st_cpg_from_stbcr3
    142264{
     265 
    143266    volatile uint8_t   STBCR3;                                 /*  STBCR3          */
    144267    volatile uint8_t   dummy1[3];                              /*                  */
    145 };
    146 
    147 
    148 struct st_cpg_from_swrstcr1
     268} r_io_cpg_from_stbcr3_t;
     269
     270
     271typedef struct st_cpg_from_swrstcr1
    149272{
     273 
    150274    volatile uint8_t   SWRSTCR1;                               /*  SWRSTCR1        */
    151275    volatile uint8_t   dummy1[3];                              /*                  */
    152 };
    153 
    154 
    155 #define CPG     (*(struct st_cpg     *)0xFCFE0010uL) /* CPG */
    156 
    157 
    158 /* Start of channnel array defines of CPG */
    159 
    160 /* Channnel array defines of CPG_FROM_SWRSTCR1_ARRAY */
    161 /*(Sample) value = CPG_FROM_SWRSTCR1_ARRAY[ channel ]->SWRSTCR1; */
    162 #define CPG_FROM_SWRSTCR1_ARRAY_COUNT  3
    163 #define CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST \
    164 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    165     &CPG_FROM_SWRSTCR1, &CPG_FROM_SWRSTCR2, &CPG_FROM_SWRSTCR3 \
    166 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    167 #define CPG_FROM_SWRSTCR1 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR1) /* CPG_FROM_SWRSTCR1 */
    168 #define CPG_FROM_SWRSTCR2 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR2) /* CPG_FROM_SWRSTCR2 */
    169 #define CPG_FROM_SWRSTCR3 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR3) /* CPG_FROM_SWRSTCR3 */
    170 
    171 
    172 /* Channnel array defines of CPG_FROM_STBCR3_ARRAY */
    173 /*(Sample) value = CPG_FROM_STBCR3_ARRAY[ channel ]->STBCR3; */
    174 #define CPG_FROM_STBCR3_ARRAY_COUNT  10
    175 #define CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST \
    176 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    177     &CPG_FROM_STBCR3, &CPG_FROM_STBCR4, &CPG_FROM_STBCR5, &CPG_FROM_STBCR6, &CPG_FROM_STBCR7, &CPG_FROM_STBCR8, &CPG_FROM_STBCR9, &CPG_FROM_STBCR10, \
    178     &CPG_FROM_STBCR11, &CPG_FROM_STBCR12 \
    179 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    180 #define CPG_FROM_STBCR3 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR3) /* CPG_FROM_STBCR3 */
    181 #define CPG_FROM_STBCR4 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR4) /* CPG_FROM_STBCR4 */
    182 #define CPG_FROM_STBCR5 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR5) /* CPG_FROM_STBCR5 */
    183 #define CPG_FROM_STBCR6 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR6) /* CPG_FROM_STBCR6 */
    184 #define CPG_FROM_STBCR7 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR7) /* CPG_FROM_STBCR7 */
    185 #define CPG_FROM_STBCR8 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR8) /* CPG_FROM_STBCR8 */
    186 #define CPG_FROM_STBCR9 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR9) /* CPG_FROM_STBCR9 */
    187 #define CPG_FROM_STBCR10 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR10) /* CPG_FROM_STBCR10 */
    188 #define CPG_FROM_STBCR11 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR11) /* CPG_FROM_STBCR11 */
    189 #define CPG_FROM_STBCR12 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR12) /* CPG_FROM_STBCR12 */
    190 
    191 
    192 /* Channnel array defines of CPG_FROM_SYSCR1_ARRAY */
    193 /*(Sample) value = CPG_FROM_SYSCR1_ARRAY[ channel ]->SYSCR1; */
    194 #define CPG_FROM_SYSCR1_ARRAY_COUNT  3
    195 #define CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST \
    196 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    197     &CPG_FROM_SYSCR1, &CPG_FROM_SYSCR2, &CPG_FROM_SYSCR3 \
    198 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    199 #define CPG_FROM_SYSCR1 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR1) /* CPG_FROM_SYSCR1 */
    200 #define CPG_FROM_SYSCR2 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR2) /* CPG_FROM_SYSCR2 */
    201 #define CPG_FROM_SYSCR3 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR3) /* CPG_FROM_SYSCR3 */
    202 
    203 /* End of channnel array defines of CPG */
    204 
    205 
    206 #define CPGFRQCR CPG.FRQCR
    207 #define CPGFRQCR2 CPG.FRQCR2
    208 #define CPGCPUSTS CPG.CPUSTS
    209 #define CPGSTBCR1 CPG.STBCR1
    210 #define CPGSTBCR2 CPG.STBCR2
    211 #define CPGSTBREQ1 CPG.STBREQ1
    212 #define CPGSTBREQ2 CPG.STBREQ2
    213 #define CPGSTBACK1 CPG.STBACK1
    214 #define CPGSTBACK2 CPG.STBACK2
    215 #define CPGSYSCR1 CPG.SYSCR1
    216 #define CPGSYSCR2 CPG.SYSCR2
    217 #define CPGSYSCR3 CPG.SYSCR3
    218 #define CPGSTBCR3 CPG.STBCR3
    219 #define CPGSTBCR4 CPG.STBCR4
    220 #define CPGSTBCR5 CPG.STBCR5
    221 #define CPGSTBCR6 CPG.STBCR6
    222 #define CPGSTBCR7 CPG.STBCR7
    223 #define CPGSTBCR8 CPG.STBCR8
    224 #define CPGSTBCR9 CPG.STBCR9
    225 #define CPGSTBCR10 CPG.STBCR10
    226 #define CPGSTBCR11 CPG.STBCR11
    227 #define CPGSTBCR12 CPG.STBCR12
    228 #define CPGSWRSTCR1 CPG.SWRSTCR1
    229 #define CPGSWRSTCR2 CPG.SWRSTCR2
    230 #define CPGSWRSTCR3 CPG.SWRSTCR3
    231 #define CPGSTBCR13 CPG.STBCR13
    232 #define CPGRRAMKP CPG.RRAMKP
    233 #define CPGDSCTR CPG.DSCTR
    234 #define CPGDSSSR CPG.DSSSR
    235 #define CPGDSESR CPG.DSESR
    236 #define CPGDSFR CPG.DSFR
    237 #define CPGXTALCTR CPG.XTALCTR
     276} r_io_cpg_from_swrstcr1_t;
     277
     278
     279/* Channel array defines of CPG (2)*/
     280#ifdef  DECLARE_CPG_FROM_SWRSTCR1_ARRAY_CHANNELS
     281volatile struct st_cpg_from_swrstcr1*  CPG_FROM_SWRSTCR1_ARRAY[ CPG_FROM_SWRSTCR1_ARRAY_COUNT ] =
     282    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     283    CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST;
     284    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     285#endif  /* DECLARE_CPG_FROM_SWRSTCR1_ARRAY_CHANNELS */
     286
     287#ifdef  DECLARE_CPG_FROM_STBCR3_ARRAY_CHANNELS
     288volatile struct st_cpg_from_stbcr3*  CPG_FROM_STBCR3_ARRAY[ CPG_FROM_STBCR3_ARRAY_COUNT ] =
     289    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     290    CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST;
     291    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     292#endif  /* DECLARE_CPG_FROM_STBCR3_ARRAY_CHANNELS */
     293
     294#ifdef  DECLARE_CPG_FROM_SYSCR1_ARRAY_CHANNELS
     295volatile struct st_cpg_from_syscr1*  CPG_FROM_SYSCR1_ARRAY[ CPG_FROM_SYSCR1_ARRAY_COUNT ] =
     296    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     297    CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST;
     298    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     299#endif  /* DECLARE_CPG_FROM_SYSCR1_ARRAY_CHANNELS */
     300/* End of channel array defines of CPG (2)*/
     301
     302
    238303/* <-SEC M1.10.1 */
     304/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     305/* <-QAC 0857 */
     306/* <-QAC 0639 */
    239307#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/disc_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef DISC_IODEFINE_H
    3030#define DISC_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3134/* ->SEC M1.10.1 : Not magic number */
    3235
    33 struct st_disc
    34 {                                                          /* DISC             */
     36#define DISC0   (*(struct st_disc    *)0xFCFFA800uL) /* DISC0 */
     37#define DISC1   (*(struct st_disc    *)0xFCFFB000uL) /* DISC1 */
     38
     39
     40/* Start of channel array defines of DISC */
     41
     42/* Channel array defines of DISC */
     43/*(Sample) value = DISC[ channel ]->DOCMCR; */
     44#define DISC_COUNT  (2)
     45#define DISC_ADDRESS_LIST \
     46{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     47    &DISC0, &DISC1 \
     48}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     49
     50/* End of channel array defines of DISC */
     51
     52
     53#define DISC0DOCMCR (DISC0.DOCMCR)
     54#define DISC0DOCMSTR (DISC0.DOCMSTR)
     55#define DISC0DOCMCLSTR (DISC0.DOCMCLSTR)
     56#define DISC0DOCMIENR (DISC0.DOCMIENR)
     57#define DISC0DOCMPMR (DISC0.DOCMPMR)
     58#define DISC0DOCMECRCR (DISC0.DOCMECRCR)
     59#define DISC0DOCMCCRCR (DISC0.DOCMCCRCR)
     60#define DISC0DOCMSPXR (DISC0.DOCMSPXR)
     61#define DISC0DOCMSPYR (DISC0.DOCMSPYR)
     62#define DISC0DOCMSZXR (DISC0.DOCMSZXR)
     63#define DISC0DOCMSZYR (DISC0.DOCMSZYR)
     64#define DISC0DOCMCRCIR (DISC0.DOCMCRCIR)
     65#define DISC1DOCMCR (DISC1.DOCMCR)
     66#define DISC1DOCMSTR (DISC1.DOCMSTR)
     67#define DISC1DOCMCLSTR (DISC1.DOCMCLSTR)
     68#define DISC1DOCMIENR (DISC1.DOCMIENR)
     69#define DISC1DOCMPMR (DISC1.DOCMPMR)
     70#define DISC1DOCMECRCR (DISC1.DOCMECRCR)
     71#define DISC1DOCMCCRCR (DISC1.DOCMCCRCR)
     72#define DISC1DOCMSPXR (DISC1.DOCMSPXR)
     73#define DISC1DOCMSPYR (DISC1.DOCMSPYR)
     74#define DISC1DOCMSZXR (DISC1.DOCMSZXR)
     75#define DISC1DOCMSZYR (DISC1.DOCMSZYR)
     76#define DISC1DOCMCRCIR (DISC1.DOCMCRCIR)
     77
     78
     79typedef struct st_disc
     80{
     81                                                           /* DISC             */
    3582    volatile uint32_t  DOCMCR;                                 /*  DOCMCR          */
    3683    volatile uint32_t  DOCMSTR;                                /*  DOCMSTR         */
    … …  
    4693    volatile uint32_t  DOCMSZYR;                               /*  DOCMSZYR        */
    4794    volatile uint32_t  DOCMCRCIR;                              /*  DOCMCRCIR       */
    48 };
     95} r_io_disc_t;
    4996
    5097
    51 #define DISC0   (*(struct st_disc    *)0xFCFFA800uL) /* DISC0 */
    52 #define DISC1   (*(struct st_disc    *)0xFCFFB000uL) /* DISC1 */
     98/* Channel array defines of DISC (2)*/
     99#ifdef  DECLARE_DISC_CHANNELS
     100volatile struct st_disc*  DISC[ DISC_COUNT ] =
     101    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     102    DISC_ADDRESS_LIST;
     103    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     104#endif  /* DECLARE_DISC_CHANNELS */
     105/* End of channel array defines of DISC (2)*/
    53106
    54107
    55 /* Start of channnel array defines of DISC */
    56 
    57 /* Channnel array defines of DISC */
    58 /*(Sample) value = DISC[ channel ]->DOCMCR; */
    59 #define DISC_COUNT  2
    60 #define DISC_ADDRESS_LIST \
    61 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    62     &DISC0, &DISC1 \
    63 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    64 
    65 /* End of channnel array defines of DISC */
    66 
    67 
    68 #define DISC0DOCMCR DISC0.DOCMCR
    69 #define DISC0DOCMSTR DISC0.DOCMSTR
    70 #define DISC0DOCMCLSTR DISC0.DOCMCLSTR
    71 #define DISC0DOCMIENR DISC0.DOCMIENR
    72 #define DISC0DOCMPMR DISC0.DOCMPMR
    73 #define DISC0DOCMECRCR DISC0.DOCMECRCR
    74 #define DISC0DOCMCCRCR DISC0.DOCMCCRCR
    75 #define DISC0DOCMSPXR DISC0.DOCMSPXR
    76 #define DISC0DOCMSPYR DISC0.DOCMSPYR
    77 #define DISC0DOCMSZXR DISC0.DOCMSZXR
    78 #define DISC0DOCMSZYR DISC0.DOCMSZYR
    79 #define DISC0DOCMCRCIR DISC0.DOCMCRCIR
    80 #define DISC1DOCMCR DISC1.DOCMCR
    81 #define DISC1DOCMSTR DISC1.DOCMSTR
    82 #define DISC1DOCMCLSTR DISC1.DOCMCLSTR
    83 #define DISC1DOCMIENR DISC1.DOCMIENR
    84 #define DISC1DOCMPMR DISC1.DOCMPMR
    85 #define DISC1DOCMECRCR DISC1.DOCMECRCR
    86 #define DISC1DOCMCCRCR DISC1.DOCMCCRCR
    87 #define DISC1DOCMSPXR DISC1.DOCMSPXR
    88 #define DISC1DOCMSPYR DISC1.DOCMSPYR
    89 #define DISC1DOCMSZXR DISC1.DOCMSZXR
    90 #define DISC1DOCMSZYR DISC1.DOCMSZYR
    91 #define DISC1DOCMCRCIR DISC1.DOCMCRCIR
    92108/* <-SEC M1.10.1 */
     109/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     110/* <-QAC 0857 */
     111/* <-QAC 0639 */
    93112#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/dmac_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef DMAC_IODEFINE_H
    3030#define DMAC_IODEFINE_H
    3131/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3234/* ->SEC M1.10.1 : Not magic number */
    3335
    34 struct st_dmac
    35 {                                                          /* DMAC             */
    36 /* start of struct st_dmac_n */
    37     volatile uint32_t  N0SA_0;                                 /*  N0SA_0          */
    38     volatile uint32_t  N0DA_0;                                 /*  N0DA_0          */
    39     volatile uint32_t  N0TB_0;                                 /*  N0TB_0          */
    40     volatile uint32_t  N1SA_0;                                 /*  N1SA_0          */
    41     volatile uint32_t  N1DA_0;                                 /*  N1DA_0          */
    42     volatile uint32_t  N1TB_0;                                 /*  N1TB_0          */
    43     volatile uint32_t  CRSA_0;                                 /*  CRSA_0          */
    44     volatile uint32_t  CRDA_0;                                 /*  CRDA_0          */
    45     volatile uint32_t  CRTB_0;                                 /*  CRTB_0          */
    46     volatile uint32_t  CHSTAT_0;                               /*  CHSTAT_0        */
    47     volatile uint32_t  CHCTRL_0;                               /*  CHCTRL_0        */
    48     volatile uint32_t  CHCFG_0;                                /*  CHCFG_0         */
    49     volatile uint32_t  CHITVL_0;                               /*  CHITVL_0        */
    50     volatile uint32_t  CHEXT_0;                                /*  CHEXT_0         */
    51     volatile uint32_t  NXLA_0;                                 /*  NXLA_0          */
    52     volatile uint32_t  CRLA_0;                                 /*  CRLA_0          */
    53 /* end of struct st_dmac_n */
    54 /* start of struct st_dmac_n */
    55     volatile uint32_t  N0SA_1;                                 /*  N0SA_1          */
    56     volatile uint32_t  N0DA_1;                                 /*  N0DA_1          */
    57     volatile uint32_t  N0TB_1;                                 /*  N0TB_1          */
    58     volatile uint32_t  N1SA_1;                                 /*  N1SA_1          */
    59     volatile uint32_t  N1DA_1;                                 /*  N1DA_1          */
    60     volatile uint32_t  N1TB_1;                                 /*  N1TB_1          */
    61     volatile uint32_t  CRSA_1;                                 /*  CRSA_1          */
    62     volatile uint32_t  CRDA_1;                                 /*  CRDA_1          */
    63     volatile uint32_t  CRTB_1;                                 /*  CRTB_1          */
    64     volatile uint32_t  CHSTAT_1;                               /*  CHSTAT_1        */
    65     volatile uint32_t  CHCTRL_1;                               /*  CHCTRL_1        */
    66     volatile uint32_t  CHCFG_1;                                /*  CHCFG_1         */
    67     volatile uint32_t  CHITVL_1;                               /*  CHITVL_1        */
    68     volatile uint32_t  CHEXT_1;                                /*  CHEXT_1         */
    69     volatile uint32_t  NXLA_1;                                 /*  NXLA_1          */
    70     volatile uint32_t  CRLA_1;                                 /*  CRLA_1          */
    71 /* end of struct st_dmac_n */
    72 /* start of struct st_dmac_n */
    73     volatile uint32_t  N0SA_2;                                 /*  N0SA_2          */
    74     volatile uint32_t  N0DA_2;                                 /*  N0DA_2          */
    75     volatile uint32_t  N0TB_2;                                 /*  N0TB_2          */
    76     volatile uint32_t  N1SA_2;                                 /*  N1SA_2          */
    77     volatile uint32_t  N1DA_2;                                 /*  N1DA_2          */
    78     volatile uint32_t  N1TB_2;                                 /*  N1TB_2          */
    79     volatile uint32_t  CRSA_2;                                 /*  CRSA_2          */
    80     volatile uint32_t  CRDA_2;                                 /*  CRDA_2          */
    81     volatile uint32_t  CRTB_2;                                 /*  CRTB_2          */
    82     volatile uint32_t  CHSTAT_2;                               /*  CHSTAT_2        */
    83     volatile uint32_t  CHCTRL_2;                               /*  CHCTRL_2        */
    84     volatile uint32_t  CHCFG_2;                                /*  CHCFG_2         */
    85     volatile uint32_t  CHITVL_2;                               /*  CHITVL_2        */
    86     volatile uint32_t  CHEXT_2;                                /*  CHEXT_2         */
    87     volatile uint32_t  NXLA_2;                                 /*  NXLA_2          */
    88     volatile uint32_t  CRLA_2;                                 /*  CRLA_2          */
    89 /* end of struct st_dmac_n */
    90 /* start of struct st_dmac_n */
    91     volatile uint32_t  N0SA_3;                                 /*  N0SA_3          */
    92     volatile uint32_t  N0DA_3;                                 /*  N0DA_3          */
    93     volatile uint32_t  N0TB_3;                                 /*  N0TB_3          */
    94     volatile uint32_t  N1SA_3;                                 /*  N1SA_3          */
    95     volatile uint32_t  N1DA_3;                                 /*  N1DA_3          */
    96     volatile uint32_t  N1TB_3;                                 /*  N1TB_3          */
    97     volatile uint32_t  CRSA_3;                                 /*  CRSA_3          */
    98     volatile uint32_t  CRDA_3;                                 /*  CRDA_3          */
    99     volatile uint32_t  CRTB_3;                                 /*  CRTB_3          */
    100     volatile uint32_t  CHSTAT_3;                               /*  CHSTAT_3        */
    101     volatile uint32_t  CHCTRL_3;                               /*  CHCTRL_3        */
    102     volatile uint32_t  CHCFG_3;                                /*  CHCFG_3         */
    103     volatile uint32_t  CHITVL_3;                               /*  CHITVL_3        */
    104     volatile uint32_t  CHEXT_3;                                /*  CHEXT_3         */
    105     volatile uint32_t  NXLA_3;                                 /*  NXLA_3          */
    106     volatile uint32_t  CRLA_3;                                 /*  CRLA_3          */
    107 /* end of struct st_dmac_n */
    108 /* start of struct st_dmac_n */
    109     volatile uint32_t  N0SA_4;                                 /*  N0SA_4          */
    110     volatile uint32_t  N0DA_4;                                 /*  N0DA_4          */
    111     volatile uint32_t  N0TB_4;                                 /*  N0TB_4          */
    112     volatile uint32_t  N1SA_4;                                 /*  N1SA_4          */
    113     volatile uint32_t  N1DA_4;                                 /*  N1DA_4          */
    114     volatile uint32_t  N1TB_4;                                 /*  N1TB_4          */
    115     volatile uint32_t  CRSA_4;                                 /*  CRSA_4          */
    116     volatile uint32_t  CRDA_4;                                 /*  CRDA_4          */
    117     volatile uint32_t  CRTB_4;                                 /*  CRTB_4          */
    118     volatile uint32_t  CHSTAT_4;                               /*  CHSTAT_4        */
    119     volatile uint32_t  CHCTRL_4;                               /*  CHCTRL_4        */
    120     volatile uint32_t  CHCFG_4;                                /*  CHCFG_4         */
    121     volatile uint32_t  CHITVL_4;                               /*  CHITVL_4        */
    122     volatile uint32_t  CHEXT_4;                                /*  CHEXT_4         */
    123     volatile uint32_t  NXLA_4;                                 /*  NXLA_4          */
    124     volatile uint32_t  CRLA_4;                                 /*  CRLA_4          */
    125 /* end of struct st_dmac_n */
    126 /* start of struct st_dmac_n */
    127     volatile uint32_t  N0SA_5;                                 /*  N0SA_5          */
    128     volatile uint32_t  N0DA_5;                                 /*  N0DA_5          */
    129     volatile uint32_t  N0TB_5;                                 /*  N0TB_5          */
    130     volatile uint32_t  N1SA_5;                                 /*  N1SA_5          */
    131     volatile uint32_t  N1DA_5;                                 /*  N1DA_5          */
    132     volatile uint32_t  N1TB_5;                                 /*  N1TB_5          */
    133     volatile uint32_t  CRSA_5;                                 /*  CRSA_5          */
    134     volatile uint32_t  CRDA_5;                                 /*  CRDA_5          */
    135     volatile uint32_t  CRTB_5;                                 /*  CRTB_5          */
    136     volatile uint32_t  CHSTAT_5;                               /*  CHSTAT_5        */
    137     volatile uint32_t  CHCTRL_5;                               /*  CHCTRL_5        */
    138     volatile uint32_t  CHCFG_5;                                /*  CHCFG_5         */
    139     volatile uint32_t  CHITVL_5;                               /*  CHITVL_5        */
    140     volatile uint32_t  CHEXT_5;                                /*  CHEXT_5         */
    141     volatile uint32_t  NXLA_5;                                 /*  NXLA_5          */
    142     volatile uint32_t  CRLA_5;                                 /*  CRLA_5          */
    143 /* end of struct st_dmac_n */
    144 /* start of struct st_dmac_n */
    145     volatile uint32_t  N0SA_6;                                 /*  N0SA_6          */
    146     volatile uint32_t  N0DA_6;                                 /*  N0DA_6          */
    147     volatile uint32_t  N0TB_6;                                 /*  N0TB_6          */
    148     volatile uint32_t  N1SA_6;                                 /*  N1SA_6          */
    149     volatile uint32_t  N1DA_6;                                 /*  N1DA_6          */
    150     volatile uint32_t  N1TB_6;                                 /*  N1TB_6          */
    151     volatile uint32_t  CRSA_6;                                 /*  CRSA_6          */
    152     volatile uint32_t  CRDA_6;                                 /*  CRDA_6          */
    153     volatile uint32_t  CRTB_6;                                 /*  CRTB_6          */
    154     volatile uint32_t  CHSTAT_6;                               /*  CHSTAT_6        */
    155     volatile uint32_t  CHCTRL_6;                               /*  CHCTRL_6        */
    156     volatile uint32_t  CHCFG_6;                                /*  CHCFG_6         */
    157     volatile uint32_t  CHITVL_6;                               /*  CHITVL_6        */
    158     volatile uint32_t  CHEXT_6;                                /*  CHEXT_6         */
    159     volatile uint32_t  NXLA_6;                                 /*  NXLA_6          */
    160     volatile uint32_t  CRLA_6;                                 /*  CRLA_6          */
    161 /* end of struct st_dmac_n */
    162 /* start of struct st_dmac_n */
    163     volatile uint32_t  N0SA_7;                                 /*  N0SA_7          */
    164     volatile uint32_t  N0DA_7;                                 /*  N0DA_7          */
    165     volatile uint32_t  N0TB_7;                                 /*  N0TB_7          */
    166     volatile uint32_t  N1SA_7;                                 /*  N1SA_7          */
    167     volatile uint32_t  N1DA_7;                                 /*  N1DA_7          */
    168     volatile uint32_t  N1TB_7;                                 /*  N1TB_7          */
    169     volatile uint32_t  CRSA_7;                                 /*  CRSA_7          */
    170     volatile uint32_t  CRDA_7;                                 /*  CRDA_7          */
    171     volatile uint32_t  CRTB_7;                                 /*  CRTB_7          */
    172     volatile uint32_t  CHSTAT_7;                               /*  CHSTAT_7        */
    173     volatile uint32_t  CHCTRL_7;                               /*  CHCTRL_7        */
    174     volatile uint32_t  CHCFG_7;                                /*  CHCFG_7         */
    175     volatile uint32_t  CHITVL_7;                               /*  CHITVL_7        */
    176     volatile uint32_t  CHEXT_7;                                /*  CHEXT_7         */
    177     volatile uint32_t  NXLA_7;                                 /*  NXLA_7          */
    178     volatile uint32_t  CRLA_7;                                 /*  CRLA_7          */
    179 /* end of struct st_dmac_n */
    180     volatile uint8_t   dummy187[256];                          /*                  */
    181 /* start of struct st_dmaccommon_n */
    182     volatile uint32_t  DCTRL_0_7;                              /*  DCTRL_0_7       */
    183     volatile uint8_t   dummy188[12];                           /*                  */
    184     volatile uint32_t  DSTAT_EN_0_7;                           /*  DSTAT_EN_0_7    */
    185     volatile uint32_t  DSTAT_ER_0_7;                           /*  DSTAT_ER_0_7    */
    186     volatile uint32_t  DSTAT_END_0_7;                          /*  DSTAT_END_0_7   */
    187     volatile uint32_t  DSTAT_TC_0_7;                           /*  DSTAT_TC_0_7    */
    188     volatile uint32_t  DSTAT_SUS_0_7;                          /*  DSTAT_SUS_0_7   */
    189 /* end of struct st_dmaccommon_n */
    190     volatile uint8_t   dummy189[220];                          /*                  */
    191 /* start of struct st_dmac_n */
    192     volatile uint32_t  N0SA_8;                                 /*  N0SA_8          */
    193     volatile uint32_t  N0DA_8;                                 /*  N0DA_8          */
    194     volatile uint32_t  N0TB_8;                                 /*  N0TB_8          */
    195     volatile uint32_t  N1SA_8;                                 /*  N1SA_8          */
    196     volatile uint32_t  N1DA_8;                                 /*  N1DA_8          */
    197     volatile uint32_t  N1TB_8;                                 /*  N1TB_8          */
    198     volatile uint32_t  CRSA_8;                                 /*  CRSA_8          */
    199     volatile uint32_t  CRDA_8;                                 /*  CRDA_8          */
    200     volatile uint32_t  CRTB_8;                                 /*  CRTB_8          */
    201     volatile uint32_t  CHSTAT_8;                               /*  CHSTAT_8        */
    202     volatile uint32_t  CHCTRL_8;                               /*  CHCTRL_8        */
    203     volatile uint32_t  CHCFG_8;                                /*  CHCFG_8         */
    204     volatile uint32_t  CHITVL_8;                               /*  CHITVL_8        */
    205     volatile uint32_t  CHEXT_8;                                /*  CHEXT_8         */
    206     volatile uint32_t  NXLA_8;                                 /*  NXLA_8          */
    207     volatile uint32_t  CRLA_8;                                 /*  CRLA_8          */
    208 /* end of struct st_dmac_n */
    209 /* start of struct st_dmac_n */
    210     volatile uint32_t  N0SA_9;                                 /*  N0SA_9          */
    211     volatile uint32_t  N0DA_9;                                 /*  N0DA_9          */
    212     volatile uint32_t  N0TB_9;                                 /*  N0TB_9          */
    213     volatile uint32_t  N1SA_9;                                 /*  N1SA_9          */
    214     volatile uint32_t  N1DA_9;                                 /*  N1DA_9          */
    215     volatile uint32_t  N1TB_9;                                 /*  N1TB_9          */
    216     volatile uint32_t  CRSA_9;                                 /*  CRSA_9          */
    217     volatile uint32_t  CRDA_9;                                 /*  CRDA_9          */
    218     volatile uint32_t  CRTB_9;                                 /*  CRTB_9          */
    219     volatile uint32_t  CHSTAT_9;                               /*  CHSTAT_9        */
    220     volatile uint32_t  CHCTRL_9;                               /*  CHCTRL_9        */
    221     volatile uint32_t  CHCFG_9;                                /*  CHCFG_9         */
    222     volatile uint32_t  CHITVL_9;                               /*  CHITVL_9        */
    223     volatile uint32_t  CHEXT_9;                                /*  CHEXT_9         */
    224     volatile uint32_t  NXLA_9;                                 /*  NXLA_9          */
    225     volatile uint32_t  CRLA_9;                                 /*  CRLA_9          */
    226 /* end of struct st_dmac_n */
    227 /* start of struct st_dmac_n */
    228     volatile uint32_t  N0SA_10;                                /*  N0SA_10         */
    229     volatile uint32_t  N0DA_10;                                /*  N0DA_10         */
    230     volatile uint32_t  N0TB_10;                                /*  N0TB_10         */
    231     volatile uint32_t  N1SA_10;                                /*  N1SA_10         */
    232     volatile uint32_t  N1DA_10;                                /*  N1DA_10         */
    233     volatile uint32_t  N1TB_10;                                /*  N1TB_10         */
    234     volatile uint32_t  CRSA_10;                                /*  CRSA_10         */
    235     volatile uint32_t  CRDA_10;                                /*  CRDA_10         */
    236     volatile uint32_t  CRTB_10;                                /*  CRTB_10         */
    237     volatile uint32_t  CHSTAT_10;                              /*  CHSTAT_10       */
    238     volatile uint32_t  CHCTRL_10;                              /*  CHCTRL_10       */
    239     volatile uint32_t  CHCFG_10;                               /*  CHCFG_10        */
    240     volatile uint32_t  CHITVL_10;                              /*  CHITVL_10       */
    241     volatile uint32_t  CHEXT_10;                               /*  CHEXT_10        */
    242     volatile uint32_t  NXLA_10;                                /*  NXLA_10         */
    243     volatile uint32_t  CRLA_10;                                /*  CRLA_10         */
    244 /* end of struct st_dmac_n */
    245 /* start of struct st_dmac_n */
    246     volatile uint32_t  N0SA_11;                                /*  N0SA_11         */
    247     volatile uint32_t  N0DA_11;                                /*  N0DA_11         */
    248     volatile uint32_t  N0TB_11;                                /*  N0TB_11         */
    249     volatile uint32_t  N1SA_11;                                /*  N1SA_11         */
    250     volatile uint32_t  N1DA_11;                                /*  N1DA_11         */
    251     volatile uint32_t  N1TB_11;                                /*  N1TB_11         */
    252     volatile uint32_t  CRSA_11;                                /*  CRSA_11         */
    253     volatile uint32_t  CRDA_11;                                /*  CRDA_11         */
    254     volatile uint32_t  CRTB_11;                                /*  CRTB_11         */
    255     volatile uint32_t  CHSTAT_11;                              /*  CHSTAT_11       */
    256     volatile uint32_t  CHCTRL_11;                              /*  CHCTRL_11       */
    257     volatile uint32_t  CHCFG_11;                               /*  CHCFG_11        */
    258     volatile uint32_t  CHITVL_11;                              /*  CHITVL_11       */
    259     volatile uint32_t  CHEXT_11;                               /*  CHEXT_11        */
    260     volatile uint32_t  NXLA_11;                                /*  NXLA_11         */
    261     volatile uint32_t  CRLA_11;                                /*  CRLA_11         */
    262 /* end of struct st_dmac_n */
    263 /* start of struct st_dmac_n */
    264     volatile uint32_t  N0SA_12;                                /*  N0SA_12         */
    265     volatile uint32_t  N0DA_12;                                /*  N0DA_12         */
    266     volatile uint32_t  N0TB_12;                                /*  N0TB_12         */
    267     volatile uint32_t  N1SA_12;                                /*  N1SA_12         */
    268     volatile uint32_t  N1DA_12;                                /*  N1DA_12         */
    269     volatile uint32_t  N1TB_12;                                /*  N1TB_12         */
    270     volatile uint32_t  CRSA_12;                                /*  CRSA_12         */
    271     volatile uint32_t  CRDA_12;                                /*  CRDA_12         */
    272     volatile uint32_t  CRTB_12;                                /*  CRTB_12         */
    273     volatile uint32_t  CHSTAT_12;                              /*  CHSTAT_12       */
    274     volatile uint32_t  CHCTRL_12;                              /*  CHCTRL_12       */
    275     volatile uint32_t  CHCFG_12;                               /*  CHCFG_12        */
    276     volatile uint32_t  CHITVL_12;                              /*  CHITVL_12       */
    277     volatile uint32_t  CHEXT_12;                               /*  CHEXT_12        */
    278     volatile uint32_t  NXLA_12;                                /*  NXLA_12         */
    279     volatile uint32_t  CRLA_12;                                /*  CRLA_12         */
    280 /* end of struct st_dmac_n */
    281 /* start of struct st_dmac_n */
    282     volatile uint32_t  N0SA_13;                                /*  N0SA_13         */
    283     volatile uint32_t  N0DA_13;                                /*  N0DA_13         */
    284     volatile uint32_t  N0TB_13;                                /*  N0TB_13         */
    285     volatile uint32_t  N1SA_13;                                /*  N1SA_13         */
    286     volatile uint32_t  N1DA_13;                                /*  N1DA_13         */
    287     volatile uint32_t  N1TB_13;                                /*  N1TB_13         */
    288     volatile uint32_t  CRSA_13;                                /*  CRSA_13         */
    289     volatile uint32_t  CRDA_13;                                /*  CRDA_13         */
    290     volatile uint32_t  CRTB_13;                                /*  CRTB_13         */
    291     volatile uint32_t  CHSTAT_13;                              /*  CHSTAT_13       */
    292     volatile uint32_t  CHCTRL_13;                              /*  CHCTRL_13       */
    293     volatile uint32_t  CHCFG_13;                               /*  CHCFG_13        */
    294     volatile uint32_t  CHITVL_13;                              /*  CHITVL_13       */
    295     volatile uint32_t  CHEXT_13;                               /*  CHEXT_13        */
    296     volatile uint32_t  NXLA_13;                                /*  NXLA_13         */
    297     volatile uint32_t  CRLA_13;                                /*  CRLA_13         */
    298 /* end of struct st_dmac_n */
    299 /* start of struct st_dmac_n */
    300     volatile uint32_t  N0SA_14;                                /*  N0SA_14         */
    301     volatile uint32_t  N0DA_14;                                /*  N0DA_14         */
    302     volatile uint32_t  N0TB_14;                                /*  N0TB_14         */
    303     volatile uint32_t  N1SA_14;                                /*  N1SA_14         */
    304     volatile uint32_t  N1DA_14;                                /*  N1DA_14         */
    305     volatile uint32_t  N1TB_14;                                /*  N1TB_14         */
    306     volatile uint32_t  CRSA_14;                                /*  CRSA_14         */
    307     volatile uint32_t  CRDA_14;                                /*  CRDA_14         */
    308     volatile uint32_t  CRTB_14;                                /*  CRTB_14         */
    309     volatile uint32_t  CHSTAT_14;                              /*  CHSTAT_14       */
    310     volatile uint32_t  CHCTRL_14;                              /*  CHCTRL_14       */
    311     volatile uint32_t  CHCFG_14;                               /*  CHCFG_14        */
    312     volatile uint32_t  CHITVL_14;                              /*  CHITVL_14       */
    313     volatile uint32_t  CHEXT_14;                               /*  CHEXT_14        */
    314     volatile uint32_t  NXLA_14;                                /*  NXLA_14         */
    315     volatile uint32_t  CRLA_14;                                /*  CRLA_14         */
    316 /* end of struct st_dmac_n */
    317 /* start of struct st_dmac_n */
    318     volatile uint32_t  N0SA_15;                                /*  N0SA_15         */
    319     volatile uint32_t  N0DA_15;                                /*  N0DA_15         */
    320     volatile uint32_t  N0TB_15;                                /*  N0TB_15         */
    321     volatile uint32_t  N1SA_15;                                /*  N1SA_15         */
    322     volatile uint32_t  N1DA_15;                                /*  N1DA_15         */
    323     volatile uint32_t  N1TB_15;                                /*  N1TB_15         */
    324     volatile uint32_t  CRSA_15;                                /*  CRSA_15         */
    325     volatile uint32_t  CRDA_15;                                /*  CRDA_15         */
    326     volatile uint32_t  CRTB_15;                                /*  CRTB_15         */
    327     volatile uint32_t  CHSTAT_15;                              /*  CHSTAT_15       */
    328     volatile uint32_t  CHCTRL_15;                              /*  CHCTRL_15       */
    329     volatile uint32_t  CHCFG_15;                               /*  CHCFG_15        */
    330     volatile uint32_t  CHITVL_15;                              /*  CHITVL_15       */
    331     volatile uint32_t  CHEXT_15;                               /*  CHEXT_15        */
    332     volatile uint32_t  NXLA_15;                                /*  NXLA_15         */
    333     volatile uint32_t  CRLA_15;                                /*  CRLA_15         */
    334 /* end of struct st_dmac_n */
    335     volatile uint8_t   dummy190[256];                          /*                  */
    336 /* start of struct st_dmaccommon_n */
    337     volatile uint32_t  DCTRL_8_15;                             /*  DCTRL_8_15      */
    338     volatile uint8_t   dummy191[12];                           /*                  */
    339     volatile uint32_t  DSTAT_EN_8_15;                          /*  DSTAT_EN_8_15   */
    340     volatile uint32_t  DSTAT_ER_8_15;                          /*  DSTAT_ER_8_15   */
    341     volatile uint32_t  DSTAT_END_8_15;                         /*  DSTAT_END_8_15  */
    342     volatile uint32_t  DSTAT_TC_8_15;                          /*  DSTAT_TC_8_15   */
    343     volatile uint32_t  DSTAT_SUS_8_15;                         /*  DSTAT_SUS_8_15  */
    344 /* end of struct st_dmaccommon_n */
    345     volatile uint8_t   dummy192[350095580];                    /*                  */
    346     volatile uint32_t  DMARS0;                                 /*  DMARS0          */
    347     volatile uint32_t  DMARS1;                                 /*  DMARS1          */
    348     volatile uint32_t  DMARS2;                                 /*  DMARS2          */
    349     volatile uint32_t  DMARS3;                                 /*  DMARS3          */
    350     volatile uint32_t  DMARS4;                                 /*  DMARS4          */
    351     volatile uint32_t  DMARS5;                                 /*  DMARS5          */
    352     volatile uint32_t  DMARS6;                                 /*  DMARS6          */
    353     volatile uint32_t  DMARS7;                                 /*  DMARS7          */
    354 };
    355 
    356 
    357 struct st_dmaccommon_n
    358 {
    359     volatile uint32_t  DCTRL_0_7;                              /*  DCTRL_0_7       */
    360     volatile uint8_t   dummy1[12];                             /*                  */
    361     volatile uint32_t  DSTAT_EN_0_7;                           /*  DSTAT_EN_0_7    */
    362     volatile uint32_t  DSTAT_ER_0_7;                           /*  DSTAT_ER_0_7    */
    363     volatile uint32_t  DSTAT_END_0_7;                          /*  DSTAT_END_0_7   */
    364     volatile uint32_t  DSTAT_TC_0_7;                           /*  DSTAT_TC_0_7    */
    365     volatile uint32_t  DSTAT_SUS_0_7;                          /*  DSTAT_SUS_0_7   */
    366 };
    367 
    368 
    369 struct st_dmac_n
    370 {
    371     volatile uint32_t  N0SA_n;                                 /*  N0SA_n          */
    372     volatile uint32_t  N0DA_n;                                 /*  N0DA_n          */
    373     volatile uint32_t  N0TB_n;                                 /*  N0TB_n          */
    374     volatile uint32_t  N1SA_n;                                 /*  N1SA_n          */
    375     volatile uint32_t  N1DA_n;                                 /*  N1DA_n          */
    376     volatile uint32_t  N1TB_n;                                 /*  N1TB_n          */
    377     volatile uint32_t  CRSA_n;                                 /*  CRSA_n          */
    378     volatile uint32_t  CRDA_n;                                 /*  CRDA_n          */
    379     volatile uint32_t  CRTB_n;                                 /*  CRTB_n          */
    380     volatile uint32_t  CHSTAT_n;                               /*  CHSTAT_n        */
    381     volatile uint32_t  CHCTRL_n;                               /*  CHCTRL_n        */
    382     volatile uint32_t  CHCFG_n;                                /*  CHCFG_n         */
    383     volatile uint32_t  CHITVL_n;                               /*  CHITVL_n        */
    384     volatile uint32_t  CHEXT_n;                                /*  CHEXT_n         */
    385     volatile uint32_t  NXLA_n;                                 /*  NXLA_n          */
    386     volatile uint32_t  CRLA_n;                                 /*  CRLA_n          */
    387 };
    388 
    389 
     36
     37
     38/* Channel array defines of DMACmm */
     39#define DMACmm_COUNT  (8)
     40#define DMACmm_ADDRESS_LIST \
     41{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     42    &DMAC01, &DMAC23, &DMAC45, &DMAC67, &DMAC89, &DMAC1011, &DMAC1213, &DMAC1415 \
     43}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     44#define DMAC01    (*(struct st_dmars_mm *)&DMAC.DMARS0)  /* DMAC0-1   */
     45#define DMAC23    (*(struct st_dmars_mm *)&DMAC.DMARS1)  /* DMAC2-3   */
     46#define DMAC45    (*(struct st_dmars_mm *)&DMAC.DMARS2)  /* DMAC4-5   */
     47#define DMAC67    (*(struct st_dmars_mm *)&DMAC.DMARS3)  /* DMAC6-7   */
     48#define DMAC89    (*(struct st_dmars_mm *)&DMAC.DMARS4)  /* DMAC8-9   */
     49#define DMAC1011  (*(struct st_dmars_mm *)&DMAC.DMARS5)  /* DMAC10-11 */
     50#define DMAC1213  (*(struct st_dmars_mm *)&DMAC.DMARS6)  /* DMAC12-13 */
     51#define DMAC1415  (*(struct st_dmars_mm *)&DMAC.DMARS7)  /* DMAC14-15 */
     52
     53
     54/*(Sample) value = DMACmm[ channel / 2 ]->DMARS; */
    39055#define DMAC    (*(struct st_dmac    *)0xE8200000uL) /* DMAC */
    39156
    39257
    393 /* Start of channnel array defines of DMAC */
    394 
    395 /* Channnel array defines of DMACn */
     58/* Start of channel array defines of DMAC */
     59
     60/* Channel array defines of DMACn */
    39661/*(Sample) value = DMACn[ channel ]->N0SA_n; */
    397 #define DMACn_COUNT  16
     62#define DMACn_COUNT  (16)
    39863#define DMACn_ADDRESS_LIST \
    39964{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    … …  
    41984
    42085
    421 /* Channnel array defines of DMACnn */
     86/* Channel array defines of DMACnn */
    42287/*(Sample) value = DMACnn[ channel / 8 ]->DCTRL_0_7; */
    423 #define DMACnn_COUNT  2
     88#define DMACnn_COUNT  (2)
    42489#define DMACnn_ADDRESS_LIST \
    42590{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    … …  
    42994#define DMAC815 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_8_15)    /* DMAC815 */
    43095
    431 
    432 /* Channnel array defines of DMACmm */
    433 /*(Sample) value = DMACmm[ channel / 2 ]->DMARS; */
    434 struct st_dmars_mm
     96/* End of channel array defines of DMAC */
     97
     98
     99#define DMACN0SA_0 (DMAC.N0SA_0)
     100#define DMACN0DA_0 (DMAC.N0DA_0)
     101#define DMACN0TB_0 (DMAC.N0TB_0)
     102#define DMACN1SA_0 (DMAC.N1SA_0)
     103#define DMACN1DA_0 (DMAC.N1DA_0)
     104#define DMACN1TB_0 (DMAC.N1TB_0)
     105#define DMACCRSA_0 (DMAC.CRSA_0)
     106#define DMACCRDA_0 (DMAC.CRDA_0)
     107#define DMACCRTB_0 (DMAC.CRTB_0)
     108#define DMACCHSTAT_0 (DMAC.CHSTAT_0)
     109#define DMACCHCTRL_0 (DMAC.CHCTRL_0)
     110#define DMACCHCFG_0 (DMAC.CHCFG_0)
     111#define DMACCHITVL_0 (DMAC.CHITVL_0)
     112#define DMACCHEXT_0 (DMAC.CHEXT_0)
     113#define DMACNXLA_0 (DMAC.NXLA_0)
     114#define DMACCRLA_0 (DMAC.CRLA_0)
     115#define DMACN0SA_1 (DMAC.N0SA_1)
     116#define DMACN0DA_1 (DMAC.N0DA_1)
     117#define DMACN0TB_1 (DMAC.N0TB_1)
     118#define DMACN1SA_1 (DMAC.N1SA_1)
     119#define DMACN1DA_1 (DMAC.N1DA_1)
     120#define DMACN1TB_1 (DMAC.N1TB_1)
     121#define DMACCRSA_1 (DMAC.CRSA_1)
     122#define DMACCRDA_1 (DMAC.CRDA_1)
     123#define DMACCRTB_1 (DMAC.CRTB_1)
     124#define DMACCHSTAT_1 (DMAC.CHSTAT_1)
     125#define DMACCHCTRL_1 (DMAC.CHCTRL_1)
     126#define DMACCHCFG_1 (DMAC.CHCFG_1)
     127#define DMACCHITVL_1 (DMAC.CHITVL_1)
     128#define DMACCHEXT_1 (DMAC.CHEXT_1)
     129#define DMACNXLA_1 (DMAC.NXLA_1)
     130#define DMACCRLA_1 (DMAC.CRLA_1)
     131#define DMACN0SA_2 (DMAC.N0SA_2)
     132#define DMACN0DA_2 (DMAC.N0DA_2)
     133#define DMACN0TB_2 (DMAC.N0TB_2)
     134#define DMACN1SA_2 (DMAC.N1SA_2)
     135#define DMACN1DA_2 (DMAC.N1DA_2)
     136#define DMACN1TB_2 (DMAC.N1TB_2)
     137#define DMACCRSA_2 (DMAC.CRSA_2)
     138#define DMACCRDA_2 (DMAC.CRDA_2)
     139#define DMACCRTB_2 (DMAC.CRTB_2)
     140#define DMACCHSTAT_2 (DMAC.CHSTAT_2)
     141#define DMACCHCTRL_2 (DMAC.CHCTRL_2)
     142#define DMACCHCFG_2 (DMAC.CHCFG_2)
     143#define DMACCHITVL_2 (DMAC.CHITVL_2)
     144#define DMACCHEXT_2 (DMAC.CHEXT_2)
     145#define DMACNXLA_2 (DMAC.NXLA_2)
     146#define DMACCRLA_2 (DMAC.CRLA_2)
     147#define DMACN0SA_3 (DMAC.N0SA_3)
     148#define DMACN0DA_3 (DMAC.N0DA_3)
     149#define DMACN0TB_3 (DMAC.N0TB_3)
     150#define DMACN1SA_3 (DMAC.N1SA_3)
     151#define DMACN1DA_3 (DMAC.N1DA_3)
     152#define DMACN1TB_3 (DMAC.N1TB_3)
     153#define DMACCRSA_3 (DMAC.CRSA_3)
     154#define DMACCRDA_3 (DMAC.CRDA_3)
     155#define DMACCRTB_3 (DMAC.CRTB_3)
     156#define DMACCHSTAT_3 (DMAC.CHSTAT_3)
     157#define DMACCHCTRL_3 (DMAC.CHCTRL_3)
     158#define DMACCHCFG_3 (DMAC.CHCFG_3)
     159#define DMACCHITVL_3 (DMAC.CHITVL_3)
     160#define DMACCHEXT_3 (DMAC.CHEXT_3)
     161#define DMACNXLA_3 (DMAC.NXLA_3)
     162#define DMACCRLA_3 (DMAC.CRLA_3)
     163#define DMACN0SA_4 (DMAC.N0SA_4)
     164#define DMACN0DA_4 (DMAC.N0DA_4)
     165#define DMACN0TB_4 (DMAC.N0TB_4)
     166#define DMACN1SA_4 (DMAC.N1SA_4)
     167#define DMACN1DA_4 (DMAC.N1DA_4)
     168#define DMACN1TB_4 (DMAC.N1TB_4)
     169#define DMACCRSA_4 (DMAC.CRSA_4)
     170#define DMACCRDA_4 (DMAC.CRDA_4)
     171#define DMACCRTB_4 (DMAC.CRTB_4)
     172#define DMACCHSTAT_4 (DMAC.CHSTAT_4)
     173#define DMACCHCTRL_4 (DMAC.CHCTRL_4)
     174#define DMACCHCFG_4 (DMAC.CHCFG_4)
     175#define DMACCHITVL_4 (DMAC.CHITVL_4)
     176#define DMACCHEXT_4 (DMAC.CHEXT_4)
     177#define DMACNXLA_4 (DMAC.NXLA_4)
     178#define DMACCRLA_4 (DMAC.CRLA_4)
     179#define DMACN0SA_5 (DMAC.N0SA_5)
     180#define DMACN0DA_5 (DMAC.N0DA_5)
     181#define DMACN0TB_5 (DMAC.N0TB_5)
     182#define DMACN1SA_5 (DMAC.N1SA_5)
     183#define DMACN1DA_5 (DMAC.N1DA_5)
     184#define DMACN1TB_5 (DMAC.N1TB_5)
     185#define DMACCRSA_5 (DMAC.CRSA_5)
     186#define DMACCRDA_5 (DMAC.CRDA_5)
     187#define DMACCRTB_5 (DMAC.CRTB_5)
     188#define DMACCHSTAT_5 (DMAC.CHSTAT_5)
     189#define DMACCHCTRL_5 (DMAC.CHCTRL_5)
     190#define DMACCHCFG_5 (DMAC.CHCFG_5)
     191#define DMACCHITVL_5 (DMAC.CHITVL_5)
     192#define DMACCHEXT_5 (DMAC.CHEXT_5)
     193#define DMACNXLA_5 (DMAC.NXLA_5)
     194#define DMACCRLA_5 (DMAC.CRLA_5)
     195#define DMACN0SA_6 (DMAC.N0SA_6)
     196#define DMACN0DA_6 (DMAC.N0DA_6)
     197#define DMACN0TB_6 (DMAC.N0TB_6)
     198#define DMACN1SA_6 (DMAC.N1SA_6)
     199#define DMACN1DA_6 (DMAC.N1DA_6)
     200#define DMACN1TB_6 (DMAC.N1TB_6)
     201#define DMACCRSA_6 (DMAC.CRSA_6)
     202#define DMACCRDA_6 (DMAC.CRDA_6)
     203#define DMACCRTB_6 (DMAC.CRTB_6)
     204#define DMACCHSTAT_6 (DMAC.CHSTAT_6)
     205#define DMACCHCTRL_6 (DMAC.CHCTRL_6)
     206#define DMACCHCFG_6 (DMAC.CHCFG_6)
     207#define DMACCHITVL_6 (DMAC.CHITVL_6)
     208#define DMACCHEXT_6 (DMAC.CHEXT_6)
     209#define DMACNXLA_6 (DMAC.NXLA_6)
     210#define DMACCRLA_6 (DMAC.CRLA_6)
     211#define DMACN0SA_7 (DMAC.N0SA_7)
     212#define DMACN0DA_7 (DMAC.N0DA_7)
     213#define DMACN0TB_7 (DMAC.N0TB_7)
     214#define DMACN1SA_7 (DMAC.N1SA_7)
     215#define DMACN1DA_7 (DMAC.N1DA_7)
     216#define DMACN1TB_7 (DMAC.N1TB_7)
     217#define DMACCRSA_7 (DMAC.CRSA_7)
     218#define DMACCRDA_7 (DMAC.CRDA_7)
     219#define DMACCRTB_7 (DMAC.CRTB_7)
     220#define DMACCHSTAT_7 (DMAC.CHSTAT_7)
     221#define DMACCHCTRL_7 (DMAC.CHCTRL_7)
     222#define DMACCHCFG_7 (DMAC.CHCFG_7)
     223#define DMACCHITVL_7 (DMAC.CHITVL_7)
     224#define DMACCHEXT_7 (DMAC.CHEXT_7)
     225#define DMACNXLA_7 (DMAC.NXLA_7)
     226#define DMACCRLA_7 (DMAC.CRLA_7)
     227#define DMACDCTRL_0_7 (DMAC.DCTRL_0_7)
     228#define DMACDSTAT_EN_0_7 (DMAC.DSTAT_EN_0_7)
     229#define DMACDSTAT_ER_0_7 (DMAC.DSTAT_ER_0_7)
     230#define DMACDSTAT_END_0_7 (DMAC.DSTAT_END_0_7)
     231#define DMACDSTAT_TC_0_7 (DMAC.DSTAT_TC_0_7)
     232#define DMACDSTAT_SUS_0_7 (DMAC.DSTAT_SUS_0_7)
     233#define DMACN0SA_8 (DMAC.N0SA_8)
     234#define DMACN0DA_8 (DMAC.N0DA_8)
     235#define DMACN0TB_8 (DMAC.N0TB_8)
     236#define DMACN1SA_8 (DMAC.N1SA_8)
     237#define DMACN1DA_8 (DMAC.N1DA_8)
     238#define DMACN1TB_8 (DMAC.N1TB_8)
     239#define DMACCRSA_8 (DMAC.CRSA_8)
     240#define DMACCRDA_8 (DMAC.CRDA_8)
     241#define DMACCRTB_8 (DMAC.CRTB_8)
     242#define DMACCHSTAT_8 (DMAC.CHSTAT_8)
     243#define DMACCHCTRL_8 (DMAC.CHCTRL_8)
     244#define DMACCHCFG_8 (DMAC.CHCFG_8)
     245#define DMACCHITVL_8 (DMAC.CHITVL_8)
     246#define DMACCHEXT_8 (DMAC.CHEXT_8)
     247#define DMACNXLA_8 (DMAC.NXLA_8)
     248#define DMACCRLA_8 (DMAC.CRLA_8)
     249#define DMACN0SA_9 (DMAC.N0SA_9)
     250#define DMACN0DA_9 (DMAC.N0DA_9)
     251#define DMACN0TB_9 (DMAC.N0TB_9)
     252#define DMACN1SA_9 (DMAC.N1SA_9)
     253#define DMACN1DA_9 (DMAC.N1DA_9)
     254#define DMACN1TB_9 (DMAC.N1TB_9)
     255#define DMACCRSA_9 (DMAC.CRSA_9)
     256#define DMACCRDA_9 (DMAC.CRDA_9)
     257#define DMACCRTB_9 (DMAC.CRTB_9)
     258#define DMACCHSTAT_9 (DMAC.CHSTAT_9)
     259#define DMACCHCTRL_9 (DMAC.CHCTRL_9)
     260#define DMACCHCFG_9 (DMAC.CHCFG_9)
     261#define DMACCHITVL_9 (DMAC.CHITVL_9)
     262#define DMACCHEXT_9 (DMAC.CHEXT_9)
     263#define DMACNXLA_9 (DMAC.NXLA_9)
     264#define DMACCRLA_9 (DMAC.CRLA_9)
     265#define DMACN0SA_10 (DMAC.N0SA_10)
     266#define DMACN0DA_10 (DMAC.N0DA_10)
     267#define DMACN0TB_10 (DMAC.N0TB_10)
     268#define DMACN1SA_10 (DMAC.N1SA_10)
     269#define DMACN1DA_10 (DMAC.N1DA_10)
     270#define DMACN1TB_10 (DMAC.N1TB_10)
     271#define DMACCRSA_10 (DMAC.CRSA_10)
     272#define DMACCRDA_10 (DMAC.CRDA_10)
     273#define DMACCRTB_10 (DMAC.CRTB_10)
     274#define DMACCHSTAT_10 (DMAC.CHSTAT_10)
     275#define DMACCHCTRL_10 (DMAC.CHCTRL_10)
     276#define DMACCHCFG_10 (DMAC.CHCFG_10)
     277#define DMACCHITVL_10 (DMAC.CHITVL_10)
     278#define DMACCHEXT_10 (DMAC.CHEXT_10)
     279#define DMACNXLA_10 (DMAC.NXLA_10)
     280#define DMACCRLA_10 (DMAC.CRLA_10)
     281#define DMACN0SA_11 (DMAC.N0SA_11)
     282#define DMACN0DA_11 (DMAC.N0DA_11)
     283#define DMACN0TB_11 (DMAC.N0TB_11)
     284#define DMACN1SA_11 (DMAC.N1SA_11)
     285#define DMACN1DA_11 (DMAC.N1DA_11)
     286#define DMACN1TB_11 (DMAC.N1TB_11)
     287#define DMACCRSA_11 (DMAC.CRSA_11)
     288#define DMACCRDA_11 (DMAC.CRDA_11)
     289#define DMACCRTB_11 (DMAC.CRTB_11)
     290#define DMACCHSTAT_11 (DMAC.CHSTAT_11)
     291#define DMACCHCTRL_11 (DMAC.CHCTRL_11)
     292#define DMACCHCFG_11 (DMAC.CHCFG_11)
     293#define DMACCHITVL_11 (DMAC.CHITVL_11)
     294#define DMACCHEXT_11 (DMAC.CHEXT_11)
     295#define DMACNXLA_11 (DMAC.NXLA_11)
     296#define DMACCRLA_11 (DMAC.CRLA_11)
     297#define DMACN0SA_12 (DMAC.N0SA_12)
     298#define DMACN0DA_12 (DMAC.N0DA_12)
     299#define DMACN0TB_12 (DMAC.N0TB_12)
     300#define DMACN1SA_12 (DMAC.N1SA_12)
     301#define DMACN1DA_12 (DMAC.N1DA_12)
     302#define DMACN1TB_12 (DMAC.N1TB_12)
     303#define DMACCRSA_12 (DMAC.CRSA_12)
     304#define DMACCRDA_12 (DMAC.CRDA_12)
     305#define DMACCRTB_12 (DMAC.CRTB_12)
     306#define DMACCHSTAT_12 (DMAC.CHSTAT_12)
     307#define DMACCHCTRL_12 (DMAC.CHCTRL_12)
     308#define DMACCHCFG_12 (DMAC.CHCFG_12)
     309#define DMACCHITVL_12 (DMAC.CHITVL_12)
     310#define DMACCHEXT_12 (DMAC.CHEXT_12)
     311#define DMACNXLA_12 (DMAC.NXLA_12)
     312#define DMACCRLA_12 (DMAC.CRLA_12)
     313#define DMACN0SA_13 (DMAC.N0SA_13)
     314#define DMACN0DA_13 (DMAC.N0DA_13)
     315#define DMACN0TB_13 (DMAC.N0TB_13)
     316#define DMACN1SA_13 (DMAC.N1SA_13)
     317#define DMACN1DA_13 (DMAC.N1DA_13)
     318#define DMACN1TB_13 (DMAC.N1TB_13)
     319#define DMACCRSA_13 (DMAC.CRSA_13)
     320#define DMACCRDA_13 (DMAC.CRDA_13)
     321#define DMACCRTB_13 (DMAC.CRTB_13)
     322#define DMACCHSTAT_13 (DMAC.CHSTAT_13)
     323#define DMACCHCTRL_13 (DMAC.CHCTRL_13)
     324#define DMACCHCFG_13 (DMAC.CHCFG_13)
     325#define DMACCHITVL_13 (DMAC.CHITVL_13)
     326#define DMACCHEXT_13 (DMAC.CHEXT_13)
     327#define DMACNXLA_13 (DMAC.NXLA_13)
     328#define DMACCRLA_13 (DMAC.CRLA_13)
     329#define DMACN0SA_14 (DMAC.N0SA_14)
     330#define DMACN0DA_14 (DMAC.N0DA_14)
     331#define DMACN0TB_14 (DMAC.N0TB_14)
     332#define DMACN1SA_14 (DMAC.N1SA_14)
     333#define DMACN1DA_14 (DMAC.N1DA_14)
     334#define DMACN1TB_14 (DMAC.N1TB_14)
     335#define DMACCRSA_14 (DMAC.CRSA_14)
     336#define DMACCRDA_14 (DMAC.CRDA_14)
     337#define DMACCRTB_14 (DMAC.CRTB_14)
     338#define DMACCHSTAT_14 (DMAC.CHSTAT_14)
     339#define DMACCHCTRL_14 (DMAC.CHCTRL_14)
     340#define DMACCHCFG_14 (DMAC.CHCFG_14)
     341#define DMACCHITVL_14 (DMAC.CHITVL_14)
     342#define DMACCHEXT_14 (DMAC.CHEXT_14)
     343#define DMACNXLA_14 (DMAC.NXLA_14)
     344#define DMACCRLA_14 (DMAC.CRLA_14)
     345#define DMACN0SA_15 (DMAC.N0SA_15)
     346#define DMACN0DA_15 (DMAC.N0DA_15)
     347#define DMACN0TB_15 (DMAC.N0TB_15)
     348#define DMACN1SA_15 (DMAC.N1SA_15)
     349#define DMACN1DA_15 (DMAC.N1DA_15)
     350#define DMACN1TB_15 (DMAC.N1TB_15)
     351#define DMACCRSA_15 (DMAC.CRSA_15)
     352#define DMACCRDA_15 (DMAC.CRDA_15)
     353#define DMACCRTB_15 (DMAC.CRTB_15)
     354#define DMACCHSTAT_15 (DMAC.CHSTAT_15)
     355#define DMACCHCTRL_15 (DMAC.CHCTRL_15)
     356#define DMACCHCFG_15 (DMAC.CHCFG_15)
     357#define DMACCHITVL_15 (DMAC.CHITVL_15)
     358#define DMACCHEXT_15 (DMAC.CHEXT_15)
     359#define DMACNXLA_15 (DMAC.NXLA_15)
     360#define DMACCRLA_15 (DMAC.CRLA_15)
     361#define DMACDCTRL_8_15 (DMAC.DCTRL_8_15)
     362#define DMACDSTAT_EN_8_15 (DMAC.DSTAT_EN_8_15)
     363#define DMACDSTAT_ER_8_15 (DMAC.DSTAT_ER_8_15)
     364#define DMACDSTAT_END_8_15 (DMAC.DSTAT_END_8_15)
     365#define DMACDSTAT_TC_8_15 (DMAC.DSTAT_TC_8_15)
     366#define DMACDSTAT_SUS_8_15 (DMAC.DSTAT_SUS_8_15)
     367#define DMACDMARS0 (DMAC.DMARS0)
     368#define DMACDMARS1 (DMAC.DMARS1)
     369#define DMACDMARS2 (DMAC.DMARS2)
     370#define DMACDMARS3 (DMAC.DMARS3)
     371#define DMACDMARS4 (DMAC.DMARS4)
     372#define DMACDMARS5 (DMAC.DMARS5)
     373#define DMACDMARS6 (DMAC.DMARS6)
     374#define DMACDMARS7 (DMAC.DMARS7)
     375
     376
     377typedef struct st_dmars_mm
    435378{
    436     uint32_t       DMARS;                                        /*  DMARS     */
    437 };
    438 #define DMACmm_COUNT  8
    439 #define DMACmm_ADDRESS_LIST \
    440 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    441     &DMAC01, &DMAC23, &DMAC45, &DMAC67, &DMAC89, &DMAC1011, &DMAC1213, &DMAC1415 \
    442 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    443 #define DMAC01    (*(struct st_dmars_mm *)&DMAC.DMARS0)  /* DMAC0-1   */
    444 #define DMAC23    (*(struct st_dmars_mm *)&DMAC.DMARS1)  /* DMAC2-3   */
    445 #define DMAC45    (*(struct st_dmars_mm *)&DMAC.DMARS2)  /* DMAC4-5   */
    446 #define DMAC67    (*(struct st_dmars_mm *)&DMAC.DMARS3)  /* DMAC6-7   */
    447 #define DMAC89    (*(struct st_dmars_mm *)&DMAC.DMARS4)  /* DMAC8-9   */
    448 #define DMAC1011  (*(struct st_dmars_mm *)&DMAC.DMARS5)  /* DMAC10-11 */
    449 #define DMAC1213  (*(struct st_dmars_mm *)&DMAC.DMARS6)  /* DMAC12-13 */
    450 #define DMAC1415  (*(struct st_dmars_mm *)&DMAC.DMARS7)  /* DMAC14-15 */
    451 
    452 /* End of channnel array defines of DMAC */
    453 
    454 
    455 #define DMACN0SA_0 DMAC.N0SA_0
    456 #define DMACN0DA_0 DMAC.N0DA_0
    457 #define DMACN0TB_0 DMAC.N0TB_0
    458 #define DMACN1SA_0 DMAC.N1SA_0
    459 #define DMACN1DA_0 DMAC.N1DA_0
    460 #define DMACN1TB_0 DMAC.N1TB_0
    461 #define DMACCRSA_0 DMAC.CRSA_0
    462 #define DMACCRDA_0 DMAC.CRDA_0
    463 #define DMACCRTB_0 DMAC.CRTB_0
    464 #define DMACCHSTAT_0 DMAC.CHSTAT_0
    465 #define DMACCHCTRL_0 DMAC.CHCTRL_0
    466 #define DMACCHCFG_0 DMAC.CHCFG_0
    467 #define DMACCHITVL_0 DMAC.CHITVL_0
    468 #define DMACCHEXT_0 DMAC.CHEXT_0
    469 #define DMACNXLA_0 DMAC.NXLA_0
    470 #define DMACCRLA_0 DMAC.CRLA_0
    471 #define DMACN0SA_1 DMAC.N0SA_1
    472 #define DMACN0DA_1 DMAC.N0DA_1
    473 #define DMACN0TB_1 DMAC.N0TB_1
    474 #define DMACN1SA_1 DMAC.N1SA_1
    475 #define DMACN1DA_1 DMAC.N1DA_1
    476 #define DMACN1TB_1 DMAC.N1TB_1
    477 #define DMACCRSA_1 DMAC.CRSA_1
    478 #define DMACCRDA_1 DMAC.CRDA_1
    479 #define DMACCRTB_1 DMAC.CRTB_1
    480 #define DMACCHSTAT_1 DMAC.CHSTAT_1
    481 #define DMACCHCTRL_1 DMAC.CHCTRL_1
    482 #define DMACCHCFG_1 DMAC.CHCFG_1
    483 #define DMACCHITVL_1 DMAC.CHITVL_1
    484 #define DMACCHEXT_1 DMAC.CHEXT_1
    485 #define DMACNXLA_1 DMAC.NXLA_1
    486 #define DMACCRLA_1 DMAC.CRLA_1
    487 #define DMACN0SA_2 DMAC.N0SA_2
    488 #define DMACN0DA_2 DMAC.N0DA_2
    489 #define DMACN0TB_2 DMAC.N0TB_2
    490 #define DMACN1SA_2 DMAC.N1SA_2
    491 #define DMACN1DA_2 DMAC.N1DA_2
    492 #define DMACN1TB_2 DMAC.N1TB_2
    493 #define DMACCRSA_2 DMAC.CRSA_2
    494 #define DMACCRDA_2 DMAC.CRDA_2
    495 #define DMACCRTB_2 DMAC.CRTB_2
    496 #define DMACCHSTAT_2 DMAC.CHSTAT_2
    497 #define DMACCHCTRL_2 DMAC.CHCTRL_2
    498 #define DMACCHCFG_2 DMAC.CHCFG_2
    499 #define DMACCHITVL_2 DMAC.CHITVL_2
    500 #define DMACCHEXT_2 DMAC.CHEXT_2
    501 #define DMACNXLA_2 DMAC.NXLA_2
    502 #define DMACCRLA_2 DMAC.CRLA_2
    503 #define DMACN0SA_3 DMAC.N0SA_3
    504 #define DMACN0DA_3 DMAC.N0DA_3
    505 #define DMACN0TB_3 DMAC.N0TB_3
    506 #define DMACN1SA_3 DMAC.N1SA_3
    507 #define DMACN1DA_3 DMAC.N1DA_3
    508 #define DMACN1TB_3 DMAC.N1TB_3
    509 #define DMACCRSA_3 DMAC.CRSA_3
    510 #define DMACCRDA_3 DMAC.CRDA_3
    511 #define DMACCRTB_3 DMAC.CRTB_3
    512 #define DMACCHSTAT_3 DMAC.CHSTAT_3
    513 #define DMACCHCTRL_3 DMAC.CHCTRL_3
    514 #define DMACCHCFG_3 DMAC.CHCFG_3
    515 #define DMACCHITVL_3 DMAC.CHITVL_3
    516 #define DMACCHEXT_3 DMAC.CHEXT_3
    517 #define DMACNXLA_3 DMAC.NXLA_3
    518 #define DMACCRLA_3 DMAC.CRLA_3
    519 #define DMACN0SA_4 DMAC.N0SA_4
    520 #define DMACN0DA_4 DMAC.N0DA_4
    521 #define DMACN0TB_4 DMAC.N0TB_4
    522 #define DMACN1SA_4 DMAC.N1SA_4
    523 #define DMACN1DA_4 DMAC.N1DA_4
    524 #define DMACN1TB_4 DMAC.N1TB_4
    525 #define DMACCRSA_4 DMAC.CRSA_4
    526 #define DMACCRDA_4 DMAC.CRDA_4
    527 #define DMACCRTB_4 DMAC.CRTB_4
    528 #define DMACCHSTAT_4 DMAC.CHSTAT_4
    529 #define DMACCHCTRL_4 DMAC.CHCTRL_4
    530 #define DMACCHCFG_4 DMAC.CHCFG_4
    531 #define DMACCHITVL_4 DMAC.CHITVL_4
    532 #define DMACCHEXT_4 DMAC.CHEXT_4
    533 #define DMACNXLA_4 DMAC.NXLA_4
    534 #define DMACCRLA_4 DMAC.CRLA_4
    535 #define DMACN0SA_5 DMAC.N0SA_5
    536 #define DMACN0DA_5 DMAC.N0DA_5
    537 #define DMACN0TB_5 DMAC.N0TB_5
    538 #define DMACN1SA_5 DMAC.N1SA_5
    539 #define DMACN1DA_5 DMAC.N1DA_5
    540 #define DMACN1TB_5 DMAC.N1TB_5
    541 #define DMACCRSA_5 DMAC.CRSA_5
    542 #define DMACCRDA_5 DMAC.CRDA_5
    543 #define DMACCRTB_5 DMAC.CRTB_5
    544 #define DMACCHSTAT_5 DMAC.CHSTAT_5
    545 #define DMACCHCTRL_5 DMAC.CHCTRL_5
    546 #define DMACCHCFG_5 DMAC.CHCFG_5
    547 #define DMACCHITVL_5 DMAC.CHITVL_5
    548 #define DMACCHEXT_5 DMAC.CHEXT_5
    549 #define DMACNXLA_5 DMAC.NXLA_5
    550 #define DMACCRLA_5 DMAC.CRLA_5
    551 #define DMACN0SA_6 DMAC.N0SA_6
    552 #define DMACN0DA_6 DMAC.N0DA_6
    553 #define DMACN0TB_6 DMAC.N0TB_6
    554 #define DMACN1SA_6 DMAC.N1SA_6
    555 #define DMACN1DA_6 DMAC.N1DA_6
    556 #define DMACN1TB_6 DMAC.N1TB_6
    557 #define DMACCRSA_6 DMAC.CRSA_6
    558 #define DMACCRDA_6 DMAC.CRDA_6
    559 #define DMACCRTB_6 DMAC.CRTB_6
    560 #define DMACCHSTAT_6 DMAC.CHSTAT_6
    561 #define DMACCHCTRL_6 DMAC.CHCTRL_6
    562 #define DMACCHCFG_6 DMAC.CHCFG_6
    563 #define DMACCHITVL_6 DMAC.CHITVL_6
    564 #define DMACCHEXT_6 DMAC.CHEXT_6
    565 #define DMACNXLA_6 DMAC.NXLA_6
    566 #define DMACCRLA_6 DMAC.CRLA_6
    567 #define DMACN0SA_7 DMAC.N0SA_7
    568 #define DMACN0DA_7 DMAC.N0DA_7
    569 #define DMACN0TB_7 DMAC.N0TB_7
    570 #define DMACN1SA_7 DMAC.N1SA_7
    571 #define DMACN1DA_7 DMAC.N1DA_7
    572 #define DMACN1TB_7 DMAC.N1TB_7
    573 #define DMACCRSA_7 DMAC.CRSA_7
    574 #define DMACCRDA_7 DMAC.CRDA_7
    575 #define DMACCRTB_7 DMAC.CRTB_7
    576 #define DMACCHSTAT_7 DMAC.CHSTAT_7
    577 #define DMACCHCTRL_7 DMAC.CHCTRL_7
    578 #define DMACCHCFG_7 DMAC.CHCFG_7
    579 #define DMACCHITVL_7 DMAC.CHITVL_7
    580 #define DMACCHEXT_7 DMAC.CHEXT_7
    581 #define DMACNXLA_7 DMAC.NXLA_7
    582 #define DMACCRLA_7 DMAC.CRLA_7
    583 #define DMACDCTRL_0_7 DMAC.DCTRL_0_7
    584 #define DMACDSTAT_EN_0_7 DMAC.DSTAT_EN_0_7
    585 #define DMACDSTAT_ER_0_7 DMAC.DSTAT_ER_0_7
    586 #define DMACDSTAT_END_0_7 DMAC.DSTAT_END_0_7
    587 #define DMACDSTAT_TC_0_7 DMAC.DSTAT_TC_0_7
    588 #define DMACDSTAT_SUS_0_7 DMAC.DSTAT_SUS_0_7
    589 #define DMACN0SA_8 DMAC.N0SA_8
    590 #define DMACN0DA_8 DMAC.N0DA_8
    591 #define DMACN0TB_8 DMAC.N0TB_8
    592 #define DMACN1SA_8 DMAC.N1SA_8
    593 #define DMACN1DA_8 DMAC.N1DA_8
    594 #define DMACN1TB_8 DMAC.N1TB_8
    595 #define DMACCRSA_8 DMAC.CRSA_8
    596 #define DMACCRDA_8 DMAC.CRDA_8
    597 #define DMACCRTB_8 DMAC.CRTB_8
    598 #define DMACCHSTAT_8 DMAC.CHSTAT_8
    599 #define DMACCHCTRL_8 DMAC.CHCTRL_8
    600 #define DMACCHCFG_8 DMAC.CHCFG_8
    601 #define DMACCHITVL_8 DMAC.CHITVL_8
    602 #define DMACCHEXT_8 DMAC.CHEXT_8
    603 #define DMACNXLA_8 DMAC.NXLA_8
    604 #define DMACCRLA_8 DMAC.CRLA_8
    605 #define DMACN0SA_9 DMAC.N0SA_9
    606 #define DMACN0DA_9 DMAC.N0DA_9
    607 #define DMACN0TB_9 DMAC.N0TB_9
    608 #define DMACN1SA_9 DMAC.N1SA_9
    609 #define DMACN1DA_9 DMAC.N1DA_9
    610 #define DMACN1TB_9 DMAC.N1TB_9
    611 #define DMACCRSA_9 DMAC.CRSA_9
    612 #define DMACCRDA_9 DMAC.CRDA_9
    613 #define DMACCRTB_9 DMAC.CRTB_9
    614 #define DMACCHSTAT_9 DMAC.CHSTAT_9
    615 #define DMACCHCTRL_9 DMAC.CHCTRL_9
    616 #define DMACCHCFG_9 DMAC.CHCFG_9
    617 #define DMACCHITVL_9 DMAC.CHITVL_9
    618 #define DMACCHEXT_9 DMAC.CHEXT_9
    619 #define DMACNXLA_9 DMAC.NXLA_9
    620 #define DMACCRLA_9 DMAC.CRLA_9
    621 #define DMACN0SA_10 DMAC.N0SA_10
    622 #define DMACN0DA_10 DMAC.N0DA_10
    623 #define DMACN0TB_10 DMAC.N0TB_10
    624 #define DMACN1SA_10 DMAC.N1SA_10
    625 #define DMACN1DA_10 DMAC.N1DA_10
    626 #define DMACN1TB_10 DMAC.N1TB_10
    627 #define DMACCRSA_10 DMAC.CRSA_10
    628 #define DMACCRDA_10 DMAC.CRDA_10
    629 #define DMACCRTB_10 DMAC.CRTB_10
    630 #define DMACCHSTAT_10 DMAC.CHSTAT_10
    631 #define DMACCHCTRL_10 DMAC.CHCTRL_10
    632 #define DMACCHCFG_10 DMAC.CHCFG_10
    633 #define DMACCHITVL_10 DMAC.CHITVL_10
    634 #define DMACCHEXT_10 DMAC.CHEXT_10
    635 #define DMACNXLA_10 DMAC.NXLA_10
    636 #define DMACCRLA_10 DMAC.CRLA_10
    637 #define DMACN0SA_11 DMAC.N0SA_11
    638 #define DMACN0DA_11 DMAC.N0DA_11
    639 #define DMACN0TB_11 DMAC.N0TB_11
    640 #define DMACN1SA_11 DMAC.N1SA_11
    641 #define DMACN1DA_11 DMAC.N1DA_11
    642 #define DMACN1TB_11 DMAC.N1TB_11
    643 #define DMACCRSA_11 DMAC.CRSA_11
    644 #define DMACCRDA_11 DMAC.CRDA_11
    645 #define DMACCRTB_11 DMAC.CRTB_11
    646 #define DMACCHSTAT_11 DMAC.CHSTAT_11
    647 #define DMACCHCTRL_11 DMAC.CHCTRL_11
    648 #define DMACCHCFG_11 DMAC.CHCFG_11
    649 #define DMACCHITVL_11 DMAC.CHITVL_11
    650 #define DMACCHEXT_11 DMAC.CHEXT_11
    651 #define DMACNXLA_11 DMAC.NXLA_11
    652 #define DMACCRLA_11 DMAC.CRLA_11
    653 #define DMACN0SA_12 DMAC.N0SA_12
    654 #define DMACN0DA_12 DMAC.N0DA_12
    655 #define DMACN0TB_12 DMAC.N0TB_12
    656 #define DMACN1SA_12 DMAC.N1SA_12
    657 #define DMACN1DA_12 DMAC.N1DA_12
    658 #define DMACN1TB_12 DMAC.N1TB_12
    659 #define DMACCRSA_12 DMAC.CRSA_12
    660 #define DMACCRDA_12 DMAC.CRDA_12
    661 #define DMACCRTB_12 DMAC.CRTB_12
    662 #define DMACCHSTAT_12 DMAC.CHSTAT_12
    663 #define DMACCHCTRL_12 DMAC.CHCTRL_12
    664 #define DMACCHCFG_12 DMAC.CHCFG_12
    665 #define DMACCHITVL_12 DMAC.CHITVL_12
    666 #define DMACCHEXT_12 DMAC.CHEXT_12
    667 #define DMACNXLA_12 DMAC.NXLA_12
    668 #define DMACCRLA_12 DMAC.CRLA_12
    669 #define DMACN0SA_13 DMAC.N0SA_13
    670 #define DMACN0DA_13 DMAC.N0DA_13
    671 #define DMACN0TB_13 DMAC.N0TB_13
    672 #define DMACN1SA_13 DMAC.N1SA_13
    673 #define DMACN1DA_13 DMAC.N1DA_13
    674 #define DMACN1TB_13 DMAC.N1TB_13
    675 #define DMACCRSA_13 DMAC.CRSA_13
    676 #define DMACCRDA_13 DMAC.CRDA_13
    677 #define DMACCRTB_13 DMAC.CRTB_13
    678 #define DMACCHSTAT_13 DMAC.CHSTAT_13
    679 #define DMACCHCTRL_13 DMAC.CHCTRL_13
    680 #define DMACCHCFG_13 DMAC.CHCFG_13
    681 #define DMACCHITVL_13 DMAC.CHITVL_13
    682 #define DMACCHEXT_13 DMAC.CHEXT_13
    683 #define DMACNXLA_13 DMAC.NXLA_13
    684 #define DMACCRLA_13 DMAC.CRLA_13
    685 #define DMACN0SA_14 DMAC.N0SA_14
    686 #define DMACN0DA_14 DMAC.N0DA_14
    687 #define DMACN0TB_14 DMAC.N0TB_14
    688 #define DMACN1SA_14 DMAC.N1SA_14
    689 #define DMACN1DA_14 DMAC.N1DA_14
    690 #define DMACN1TB_14 DMAC.N1TB_14
    691 #define DMACCRSA_14 DMAC.CRSA_14
    692 #define DMACCRDA_14 DMAC.CRDA_14
    693 #define DMACCRTB_14 DMAC.CRTB_14
    694 #define DMACCHSTAT_14 DMAC.CHSTAT_14
    695 #define DMACCHCTRL_14 DMAC.CHCTRL_14
    696 #define DMACCHCFG_14 DMAC.CHCFG_14
    697 #define DMACCHITVL_14 DMAC.CHITVL_14
    698 #define DMACCHEXT_14 DMAC.CHEXT_14
    699 #define DMACNXLA_14 DMAC.NXLA_14
    700 #define DMACCRLA_14 DMAC.CRLA_14
    701 #define DMACN0SA_15 DMAC.N0SA_15
    702 #define DMACN0DA_15 DMAC.N0DA_15
    703 #define DMACN0TB_15 DMAC.N0TB_15
    704 #define DMACN1SA_15 DMAC.N1SA_15
    705 #define DMACN1DA_15 DMAC.N1DA_15
    706 #define DMACN1TB_15 DMAC.N1TB_15
    707 #define DMACCRSA_15 DMAC.CRSA_15
    708 #define DMACCRDA_15 DMAC.CRDA_15
    709 #define DMACCRTB_15 DMAC.CRTB_15
    710 #define DMACCHSTAT_15 DMAC.CHSTAT_15
    711 #define DMACCHCTRL_15 DMAC.CHCTRL_15
    712 #define DMACCHCFG_15 DMAC.CHCFG_15
    713 #define DMACCHITVL_15 DMAC.CHITVL_15
    714 #define DMACCHEXT_15 DMAC.CHEXT_15
    715 #define DMACNXLA_15 DMAC.NXLA_15
    716 #define DMACCRLA_15 DMAC.CRLA_15
    717 #define DMACDCTRL_8_15 DMAC.DCTRL_8_15
    718 #define DMACDSTAT_EN_8_15 DMAC.DSTAT_EN_8_15
    719 #define DMACDSTAT_ER_8_15 DMAC.DSTAT_ER_8_15
    720 #define DMACDSTAT_END_8_15 DMAC.DSTAT_END_8_15
    721 #define DMACDSTAT_TC_8_15 DMAC.DSTAT_TC_8_15
    722 #define DMACDSTAT_SUS_8_15 DMAC.DSTAT_SUS_8_15
    723 #define DMACDMARS0 DMAC.DMARS0
    724 #define DMACDMARS1 DMAC.DMARS1
    725 #define DMACDMARS2 DMAC.DMARS2
    726 #define DMACDMARS3 DMAC.DMARS3
    727 #define DMACDMARS4 DMAC.DMARS4
    728 #define DMACDMARS5 DMAC.DMARS5
    729 #define DMACDMARS6 DMAC.DMARS6
    730 #define DMACDMARS7 DMAC.DMARS7
     379 
     380    volatile uint32_t  DMARS;                                    /*  DMARS     */
     381} r_io_dmars_mm_t;
     382
     383
     384typedef struct st_dmac
     385{
     386                                                           /* DMAC             */
     387
     388/* start of struct st_dmac_n */
     389    volatile uint32_t  N0SA_0;                                 /*  N0SA_0          */
     390    volatile uint32_t  N0DA_0;                                 /*  N0DA_0          */
     391    volatile uint32_t  N0TB_0;                                 /*  N0TB_0          */
     392    volatile uint32_t  N1SA_0;                                 /*  N1SA_0          */
     393    volatile uint32_t  N1DA_0;                                 /*  N1DA_0          */
     394    volatile uint32_t  N1TB_0;                                 /*  N1TB_0          */
     395    volatile uint32_t  CRSA_0;                                 /*  CRSA_0          */
     396    volatile uint32_t  CRDA_0;                                 /*  CRDA_0          */
     397    volatile uint32_t  CRTB_0;                                 /*  CRTB_0          */
     398    volatile uint32_t  CHSTAT_0;                               /*  CHSTAT_0        */
     399    volatile uint32_t  CHCTRL_0;                               /*  CHCTRL_0        */
     400    volatile uint32_t  CHCFG_0;                                /*  CHCFG_0         */
     401    volatile uint32_t  CHITVL_0;                               /*  CHITVL_0        */
     402    volatile uint32_t  CHEXT_0;                                /*  CHEXT_0         */
     403    volatile uint32_t  NXLA_0;                                 /*  NXLA_0          */
     404    volatile uint32_t  CRLA_0;                                 /*  CRLA_0          */
     405
     406/* end of struct st_dmac_n */
     407
     408/* start of struct st_dmac_n */
     409    volatile uint32_t  N0SA_1;                                 /*  N0SA_1          */
     410    volatile uint32_t  N0DA_1;                                 /*  N0DA_1          */
     411    volatile uint32_t  N0TB_1;                                 /*  N0TB_1          */
     412    volatile uint32_t  N1SA_1;                                 /*  N1SA_1          */
     413    volatile uint32_t  N1DA_1;                                 /*  N1DA_1          */
     414    volatile uint32_t  N1TB_1;                                 /*  N1TB_1          */
     415    volatile uint32_t  CRSA_1;                                 /*  CRSA_1          */
     416    volatile uint32_t  CRDA_1;                                 /*  CRDA_1          */
     417    volatile uint32_t  CRTB_1;                                 /*  CRTB_1          */
     418    volatile uint32_t  CHSTAT_1;                               /*  CHSTAT_1        */
     419    volatile uint32_t  CHCTRL_1;                               /*  CHCTRL_1        */
     420    volatile uint32_t  CHCFG_1;                                /*  CHCFG_1         */
     421    volatile uint32_t  CHITVL_1;                               /*  CHITVL_1        */
     422    volatile uint32_t  CHEXT_1;                                /*  CHEXT_1         */
     423    volatile uint32_t  NXLA_1;                                 /*  NXLA_1          */
     424    volatile uint32_t  CRLA_1;                                 /*  CRLA_1          */
     425
     426/* end of struct st_dmac_n */
     427
     428/* start of struct st_dmac_n */
     429    volatile uint32_t  N0SA_2;                                 /*  N0SA_2          */
     430    volatile uint32_t  N0DA_2;                                 /*  N0DA_2          */
     431    volatile uint32_t  N0TB_2;                                 /*  N0TB_2          */
     432    volatile uint32_t  N1SA_2;                                 /*  N1SA_2          */
     433    volatile uint32_t  N1DA_2;                                 /*  N1DA_2          */
     434    volatile uint32_t  N1TB_2;                                 /*  N1TB_2          */
     435    volatile uint32_t  CRSA_2;                                 /*  CRSA_2          */
     436    volatile uint32_t  CRDA_2;                                 /*  CRDA_2          */
     437    volatile uint32_t  CRTB_2;                                 /*  CRTB_2          */
     438    volatile uint32_t  CHSTAT_2;                               /*  CHSTAT_2        */
     439    volatile uint32_t  CHCTRL_2;                               /*  CHCTRL_2        */
     440    volatile uint32_t  CHCFG_2;                                /*  CHCFG_2         */
     441    volatile uint32_t  CHITVL_2;                               /*  CHITVL_2        */
     442    volatile uint32_t  CHEXT_2;                                /*  CHEXT_2         */
     443    volatile uint32_t  NXLA_2;                                 /*  NXLA_2          */
     444    volatile uint32_t  CRLA_2;                                 /*  CRLA_2          */
     445
     446/* end of struct st_dmac_n */
     447
     448/* start of struct st_dmac_n */
     449    volatile uint32_t  N0SA_3;                                 /*  N0SA_3          */
     450    volatile uint32_t  N0DA_3;                                 /*  N0DA_3          */
     451    volatile uint32_t  N0TB_3;                                 /*  N0TB_3          */
     452    volatile uint32_t  N1SA_3;                                 /*  N1SA_3          */
     453    volatile uint32_t  N1DA_3;                                 /*  N1DA_3          */
     454    volatile uint32_t  N1TB_3;                                 /*  N1TB_3          */
     455    volatile uint32_t  CRSA_3;                                 /*  CRSA_3          */
     456    volatile uint32_t  CRDA_3;                                 /*  CRDA_3          */
     457    volatile uint32_t  CRTB_3;                                 /*  CRTB_3          */
     458    volatile uint32_t  CHSTAT_3;                               /*  CHSTAT_3        */
     459    volatile uint32_t  CHCTRL_3;                               /*  CHCTRL_3        */
     460    volatile uint32_t  CHCFG_3;                                /*  CHCFG_3         */
     461    volatile uint32_t  CHITVL_3;                               /*  CHITVL_3        */
     462    volatile uint32_t  CHEXT_3;                                /*  CHEXT_3         */
     463    volatile uint32_t  NXLA_3;                                 /*  NXLA_3          */
     464    volatile uint32_t  CRLA_3;                                 /*  CRLA_3          */
     465
     466/* end of struct st_dmac_n */
     467
     468/* start of struct st_dmac_n */
     469    volatile uint32_t  N0SA_4;                                 /*  N0SA_4          */
     470    volatile uint32_t  N0DA_4;                                 /*  N0DA_4          */
     471    volatile uint32_t  N0TB_4;                                 /*  N0TB_4          */
     472    volatile uint32_t  N1SA_4;                                 /*  N1SA_4          */
     473    volatile uint32_t  N1DA_4;                                 /*  N1DA_4          */
     474    volatile uint32_t  N1TB_4;                                 /*  N1TB_4          */
     475    volatile uint32_t  CRSA_4;                                 /*  CRSA_4          */
     476    volatile uint32_t  CRDA_4;                                 /*  CRDA_4          */
     477    volatile uint32_t  CRTB_4;                                 /*  CRTB_4          */
     478    volatile uint32_t  CHSTAT_4;                               /*  CHSTAT_4        */
     479    volatile uint32_t  CHCTRL_4;                               /*  CHCTRL_4        */
     480    volatile uint32_t  CHCFG_4;                                /*  CHCFG_4         */
     481    volatile uint32_t  CHITVL_4;                               /*  CHITVL_4        */
     482    volatile uint32_t  CHEXT_4;                                /*  CHEXT_4         */
     483    volatile uint32_t  NXLA_4;                                 /*  NXLA_4          */
     484    volatile uint32_t  CRLA_4;                                 /*  CRLA_4          */
     485
     486/* end of struct st_dmac_n */
     487
     488/* start of struct st_dmac_n */
     489    volatile uint32_t  N0SA_5;                                 /*  N0SA_5          */
     490    volatile uint32_t  N0DA_5;                                 /*  N0DA_5          */
     491    volatile uint32_t  N0TB_5;                                 /*  N0TB_5          */
     492    volatile uint32_t  N1SA_5;                                 /*  N1SA_5          */
     493    volatile uint32_t  N1DA_5;                                 /*  N1DA_5          */
     494    volatile uint32_t  N1TB_5;                                 /*  N1TB_5          */
     495    volatile uint32_t  CRSA_5;                                 /*  CRSA_5          */
     496    volatile uint32_t  CRDA_5;                                 /*  CRDA_5          */
     497    volatile uint32_t  CRTB_5;                                 /*  CRTB_5          */
     498    volatile uint32_t  CHSTAT_5;                               /*  CHSTAT_5        */
     499    volatile uint32_t  CHCTRL_5;                               /*  CHCTRL_5        */
     500    volatile uint32_t  CHCFG_5;                                /*  CHCFG_5         */
     501    volatile uint32_t  CHITVL_5;                               /*  CHITVL_5        */
     502    volatile uint32_t  CHEXT_5;                                /*  CHEXT_5         */
     503    volatile uint32_t  NXLA_5;                                 /*  NXLA_5          */
     504    volatile uint32_t  CRLA_5;                                 /*  CRLA_5          */
     505
     506/* end of struct st_dmac_n */
     507
     508/* start of struct st_dmac_n */
     509    volatile uint32_t  N0SA_6;                                 /*  N0SA_6          */
     510    volatile uint32_t  N0DA_6;                                 /*  N0DA_6          */
     511    volatile uint32_t  N0TB_6;                                 /*  N0TB_6          */
     512    volatile uint32_t  N1SA_6;                                 /*  N1SA_6          */
     513    volatile uint32_t  N1DA_6;                                 /*  N1DA_6          */
     514    volatile uint32_t  N1TB_6;                                 /*  N1TB_6          */
     515    volatile uint32_t  CRSA_6;                                 /*  CRSA_6          */
     516    volatile uint32_t  CRDA_6;                                 /*  CRDA_6          */
     517    volatile uint32_t  CRTB_6;                                 /*  CRTB_6          */
     518    volatile uint32_t  CHSTAT_6;                               /*  CHSTAT_6        */
     519    volatile uint32_t  CHCTRL_6;                               /*  CHCTRL_6        */
     520    volatile uint32_t  CHCFG_6;                                /*  CHCFG_6         */
     521    volatile uint32_t  CHITVL_6;                               /*  CHITVL_6        */
     522    volatile uint32_t  CHEXT_6;                                /*  CHEXT_6         */
     523    volatile uint32_t  NXLA_6;                                 /*  NXLA_6          */
     524    volatile uint32_t  CRLA_6;                                 /*  CRLA_6          */
     525
     526/* end of struct st_dmac_n */
     527
     528/* start of struct st_dmac_n */
     529    volatile uint32_t  N0SA_7;                                 /*  N0SA_7          */
     530    volatile uint32_t  N0DA_7;                                 /*  N0DA_7          */
     531    volatile uint32_t  N0TB_7;                                 /*  N0TB_7          */
     532    volatile uint32_t  N1SA_7;                                 /*  N1SA_7          */
     533    volatile uint32_t  N1DA_7;                                 /*  N1DA_7          */
     534    volatile uint32_t  N1TB_7;                                 /*  N1TB_7          */
     535    volatile uint32_t  CRSA_7;                                 /*  CRSA_7          */
     536    volatile uint32_t  CRDA_7;                                 /*  CRDA_7          */
     537    volatile uint32_t  CRTB_7;                                 /*  CRTB_7          */
     538    volatile uint32_t  CHSTAT_7;                               /*  CHSTAT_7        */
     539    volatile uint32_t  CHCTRL_7;                               /*  CHCTRL_7        */
     540    volatile uint32_t  CHCFG_7;                                /*  CHCFG_7         */
     541    volatile uint32_t  CHITVL_7;                               /*  CHITVL_7        */
     542    volatile uint32_t  CHEXT_7;                                /*  CHEXT_7         */
     543    volatile uint32_t  NXLA_7;                                 /*  NXLA_7          */
     544    volatile uint32_t  CRLA_7;                                 /*  CRLA_7          */
     545
     546/* end of struct st_dmac_n */
     547    volatile uint8_t   dummy187[256];                          /*                  */
     548
     549/* start of struct st_dmaccommon_n */
     550    volatile uint32_t  DCTRL_0_7;                              /*  DCTRL_0_7       */
     551    volatile uint8_t   dummy188[12];                           /*                  */
     552    volatile uint32_t  DSTAT_EN_0_7;                           /*  DSTAT_EN_0_7    */
     553    volatile uint32_t  DSTAT_ER_0_7;                           /*  DSTAT_ER_0_7    */
     554    volatile uint32_t  DSTAT_END_0_7;                          /*  DSTAT_END_0_7   */
     555    volatile uint32_t  DSTAT_TC_0_7;                           /*  DSTAT_TC_0_7    */
     556    volatile uint32_t  DSTAT_SUS_0_7;                          /*  DSTAT_SUS_0_7   */
     557
     558/* end of struct st_dmaccommon_n */
     559    volatile uint8_t   dummy189[220];                          /*                  */
     560
     561/* start of struct st_dmac_n */
     562    volatile uint32_t  N0SA_8;                                 /*  N0SA_8          */
     563    volatile uint32_t  N0DA_8;                                 /*  N0DA_8          */
     564    volatile uint32_t  N0TB_8;                                 /*  N0TB_8          */
     565    volatile uint32_t  N1SA_8;                                 /*  N1SA_8          */
     566    volatile uint32_t  N1DA_8;                                 /*  N1DA_8          */
     567    volatile uint32_t  N1TB_8;                                 /*  N1TB_8          */
     568    volatile uint32_t  CRSA_8;                                 /*  CRSA_8          */
     569    volatile uint32_t  CRDA_8;                                 /*  CRDA_8          */
     570    volatile uint32_t  CRTB_8;                                 /*  CRTB_8          */
     571    volatile uint32_t  CHSTAT_8;                               /*  CHSTAT_8        */
     572    volatile uint32_t  CHCTRL_8;                               /*  CHCTRL_8        */
     573    volatile uint32_t  CHCFG_8;                                /*  CHCFG_8         */
     574    volatile uint32_t  CHITVL_8;                               /*  CHITVL_8        */
     575    volatile uint32_t  CHEXT_8;                                /*  CHEXT_8         */
     576    volatile uint32_t  NXLA_8;                                 /*  NXLA_8          */
     577    volatile uint32_t  CRLA_8;                                 /*  CRLA_8          */
     578
     579/* end of struct st_dmac_n */
     580
     581/* start of struct st_dmac_n */
     582    volatile uint32_t  N0SA_9;                                 /*  N0SA_9          */
     583    volatile uint32_t  N0DA_9;                                 /*  N0DA_9          */
     584    volatile uint32_t  N0TB_9;                                 /*  N0TB_9          */
     585    volatile uint32_t  N1SA_9;                                 /*  N1SA_9          */
     586    volatile uint32_t  N1DA_9;                                 /*  N1DA_9          */
     587    volatile uint32_t  N1TB_9;                                 /*  N1TB_9          */
     588    volatile uint32_t  CRSA_9;                                 /*  CRSA_9          */
     589    volatile uint32_t  CRDA_9;                                 /*  CRDA_9          */
     590    volatile uint32_t  CRTB_9;                                 /*  CRTB_9          */
     591    volatile uint32_t  CHSTAT_9;                               /*  CHSTAT_9        */
     592    volatile uint32_t  CHCTRL_9;                               /*  CHCTRL_9        */
     593    volatile uint32_t  CHCFG_9;                                /*  CHCFG_9         */
     594    volatile uint32_t  CHITVL_9;                               /*  CHITVL_9        */
     595    volatile uint32_t  CHEXT_9;                                /*  CHEXT_9         */
     596    volatile uint32_t  NXLA_9;                                 /*  NXLA_9          */
     597    volatile uint32_t  CRLA_9;                                 /*  CRLA_9          */
     598
     599/* end of struct st_dmac_n */
     600
     601/* start of struct st_dmac_n */
     602    volatile uint32_t  N0SA_10;                                /*  N0SA_10         */
     603    volatile uint32_t  N0DA_10;                                /*  N0DA_10         */
     604    volatile uint32_t  N0TB_10;                                /*  N0TB_10         */
     605    volatile uint32_t  N1SA_10;                                /*  N1SA_10         */
     606    volatile uint32_t  N1DA_10;                                /*  N1DA_10         */
     607    volatile uint32_t  N1TB_10;                                /*  N1TB_10         */
     608    volatile uint32_t  CRSA_10;                                /*  CRSA_10         */
     609    volatile uint32_t  CRDA_10;                                /*  CRDA_10         */
     610    volatile uint32_t  CRTB_10;                                /*  CRTB_10         */
     611    volatile uint32_t  CHSTAT_10;                              /*  CHSTAT_10       */
     612    volatile uint32_t  CHCTRL_10;                              /*  CHCTRL_10       */
     613    volatile uint32_t  CHCFG_10;                               /*  CHCFG_10        */
     614    volatile uint32_t  CHITVL_10;                              /*  CHITVL_10       */
     615    volatile uint32_t  CHEXT_10;                               /*  CHEXT_10        */
     616    volatile uint32_t  NXLA_10;                                /*  NXLA_10         */
     617    volatile uint32_t  CRLA_10;                                /*  CRLA_10         */
     618
     619/* end of struct st_dmac_n */
     620
     621/* start of struct st_dmac_n */
     622    volatile uint32_t  N0SA_11;                                /*  N0SA_11         */
     623    volatile uint32_t  N0DA_11;                                /*  N0DA_11         */
     624    volatile uint32_t  N0TB_11;                                /*  N0TB_11         */
     625    volatile uint32_t  N1SA_11;                                /*  N1SA_11         */
     626    volatile uint32_t  N1DA_11;                                /*  N1DA_11         */
     627    volatile uint32_t  N1TB_11;                                /*  N1TB_11         */
     628    volatile uint32_t  CRSA_11;                                /*  CRSA_11         */
     629    volatile uint32_t  CRDA_11;                                /*  CRDA_11         */
     630    volatile uint32_t  CRTB_11;                                /*  CRTB_11         */
     631    volatile uint32_t  CHSTAT_11;                              /*  CHSTAT_11       */
     632    volatile uint32_t  CHCTRL_11;                              /*  CHCTRL_11       */
     633    volatile uint32_t  CHCFG_11;                               /*  CHCFG_11        */
     634    volatile uint32_t  CHITVL_11;                              /*  CHITVL_11       */
     635    volatile uint32_t  CHEXT_11;                               /*  CHEXT_11        */
     636    volatile uint32_t  NXLA_11;                                /*  NXLA_11         */
     637    volatile uint32_t  CRLA_11;                                /*  CRLA_11         */
     638
     639/* end of struct st_dmac_n */
     640
     641/* start of struct st_dmac_n */
     642    volatile uint32_t  N0SA_12;                                /*  N0SA_12         */
     643    volatile uint32_t  N0DA_12;                                /*  N0DA_12         */
     644    volatile uint32_t  N0TB_12;                                /*  N0TB_12         */
     645    volatile uint32_t  N1SA_12;                                /*  N1SA_12         */
     646    volatile uint32_t  N1DA_12;                                /*  N1DA_12         */
     647    volatile uint32_t  N1TB_12;                                /*  N1TB_12         */
     648    volatile uint32_t  CRSA_12;                                /*  CRSA_12         */
     649    volatile uint32_t  CRDA_12;                                /*  CRDA_12         */
     650    volatile uint32_t  CRTB_12;                                /*  CRTB_12         */
     651    volatile uint32_t  CHSTAT_12;                              /*  CHSTAT_12       */
     652    volatile uint32_t  CHCTRL_12;                              /*  CHCTRL_12       */
     653    volatile uint32_t  CHCFG_12;                               /*  CHCFG_12        */
     654    volatile uint32_t  CHITVL_12;                              /*  CHITVL_12       */
     655    volatile uint32_t  CHEXT_12;                               /*  CHEXT_12        */
     656    volatile uint32_t  NXLA_12;                                /*  NXLA_12         */
     657    volatile uint32_t  CRLA_12;                                /*  CRLA_12         */
     658
     659/* end of struct st_dmac_n */
     660
     661/* start of struct st_dmac_n */
     662    volatile uint32_t  N0SA_13;                                /*  N0SA_13         */
     663    volatile uint32_t  N0DA_13;                                /*  N0DA_13         */
     664    volatile uint32_t  N0TB_13;                                /*  N0TB_13         */
     665    volatile uint32_t  N1SA_13;                                /*  N1SA_13         */
     666    volatile uint32_t  N1DA_13;                                /*  N1DA_13         */
     667    volatile uint32_t  N1TB_13;                                /*  N1TB_13         */
     668    volatile uint32_t  CRSA_13;                                /*  CRSA_13         */
     669    volatile uint32_t  CRDA_13;                                /*  CRDA_13         */
     670    volatile uint32_t  CRTB_13;                                /*  CRTB_13         */
     671    volatile uint32_t  CHSTAT_13;                              /*  CHSTAT_13       */
     672    volatile uint32_t  CHCTRL_13;                              /*  CHCTRL_13       */
     673    volatile uint32_t  CHCFG_13;                               /*  CHCFG_13        */
     674    volatile uint32_t  CHITVL_13;                              /*  CHITVL_13       */
     675    volatile uint32_t  CHEXT_13;                               /*  CHEXT_13        */
     676    volatile uint32_t  NXLA_13;                                /*  NXLA_13         */
     677    volatile uint32_t  CRLA_13;                                /*  CRLA_13         */
     678
     679/* end of struct st_dmac_n */
     680
     681/* start of struct st_dmac_n */
     682    volatile uint32_t  N0SA_14;                                /*  N0SA_14         */
     683    volatile uint32_t  N0DA_14;                                /*  N0DA_14         */
     684    volatile uint32_t  N0TB_14;                                /*  N0TB_14         */
     685    volatile uint32_t  N1SA_14;                                /*  N1SA_14         */
     686    volatile uint32_t  N1DA_14;                                /*  N1DA_14         */
     687    volatile uint32_t  N1TB_14;                                /*  N1TB_14         */
     688    volatile uint32_t  CRSA_14;                                /*  CRSA_14         */
     689    volatile uint32_t  CRDA_14;                                /*  CRDA_14         */
     690    volatile uint32_t  CRTB_14;                                /*  CRTB_14         */
     691    volatile uint32_t  CHSTAT_14;                              /*  CHSTAT_14       */
     692    volatile uint32_t  CHCTRL_14;                              /*  CHCTRL_14       */
     693    volatile uint32_t  CHCFG_14;                               /*  CHCFG_14        */
     694    volatile uint32_t  CHITVL_14;                              /*  CHITVL_14       */
     695    volatile uint32_t  CHEXT_14;                               /*  CHEXT_14        */
     696    volatile uint32_t  NXLA_14;                                /*  NXLA_14         */
     697    volatile uint32_t  CRLA_14;                                /*  CRLA_14         */
     698
     699/* end of struct st_dmac_n */
     700
     701/* start of struct st_dmac_n */
     702    volatile uint32_t  N0SA_15;                                /*  N0SA_15         */
     703    volatile uint32_t  N0DA_15;                                /*  N0DA_15         */
     704    volatile uint32_t  N0TB_15;                                /*  N0TB_15         */
     705    volatile uint32_t  N1SA_15;                                /*  N1SA_15         */
     706    volatile uint32_t  N1DA_15;                                /*  N1DA_15         */
     707    volatile uint32_t  N1TB_15;                                /*  N1TB_15         */
     708    volatile uint32_t  CRSA_15;                                /*  CRSA_15         */
     709    volatile uint32_t  CRDA_15;                                /*  CRDA_15         */
     710    volatile uint32_t  CRTB_15;                                /*  CRTB_15         */
     711    volatile uint32_t  CHSTAT_15;                              /*  CHSTAT_15       */
     712    volatile uint32_t  CHCTRL_15;                              /*  CHCTRL_15       */
     713    volatile uint32_t  CHCFG_15;                               /*  CHCFG_15        */
     714    volatile uint32_t  CHITVL_15;                              /*  CHITVL_15       */
     715    volatile uint32_t  CHEXT_15;                               /*  CHEXT_15        */
     716    volatile uint32_t  NXLA_15;                                /*  NXLA_15         */
     717    volatile uint32_t  CRLA_15;                                /*  CRLA_15         */
     718
     719/* end of struct st_dmac_n */
     720    volatile uint8_t   dummy190[256];                          /*                  */
     721
     722/* start of struct st_dmaccommon_n */
     723    volatile uint32_t  DCTRL_8_15;                             /*  DCTRL_8_15      */
     724    volatile uint8_t   dummy191[12];                           /*                  */
     725    volatile uint32_t  DSTAT_EN_8_15;                          /*  DSTAT_EN_8_15   */
     726    volatile uint32_t  DSTAT_ER_8_15;                          /*  DSTAT_ER_8_15   */
     727    volatile uint32_t  DSTAT_END_8_15;                         /*  DSTAT_END_8_15  */
     728    volatile uint32_t  DSTAT_TC_8_15;                          /*  DSTAT_TC_8_15   */
     729    volatile uint32_t  DSTAT_SUS_8_15;                         /*  DSTAT_SUS_8_15  */
     730
     731/* end of struct st_dmaccommon_n */
     732    volatile uint8_t   dummy192[350095580];                    /*                  */
     733    volatile uint32_t  DMARS0;                                 /*  DMARS0          */
     734    volatile uint32_t  DMARS1;                                 /*  DMARS1          */
     735    volatile uint32_t  DMARS2;                                 /*  DMARS2          */
     736    volatile uint32_t  DMARS3;                                 /*  DMARS3          */
     737    volatile uint32_t  DMARS4;                                 /*  DMARS4          */
     738    volatile uint32_t  DMARS5;                                 /*  DMARS5          */
     739    volatile uint32_t  DMARS6;                                 /*  DMARS6          */
     740    volatile uint32_t  DMARS7;                                 /*  DMARS7          */
     741} r_io_dmac_t;
     742
     743
     744typedef struct st_dmaccommon_n
     745{
     746 
     747    volatile uint32_t  DCTRL_0_7;                              /*  DCTRL_0_7       */
     748    volatile uint8_t   dummy1[12];                             /*                  */
     749    volatile uint32_t  DSTAT_EN_0_7;                           /*  DSTAT_EN_0_7    */
     750    volatile uint32_t  DSTAT_ER_0_7;                           /*  DSTAT_ER_0_7    */
     751    volatile uint32_t  DSTAT_END_0_7;                          /*  DSTAT_END_0_7   */
     752    volatile uint32_t  DSTAT_TC_0_7;                           /*  DSTAT_TC_0_7    */
     753    volatile uint32_t  DSTAT_SUS_0_7;                          /*  DSTAT_SUS_0_7   */
     754} r_io_dmaccommon_n_t;
     755
     756
     757typedef struct st_dmac_n
     758{
     759 
     760    volatile uint32_t  N0SA_n;                                 /*  N0SA_n          */
     761    volatile uint32_t  N0DA_n;                                 /*  N0DA_n          */
     762    volatile uint32_t  N0TB_n;                                 /*  N0TB_n          */
     763    volatile uint32_t  N1SA_n;                                 /*  N1SA_n          */
     764    volatile uint32_t  N1DA_n;                                 /*  N1DA_n          */
     765    volatile uint32_t  N1TB_n;                                 /*  N1TB_n          */
     766    volatile uint32_t  CRSA_n;                                 /*  CRSA_n          */
     767    volatile uint32_t  CRDA_n;                                 /*  CRDA_n          */
     768    volatile uint32_t  CRTB_n;                                 /*  CRTB_n          */
     769    volatile uint32_t  CHSTAT_n;                               /*  CHSTAT_n        */
     770    volatile uint32_t  CHCTRL_n;                               /*  CHCTRL_n        */
     771    volatile uint32_t  CHCFG_n;                                /*  CHCFG_n         */
     772    volatile uint32_t  CHITVL_n;                               /*  CHITVL_n        */
     773    volatile uint32_t  CHEXT_n;                                /*  CHEXT_n         */
     774    volatile uint32_t  NXLA_n;                                 /*  NXLA_n          */
     775    volatile uint32_t  CRLA_n;                                 /*  CRLA_n          */
     776} r_io_dmac_n_t;
     777
     778
     779/* Channel array defines of DMAC (2)*/
     780#ifdef  DECLARE_DMACmm_CHANNELS
     781volatile struct st_dmars_mm*  DMACmm[ DMACmm_COUNT ] =
     782    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     783    DMACmm_ADDRESS_LIST;
     784    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     785#endif  /* DECLARE_DMACmm_CHANNELS */
     786
     787#ifdef  DECLARE_DMACn_CHANNELS
     788volatile struct st_dmac_n*  DMACn[ DMACn_COUNT ] =
     789    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     790    DMACn_ADDRESS_LIST;
     791    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     792#endif  /* DECLARE_DMACn_CHANNELS */
     793
     794#ifdef  DECLARE_DMACnn_CHANNELS
     795volatile struct st_dmaccommon_n*  DMACnn[ DMACnn_COUNT ] =
     796    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     797    DMACnn_ADDRESS_LIST;
     798    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     799#endif  /* DECLARE_DMACnn_CHANNELS */
     800/* End of channel array defines of DMAC (2)*/
     801
     802
    731803/* <-SEC M1.10.1 */
     804/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     805/* <-QAC 0857 */
    732806/* <-QAC 0639 */
    733807#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef DVDEC_IODEFINE_H
    3030#define DVDEC_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3134/* ->SEC M1.10.1 : Not magic number */
    3235
    33 struct st_dvdec
    34 {                                                          /* DVDEC            */
     36#define DVDEC1  (*(struct st_dvdec   *)0xFCFFA008uL) /* DVDEC1 */
     37#define DVDEC0  (*(struct st_dvdec   *)0xFCFFB808uL) /* DVDEC0 */
     38
     39
     40/* Start of channel array defines of DVDEC */
     41
     42/* Channel array defines of DVDEC */
     43/*(Sample) value = DVDEC[ channel ]->ADCCR1; */
     44#define DVDEC_COUNT  (2)
     45#define DVDEC_ADDRESS_LIST \
     46{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     47    &DVDEC0, &DVDEC1 \
     48}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     49
     50/* End of channel array defines of DVDEC */
     51
     52
     53#define ADCCR1_1 (DVDEC1.ADCCR1)
     54#define TGCR1_1 (DVDEC1.TGCR1)
     55#define TGCR2_1 (DVDEC1.TGCR2)
     56#define TGCR3_1 (DVDEC1.TGCR3)
     57#define SYNSCR1_1 (DVDEC1.SYNSCR1)
     58#define SYNSCR2_1 (DVDEC1.SYNSCR2)
     59#define SYNSCR3_1 (DVDEC1.SYNSCR3)
     60#define SYNSCR4_1 (DVDEC1.SYNSCR4)
     61#define SYNSCR5_1 (DVDEC1.SYNSCR5)
     62#define HAFCCR1_1 (DVDEC1.HAFCCR1)
     63#define HAFCCR2_1 (DVDEC1.HAFCCR2)
     64#define HAFCCR3_1 (DVDEC1.HAFCCR3)
     65#define VCDWCR1_1 (DVDEC1.VCDWCR1)
     66#define DCPCR1_1 (DVDEC1.DCPCR1)
     67#define DCPCR2_1 (DVDEC1.DCPCR2)
     68#define DCPCR3_1 (DVDEC1.DCPCR3)
     69#define DCPCR4_1 (DVDEC1.DCPCR4)
     70#define DCPCR5_1 (DVDEC1.DCPCR5)
     71#define DCPCR6_1 (DVDEC1.DCPCR6)
     72#define DCPCR7_1 (DVDEC1.DCPCR7)
     73#define DCPCR8_1 (DVDEC1.DCPCR8)
     74#define NSDCR_1 (DVDEC1.NSDCR)
     75#define BTLCR_1 (DVDEC1.BTLCR)
     76#define BTGPCR_1 (DVDEC1.BTGPCR)
     77#define ACCCR1_1 (DVDEC1.ACCCR1)
     78#define ACCCR2_1 (DVDEC1.ACCCR2)
     79#define ACCCR3_1 (DVDEC1.ACCCR3)
     80#define TINTCR_1 (DVDEC1.TINTCR)
     81#define YCDCR_1 (DVDEC1.YCDCR)
     82#define AGCCR1_1 (DVDEC1.AGCCR1)
     83#define AGCCR2_1 (DVDEC1.AGCCR2)
     84#define PKLIMITCR_1 (DVDEC1.PKLIMITCR)
     85#define RGORCR1_1 (DVDEC1.RGORCR1)
     86#define RGORCR2_1 (DVDEC1.RGORCR2)
     87#define RGORCR3_1 (DVDEC1.RGORCR3)
     88#define RGORCR4_1 (DVDEC1.RGORCR4)
     89#define RGORCR5_1 (DVDEC1.RGORCR5)
     90#define RGORCR6_1 (DVDEC1.RGORCR6)
     91#define RGORCR7_1 (DVDEC1.RGORCR7)
     92#define AFCPFCR_1 (DVDEC1.AFCPFCR)
     93#define RUPDCR_1 (DVDEC1.RUPDCR)
     94#define VSYNCSR_1 (DVDEC1.VSYNCSR)
     95#define HSYNCSR_1 (DVDEC1.HSYNCSR)
     96#define DCPSR1_1 (DVDEC1.DCPSR1)
     97#define DCPSR2_1 (DVDEC1.DCPSR2)
     98#define NSDSR_1 (DVDEC1.NSDSR)
     99#define CROMASR1_1 (DVDEC1.CROMASR1)
     100#define CROMASR2_1 (DVDEC1.CROMASR2)
     101#define SYNCSSR_1 (DVDEC1.SYNCSSR)
     102#define AGCCSR1_1 (DVDEC1.AGCCSR1)
     103#define AGCCSR2_1 (DVDEC1.AGCCSR2)
     104#define YCSCR3_1 (DVDEC1.YCSCR3)
     105#define YCSCR4_1 (DVDEC1.YCSCR4)
     106#define YCSCR5_1 (DVDEC1.YCSCR5)
     107#define YCSCR6_1 (DVDEC1.YCSCR6)
     108#define YCSCR7_1 (DVDEC1.YCSCR7)
     109#define YCSCR8_1 (DVDEC1.YCSCR8)
     110#define YCSCR9_1 (DVDEC1.YCSCR9)
     111#define YCSCR11_1 (DVDEC1.YCSCR11)
     112#define YCSCR12_1 (DVDEC1.YCSCR12)
     113#define DCPCR9_1 (DVDEC1.DCPCR9)
     114#define YCTWA_F0_1 (DVDEC1.YCTWA_F0)
     115#define YCTWA_F1_1 (DVDEC1.YCTWA_F1)
     116#define YCTWA_F2_1 (DVDEC1.YCTWA_F2)
     117#define YCTWA_F3_1 (DVDEC1.YCTWA_F3)
     118#define YCTWA_F4_1 (DVDEC1.YCTWA_F4)
     119#define YCTWA_F5_1 (DVDEC1.YCTWA_F5)
     120#define YCTWA_F6_1 (DVDEC1.YCTWA_F6)
     121#define YCTWA_F7_1 (DVDEC1.YCTWA_F7)
     122#define YCTWA_F8_1 (DVDEC1.YCTWA_F8)
     123#define YCTWB_F0_1 (DVDEC1.YCTWB_F0)
     124#define YCTWB_F1_1 (DVDEC1.YCTWB_F1)
     125#define YCTWB_F2_1 (DVDEC1.YCTWB_F2)
     126#define YCTWB_F3_1 (DVDEC1.YCTWB_F3)
     127#define YCTWB_F4_1 (DVDEC1.YCTWB_F4)
     128#define YCTWB_F5_1 (DVDEC1.YCTWB_F5)
     129#define YCTWB_F6_1 (DVDEC1.YCTWB_F6)
     130#define YCTWB_F7_1 (DVDEC1.YCTWB_F7)
     131#define YCTWB_F8_1 (DVDEC1.YCTWB_F8)
     132#define YCTNA_F0_1 (DVDEC1.YCTNA_F0)
     133#define YCTNA_F1_1 (DVDEC1.YCTNA_F1)
     134#define YCTNA_F2_1 (DVDEC1.YCTNA_F2)
     135#define YCTNA_F3_1 (DVDEC1.YCTNA_F3)
     136#define YCTNA_F4_1 (DVDEC1.YCTNA_F4)
     137#define YCTNA_F5_1 (DVDEC1.YCTNA_F5)
     138#define YCTNA_F6_1 (DVDEC1.YCTNA_F6)
     139#define YCTNA_F7_1 (DVDEC1.YCTNA_F7)
     140#define YCTNA_F8_1 (DVDEC1.YCTNA_F8)
     141#define YCTNB_F0_1 (DVDEC1.YCTNB_F0)
     142#define YCTNB_F1_1 (DVDEC1.YCTNB_F1)
     143#define YCTNB_F2_1 (DVDEC1.YCTNB_F2)
     144#define YCTNB_F3_1 (DVDEC1.YCTNB_F3)
     145#define YCTNB_F4_1 (DVDEC1.YCTNB_F4)
     146#define YCTNB_F5_1 (DVDEC1.YCTNB_F5)
     147#define YCTNB_F6_1 (DVDEC1.YCTNB_F6)
     148#define YCTNB_F7_1 (DVDEC1.YCTNB_F7)
     149#define YCTNB_F8_1 (DVDEC1.YCTNB_F8)
     150#define YGAINCR_1 (DVDEC1.YGAINCR)
     151#define CBGAINCR_1 (DVDEC1.CBGAINCR)
     152#define CRGAINCR_1 (DVDEC1.CRGAINCR)
     153#define PGA_UPDATE_1 (DVDEC1.PGA_UPDATE)
     154#define PGACR_1 (DVDEC1.PGACR)
     155#define ADCCR2_1 (DVDEC1.ADCCR2)
     156#define ADCCR1_0 (DVDEC0.ADCCR1)
     157#define TGCR1_0 (DVDEC0.TGCR1)
     158#define TGCR2_0 (DVDEC0.TGCR2)
     159#define TGCR3_0 (DVDEC0.TGCR3)
     160#define SYNSCR1_0 (DVDEC0.SYNSCR1)
     161#define SYNSCR2_0 (DVDEC0.SYNSCR2)
     162#define SYNSCR3_0 (DVDEC0.SYNSCR3)
     163#define SYNSCR4_0 (DVDEC0.SYNSCR4)
     164#define SYNSCR5_0 (DVDEC0.SYNSCR5)
     165#define HAFCCR1_0 (DVDEC0.HAFCCR1)
     166#define HAFCCR2_0 (DVDEC0.HAFCCR2)
     167#define HAFCCR3_0 (DVDEC0.HAFCCR3)
     168#define VCDWCR1_0 (DVDEC0.VCDWCR1)
     169#define DCPCR1_0 (DVDEC0.DCPCR1)
     170#define DCPCR2_0 (DVDEC0.DCPCR2)
     171#define DCPCR3_0 (DVDEC0.DCPCR3)
     172#define DCPCR4_0 (DVDEC0.DCPCR4)
     173#define DCPCR5_0 (DVDEC0.DCPCR5)
     174#define DCPCR6_0 (DVDEC0.DCPCR6)
     175#define DCPCR7_0 (DVDEC0.DCPCR7)
     176#define DCPCR8_0 (DVDEC0.DCPCR8)
     177#define NSDCR_0 (DVDEC0.NSDCR)
     178#define BTLCR_0 (DVDEC0.BTLCR)
     179#define BTGPCR_0 (DVDEC0.BTGPCR)
     180#define ACCCR1_0 (DVDEC0.ACCCR1)
     181#define ACCCR2_0 (DVDEC0.ACCCR2)
     182#define ACCCR3_0 (DVDEC0.ACCCR3)
     183#define TINTCR_0 (DVDEC0.TINTCR)
     184#define YCDCR_0 (DVDEC0.YCDCR)
     185#define AGCCR1_0 (DVDEC0.AGCCR1)
     186#define AGCCR2_0 (DVDEC0.AGCCR2)
     187#define PKLIMITCR_0 (DVDEC0.PKLIMITCR)
     188#define RGORCR1_0 (DVDEC0.RGORCR1)
     189#define RGORCR2_0 (DVDEC0.RGORCR2)
     190#define RGORCR3_0 (DVDEC0.RGORCR3)
     191#define RGORCR4_0 (DVDEC0.RGORCR4)
     192#define RGORCR5_0 (DVDEC0.RGORCR5)
     193#define RGORCR6_0 (DVDEC0.RGORCR6)
     194#define RGORCR7_0 (DVDEC0.RGORCR7)
     195#define AFCPFCR_0 (DVDEC0.AFCPFCR)
     196#define RUPDCR_0 (DVDEC0.RUPDCR)
     197#define VSYNCSR_0 (DVDEC0.VSYNCSR)
     198#define HSYNCSR_0 (DVDEC0.HSYNCSR)
     199#define DCPSR1_0 (DVDEC0.DCPSR1)
     200#define DCPSR2_0 (DVDEC0.DCPSR2)
     201#define NSDSR_0 (DVDEC0.NSDSR)
     202#define CROMASR1_0 (DVDEC0.CROMASR1)
     203#define CROMASR2_0 (DVDEC0.CROMASR2)
     204#define SYNCSSR_0 (DVDEC0.SYNCSSR)
     205#define AGCCSR1_0 (DVDEC0.AGCCSR1)
     206#define AGCCSR2_0 (DVDEC0.AGCCSR2)
     207#define YCSCR3_0 (DVDEC0.YCSCR3)
     208#define YCSCR4_0 (DVDEC0.YCSCR4)
     209#define YCSCR5_0 (DVDEC0.YCSCR5)
     210#define YCSCR6_0 (DVDEC0.YCSCR6)
     211#define YCSCR7_0 (DVDEC0.YCSCR7)
     212#define YCSCR8_0 (DVDEC0.YCSCR8)
     213#define YCSCR9_0 (DVDEC0.YCSCR9)
     214#define YCSCR11_0 (DVDEC0.YCSCR11)
     215#define YCSCR12_0 (DVDEC0.YCSCR12)
     216#define DCPCR9_0 (DVDEC0.DCPCR9)
     217#define YCTWA_F0_0 (DVDEC0.YCTWA_F0)
     218#define YCTWA_F1_0 (DVDEC0.YCTWA_F1)
     219#define YCTWA_F2_0 (DVDEC0.YCTWA_F2)
     220#define YCTWA_F3_0 (DVDEC0.YCTWA_F3)
     221#define YCTWA_F4_0 (DVDEC0.YCTWA_F4)
     222#define YCTWA_F5_0 (DVDEC0.YCTWA_F5)
     223#define YCTWA_F6_0 (DVDEC0.YCTWA_F6)
     224#define YCTWA_F7_0 (DVDEC0.YCTWA_F7)
     225#define YCTWA_F8_0 (DVDEC0.YCTWA_F8)
     226#define YCTWB_F0_0 (DVDEC0.YCTWB_F0)
     227#define YCTWB_F1_0 (DVDEC0.YCTWB_F1)
     228#define YCTWB_F2_0 (DVDEC0.YCTWB_F2)
     229#define YCTWB_F3_0 (DVDEC0.YCTWB_F3)
     230#define YCTWB_F4_0 (DVDEC0.YCTWB_F4)
     231#define YCTWB_F5_0 (DVDEC0.YCTWB_F5)
     232#define YCTWB_F6_0 (DVDEC0.YCTWB_F6)
     233#define YCTWB_F7_0 (DVDEC0.YCTWB_F7)
     234#define YCTWB_F8_0 (DVDEC0.YCTWB_F8)
     235#define YCTNA_F0_0 (DVDEC0.YCTNA_F0)
     236#define YCTNA_F1_0 (DVDEC0.YCTNA_F1)
     237#define YCTNA_F2_0 (DVDEC0.YCTNA_F2)
     238#define YCTNA_F3_0 (DVDEC0.YCTNA_F3)
     239#define YCTNA_F4_0 (DVDEC0.YCTNA_F4)
     240#define YCTNA_F5_0 (DVDEC0.YCTNA_F5)
     241#define YCTNA_F6_0 (DVDEC0.YCTNA_F6)
     242#define YCTNA_F7_0 (DVDEC0.YCTNA_F7)
     243#define YCTNA_F8_0 (DVDEC0.YCTNA_F8)
     244#define YCTNB_F0_0 (DVDEC0.YCTNB_F0)
     245#define YCTNB_F1_0 (DVDEC0.YCTNB_F1)
     246#define YCTNB_F2_0 (DVDEC0.YCTNB_F2)
     247#define YCTNB_F3_0 (DVDEC0.YCTNB_F3)
     248#define YCTNB_F4_0 (DVDEC0.YCTNB_F4)
     249#define YCTNB_F5_0 (DVDEC0.YCTNB_F5)
     250#define YCTNB_F6_0 (DVDEC0.YCTNB_F6)
     251#define YCTNB_F7_0 (DVDEC0.YCTNB_F7)
     252#define YCTNB_F8_0 (DVDEC0.YCTNB_F8)
     253#define YGAINCR_0 (DVDEC0.YGAINCR)
     254#define CBGAINCR_0 (DVDEC0.CBGAINCR)
     255#define CRGAINCR_0 (DVDEC0.CRGAINCR)
     256#define PGA_UPDATE_0 (DVDEC0.PGA_UPDATE)
     257#define PGACR_0 (DVDEC0.PGACR)
     258#define ADCCR2_0 (DVDEC0.ADCCR2)
     259
     260#define DVDEC_TGCRn_COUNT (3)
     261#define DVDEC_SYNSCRn_COUNT (5)
     262#define DVDEC_HAFCCRn_COUNT (3)
     263#define DVDEC_DCPCRn_COUNT (8)
     264#define DVDEC_ACCCRn_COUNT (3)
     265#define DVDEC_AGCCRn_COUNT (2)
     266#define DVDEC_RGORCRn_COUNT (7)
     267#define DVDEC_DCPSRn_COUNT (2)
     268#define DVDEC_CROMASRn_COUNT (2)
     269#define DVDEC_AGCCSRn_COUNT (2)
     270#define DVDEC_YCSCRn_COUNT (7)
     271#define DVDEC_YCTWA_Fn_COUNT (9)
     272#define DVDEC_YCTWB_Fn_COUNT (9)
     273#define DVDEC_YCTNA_Fn_COUNT (9)
     274#define DVDEC_YCTNB_Fn_COUNT (9)
     275
     276
     277typedef struct st_dvdec
     278{
     279                                                           /* DVDEC            */
    35280    volatile uint16_t ADCCR1;                                 /*  ADCCR1          */
    36281    volatile uint8_t   dummy1[4];                              /*                  */
    37 #define DVDEC_TGCRn_COUNT 3
     282
     283/* #define DVDEC_TGCRn_COUNT (3) */
    38284    volatile uint16_t TGCR1;                                  /*  TGCR1           */
    39285    volatile uint16_t TGCR2;                                  /*  TGCR2           */
    40286    volatile uint16_t TGCR3;                                  /*  TGCR3           */
    41287    volatile uint8_t   dummy2[6];                              /*                  */
    42 #define DVDEC_SYNSCRn_COUNT 5
     288
     289/* #define DVDEC_SYNSCRn_COUNT (5) */
    43290    volatile uint16_t SYNSCR1;                                /*  SYNSCR1         */
    44291    volatile uint16_t SYNSCR2;                                /*  SYNSCR2         */
    … …  
    46293    volatile uint16_t SYNSCR4;                                /*  SYNSCR4         */
    47294    volatile uint16_t SYNSCR5;                                /*  SYNSCR5         */
    48 #define DVDEC_HAFCCRn_COUNT 3
     295
     296/* #define DVDEC_HAFCCRn_COUNT (3) */
    49297    volatile uint16_t HAFCCR1;                                /*  HAFCCR1         */
    50298    volatile uint16_t HAFCCR2;                                /*  HAFCCR2         */
    … …  
    52300    volatile uint16_t VCDWCR1;                                /*  VCDWCR1         */
    53301    volatile uint8_t   dummy3[4];                              /*                  */
    54 #define DVDEC_DCPCRn_COUNT 8
     302
     303/* #define DVDEC_DCPCRn_COUNT (8) */
    55304    volatile uint16_t DCPCR1;                                 /*  DCPCR1          */
    56305    volatile uint16_t DCPCR2;                                 /*  DCPCR2          */
    … …  
    64313    volatile uint16_t BTLCR;                                  /*  BTLCR           */
    65314    volatile uint16_t BTGPCR;                                 /*  BTGPCR          */
    66 #define DVDEC_ACCCRn_COUNT 3
     315
     316/* #define DVDEC_ACCCRn_COUNT (3) */
    67317    volatile uint16_t ACCCR1;                                 /*  ACCCR1          */
    68318    volatile uint16_t ACCCR2;                                 /*  ACCCR2          */
    … …  
    70320    volatile uint16_t TINTCR;                                 /*  TINTCR          */
    71321    volatile uint16_t YCDCR;                                  /*  YCDCR           */
    72 #define DVDEC_AGCCRn_COUNT 2
     322
     323/* #define DVDEC_AGCCRn_COUNT (2) */
    73324    volatile uint16_t AGCCR1;                                 /*  AGCCR1          */
    74325    volatile uint16_t AGCCR2;                                 /*  AGCCR2          */
    75326    volatile uint16_t PKLIMITCR;                              /*  PKLIMITCR       */
    76 #define DVDEC_RGORCRn_COUNT 7
     327
     328/* #define DVDEC_RGORCRn_COUNT (7) */
    77329    volatile uint16_t RGORCR1;                                /*  RGORCR1         */
    78330    volatile uint16_t RGORCR2;                                /*  RGORCR2         */
    … …  
    87339    volatile uint16_t VSYNCSR;                                /*  VSYNCSR         */
    88340    volatile uint16_t HSYNCSR;                                /*  HSYNCSR         */
    89 #define DVDEC_DCPSRn_COUNT 2
     341
     342/* #define DVDEC_DCPSRn_COUNT (2) */
    90343    volatile uint16_t DCPSR1;                                 /*  DCPSR1          */
    91344    volatile uint16_t DCPSR2;                                 /*  DCPSR2          */
    92345    volatile uint8_t   dummy5[4];                              /*                  */
    93346    volatile uint16_t NSDSR;                                  /*  NSDSR           */
    94 #define DVDEC_CROMASRn_COUNT 2
     347
     348/* #define DVDEC_CROMASRn_COUNT (2) */
    95349    volatile uint16_t CROMASR1;                               /*  CROMASR1        */
    96350    volatile uint16_t CROMASR2;                               /*  CROMASR2        */
    97351    volatile uint16_t SYNCSSR;                                /*  SYNCSSR         */
    98 #define DVDEC_AGCCSRn_COUNT 2
     352
     353/* #define DVDEC_AGCCSRn_COUNT (2) */
    99354    volatile uint16_t AGCCSR1;                                /*  AGCCSR1         */
    100355    volatile uint16_t AGCCSR2;                                /*  AGCCSR2         */
    101356    volatile uint8_t   dummy6[108];                            /*                  */
    102 #define DVDEC_YCSCRn_COUNT 7
     357
     358/* #define DVDEC_YCSCRn_COUNT (7) */
    103359    volatile uint16_t YCSCR3;                                 /*  YCSCR3          */
    104360    volatile uint16_t YCSCR4;                                 /*  YCSCR4          */
    … …  
    114370    volatile uint16_t DCPCR9;                                 /*  DCPCR9          */
    115371    volatile uint8_t   dummy9[16];                             /*                  */
    116 #define DVDEC_YCTWA_Fn_COUNT 9
     372
     373/* #define DVDEC_YCTWA_Fn_COUNT (9) */
    117374    volatile uint16_t YCTWA_F0;                               /*  YCTWA_F0        */
    118375    volatile uint16_t YCTWA_F1;                               /*  YCTWA_F1        */
    … …  
    124381    volatile uint16_t YCTWA_F7;                               /*  YCTWA_F7        */
    125382    volatile uint16_t YCTWA_F8;                               /*  YCTWA_F8        */
    126 #define DVDEC_YCTWB_Fn_COUNT 9
     383
     384/* #define DVDEC_YCTWB_Fn_COUNT (9) */
    127385    volatile uint16_t YCTWB_F0;                               /*  YCTWB_F0        */
    128386    volatile uint16_t YCTWB_F1;                               /*  YCTWB_F1        */
    … …  
    134392    volatile uint16_t YCTWB_F7;                               /*  YCTWB_F7        */
    135393    volatile uint16_t YCTWB_F8;                               /*  YCTWB_F8        */
    136 #define DVDEC_YCTNA_Fn_COUNT 9
     394
     395/* #define DVDEC_YCTNA_Fn_COUNT (9) */
    137396    volatile uint16_t YCTNA_F0;                               /*  YCTNA_F0        */
    138397    volatile uint16_t YCTNA_F1;                               /*  YCTNA_F1        */
    … …  
    144403    volatile uint16_t YCTNA_F7;                               /*  YCTNA_F7        */
    145404    volatile uint16_t YCTNA_F8;                               /*  YCTNA_F8        */
    146 #define DVDEC_YCTNB_Fn_COUNT 9
     405
     406/* #define DVDEC_YCTNB_Fn_COUNT (9) */
    147407    volatile uint16_t YCTNB_F0;                               /*  YCTNB_F0        */
    148408    volatile uint16_t YCTNB_F1;                               /*  YCTNB_F1        */
    … …  
    162422    volatile uint16_t PGACR;                                  /*  PGACR           */
    163423    volatile uint16_t ADCCR2;                                 /*  ADCCR2          */
    164 };
    165 
    166 
    167 #define DVDEC1  (*(struct st_dvdec   *)0xFCFFA008uL) /* DVDEC1 */
    168 #define DVDEC0  (*(struct st_dvdec   *)0xFCFFB808uL) /* DVDEC0 */
    169 
    170 
    171 /* Start of channnel array defines of DVDEC */
    172 
    173 /* Channnel array defines of DVDEC */
    174 /*(Sample) value = DVDEC[ channel ]->ADCCR1; */
    175 #define DVDEC_COUNT  2
    176 #define DVDEC_ADDRESS_LIST \
    177 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    178     &DVDEC0, &DVDEC1 \
    179 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    180 
    181 /* End of channnel array defines of DVDEC */
    182 
    183 
    184 #define ADCCR1_1 DVDEC1.ADCCR1
    185 #define TGCR1_1 DVDEC1.TGCR1
    186 #define TGCR2_1 DVDEC1.TGCR2
    187 #define TGCR3_1 DVDEC1.TGCR3
    188 #define SYNSCR1_1 DVDEC1.SYNSCR1
    189 #define SYNSCR2_1 DVDEC1.SYNSCR2
    190 #define SYNSCR3_1 DVDEC1.SYNSCR3
    191 #define SYNSCR4_1 DVDEC1.SYNSCR4
    192 #define SYNSCR5_1 DVDEC1.SYNSCR5
    193 #define HAFCCR1_1 DVDEC1.HAFCCR1
    194 #define HAFCCR2_1 DVDEC1.HAFCCR2
    195 #define HAFCCR3_1 DVDEC1.HAFCCR3
    196 #define VCDWCR1_1 DVDEC1.VCDWCR1
    197 #define DCPCR1_1 DVDEC1.DCPCR1
    198 #define DCPCR2_1 DVDEC1.DCPCR2
    199 #define DCPCR3_1 DVDEC1.DCPCR3
    200 #define DCPCR4_1 DVDEC1.DCPCR4
    201 #define DCPCR5_1 DVDEC1.DCPCR5
    202 #define DCPCR6_1 DVDEC1.DCPCR6
    203 #define DCPCR7_1 DVDEC1.DCPCR7
    204 #define DCPCR8_1 DVDEC1.DCPCR8
    205 #define NSDCR_1 DVDEC1.NSDCR
    206 #define BTLCR_1 DVDEC1.BTLCR
    207 #define BTGPCR_1 DVDEC1.BTGPCR
    208 #define ACCCR1_1 DVDEC1.ACCCR1
    209 #define ACCCR2_1 DVDEC1.ACCCR2
    210 #define ACCCR3_1 DVDEC1.ACCCR3
    211 #define TINTCR_1 DVDEC1.TINTCR
    212 #define YCDCR_1 DVDEC1.YCDCR
    213 #define AGCCR1_1 DVDEC1.AGCCR1
    214 #define AGCCR2_1 DVDEC1.AGCCR2
    215 #define PKLIMITCR_1 DVDEC1.PKLIMITCR
    216 #define RGORCR1_1 DVDEC1.RGORCR1
    217 #define RGORCR2_1 DVDEC1.RGORCR2
    218 #define RGORCR3_1 DVDEC1.RGORCR3
    219 #define RGORCR4_1 DVDEC1.RGORCR4
    220 #define RGORCR5_1 DVDEC1.RGORCR5
    221 #define RGORCR6_1 DVDEC1.RGORCR6
    222 #define RGORCR7_1 DVDEC1.RGORCR7
    223 #define AFCPFCR_1 DVDEC1.AFCPFCR
    224 #define RUPDCR_1 DVDEC1.RUPDCR
    225 #define VSYNCSR_1 DVDEC1.VSYNCSR
    226 #define HSYNCSR_1 DVDEC1.HSYNCSR
    227 #define DCPSR1_1 DVDEC1.DCPSR1
    228 #define DCPSR2_1 DVDEC1.DCPSR2
    229 #define NSDSR_1 DVDEC1.NSDSR
    230 #define CROMASR1_1 DVDEC1.CROMASR1
    231 #define CROMASR2_1 DVDEC1.CROMASR2
    232 #define SYNCSSR_1 DVDEC1.SYNCSSR
    233 #define AGCCSR1_1 DVDEC1.AGCCSR1
    234 #define AGCCSR2_1 DVDEC1.AGCCSR2
    235 #define YCSCR3_1 DVDEC1.YCSCR3
    236 #define YCSCR4_1 DVDEC1.YCSCR4
    237 #define YCSCR5_1 DVDEC1.YCSCR5
    238 #define YCSCR6_1 DVDEC1.YCSCR6
    239 #define YCSCR7_1 DVDEC1.YCSCR7
    240 #define YCSCR8_1 DVDEC1.YCSCR8
    241 #define YCSCR9_1 DVDEC1.YCSCR9
    242 #define YCSCR11_1 DVDEC1.YCSCR11
    243 #define YCSCR12_1 DVDEC1.YCSCR12
    244 #define DCPCR9_1 DVDEC1.DCPCR9
    245 #define YCTWA_F0_1 DVDEC1.YCTWA_F0
    246 #define YCTWA_F1_1 DVDEC1.YCTWA_F1
    247 #define YCTWA_F2_1 DVDEC1.YCTWA_F2
    248 #define YCTWA_F3_1 DVDEC1.YCTWA_F3
    249 #define YCTWA_F4_1 DVDEC1.YCTWA_F4
    250 #define YCTWA_F5_1 DVDEC1.YCTWA_F5
    251 #define YCTWA_F6_1 DVDEC1.YCTWA_F6
    252 #define YCTWA_F7_1 DVDEC1.YCTWA_F7
    253 #define YCTWA_F8_1 DVDEC1.YCTWA_F8
    254 #define YCTWB_F0_1 DVDEC1.YCTWB_F0
    255 #define YCTWB_F1_1 DVDEC1.YCTWB_F1
    256 #define YCTWB_F2_1 DVDEC1.YCTWB_F2
    257 #define YCTWB_F3_1 DVDEC1.YCTWB_F3
    258 #define YCTWB_F4_1 DVDEC1.YCTWB_F4
    259 #define YCTWB_F5_1 DVDEC1.YCTWB_F5
    260 #define YCTWB_F6_1 DVDEC1.YCTWB_F6
    261 #define YCTWB_F7_1 DVDEC1.YCTWB_F7
    262 #define YCTWB_F8_1 DVDEC1.YCTWB_F8
    263 #define YCTNA_F0_1 DVDEC1.YCTNA_F0
    264 #define YCTNA_F1_1 DVDEC1.YCTNA_F1
    265 #define YCTNA_F2_1 DVDEC1.YCTNA_F2
    266 #define YCTNA_F3_1 DVDEC1.YCTNA_F3
    267 #define YCTNA_F4_1 DVDEC1.YCTNA_F4
    268 #define YCTNA_F5_1 DVDEC1.YCTNA_F5
    269 #define YCTNA_F6_1 DVDEC1.YCTNA_F6
    270 #define YCTNA_F7_1 DVDEC1.YCTNA_F7
    271 #define YCTNA_F8_1 DVDEC1.YCTNA_F8
    272 #define YCTNB_F0_1 DVDEC1.YCTNB_F0
    273 #define YCTNB_F1_1 DVDEC1.YCTNB_F1
    274 #define YCTNB_F2_1 DVDEC1.YCTNB_F2
    275 #define YCTNB_F3_1 DVDEC1.YCTNB_F3
    276 #define YCTNB_F4_1 DVDEC1.YCTNB_F4
    277 #define YCTNB_F5_1 DVDEC1.YCTNB_F5
    278 #define YCTNB_F6_1 DVDEC1.YCTNB_F6
    279 #define YCTNB_F7_1 DVDEC1.YCTNB_F7
    280 #define YCTNB_F8_1 DVDEC1.YCTNB_F8
    281 #define YGAINCR_1 DVDEC1.YGAINCR
    282 #define CBGAINCR_1 DVDEC1.CBGAINCR
    283 #define CRGAINCR_1 DVDEC1.CRGAINCR
    284 #define PGA_UPDATE_1 DVDEC1.PGA_UPDATE
    285 #define PGACR_1 DVDEC1.PGACR
    286 #define ADCCR2_1 DVDEC1.ADCCR2
    287 #define ADCCR1_0 DVDEC0.ADCCR1
    288 #define TGCR1_0 DVDEC0.TGCR1
    289 #define TGCR2_0 DVDEC0.TGCR2
    290 #define TGCR3_0 DVDEC0.TGCR3
    291 #define SYNSCR1_0 DVDEC0.SYNSCR1
    292 #define SYNSCR2_0 DVDEC0.SYNSCR2
    293 #define SYNSCR3_0 DVDEC0.SYNSCR3
    294 #define SYNSCR4_0 DVDEC0.SYNSCR4
    295 #define SYNSCR5_0 DVDEC0.SYNSCR5
    296 #define HAFCCR1_0 DVDEC0.HAFCCR1
    297 #define HAFCCR2_0 DVDEC0.HAFCCR2
    298 #define HAFCCR3_0 DVDEC0.HAFCCR3
    299 #define VCDWCR1_0 DVDEC0.VCDWCR1
    300 #define DCPCR1_0 DVDEC0.DCPCR1
    301 #define DCPCR2_0 DVDEC0.DCPCR2
    302 #define DCPCR3_0 DVDEC0.DCPCR3
    303 #define DCPCR4_0 DVDEC0.DCPCR4
    304 #define DCPCR5_0 DVDEC0.DCPCR5
    305 #define DCPCR6_0 DVDEC0.DCPCR6
    306 #define DCPCR7_0 DVDEC0.DCPCR7
    307 #define DCPCR8_0 DVDEC0.DCPCR8
    308 #define NSDCR_0 DVDEC0.NSDCR
    309 #define BTLCR_0 DVDEC0.BTLCR
    310 #define BTGPCR_0 DVDEC0.BTGPCR
    311 #define ACCCR1_0 DVDEC0.ACCCR1
    312 #define ACCCR2_0 DVDEC0.ACCCR2
    313 #define ACCCR3_0 DVDEC0.ACCCR3
    314 #define TINTCR_0 DVDEC0.TINTCR
    315 #define YCDCR_0 DVDEC0.YCDCR
    316 #define AGCCR1_0 DVDEC0.AGCCR1
    317 #define AGCCR2_0 DVDEC0.AGCCR2
    318 #define PKLIMITCR_0 DVDEC0.PKLIMITCR
    319 #define RGORCR1_0 DVDEC0.RGORCR1
    320 #define RGORCR2_0 DVDEC0.RGORCR2
    321 #define RGORCR3_0 DVDEC0.RGORCR3
    322 #define RGORCR4_0 DVDEC0.RGORCR4
    323 #define RGORCR5_0 DVDEC0.RGORCR5
    324 #define RGORCR6_0 DVDEC0.RGORCR6
    325 #define RGORCR7_0 DVDEC0.RGORCR7
    326 #define AFCPFCR_0 DVDEC0.AFCPFCR
    327 #define RUPDCR_0 DVDEC0.RUPDCR
    328 #define VSYNCSR_0 DVDEC0.VSYNCSR
    329 #define HSYNCSR_0 DVDEC0.HSYNCSR
    330 #define DCPSR1_0 DVDEC0.DCPSR1
    331 #define DCPSR2_0 DVDEC0.DCPSR2
    332 #define NSDSR_0 DVDEC0.NSDSR
    333 #define CROMASR1_0 DVDEC0.CROMASR1
    334 #define CROMASR2_0 DVDEC0.CROMASR2
    335 #define SYNCSSR_0 DVDEC0.SYNCSSR
    336 #define AGCCSR1_0 DVDEC0.AGCCSR1
    337 #define AGCCSR2_0 DVDEC0.AGCCSR2
    338 #define YCSCR3_0 DVDEC0.YCSCR3
    339 #define YCSCR4_0 DVDEC0.YCSCR4
    340 #define YCSCR5_0 DVDEC0.YCSCR5
    341 #define YCSCR6_0 DVDEC0.YCSCR6
    342 #define YCSCR7_0 DVDEC0.YCSCR7
    343 #define YCSCR8_0 DVDEC0.YCSCR8
    344 #define YCSCR9_0 DVDEC0.YCSCR9
    345 #define YCSCR11_0 DVDEC0.YCSCR11
    346 #define YCSCR12_0 DVDEC0.YCSCR12
    347 #define DCPCR9_0 DVDEC0.DCPCR9
    348 #define YCTWA_F0_0 DVDEC0.YCTWA_F0
    349 #define YCTWA_F1_0 DVDEC0.YCTWA_F1
    350 #define YCTWA_F2_0 DVDEC0.YCTWA_F2
    351 #define YCTWA_F3_0 DVDEC0.YCTWA_F3
    352 #define YCTWA_F4_0 DVDEC0.YCTWA_F4
    353 #define YCTWA_F5_0 DVDEC0.YCTWA_F5
    354 #define YCTWA_F6_0 DVDEC0.YCTWA_F6
    355 #define YCTWA_F7_0 DVDEC0.YCTWA_F7
    356 #define YCTWA_F8_0 DVDEC0.YCTWA_F8
    357 #define YCTWB_F0_0 DVDEC0.YCTWB_F0
    358 #define YCTWB_F1_0 DVDEC0.YCTWB_F1
    359 #define YCTWB_F2_0 DVDEC0.YCTWB_F2
    360 #define YCTWB_F3_0 DVDEC0.YCTWB_F3
    361 #define YCTWB_F4_0 DVDEC0.YCTWB_F4
    362 #define YCTWB_F5_0 DVDEC0.YCTWB_F5
    363 #define YCTWB_F6_0 DVDEC0.YCTWB_F6
    364 #define YCTWB_F7_0 DVDEC0.YCTWB_F7
    365 #define YCTWB_F8_0 DVDEC0.YCTWB_F8
    366 #define YCTNA_F0_0 DVDEC0.YCTNA_F0
    367 #define YCTNA_F1_0 DVDEC0.YCTNA_F1
    368 #define YCTNA_F2_0 DVDEC0.YCTNA_F2
    369 #define YCTNA_F3_0 DVDEC0.YCTNA_F3
    370 #define YCTNA_F4_0 DVDEC0.YCTNA_F4
    371 #define YCTNA_F5_0 DVDEC0.YCTNA_F5
    372 #define YCTNA_F6_0 DVDEC0.YCTNA_F6
    373 #define YCTNA_F7_0 DVDEC0.YCTNA_F7
    374 #define YCTNA_F8_0 DVDEC0.YCTNA_F8
    375 #define YCTNB_F0_0 DVDEC0.YCTNB_F0
    376 #define YCTNB_F1_0 DVDEC0.YCTNB_F1
    377 #define YCTNB_F2_0 DVDEC0.YCTNB_F2
    378 #define YCTNB_F3_0 DVDEC0.YCTNB_F3
    379 #define YCTNB_F4_0 DVDEC0.YCTNB_F4
    380 #define YCTNB_F5_0 DVDEC0.YCTNB_F5
    381 #define YCTNB_F6_0 DVDEC0.YCTNB_F6
    382 #define YCTNB_F7_0 DVDEC0.YCTNB_F7
    383 #define YCTNB_F8_0 DVDEC0.YCTNB_F8
    384 #define YGAINCR_0 DVDEC0.YGAINCR
    385 #define CBGAINCR_0 DVDEC0.CBGAINCR
    386 #define CRGAINCR_0 DVDEC0.CRGAINCR
    387 #define PGA_UPDATE_0 DVDEC0.PGA_UPDATE
    388 #define PGACR_0 DVDEC0.PGACR
    389 #define ADCCR2_0 DVDEC0.ADCCR2
     424} r_io_dvdec_t;
     425
     426
     427/* Channel array defines of DVDEC (2)*/
     428#ifdef  DECLARE_DVDEC_CHANNELS
     429volatile struct st_dvdec*  DVDEC[ DVDEC_COUNT ] =
     430    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     431    DVDEC_ADDRESS_LIST;
     432    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     433#endif  /* DECLARE_DVDEC_CHANNELS */
     434/* End of channel array defines of DVDEC (2)*/
     435
     436
    390437/* <-SEC M1.10.1 */
     438/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     439/* <-QAC 0857 */
     440/* <-QAC 0639 */
    391441#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/ether_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef ETHER_IODEFINE_H
    3030#define ETHER_IODEFINE_H
    3131/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3234/* ->SEC M1.10.1 : Not magic number */
    3335
    34 struct st_ether
    35 {                                                          /* ETHER            */
     36#define ETHER   (*(struct st_ether   *)0xE8203000uL) /* ETHER */
     37
     38
     39/* Start of channel array defines of ETHER */
     40
     41/* Channel array defines of ETHER_FROM_TSU_ADRH0_ARRAY */
     42/*(Sample) value = ETHER_FROM_TSU_ADRH0_ARRAY[ channel ]->TSU_ADRH0; */
     43#define ETHER_FROM_TSU_ADRH0_ARRAY_COUNT  (32)
     44#define ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST \
     45{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     46    &ETHER_FROM_TSU_ADRH0, &ETHER_FROM_TSU_ADRH1, &ETHER_FROM_TSU_ADRH2, &ETHER_FROM_TSU_ADRH3, &ETHER_FROM_TSU_ADRH4, &ETHER_FROM_TSU_ADRH5, &ETHER_FROM_TSU_ADRH6, &ETHER_FROM_TSU_ADRH7, \
     47    &ETHER_FROM_TSU_ADRH8, &ETHER_FROM_TSU_ADRH9, &ETHER_FROM_TSU_ADRH10, &ETHER_FROM_TSU_ADRH11, &ETHER_FROM_TSU_ADRH12, &ETHER_FROM_TSU_ADRH13, &ETHER_FROM_TSU_ADRH14, &ETHER_FROM_TSU_ADRH15, \
     48    &ETHER_FROM_TSU_ADRH16, &ETHER_FROM_TSU_ADRH17, &ETHER_FROM_TSU_ADRH18, &ETHER_FROM_TSU_ADRH19, &ETHER_FROM_TSU_ADRH20, &ETHER_FROM_TSU_ADRH21, &ETHER_FROM_TSU_ADRH22, &ETHER_FROM_TSU_ADRH23, \
     49    &ETHER_FROM_TSU_ADRH24, &ETHER_FROM_TSU_ADRH25, &ETHER_FROM_TSU_ADRH26, &ETHER_FROM_TSU_ADRH27, &ETHER_FROM_TSU_ADRH28, &ETHER_FROM_TSU_ADRH29, &ETHER_FROM_TSU_ADRH30, &ETHER_FROM_TSU_ADRH31 \
     50}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     51#define ETHER_FROM_TSU_ADRH0 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH0) /* ETHER_FROM_TSU_ADRH0 */
     52#define ETHER_FROM_TSU_ADRH1 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH1) /* ETHER_FROM_TSU_ADRH1 */
     53#define ETHER_FROM_TSU_ADRH2 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH2) /* ETHER_FROM_TSU_ADRH2 */
     54#define ETHER_FROM_TSU_ADRH3 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH3) /* ETHER_FROM_TSU_ADRH3 */
     55#define ETHER_FROM_TSU_ADRH4 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH4) /* ETHER_FROM_TSU_ADRH4 */
     56#define ETHER_FROM_TSU_ADRH5 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH5) /* ETHER_FROM_TSU_ADRH5 */
     57#define ETHER_FROM_TSU_ADRH6 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH6) /* ETHER_FROM_TSU_ADRH6 */
     58#define ETHER_FROM_TSU_ADRH7 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH7) /* ETHER_FROM_TSU_ADRH7 */
     59#define ETHER_FROM_TSU_ADRH8 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH8) /* ETHER_FROM_TSU_ADRH8 */
     60#define ETHER_FROM_TSU_ADRH9 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH9) /* ETHER_FROM_TSU_ADRH9 */
     61#define ETHER_FROM_TSU_ADRH10 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH10) /* ETHER_FROM_TSU_ADRH10 */
     62#define ETHER_FROM_TSU_ADRH11 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH11) /* ETHER_FROM_TSU_ADRH11 */
     63#define ETHER_FROM_TSU_ADRH12 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH12) /* ETHER_FROM_TSU_ADRH12 */
     64#define ETHER_FROM_TSU_ADRH13 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH13) /* ETHER_FROM_TSU_ADRH13 */
     65#define ETHER_FROM_TSU_ADRH14 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH14) /* ETHER_FROM_TSU_ADRH14 */
     66#define ETHER_FROM_TSU_ADRH15 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH15) /* ETHER_FROM_TSU_ADRH15 */
     67#define ETHER_FROM_TSU_ADRH16 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH16) /* ETHER_FROM_TSU_ADRH16 */
     68#define ETHER_FROM_TSU_ADRH17 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH17) /* ETHER_FROM_TSU_ADRH17 */
     69#define ETHER_FROM_TSU_ADRH18 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH18) /* ETHER_FROM_TSU_ADRH18 */
     70#define ETHER_FROM_TSU_ADRH19 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH19) /* ETHER_FROM_TSU_ADRH19 */
     71#define ETHER_FROM_TSU_ADRH20 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH20) /* ETHER_FROM_TSU_ADRH20 */
     72#define ETHER_FROM_TSU_ADRH21 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH21) /* ETHER_FROM_TSU_ADRH21 */
     73#define ETHER_FROM_TSU_ADRH22 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH22) /* ETHER_FROM_TSU_ADRH22 */
     74#define ETHER_FROM_TSU_ADRH23 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH23) /* ETHER_FROM_TSU_ADRH23 */
     75#define ETHER_FROM_TSU_ADRH24 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH24) /* ETHER_FROM_TSU_ADRH24 */
     76#define ETHER_FROM_TSU_ADRH25 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH25) /* ETHER_FROM_TSU_ADRH25 */
     77#define ETHER_FROM_TSU_ADRH26 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH26) /* ETHER_FROM_TSU_ADRH26 */
     78#define ETHER_FROM_TSU_ADRH27 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH27) /* ETHER_FROM_TSU_ADRH27 */
     79#define ETHER_FROM_TSU_ADRH28 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH28) /* ETHER_FROM_TSU_ADRH28 */
     80#define ETHER_FROM_TSU_ADRH29 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH29) /* ETHER_FROM_TSU_ADRH29 */
     81#define ETHER_FROM_TSU_ADRH30 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH30) /* ETHER_FROM_TSU_ADRH30 */
     82#define ETHER_FROM_TSU_ADRH31 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH31) /* ETHER_FROM_TSU_ADRH31 */
     83
     84/* End of channel array defines of ETHER */
     85
     86
     87#define ETHEREDSR0 (ETHER.EDSR0)
     88#define ETHERTDLAR0 (ETHER.TDLAR0)
     89#define ETHERTDFAR0 (ETHER.TDFAR0)
     90#define ETHERTDFXR0 (ETHER.TDFXR0)
     91#define ETHERTDFFR0 (ETHER.TDFFR0)
     92#define ETHERRDLAR0 (ETHER.RDLAR0)
     93#define ETHERRDFAR0 (ETHER.RDFAR0)
     94#define ETHERRDFXR0 (ETHER.RDFXR0)
     95#define ETHERRDFFR0 (ETHER.RDFFR0)
     96#define ETHEREDMR0 (ETHER.EDMR0)
     97#define ETHEREDTRR0 (ETHER.EDTRR0)
     98#define ETHEREDRRR0 (ETHER.EDRRR0)
     99#define ETHEREESR0 (ETHER.EESR0)
     100#define ETHEREESIPR0 (ETHER.EESIPR0)
     101#define ETHERTRSCER0 (ETHER.TRSCER0)
     102#define ETHERRMFCR0 (ETHER.RMFCR0)
     103#define ETHERTFTR0 (ETHER.TFTR0)
     104#define ETHERFDR0 (ETHER.FDR0)
     105#define ETHERRMCR0 (ETHER.RMCR0)
     106#define ETHERRPADIR0 (ETHER.RPADIR0)
     107#define ETHERFCFTR0 (ETHER.FCFTR0)
     108#define ETHERCSMR (ETHER.CSMR)
     109#define ETHERCSSBM (ETHER.CSSBM)
     110#define ETHERCSSMR (ETHER.CSSMR)
     111#define ETHERECMR0 (ETHER.ECMR0)
     112#define ETHERRFLR0 (ETHER.RFLR0)
     113#define ETHERECSR0 (ETHER.ECSR0)
     114#define ETHERECSIPR0 (ETHER.ECSIPR0)
     115#define ETHERPIR0 (ETHER.PIR0)
     116#define ETHERAPR0 (ETHER.APR0)
     117#define ETHERMPR0 (ETHER.MPR0)
     118#define ETHERPFTCR0 (ETHER.PFTCR0)
     119#define ETHERPFRCR0 (ETHER.PFRCR0)
     120#define ETHERTPAUSER0 (ETHER.TPAUSER0)
     121#define ETHERMAHR0 (ETHER.MAHR0)
     122#define ETHERMALR0 (ETHER.MALR0)
     123#define ETHERCEFCR0 (ETHER.CEFCR0)
     124#define ETHERFRECR0 (ETHER.FRECR0)
     125#define ETHERTSFRCR0 (ETHER.TSFRCR0)
     126#define ETHERTLFRCR0 (ETHER.TLFRCR0)
     127#define ETHERRFCR0 (ETHER.RFCR0)
     128#define ETHERMAFCR0 (ETHER.MAFCR0)
     129#define ETHERARSTR (ETHER.ARSTR)
     130#define ETHERTSU_CTRST (ETHER.TSU_CTRST)
     131#define ETHERTSU_VTAG0 (ETHER.TSU_VTAG0)
     132#define ETHERTSU_ADSBSY (ETHER.TSU_ADSBSY)
     133#define ETHERTSU_TEN (ETHER.TSU_TEN)
     134#define ETHERTXNLCR0 (ETHER.TXNLCR0)
     135#define ETHERTXALCR0 (ETHER.TXALCR0)
     136#define ETHERRXNLCR0 (ETHER.RXNLCR0)
     137#define ETHERRXALCR0 (ETHER.RXALCR0)
     138#define ETHERTSU_ADRH0 (ETHER.TSU_ADRH0)
     139#define ETHERTSU_ADRL0 (ETHER.TSU_ADRL0)
     140#define ETHERTSU_ADRH1 (ETHER.TSU_ADRH1)
     141#define ETHERTSU_ADRL1 (ETHER.TSU_ADRL1)
     142#define ETHERTSU_ADRH2 (ETHER.TSU_ADRH2)
     143#define ETHERTSU_ADRL2 (ETHER.TSU_ADRL2)
     144#define ETHERTSU_ADRH3 (ETHER.TSU_ADRH3)
     145#define ETHERTSU_ADRL3 (ETHER.TSU_ADRL3)
     146#define ETHERTSU_ADRH4 (ETHER.TSU_ADRH4)
     147#define ETHERTSU_ADRL4 (ETHER.TSU_ADRL4)
     148#define ETHERTSU_ADRH5 (ETHER.TSU_ADRH5)
     149#define ETHERTSU_ADRL5 (ETHER.TSU_ADRL5)
     150#define ETHERTSU_ADRH6 (ETHER.TSU_ADRH6)
     151#define ETHERTSU_ADRL6 (ETHER.TSU_ADRL6)
     152#define ETHERTSU_ADRH7 (ETHER.TSU_ADRH7)
     153#define ETHERTSU_ADRL7 (ETHER.TSU_ADRL7)
     154#define ETHERTSU_ADRH8 (ETHER.TSU_ADRH8)
     155#define ETHERTSU_ADRL8 (ETHER.TSU_ADRL8)
     156#define ETHERTSU_ADRH9 (ETHER.TSU_ADRH9)
     157#define ETHERTSU_ADRL9 (ETHER.TSU_ADRL9)
     158#define ETHERTSU_ADRH10 (ETHER.TSU_ADRH10)
     159#define ETHERTSU_ADRL10 (ETHER.TSU_ADRL10)
     160#define ETHERTSU_ADRH11 (ETHER.TSU_ADRH11)
     161#define ETHERTSU_ADRL11 (ETHER.TSU_ADRL11)
     162#define ETHERTSU_ADRH12 (ETHER.TSU_ADRH12)
     163#define ETHERTSU_ADRL12 (ETHER.TSU_ADRL12)
     164#define ETHERTSU_ADRH13 (ETHER.TSU_ADRH13)
     165#define ETHERTSU_ADRL13 (ETHER.TSU_ADRL13)
     166#define ETHERTSU_ADRH14 (ETHER.TSU_ADRH14)
     167#define ETHERTSU_ADRL14 (ETHER.TSU_ADRL14)
     168#define ETHERTSU_ADRH15 (ETHER.TSU_ADRH15)
     169#define ETHERTSU_ADRL15 (ETHER.TSU_ADRL15)
     170#define ETHERTSU_ADRH16 (ETHER.TSU_ADRH16)
     171#define ETHERTSU_ADRL16 (ETHER.TSU_ADRL16)
     172#define ETHERTSU_ADRH17 (ETHER.TSU_ADRH17)
     173#define ETHERTSU_ADRL17 (ETHER.TSU_ADRL17)
     174#define ETHERTSU_ADRH18 (ETHER.TSU_ADRH18)
     175#define ETHERTSU_ADRL18 (ETHER.TSU_ADRL18)
     176#define ETHERTSU_ADRH19 (ETHER.TSU_ADRH19)
     177#define ETHERTSU_ADRL19 (ETHER.TSU_ADRL19)
     178#define ETHERTSU_ADRH20 (ETHER.TSU_ADRH20)
     179#define ETHERTSU_ADRL20 (ETHER.TSU_ADRL20)
     180#define ETHERTSU_ADRH21 (ETHER.TSU_ADRH21)
     181#define ETHERTSU_ADRL21 (ETHER.TSU_ADRL21)
     182#define ETHERTSU_ADRH22 (ETHER.TSU_ADRH22)
     183#define ETHERTSU_ADRL22 (ETHER.TSU_ADRL22)
     184#define ETHERTSU_ADRH23 (ETHER.TSU_ADRH23)
     185#define ETHERTSU_ADRL23 (ETHER.TSU_ADRL23)
     186#define ETHERTSU_ADRH24 (ETHER.TSU_ADRH24)
     187#define ETHERTSU_ADRL24 (ETHER.TSU_ADRL24)
     188#define ETHERTSU_ADRH25 (ETHER.TSU_ADRH25)
     189#define ETHERTSU_ADRL25 (ETHER.TSU_ADRL25)
     190#define ETHERTSU_ADRH26 (ETHER.TSU_ADRH26)
     191#define ETHERTSU_ADRL26 (ETHER.TSU_ADRL26)
     192#define ETHERTSU_ADRH27 (ETHER.TSU_ADRH27)
     193#define ETHERTSU_ADRL27 (ETHER.TSU_ADRL27)
     194#define ETHERTSU_ADRH28 (ETHER.TSU_ADRH28)
     195#define ETHERTSU_ADRL28 (ETHER.TSU_ADRL28)
     196#define ETHERTSU_ADRH29 (ETHER.TSU_ADRH29)
     197#define ETHERTSU_ADRL29 (ETHER.TSU_ADRL29)
     198#define ETHERTSU_ADRH30 (ETHER.TSU_ADRH30)
     199#define ETHERTSU_ADRL30 (ETHER.TSU_ADRL30)
     200#define ETHERTSU_ADRH31 (ETHER.TSU_ADRH31)
     201#define ETHERTSU_ADRL31 (ETHER.TSU_ADRL31)
     202
     203
     204typedef struct st_ether
     205{
     206                                                           /* ETHER            */
    36207    volatile uint32_t  EDSR0;                                  /*  EDSR0           */
    37208    volatile uint8_t   dummy207[12];                           /*                  */
    … …  
    119290    volatile uint32_t  RXALCR0;                                /*  RXALCR0         */
    120291    volatile uint8_t   dummy240[112];                          /*                  */
     292
    121293/* start of struct st_ether_from_tsu_adrh0 */
    122294    volatile uint32_t  TSU_ADRH0;                              /*  TSU_ADRH0       */
    123295    volatile uint32_t  TSU_ADRL0;                              /*  TSU_ADRL0       */
    124 /* end of struct st_ether_from_tsu_adrh0 */
     296
     297/* end of struct st_ether_from_tsu_adrh0 */
     298
    125299/* start of struct st_ether_from_tsu_adrh0 */
    126300    volatile uint32_t  TSU_ADRH1;                              /*  TSU_ADRH1       */
    127301    volatile uint32_t  TSU_ADRL1;                              /*  TSU_ADRL1       */
    128 /* end of struct st_ether_from_tsu_adrh0 */
     302
     303/* end of struct st_ether_from_tsu_adrh0 */
     304
    129305/* start of struct st_ether_from_tsu_adrh0 */
    130306    volatile uint32_t  TSU_ADRH2;                              /*  TSU_ADRH2       */
    131307    volatile uint32_t  TSU_ADRL2;                              /*  TSU_ADRL2       */
    132 /* end of struct st_ether_from_tsu_adrh0 */
     308
     309/* end of struct st_ether_from_tsu_adrh0 */
     310
    133311/* start of struct st_ether_from_tsu_adrh0 */
    134312    volatile uint32_t  TSU_ADRH3;                              /*  TSU_ADRH3       */
    135313    volatile uint32_t  TSU_ADRL3;                              /*  TSU_ADRL3       */
    136 /* end of struct st_ether_from_tsu_adrh0 */
     314
     315/* end of struct st_ether_from_tsu_adrh0 */
     316
    137317/* start of struct st_ether_from_tsu_adrh0 */
    138318    volatile uint32_t  TSU_ADRH4;                              /*  TSU_ADRH4       */
    139319    volatile uint32_t  TSU_ADRL4;                              /*  TSU_ADRL4       */
    140 /* end of struct st_ether_from_tsu_adrh0 */
     320
     321/* end of struct st_ether_from_tsu_adrh0 */
     322
    141323/* start of struct st_ether_from_tsu_adrh0 */
    142324    volatile uint32_t  TSU_ADRH5;                              /*  TSU_ADRH5       */
    143325    volatile uint32_t  TSU_ADRL5;                              /*  TSU_ADRL5       */
    144 /* end of struct st_ether_from_tsu_adrh0 */
     326
     327/* end of struct st_ether_from_tsu_adrh0 */
     328
    145329/* start of struct st_ether_from_tsu_adrh0 */
    146330    volatile uint32_t  TSU_ADRH6;                              /*  TSU_ADRH6       */
    147331    volatile uint32_t  TSU_ADRL6;                              /*  TSU_ADRL6       */
    148 /* end of struct st_ether_from_tsu_adrh0 */
     332
     333/* end of struct st_ether_from_tsu_adrh0 */
     334
    149335/* start of struct st_ether_from_tsu_adrh0 */
    150336    volatile uint32_t  TSU_ADRH7;                              /*  TSU_ADRH7       */
    151337    volatile uint32_t  TSU_ADRL7;                              /*  TSU_ADRL7       */
    152 /* end of struct st_ether_from_tsu_adrh0 */
     338
     339/* end of struct st_ether_from_tsu_adrh0 */
     340
    153341/* start of struct st_ether_from_tsu_adrh0 */
    154342    volatile uint32_t  TSU_ADRH8;                              /*  TSU_ADRH8       */
    155343    volatile uint32_t  TSU_ADRL8;                              /*  TSU_ADRL8       */
    156 /* end of struct st_ether_from_tsu_adrh0 */
     344
     345/* end of struct st_ether_from_tsu_adrh0 */
     346
    157347/* start of struct st_ether_from_tsu_adrh0 */
    158348    volatile uint32_t  TSU_ADRH9;                              /*  TSU_ADRH9       */
    159349    volatile uint32_t  TSU_ADRL9;                              /*  TSU_ADRL9       */
    160 /* end of struct st_ether_from_tsu_adrh0 */
     350
     351/* end of struct st_ether_from_tsu_adrh0 */
     352
    161353/* start of struct st_ether_from_tsu_adrh0 */
    162354    volatile uint32_t  TSU_ADRH10;                             /*  TSU_ADRH10      */
    163355    volatile uint32_t  TSU_ADRL10;                             /*  TSU_ADRL10      */
    164 /* end of struct st_ether_from_tsu_adrh0 */
     356
     357/* end of struct st_ether_from_tsu_adrh0 */
     358
    165359/* start of struct st_ether_from_tsu_adrh0 */
    166360    volatile uint32_t  TSU_ADRH11;                             /*  TSU_ADRH11      */
    167361    volatile uint32_t  TSU_ADRL11;                             /*  TSU_ADRL11      */
    168 /* end of struct st_ether_from_tsu_adrh0 */
     362
     363/* end of struct st_ether_from_tsu_adrh0 */
     364
    169365/* start of struct st_ether_from_tsu_adrh0 */
    170366    volatile uint32_t  TSU_ADRH12;                             /*  TSU_ADRH12      */
    171367    volatile uint32_t  TSU_ADRL12;                             /*  TSU_ADRL12      */
    172 /* end of struct st_ether_from_tsu_adrh0 */
     368
     369/* end of struct st_ether_from_tsu_adrh0 */
     370
    173371/* start of struct st_ether_from_tsu_adrh0 */
    174372    volatile uint32_t  TSU_ADRH13;                             /*  TSU_ADRH13      */
    175373    volatile uint32_t  TSU_ADRL13;                             /*  TSU_ADRL13      */
    176 /* end of struct st_ether_from_tsu_adrh0 */
     374
     375/* end of struct st_ether_from_tsu_adrh0 */
     376
    177377/* start of struct st_ether_from_tsu_adrh0 */
    178378    volatile uint32_t  TSU_ADRH14;                             /*  TSU_ADRH14      */
    179379    volatile uint32_t  TSU_ADRL14;                             /*  TSU_ADRL14      */
    180 /* end of struct st_ether_from_tsu_adrh0 */
     380
     381/* end of struct st_ether_from_tsu_adrh0 */
     382
    181383/* start of struct st_ether_from_tsu_adrh0 */
    182384    volatile uint32_t  TSU_ADRH15;                             /*  TSU_ADRH15      */
    183385    volatile uint32_t  TSU_ADRL15;                             /*  TSU_ADRL15      */
    184 /* end of struct st_ether_from_tsu_adrh0 */
     386
     387/* end of struct st_ether_from_tsu_adrh0 */
     388
    185389/* start of struct st_ether_from_tsu_adrh0 */
    186390    volatile uint32_t  TSU_ADRH16;                             /*  TSU_ADRH16      */
    187391    volatile uint32_t  TSU_ADRL16;                             /*  TSU_ADRL16      */
    188 /* end of struct st_ether_from_tsu_adrh0 */
     392
     393/* end of struct st_ether_from_tsu_adrh0 */
     394
    189395/* start of struct st_ether_from_tsu_adrh0 */
    190396    volatile uint32_t  TSU_ADRH17;                             /*  TSU_ADRH17      */
    191397    volatile uint32_t  TSU_ADRL17;                             /*  TSU_ADRL17      */
    192 /* end of struct st_ether_from_tsu_adrh0 */
     398
     399/* end of struct st_ether_from_tsu_adrh0 */
     400
    193401/* start of struct st_ether_from_tsu_adrh0 */
    194402    volatile uint32_t  TSU_ADRH18;                             /*  TSU_ADRH18      */
    195403    volatile uint32_t  TSU_ADRL18;                             /*  TSU_ADRL18      */
    196 /* end of struct st_ether_from_tsu_adrh0 */
     404
     405/* end of struct st_ether_from_tsu_adrh0 */
     406
    197407/* start of struct st_ether_from_tsu_adrh0 */
    198408    volatile uint32_t  TSU_ADRH19;                             /*  TSU_ADRH19      */
    199409    volatile uint32_t  TSU_ADRL19;                             /*  TSU_ADRL19      */
    200 /* end of struct st_ether_from_tsu_adrh0 */
     410
     411/* end of struct st_ether_from_tsu_adrh0 */
     412
    201413/* start of struct st_ether_from_tsu_adrh0 */
    202414    volatile uint32_t  TSU_ADRH20;                             /*  TSU_ADRH20      */
    203415    volatile uint32_t  TSU_ADRL20;                             /*  TSU_ADRL20      */
    204 /* end of struct st_ether_from_tsu_adrh0 */
     416
     417/* end of struct st_ether_from_tsu_adrh0 */
     418
    205419/* start of struct st_ether_from_tsu_adrh0 */
    206420    volatile uint32_t  TSU_ADRH21;                             /*  TSU_ADRH21      */
    207421    volatile uint32_t  TSU_ADRL21;                             /*  TSU_ADRL21      */
    208 /* end of struct st_ether_from_tsu_adrh0 */
     422
     423/* end of struct st_ether_from_tsu_adrh0 */
     424
    209425/* start of struct st_ether_from_tsu_adrh0 */
    210426    volatile uint32_t  TSU_ADRH22;                             /*  TSU_ADRH22      */
    211427    volatile uint32_t  TSU_ADRL22;                             /*  TSU_ADRL22      */
    212 /* end of struct st_ether_from_tsu_adrh0 */
     428
     429/* end of struct st_ether_from_tsu_adrh0 */
     430
    213431/* start of struct st_ether_from_tsu_adrh0 */
    214432    volatile uint32_t  TSU_ADRH23;                             /*  TSU_ADRH23      */
    215433    volatile uint32_t  TSU_ADRL23;                             /*  TSU_ADRL23      */
    216 /* end of struct st_ether_from_tsu_adrh0 */
     434
     435/* end of struct st_ether_from_tsu_adrh0 */
     436
    217437/* start of struct st_ether_from_tsu_adrh0 */
    218438    volatile uint32_t  TSU_ADRH24;                             /*  TSU_ADRH24      */
    219439    volatile uint32_t  TSU_ADRL24;                             /*  TSU_ADRL24      */
    220 /* end of struct st_ether_from_tsu_adrh0 */
     440
     441/* end of struct st_ether_from_tsu_adrh0 */
     442
    221443/* start of struct st_ether_from_tsu_adrh0 */
    222444    volatile uint32_t  TSU_ADRH25;                             /*  TSU_ADRH25      */
    223445    volatile uint32_t  TSU_ADRL25;                             /*  TSU_ADRL25      */
    224 /* end of struct st_ether_from_tsu_adrh0 */
     446
     447/* end of struct st_ether_from_tsu_adrh0 */
     448
    225449/* start of struct st_ether_from_tsu_adrh0 */
    226450    volatile uint32_t  TSU_ADRH26;                             /*  TSU_ADRH26      */
    227451    volatile uint32_t  TSU_ADRL26;                             /*  TSU_ADRL26      */
    228 /* end of struct st_ether_from_tsu_adrh0 */
     452
     453/* end of struct st_ether_from_tsu_adrh0 */
     454
    229455/* start of struct st_ether_from_tsu_adrh0 */
    230456    volatile uint32_t  TSU_ADRH27;                             /*  TSU_ADRH27      */
    231457    volatile uint32_t  TSU_ADRL27;                             /*  TSU_ADRL27      */
    232 /* end of struct st_ether_from_tsu_adrh0 */
     458
     459/* end of struct st_ether_from_tsu_adrh0 */
     460
    233461/* start of struct st_ether_from_tsu_adrh0 */
    234462    volatile uint32_t  TSU_ADRH28;                             /*  TSU_ADRH28      */
    235463    volatile uint32_t  TSU_ADRL28;                             /*  TSU_ADRL28      */
    236 /* end of struct st_ether_from_tsu_adrh0 */
     464
     465/* end of struct st_ether_from_tsu_adrh0 */
     466
    237467/* start of struct st_ether_from_tsu_adrh0 */
    238468    volatile uint32_t  TSU_ADRH29;                             /*  TSU_ADRH29      */
    239469    volatile uint32_t  TSU_ADRL29;                             /*  TSU_ADRL29      */
    240 /* end of struct st_ether_from_tsu_adrh0 */
     470
     471/* end of struct st_ether_from_tsu_adrh0 */
     472
    241473/* start of struct st_ether_from_tsu_adrh0 */
    242474    volatile uint32_t  TSU_ADRH30;                             /*  TSU_ADRH30      */
    243475    volatile uint32_t  TSU_ADRL30;                             /*  TSU_ADRL30      */
    244 /* end of struct st_ether_from_tsu_adrh0 */
     476
     477/* end of struct st_ether_from_tsu_adrh0 */
     478
    245479/* start of struct st_ether_from_tsu_adrh0 */
    246480    volatile uint32_t  TSU_ADRH31;                             /*  TSU_ADRH31      */
    247481    volatile uint32_t  TSU_ADRL31;                             /*  TSU_ADRL31      */
    248 /* end of struct st_ether_from_tsu_adrh0 */
    249 };
    250 
    251 
    252 struct st_ether_from_tsu_adrh0
     482
     483/* end of struct st_ether_from_tsu_adrh0 */
     484} r_io_ether_t;
     485
     486
     487typedef struct st_ether_from_tsu_adrh0
    253488{
     489 
    254490    volatile uint32_t  TSU_ADRH0;                              /*  TSU_ADRH0       */
    255491    volatile uint32_t  TSU_ADRL0;                              /*  TSU_ADRL0       */
    256 };
    257 
    258 
    259 #define ETHER   (*(struct st_ether   *)0xE8203000uL) /* ETHER */
    260 
    261 
    262 /* Start of channnel array defines of ETHER */
    263 
    264 /* Channnel array defines of ETHER_FROM_TSU_ADRH0_ARRAY */
    265 /*(Sample) value = ETHER_FROM_TSU_ADRH0_ARRAY[ channel ]->TSU_ADRH0; */
    266 #define ETHER_FROM_TSU_ADRH0_ARRAY_COUNT  32
    267 #define ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST \
    268 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    269     &ETHER_FROM_TSU_ADRH0, &ETHER_FROM_TSU_ADRH1, &ETHER_FROM_TSU_ADRH2, &ETHER_FROM_TSU_ADRH3, &ETHER_FROM_TSU_ADRH4, &ETHER_FROM_TSU_ADRH5, &ETHER_FROM_TSU_ADRH6, &ETHER_FROM_TSU_ADRH7, \
    270     &ETHER_FROM_TSU_ADRH8, &ETHER_FROM_TSU_ADRH9, &ETHER_FROM_TSU_ADRH10, &ETHER_FROM_TSU_ADRH11, &ETHER_FROM_TSU_ADRH12, &ETHER_FROM_TSU_ADRH13, &ETHER_FROM_TSU_ADRH14, &ETHER_FROM_TSU_ADRH15, \
    271     &ETHER_FROM_TSU_ADRH16, &ETHER_FROM_TSU_ADRH17, &ETHER_FROM_TSU_ADRH18, &ETHER_FROM_TSU_ADRH19, &ETHER_FROM_TSU_ADRH20, &ETHER_FROM_TSU_ADRH21, &ETHER_FROM_TSU_ADRH22, &ETHER_FROM_TSU_ADRH23, \
    272     &ETHER_FROM_TSU_ADRH24, &ETHER_FROM_TSU_ADRH25, &ETHER_FROM_TSU_ADRH26, &ETHER_FROM_TSU_ADRH27, &ETHER_FROM_TSU_ADRH28, &ETHER_FROM_TSU_ADRH29, &ETHER_FROM_TSU_ADRH30, &ETHER_FROM_TSU_ADRH31 \
    273 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    274 #define ETHER_FROM_TSU_ADRH0 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH0) /* ETHER_FROM_TSU_ADRH0 */
    275 #define ETHER_FROM_TSU_ADRH1 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH1) /* ETHER_FROM_TSU_ADRH1 */
    276 #define ETHER_FROM_TSU_ADRH2 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH2) /* ETHER_FROM_TSU_ADRH2 */
    277 #define ETHER_FROM_TSU_ADRH3 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH3) /* ETHER_FROM_TSU_ADRH3 */
    278 #define ETHER_FROM_TSU_ADRH4 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH4) /* ETHER_FROM_TSU_ADRH4 */
    279 #define ETHER_FROM_TSU_ADRH5 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH5) /* ETHER_FROM_TSU_ADRH5 */
    280 #define ETHER_FROM_TSU_ADRH6 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH6) /* ETHER_FROM_TSU_ADRH6 */
    281 #define ETHER_FROM_TSU_ADRH7 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH7) /* ETHER_FROM_TSU_ADRH7 */
    282 #define ETHER_FROM_TSU_ADRH8 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH8) /* ETHER_FROM_TSU_ADRH8 */
    283 #define ETHER_FROM_TSU_ADRH9 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH9) /* ETHER_FROM_TSU_ADRH9 */
    284 #define ETHER_FROM_TSU_ADRH10 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH10) /* ETHER_FROM_TSU_ADRH10 */
    285 #define ETHER_FROM_TSU_ADRH11 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH11) /* ETHER_FROM_TSU_ADRH11 */
    286 #define ETHER_FROM_TSU_ADRH12 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH12) /* ETHER_FROM_TSU_ADRH12 */
    287 #define ETHER_FROM_TSU_ADRH13 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH13) /* ETHER_FROM_TSU_ADRH13 */
    288 #define ETHER_FROM_TSU_ADRH14 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH14) /* ETHER_FROM_TSU_ADRH14 */
    289 #define ETHER_FROM_TSU_ADRH15 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH15) /* ETHER_FROM_TSU_ADRH15 */
    290 #define ETHER_FROM_TSU_ADRH16 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH16) /* ETHER_FROM_TSU_ADRH16 */
    291 #define ETHER_FROM_TSU_ADRH17 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH17) /* ETHER_FROM_TSU_ADRH17 */
    292 #define ETHER_FROM_TSU_ADRH18 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH18) /* ETHER_FROM_TSU_ADRH18 */
    293 #define ETHER_FROM_TSU_ADRH19 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH19) /* ETHER_FROM_TSU_ADRH19 */
    294 #define ETHER_FROM_TSU_ADRH20 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH20) /* ETHER_FROM_TSU_ADRH20 */
    295 #define ETHER_FROM_TSU_ADRH21 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH21) /* ETHER_FROM_TSU_ADRH21 */
    296 #define ETHER_FROM_TSU_ADRH22 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH22) /* ETHER_FROM_TSU_ADRH22 */
    297 #define ETHER_FROM_TSU_ADRH23 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH23) /* ETHER_FROM_TSU_ADRH23 */
    298 #define ETHER_FROM_TSU_ADRH24 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH24) /* ETHER_FROM_TSU_ADRH24 */
    299 #define ETHER_FROM_TSU_ADRH25 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH25) /* ETHER_FROM_TSU_ADRH25 */
    300 #define ETHER_FROM_TSU_ADRH26 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH26) /* ETHER_FROM_TSU_ADRH26 */
    301 #define ETHER_FROM_TSU_ADRH27 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH27) /* ETHER_FROM_TSU_ADRH27 */
    302 #define ETHER_FROM_TSU_ADRH28 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH28) /* ETHER_FROM_TSU_ADRH28 */
    303 #define ETHER_FROM_TSU_ADRH29 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH29) /* ETHER_FROM_TSU_ADRH29 */
    304 #define ETHER_FROM_TSU_ADRH30 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH30) /* ETHER_FROM_TSU_ADRH30 */
    305 #define ETHER_FROM_TSU_ADRH31 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH31) /* ETHER_FROM_TSU_ADRH31 */
    306 
    307 /* End of channnel array defines of ETHER */
    308 
    309 
    310 #define ETHEREDSR0 ETHER.EDSR0
    311 #define ETHERTDLAR0 ETHER.TDLAR0
    312 #define ETHERTDFAR0 ETHER.TDFAR0
    313 #define ETHERTDFXR0 ETHER.TDFXR0
    314 #define ETHERTDFFR0 ETHER.TDFFR0
    315 #define ETHERRDLAR0 ETHER.RDLAR0
    316 #define ETHERRDFAR0 ETHER.RDFAR0
    317 #define ETHERRDFXR0 ETHER.RDFXR0
    318 #define ETHERRDFFR0 ETHER.RDFFR0
    319 #define ETHEREDMR0 ETHER.EDMR0
    320 #define ETHEREDTRR0 ETHER.EDTRR0
    321 #define ETHEREDRRR0 ETHER.EDRRR0
    322 #define ETHEREESR0 ETHER.EESR0
    323 #define ETHEREESIPR0 ETHER.EESIPR0
    324 #define ETHERTRSCER0 ETHER.TRSCER0
    325 #define ETHERRMFCR0 ETHER.RMFCR0
    326 #define ETHERTFTR0 ETHER.TFTR0
    327 #define ETHERFDR0 ETHER.FDR0
    328 #define ETHERRMCR0 ETHER.RMCR0
    329 #define ETHERRPADIR0 ETHER.RPADIR0
    330 #define ETHERFCFTR0 ETHER.FCFTR0
    331 #define ETHERCSMR ETHER.CSMR
    332 #define ETHERCSSBM ETHER.CSSBM
    333 #define ETHERCSSMR ETHER.CSSMR
    334 #define ETHERECMR0 ETHER.ECMR0
    335 #define ETHERRFLR0 ETHER.RFLR0
    336 #define ETHERECSR0 ETHER.ECSR0
    337 #define ETHERECSIPR0 ETHER.ECSIPR0
    338 #define ETHERPIR0 ETHER.PIR0
    339 #define ETHERAPR0 ETHER.APR0
    340 #define ETHERMPR0 ETHER.MPR0
    341 #define ETHERPFTCR0 ETHER.PFTCR0
    342 #define ETHERPFRCR0 ETHER.PFRCR0
    343 #define ETHERTPAUSER0 ETHER.TPAUSER0
    344 #define ETHERMAHR0 ETHER.MAHR0
    345 #define ETHERMALR0 ETHER.MALR0
    346 #define ETHERCEFCR0 ETHER.CEFCR0
    347 #define ETHERFRECR0 ETHER.FRECR0
    348 #define ETHERTSFRCR0 ETHER.TSFRCR0
    349 #define ETHERTLFRCR0 ETHER.TLFRCR0
    350 #define ETHERRFCR0 ETHER.RFCR0
    351 #define ETHERMAFCR0 ETHER.MAFCR0
    352 #define ETHERARSTR ETHER.ARSTR
    353 #define ETHERTSU_CTRST ETHER.TSU_CTRST
    354 #define ETHERTSU_VTAG0 ETHER.TSU_VTAG0
    355 #define ETHERTSU_ADSBSY ETHER.TSU_ADSBSY
    356 #define ETHERTSU_TEN ETHER.TSU_TEN
    357 #define ETHERTXNLCR0 ETHER.TXNLCR0
    358 #define ETHERTXALCR0 ETHER.TXALCR0
    359 #define ETHERRXNLCR0 ETHER.RXNLCR0
    360 #define ETHERRXALCR0 ETHER.RXALCR0
    361 #define ETHERTSU_ADRH0 ETHER.TSU_ADRH0
    362 #define ETHERTSU_ADRL0 ETHER.TSU_ADRL0
    363 #define ETHERTSU_ADRH1 ETHER.TSU_ADRH1
    364 #define ETHERTSU_ADRL1 ETHER.TSU_ADRL1
    365 #define ETHERTSU_ADRH2 ETHER.TSU_ADRH2
    366 #define ETHERTSU_ADRL2 ETHER.TSU_ADRL2
    367 #define ETHERTSU_ADRH3 ETHER.TSU_ADRH3
    368 #define ETHERTSU_ADRL3 ETHER.TSU_ADRL3
    369 #define ETHERTSU_ADRH4 ETHER.TSU_ADRH4
    370 #define ETHERTSU_ADRL4 ETHER.TSU_ADRL4
    371 #define ETHERTSU_ADRH5 ETHER.TSU_ADRH5
    372 #define ETHERTSU_ADRL5 ETHER.TSU_ADRL5
    373 #define ETHERTSU_ADRH6 ETHER.TSU_ADRH6
    374 #define ETHERTSU_ADRL6 ETHER.TSU_ADRL6
    375 #define ETHERTSU_ADRH7 ETHER.TSU_ADRH7
    376 #define ETHERTSU_ADRL7 ETHER.TSU_ADRL7
    377 #define ETHERTSU_ADRH8 ETHER.TSU_ADRH8
    378 #define ETHERTSU_ADRL8 ETHER.TSU_ADRL8
    379 #define ETHERTSU_ADRH9 ETHER.TSU_ADRH9
    380 #define ETHERTSU_ADRL9 ETHER.TSU_ADRL9
    381 #define ETHERTSU_ADRH10 ETHER.TSU_ADRH10
    382 #define ETHERTSU_ADRL10 ETHER.TSU_ADRL10
    383 #define ETHERTSU_ADRH11 ETHER.TSU_ADRH11
    384 #define ETHERTSU_ADRL11 ETHER.TSU_ADRL11
    385 #define ETHERTSU_ADRH12 ETHER.TSU_ADRH12
    386 #define ETHERTSU_ADRL12 ETHER.TSU_ADRL12
    387 #define ETHERTSU_ADRH13 ETHER.TSU_ADRH13
    388 #define ETHERTSU_ADRL13 ETHER.TSU_ADRL13
    389 #define ETHERTSU_ADRH14 ETHER.TSU_ADRH14
    390 #define ETHERTSU_ADRL14 ETHER.TSU_ADRL14
    391 #define ETHERTSU_ADRH15 ETHER.TSU_ADRH15
    392 #define ETHERTSU_ADRL15 ETHER.TSU_ADRL15
    393 #define ETHERTSU_ADRH16 ETHER.TSU_ADRH16
    394 #define ETHERTSU_ADRL16 ETHER.TSU_ADRL16
    395 #define ETHERTSU_ADRH17 ETHER.TSU_ADRH17
    396 #define ETHERTSU_ADRL17 ETHER.TSU_ADRL17
    397 #define ETHERTSU_ADRH18 ETHER.TSU_ADRH18
    398 #define ETHERTSU_ADRL18 ETHER.TSU_ADRL18
    399 #define ETHERTSU_ADRH19 ETHER.TSU_ADRH19
    400 #define ETHERTSU_ADRL19 ETHER.TSU_ADRL19
    401 #define ETHERTSU_ADRH20 ETHER.TSU_ADRH20
    402 #define ETHERTSU_ADRL20 ETHER.TSU_ADRL20
    403 #define ETHERTSU_ADRH21 ETHER.TSU_ADRH21
    404 #define ETHERTSU_ADRL21 ETHER.TSU_ADRL21
    405 #define ETHERTSU_ADRH22 ETHER.TSU_ADRH22
    406 #define ETHERTSU_ADRL22 ETHER.TSU_ADRL22
    407 #define ETHERTSU_ADRH23 ETHER.TSU_ADRH23
    408 #define ETHERTSU_ADRL23 ETHER.TSU_ADRL23
    409 #define ETHERTSU_ADRH24 ETHER.TSU_ADRH24
    410 #define ETHERTSU_ADRL24 ETHER.TSU_ADRL24
    411 #define ETHERTSU_ADRH25 ETHER.TSU_ADRH25
    412 #define ETHERTSU_ADRL25 ETHER.TSU_ADRL25
    413 #define ETHERTSU_ADRH26 ETHER.TSU_ADRH26
    414 #define ETHERTSU_ADRL26 ETHER.TSU_ADRL26
    415 #define ETHERTSU_ADRH27 ETHER.TSU_ADRH27
    416 #define ETHERTSU_ADRL27 ETHER.TSU_ADRL27
    417 #define ETHERTSU_ADRH28 ETHER.TSU_ADRH28
    418 #define ETHERTSU_ADRL28 ETHER.TSU_ADRL28
    419 #define ETHERTSU_ADRH29 ETHER.TSU_ADRH29
    420 #define ETHERTSU_ADRL29 ETHER.TSU_ADRL29
    421 #define ETHERTSU_ADRH30 ETHER.TSU_ADRH30
    422 #define ETHERTSU_ADRL30 ETHER.TSU_ADRL30
    423 #define ETHERTSU_ADRH31 ETHER.TSU_ADRH31
    424 #define ETHERTSU_ADRL31 ETHER.TSU_ADRL31
     492} r_io_ether_from_tsu_adrh0_t;
     493
     494
     495/* Channel array defines of ETHER (2)*/
     496#ifdef  DECLARE_ETHER_FROM_TSU_ADRH0_ARRAY_CHANNELS
     497volatile struct st_ether_from_tsu_adrh0*  ETHER_FROM_TSU_ADRH0_ARRAY[ ETHER_FROM_TSU_ADRH0_ARRAY_COUNT ] =
     498    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     499    ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST;
     500    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     501#endif  /* DECLARE_ETHER_FROM_TSU_ADRH0_ARRAY_CHANNELS */
     502/* End of channel array defines of ETHER (2)*/
     503
     504
    425505/* <-SEC M1.10.1 */
     506/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     507/* <-QAC 0857 */
    426508/* <-QAC 0639 */
    427509#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/flctl_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef FLCTL_IODEFINE_H
    3030#define FLCTL_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3134/* ->SEC M1.10.1 : Not magic number */
    3235
    33 struct st_flctl
    34 {                                                          /* FLCTL            */
     36#define FLCTL   (*(struct st_flctl   *)0xFCFF4000uL) /* FLCTL */
     37
     38
     39#define FLCTLFLCMNCR (FLCTL.FLCMNCR)
     40#define FLCTLFLCMDCR (FLCTL.FLCMDCR)
     41#define FLCTLFLCMCDR (FLCTL.FLCMCDR)
     42#define FLCTLFLADR (FLCTL.FLADR)
     43#define FLCTLFLDATAR (FLCTL.FLDATAR)
     44#define FLCTLFLDTCNTR (FLCTL.FLDTCNTR)
     45#define FLCTLFLINTDMACR (FLCTL.FLINTDMACR)
     46#define FLCTLFLBSYTMR (FLCTL.FLBSYTMR)
     47#define FLCTLFLBSYCNT (FLCTL.FLBSYCNT)
     48#define FLCTLFLTRCR (FLCTL.FLTRCR)
     49#define FLCTLFLADR2 (FLCTL.FLADR2)
     50#define FLCTLFLDTFIFO (FLCTL.FLDTFIFO)
     51
     52
     53typedef struct st_flctl
     54{
     55                                                           /* FLCTL            */
    3556    volatile uint32_t  FLCMNCR;                                /*  FLCMNCR         */
    3657    volatile uint32_t  FLCMDCR;                                /*  FLCMDCR         */
    … …  
    4869    volatile uint8_t   dummy557[16];                           /*                  */
    4970    volatile uint32_t  FLDTFIFO;                               /*  FLDTFIFO        */
    50     volatile uint8_t   dummy558[12];                           /*                  */
    51     volatile uint32_t  FLECFIFO;                               /*  FLECFIFO        */
    52 };
     71} r_io_flctl_t;
    5372
    5473
    55 #define FLCTL   (*(struct st_flctl   *)0xFCFF4000uL) /* FLCTL */
    56 
    57 
    58 #define FLCTLFLCMNCR FLCTL.FLCMNCR
    59 #define FLCTLFLCMDCR FLCTL.FLCMDCR
    60 #define FLCTLFLCMCDR FLCTL.FLCMCDR
    61 #define FLCTLFLADR FLCTL.FLADR
    62 #define FLCTLFLDATAR FLCTL.FLDATAR
    63 #define FLCTLFLDTCNTR FLCTL.FLDTCNTR
    64 #define FLCTLFLINTDMACR FLCTL.FLINTDMACR
    65 #define FLCTLFLBSYTMR FLCTL.FLBSYTMR
    66 #define FLCTLFLBSYCNT FLCTL.FLBSYCNT
    67 #define FLCTLFLTRCR FLCTL.FLTRCR
    68 #define FLCTLFLADR2 FLCTL.FLADR2
    69 #define FLCTLFLDTFIFO FLCTL.FLDTFIFO
    70 #define FLCTLFLECFIFO FLCTL.FLECFIFO
    7174/* <-SEC M1.10.1 */
     75/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     76/* <-QAC 0857 */
     77/* <-QAC 0639 */
    7278#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/gpio_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef GPIO_IODEFINE_H
    3030#define GPIO_IODEFINE_H
    3131/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3234/* ->SEC M1.10.1 : Not magic number */
    3335
    34 struct st_gpio
    35 {                                                          /* GPIO             */
    36 /* start of struct st_gpio_from_p1 */
    37     volatile uint16_t P1;                                     /*  P1              */
    38     volatile uint8_t   dummy348[2];                            /*                  */
    39 /* end of struct st_gpio_from_p1 */
    40 /* start of struct st_gpio_from_p1 */
    41     volatile uint16_t P2;                                     /*  P2              */
    42     volatile uint8_t   dummy349[2];                            /*                  */
    43 /* end of struct st_gpio_from_p1 */
    44 /* start of struct st_gpio_from_p1 */
    45     volatile uint16_t P3;                                     /*  P3              */
    46     volatile uint8_t   dummy350[2];                            /*                  */
    47 /* end of struct st_gpio_from_p1 */
    48 /* start of struct st_gpio_from_p1 */
    49     volatile uint16_t P4;                                     /*  P4              */
    50     volatile uint8_t   dummy351[2];                            /*                  */
    51 /* end of struct st_gpio_from_p1 */
    52 /* start of struct st_gpio_from_p1 */
    53     volatile uint16_t P5;                                     /*  P5              */
    54     volatile uint8_t   dummy352[2];                            /*                  */
    55 /* end of struct st_gpio_from_p1 */
    56 /* start of struct st_gpio_from_p1 */
    57     volatile uint16_t P6;                                     /*  P6              */
    58     volatile uint8_t   dummy353[2];                            /*                  */
    59 /* end of struct st_gpio_from_p1 */
    60 /* start of struct st_gpio_from_p1 */
    61     volatile uint16_t P7;                                     /*  P7              */
    62     volatile uint8_t   dummy354[2];                            /*                  */
    63 /* end of struct st_gpio_from_p1 */
    64 /* start of struct st_gpio_from_p1 */
    65     volatile uint16_t P8;                                     /*  P8              */
    66     volatile uint8_t   dummy355[2];                            /*                  */
    67 /* end of struct st_gpio_from_p1 */
    68 /* start of struct st_gpio_from_p1 */
    69     volatile uint16_t P9;                                     /*  P9              */
    70     volatile uint8_t   dummy356[2];                            /*                  */
    71 /* end of struct st_gpio_from_p1 */
    72 /* start of struct st_gpio_from_p1 */
    73     volatile uint16_t P10;                                    /*  P10             */
    74     volatile uint8_t   dummy357[2];                            /*                  */
    75 /* end of struct st_gpio_from_p1 */
    76 /* start of struct st_gpio_from_p1 */
    77     volatile uint16_t P11;                                    /*  P11             */
    78     volatile uint8_t   dummy3580[2];                           /*                  */
    79 /* end of struct st_gpio_from_p1 */
    80     volatile uint8_t   dummy3581[212];                         /*                  */
    81 #define GPIO_PSRn_COUNT 11
    82     volatile uint32_t  PSR1;                                   /*  PSR1            */
    83     volatile uint32_t  PSR2;                                   /*  PSR2            */
    84     volatile uint32_t  PSR3;                                   /*  PSR3            */
    85     volatile uint32_t  PSR4;                                   /*  PSR4            */
    86     volatile uint32_t  PSR5;                                   /*  PSR5            */
    87     volatile uint32_t  PSR6;                                   /*  PSR6            */
    88     volatile uint32_t  PSR7;                                   /*  PSR7            */
    89     volatile uint32_t  PSR8;                                   /*  PSR8            */
    90     volatile uint32_t  PSR9;                                   /*  PSR9            */
    91     volatile uint32_t  PSR10;                                  /*  PSR10           */
    92     volatile uint32_t  PSR11;                                  /*  PSR11           */
    93     volatile uint8_t   dummy359[208];                          /*                  */
    94 /* start of struct st_gpio_from_ppr0 */
    95     volatile uint16_t PPR0;                                   /*  PPR0            */
    96     volatile uint8_t   dummy360[2];                            /*                  */
    97 /* end of struct st_gpio_from_ppr0 */
    98 /* start of struct st_gpio_from_ppr0 */
    99     volatile uint16_t PPR1;                                   /*  PPR1            */
    100     volatile uint8_t   dummy361[2];                            /*                  */
    101 /* end of struct st_gpio_from_ppr0 */
    102 /* start of struct st_gpio_from_ppr0 */
    103     volatile uint16_t PPR2;                                   /*  PPR2            */
    104     volatile uint8_t   dummy362[2];                            /*                  */
    105 /* end of struct st_gpio_from_ppr0 */
    106 /* start of struct st_gpio_from_ppr0 */
    107     volatile uint16_t PPR3;                                   /*  PPR3            */
    108     volatile uint8_t   dummy363[2];                            /*                  */
    109 /* end of struct st_gpio_from_ppr0 */
    110 /* start of struct st_gpio_from_ppr0 */
    111     volatile uint16_t PPR4;                                   /*  PPR4            */
    112     volatile uint8_t   dummy364[2];                            /*                  */
    113 /* end of struct st_gpio_from_ppr0 */
    114 /* start of struct st_gpio_from_ppr0 */
    115     volatile uint16_t PPR5;                                   /*  PPR5            */
    116     volatile uint8_t   dummy365[2];                            /*                  */
    117 /* end of struct st_gpio_from_ppr0 */
    118 /* start of struct st_gpio_from_ppr0 */
    119     volatile uint16_t PPR6;                                   /*  PPR6            */
    120     volatile uint8_t   dummy366[2];                            /*                  */
    121 /* end of struct st_gpio_from_ppr0 */
    122 /* start of struct st_gpio_from_ppr0 */
    123     volatile uint16_t PPR7;                                   /*  PPR7            */
    124     volatile uint8_t   dummy367[2];                            /*                  */
    125 /* end of struct st_gpio_from_ppr0 */
    126 /* start of struct st_gpio_from_ppr0 */
    127     volatile uint16_t PPR8;                                   /*  PPR8            */
    128     volatile uint8_t   dummy368[2];                            /*                  */
    129 /* end of struct st_gpio_from_ppr0 */
    130 /* start of struct st_gpio_from_ppr0 */
    131     volatile uint16_t PPR9;                                   /*  PPR9            */
    132     volatile uint8_t   dummy369[2];                            /*                  */
    133 /* end of struct st_gpio_from_ppr0 */
    134 /* start of struct st_gpio_from_ppr0 */
    135     volatile uint16_t PPR10;                                  /*  PPR10           */
    136     volatile uint8_t   dummy370[2];                            /*                  */
    137 /* end of struct st_gpio_from_ppr0 */
    138 /* start of struct st_gpio_from_ppr0 */
    139     volatile uint16_t PPR11;                                  /*  PPR11           */
    140     volatile uint8_t   dummy3710[2];                           /*                  */
    141 /* end of struct st_gpio_from_ppr0 */
    142     volatile uint8_t   dummy3711[212];                         /*                  */
    143 /* start of struct st_gpio_from_pm1 */
    144     volatile uint16_t PM1;                                    /*  PM1             */
    145     volatile uint8_t   dummy372[2];                            /*                  */
    146 /* end of struct st_gpio_from_pm1 */
    147 /* start of struct st_gpio_from_pm1 */
    148     volatile uint16_t PM2;                                    /*  PM2             */
    149     volatile uint8_t   dummy373[2];                            /*                  */
    150 /* end of struct st_gpio_from_pm1 */
    151 /* start of struct st_gpio_from_pm1 */
    152     volatile uint16_t PM3;                                    /*  PM3             */
    153     volatile uint8_t   dummy374[2];                            /*                  */
    154 /* end of struct st_gpio_from_pm1 */
    155 /* start of struct st_gpio_from_pm1 */
    156     volatile uint16_t PM4;                                    /*  PM4             */
    157     volatile uint8_t   dummy375[2];                            /*                  */
    158 /* end of struct st_gpio_from_pm1 */
    159 /* start of struct st_gpio_from_pm1 */
    160     volatile uint16_t PM5;                                    /*  PM5             */
    161     volatile uint8_t   dummy376[2];                            /*                  */
    162 /* end of struct st_gpio_from_pm1 */
    163 /* start of struct st_gpio_from_pm1 */
    164     volatile uint16_t PM6;                                    /*  PM6             */
    165     volatile uint8_t   dummy377[2];                            /*                  */
    166 /* end of struct st_gpio_from_pm1 */
    167 /* start of struct st_gpio_from_pm1 */
    168     volatile uint16_t PM7;                                    /*  PM7             */
    169     volatile uint8_t   dummy378[2];                            /*                  */
    170 /* end of struct st_gpio_from_pm1 */
    171 /* start of struct st_gpio_from_pm1 */
    172     volatile uint16_t PM8;                                    /*  PM8             */
    173     volatile uint8_t   dummy379[2];                            /*                  */
    174 /* end of struct st_gpio_from_pm1 */
    175 /* start of struct st_gpio_from_pm1 */
    176     volatile uint16_t PM9;                                    /*  PM9             */
    177     volatile uint8_t   dummy380[2];                            /*                  */
    178 /* end of struct st_gpio_from_pm1 */
    179 /* start of struct st_gpio_from_pm1 */
    180     volatile uint16_t PM10;                                   /*  PM10            */
    181     volatile uint8_t   dummy381[2];                            /*                  */
    182 /* end of struct st_gpio_from_pm1 */
    183 /* start of struct st_gpio_from_pm1 */
    184     volatile uint16_t PM11;                                   /*  PM11            */
    185     volatile uint8_t   dummy3820[2];                           /*                  */
    186 /* end of struct st_gpio_from_pm1 */
    187     volatile uint8_t   dummy3821[208];                         /*                  */
    188 /* start of struct st_gpio_from_pmc0 */
    189     volatile uint16_t PMC0;                                   /*  PMC0            */
    190     volatile uint8_t   dummy383[2];                            /*                  */
    191 /* end of struct st_gpio_from_pmc0 */
    192 /* start of struct st_gpio_from_pmc0 */
    193     volatile uint16_t PMC1;                                   /*  PMC1            */
    194     volatile uint8_t   dummy384[2];                            /*                  */
    195 /* end of struct st_gpio_from_pmc0 */
    196 /* start of struct st_gpio_from_pmc0 */
    197     volatile uint16_t PMC2;                                   /*  PMC2            */
    198     volatile uint8_t   dummy385[2];                            /*                  */
    199 /* end of struct st_gpio_from_pmc0 */
    200 /* start of struct st_gpio_from_pmc0 */
    201     volatile uint16_t PMC3;                                   /*  PMC3            */
    202     volatile uint8_t   dummy386[2];                            /*                  */
    203 /* end of struct st_gpio_from_pmc0 */
    204 /* start of struct st_gpio_from_pmc0 */
    205     volatile uint16_t PMC4;                                   /*  PMC4            */
    206     volatile uint8_t   dummy387[2];                            /*                  */
    207 /* end of struct st_gpio_from_pmc0 */
    208 /* start of struct st_gpio_from_pmc0 */
    209     volatile uint16_t PMC5;                                   /*  PMC5            */
    210     volatile uint8_t   dummy388[2];                            /*                  */
    211 /* end of struct st_gpio_from_pmc0 */
    212 /* start of struct st_gpio_from_pmc0 */
    213     volatile uint16_t PMC6;                                   /*  PMC6            */
    214     volatile uint8_t   dummy389[2];                            /*                  */
    215 /* end of struct st_gpio_from_pmc0 */
    216 /* start of struct st_gpio_from_pmc0 */
    217     volatile uint16_t PMC7;                                   /*  PMC7            */
    218     volatile uint8_t   dummy390[2];                            /*                  */
    219 /* end of struct st_gpio_from_pmc0 */
    220 /* start of struct st_gpio_from_pmc0 */
    221     volatile uint16_t PMC8;                                   /*  PMC8            */
    222     volatile uint8_t   dummy391[2];                            /*                  */
    223 /* end of struct st_gpio_from_pmc0 */
    224 /* start of struct st_gpio_from_pmc0 */
    225     volatile uint16_t PMC9;                                   /*  PMC9            */
    226     volatile uint8_t   dummy392[2];                            /*                  */
    227 /* end of struct st_gpio_from_pmc0 */
    228 /* start of struct st_gpio_from_pmc0 */
    229     volatile uint16_t PMC10;                                  /*  PMC10           */
    230     volatile uint8_t   dummy393[2];                            /*                  */
    231 /* end of struct st_gpio_from_pmc0 */
    232 /* start of struct st_gpio_from_pmc0 */
    233     volatile uint16_t PMC11;                                  /*  PMC11           */
    234     volatile uint8_t   dummy3940[2];                           /*                  */
    235 /* end of struct st_gpio_from_pmc0 */
    236     volatile uint8_t   dummy3941[212];                         /*                  */
    237 /* start of struct st_gpio_from_pfc1 */
    238     volatile uint16_t PFC1;                                   /*  PFC1            */
    239     volatile uint8_t   dummy395[2];                            /*                  */
    240 /* end of struct st_gpio_from_pfc1 */
    241 /* start of struct st_gpio_from_pfc1 */
    242     volatile uint16_t PFC2;                                   /*  PFC2            */
    243     volatile uint8_t   dummy396[2];                            /*                  */
    244 /* end of struct st_gpio_from_pfc1 */
    245 /* start of struct st_gpio_from_pfc1 */
    246     volatile uint16_t PFC3;                                   /*  PFC3            */
    247     volatile uint8_t   dummy397[2];                            /*                  */
    248 /* end of struct st_gpio_from_pfc1 */
    249 /* start of struct st_gpio_from_pfc1 */
    250     volatile uint16_t PFC4;                                   /*  PFC4            */
    251     volatile uint8_t   dummy398[2];                            /*                  */
    252 /* end of struct st_gpio_from_pfc1 */
    253 /* start of struct st_gpio_from_pfc1 */
    254     volatile uint16_t PFC5;                                   /*  PFC5            */
    255     volatile uint8_t   dummy399[2];                            /*                  */
    256 /* end of struct st_gpio_from_pfc1 */
    257 /* start of struct st_gpio_from_pfc1 */
    258     volatile uint16_t PFC6;                                   /*  PFC6            */
    259     volatile uint8_t   dummy400[2];                            /*                  */
    260 /* end of struct st_gpio_from_pfc1 */
    261 /* start of struct st_gpio_from_pfc1 */
    262     volatile uint16_t PFC7;                                   /*  PFC7            */
    263     volatile uint8_t   dummy401[2];                            /*                  */
    264 /* end of struct st_gpio_from_pfc1 */
    265 /* start of struct st_gpio_from_pfc1 */
    266     volatile uint16_t PFC8;                                   /*  PFC8            */
    267     volatile uint8_t   dummy402[2];                            /*                  */
    268 /* end of struct st_gpio_from_pfc1 */
    269 /* start of struct st_gpio_from_pfc1 */
    270     volatile uint16_t PFC9;                                   /*  PFC9            */
    271     volatile uint8_t   dummy403[2];                            /*                  */
    272 /* end of struct st_gpio_from_pfc1 */
    273 /* start of struct st_gpio_from_pfc1 */
    274     volatile uint16_t PFC10;                                  /*  PFC10           */
    275     volatile uint8_t   dummy404[2];                            /*                  */
    276 /* end of struct st_gpio_from_pfc1 */
    277 /* start of struct st_gpio_from_pfc1 */
    278     volatile uint16_t PFC11;                                  /*  PFC11           */
    279     volatile uint8_t   dummy4050[2];                           /*                  */
    280 /* end of struct st_gpio_from_pfc1 */
    281     volatile uint8_t   dummy4051[212];                         /*                  */
    282 /* start of struct st_gpio_from_pfce1 */
    283     volatile uint16_t PFCE1;                                  /*  PFCE1           */
    284     volatile uint8_t   dummy406[2];                            /*                  */
    285 /* end of struct st_gpio_from_pfce1 */
    286 /* start of struct st_gpio_from_pfce1 */
    287     volatile uint16_t PFCE2;                                  /*  PFCE2           */
    288     volatile uint8_t   dummy407[2];                            /*                  */
    289 /* end of struct st_gpio_from_pfce1 */
    290 /* start of struct st_gpio_from_pfce1 */
    291     volatile uint16_t PFCE3;                                  /*  PFCE3           */
    292     volatile uint8_t   dummy408[2];                            /*                  */
    293 /* end of struct st_gpio_from_pfce1 */
    294 /* start of struct st_gpio_from_pfce1 */
    295     volatile uint16_t PFCE4;                                  /*  PFCE4           */
    296     volatile uint8_t   dummy409[2];                            /*                  */
    297 /* end of struct st_gpio_from_pfce1 */
    298 /* start of struct st_gpio_from_pfce1 */
    299     volatile uint16_t PFCE5;                                  /*  PFCE5           */
    300     volatile uint8_t   dummy410[2];                            /*                  */
    301 /* end of struct st_gpio_from_pfce1 */
    302 /* start of struct st_gpio_from_pfce1 */
    303     volatile uint16_t PFCE6;                                  /*  PFCE6           */
    304     volatile uint8_t   dummy411[2];                            /*                  */
    305 /* end of struct st_gpio_from_pfce1 */
    306 /* start of struct st_gpio_from_pfce1 */
    307     volatile uint16_t PFCE7;                                  /*  PFCE7           */
    308     volatile uint8_t   dummy412[2];                            /*                  */
    309 /* end of struct st_gpio_from_pfce1 */
    310 /* start of struct st_gpio_from_pfce1 */
    311     volatile uint16_t PFCE8;                                  /*  PFCE8           */
    312     volatile uint8_t   dummy413[2];                            /*                  */
    313 /* end of struct st_gpio_from_pfce1 */
    314 /* start of struct st_gpio_from_pfce1 */
    315     volatile uint16_t PFCE9;                                  /*  PFCE9           */
    316     volatile uint8_t   dummy414[2];                            /*                  */
    317 /* end of struct st_gpio_from_pfce1 */
    318 /* start of struct st_gpio_from_pfce1 */
    319     volatile uint16_t PFCE10;                                 /*  PFCE10          */
    320     volatile uint8_t   dummy415[2];                            /*                  */
    321 /* end of struct st_gpio_from_pfce1 */
    322 /* start of struct st_gpio_from_pfce1 */
    323     volatile uint16_t PFCE11;                                 /*  PFCE11          */
    324     volatile uint8_t   dummy4160[2];                           /*                  */
    325 /* end of struct st_gpio_from_pfce1 */
    326     volatile uint8_t   dummy4161[212];                         /*                  */
    327 /* start of struct st_gpio_from_pnot1 */
    328     volatile uint16_t PNOT1;                                  /*  PNOT1           */
    329     volatile uint8_t   dummy417[2];                            /*                  */
    330 /* end of struct st_gpio_from_pnot1 */
    331 /* start of struct st_gpio_from_pnot1 */
    332     volatile uint16_t PNOT2;                                  /*  PNOT2           */
    333     volatile uint8_t   dummy418[2];                            /*                  */
    334 /* end of struct st_gpio_from_pnot1 */
    335 /* start of struct st_gpio_from_pnot1 */
    336     volatile uint16_t PNOT3;                                  /*  PNOT3           */
    337     volatile uint8_t   dummy419[2];                            /*                  */
    338 /* end of struct st_gpio_from_pnot1 */
    339 /* start of struct st_gpio_from_pnot1 */
    340     volatile uint16_t PNOT4;                                  /*  PNOT4           */
    341     volatile uint8_t   dummy420[2];                            /*                  */
    342 /* end of struct st_gpio_from_pnot1 */
    343 /* start of struct st_gpio_from_pnot1 */
    344     volatile uint16_t PNOT5;                                  /*  PNOT5           */
    345     volatile uint8_t   dummy421[2];                            /*                  */
    346 /* end of struct st_gpio_from_pnot1 */
    347 /* start of struct st_gpio_from_pnot1 */
    348     volatile uint16_t PNOT6;                                  /*  PNOT6           */
    349     volatile uint8_t   dummy422[2];                            /*                  */
    350 /* end of struct st_gpio_from_pnot1 */
    351 /* start of struct st_gpio_from_pnot1 */
    352     volatile uint16_t PNOT7;                                  /*  PNOT7           */
    353     volatile uint8_t   dummy423[2];                            /*                  */
    354 /* end of struct st_gpio_from_pnot1 */
    355 /* start of struct st_gpio_from_pnot1 */
    356     volatile uint16_t PNOT8;                                  /*  PNOT8           */
    357     volatile uint8_t   dummy424[2];                            /*                  */
    358 /* end of struct st_gpio_from_pnot1 */
    359 /* start of struct st_gpio_from_pnot1 */
    360     volatile uint16_t PNOT9;                                  /*  PNOT9           */
    361     volatile uint8_t   dummy425[2];                            /*                  */
    362 /* end of struct st_gpio_from_pnot1 */
    363 /* start of struct st_gpio_from_pnot1 */
    364     volatile uint16_t PNOT10;                                 /*  PNOT10          */
    365     volatile uint8_t   dummy426[2];                            /*                  */
    366 /* end of struct st_gpio_from_pnot1 */
    367 /* start of struct st_gpio_from_pnot1 */
    368     volatile uint16_t PNOT11;                                 /*  PNOT11          */
    369     volatile uint8_t   dummy4270[2];                           /*                  */
    370 /* end of struct st_gpio_from_pnot1 */
    371     volatile uint8_t   dummy4271[212];                         /*                  */
    372 #define GPIO_PMSRn_COUNT 11
    373     volatile uint32_t  PMSR1;                                  /*  PMSR1           */
    374     volatile uint32_t  PMSR2;                                  /*  PMSR2           */
    375     volatile uint32_t  PMSR3;                                  /*  PMSR3           */
    376     volatile uint32_t  PMSR4;                                  /*  PMSR4           */
    377     volatile uint32_t  PMSR5;                                  /*  PMSR5           */
    378     volatile uint32_t  PMSR6;                                  /*  PMSR6           */
    379     volatile uint32_t  PMSR7;                                  /*  PMSR7           */
    380     volatile uint32_t  PMSR8;                                  /*  PMSR8           */
    381     volatile uint32_t  PMSR9;                                  /*  PMSR9           */
    382     volatile uint32_t  PMSR10;                                 /*  PMSR10          */
    383     volatile uint32_t  PMSR11;                                 /*  PMSR11          */
    384     volatile uint8_t   dummy428[208];                          /*                  */
    385 #define GPIO_PMCSRn_COUNT 12
    386     volatile uint32_t  PMCSR0;                                 /*  PMCSR0          */
    387     volatile uint32_t  PMCSR1;                                 /*  PMCSR1          */
    388     volatile uint32_t  PMCSR2;                                 /*  PMCSR2          */
    389     volatile uint32_t  PMCSR3;                                 /*  PMCSR3          */
    390     volatile uint32_t  PMCSR4;                                 /*  PMCSR4          */
    391     volatile uint32_t  PMCSR5;                                 /*  PMCSR5          */
    392     volatile uint32_t  PMCSR6;                                 /*  PMCSR6          */
    393     volatile uint32_t  PMCSR7;                                 /*  PMCSR7          */
    394     volatile uint32_t  PMCSR8;                                 /*  PMCSR8          */
    395     volatile uint32_t  PMCSR9;                                 /*  PMCSR9          */
    396     volatile uint32_t  PMCSR10;                                /*  PMCSR10         */
    397     volatile uint32_t  PMCSR11;                                /*  PMCSR11         */
    398     volatile uint8_t   dummy429[212];                          /*                  */
    399 /* start of struct st_gpio_from_pfcae1 */
    400     volatile uint16_t PFCAE1;                                 /*  PFCAE1          */
    401     volatile uint8_t   dummy430[2];                            /*                  */
    402 /* end of struct st_gpio_from_pfcae1 */
    403 /* start of struct st_gpio_from_pfcae1 */
    404     volatile uint16_t PFCAE2;                                 /*  PFCAE2          */
    405     volatile uint8_t   dummy431[2];                            /*                  */
    406 /* end of struct st_gpio_from_pfcae1 */
    407 /* start of struct st_gpio_from_pfcae1 */
    408     volatile uint16_t PFCAE3;                                 /*  PFCAE3          */
    409     volatile uint8_t   dummy432[2];                            /*                  */
    410 /* end of struct st_gpio_from_pfcae1 */
    411 /* start of struct st_gpio_from_pfcae1 */
    412     volatile uint16_t PFCAE4;                                 /*  PFCAE4          */
    413     volatile uint8_t   dummy433[2];                            /*                  */
    414 /* end of struct st_gpio_from_pfcae1 */
    415 /* start of struct st_gpio_from_pfcae1 */
    416     volatile uint16_t PFCAE5;                                 /*  PFCAE5          */
    417     volatile uint8_t   dummy434[2];                            /*                  */
    418 /* end of struct st_gpio_from_pfcae1 */
    419 /* start of struct st_gpio_from_pfcae1 */
    420     volatile uint16_t PFCAE6;                                 /*  PFCAE6          */
    421     volatile uint8_t   dummy435[2];                            /*                  */
    422 /* end of struct st_gpio_from_pfcae1 */
    423 /* start of struct st_gpio_from_pfcae1 */
    424     volatile uint16_t PFCAE7;                                 /*  PFCAE7          */
    425     volatile uint8_t   dummy436[2];                            /*                  */
    426 /* end of struct st_gpio_from_pfcae1 */
    427 /* start of struct st_gpio_from_pfcae1 */
    428     volatile uint16_t PFCAE8;                                 /*  PFCAE8          */
    429     volatile uint8_t   dummy437[2];                            /*                  */
    430 /* end of struct st_gpio_from_pfcae1 */
    431 /* start of struct st_gpio_from_pfcae1 */
    432     volatile uint16_t PFCAE9;                                 /*  PFCAE9          */
    433     volatile uint8_t   dummy438[2];                            /*                  */
    434 /* end of struct st_gpio_from_pfcae1 */
    435 /* start of struct st_gpio_from_pfcae1 */
    436     volatile uint16_t PFCAE10;                                /*  PFCAE10         */
    437     volatile uint8_t   dummy439[2];                            /*                  */
    438 /* end of struct st_gpio_from_pfcae1 */
    439 /* start of struct st_gpio_from_pfcae1 */
    440     volatile uint16_t PFCAE11;                                /*  PFCAE11         */
    441     volatile uint8_t   dummy4400[2];                           /*                  */
    442 /* end of struct st_gpio_from_pfcae1 */
    443     volatile uint8_t   dummy4401[464];                         /*                  */
    444     volatile uint32_t  SNCR;                                   /*  SNCR            */
    445     volatile uint8_t   dummy441[13308];                        /*                  */
    446     volatile uint16_t PIBC0;                                  /*  PIBC0           */
    447     volatile uint8_t   dummy442[2];                            /*                  */
    448 /* start of struct st_gpio_from_pibc1 */
    449     volatile uint16_t PIBC1;                                  /*  PIBC1           */
    450     volatile uint8_t   dummy443[2];                            /*                  */
    451 /* end of struct st_gpio_from_pibc1 */
    452 /* start of struct st_gpio_from_pibc1 */
    453     volatile uint16_t PIBC2;                                  /*  PIBC2           */
    454     volatile uint8_t   dummy444[2];                            /*                  */
    455 /* end of struct st_gpio_from_pibc1 */
    456 /* start of struct st_gpio_from_pibc1 */
    457     volatile uint16_t PIBC3;                                  /*  PIBC3           */
    458     volatile uint8_t   dummy445[2];                            /*                  */
    459 /* end of struct st_gpio_from_pibc1 */
    460 /* start of struct st_gpio_from_pibc1 */
    461     volatile uint16_t PIBC4;                                  /*  PIBC4           */
    462     volatile uint8_t   dummy446[2];                            /*                  */
    463 /* end of struct st_gpio_from_pibc1 */
    464 /* start of struct st_gpio_from_pibc1 */
    465     volatile uint16_t PIBC5;                                  /*  PIBC5           */
    466     volatile uint8_t   dummy447[2];                            /*                  */
    467 /* end of struct st_gpio_from_pibc1 */
    468 /* start of struct st_gpio_from_pibc1 */
    469     volatile uint16_t PIBC6;                                  /*  PIBC6           */
    470     volatile uint8_t   dummy448[2];                            /*                  */
    471 /* end of struct st_gpio_from_pibc1 */
    472 /* start of struct st_gpio_from_pibc1 */
    473     volatile uint16_t PIBC7;                                  /*  PIBC7           */
    474     volatile uint8_t   dummy449[2];                            /*                  */
    475 /* end of struct st_gpio_from_pibc1 */
    476 /* start of struct st_gpio_from_pibc1 */
    477     volatile uint16_t PIBC8;                                  /*  PIBC8           */
    478     volatile uint8_t   dummy450[2];                            /*                  */
    479 /* end of struct st_gpio_from_pibc1 */
    480 /* start of struct st_gpio_from_pibc1 */
    481     volatile uint16_t PIBC9;                                  /*  PIBC9           */
    482     volatile uint8_t   dummy451[2];                            /*                  */
    483 /* end of struct st_gpio_from_pibc1 */
    484 /* start of struct st_gpio_from_pibc1 */
    485     volatile uint16_t PIBC10;                                 /*  PIBC10          */
    486     volatile uint8_t   dummy452[2];                            /*                  */
    487 /* end of struct st_gpio_from_pibc1 */
    488 /* start of struct st_gpio_from_pibc1 */
    489     volatile uint16_t PIBC11;                                 /*  PIBC11          */
    490     volatile uint8_t   dummy4530[2];                           /*                  */
    491 /* end of struct st_gpio_from_pibc1 */
    492     volatile uint8_t   dummy4531[212];                         /*                  */
    493 /* start of struct st_gpio_from_pbdc1 */
    494     volatile uint16_t PBDC1;                                  /*  PBDC1           */
    495     volatile uint8_t   dummy454[2];                            /*                  */
    496 /* end of struct st_gpio_from_pbdc1 */
    497 /* start of struct st_gpio_from_pbdc1 */
    498     volatile uint16_t PBDC2;                                  /*  PBDC2           */
    499     volatile uint8_t   dummy455[2];                            /*                  */
    500 /* end of struct st_gpio_from_pbdc1 */
    501 /* start of struct st_gpio_from_pbdc1 */
    502     volatile uint16_t PBDC3;                                  /*  PBDC3           */
    503     volatile uint8_t   dummy456[2];                            /*                  */
    504 /* end of struct st_gpio_from_pbdc1 */
    505 /* start of struct st_gpio_from_pbdc1 */
    506     volatile uint16_t PBDC4;                                  /*  PBDC4           */
    507     volatile uint8_t   dummy457[2];                            /*                  */
    508 /* end of struct st_gpio_from_pbdc1 */
    509 /* start of struct st_gpio_from_pbdc1 */
    510     volatile uint16_t PBDC5;                                  /*  PBDC5           */
    511     volatile uint8_t   dummy458[2];                            /*                  */
    512 /* end of struct st_gpio_from_pbdc1 */
    513 /* start of struct st_gpio_from_pbdc1 */
    514     volatile uint16_t PBDC6;                                  /*  PBDC6           */
    515     volatile uint8_t   dummy459[2];                            /*                  */
    516 /* end of struct st_gpio_from_pbdc1 */
    517 /* start of struct st_gpio_from_pbdc1 */
    518     volatile uint16_t PBDC7;                                  /*  PBDC7           */
    519     volatile uint8_t   dummy460[2];                            /*                  */
    520 /* end of struct st_gpio_from_pbdc1 */
    521 /* start of struct st_gpio_from_pbdc1 */
    522     volatile uint16_t PBDC8;                                  /*  PBDC8           */
    523     volatile uint8_t   dummy461[2];                            /*                  */
    524 /* end of struct st_gpio_from_pbdc1 */
    525 /* start of struct st_gpio_from_pbdc1 */
    526     volatile uint16_t PBDC9;                                  /*  PBDC9           */
    527     volatile uint8_t   dummy462[2];                            /*                  */
    528 /* end of struct st_gpio_from_pbdc1 */
    529 /* start of struct st_gpio_from_pbdc1 */
    530     volatile uint16_t PBDC10;                                 /*  PBDC10          */
    531     volatile uint8_t   dummy463[2];                            /*                  */
    532 /* end of struct st_gpio_from_pbdc1 */
    533 /* start of struct st_gpio_from_pbdc1 */
    534     volatile uint16_t PBDC11;                                 /*  PBDC11          */
    535     volatile uint8_t   dummy4640[2];                           /*                  */
    536 /* end of struct st_gpio_from_pbdc1 */
    537     volatile uint8_t   dummy4641[212];                         /*                  */
    538 /* start of struct st_gpio_from_pipc1 */
    539     volatile uint16_t PIPC1;                                  /*  PIPC1           */
    540     volatile uint8_t   dummy465[2];                            /*                  */
    541 /* end of struct st_gpio_from_pipc1 */
    542 /* start of struct st_gpio_from_pipc1 */
    543     volatile uint16_t PIPC2;                                  /*  PIPC2           */
    544     volatile uint8_t   dummy466[2];                            /*                  */
    545 /* end of struct st_gpio_from_pipc1 */
    546 /* start of struct st_gpio_from_pipc1 */
    547     volatile uint16_t PIPC3;                                  /*  PIPC3           */
    548     volatile uint8_t   dummy467[2];                            /*                  */
    549 /* end of struct st_gpio_from_pipc1 */
    550 /* start of struct st_gpio_from_pipc1 */
    551     volatile uint16_t PIPC4;                                  /*  PIPC4           */
    552     volatile uint8_t   dummy468[2];                            /*                  */
    553 /* end of struct st_gpio_from_pipc1 */
    554 /* start of struct st_gpio_from_pipc1 */
    555     volatile uint16_t PIPC5;                                  /*  PIPC5           */
    556     volatile uint8_t   dummy469[2];                            /*                  */
    557 /* end of struct st_gpio_from_pipc1 */
    558 /* start of struct st_gpio_from_pipc1 */
    559     volatile uint16_t PIPC6;                                  /*  PIPC6           */
    560     volatile uint8_t   dummy470[2];                            /*                  */
    561 /* end of struct st_gpio_from_pipc1 */
    562 /* start of struct st_gpio_from_pipc1 */
    563     volatile uint16_t PIPC7;                                  /*  PIPC7           */
    564     volatile uint8_t   dummy471[2];                            /*                  */
    565 /* end of struct st_gpio_from_pipc1 */
    566 /* start of struct st_gpio_from_pipc1 */
    567     volatile uint16_t PIPC8;                                  /*  PIPC8           */
    568     volatile uint8_t   dummy472[2];                            /*                  */
    569 /* end of struct st_gpio_from_pipc1 */
    570 /* start of struct st_gpio_from_pipc1 */
    571     volatile uint16_t PIPC9;                                  /*  PIPC9           */
    572     volatile uint8_t   dummy473[2];                            /*                  */
    573 /* end of struct st_gpio_from_pipc1 */
    574 /* start of struct st_gpio_from_pipc1 */
    575     volatile uint16_t PIPC10;                                 /*  PIPC10          */
    576     volatile uint8_t   dummy474[2];                            /*                  */
    577 /* end of struct st_gpio_from_pipc1 */
    578 /* start of struct st_gpio_from_pipc1 */
    579     volatile uint16_t PIPC11;                                 /*  PIPC11          */
    580     volatile uint8_t   dummy4750[2];                           /*                  */
    581 /* end of struct st_gpio_from_pipc1 */
    582     volatile uint8_t   dummy4751[2288];                        /*                  */
    583     volatile uint16_t JPPR0;                                  /*  JPPR0           */
    584     volatile uint8_t   dummy476[30];                           /*                  */
    585     volatile uint16_t JPMC0;                                  /*  JPMC0           */
    586     volatile uint8_t   dummy477[78];                           /*                  */
    587     volatile uint32_t  JPMCSR0;                                /*  JPMCSR0         */
    588     volatile uint8_t   dummy478[876];                          /*                  */
    589     volatile uint16_t JPIBC0;                                 /*  JPIBC0          */
    590 };
    591 
    592 
    593 struct st_gpio_from_p1
    594 {
    595     volatile uint16_t P1;                                     /*  P1              */
    596     volatile uint8_t   dummy1[3];                              /*                  */
    597 };
    598 
    599 
    600 struct st_gpio_from_ppr0
    601 {
    602     volatile uint16_t PPR0;                                   /*  PPR0            */
    603     volatile uint8_t   dummy1[2];                              /*                  */
    604 };
    605 
    606 
    607 struct st_gpio_from_pm1
    608 {
    609     volatile uint16_t PM1;                                    /*  PM1             */
    610     volatile uint8_t   dummy1[2];                              /*                  */
    611 };
    612 
    613 
    614 struct st_gpio_from_pmc0
    615 {
    616     volatile uint16_t PMC0;                                   /*  PMC0            */
    617     volatile uint8_t   dummy1[2];                              /*                  */
    618 };
    619 
    620 
    621 struct st_gpio_from_pfc1
    622 {
    623     volatile uint16_t PFC1;                                   /*  PFC1            */
    624     volatile uint8_t   dummy1[2];                              /*                  */
    625 };
    626 
    627 
    628 struct st_gpio_from_pfce1
    629 {
    630     volatile uint16_t PFCE1;                                  /*  PFCE1           */
    631     volatile uint8_t   dummy1[2];                              /*                  */
    632 };
    633 
    634 
    635 struct st_gpio_from_pnot1
    636 {
    637     volatile uint16_t PNOT1;                                  /*  PNOT1           */
    638     volatile uint8_t   dummy1[2];                              /*                  */
    639 };
    640 
    641 
    642 struct st_gpio_from_pfcae1
    643 {
    644     volatile uint16_t PFCAE1;                                 /*  PFCAE1          */
    645     volatile uint8_t   dummy1[2];                              /*                  */
    646 };
    647 
    648 
    649 struct st_gpio_from_pibc1
    650 {
    651     volatile uint16_t PIBC1;                                  /*  PIBC1           */
    652     volatile uint8_t   dummy1[2];                              /*                  */
    653 };
    654 
    655 
    656 struct st_gpio_from_pbdc1
    657 {
    658     volatile uint16_t PBDC1;                                  /*  PBDC1           */
    659     volatile uint8_t   dummy1[2];                              /*                  */
    660 };
    661 
    662 
    663 struct st_gpio_from_pipc1
    664 {
    665     volatile uint16_t PIPC1;                                  /*  PIPC1           */
    666     volatile uint8_t   dummy1[2];                              /*                  */
    667 };
    668 
    669 
    67036#define GPIO    (*(struct st_gpio    *)0xFCFE3004uL) /* GPIO */
    67137
    672 /* Start of channnel array defines of GPIO */
    673 
    674 /* Channnel array defines of GPIO_FROM_PIPC1_ARRAY */
     38
     39/* Start of channel array defines of GPIO */
     40
     41/* Channel array defines of GPIO_FROM_PIPC1_ARRAY */
    67542/*(Sample) value = GPIO_FROM_PIPC1_ARRAY[ channel ]->PIPC1; */
    676 #define GPIO_FROM_PIPC1_ARRAY_COUNT  11
     43#define GPIO_FROM_PIPC1_ARRAY_COUNT  (11)
    67744#define GPIO_FROM_PIPC1_ARRAY_ADDRESS_LIST \
    67845{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    … …  
    69360
    69461
    695 /* Channnel array defines of GPIO_FROM_PBDC1_ARRAY */
     62/* Channel array defines of GPIO_FROM_PBDC1_ARRAY */
    69663/*(Sample) value = GPIO_FROM_PBDC1_ARRAY[ channel ]->PBDC1; */
    697 #define GPIO_FROM_PBDC1_ARRAY_COUNT  11
     64#define GPIO_FROM_PBDC1_ARRAY_COUNT  (11)
    69865#define GPIO_FROM_PBDC1_ARRAY_ADDRESS_LIST \
    69966{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    … …  
    71481
    71582
    716 /* Channnel array defines of GPIO_FROM_PIBC1_ARRAY */
     83/* Channel array defines of GPIO_FROM_PIBC1_ARRAY */
    71784/*(Sample) value = GPIO_FROM_PIBC1_ARRAY[ channel ]->PIBC1; */
    718 #define GPIO_FROM_PIBC1_ARRAY_COUNT  11
     85#define GPIO_FROM_PIBC1_ARRAY_COUNT  (12)
    71986#define GPIO_FROM_PIBC1_ARRAY_ADDRESS_LIST \
    72087{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    721     &GPIO_FROM_PIBC1, &GPIO_FROM_PIBC2, &GPIO_FROM_PIBC3, &GPIO_FROM_PIBC4, &GPIO_FROM_PIBC5, &GPIO_FROM_PIBC6, &GPIO_FROM_PIBC7, &GPIO_FROM_PIBC8, \
    722     &GPIO_FROM_PIBC9, &GPIO_FROM_PIBC10, &GPIO_FROM_PIBC11 \
     88    &GPIO_FROM_PIBC0, &GPIO_FROM_PIBC1, &GPIO_FROM_PIBC2, &GPIO_FROM_PIBC3, &GPIO_FROM_PIBC4, &GPIO_FROM_PIBC5, &GPIO_FROM_PIBC6, &GPIO_FROM_PIBC7, \
     89    &GPIO_FROM_PIBC8, &GPIO_FROM_PIBC9, &GPIO_FROM_PIBC10, &GPIO_FROM_PIBC11 \
    72390}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     91#define GPIO_FROM_PIBC0 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC0) /* GPIO_FROM_PIBC0 */
    72492#define GPIO_FROM_PIBC1 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC1) /* GPIO_FROM_PIBC1 */
    72593#define GPIO_FROM_PIBC2 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC2) /* GPIO_FROM_PIBC2 */
    … …  
    735103
    736104
    737 /* Channnel array defines of GPIO_FROM_PFCAE1_ARRAY */
     105/* Channel array defines of GPIO_FROM_PFCAE1_ARRAY */
    738106/*(Sample) value = GPIO_FROM_PFCAE1_ARRAY[ channel ]->PFCAE1; */
    739 #define GPIO_FROM_PFCAE1_ARRAY_COUNT  11
     107#define GPIO_FROM_PFCAE1_ARRAY_COUNT  (11)
    740108#define GPIO_FROM_PFCAE1_ARRAY_ADDRESS_LIST \
    741109{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    … …  
    756124
    757125
    758 /* Channnel array defines of GPIO_FROM_PNOT1_ARRAY */
     126/* Channel array defines of GPIO_FROM_PNOT1_ARRAY */
    759127/*(Sample) value = GPIO_FROM_PNOT1_ARRAY[ channel ]->PNOT1; */
    760 #define GPIO_FROM_PNOT1_ARRAY_COUNT  11
     128#define GPIO_FROM_PNOT1_ARRAY_COUNT  (11)
    761129#define GPIO_FROM_PNOT1_ARRAY_ADDRESS_LIST \
    762130{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    … …  
    777145
    778146
    779 /* Channnel array defines of GPIO_FROM_PFCE1_ARRAY */
     147/* Channel array defines of GPIO_FROM_PFCE1_ARRAY */
    780148/*(Sample) value = GPIO_FROM_PFCE1_ARRAY[ channel ]->PFCE1; */
    781 #define GPIO_FROM_PFCE1_ARRAY_COUNT  11
     149#define GPIO_FROM_PFCE1_ARRAY_COUNT  (11)
    782150#define GPIO_FROM_PFCE1_ARRAY_ADDRESS_LIST \
    783151{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    … …  
    798166
    799167
    800 /* Channnel array defines of GPIO_FROM_PFC1_ARRAY */
     168/* Channel array defines of GPIO_FROM_PFC1_ARRAY */
    801169/*(Sample) value = GPIO_FROM_PFC1_ARRAY[ channel ]->PFC1; */
    802 #define GPIO_FROM_PFC1_ARRAY_COUNT  11
     170#define GPIO_FROM_PFC1_ARRAY_COUNT  (11)
    803171#define GPIO_FROM_PFC1_ARRAY_ADDRESS_LIST \
    804172{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    … …  
    819187
    820188
    821 /* Channnel array defines of GPIO_FROM_PMC0_ARRAY */
     189/* Channel array defines of GPIO_FROM_PMC0_ARRAY */
    822190/*(Sample) value = GPIO_FROM_PMC0_ARRAY[ channel ]->PMC0; */
    823 #define GPIO_FROM_PMC0_ARRAY_COUNT  12
     191#define GPIO_FROM_PMC0_ARRAY_COUNT  (12)
    824192#define GPIO_FROM_PMC0_ARRAY_ADDRESS_LIST \
    825193{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    … …  
    841209
    842210
    843 /* Channnel array defines of GPIO_FROM_PM1_ARRAY */
     211/* Channel array defines of GPIO_FROM_PM1_ARRAY */
    844212/*(Sample) value = GPIO_FROM_PM1_ARRAY[ channel ]->PM1; */
    845 #define GPIO_FROM_PM1_ARRAY_COUNT  11
     213#define GPIO_FROM_PM1_ARRAY_COUNT  (11)
    846214#define GPIO_FROM_PM1_ARRAY_ADDRESS_LIST \
    847215{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    … …  
    862230
    863231
    864 /* Channnel array defines of GPIO_FROM_PPR0_ARRAY */
     232/* Channel array defines of GPIO_FROM_PPR0_ARRAY */
    865233/*(Sample) value = GPIO_FROM_PPR0_ARRAY[ channel ]->PPR0; */
    866 #define GPIO_FROM_PPR0_ARRAY_COUNT  12
     234#define GPIO_FROM_PPR0_ARRAY_COUNT  (12)
    867235#define GPIO_FROM_PPR0_ARRAY_ADDRESS_LIST \
    868236{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    … …  
    884252
    885253
    886 /* Channnel array defines of GPIO_FROM_P1_ARRAY */
     254/* Channel array defines of GPIO_FROM_P1_ARRAY */
    887255/*(Sample) value = GPIO_FROM_P1_ARRAY[ channel ]->P1; */
    888 #define GPIO_FROM_P1_ARRAY_COUNT  11
     256#define GPIO_FROM_P1_ARRAY_COUNT  (11)
    889257#define GPIO_FROM_P1_ARRAY_ADDRESS_LIST \
    890258{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    … …  
    904272#define GPIO_FROM_P11 (*(struct st_gpio_from_p1 *)&GPIO.P11)     /* GPIO_FROM_P11 */
    905273
    906 /* End of channnel array defines of GPIO */
    907 
    908 
    909 #define GPIOP1 GPIO.P1
    910 #define GPIOP2 GPIO.P2
    911 #define GPIOP3 GPIO.P3
    912 #define GPIOP4 GPIO.P4
    913 #define GPIOP5 GPIO.P5
    914 #define GPIOP6 GPIO.P6
    915 #define GPIOP7 GPIO.P7
    916 #define GPIOP8 GPIO.P8
    917 #define GPIOP9 GPIO.P9
    918 #define GPIOP10 GPIO.P10
    919 #define GPIOP11 GPIO.P11
    920 #define GPIOPSR1 GPIO.PSR1
    921 #define GPIOPSR2 GPIO.PSR2
    922 #define GPIOPSR3 GPIO.PSR3
    923 #define GPIOPSR4 GPIO.PSR4
    924 #define GPIOPSR5 GPIO.PSR5
    925 #define GPIOPSR6 GPIO.PSR6
    926 #define GPIOPSR7 GPIO.PSR7
    927 #define GPIOPSR8 GPIO.PSR8
    928 #define GPIOPSR9 GPIO.PSR9
    929 #define GPIOPSR10 GPIO.PSR10
    930 #define GPIOPSR11 GPIO.PSR11
    931 #define GPIOPPR0 GPIO.PPR0
    932 #define GPIOPPR1 GPIO.PPR1
    933 #define GPIOPPR2 GPIO.PPR2
    934 #define GPIOPPR3 GPIO.PPR3
    935 #define GPIOPPR4 GPIO.PPR4
    936 #define GPIOPPR5 GPIO.PPR5
    937 #define GPIOPPR6 GPIO.PPR6
    938 #define GPIOPPR7 GPIO.PPR7
    939 #define GPIOPPR8 GPIO.PPR8
    940 #define GPIOPPR9 GPIO.PPR9
    941 #define GPIOPPR10 GPIO.PPR10
    942 #define GPIOPPR11 GPIO.PPR11
    943 #define GPIOPM1 GPIO.PM1
    944 #define GPIOPM2 GPIO.PM2
    945 #define GPIOPM3 GPIO.PM3
    946 #define GPIOPM4 GPIO.PM4
    947 #define GPIOPM5 GPIO.PM5
    948 #define GPIOPM6 GPIO.PM6
    949 #define GPIOPM7 GPIO.PM7
    950 #define GPIOPM8 GPIO.PM8
    951 #define GPIOPM9 GPIO.PM9
    952 #define GPIOPM10 GPIO.PM10
    953 #define GPIOPM11 GPIO.PM11
    954 #define GPIOPMC0 GPIO.PMC0
    955 #define GPIOPMC1 GPIO.PMC1
    956 #define GPIOPMC2 GPIO.PMC2
    957 #define GPIOPMC3 GPIO.PMC3
    958 #define GPIOPMC4 GPIO.PMC4
    959 #define GPIOPMC5 GPIO.PMC5
    960 #define GPIOPMC6 GPIO.PMC6
    961 #define GPIOPMC7 GPIO.PMC7
    962 #define GPIOPMC8 GPIO.PMC8
    963 #define GPIOPMC9 GPIO.PMC9
    964 #define GPIOPMC10 GPIO.PMC10
    965 #define GPIOPMC11 GPIO.PMC11
    966 #define GPIOPFC1 GPIO.PFC1
    967 #define GPIOPFC2 GPIO.PFC2
    968 #define GPIOPFC3 GPIO.PFC3
    969 #define GPIOPFC4 GPIO.PFC4
    970 #define GPIOPFC5 GPIO.PFC5
    971 #define GPIOPFC6 GPIO.PFC6
    972 #define GPIOPFC7 GPIO.PFC7
    973 #define GPIOPFC8 GPIO.PFC8
    974 #define GPIOPFC9 GPIO.PFC9
    975 #define GPIOPFC10 GPIO.PFC10
    976 #define GPIOPFC11 GPIO.PFC11
    977 #define GPIOPFCE1 GPIO.PFCE1
    978 #define GPIOPFCE2 GPIO.PFCE2
    979 #define GPIOPFCE3 GPIO.PFCE3
    980 #define GPIOPFCE4 GPIO.PFCE4
    981 #define GPIOPFCE5 GPIO.PFCE5
    982 #define GPIOPFCE6 GPIO.PFCE6
    983 #define GPIOPFCE7 GPIO.PFCE7
    984 #define GPIOPFCE8 GPIO.PFCE8
    985 #define GPIOPFCE9 GPIO.PFCE9
    986 #define GPIOPFCE10 GPIO.PFCE10
    987 #define GPIOPFCE11 GPIO.PFCE11
    988 #define GPIOPNOT1 GPIO.PNOT1
    989 #define GPIOPNOT2 GPIO.PNOT2
    990 #define GPIOPNOT3 GPIO.PNOT3
    991 #define GPIOPNOT4 GPIO.PNOT4
    992 #define GPIOPNOT5 GPIO.PNOT5
    993 #define GPIOPNOT6 GPIO.PNOT6
    994 #define GPIOPNOT7 GPIO.PNOT7
    995 #define GPIOPNOT8 GPIO.PNOT8
    996 #define GPIOPNOT9 GPIO.PNOT9
    997 #define GPIOPNOT10 GPIO.PNOT10
    998 #define GPIOPNOT11 GPIO.PNOT11
    999 #define GPIOPMSR1 GPIO.PMSR1
    1000 #define GPIOPMSR2 GPIO.PMSR2
    1001 #define GPIOPMSR3 GPIO.PMSR3
    1002 #define GPIOPMSR4 GPIO.PMSR4
    1003 #define GPIOPMSR5 GPIO.PMSR5
    1004 #define GPIOPMSR6 GPIO.PMSR6
    1005 #define GPIOPMSR7 GPIO.PMSR7
    1006 #define GPIOPMSR8 GPIO.PMSR8
    1007 #define GPIOPMSR9 GPIO.PMSR9
    1008 #define GPIOPMSR10 GPIO.PMSR10
    1009 #define GPIOPMSR11 GPIO.PMSR11
    1010 #define GPIOPMCSR0 GPIO.PMCSR0
    1011 #define GPIOPMCSR1 GPIO.PMCSR1
    1012 #define GPIOPMCSR2 GPIO.PMCSR2
    1013 #define GPIOPMCSR3 GPIO.PMCSR3
    1014 #define GPIOPMCSR4 GPIO.PMCSR4
    1015 #define GPIOPMCSR5 GPIO.PMCSR5
    1016 #define GPIOPMCSR6 GPIO.PMCSR6
    1017 #define GPIOPMCSR7 GPIO.PMCSR7
    1018 #define GPIOPMCSR8 GPIO.PMCSR8
    1019 #define GPIOPMCSR9 GPIO.PMCSR9
    1020 #define GPIOPMCSR10 GPIO.PMCSR10
    1021 #define GPIOPMCSR11 GPIO.PMCSR11
    1022 #define GPIOPFCAE1 GPIO.PFCAE1
    1023 #define GPIOPFCAE2 GPIO.PFCAE2
    1024 #define GPIOPFCAE3 GPIO.PFCAE3
    1025 #define GPIOPFCAE4 GPIO.PFCAE4
    1026 #define GPIOPFCAE5 GPIO.PFCAE5
    1027 #define GPIOPFCAE6 GPIO.PFCAE6
    1028 #define GPIOPFCAE7 GPIO.PFCAE7
    1029 #define GPIOPFCAE8 GPIO.PFCAE8
    1030 #define GPIOPFCAE9 GPIO.PFCAE9
    1031 #define GPIOPFCAE10 GPIO.PFCAE10
    1032 #define GPIOPFCAE11 GPIO.PFCAE11
    1033 #define GPIOSNCR GPIO.SNCR
    1034 #define GPIOPIBC0 GPIO.PIBC0
    1035 #define GPIOPIBC1 GPIO.PIBC1
    1036 #define GPIOPIBC2 GPIO.PIBC2
    1037 #define GPIOPIBC3 GPIO.PIBC3
    1038 #define GPIOPIBC4 GPIO.PIBC4
    1039 #define GPIOPIBC5 GPIO.PIBC5
    1040 #define GPIOPIBC6 GPIO.PIBC6
    1041 #define GPIOPIBC7 GPIO.PIBC7
    1042 #define GPIOPIBC8 GPIO.PIBC8
    1043 #define GPIOPIBC9 GPIO.PIBC9
    1044 #define GPIOPIBC10 GPIO.PIBC10
    1045 #define GPIOPIBC11 GPIO.PIBC11
    1046 #define GPIOPBDC1 GPIO.PBDC1
    1047 #define GPIOPBDC2 GPIO.PBDC2
    1048 #define GPIOPBDC3 GPIO.PBDC3
    1049 #define GPIOPBDC4 GPIO.PBDC4
    1050 #define GPIOPBDC5 GPIO.PBDC5
    1051 #define GPIOPBDC6 GPIO.PBDC6
    1052 #define GPIOPBDC7 GPIO.PBDC7
    1053 #define GPIOPBDC8 GPIO.PBDC8
    1054 #define GPIOPBDC9 GPIO.PBDC9
    1055 #define GPIOPBDC10 GPIO.PBDC10
    1056 #define GPIOPBDC11 GPIO.PBDC11
    1057 #define GPIOPIPC1 GPIO.PIPC1
    1058 #define GPIOPIPC2 GPIO.PIPC2
    1059 #define GPIOPIPC3 GPIO.PIPC3
    1060 #define GPIOPIPC4 GPIO.PIPC4
    1061 #define GPIOPIPC5 GPIO.PIPC5
    1062 #define GPIOPIPC6 GPIO.PIPC6
    1063 #define GPIOPIPC7 GPIO.PIPC7
    1064 #define GPIOPIPC8 GPIO.PIPC8
    1065 #define GPIOPIPC9 GPIO.PIPC9
    1066 #define GPIOPIPC10 GPIO.PIPC10
    1067 #define GPIOPIPC11 GPIO.PIPC11
    1068 #define GPIOJPPR0 GPIO.JPPR0
    1069 #define GPIOJPMC0 GPIO.JPMC0
    1070 #define GPIOJPMCSR0 GPIO.JPMCSR0
    1071 #define GPIOJPIBC0 GPIO.JPIBC0
     274/* End of channel array defines of GPIO */
     275
     276
     277#define GPIOP1 (GPIO.P1)
     278#define GPIOP2 (GPIO.P2)
     279#define GPIOP3 (GPIO.P3)
     280#define GPIOP4 (GPIO.P4)
     281#define GPIOP5 (GPIO.P5)
     282#define GPIOP6 (GPIO.P6)
     283#define GPIOP7 (GPIO.P7)
     284#define GPIOP8 (GPIO.P8)
     285#define GPIOP9 (GPIO.P9)
     286#define GPIOP10 (GPIO.P10)
     287#define GPIOP11 (GPIO.P11)
     288#define GPIOPSR1 (GPIO.PSR1)
     289#define GPIOPSR2 (GPIO.PSR2)
     290#define GPIOPSR3 (GPIO.PSR3)
     291#define GPIOPSR4 (GPIO.PSR4)
     292#define GPIOPSR5 (GPIO.PSR5)
     293#define GPIOPSR6 (GPIO.PSR6)
     294#define GPIOPSR7 (GPIO.PSR7)
     295#define GPIOPSR8 (GPIO.PSR8)
     296#define GPIOPSR9 (GPIO.PSR9)
     297#define GPIOPSR10 (GPIO.PSR10)
     298#define GPIOPSR11 (GPIO.PSR11)
     299#define GPIOPPR0 (GPIO.PPR0)
     300#define GPIOPPR1 (GPIO.PPR1)
     301#define GPIOPPR2 (GPIO.PPR2)
     302#define GPIOPPR3 (GPIO.PPR3)
     303#define GPIOPPR4 (GPIO.PPR4)
     304#define GPIOPPR5 (GPIO.PPR5)
     305#define GPIOPPR6 (GPIO.PPR6)
     306#define GPIOPPR7 (GPIO.PPR7)
     307#define GPIOPPR8 (GPIO.PPR8)
     308#define GPIOPPR9 (GPIO.PPR9)
     309#define GPIOPPR10 (GPIO.PPR10)
     310#define GPIOPPR11 (GPIO.PPR11)
     311#define GPIOPM1 (GPIO.PM1)
     312#define GPIOPM2 (GPIO.PM2)
     313#define GPIOPM3 (GPIO.PM3)
     314#define GPIOPM4 (GPIO.PM4)
     315#define GPIOPM5 (GPIO.PM5)
     316#define GPIOPM6 (GPIO.PM6)
     317#define GPIOPM7 (GPIO.PM7)
     318#define GPIOPM8 (GPIO.PM8)
     319#define GPIOPM9 (GPIO.PM9)
     320#define GPIOPM10 (GPIO.PM10)
     321#define GPIOPM11 (GPIO.PM11)
     322#define GPIOPMC0 (GPIO.PMC0)
     323#define GPIOPMC1 (GPIO.PMC1)
     324#define GPIOPMC2 (GPIO.PMC2)
     325#define GPIOPMC3 (GPIO.PMC3)
     326#define GPIOPMC4 (GPIO.PMC4)
     327#define GPIOPMC5 (GPIO.PMC5)
     328#define GPIOPMC6 (GPIO.PMC6)
     329#define GPIOPMC7 (GPIO.PMC7)
     330#define GPIOPMC8 (GPIO.PMC8)
     331#define GPIOPMC9 (GPIO.PMC9)
     332#define GPIOPMC10 (GPIO.PMC10)
     333#define GPIOPMC11 (GPIO.PMC11)
     334#define GPIOPFC1 (GPIO.PFC1)
     335#define GPIOPFC2 (GPIO.PFC2)
     336#define GPIOPFC3 (GPIO.PFC3)
     337#define GPIOPFC4 (GPIO.PFC4)
     338#define GPIOPFC5 (GPIO.PFC5)
     339#define GPIOPFC6 (GPIO.PFC6)
     340#define GPIOPFC7 (GPIO.PFC7)
     341#define GPIOPFC8 (GPIO.PFC8)
     342#define GPIOPFC9 (GPIO.PFC9)
     343#define GPIOPFC10 (GPIO.PFC10)
     344#define GPIOPFC11 (GPIO.PFC11)
     345#define GPIOPFCE1 (GPIO.PFCE1)
     346#define GPIOPFCE2 (GPIO.PFCE2)
     347#define GPIOPFCE3 (GPIO.PFCE3)
     348#define GPIOPFCE4 (GPIO.PFCE4)
     349#define GPIOPFCE5 (GPIO.PFCE5)
     350#define GPIOPFCE6 (GPIO.PFCE6)
     351#define GPIOPFCE7 (GPIO.PFCE7)
     352#define GPIOPFCE8 (GPIO.PFCE8)
     353#define GPIOPFCE9 (GPIO.PFCE9)
     354#define GPIOPFCE10 (GPIO.PFCE10)
     355#define GPIOPFCE11 (GPIO.PFCE11)
     356#define GPIOPNOT1 (GPIO.PNOT1)
     357#define GPIOPNOT2 (GPIO.PNOT2)
     358#define GPIOPNOT3 (GPIO.PNOT3)
     359#define GPIOPNOT4 (GPIO.PNOT4)
     360#define GPIOPNOT5 (GPIO.PNOT5)
     361#define GPIOPNOT6 (GPIO.PNOT6)
     362#define GPIOPNOT7 (GPIO.PNOT7)
     363#define GPIOPNOT8 (GPIO.PNOT8)
     364#define GPIOPNOT9 (GPIO.PNOT9)
     365#define GPIOPNOT10 (GPIO.PNOT10)
     366#define GPIOPNOT11 (GPIO.PNOT11)
     367#define GPIOPMSR1 (GPIO.PMSR1)
     368#define GPIOPMSR2 (GPIO.PMSR2)
     369#define GPIOPMSR3 (GPIO.PMSR3)
     370#define GPIOPMSR4 (GPIO.PMSR4)
     371#define GPIOPMSR5 (GPIO.PMSR5)
     372#define GPIOPMSR6 (GPIO.PMSR6)
     373#define GPIOPMSR7 (GPIO.PMSR7)
     374#define GPIOPMSR8 (GPIO.PMSR8)
     375#define GPIOPMSR9 (GPIO.PMSR9)
     376#define GPIOPMSR10 (GPIO.PMSR10)
     377#define GPIOPMSR11 (GPIO.PMSR11)
     378#define GPIOPMCSR0 (GPIO.PMCSR0)
     379#define GPIOPMCSR1 (GPIO.PMCSR1)
     380#define GPIOPMCSR2 (GPIO.PMCSR2)
     381#define GPIOPMCSR3 (GPIO.PMCSR3)
     382#define GPIOPMCSR4 (GPIO.PMCSR4)
     383#define GPIOPMCSR5 (GPIO.PMCSR5)
     384#define GPIOPMCSR6 (GPIO.PMCSR6)
     385#define GPIOPMCSR7 (GPIO.PMCSR7)
     386#define GPIOPMCSR8 (GPIO.PMCSR8)
     387#define GPIOPMCSR9 (GPIO.PMCSR9)
     388#define GPIOPMCSR10 (GPIO.PMCSR10)
     389#define GPIOPMCSR11 (GPIO.PMCSR11)
     390#define GPIOPFCAE1 (GPIO.PFCAE1)
     391#define GPIOPFCAE2 (GPIO.PFCAE2)
     392#define GPIOPFCAE3 (GPIO.PFCAE3)
     393#define GPIOPFCAE4 (GPIO.PFCAE4)
     394#define GPIOPFCAE5 (GPIO.PFCAE5)
     395#define GPIOPFCAE6 (GPIO.PFCAE6)
     396#define GPIOPFCAE7 (GPIO.PFCAE7)
     397#define GPIOPFCAE8 (GPIO.PFCAE8)
     398#define GPIOPFCAE9 (GPIO.PFCAE9)
     399#define GPIOPFCAE10 (GPIO.PFCAE10)
     400#define GPIOPFCAE11 (GPIO.PFCAE11)
     401#define GPIOSNCR (GPIO.SNCR)
     402#define GPIOPIBC0 (GPIO.PIBC0)
     403#define GPIOPIBC1 (GPIO.PIBC1)
     404#define GPIOPIBC2 (GPIO.PIBC2)
     405#define GPIOPIBC3 (GPIO.PIBC3)
     406#define GPIOPIBC4 (GPIO.PIBC4)
     407#define GPIOPIBC5 (GPIO.PIBC5)
     408#define GPIOPIBC6 (GPIO.PIBC6)
     409#define GPIOPIBC7 (GPIO.PIBC7)
     410#define GPIOPIBC8 (GPIO.PIBC8)
     411#define GPIOPIBC9 (GPIO.PIBC9)
     412#define GPIOPIBC10 (GPIO.PIBC10)
     413#define GPIOPIBC11 (GPIO.PIBC11)
     414#define GPIOPBDC1 (GPIO.PBDC1)
     415#define GPIOPBDC2 (GPIO.PBDC2)
     416#define GPIOPBDC3 (GPIO.PBDC3)
     417#define GPIOPBDC4 (GPIO.PBDC4)
     418#define GPIOPBDC5 (GPIO.PBDC5)
     419#define GPIOPBDC6 (GPIO.PBDC6)
     420#define GPIOPBDC7 (GPIO.PBDC7)
     421#define GPIOPBDC8 (GPIO.PBDC8)
     422#define GPIOPBDC9 (GPIO.PBDC9)
     423#define GPIOPBDC10 (GPIO.PBDC10)
     424#define GPIOPBDC11 (GPIO.PBDC11)
     425#define GPIOPIPC1 (GPIO.PIPC1)
     426#define GPIOPIPC2 (GPIO.PIPC2)
     427#define GPIOPIPC3 (GPIO.PIPC3)
     428#define GPIOPIPC4 (GPIO.PIPC4)
     429#define GPIOPIPC5 (GPIO.PIPC5)
     430#define GPIOPIPC6 (GPIO.PIPC6)
     431#define GPIOPIPC7 (GPIO.PIPC7)
     432#define GPIOPIPC8 (GPIO.PIPC8)
     433#define GPIOPIPC9 (GPIO.PIPC9)
     434#define GPIOPIPC10 (GPIO.PIPC10)
     435#define GPIOPIPC11 (GPIO.PIPC11)
     436#define GPIOJPPR0 (GPIO.JPPR0)
     437#define GPIOJPMC0 (GPIO.JPMC0)
     438#define GPIOJPMCSR0 (GPIO.JPMCSR0)
     439#define GPIOJPIBC0 (GPIO.JPIBC0)
     440
     441#define GPIO_PSRn_COUNT (11)
     442#define GPIO_PMSRn_COUNT (11)
     443#define GPIO_PMCSRn_COUNT (12)
     444
     445
     446typedef struct st_gpio
     447{
     448                                                           /* GPIO             */
     449
     450/* start of struct st_gpio_from_p1 */
     451    volatile uint16_t P1;                                     /*  P1              */
     452    volatile uint8_t   dummy348[2];                            /*                  */
     453
     454/* end of struct st_gpio_from_p1 */
     455
     456/* start of struct st_gpio_from_p1 */
     457    volatile uint16_t P2;                                     /*  P2              */
     458    volatile uint8_t   dummy349[2];                            /*                  */
     459
     460/* end of struct st_gpio_from_p1 */
     461
     462/* start of struct st_gpio_from_p1 */
     463    volatile uint16_t P3;                                     /*  P3              */
     464    volatile uint8_t   dummy350[2];                            /*                  */
     465
     466/* end of struct st_gpio_from_p1 */
     467
     468/* start of struct st_gpio_from_p1 */
     469    volatile uint16_t P4;                                     /*  P4              */
     470    volatile uint8_t   dummy351[2];                            /*                  */
     471
     472/* end of struct st_gpio_from_p1 */
     473
     474/* start of struct st_gpio_from_p1 */
     475    volatile uint16_t P5;                                     /*  P5              */
     476    volatile uint8_t   dummy352[2];                            /*                  */
     477
     478/* end of struct st_gpio_from_p1 */
     479
     480/* start of struct st_gpio_from_p1 */
     481    volatile uint16_t P6;                                     /*  P6              */
     482    volatile uint8_t   dummy353[2];                            /*                  */
     483
     484/* end of struct st_gpio_from_p1 */
     485
     486/* start of struct st_gpio_from_p1 */
     487    volatile uint16_t P7;                                     /*  P7              */
     488    volatile uint8_t   dummy354[2];                            /*                  */
     489
     490/* end of struct st_gpio_from_p1 */
     491
     492/* start of struct st_gpio_from_p1 */
     493    volatile uint16_t P8;                                     /*  P8              */
     494    volatile uint8_t   dummy355[2];                            /*                  */
     495
     496/* end of struct st_gpio_from_p1 */
     497
     498/* start of struct st_gpio_from_p1 */
     499    volatile uint16_t P9;                                     /*  P9              */
     500    volatile uint8_t   dummy356[2];                            /*                  */
     501
     502/* end of struct st_gpio_from_p1 */
     503
     504/* start of struct st_gpio_from_p1 */
     505    volatile uint16_t P10;                                    /*  P10             */
     506    volatile uint8_t   dummy357[2];                            /*                  */
     507
     508/* end of struct st_gpio_from_p1 */
     509
     510/* start of struct st_gpio_from_p1 */
     511    volatile uint16_t P11;                                    /*  P11             */
     512    volatile uint8_t   dummy3580[2];                           /*                  */
     513
     514/* end of struct st_gpio_from_p1 */
     515    volatile uint8_t   dummy3581[212];                         /*                  */
     516
     517/* #define GPIO_PSRn_COUNT (11) */
     518    volatile uint32_t  PSR1;                                   /*  PSR1            */
     519    volatile uint32_t  PSR2;                                   /*  PSR2            */
     520    volatile uint32_t  PSR3;                                   /*  PSR3            */
     521    volatile uint32_t  PSR4;                                   /*  PSR4            */
     522    volatile uint32_t  PSR5;                                   /*  PSR5            */
     523    volatile uint32_t  PSR6;                                   /*  PSR6            */
     524    volatile uint32_t  PSR7;                                   /*  PSR7            */
     525    volatile uint32_t  PSR8;                                   /*  PSR8            */
     526    volatile uint32_t  PSR9;                                   /*  PSR9            */
     527    volatile uint32_t  PSR10;                                  /*  PSR10           */
     528    volatile uint32_t  PSR11;                                  /*  PSR11           */
     529    volatile uint8_t   dummy359[208];                          /*                  */
     530
     531/* start of struct st_gpio_from_ppr0 */
     532    volatile uint16_t PPR0;                                   /*  PPR0            */
     533    volatile uint8_t   dummy360[2];                            /*                  */
     534
     535/* end of struct st_gpio_from_ppr0 */
     536
     537/* start of struct st_gpio_from_ppr0 */
     538    volatile uint16_t PPR1;                                   /*  PPR1            */
     539    volatile uint8_t   dummy361[2];                            /*                  */
     540
     541/* end of struct st_gpio_from_ppr0 */
     542
     543/* start of struct st_gpio_from_ppr0 */
     544    volatile uint16_t PPR2;                                   /*  PPR2            */
     545    volatile uint8_t   dummy362[2];                            /*                  */
     546
     547/* end of struct st_gpio_from_ppr0 */
     548
     549/* start of struct st_gpio_from_ppr0 */
     550    volatile uint16_t PPR3;                                   /*  PPR3            */
     551    volatile uint8_t   dummy363[2];                            /*                  */
     552
     553/* end of struct st_gpio_from_ppr0 */
     554
     555/* start of struct st_gpio_from_ppr0 */
     556    volatile uint16_t PPR4;                                   /*  PPR4            */
     557    volatile uint8_t   dummy364[2];                            /*                  */
     558
     559/* end of struct st_gpio_from_ppr0 */
     560
     561/* start of struct st_gpio_from_ppr0 */
     562    volatile uint16_t PPR5;                                   /*  PPR5            */
     563    volatile uint8_t   dummy365[2];                            /*                  */
     564
     565/* end of struct st_gpio_from_ppr0 */
     566
     567/* start of struct st_gpio_from_ppr0 */
     568    volatile uint16_t PPR6;                                   /*  PPR6            */
     569    volatile uint8_t   dummy366[2];                            /*                  */
     570
     571/* end of struct st_gpio_from_ppr0 */
     572
     573/* start of struct st_gpio_from_ppr0 */
     574    volatile uint16_t PPR7;                                   /*  PPR7            */
     575    volatile uint8_t   dummy367[2];                            /*                  */
     576
     577/* end of struct st_gpio_from_ppr0 */
     578
     579/* start of struct st_gpio_from_ppr0 */
     580    volatile uint16_t PPR8;                                   /*  PPR8            */
     581    volatile uint8_t   dummy368[2];                            /*                  */
     582
     583/* end of struct st_gpio_from_ppr0 */
     584
     585/* start of struct st_gpio_from_ppr0 */
     586    volatile uint16_t PPR9;                                   /*  PPR9            */
     587    volatile uint8_t   dummy369[2];                            /*                  */
     588
     589/* end of struct st_gpio_from_ppr0 */
     590
     591/* start of struct st_gpio_from_ppr0 */
     592    volatile uint16_t PPR10;                                  /*  PPR10           */
     593    volatile uint8_t   dummy370[2];                            /*                  */
     594
     595/* end of struct st_gpio_from_ppr0 */
     596
     597/* start of struct st_gpio_from_ppr0 */
     598    volatile uint16_t PPR11;                                  /*  PPR11           */
     599    volatile uint8_t   dummy3710[2];                           /*                  */
     600
     601/* end of struct st_gpio_from_ppr0 */
     602    volatile uint8_t   dummy3711[212];                         /*                  */
     603
     604/* start of struct st_gpio_from_pm1 */
     605    volatile uint16_t PM1;                                    /*  PM1             */
     606    volatile uint8_t   dummy372[2];                            /*                  */
     607
     608/* end of struct st_gpio_from_pm1 */
     609
     610/* start of struct st_gpio_from_pm1 */
     611    volatile uint16_t PM2;                                    /*  PM2             */
     612    volatile uint8_t   dummy373[2];                            /*                  */
     613
     614/* end of struct st_gpio_from_pm1 */
     615
     616/* start of struct st_gpio_from_pm1 */
     617    volatile uint16_t PM3;                                    /*  PM3             */
     618    volatile uint8_t   dummy374[2];                            /*                  */
     619
     620/* end of struct st_gpio_from_pm1 */
     621
     622/* start of struct st_gpio_from_pm1 */
     623    volatile uint16_t PM4;                                    /*  PM4             */
     624    volatile uint8_t   dummy375[2];                            /*                  */
     625
     626/* end of struct st_gpio_from_pm1 */
     627
     628/* start of struct st_gpio_from_pm1 */
     629    volatile uint16_t PM5;                                    /*  PM5             */
     630    volatile uint8_t   dummy376[2];                            /*                  */
     631
     632/* end of struct st_gpio_from_pm1 */
     633
     634/* start of struct st_gpio_from_pm1 */
     635    volatile uint16_t PM6;                                    /*  PM6             */
     636    volatile uint8_t   dummy377[2];                            /*                  */
     637
     638/* end of struct st_gpio_from_pm1 */
     639
     640/* start of struct st_gpio_from_pm1 */
     641    volatile uint16_t PM7;                                    /*  PM7             */
     642    volatile uint8_t   dummy378[2];                            /*                  */
     643
     644/* end of struct st_gpio_from_pm1 */
     645
     646/* start of struct st_gpio_from_pm1 */
     647    volatile uint16_t PM8;                                    /*  PM8             */
     648    volatile uint8_t   dummy379[2];                            /*                  */
     649
     650/* end of struct st_gpio_from_pm1 */
     651
     652/* start of struct st_gpio_from_pm1 */
     653    volatile uint16_t PM9;                                    /*  PM9             */
     654    volatile uint8_t   dummy380[2];                            /*                  */
     655
     656/* end of struct st_gpio_from_pm1 */
     657
     658/* start of struct st_gpio_from_pm1 */
     659    volatile uint16_t PM10;                                   /*  PM10            */
     660    volatile uint8_t   dummy381[2];                            /*                  */
     661
     662/* end of struct st_gpio_from_pm1 */
     663
     664/* start of struct st_gpio_from_pm1 */
     665    volatile uint16_t PM11;                                   /*  PM11            */
     666    volatile uint8_t   dummy3820[2];                           /*                  */
     667
     668/* end of struct st_gpio_from_pm1 */
     669    volatile uint8_t   dummy3821[208];                         /*                  */
     670
     671/* start of struct st_gpio_from_pmc0 */
     672    volatile uint16_t PMC0;                                   /*  PMC0            */
     673    volatile uint8_t   dummy383[2];                            /*                  */
     674
     675/* end of struct st_gpio_from_pmc0 */
     676
     677/* start of struct st_gpio_from_pmc0 */
     678    volatile uint16_t PMC1;                                   /*  PMC1            */
     679    volatile uint8_t   dummy384[2];                            /*                  */
     680
     681/* end of struct st_gpio_from_pmc0 */
     682
     683/* start of struct st_gpio_from_pmc0 */
     684    volatile uint16_t PMC2;                                   /*  PMC2            */
     685    volatile uint8_t   dummy385[2];                            /*                  */
     686
     687/* end of struct st_gpio_from_pmc0 */
     688
     689/* start of struct st_gpio_from_pmc0 */
     690    volatile uint16_t PMC3;                                   /*  PMC3            */
     691    volatile uint8_t   dummy386[2];                            /*                  */
     692
     693/* end of struct st_gpio_from_pmc0 */
     694
     695/* start of struct st_gpio_from_pmc0 */
     696    volatile uint16_t PMC4;                                   /*  PMC4            */
     697    volatile uint8_t   dummy387[2];                            /*                  */
     698
     699/* end of struct st_gpio_from_pmc0 */
     700
     701/* start of struct st_gpio_from_pmc0 */
     702    volatile uint16_t PMC5;                                   /*  PMC5            */
     703    volatile uint8_t   dummy388[2];                            /*                  */
     704
     705/* end of struct st_gpio_from_pmc0 */
     706
     707/* start of struct st_gpio_from_pmc0 */
     708    volatile uint16_t PMC6;                                   /*  PMC6            */
     709    volatile uint8_t   dummy389[2];                            /*                  */
     710
     711/* end of struct st_gpio_from_pmc0 */
     712
     713/* start of struct st_gpio_from_pmc0 */
     714    volatile uint16_t PMC7;                                   /*  PMC7            */
     715    volatile uint8_t   dummy390[2];                            /*                  */
     716
     717/* end of struct st_gpio_from_pmc0 */
     718
     719/* start of struct st_gpio_from_pmc0 */
     720    volatile uint16_t PMC8;                                   /*  PMC8            */
     721    volatile uint8_t   dummy391[2];                            /*                  */
     722
     723/* end of struct st_gpio_from_pmc0 */
     724
     725/* start of struct st_gpio_from_pmc0 */
     726    volatile uint16_t PMC9;                                   /*  PMC9            */
     727    volatile uint8_t   dummy392[2];                            /*                  */
     728
     729/* end of struct st_gpio_from_pmc0 */
     730
     731/* start of struct st_gpio_from_pmc0 */
     732    volatile uint16_t PMC10;                                  /*  PMC10           */
     733    volatile uint8_t   dummy393[2];                            /*                  */
     734
     735/* end of struct st_gpio_from_pmc0 */
     736
     737/* start of struct st_gpio_from_pmc0 */
     738    volatile uint16_t PMC11;                                  /*  PMC11           */
     739    volatile uint8_t   dummy3940[2];                           /*                  */
     740
     741/* end of struct st_gpio_from_pmc0 */
     742    volatile uint8_t   dummy3941[212];                         /*                  */
     743
     744/* start of struct st_gpio_from_pfc1 */
     745    volatile uint16_t PFC1;                                   /*  PFC1            */
     746    volatile uint8_t   dummy395[2];                            /*                  */
     747
     748/* end of struct st_gpio_from_pfc1 */
     749
     750/* start of struct st_gpio_from_pfc1 */
     751    volatile uint16_t PFC2;                                   /*  PFC2            */
     752    volatile uint8_t   dummy396[2];                            /*                  */
     753
     754/* end of struct st_gpio_from_pfc1 */
     755
     756/* start of struct st_gpio_from_pfc1 */
     757    volatile uint16_t PFC3;                                   /*  PFC3            */
     758    volatile uint8_t   dummy397[2];                            /*                  */
     759
     760/* end of struct st_gpio_from_pfc1 */
     761
     762/* start of struct st_gpio_from_pfc1 */
     763    volatile uint16_t PFC4;                                   /*  PFC4            */
     764    volatile uint8_t   dummy398[2];                            /*                  */
     765
     766/* end of struct st_gpio_from_pfc1 */
     767
     768/* start of struct st_gpio_from_pfc1 */
     769    volatile uint16_t PFC5;                                   /*  PFC5            */
     770    volatile uint8_t   dummy399[2];                            /*                  */
     771
     772/* end of struct st_gpio_from_pfc1 */
     773
     774/* start of struct st_gpio_from_pfc1 */
     775    volatile uint16_t PFC6;                                   /*  PFC6            */
     776    volatile uint8_t   dummy400[2];                            /*                  */
     777
     778/* end of struct st_gpio_from_pfc1 */
     779
     780/* start of struct st_gpio_from_pfc1 */
     781    volatile uint16_t PFC7;                                   /*  PFC7            */
     782    volatile uint8_t   dummy401[2];                            /*                  */
     783
     784/* end of struct st_gpio_from_pfc1 */
     785
     786/* start of struct st_gpio_from_pfc1 */
     787    volatile uint16_t PFC8;                                   /*  PFC8            */
     788    volatile uint8_t   dummy402[2];                            /*                  */
     789
     790/* end of struct st_gpio_from_pfc1 */
     791
     792/* start of struct st_gpio_from_pfc1 */
     793    volatile uint16_t PFC9;                                   /*  PFC9            */
     794    volatile uint8_t   dummy403[2];                            /*                  */
     795
     796/* end of struct st_gpio_from_pfc1 */
     797
     798/* start of struct st_gpio_from_pfc1 */
     799    volatile uint16_t PFC10;                                  /*  PFC10           */
     800    volatile uint8_t   dummy404[2];                            /*                  */
     801
     802/* end of struct st_gpio_from_pfc1 */
     803
     804/* start of struct st_gpio_from_pfc1 */
     805    volatile uint16_t PFC11;                                  /*  PFC11           */
     806    volatile uint8_t   dummy4050[2];                           /*                  */
     807
     808/* end of struct st_gpio_from_pfc1 */
     809    volatile uint8_t   dummy4051[212];                         /*                  */
     810
     811/* start of struct st_gpio_from_pfce1 */
     812    volatile uint16_t PFCE1;                                  /*  PFCE1           */
     813    volatile uint8_t   dummy406[2];                            /*                  */
     814
     815/* end of struct st_gpio_from_pfce1 */
     816
     817/* start of struct st_gpio_from_pfce1 */
     818    volatile uint16_t PFCE2;                                  /*  PFCE2           */
     819    volatile uint8_t   dummy407[2];                            /*                  */
     820
     821/* end of struct st_gpio_from_pfce1 */
     822
     823/* start of struct st_gpio_from_pfce1 */
     824    volatile uint16_t PFCE3;                                  /*  PFCE3           */
     825    volatile uint8_t   dummy408[2];                            /*                  */
     826
     827/* end of struct st_gpio_from_pfce1 */
     828
     829/* start of struct st_gpio_from_pfce1 */
     830    volatile uint16_t PFCE4;                                  /*  PFCE4           */
     831    volatile uint8_t   dummy409[2];                            /*                  */
     832
     833/* end of struct st_gpio_from_pfce1 */
     834
     835/* start of struct st_gpio_from_pfce1 */
     836    volatile uint16_t PFCE5;                                  /*  PFCE5           */
     837    volatile uint8_t   dummy410[2];                            /*                  */
     838
     839/* end of struct st_gpio_from_pfce1 */
     840
     841/* start of struct st_gpio_from_pfce1 */
     842    volatile uint16_t PFCE6;                                  /*  PFCE6           */
     843    volatile uint8_t   dummy411[2];                            /*                  */
     844
     845/* end of struct st_gpio_from_pfce1 */
     846
     847/* start of struct st_gpio_from_pfce1 */
     848    volatile uint16_t PFCE7;                                  /*  PFCE7           */
     849    volatile uint8_t   dummy412[2];                            /*                  */
     850
     851/* end of struct st_gpio_from_pfce1 */
     852
     853/* start of struct st_gpio_from_pfce1 */
     854    volatile uint16_t PFCE8;                                  /*  PFCE8           */
     855    volatile uint8_t   dummy413[2];                            /*                  */
     856
     857/* end of struct st_gpio_from_pfce1 */
     858
     859/* start of struct st_gpio_from_pfce1 */
     860    volatile uint16_t PFCE9;                                  /*  PFCE9           */
     861    volatile uint8_t   dummy414[2];                            /*                  */
     862
     863/* end of struct st_gpio_from_pfce1 */
     864
     865/* start of struct st_gpio_from_pfce1 */
     866    volatile uint16_t PFCE10;                                 /*  PFCE10          */
     867    volatile uint8_t   dummy415[2];                            /*                  */
     868
     869/* end of struct st_gpio_from_pfce1 */
     870
     871/* start of struct st_gpio_from_pfce1 */
     872    volatile uint16_t PFCE11;                                 /*  PFCE11          */
     873    volatile uint8_t   dummy4160[2];                           /*                  */
     874
     875/* end of struct st_gpio_from_pfce1 */
     876    volatile uint8_t   dummy4161[212];                         /*                  */
     877
     878/* start of struct st_gpio_from_pnot1 */
     879    volatile uint16_t PNOT1;                                  /*  PNOT1           */
     880    volatile uint8_t   dummy417[2];                            /*                  */
     881
     882/* end of struct st_gpio_from_pnot1 */
     883
     884/* start of struct st_gpio_from_pnot1 */
     885    volatile uint16_t PNOT2;                                  /*  PNOT2           */
     886    volatile uint8_t   dummy418[2];                            /*                  */
     887
     888/* end of struct st_gpio_from_pnot1 */
     889
     890/* start of struct st_gpio_from_pnot1 */
     891    volatile uint16_t PNOT3;                                  /*  PNOT3           */
     892    volatile uint8_t   dummy419[2];                            /*                  */
     893
     894/* end of struct st_gpio_from_pnot1 */
     895
     896/* start of struct st_gpio_from_pnot1 */
     897    volatile uint16_t PNOT4;                                  /*  PNOT4           */
     898    volatile uint8_t   dummy420[2];                            /*                  */
     899
     900/* end of struct st_gpio_from_pnot1 */
     901
     902/* start of struct st_gpio_from_pnot1 */
     903    volatile uint16_t PNOT5;                                  /*  PNOT5           */
     904    volatile uint8_t   dummy421[2];                            /*                  */
     905
     906/* end of struct st_gpio_from_pnot1 */
     907
     908/* start of struct st_gpio_from_pnot1 */
     909    volatile uint16_t PNOT6;                                  /*  PNOT6           */
     910    volatile uint8_t   dummy422[2];                            /*                  */
     911
     912/* end of struct st_gpio_from_pnot1 */
     913
     914/* start of struct st_gpio_from_pnot1 */
     915    volatile uint16_t PNOT7;                                  /*  PNOT7           */
     916    volatile uint8_t   dummy423[2];                            /*                  */
     917
     918/* end of struct st_gpio_from_pnot1 */
     919
     920/* start of struct st_gpio_from_pnot1 */
     921    volatile uint16_t PNOT8;                                  /*  PNOT8           */
     922    volatile uint8_t   dummy424[2];                            /*                  */
     923
     924/* end of struct st_gpio_from_pnot1 */
     925
     926/* start of struct st_gpio_from_pnot1 */
     927    volatile uint16_t PNOT9;                                  /*  PNOT9           */
     928    volatile uint8_t   dummy425[2];                            /*                  */
     929
     930/* end of struct st_gpio_from_pnot1 */
     931
     932/* start of struct st_gpio_from_pnot1 */
     933    volatile uint16_t PNOT10;                                 /*  PNOT10          */
     934    volatile uint8_t   dummy426[2];                            /*                  */
     935
     936/* end of struct st_gpio_from_pnot1 */
     937
     938/* start of struct st_gpio_from_pnot1 */
     939    volatile uint16_t PNOT11;                                 /*  PNOT11          */
     940    volatile uint8_t   dummy4270[2];                           /*                  */
     941
     942/* end of struct st_gpio_from_pnot1 */
     943    volatile uint8_t   dummy4271[212];                         /*                  */
     944
     945/* #define GPIO_PMSRn_COUNT (11) */
     946    volatile uint32_t  PMSR1;                                  /*  PMSR1           */
     947    volatile uint32_t  PMSR2;                                  /*  PMSR2           */
     948    volatile uint32_t  PMSR3;                                  /*  PMSR3           */
     949    volatile uint32_t  PMSR4;                                  /*  PMSR4           */
     950    volatile uint32_t  PMSR5;                                  /*  PMSR5           */
     951    volatile uint32_t  PMSR6;                                  /*  PMSR6           */
     952    volatile uint32_t  PMSR7;                                  /*  PMSR7           */
     953    volatile uint32_t  PMSR8;                                  /*  PMSR8           */
     954    volatile uint32_t  PMSR9;                                  /*  PMSR9           */
     955    volatile uint32_t  PMSR10;                                 /*  PMSR10          */
     956    volatile uint32_t  PMSR11;                                 /*  PMSR11          */
     957    volatile uint8_t   dummy428[208];                          /*                  */
     958
     959/* #define GPIO_PMCSRn_COUNT (12) */
     960    volatile uint32_t  PMCSR0;                                 /*  PMCSR0          */
     961    volatile uint32_t  PMCSR1;                                 /*  PMCSR1          */
     962    volatile uint32_t  PMCSR2;                                 /*  PMCSR2          */
     963    volatile uint32_t  PMCSR3;                                 /*  PMCSR3          */
     964    volatile uint32_t  PMCSR4;                                 /*  PMCSR4          */
     965    volatile uint32_t  PMCSR5;                                 /*  PMCSR5          */
     966    volatile uint32_t  PMCSR6;                                 /*  PMCSR6          */
     967    volatile uint32_t  PMCSR7;                                 /*  PMCSR7          */
     968    volatile uint32_t  PMCSR8;                                 /*  PMCSR8          */
     969    volatile uint32_t  PMCSR9;                                 /*  PMCSR9          */
     970    volatile uint32_t  PMCSR10;                                /*  PMCSR10         */
     971    volatile uint32_t  PMCSR11;                                /*  PMCSR11         */
     972    volatile uint8_t   dummy429[212];                          /*                  */
     973
     974/* start of struct st_gpio_from_pfcae1 */
     975    volatile uint16_t PFCAE1;                                 /*  PFCAE1          */
     976    volatile uint8_t   dummy430[2];                            /*                  */
     977
     978/* end of struct st_gpio_from_pfcae1 */
     979
     980/* start of struct st_gpio_from_pfcae1 */
     981    volatile uint16_t PFCAE2;                                 /*  PFCAE2          */
     982    volatile uint8_t   dummy431[2];                            /*                  */
     983
     984/* end of struct st_gpio_from_pfcae1 */
     985
     986/* start of struct st_gpio_from_pfcae1 */
     987    volatile uint16_t PFCAE3;                                 /*  PFCAE3          */
     988    volatile uint8_t   dummy432[2];                            /*                  */
     989
     990/* end of struct st_gpio_from_pfcae1 */
     991
     992/* start of struct st_gpio_from_pfcae1 */
     993    volatile uint16_t PFCAE4;                                 /*  PFCAE4          */
     994    volatile uint8_t   dummy433[2];                            /*                  */
     995
     996/* end of struct st_gpio_from_pfcae1 */
     997
     998/* start of struct st_gpio_from_pfcae1 */
     999    volatile uint16_t PFCAE5;                                 /*  PFCAE5          */
     1000    volatile uint8_t   dummy434[2];                            /*                  */
     1001
     1002/* end of struct st_gpio_from_pfcae1 */
     1003
     1004/* start of struct st_gpio_from_pfcae1 */
     1005    volatile uint16_t PFCAE6;                                 /*  PFCAE6          */
     1006    volatile uint8_t   dummy435[2];                            /*                  */
     1007
     1008/* end of struct st_gpio_from_pfcae1 */
     1009
     1010/* start of struct st_gpio_from_pfcae1 */
     1011    volatile uint16_t PFCAE7;                                 /*  PFCAE7          */
     1012    volatile uint8_t   dummy436[2];                            /*                  */
     1013
     1014/* end of struct st_gpio_from_pfcae1 */
     1015
     1016/* start of struct st_gpio_from_pfcae1 */
     1017    volatile uint16_t PFCAE8;                                 /*  PFCAE8          */
     1018    volatile uint8_t   dummy437[2];                            /*                  */
     1019
     1020/* end of struct st_gpio_from_pfcae1 */
     1021
     1022/* start of struct st_gpio_from_pfcae1 */
     1023    volatile uint16_t PFCAE9;                                 /*  PFCAE9          */
     1024    volatile uint8_t   dummy438[2];                            /*                  */
     1025
     1026/* end of struct st_gpio_from_pfcae1 */
     1027
     1028/* start of struct st_gpio_from_pfcae1 */
     1029    volatile uint16_t PFCAE10;                                /*  PFCAE10         */
     1030    volatile uint8_t   dummy439[2];                            /*                  */
     1031
     1032/* end of struct st_gpio_from_pfcae1 */
     1033
     1034/* start of struct st_gpio_from_pfcae1 */
     1035    volatile uint16_t PFCAE11;                                /*  PFCAE11         */
     1036    volatile uint8_t   dummy4400[2];                           /*                  */
     1037
     1038/* end of struct st_gpio_from_pfcae1 */
     1039    volatile uint8_t   dummy4401[464];                         /*                  */
     1040    volatile uint32_t  SNCR;                                   /*  SNCR            */
     1041    volatile uint8_t   dummy441[13308];                        /*                  */
     1042
     1043/* start of struct st_gpio_from_pibc1 */
     1044    volatile uint16_t PIBC0;                                  /*  PIBC0           */
     1045    volatile uint8_t   dummy442[2];                            /*                  */
     1046
     1047/* end of struct st_gpio_from_pibc1 */
     1048
     1049/* start of struct st_gpio_from_pibc1 */
     1050    volatile uint16_t PIBC1;                                  /*  PIBC1           */
     1051    volatile uint8_t   dummy443[2];                            /*                  */
     1052
     1053/* end of struct st_gpio_from_pibc1 */
     1054
     1055/* start of struct st_gpio_from_pibc1 */
     1056    volatile uint16_t PIBC2;                                  /*  PIBC2           */
     1057    volatile uint8_t   dummy444[2];                            /*                  */
     1058
     1059/* end of struct st_gpio_from_pibc1 */
     1060
     1061/* start of struct st_gpio_from_pibc1 */
     1062    volatile uint16_t PIBC3;                                  /*  PIBC3           */
     1063    volatile uint8_t   dummy445[2];                            /*                  */
     1064
     1065/* end of struct st_gpio_from_pibc1 */
     1066
     1067/* start of struct st_gpio_from_pibc1 */
     1068    volatile uint16_t PIBC4;                                  /*  PIBC4           */
     1069    volatile uint8_t   dummy446[2];                            /*                  */
     1070
     1071/* end of struct st_gpio_from_pibc1 */
     1072
     1073/* start of struct st_gpio_from_pibc1 */
     1074    volatile uint16_t PIBC5;                                  /*  PIBC5           */
     1075    volatile uint8_t   dummy447[2];                            /*                  */
     1076
     1077/* end of struct st_gpio_from_pibc1 */
     1078
     1079/* start of struct st_gpio_from_pibc1 */
     1080    volatile uint16_t PIBC6;                                  /*  PIBC6           */
     1081    volatile uint8_t   dummy448[2];                            /*                  */
     1082
     1083/* end of struct st_gpio_from_pibc1 */
     1084
     1085/* start of struct st_gpio_from_pibc1 */
     1086    volatile uint16_t PIBC7;                                  /*  PIBC7           */
     1087    volatile uint8_t   dummy449[2];                            /*                  */
     1088
     1089/* end of struct st_gpio_from_pibc1 */
     1090
     1091/* start of struct st_gpio_from_pibc1 */
     1092    volatile uint16_t PIBC8;                                  /*  PIBC8           */
     1093    volatile uint8_t   dummy450[2];                            /*                  */
     1094
     1095/* end of struct st_gpio_from_pibc1 */
     1096
     1097/* start of struct st_gpio_from_pibc1 */
     1098    volatile uint16_t PIBC9;                                  /*  PIBC9           */
     1099    volatile uint8_t   dummy451[2];                            /*                  */
     1100
     1101/* end of struct st_gpio_from_pibc1 */
     1102
     1103/* start of struct st_gpio_from_pibc1 */
     1104    volatile uint16_t PIBC10;                                 /*  PIBC10          */
     1105    volatile uint8_t   dummy452[2];                            /*                  */
     1106
     1107/* end of struct st_gpio_from_pibc1 */
     1108
     1109/* start of struct st_gpio_from_pibc1 */
     1110    volatile uint16_t PIBC11;                                 /*  PIBC11          */
     1111    volatile uint8_t   dummy4530[2];                           /*                  */
     1112
     1113/* end of struct st_gpio_from_pibc1 */
     1114    volatile uint8_t   dummy4531[212];                         /*                  */
     1115
     1116/* start of struct st_gpio_from_pbdc1 */
     1117    volatile uint16_t PBDC1;                                  /*  PBDC1           */
     1118    volatile uint8_t   dummy454[2];                            /*                  */
     1119
     1120/* end of struct st_gpio_from_pbdc1 */
     1121
     1122/* start of struct st_gpio_from_pbdc1 */
     1123    volatile uint16_t PBDC2;                                  /*  PBDC2           */
     1124    volatile uint8_t   dummy455[2];                            /*                  */
     1125
     1126/* end of struct st_gpio_from_pbdc1 */
     1127
     1128/* start of struct st_gpio_from_pbdc1 */
     1129    volatile uint16_t PBDC3;                                  /*  PBDC3           */
     1130    volatile uint8_t   dummy456[2];                            /*                  */
     1131
     1132/* end of struct st_gpio_from_pbdc1 */
     1133
     1134/* start of struct st_gpio_from_pbdc1 */
     1135    volatile uint16_t PBDC4;                                  /*  PBDC4           */
     1136    volatile uint8_t   dummy457[2];                            /*                  */
     1137
     1138/* end of struct st_gpio_from_pbdc1 */
     1139
     1140/* start of struct st_gpio_from_pbdc1 */
     1141    volatile uint16_t PBDC5;                                  /*  PBDC5           */
     1142    volatile uint8_t   dummy458[2];                            /*                  */
     1143
     1144/* end of struct st_gpio_from_pbdc1 */
     1145
     1146/* start of struct st_gpio_from_pbdc1 */
     1147    volatile uint16_t PBDC6;                                  /*  PBDC6           */
     1148    volatile uint8_t   dummy459[2];                            /*                  */
     1149
     1150/* end of struct st_gpio_from_pbdc1 */
     1151
     1152/* start of struct st_gpio_from_pbdc1 */
     1153    volatile uint16_t PBDC7;                                  /*  PBDC7           */
     1154    volatile uint8_t   dummy460[2];                            /*                  */
     1155
     1156/* end of struct st_gpio_from_pbdc1 */
     1157
     1158/* start of struct st_gpio_from_pbdc1 */
     1159    volatile uint16_t PBDC8;                                  /*  PBDC8           */
     1160    volatile uint8_t   dummy461[2];                            /*                  */
     1161
     1162/* end of struct st_gpio_from_pbdc1 */
     1163
     1164/* start of struct st_gpio_from_pbdc1 */
     1165    volatile uint16_t PBDC9;                                  /*  PBDC9           */
     1166    volatile uint8_t   dummy462[2];                            /*                  */
     1167
     1168/* end of struct st_gpio_from_pbdc1 */
     1169
     1170/* start of struct st_gpio_from_pbdc1 */
     1171    volatile uint16_t PBDC10;                                 /*  PBDC10          */
     1172    volatile uint8_t   dummy463[2];                            /*                  */
     1173
     1174/* end of struct st_gpio_from_pbdc1 */
     1175
     1176/* start of struct st_gpio_from_pbdc1 */
     1177    volatile uint16_t PBDC11;                                 /*  PBDC11          */
     1178    volatile uint8_t   dummy4640[2];                           /*                  */
     1179
     1180/* end of struct st_gpio_from_pbdc1 */
     1181    volatile uint8_t   dummy4641[212];                         /*                  */
     1182
     1183/* start of struct st_gpio_from_pipc1 */
     1184    volatile uint16_t PIPC1;                                  /*  PIPC1           */
     1185    volatile uint8_t   dummy465[2];                            /*                  */
     1186
     1187/* end of struct st_gpio_from_pipc1 */
     1188
     1189/* start of struct st_gpio_from_pipc1 */
     1190    volatile uint16_t PIPC2;                                  /*  PIPC2           */
     1191    volatile uint8_t   dummy466[2];                            /*                  */
     1192
     1193/* end of struct st_gpio_from_pipc1 */
     1194
     1195/* start of struct st_gpio_from_pipc1 */
     1196    volatile uint16_t PIPC3;                                  /*  PIPC3           */
     1197    volatile uint8_t   dummy467[2];                            /*                  */
     1198
     1199/* end of struct st_gpio_from_pipc1 */
     1200
     1201/* start of struct st_gpio_from_pipc1 */
     1202    volatile uint16_t PIPC4;                                  /*  PIPC4           */
     1203    volatile uint8_t   dummy468[2];                            /*                  */
     1204
     1205/* end of struct st_gpio_from_pipc1 */
     1206
     1207/* start of struct st_gpio_from_pipc1 */
     1208    volatile uint16_t PIPC5;                                  /*  PIPC5           */
     1209    volatile uint8_t   dummy469[2];                            /*                  */
     1210
     1211/* end of struct st_gpio_from_pipc1 */
     1212
     1213/* start of struct st_gpio_from_pipc1 */
     1214    volatile uint16_t PIPC6;                                  /*  PIPC6           */
     1215    volatile uint8_t   dummy470[2];                            /*                  */
     1216
     1217/* end of struct st_gpio_from_pipc1 */
     1218
     1219/* start of struct st_gpio_from_pipc1 */
     1220    volatile uint16_t PIPC7;                                  /*  PIPC7           */
     1221    volatile uint8_t   dummy471[2];                            /*                  */
     1222
     1223/* end of struct st_gpio_from_pipc1 */
     1224
     1225/* start of struct st_gpio_from_pipc1 */
     1226    volatile uint16_t PIPC8;                                  /*  PIPC8           */
     1227    volatile uint8_t   dummy472[2];                            /*                  */
     1228
     1229/* end of struct st_gpio_from_pipc1 */
     1230
     1231/* start of struct st_gpio_from_pipc1 */
     1232    volatile uint16_t PIPC9;                                  /*  PIPC9           */
     1233    volatile uint8_t   dummy473[2];                            /*                  */
     1234
     1235/* end of struct st_gpio_from_pipc1 */
     1236
     1237/* start of struct st_gpio_from_pipc1 */
     1238    volatile uint16_t PIPC10;                                 /*  PIPC10          */
     1239    volatile uint8_t   dummy474[2];                            /*                  */
     1240
     1241/* end of struct st_gpio_from_pipc1 */
     1242
     1243/* start of struct st_gpio_from_pipc1 */
     1244    volatile uint16_t PIPC11;                                 /*  PIPC11          */
     1245    volatile uint8_t   dummy4750[2];                           /*                  */
     1246
     1247/* end of struct st_gpio_from_pipc1 */
     1248    volatile uint8_t   dummy4751[2288];                        /*                  */
     1249    volatile uint16_t JPPR0;                                  /*  JPPR0           */
     1250    volatile uint8_t   dummy476[30];                           /*                  */
     1251    volatile uint16_t JPMC0;                                  /*  JPMC0           */
     1252    volatile uint8_t   dummy477[78];                           /*                  */
     1253    volatile uint32_t  JPMCSR0;                                /*  JPMCSR0         */
     1254    volatile uint8_t   dummy478[876];                          /*                  */
     1255    volatile uint16_t JPIBC0;                                 /*  JPIBC0          */
     1256} r_io_gpio_t;
     1257
     1258
     1259typedef struct st_gpio_from_p1
     1260{
     1261 
     1262    volatile uint16_t P1;                                     /*  P1              */
     1263    volatile uint8_t   dummy1[3];                              /*                  */
     1264} r_io_gpio_from_p1_t;
     1265
     1266
     1267typedef struct st_gpio_from_ppr0
     1268{
     1269 
     1270    volatile uint16_t PPR0;                                   /*  PPR0            */
     1271    volatile uint8_t   dummy1[2];                              /*                  */
     1272} r_io_gpio_from_ppr0_t;
     1273
     1274
     1275typedef struct st_gpio_from_pm1
     1276{
     1277 
     1278    volatile uint16_t PM1;                                    /*  PM1             */
     1279    volatile uint8_t   dummy1[2];                              /*                  */
     1280} r_io_gpio_from_pm1_t;
     1281
     1282
     1283typedef struct st_gpio_from_pmc0
     1284{
     1285 
     1286    volatile uint16_t PMC0;                                   /*  PMC0            */
     1287    volatile uint8_t   dummy1[2];                              /*                  */
     1288} r_io_gpio_from_pmc0_t;
     1289
     1290
     1291typedef struct st_gpio_from_pfc1
     1292{
     1293 
     1294    volatile uint16_t PFC1;                                   /*  PFC1            */
     1295    volatile uint8_t   dummy1[2];                              /*                  */
     1296} r_io_gpio_from_pfc1_t;
     1297
     1298
     1299typedef struct st_gpio_from_pfce1
     1300{
     1301 
     1302    volatile uint16_t PFCE1;                                  /*  PFCE1           */
     1303    volatile uint8_t   dummy1[2];                              /*                  */
     1304} r_io_gpio_from_pfce1_t;
     1305
     1306
     1307typedef struct st_gpio_from_pnot1
     1308{
     1309 
     1310    volatile uint16_t PNOT1;                                  /*  PNOT1           */
     1311    volatile uint8_t   dummy1[2];                              /*                  */
     1312} r_io_gpio_from_pnot1_t;
     1313
     1314
     1315typedef struct st_gpio_from_pfcae1
     1316{
     1317 
     1318    volatile uint16_t PFCAE1;                                 /*  PFCAE1          */
     1319    volatile uint8_t   dummy1[2];                              /*                  */
     1320} r_io_gpio_from_pfcae1_t;
     1321
     1322
     1323typedef struct st_gpio_from_pibc1
     1324{
     1325 
     1326    volatile uint16_t PIBC1;                                  /*  PIBC1           */
     1327    volatile uint8_t   dummy1[2];                              /*                  */
     1328} r_io_gpio_from_pibc1_t;
     1329
     1330
     1331typedef struct st_gpio_from_pbdc1
     1332{
     1333 
     1334    volatile uint16_t PBDC1;                                  /*  PBDC1           */
     1335    volatile uint8_t   dummy1[2];                              /*                  */
     1336} r_io_gpio_from_pbdc1_t;
     1337
     1338
     1339typedef struct st_gpio_from_pipc1
     1340{
     1341 
     1342    volatile uint16_t PIPC1;                                  /*  PIPC1           */
     1343    volatile uint8_t   dummy1[2];                              /*                  */
     1344} r_io_gpio_from_pipc1_t;
     1345
     1346
     1347/* Channel array defines of GPIO (2)*/
     1348#ifdef  DECLARE_GPIO_FROM_PIPC1_ARRAY_CHANNELS
     1349volatile struct st_gpio_from_pipc1*  GPIO_FROM_PIPC1_ARRAY[ GPIO_FROM_PIPC1_ARRAY_COUNT ] =
     1350    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     1351    GPIO_FROM_PIPC1_ARRAY_ADDRESS_LIST;
     1352    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     1353#endif  /* DECLARE_GPIO_FROM_PIPC1_ARRAY_CHANNELS */
     1354
     1355#ifdef  DECLARE_GPIO_FROM_PBDC1_ARRAY_CHANNELS
     1356volatile struct st_gpio_from_pbdc1*  GPIO_FROM_PBDC1_ARRAY[ GPIO_FROM_PBDC1_ARRAY_COUNT ] =
     1357    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     1358    GPIO_FROM_PBDC1_ARRAY_ADDRESS_LIST;
     1359    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     1360#endif  /* DECLARE_GPIO_FROM_PBDC1_ARRAY_CHANNELS */
     1361
     1362#ifdef  DECLARE_GPIO_FROM_PIBC1_ARRAY_CHANNELS
     1363volatile struct st_gpio_from_pibc1*  GPIO_FROM_PIBC1_ARRAY[ GPIO_FROM_PIBC1_ARRAY_COUNT ] =
     1364    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     1365    GPIO_FROM_PIBC1_ARRAY_ADDRESS_LIST;
     1366    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     1367#endif  /* DECLARE_GPIO_FROM_PIBC1_ARRAY_CHANNELS */
     1368
     1369#ifdef  DECLARE_GPIO_FROM_PFCAE1_ARRAY_CHANNELS
     1370volatile struct st_gpio_from_pfcae1*  GPIO_FROM_PFCAE1_ARRAY[ GPIO_FROM_PFCAE1_ARRAY_COUNT ] =
     1371    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     1372    GPIO_FROM_PFCAE1_ARRAY_ADDRESS_LIST;
     1373    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     1374#endif  /* DECLARE_GPIO_FROM_PFCAE1_ARRAY_CHANNELS */
     1375
     1376#ifdef  DECLARE_GPIO_FROM_PNOT1_ARRAY_CHANNELS
     1377volatile struct st_gpio_from_pnot1*  GPIO_FROM_PNOT1_ARRAY[ GPIO_FROM_PNOT1_ARRAY_COUNT ] =
     1378    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     1379    GPIO_FROM_PNOT1_ARRAY_ADDRESS_LIST;
     1380    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     1381#endif  /* DECLARE_GPIO_FROM_PNOT1_ARRAY_CHANNELS */
     1382
     1383#ifdef  DECLARE_GPIO_FROM_PFCE1_ARRAY_CHANNELS
     1384volatile struct st_gpio_from_pfce1*  GPIO_FROM_PFCE1_ARRAY[ GPIO_FROM_PFCE1_ARRAY_COUNT ] =
     1385    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     1386    GPIO_FROM_PFCE1_ARRAY_ADDRESS_LIST;
     1387    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     1388#endif  /* DECLARE_GPIO_FROM_PFCE1_ARRAY_CHANNELS */
     1389
     1390#ifdef  DECLARE_GPIO_FROM_PFC1_ARRAY_CHANNELS
     1391volatile struct st_gpio_from_pfc1*  GPIO_FROM_PFC1_ARRAY[ GPIO_FROM_PFC1_ARRAY_COUNT ] =
     1392    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     1393    GPIO_FROM_PFC1_ARRAY_ADDRESS_LIST;
     1394    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     1395#endif  /* DECLARE_GPIO_FROM_PFC1_ARRAY_CHANNELS */
     1396
     1397#ifdef  DECLARE_GPIO_FROM_PMC0_ARRAY_CHANNELS
     1398volatile struct st_gpio_from_pmc0*  GPIO_FROM_PMC0_ARRAY[ GPIO_FROM_PMC0_ARRAY_COUNT ] =
     1399    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     1400    GPIO_FROM_PMC0_ARRAY_ADDRESS_LIST;
     1401    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     1402#endif  /* DECLARE_GPIO_FROM_PMC0_ARRAY_CHANNELS */
     1403
     1404#ifdef  DECLARE_GPIO_FROM_PM1_ARRAY_CHANNELS
     1405volatile struct st_gpio_from_pm1*  GPIO_FROM_PM1_ARRAY[ GPIO_FROM_PM1_ARRAY_COUNT ] =
     1406    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     1407    GPIO_FROM_PM1_ARRAY_ADDRESS_LIST;
     1408    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     1409#endif  /* DECLARE_GPIO_FROM_PM1_ARRAY_CHANNELS */
     1410
     1411#ifdef  DECLARE_GPIO_FROM_PPR0_ARRAY_CHANNELS
     1412volatile struct st_gpio_from_ppr0*  GPIO_FROM_PPR0_ARRAY[ GPIO_FROM_PPR0_ARRAY_COUNT ] =
     1413    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     1414    GPIO_FROM_PPR0_ARRAY_ADDRESS_LIST;
     1415    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     1416#endif  /* DECLARE_GPIO_FROM_PPR0_ARRAY_CHANNELS */
     1417
     1418#ifdef  DECLARE_GPIO_FROM_P1_ARRAY_CHANNELS
     1419volatile struct st_gpio_from_p1*  GPIO_FROM_P1_ARRAY[ GPIO_FROM_P1_ARRAY_COUNT ] =
     1420    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     1421    GPIO_FROM_P1_ARRAY_ADDRESS_LIST;
     1422    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     1423#endif  /* DECLARE_GPIO_FROM_P1_ARRAY_CHANNELS */
     1424/* End of channel array defines of GPIO (2)*/
     1425
     1426
    10721427/* <-SEC M1.10.1 */
     1428/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     1429/* <-QAC 0857 */
    10731430/* <-QAC 0639 */
    10741431#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/ieb_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef IEB_IODEFINE_H
    3030#define IEB_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3134/* ->SEC M1.10.1 : Not magic number */
    3235
    33 struct st_ieb
    34 {                                                          /* IEB              */
     36#define IEB     (*(struct st_ieb     *)0xFCFEF000uL) /* IEB */
     37
     38
     39#define IEBB0BCR (IEB.B0BCR)
     40#define IEBB0PSR (IEB.B0PSR)
     41#define IEBB0UAR (IEB.B0UAR)
     42#define IEBB0SAR (IEB.B0SAR)
     43#define IEBB0PAR (IEB.B0PAR)
     44#define IEBB0RSA (IEB.B0RSA)
     45#define IEBB0CDR (IEB.B0CDR)
     46#define IEBB0TCD (IEB.B0TCD)
     47#define IEBB0RCD (IEB.B0RCD)
     48#define IEBB0DLR (IEB.B0DLR)
     49#define IEBB0TDL (IEB.B0TDL)
     50#define IEBB0RDL (IEB.B0RDL)
     51#define IEBB0CKS (IEB.B0CKS)
     52#define IEBB0TMS (IEB.B0TMS)
     53#define IEBB0PCR (IEB.B0PCR)
     54#define IEBB0BSR (IEB.B0BSR)
     55#define IEBB0SSR (IEB.B0SSR)
     56#define IEBB0USR (IEB.B0USR)
     57#define IEBB0ISR (IEB.B0ISR)
     58#define IEBB0ESR (IEB.B0ESR)
     59#define IEBB0FSR (IEB.B0FSR)
     60#define IEBB0SCR (IEB.B0SCR)
     61#define IEBB0CCR (IEB.B0CCR)
     62#define IEBB0STC0 (IEB.B0STC0)
     63#define IEBB0STC1 (IEB.B0STC1)
     64#define IEBB0DR (IEB.B0DR)
     65
     66
     67typedef struct st_ieb
     68{
     69                                                           /* IEB              */
    3570    volatile uint8_t   B0BCR;                                  /*  B0BCR           */
    3671    volatile uint8_t   dummy495[3];                            /*                  */
    … …  
    84119    volatile uint8_t   dummy519[3];                            /*                  */
    85120    volatile uint8_t   B0DR;                                   /*  B0DR            */
    86 };
     121} r_io_ieb_t;
    87122
    88123
    89 #define IEB     (*(struct st_ieb     *)0xFCFEF000uL) /* IEB */
    90 
    91 
    92 #define IEBB0BCR IEB.B0BCR
    93 #define IEBB0PSR IEB.B0PSR
    94 #define IEBB0UAR IEB.B0UAR
    95 #define IEBB0SAR IEB.B0SAR
    96 #define IEBB0PAR IEB.B0PAR
    97 #define IEBB0RSA IEB.B0RSA
    98 #define IEBB0CDR IEB.B0CDR
    99 #define IEBB0TCD IEB.B0TCD
    100 #define IEBB0RCD IEB.B0RCD
    101 #define IEBB0DLR IEB.B0DLR
    102 #define IEBB0TDL IEB.B0TDL
    103 #define IEBB0RDL IEB.B0RDL
    104 #define IEBB0CKS IEB.B0CKS
    105 #define IEBB0TMS IEB.B0TMS
    106 #define IEBB0PCR IEB.B0PCR
    107 #define IEBB0BSR IEB.B0BSR
    108 #define IEBB0SSR IEB.B0SSR
    109 #define IEBB0USR IEB.B0USR
    110 #define IEBB0ISR IEB.B0ISR
    111 #define IEBB0ESR IEB.B0ESR
    112 #define IEBB0FSR IEB.B0FSR
    113 #define IEBB0SCR IEB.B0SCR
    114 #define IEBB0CCR IEB.B0CCR
    115 #define IEBB0STC0 IEB.B0STC0
    116 #define IEBB0STC1 IEB.B0STC1
    117 #define IEBB0DR IEB.B0DR
    118124/* <-SEC M1.10.1 */
     125/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     126/* <-QAC 0857 */
     127/* <-QAC 0639 */
    119128#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/inb_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef INB_IODEFINE_H
    3030#define INB_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
     34/* ->SEC M1.10.1 : Not magic number */
    3135
    32 struct st_inb
    33 {                                                          /* INB              */
     36#define INB     (*(struct st_inb     *)0xFCFE1A00uL) /* INB */
     37
     38
     39#define INBRMPR (INB.RMPR)
     40#define INBAXIBUSCTL0 (INB.AXIBUSCTL0)
     41#define INBAXIBUSCTL1 (INB.AXIBUSCTL1)
     42#define INBAXIBUSCTL2 (INB.AXIBUSCTL2)
     43#define INBAXIBUSCTL3 (INB.AXIBUSCTL3)
     44#define INBAXIBUSCTL4 (INB.AXIBUSCTL4)
     45#define INBAXIBUSCTL5 (INB.AXIBUSCTL5)
     46#define INBAXIBUSCTL6 (INB.AXIBUSCTL6)
     47#define INBAXIBUSCTL7 (INB.AXIBUSCTL7)
     48#define INBAXIBUSCTL8 (INB.AXIBUSCTL8)
     49#define INBAXIBUSCTL9 (INB.AXIBUSCTL9)
     50#define INBAXIBUSCTL10 (INB.AXIBUSCTL10)
     51#define INBAXIRERRCTL0 (INB.AXIRERRCTL0)
     52#define INBAXIRERRCTL1 (INB.AXIRERRCTL1)
     53#define INBAXIRERRCTL2 (INB.AXIRERRCTL2)
     54#define INBAXIRERRCTL3 (INB.AXIRERRCTL3)
     55#define INBAXIRERRST0 (INB.AXIRERRST0)
     56#define INBAXIRERRST1 (INB.AXIRERRST1)
     57#define INBAXIRERRST2 (INB.AXIRERRST2)
     58#define INBAXIRERRST3 (INB.AXIRERRST3)
     59#define INBAXIRERRCLR0 (INB.AXIRERRCLR0)
     60#define INBAXIRERRCLR1 (INB.AXIRERRCLR1)
     61#define INBAXIRERRCLR2 (INB.AXIRERRCLR2)
     62#define INBAXIRERRCLR3 (INB.AXIRERRCLR3)
     63
     64#define INB_AXIBUSCTLn_COUNT (11)
     65#define INB_AXIRERRCTLn_COUNT (4)
     66#define INB_AXIRERRSTn_COUNT (4)
     67#define INB_AXIRERRCLRn_COUNT (4)
     68
     69
     70typedef struct st_inb
     71{
     72                                                           /* INB              */
    3473    volatile uint32_t  RMPR;                                   /*  RMPR            */
    35 #define INB_AXIBUSCTLn_COUNT 11
     74
     75/* #define INB_AXIBUSCTLn_COUNT (11) */
    3676    volatile uint32_t  AXIBUSCTL0;                             /*  AXIBUSCTL0      */
    3777    volatile uint32_t  AXIBUSCTL1;                             /*  AXIBUSCTL1      */
    … …  
    4585    volatile uint32_t  AXIBUSCTL9;                             /*  AXIBUSCTL9      */
    4686    volatile uint32_t  AXIBUSCTL10;                            /*  AXIBUSCTL10     */
    47 #define INB_AXIRERRCTLn_COUNT 4
     87
     88/* #define INB_AXIRERRCTLn_COUNT (4) */
    4889    volatile uint32_t  AXIRERRCTL0;                            /*  AXIRERRCTL0     */
    4990    volatile uint32_t  AXIRERRCTL1;                            /*  AXIRERRCTL1     */
    5091    volatile uint32_t  AXIRERRCTL2;                            /*  AXIRERRCTL2     */
    5192    volatile uint32_t  AXIRERRCTL3;                            /*  AXIRERRCTL3     */
    52 #define INB_AXIRERRSTn_COUNT 4
     93
     94/* #define INB_AXIRERRSTn_COUNT (4) */
    5395    volatile uint32_t  AXIRERRST0;                             /*  AXIRERRST0      */
    5496    volatile uint32_t  AXIRERRST1;                             /*  AXIRERRST1      */
    5597    volatile uint32_t  AXIRERRST2;                             /*  AXIRERRST2      */
    5698    volatile uint32_t  AXIRERRST3;                             /*  AXIRERRST3      */
    57 #define INB_AXIRERRCLRn_COUNT 4
     99
     100/* #define INB_AXIRERRCLRn_COUNT (4) */
    58101    volatile uint32_t  AXIRERRCLR0;                            /*  AXIRERRCLR0     */
    59102    volatile uint32_t  AXIRERRCLR1;                            /*  AXIRERRCLR1     */
    60103    volatile uint32_t  AXIRERRCLR2;                            /*  AXIRERRCLR2     */
    61104    volatile uint32_t  AXIRERRCLR3;                            /*  AXIRERRCLR3     */
    62 };
     105} r_io_inb_t;
    63106
    64107
    65 #define INB     (*(struct st_inb     *)0xFCFE1A00uL) /* INB */
    66 
    67 
    68 #define INBRMPR INB.RMPR
    69 #define INBAXIBUSCTL0 INB.AXIBUSCTL0
    70 #define INBAXIBUSCTL1 INB.AXIBUSCTL1
    71 #define INBAXIBUSCTL2 INB.AXIBUSCTL2
    72 #define INBAXIBUSCTL3 INB.AXIBUSCTL3
    73 #define INBAXIBUSCTL4 INB.AXIBUSCTL4
    74 #define INBAXIBUSCTL5 INB.AXIBUSCTL5
    75 #define INBAXIBUSCTL6 INB.AXIBUSCTL6
    76 #define INBAXIBUSCTL7 INB.AXIBUSCTL7
    77 #define INBAXIBUSCTL8 INB.AXIBUSCTL8
    78 #define INBAXIBUSCTL9 INB.AXIBUSCTL9
    79 #define INBAXIBUSCTL10 INB.AXIBUSCTL10
    80 #define INBAXIRERRCTL0 INB.AXIRERRCTL0
    81 #define INBAXIRERRCTL1 INB.AXIRERRCTL1
    82 #define INBAXIRERRCTL2 INB.AXIRERRCTL2
    83 #define INBAXIRERRCTL3 INB.AXIRERRCTL3
    84 #define INBAXIRERRST0 INB.AXIRERRST0
    85 #define INBAXIRERRST1 INB.AXIRERRST1
    86 #define INBAXIRERRST2 INB.AXIRERRST2
    87 #define INBAXIRERRST3 INB.AXIRERRST3
    88 #define INBAXIRERRCLR0 INB.AXIRERRCLR0
    89 #define INBAXIRERRCLR1 INB.AXIRERRCLR1
    90 #define INBAXIRERRCLR2 INB.AXIRERRCLR2
    91 #define INBAXIRERRCLR3 INB.AXIRERRCLR3
     108/* <-SEC M1.10.1 */
     109/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     110/* <-QAC 0857 */
     111/* <-QAC 0639 */
    92112#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/intc_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef INTC_IODEFINE_H
    3030#define INTC_IODEFINE_H
    3131/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3234/* ->SEC M1.10.1 : Not magic number */
    3335
    34 struct st_intc
    35 {                                                          /* INTC             */
     36#define INTC    (*(struct st_intc    *)0xE8201000uL) /* INTC */
     37
     38
     39#define INTCICDDCR (INTC.ICDDCR)
     40#define INTCICDICTR (INTC.ICDICTR)
     41#define INTCICDIIDR (INTC.ICDIIDR)
     42#define INTCICDISR0 (INTC.ICDISR0)
     43#define INTCICDISR1 (INTC.ICDISR1)
     44#define INTCICDISR2 (INTC.ICDISR2)
     45#define INTCICDISR3 (INTC.ICDISR3)
     46#define INTCICDISR4 (INTC.ICDISR4)
     47#define INTCICDISR5 (INTC.ICDISR5)
     48#define INTCICDISR6 (INTC.ICDISR6)
     49#define INTCICDISR7 (INTC.ICDISR7)
     50#define INTCICDISR8 (INTC.ICDISR8)
     51#define INTCICDISR9 (INTC.ICDISR9)
     52#define INTCICDISR10 (INTC.ICDISR10)
     53#define INTCICDISR11 (INTC.ICDISR11)
     54#define INTCICDISR12 (INTC.ICDISR12)
     55#define INTCICDISR13 (INTC.ICDISR13)
     56#define INTCICDISR14 (INTC.ICDISR14)
     57#define INTCICDISR15 (INTC.ICDISR15)
     58#define INTCICDISR16 (INTC.ICDISR16)
     59#define INTCICDISR17 (INTC.ICDISR17)
     60#define INTCICDISR18 (INTC.ICDISR18)
     61#define INTCICDISER0 (INTC.ICDISER0)
     62#define INTCICDISER1 (INTC.ICDISER1)
     63#define INTCICDISER2 (INTC.ICDISER2)
     64#define INTCICDISER3 (INTC.ICDISER3)
     65#define INTCICDISER4 (INTC.ICDISER4)
     66#define INTCICDISER5 (INTC.ICDISER5)
     67#define INTCICDISER6 (INTC.ICDISER6)
     68#define INTCICDISER7 (INTC.ICDISER7)
     69#define INTCICDISER8 (INTC.ICDISER8)
     70#define INTCICDISER9 (INTC.ICDISER9)
     71#define INTCICDISER10 (INTC.ICDISER10)
     72#define INTCICDISER11 (INTC.ICDISER11)
     73#define INTCICDISER12 (INTC.ICDISER12)
     74#define INTCICDISER13 (INTC.ICDISER13)
     75#define INTCICDISER14 (INTC.ICDISER14)
     76#define INTCICDISER15 (INTC.ICDISER15)
     77#define INTCICDISER16 (INTC.ICDISER16)
     78#define INTCICDISER17 (INTC.ICDISER17)
     79#define INTCICDISER18 (INTC.ICDISER18)
     80#define INTCICDICER0 (INTC.ICDICER0)
     81#define INTCICDICER1 (INTC.ICDICER1)
     82#define INTCICDICER2 (INTC.ICDICER2)
     83#define INTCICDICER3 (INTC.ICDICER3)
     84#define INTCICDICER4 (INTC.ICDICER4)
     85#define INTCICDICER5 (INTC.ICDICER5)
     86#define INTCICDICER6 (INTC.ICDICER6)
     87#define INTCICDICER7 (INTC.ICDICER7)
     88#define INTCICDICER8 (INTC.ICDICER8)
     89#define INTCICDICER9 (INTC.ICDICER9)
     90#define INTCICDICER10 (INTC.ICDICER10)
     91#define INTCICDICER11 (INTC.ICDICER11)
     92#define INTCICDICER12 (INTC.ICDICER12)
     93#define INTCICDICER13 (INTC.ICDICER13)
     94#define INTCICDICER14 (INTC.ICDICER14)
     95#define INTCICDICER15 (INTC.ICDICER15)
     96#define INTCICDICER16 (INTC.ICDICER16)
     97#define INTCICDICER17 (INTC.ICDICER17)
     98#define INTCICDICER18 (INTC.ICDICER18)
     99#define INTCICDISPR0 (INTC.ICDISPR0)
     100#define INTCICDISPR1 (INTC.ICDISPR1)
     101#define INTCICDISPR2 (INTC.ICDISPR2)
     102#define INTCICDISPR3 (INTC.ICDISPR3)
     103#define INTCICDISPR4 (INTC.ICDISPR4)
     104#define INTCICDISPR5 (INTC.ICDISPR5)
     105#define INTCICDISPR6 (INTC.ICDISPR6)
     106#define INTCICDISPR7 (INTC.ICDISPR7)
     107#define INTCICDISPR8 (INTC.ICDISPR8)
     108#define INTCICDISPR9 (INTC.ICDISPR9)
     109#define INTCICDISPR10 (INTC.ICDISPR10)
     110#define INTCICDISPR11 (INTC.ICDISPR11)
     111#define INTCICDISPR12 (INTC.ICDISPR12)
     112#define INTCICDISPR13 (INTC.ICDISPR13)
     113#define INTCICDISPR14 (INTC.ICDISPR14)
     114#define INTCICDISPR15 (INTC.ICDISPR15)
     115#define INTCICDISPR16 (INTC.ICDISPR16)
     116#define INTCICDISPR17 (INTC.ICDISPR17)
     117#define INTCICDISPR18 (INTC.ICDISPR18)
     118#define INTCICDICPR0 (INTC.ICDICPR0)
     119#define INTCICDICPR1 (INTC.ICDICPR1)
     120#define INTCICDICPR2 (INTC.ICDICPR2)
     121#define INTCICDICPR3 (INTC.ICDICPR3)
     122#define INTCICDICPR4 (INTC.ICDICPR4)
     123#define INTCICDICPR5 (INTC.ICDICPR5)
     124#define INTCICDICPR6 (INTC.ICDICPR6)
     125#define INTCICDICPR7 (INTC.ICDICPR7)
     126#define INTCICDICPR8 (INTC.ICDICPR8)
     127#define INTCICDICPR9 (INTC.ICDICPR9)
     128#define INTCICDICPR10 (INTC.ICDICPR10)
     129#define INTCICDICPR11 (INTC.ICDICPR11)
     130#define INTCICDICPR12 (INTC.ICDICPR12)
     131#define INTCICDICPR13 (INTC.ICDICPR13)
     132#define INTCICDICPR14 (INTC.ICDICPR14)
     133#define INTCICDICPR15 (INTC.ICDICPR15)
     134#define INTCICDICPR16 (INTC.ICDICPR16)
     135#define INTCICDICPR17 (INTC.ICDICPR17)
     136#define INTCICDICPR18 (INTC.ICDICPR18)
     137#define INTCICDABR0 (INTC.ICDABR0)
     138#define INTCICDABR1 (INTC.ICDABR1)
     139#define INTCICDABR2 (INTC.ICDABR2)
     140#define INTCICDABR3 (INTC.ICDABR3)
     141#define INTCICDABR4 (INTC.ICDABR4)
     142#define INTCICDABR5 (INTC.ICDABR5)
     143#define INTCICDABR6 (INTC.ICDABR6)
     144#define INTCICDABR7 (INTC.ICDABR7)
     145#define INTCICDABR8 (INTC.ICDABR8)
     146#define INTCICDABR9 (INTC.ICDABR9)
     147#define INTCICDABR10 (INTC.ICDABR10)
     148#define INTCICDABR11 (INTC.ICDABR11)
     149#define INTCICDABR12 (INTC.ICDABR12)
     150#define INTCICDABR13 (INTC.ICDABR13)
     151#define INTCICDABR14 (INTC.ICDABR14)
     152#define INTCICDABR15 (INTC.ICDABR15)
     153#define INTCICDABR16 (INTC.ICDABR16)
     154#define INTCICDABR17 (INTC.ICDABR17)
     155#define INTCICDABR18 (INTC.ICDABR18)
     156#define INTCICDIPR0 (INTC.ICDIPR0)
     157#define INTCICDIPR1 (INTC.ICDIPR1)
     158#define INTCICDIPR2 (INTC.ICDIPR2)
     159#define INTCICDIPR3 (INTC.ICDIPR3)
     160#define INTCICDIPR4 (INTC.ICDIPR4)
     161#define INTCICDIPR5 (INTC.ICDIPR5)
     162#define INTCICDIPR6 (INTC.ICDIPR6)
     163#define INTCICDIPR7 (INTC.ICDIPR7)
     164#define INTCICDIPR8 (INTC.ICDIPR8)
     165#define INTCICDIPR9 (INTC.ICDIPR9)
     166#define INTCICDIPR10 (INTC.ICDIPR10)
     167#define INTCICDIPR11 (INTC.ICDIPR11)
     168#define INTCICDIPR12 (INTC.ICDIPR12)
     169#define INTCICDIPR13 (INTC.ICDIPR13)
     170#define INTCICDIPR14 (INTC.ICDIPR14)
     171#define INTCICDIPR15 (INTC.ICDIPR15)
     172#define INTCICDIPR16 (INTC.ICDIPR16)
     173#define INTCICDIPR17 (INTC.ICDIPR17)
     174#define INTCICDIPR18 (INTC.ICDIPR18)
     175#define INTCICDIPR19 (INTC.ICDIPR19)
     176#define INTCICDIPR20 (INTC.ICDIPR20)
     177#define INTCICDIPR21 (INTC.ICDIPR21)
     178#define INTCICDIPR22 (INTC.ICDIPR22)
     179#define INTCICDIPR23 (INTC.ICDIPR23)
     180#define INTCICDIPR24 (INTC.ICDIPR24)
     181#define INTCICDIPR25 (INTC.ICDIPR25)
     182#define INTCICDIPR26 (INTC.ICDIPR26)
     183#define INTCICDIPR27 (INTC.ICDIPR27)
     184#define INTCICDIPR28 (INTC.ICDIPR28)
     185#define INTCICDIPR29 (INTC.ICDIPR29)
     186#define INTCICDIPR30 (INTC.ICDIPR30)
     187#define INTCICDIPR31 (INTC.ICDIPR31)
     188#define INTCICDIPR32 (INTC.ICDIPR32)
     189#define INTCICDIPR33 (INTC.ICDIPR33)
     190#define INTCICDIPR34 (INTC.ICDIPR34)
     191#define INTCICDIPR35 (INTC.ICDIPR35)
     192#define INTCICDIPR36 (INTC.ICDIPR36)
     193#define INTCICDIPR37 (INTC.ICDIPR37)
     194#define INTCICDIPR38 (INTC.ICDIPR38)
     195#define INTCICDIPR39 (INTC.ICDIPR39)
     196#define INTCICDIPR40 (INTC.ICDIPR40)
     197#define INTCICDIPR41 (INTC.ICDIPR41)
     198#define INTCICDIPR42 (INTC.ICDIPR42)
     199#define INTCICDIPR43 (INTC.ICDIPR43)
     200#define INTCICDIPR44 (INTC.ICDIPR44)
     201#define INTCICDIPR45 (INTC.ICDIPR45)
     202#define INTCICDIPR46 (INTC.ICDIPR46)
     203#define INTCICDIPR47 (INTC.ICDIPR47)
     204#define INTCICDIPR48 (INTC.ICDIPR48)
     205#define INTCICDIPR49 (INTC.ICDIPR49)
     206#define INTCICDIPR50 (INTC.ICDIPR50)
     207#define INTCICDIPR51 (INTC.ICDIPR51)
     208#define INTCICDIPR52 (INTC.ICDIPR52)
     209#define INTCICDIPR53 (INTC.ICDIPR53)
     210#define INTCICDIPR54 (INTC.ICDIPR54)
     211#define INTCICDIPR55 (INTC.ICDIPR55)
     212#define INTCICDIPR56 (INTC.ICDIPR56)
     213#define INTCICDIPR57 (INTC.ICDIPR57)
     214#define INTCICDIPR58 (INTC.ICDIPR58)
     215#define INTCICDIPR59 (INTC.ICDIPR59)
     216#define INTCICDIPR60 (INTC.ICDIPR60)
     217#define INTCICDIPR61 (INTC.ICDIPR61)
     218#define INTCICDIPR62 (INTC.ICDIPR62)
     219#define INTCICDIPR63 (INTC.ICDIPR63)
     220#define INTCICDIPR64 (INTC.ICDIPR64)
     221#define INTCICDIPR65 (INTC.ICDIPR65)
     222#define INTCICDIPR66 (INTC.ICDIPR66)
     223#define INTCICDIPR67 (INTC.ICDIPR67)
     224#define INTCICDIPR68 (INTC.ICDIPR68)
     225#define INTCICDIPR69 (INTC.ICDIPR69)
     226#define INTCICDIPR70 (INTC.ICDIPR70)
     227#define INTCICDIPR71 (INTC.ICDIPR71)
     228#define INTCICDIPR72 (INTC.ICDIPR72)
     229#define INTCICDIPR73 (INTC.ICDIPR73)
     230#define INTCICDIPR74 (INTC.ICDIPR74)
     231#define INTCICDIPR75 (INTC.ICDIPR75)
     232#define INTCICDIPR76 (INTC.ICDIPR76)
     233#define INTCICDIPR77 (INTC.ICDIPR77)
     234#define INTCICDIPR78 (INTC.ICDIPR78)
     235#define INTCICDIPR79 (INTC.ICDIPR79)
     236#define INTCICDIPR80 (INTC.ICDIPR80)
     237#define INTCICDIPR81 (INTC.ICDIPR81)
     238#define INTCICDIPR82 (INTC.ICDIPR82)
     239#define INTCICDIPR83 (INTC.ICDIPR83)
     240#define INTCICDIPR84 (INTC.ICDIPR84)
     241#define INTCICDIPR85 (INTC.ICDIPR85)
     242#define INTCICDIPR86 (INTC.ICDIPR86)
     243#define INTCICDIPR87 (INTC.ICDIPR87)
     244#define INTCICDIPR88 (INTC.ICDIPR88)
     245#define INTCICDIPR89 (INTC.ICDIPR89)
     246#define INTCICDIPR90 (INTC.ICDIPR90)
     247#define INTCICDIPR91 (INTC.ICDIPR91)
     248#define INTCICDIPR92 (INTC.ICDIPR92)
     249#define INTCICDIPR93 (INTC.ICDIPR93)
     250#define INTCICDIPR94 (INTC.ICDIPR94)
     251#define INTCICDIPR95 (INTC.ICDIPR95)
     252#define INTCICDIPR96 (INTC.ICDIPR96)
     253#define INTCICDIPR97 (INTC.ICDIPR97)
     254#define INTCICDIPR98 (INTC.ICDIPR98)
     255#define INTCICDIPR99 (INTC.ICDIPR99)
     256#define INTCICDIPR100 (INTC.ICDIPR100)
     257#define INTCICDIPR101 (INTC.ICDIPR101)
     258#define INTCICDIPR102 (INTC.ICDIPR102)
     259#define INTCICDIPR103 (INTC.ICDIPR103)
     260#define INTCICDIPR104 (INTC.ICDIPR104)
     261#define INTCICDIPR105 (INTC.ICDIPR105)
     262#define INTCICDIPR106 (INTC.ICDIPR106)
     263#define INTCICDIPR107 (INTC.ICDIPR107)
     264#define INTCICDIPR108 (INTC.ICDIPR108)
     265#define INTCICDIPR109 (INTC.ICDIPR109)
     266#define INTCICDIPR110 (INTC.ICDIPR110)
     267#define INTCICDIPR111 (INTC.ICDIPR111)
     268#define INTCICDIPR112 (INTC.ICDIPR112)
     269#define INTCICDIPR113 (INTC.ICDIPR113)
     270#define INTCICDIPR114 (INTC.ICDIPR114)
     271#define INTCICDIPR115 (INTC.ICDIPR115)
     272#define INTCICDIPR116 (INTC.ICDIPR116)
     273#define INTCICDIPR117 (INTC.ICDIPR117)
     274#define INTCICDIPR118 (INTC.ICDIPR118)
     275#define INTCICDIPR119 (INTC.ICDIPR119)
     276#define INTCICDIPR120 (INTC.ICDIPR120)
     277#define INTCICDIPR121 (INTC.ICDIPR121)
     278#define INTCICDIPR122 (INTC.ICDIPR122)
     279#define INTCICDIPR123 (INTC.ICDIPR123)
     280#define INTCICDIPR124 (INTC.ICDIPR124)
     281#define INTCICDIPR125 (INTC.ICDIPR125)
     282#define INTCICDIPR126 (INTC.ICDIPR126)
     283#define INTCICDIPR127 (INTC.ICDIPR127)
     284#define INTCICDIPR128 (INTC.ICDIPR128)
     285#define INTCICDIPR129 (INTC.ICDIPR129)
     286#define INTCICDIPR130 (INTC.ICDIPR130)
     287#define INTCICDIPR131 (INTC.ICDIPR131)
     288#define INTCICDIPR132 (INTC.ICDIPR132)
     289#define INTCICDIPR133 (INTC.ICDIPR133)
     290#define INTCICDIPR134 (INTC.ICDIPR134)
     291#define INTCICDIPR135 (INTC.ICDIPR135)
     292#define INTCICDIPR136 (INTC.ICDIPR136)
     293#define INTCICDIPR137 (INTC.ICDIPR137)
     294#define INTCICDIPR138 (INTC.ICDIPR138)
     295#define INTCICDIPR139 (INTC.ICDIPR139)
     296#define INTCICDIPR140 (INTC.ICDIPR140)
     297#define INTCICDIPR141 (INTC.ICDIPR141)
     298#define INTCICDIPR142 (INTC.ICDIPR142)
     299#define INTCICDIPR143 (INTC.ICDIPR143)
     300#define INTCICDIPR144 (INTC.ICDIPR144)
     301#define INTCICDIPR145 (INTC.ICDIPR145)
     302#define INTCICDIPR146 (INTC.ICDIPR146)
     303#define INTCICDIPTR0 (INTC.ICDIPTR0)
     304#define INTCICDIPTR1 (INTC.ICDIPTR1)
     305#define INTCICDIPTR2 (INTC.ICDIPTR2)
     306#define INTCICDIPTR3 (INTC.ICDIPTR3)
     307#define INTCICDIPTR4 (INTC.ICDIPTR4)
     308#define INTCICDIPTR5 (INTC.ICDIPTR5)
     309#define INTCICDIPTR6 (INTC.ICDIPTR6)
     310#define INTCICDIPTR7 (INTC.ICDIPTR7)
     311#define INTCICDIPTR8 (INTC.ICDIPTR8)
     312#define INTCICDIPTR9 (INTC.ICDIPTR9)
     313#define INTCICDIPTR10 (INTC.ICDIPTR10)
     314#define INTCICDIPTR11 (INTC.ICDIPTR11)
     315#define INTCICDIPTR12 (INTC.ICDIPTR12)
     316#define INTCICDIPTR13 (INTC.ICDIPTR13)
     317#define INTCICDIPTR14 (INTC.ICDIPTR14)
     318#define INTCICDIPTR15 (INTC.ICDIPTR15)
     319#define INTCICDIPTR16 (INTC.ICDIPTR16)
     320#define INTCICDIPTR17 (INTC.ICDIPTR17)
     321#define INTCICDIPTR18 (INTC.ICDIPTR18)
     322#define INTCICDIPTR19 (INTC.ICDIPTR19)
     323#define INTCICDIPTR20 (INTC.ICDIPTR20)
     324#define INTCICDIPTR21 (INTC.ICDIPTR21)
     325#define INTCICDIPTR22 (INTC.ICDIPTR22)
     326#define INTCICDIPTR23 (INTC.ICDIPTR23)
     327#define INTCICDIPTR24 (INTC.ICDIPTR24)
     328#define INTCICDIPTR25 (INTC.ICDIPTR25)
     329#define INTCICDIPTR26 (INTC.ICDIPTR26)
     330#define INTCICDIPTR27 (INTC.ICDIPTR27)
     331#define INTCICDIPTR28 (INTC.ICDIPTR28)
     332#define INTCICDIPTR29 (INTC.ICDIPTR29)
     333#define INTCICDIPTR30 (INTC.ICDIPTR30)
     334#define INTCICDIPTR31 (INTC.ICDIPTR31)
     335#define INTCICDIPTR32 (INTC.ICDIPTR32)
     336#define INTCICDIPTR33 (INTC.ICDIPTR33)
     337#define INTCICDIPTR34 (INTC.ICDIPTR34)
     338#define INTCICDIPTR35 (INTC.ICDIPTR35)
     339#define INTCICDIPTR36 (INTC.ICDIPTR36)
     340#define INTCICDIPTR37 (INTC.ICDIPTR37)
     341#define INTCICDIPTR38 (INTC.ICDIPTR38)
     342#define INTCICDIPTR39 (INTC.ICDIPTR39)
     343#define INTCICDIPTR40 (INTC.ICDIPTR40)
     344#define INTCICDIPTR41 (INTC.ICDIPTR41)
     345#define INTCICDIPTR42 (INTC.ICDIPTR42)
     346#define INTCICDIPTR43 (INTC.ICDIPTR43)
     347#define INTCICDIPTR44 (INTC.ICDIPTR44)
     348#define INTCICDIPTR45 (INTC.ICDIPTR45)
     349#define INTCICDIPTR46 (INTC.ICDIPTR46)
     350#define INTCICDIPTR47 (INTC.ICDIPTR47)
     351#define INTCICDIPTR48 (INTC.ICDIPTR48)
     352#define INTCICDIPTR49 (INTC.ICDIPTR49)
     353#define INTCICDIPTR50 (INTC.ICDIPTR50)
     354#define INTCICDIPTR51 (INTC.ICDIPTR51)
     355#define INTCICDIPTR52 (INTC.ICDIPTR52)
     356#define INTCICDIPTR53 (INTC.ICDIPTR53)
     357#define INTCICDIPTR54 (INTC.ICDIPTR54)
     358#define INTCICDIPTR55 (INTC.ICDIPTR55)
     359#define INTCICDIPTR56 (INTC.ICDIPTR56)
     360#define INTCICDIPTR57 (INTC.ICDIPTR57)
     361#define INTCICDIPTR58 (INTC.ICDIPTR58)
     362#define INTCICDIPTR59 (INTC.ICDIPTR59)
     363#define INTCICDIPTR60 (INTC.ICDIPTR60)
     364#define INTCICDIPTR61 (INTC.ICDIPTR61)
     365#define INTCICDIPTR62 (INTC.ICDIPTR62)
     366#define INTCICDIPTR63 (INTC.ICDIPTR63)
     367#define INTCICDIPTR64 (INTC.ICDIPTR64)
     368#define INTCICDIPTR65 (INTC.ICDIPTR65)
     369#define INTCICDIPTR66 (INTC.ICDIPTR66)
     370#define INTCICDIPTR67 (INTC.ICDIPTR67)
     371#define INTCICDIPTR68 (INTC.ICDIPTR68)
     372#define INTCICDIPTR69 (INTC.ICDIPTR69)
     373#define INTCICDIPTR70 (INTC.ICDIPTR70)
     374#define INTCICDIPTR71 (INTC.ICDIPTR71)
     375#define INTCICDIPTR72 (INTC.ICDIPTR72)
     376#define INTCICDIPTR73 (INTC.ICDIPTR73)
     377#define INTCICDIPTR74 (INTC.ICDIPTR74)
     378#define INTCICDIPTR75 (INTC.ICDIPTR75)
     379#define INTCICDIPTR76 (INTC.ICDIPTR76)
     380#define INTCICDIPTR77 (INTC.ICDIPTR77)
     381#define INTCICDIPTR78 (INTC.ICDIPTR78)
     382#define INTCICDIPTR79 (INTC.ICDIPTR79)
     383#define INTCICDIPTR80 (INTC.ICDIPTR80)
     384#define INTCICDIPTR81 (INTC.ICDIPTR81)
     385#define INTCICDIPTR82 (INTC.ICDIPTR82)
     386#define INTCICDIPTR83 (INTC.ICDIPTR83)
     387#define INTCICDIPTR84 (INTC.ICDIPTR84)
     388#define INTCICDIPTR85 (INTC.ICDIPTR85)
     389#define INTCICDIPTR86 (INTC.ICDIPTR86)
     390#define INTCICDIPTR87 (INTC.ICDIPTR87)
     391#define INTCICDIPTR88 (INTC.ICDIPTR88)
     392#define INTCICDIPTR89 (INTC.ICDIPTR89)
     393#define INTCICDIPTR90 (INTC.ICDIPTR90)
     394#define INTCICDIPTR91 (INTC.ICDIPTR91)
     395#define INTCICDIPTR92 (INTC.ICDIPTR92)
     396#define INTCICDIPTR93 (INTC.ICDIPTR93)
     397#define INTCICDIPTR94 (INTC.ICDIPTR94)
     398#define INTCICDIPTR95 (INTC.ICDIPTR95)
     399#define INTCICDIPTR96 (INTC.ICDIPTR96)
     400#define INTCICDIPTR97 (INTC.ICDIPTR97)
     401#define INTCICDIPTR98 (INTC.ICDIPTR98)
     402#define INTCICDIPTR99 (INTC.ICDIPTR99)
     403#define INTCICDIPTR100 (INTC.ICDIPTR100)
     404#define INTCICDIPTR101 (INTC.ICDIPTR101)
     405#define INTCICDIPTR102 (INTC.ICDIPTR102)
     406#define INTCICDIPTR103 (INTC.ICDIPTR103)
     407#define INTCICDIPTR104 (INTC.ICDIPTR104)
     408#define INTCICDIPTR105 (INTC.ICDIPTR105)
     409#define INTCICDIPTR106 (INTC.ICDIPTR106)
     410#define INTCICDIPTR107 (INTC.ICDIPTR107)
     411#define INTCICDIPTR108 (INTC.ICDIPTR108)
     412#define INTCICDIPTR109 (INTC.ICDIPTR109)
     413#define INTCICDIPTR110 (INTC.ICDIPTR110)
     414#define INTCICDIPTR111 (INTC.ICDIPTR111)
     415#define INTCICDIPTR112 (INTC.ICDIPTR112)
     416#define INTCICDIPTR113 (INTC.ICDIPTR113)
     417#define INTCICDIPTR114 (INTC.ICDIPTR114)
     418#define INTCICDIPTR115 (INTC.ICDIPTR115)
     419#define INTCICDIPTR116 (INTC.ICDIPTR116)
     420#define INTCICDIPTR117 (INTC.ICDIPTR117)
     421#define INTCICDIPTR118 (INTC.ICDIPTR118)
     422#define INTCICDIPTR119 (INTC.ICDIPTR119)
     423#define INTCICDIPTR120 (INTC.ICDIPTR120)
     424#define INTCICDIPTR121 (INTC.ICDIPTR121)
     425#define INTCICDIPTR122 (INTC.ICDIPTR122)
     426#define INTCICDIPTR123 (INTC.ICDIPTR123)
     427#define INTCICDIPTR124 (INTC.ICDIPTR124)
     428#define INTCICDIPTR125 (INTC.ICDIPTR125)
     429#define INTCICDIPTR126 (INTC.ICDIPTR126)
     430#define INTCICDIPTR127 (INTC.ICDIPTR127)
     431#define INTCICDIPTR128 (INTC.ICDIPTR128)
     432#define INTCICDIPTR129 (INTC.ICDIPTR129)
     433#define INTCICDIPTR130 (INTC.ICDIPTR130)
     434#define INTCICDIPTR131 (INTC.ICDIPTR131)
     435#define INTCICDIPTR132 (INTC.ICDIPTR132)
     436#define INTCICDIPTR133 (INTC.ICDIPTR133)
     437#define INTCICDIPTR134 (INTC.ICDIPTR134)
     438#define INTCICDIPTR135 (INTC.ICDIPTR135)
     439#define INTCICDIPTR136 (INTC.ICDIPTR136)
     440#define INTCICDIPTR137 (INTC.ICDIPTR137)
     441#define INTCICDIPTR138 (INTC.ICDIPTR138)
     442#define INTCICDIPTR139 (INTC.ICDIPTR139)
     443#define INTCICDIPTR140 (INTC.ICDIPTR140)
     444#define INTCICDIPTR141 (INTC.ICDIPTR141)
     445#define INTCICDIPTR142 (INTC.ICDIPTR142)
     446#define INTCICDIPTR143 (INTC.ICDIPTR143)
     447#define INTCICDIPTR144 (INTC.ICDIPTR144)
     448#define INTCICDIPTR145 (INTC.ICDIPTR145)
     449#define INTCICDIPTR146 (INTC.ICDIPTR146)
     450#define INTCICDICFR0 (INTC.ICDICFR0)
     451#define INTCICDICFR1 (INTC.ICDICFR1)
     452#define INTCICDICFR2 (INTC.ICDICFR2)
     453#define INTCICDICFR3 (INTC.ICDICFR3)
     454#define INTCICDICFR4 (INTC.ICDICFR4)
     455#define INTCICDICFR5 (INTC.ICDICFR5)
     456#define INTCICDICFR6 (INTC.ICDICFR6)
     457#define INTCICDICFR7 (INTC.ICDICFR7)
     458#define INTCICDICFR8 (INTC.ICDICFR8)
     459#define INTCICDICFR9 (INTC.ICDICFR9)
     460#define INTCICDICFR10 (INTC.ICDICFR10)
     461#define INTCICDICFR11 (INTC.ICDICFR11)
     462#define INTCICDICFR12 (INTC.ICDICFR12)
     463#define INTCICDICFR13 (INTC.ICDICFR13)
     464#define INTCICDICFR14 (INTC.ICDICFR14)
     465#define INTCICDICFR15 (INTC.ICDICFR15)
     466#define INTCICDICFR16 (INTC.ICDICFR16)
     467#define INTCICDICFR17 (INTC.ICDICFR17)
     468#define INTCICDICFR18 (INTC.ICDICFR18)
     469#define INTCICDICFR19 (INTC.ICDICFR19)
     470#define INTCICDICFR20 (INTC.ICDICFR20)
     471#define INTCICDICFR21 (INTC.ICDICFR21)
     472#define INTCICDICFR22 (INTC.ICDICFR22)
     473#define INTCICDICFR23 (INTC.ICDICFR23)
     474#define INTCICDICFR24 (INTC.ICDICFR24)
     475#define INTCICDICFR25 (INTC.ICDICFR25)
     476#define INTCICDICFR26 (INTC.ICDICFR26)
     477#define INTCICDICFR27 (INTC.ICDICFR27)
     478#define INTCICDICFR28 (INTC.ICDICFR28)
     479#define INTCICDICFR29 (INTC.ICDICFR29)
     480#define INTCICDICFR30 (INTC.ICDICFR30)
     481#define INTCICDICFR31 (INTC.ICDICFR31)
     482#define INTCICDICFR32 (INTC.ICDICFR32)
     483#define INTCICDICFR33 (INTC.ICDICFR33)
     484#define INTCICDICFR34 (INTC.ICDICFR34)
     485#define INTCICDICFR35 (INTC.ICDICFR35)
     486#define INTCICDICFR36 (INTC.ICDICFR36)
     487#define INTCPPI_STATUS (INTC.PPI_STATUS)
     488#define INTCSPI_STATUS0 (INTC.SPI_STATUS0)
     489#define INTCSPI_STATUS1 (INTC.SPI_STATUS1)
     490#define INTCSPI_STATUS2 (INTC.SPI_STATUS2)
     491#define INTCSPI_STATUS3 (INTC.SPI_STATUS3)
     492#define INTCSPI_STATUS4 (INTC.SPI_STATUS4)
     493#define INTCSPI_STATUS5 (INTC.SPI_STATUS5)
     494#define INTCSPI_STATUS6 (INTC.SPI_STATUS6)
     495#define INTCSPI_STATUS7 (INTC.SPI_STATUS7)
     496#define INTCSPI_STATUS8 (INTC.SPI_STATUS8)
     497#define INTCSPI_STATUS9 (INTC.SPI_STATUS9)
     498#define INTCSPI_STATUS10 (INTC.SPI_STATUS10)
     499#define INTCSPI_STATUS11 (INTC.SPI_STATUS11)
     500#define INTCSPI_STATUS12 (INTC.SPI_STATUS12)
     501#define INTCSPI_STATUS13 (INTC.SPI_STATUS13)
     502#define INTCSPI_STATUS14 (INTC.SPI_STATUS14)
     503#define INTCSPI_STATUS15 (INTC.SPI_STATUS15)
     504#define INTCSPI_STATUS16 (INTC.SPI_STATUS16)
     505#define INTCICDSGIR (INTC.ICDSGIR)
     506#define INTCICCICR (INTC.ICCICR)
     507#define INTCICCPMR (INTC.ICCPMR)
     508#define INTCICCBPR (INTC.ICCBPR)
     509#define INTCICCIAR (INTC.ICCIAR)
     510#define INTCICCEOIR (INTC.ICCEOIR)
     511#define INTCICCRPR (INTC.ICCRPR)
     512#define INTCICCHPIR (INTC.ICCHPIR)
     513#define INTCICCABPR (INTC.ICCABPR)
     514#define INTCICCIIDR (INTC.ICCIIDR)
     515#define INTCICR0 (INTC.ICR0)
     516#define INTCICR1 (INTC.ICR1)
     517#define INTCIRQRR (INTC.IRQRR)
     518
     519#define INTC_ICDISR0_COUNT (19)
     520#define INTC_ICDISER0_COUNT (19)
     521#define INTC_ICDICER0_COUNT (19)
     522#define INTC_ICDISPR0_COUNT (19)
     523#define INTC_ICDICPR0_COUNT (19)
     524#define INTC_ICDABR0_COUNT (19)
     525#define INTC_ICDIPR0_COUNT (147)
     526#define INTC_ICDIPTR0_COUNT (147)
     527#define INTC_ICDICFR0_COUNT (37)
     528#define INTC_SPI_STATUS0_COUNT (17)
     529
     530
     531typedef struct st_intc
     532{
     533                                                           /* INTC             */
    36534    volatile uint32_t  ICDDCR;                                 /*  ICDDCR          */
    37535    volatile uint32_t  ICDICTR;                                /*  ICDICTR         */
    38536    volatile uint32_t  ICDIIDR;                                /*  ICDIIDR         */
    39537    volatile uint8_t   dummy193[116];                          /*                  */
    40 #define INTC_ICDISR0_COUNT 19
     538
     539/* #define INTC_ICDISR0_COUNT (19) */
    41540    volatile uint32_t  ICDISR0;                                /*  ICDISR0         */
    42541    volatile uint32_t  ICDISR1;                                /*  ICDISR1         */
    … …  
    59558    volatile uint32_t  ICDISR18;                               /*  ICDISR18        */
    60559    volatile uint8_t   dummy194[52];                           /*                  */
    61 #define INTC_ICDISER0_COUNT 19
     560
     561/* #define INTC_ICDISER0_COUNT (19) */
    62562    volatile uint32_t  ICDISER0;                               /*  ICDISER0        */
    63563    volatile uint32_t  ICDISER1;                               /*  ICDISER1        */
    … …  
    80580    volatile uint32_t  ICDISER18;                              /*  ICDISER18       */
    81581    volatile uint8_t   dummy195[52];                           /*                  */
    82 #define INTC_ICDICER0_COUNT 19
     582
     583/* #define INTC_ICDICER0_COUNT (19) */
    83584    volatile uint32_t  ICDICER0;                               /*  ICDICER0        */
    84585    volatile uint32_t  ICDICER1;                               /*  ICDICER1        */
    … …  
    101602    volatile uint32_t  ICDICER18;                              /*  ICDICER18       */
    102603    volatile uint8_t   dummy196[52];                           /*                  */
    103 #define INTC_ICDISPR0_COUNT 19
     604
     605/* #define INTC_ICDISPR0_COUNT (19) */
    104606    volatile uint32_t  ICDISPR0;                               /*  ICDISPR0        */
    105607    volatile uint32_t  ICDISPR1;                               /*  ICDISPR1        */
    … …  
    122624    volatile uint32_t  ICDISPR18;                              /*  ICDISPR18       */
    123625    volatile uint8_t   dummy197[52];                           /*                  */
    124 #define INTC_ICDICPR0_COUNT 19
     626
     627/* #define INTC_ICDICPR0_COUNT (19) */
    125628    volatile uint32_t  ICDICPR0;                               /*  ICDICPR0        */
    126629    volatile uint32_t  ICDICPR1;                               /*  ICDICPR1        */
    … …  
    143646    volatile uint32_t  ICDICPR18;                              /*  ICDICPR18       */
    144647    volatile uint8_t   dummy198[52];                           /*                  */
    145 #define INTC_ICDABR0_COUNT 19
     648
     649/* #define INTC_ICDABR0_COUNT (19) */
    146650    volatile uint32_t  ICDABR0;                                /*  ICDABR0         */
    147651    volatile uint32_t  ICDABR1;                                /*  ICDABR1         */
    … …  
    164668    volatile uint32_t  ICDABR18;                               /*  ICDABR18        */
    165669    volatile uint8_t   dummy199[180];                          /*                  */
    166 #define INTC_ICDIPR0_COUNT 147
     670
     671/* #define INTC_ICDIPR0_COUNT (147) */
    167672    volatile uint32_t  ICDIPR0;                                /*  ICDIPR0         */
    168673    volatile uint32_t  ICDIPR1;                                /*  ICDIPR1         */
    … …  
    313818    volatile uint32_t  ICDIPR146;                              /*  ICDIPR146       */
    314819    volatile uint8_t   dummy200[436];                          /*                  */
    315 #define INTC_ICDIPTR0_COUNT 147
     820
     821/* #define INTC_ICDIPTR0_COUNT (147) */
    316822    volatile uint32_t  ICDIPTR0;                               /*  ICDIPTR0        */
    317823    volatile uint32_t  ICDIPTR1;                               /*  ICDIPTR1        */
    … …  
    462968    volatile uint32_t  ICDIPTR146;                             /*  ICDIPTR146      */
    463969    volatile uint8_t   dummy201[436];                          /*                  */
    464 #define INTC_ICDICFR0_COUNT 37
     970
     971/* #define INTC_ICDICFR0_COUNT (37) */
    465972    volatile uint32_t  ICDICFR0;                               /*  ICDICFR0        */
    466973    volatile uint32_t  ICDICFR1;                               /*  ICDICFR1        */
    … …  
    5021009    volatile uint8_t   dummy202[108];                          /*                  */
    5031010    volatile uint32_t  PPI_STATUS;                             /*  PPI_STATUS      */
    504 #define INTC_SPI_STATUS0_COUNT 17
     1011
     1012/* #define INTC_SPI_STATUS0_COUNT (17) */
    5051013    volatile uint32_t  SPI_STATUS0;                            /*  SPI_STATUS0     */
    5061014    volatile uint32_t  SPI_STATUS1;                            /*  SPI_STATUS1     */
    … …  
    5371045    volatile uint16_t ICR1;                                   /*  ICR1            */
    5381046    volatile uint16_t IRQRR;                                  /*  IRQRR           */
    539 };
    540 
    541 
    542 #define INTC    (*(struct st_intc    *)0xE8201000uL) /* INTC */
    543 
    544 
    545 #define INTCICDDCR INTC.ICDDCR
    546 #define INTCICDICTR INTC.ICDICTR
    547 #define INTCICDIIDR INTC.ICDIIDR
    548 #define INTCICDISR0 INTC.ICDISR0
    549 #define INTCICDISR1 INTC.ICDISR1
    550 #define INTCICDISR2 INTC.ICDISR2
    551 #define INTCICDISR3 INTC.ICDISR3
    552 #define INTCICDISR4 INTC.ICDISR4
    553 #define INTCICDISR5 INTC.ICDISR5
    554 #define INTCICDISR6 INTC.ICDISR6
    555 #define INTCICDISR7 INTC.ICDISR7
    556 #define INTCICDISR8 INTC.ICDISR8
    557 #define INTCICDISR9 INTC.ICDISR9
    558 #define INTCICDISR10 INTC.ICDISR10
    559 #define INTCICDISR11 INTC.ICDISR11
    560 #define INTCICDISR12 INTC.ICDISR12
    561 #define INTCICDISR13 INTC.ICDISR13
    562 #define INTCICDISR14 INTC.ICDISR14
    563 #define INTCICDISR15 INTC.ICDISR15
    564 #define INTCICDISR16 INTC.ICDISR16
    565 #define INTCICDISR17 INTC.ICDISR17
    566 #define INTCICDISR18 INTC.ICDISR18
    567 #define INTCICDISER0 INTC.ICDISER0
    568 #define INTCICDISER1 INTC.ICDISER1
    569 #define INTCICDISER2 INTC.ICDISER2
    570 #define INTCICDISER3 INTC.ICDISER3
    571 #define INTCICDISER4 INTC.ICDISER4
    572 #define INTCICDISER5 INTC.ICDISER5
    573 #define INTCICDISER6 INTC.ICDISER6
    574 #define INTCICDISER7 INTC.ICDISER7
    575 #define INTCICDISER8 INTC.ICDISER8
    576 #define INTCICDISER9 INTC.ICDISER9
    577 #define INTCICDISER10 INTC.ICDISER10
    578 #define INTCICDISER11 INTC.ICDISER11
    579 #define INTCICDISER12 INTC.ICDISER12
    580 #define INTCICDISER13 INTC.ICDISER13
    581 #define INTCICDISER14 INTC.ICDISER14
    582 #define INTCICDISER15 INTC.ICDISER15
    583 #define INTCICDISER16 INTC.ICDISER16
    584 #define INTCICDISER17 INTC.ICDISER17
    585 #define INTCICDISER18 INTC.ICDISER18
    586 #define INTCICDICER0 INTC.ICDICER0
    587 #define INTCICDICER1 INTC.ICDICER1
    588 #define INTCICDICER2 INTC.ICDICER2
    589 #define INTCICDICER3 INTC.ICDICER3
    590 #define INTCICDICER4 INTC.ICDICER4
    591 #define INTCICDICER5 INTC.ICDICER5
    592 #define INTCICDICER6 INTC.ICDICER6
    593 #define INTCICDICER7 INTC.ICDICER7
    594 #define INTCICDICER8 INTC.ICDICER8
    595 #define INTCICDICER9 INTC.ICDICER9
    596 #define INTCICDICER10 INTC.ICDICER10
    597 #define INTCICDICER11 INTC.ICDICER11
    598 #define INTCICDICER12 INTC.ICDICER12
    599 #define INTCICDICER13 INTC.ICDICER13
    600 #define INTCICDICER14 INTC.ICDICER14
    601 #define INTCICDICER15 INTC.ICDICER15
    602 #define INTCICDICER16 INTC.ICDICER16
    603 #define INTCICDICER17 INTC.ICDICER17
    604 #define INTCICDICER18 INTC.ICDICER18
    605 #define INTCICDISPR0 INTC.ICDISPR0
    606 #define INTCICDISPR1 INTC.ICDISPR1
    607 #define INTCICDISPR2 INTC.ICDISPR2
    608 #define INTCICDISPR3 INTC.ICDISPR3
    609 #define INTCICDISPR4 INTC.ICDISPR4
    610 #define INTCICDISPR5 INTC.ICDISPR5
    611 #define INTCICDISPR6 INTC.ICDISPR6
    612 #define INTCICDISPR7 INTC.ICDISPR7
    613 #define INTCICDISPR8 INTC.ICDISPR8
    614 #define INTCICDISPR9 INTC.ICDISPR9
    615 #define INTCICDISPR10 INTC.ICDISPR10
    616 #define INTCICDISPR11 INTC.ICDISPR11
    617 #define INTCICDISPR12 INTC.ICDISPR12
    618 #define INTCICDISPR13 INTC.ICDISPR13
    619 #define INTCICDISPR14 INTC.ICDISPR14
    620 #define INTCICDISPR15 INTC.ICDISPR15
    621 #define INTCICDISPR16 INTC.ICDISPR16
    622 #define INTCICDISPR17 INTC.ICDISPR17
    623 #define INTCICDISPR18 INTC.ICDISPR18
    624 #define INTCICDICPR0 INTC.ICDICPR0
    625 #define INTCICDICPR1 INTC.ICDICPR1
    626 #define INTCICDICPR2 INTC.ICDICPR2
    627 #define INTCICDICPR3 INTC.ICDICPR3
    628 #define INTCICDICPR4 INTC.ICDICPR4
    629 #define INTCICDICPR5 INTC.ICDICPR5
    630 #define INTCICDICPR6 INTC.ICDICPR6
    631 #define INTCICDICPR7 INTC.ICDICPR7
    632 #define INTCICDICPR8 INTC.ICDICPR8
    633 #define INTCICDICPR9 INTC.ICDICPR9
    634 #define INTCICDICPR10 INTC.ICDICPR10
    635 #define INTCICDICPR11 INTC.ICDICPR11
    636 #define INTCICDICPR12 INTC.ICDICPR12
    637 #define INTCICDICPR13 INTC.ICDICPR13
    638 #define INTCICDICPR14 INTC.ICDICPR14
    639 #define INTCICDICPR15 INTC.ICDICPR15
    640 #define INTCICDICPR16 INTC.ICDICPR16
    641 #define INTCICDICPR17 INTC.ICDICPR17
    642 #define INTCICDICPR18 INTC.ICDICPR18
    643 #define INTCICDABR0 INTC.ICDABR0
    644 #define INTCICDABR1 INTC.ICDABR1
    645 #define INTCICDABR2 INTC.ICDABR2
    646 #define INTCICDABR3 INTC.ICDABR3
    647 #define INTCICDABR4 INTC.ICDABR4
    648 #define INTCICDABR5 INTC.ICDABR5
    649 #define INTCICDABR6 INTC.ICDABR6
    650 #define INTCICDABR7 INTC.ICDABR7
    651 #define INTCICDABR8 INTC.ICDABR8
    652 #define INTCICDABR9 INTC.ICDABR9
    653 #define INTCICDABR10 INTC.ICDABR10
    654 #define INTCICDABR11 INTC.ICDABR11
    655 #define INTCICDABR12 INTC.ICDABR12
    656 #define INTCICDABR13 INTC.ICDABR13
    657 #define INTCICDABR14 INTC.ICDABR14
    658 #define INTCICDABR15 INTC.ICDABR15
    659 #define INTCICDABR16 INTC.ICDABR16
    660 #define INTCICDABR17 INTC.ICDABR17
    661 #define INTCICDABR18 INTC.ICDABR18
    662 #define INTCICDIPR0 INTC.ICDIPR0
    663 #define INTCICDIPR1 INTC.ICDIPR1
    664 #define INTCICDIPR2 INTC.ICDIPR2
    665 #define INTCICDIPR3 INTC.ICDIPR3
    666 #define INTCICDIPR4 INTC.ICDIPR4
    667 #define INTCICDIPR5 INTC.ICDIPR5
    668 #define INTCICDIPR6 INTC.ICDIPR6
    669 #define INTCICDIPR7 INTC.ICDIPR7
    670 #define INTCICDIPR8 INTC.ICDIPR8
    671 #define INTCICDIPR9 INTC.ICDIPR9
    672 #define INTCICDIPR10 INTC.ICDIPR10
    673 #define INTCICDIPR11 INTC.ICDIPR11
    674 #define INTCICDIPR12 INTC.ICDIPR12
    675 #define INTCICDIPR13 INTC.ICDIPR13
    676 #define INTCICDIPR14 INTC.ICDIPR14
    677 #define INTCICDIPR15 INTC.ICDIPR15
    678 #define INTCICDIPR16 INTC.ICDIPR16
    679 #define INTCICDIPR17 INTC.ICDIPR17
    680 #define INTCICDIPR18 INTC.ICDIPR18
    681 #define INTCICDIPR19 INTC.ICDIPR19
    682 #define INTCICDIPR20 INTC.ICDIPR20
    683 #define INTCICDIPR21 INTC.ICDIPR21
    684 #define INTCICDIPR22 INTC.ICDIPR22
    685 #define INTCICDIPR23 INTC.ICDIPR23
    686 #define INTCICDIPR24 INTC.ICDIPR24
    687 #define INTCICDIPR25 INTC.ICDIPR25
    688 #define INTCICDIPR26 INTC.ICDIPR26
    689 #define INTCICDIPR27 INTC.ICDIPR27
    690 #define INTCICDIPR28 INTC.ICDIPR28
    691 #define INTCICDIPR29 INTC.ICDIPR29
    692 #define INTCICDIPR30 INTC.ICDIPR30
    693 #define INTCICDIPR31 INTC.ICDIPR31
    694 #define INTCICDIPR32 INTC.ICDIPR32
    695 #define INTCICDIPR33 INTC.ICDIPR33
    696 #define INTCICDIPR34 INTC.ICDIPR34
    697 #define INTCICDIPR35 INTC.ICDIPR35
    698 #define INTCICDIPR36 INTC.ICDIPR36
    699 #define INTCICDIPR37 INTC.ICDIPR37
    700 #define INTCICDIPR38 INTC.ICDIPR38
    701 #define INTCICDIPR39 INTC.ICDIPR39
    702 #define INTCICDIPR40 INTC.ICDIPR40
    703 #define INTCICDIPR41 INTC.ICDIPR41
    704 #define INTCICDIPR42 INTC.ICDIPR42
    705 #define INTCICDIPR43 INTC.ICDIPR43
    706 #define INTCICDIPR44 INTC.ICDIPR44
    707 #define INTCICDIPR45 INTC.ICDIPR45
    708 #define INTCICDIPR46 INTC.ICDIPR46
    709 #define INTCICDIPR47 INTC.ICDIPR47
    710 #define INTCICDIPR48 INTC.ICDIPR48
    711 #define INTCICDIPR49 INTC.ICDIPR49
    712 #define INTCICDIPR50 INTC.ICDIPR50
    713 #define INTCICDIPR51 INTC.ICDIPR51
    714 #define INTCICDIPR52 INTC.ICDIPR52
    715 #define INTCICDIPR53 INTC.ICDIPR53
    716 #define INTCICDIPR54 INTC.ICDIPR54
    717 #define INTCICDIPR55 INTC.ICDIPR55
    718 #define INTCICDIPR56 INTC.ICDIPR56
    719 #define INTCICDIPR57 INTC.ICDIPR57
    720 #define INTCICDIPR58 INTC.ICDIPR58
    721 #define INTCICDIPR59 INTC.ICDIPR59
    722 #define INTCICDIPR60 INTC.ICDIPR60
    723 #define INTCICDIPR61 INTC.ICDIPR61
    724 #define INTCICDIPR62 INTC.ICDIPR62
    725 #define INTCICDIPR63 INTC.ICDIPR63
    726 #define INTCICDIPR64 INTC.ICDIPR64
    727 #define INTCICDIPR65 INTC.ICDIPR65
    728 #define INTCICDIPR66 INTC.ICDIPR66
    729 #define INTCICDIPR67 INTC.ICDIPR67
    730 #define INTCICDIPR68 INTC.ICDIPR68
    731 #define INTCICDIPR69 INTC.ICDIPR69
    732 #define INTCICDIPR70 INTC.ICDIPR70
    733 #define INTCICDIPR71 INTC.ICDIPR71
    734 #define INTCICDIPR72 INTC.ICDIPR72
    735 #define INTCICDIPR73 INTC.ICDIPR73
    736 #define INTCICDIPR74 INTC.ICDIPR74
    737 #define INTCICDIPR75 INTC.ICDIPR75
    738 #define INTCICDIPR76 INTC.ICDIPR76
    739 #define INTCICDIPR77 INTC.ICDIPR77
    740 #define INTCICDIPR78 INTC.ICDIPR78
    741 #define INTCICDIPR79 INTC.ICDIPR79
    742 #define INTCICDIPR80 INTC.ICDIPR80
    743 #define INTCICDIPR81 INTC.ICDIPR81
    744 #define INTCICDIPR82 INTC.ICDIPR82
    745 #define INTCICDIPR83 INTC.ICDIPR83
    746 #define INTCICDIPR84 INTC.ICDIPR84
    747 #define INTCICDIPR85 INTC.ICDIPR85
    748 #define INTCICDIPR86 INTC.ICDIPR86
    749 #define INTCICDIPR87 INTC.ICDIPR87
    750 #define INTCICDIPR88 INTC.ICDIPR88
    751 #define INTCICDIPR89 INTC.ICDIPR89
    752 #define INTCICDIPR90 INTC.ICDIPR90
    753 #define INTCICDIPR91 INTC.ICDIPR91
    754 #define INTCICDIPR92 INTC.ICDIPR92
    755 #define INTCICDIPR93 INTC.ICDIPR93
    756 #define INTCICDIPR94 INTC.ICDIPR94
    757 #define INTCICDIPR95 INTC.ICDIPR95
    758 #define INTCICDIPR96 INTC.ICDIPR96
    759 #define INTCICDIPR97 INTC.ICDIPR97
    760 #define INTCICDIPR98 INTC.ICDIPR98
    761 #define INTCICDIPR99 INTC.ICDIPR99
    762 #define INTCICDIPR100 INTC.ICDIPR100
    763 #define INTCICDIPR101 INTC.ICDIPR101
    764 #define INTCICDIPR102 INTC.ICDIPR102
    765 #define INTCICDIPR103 INTC.ICDIPR103
    766 #define INTCICDIPR104 INTC.ICDIPR104
    767 #define INTCICDIPR105 INTC.ICDIPR105
    768 #define INTCICDIPR106 INTC.ICDIPR106
    769 #define INTCICDIPR107 INTC.ICDIPR107
    770 #define INTCICDIPR108 INTC.ICDIPR108
    771 #define INTCICDIPR109 INTC.ICDIPR109
    772 #define INTCICDIPR110 INTC.ICDIPR110
    773 #define INTCICDIPR111 INTC.ICDIPR111
    774 #define INTCICDIPR112 INTC.ICDIPR112
    775 #define INTCICDIPR113 INTC.ICDIPR113
    776 #define INTCICDIPR114 INTC.ICDIPR114
    777 #define INTCICDIPR115 INTC.ICDIPR115
    778 #define INTCICDIPR116 INTC.ICDIPR116
    779 #define INTCICDIPR117 INTC.ICDIPR117
    780 #define INTCICDIPR118 INTC.ICDIPR118
    781 #define INTCICDIPR119 INTC.ICDIPR119
    782 #define INTCICDIPR120 INTC.ICDIPR120
    783 #define INTCICDIPR121 INTC.ICDIPR121
    784 #define INTCICDIPR122 INTC.ICDIPR122
    785 #define INTCICDIPR123 INTC.ICDIPR123
    786 #define INTCICDIPR124 INTC.ICDIPR124
    787 #define INTCICDIPR125 INTC.ICDIPR125
    788 #define INTCICDIPR126 INTC.ICDIPR126
    789 #define INTCICDIPR127 INTC.ICDIPR127
    790 #define INTCICDIPR128 INTC.ICDIPR128
    791 #define INTCICDIPR129 INTC.ICDIPR129
    792 #define INTCICDIPR130 INTC.ICDIPR130
    793 #define INTCICDIPR131 INTC.ICDIPR131
    794 #define INTCICDIPR132 INTC.ICDIPR132
    795 #define INTCICDIPR133 INTC.ICDIPR133
    796 #define INTCICDIPR134 INTC.ICDIPR134
    797 #define INTCICDIPR135 INTC.ICDIPR135
    798 #define INTCICDIPR136 INTC.ICDIPR136
    799 #define INTCICDIPR137 INTC.ICDIPR137
    800 #define INTCICDIPR138 INTC.ICDIPR138
    801 #define INTCICDIPR139 INTC.ICDIPR139
    802 #define INTCICDIPR140 INTC.ICDIPR140
    803 #define INTCICDIPR141 INTC.ICDIPR141
    804 #define INTCICDIPR142 INTC.ICDIPR142
    805 #define INTCICDIPR143 INTC.ICDIPR143
    806 #define INTCICDIPR144 INTC.ICDIPR144
    807 #define INTCICDIPR145 INTC.ICDIPR145
    808 #define INTCICDIPR146 INTC.ICDIPR146
    809 #define INTCICDIPTR0 INTC.ICDIPTR0
    810 #define INTCICDIPTR1 INTC.ICDIPTR1
    811 #define INTCICDIPTR2 INTC.ICDIPTR2
    812 #define INTCICDIPTR3 INTC.ICDIPTR3
    813 #define INTCICDIPTR4 INTC.ICDIPTR4
    814 #define INTCICDIPTR5 INTC.ICDIPTR5
    815 #define INTCICDIPTR6 INTC.ICDIPTR6
    816 #define INTCICDIPTR7 INTC.ICDIPTR7
    817 #define INTCICDIPTR8 INTC.ICDIPTR8
    818 #define INTCICDIPTR9 INTC.ICDIPTR9
    819 #define INTCICDIPTR10 INTC.ICDIPTR10
    820 #define INTCICDIPTR11 INTC.ICDIPTR11
    821 #define INTCICDIPTR12 INTC.ICDIPTR12
    822 #define INTCICDIPTR13 INTC.ICDIPTR13
    823 #define INTCICDIPTR14 INTC.ICDIPTR14
    824 #define INTCICDIPTR15 INTC.ICDIPTR15
    825 #define INTCICDIPTR16 INTC.ICDIPTR16
    826 #define INTCICDIPTR17 INTC.ICDIPTR17
    827 #define INTCICDIPTR18 INTC.ICDIPTR18
    828 #define INTCICDIPTR19 INTC.ICDIPTR19
    829 #define INTCICDIPTR20 INTC.ICDIPTR20
    830 #define INTCICDIPTR21 INTC.ICDIPTR21
    831 #define INTCICDIPTR22 INTC.ICDIPTR22
    832 #define INTCICDIPTR23 INTC.ICDIPTR23
    833 #define INTCICDIPTR24 INTC.ICDIPTR24
    834 #define INTCICDIPTR25 INTC.ICDIPTR25
    835 #define INTCICDIPTR26 INTC.ICDIPTR26
    836 #define INTCICDIPTR27 INTC.ICDIPTR27
    837 #define INTCICDIPTR28 INTC.ICDIPTR28
    838 #define INTCICDIPTR29 INTC.ICDIPTR29
    839 #define INTCICDIPTR30 INTC.ICDIPTR30
    840 #define INTCICDIPTR31 INTC.ICDIPTR31
    841 #define INTCICDIPTR32 INTC.ICDIPTR32
    842 #define INTCICDIPTR33 INTC.ICDIPTR33
    843 #define INTCICDIPTR34 INTC.ICDIPTR34
    844 #define INTCICDIPTR35 INTC.ICDIPTR35
    845 #define INTCICDIPTR36 INTC.ICDIPTR36
    846 #define INTCICDIPTR37 INTC.ICDIPTR37
    847 #define INTCICDIPTR38 INTC.ICDIPTR38
    848 #define INTCICDIPTR39 INTC.ICDIPTR39
    849 #define INTCICDIPTR40 INTC.ICDIPTR40
    850 #define INTCICDIPTR41 INTC.ICDIPTR41
    851 #define INTCICDIPTR42 INTC.ICDIPTR42
    852 #define INTCICDIPTR43 INTC.ICDIPTR43
    853 #define INTCICDIPTR44 INTC.ICDIPTR44
    854 #define INTCICDIPTR45 INTC.ICDIPTR45
    855 #define INTCICDIPTR46 INTC.ICDIPTR46
    856 #define INTCICDIPTR47 INTC.ICDIPTR47
    857 #define INTCICDIPTR48 INTC.ICDIPTR48
    858 #define INTCICDIPTR49 INTC.ICDIPTR49
    859 #define INTCICDIPTR50 INTC.ICDIPTR50
    860 #define INTCICDIPTR51 INTC.ICDIPTR51
    861 #define INTCICDIPTR52 INTC.ICDIPTR52
    862 #define INTCICDIPTR53 INTC.ICDIPTR53
    863 #define INTCICDIPTR54 INTC.ICDIPTR54
    864 #define INTCICDIPTR55 INTC.ICDIPTR55
    865 #define INTCICDIPTR56 INTC.ICDIPTR56
    866 #define INTCICDIPTR57 INTC.ICDIPTR57
    867 #define INTCICDIPTR58 INTC.ICDIPTR58
    868 #define INTCICDIPTR59 INTC.ICDIPTR59
    869 #define INTCICDIPTR60 INTC.ICDIPTR60
    870 #define INTCICDIPTR61 INTC.ICDIPTR61
    871 #define INTCICDIPTR62 INTC.ICDIPTR62
    872 #define INTCICDIPTR63 INTC.ICDIPTR63
    873 #define INTCICDIPTR64 INTC.ICDIPTR64
    874 #define INTCICDIPTR65 INTC.ICDIPTR65
    875 #define INTCICDIPTR66 INTC.ICDIPTR66
    876 #define INTCICDIPTR67 INTC.ICDIPTR67
    877 #define INTCICDIPTR68 INTC.ICDIPTR68
    878 #define INTCICDIPTR69 INTC.ICDIPTR69
    879 #define INTCICDIPTR70 INTC.ICDIPTR70
    880 #define INTCICDIPTR71 INTC.ICDIPTR71
    881 #define INTCICDIPTR72 INTC.ICDIPTR72
    882 #define INTCICDIPTR73 INTC.ICDIPTR73
    883 #define INTCICDIPTR74 INTC.ICDIPTR74
    884 #define INTCICDIPTR75 INTC.ICDIPTR75
    885 #define INTCICDIPTR76 INTC.ICDIPTR76
    886 #define INTCICDIPTR77 INTC.ICDIPTR77
    887 #define INTCICDIPTR78 INTC.ICDIPTR78
    888 #define INTCICDIPTR79 INTC.ICDIPTR79
    889 #define INTCICDIPTR80 INTC.ICDIPTR80
    890 #define INTCICDIPTR81 INTC.ICDIPTR81
    891 #define INTCICDIPTR82 INTC.ICDIPTR82
    892 #define INTCICDIPTR83 INTC.ICDIPTR83
    893 #define INTCICDIPTR84 INTC.ICDIPTR84
    894 #define INTCICDIPTR85 INTC.ICDIPTR85
    895 #define INTCICDIPTR86 INTC.ICDIPTR86
    896 #define INTCICDIPTR87 INTC.ICDIPTR87
    897 #define INTCICDIPTR88 INTC.ICDIPTR88
    898 #define INTCICDIPTR89 INTC.ICDIPTR89
    899 #define INTCICDIPTR90 INTC.ICDIPTR90
    900 #define INTCICDIPTR91 INTC.ICDIPTR91
    901 #define INTCICDIPTR92 INTC.ICDIPTR92
    902 #define INTCICDIPTR93 INTC.ICDIPTR93
    903 #define INTCICDIPTR94 INTC.ICDIPTR94
    904 #define INTCICDIPTR95 INTC.ICDIPTR95
    905 #define INTCICDIPTR96 INTC.ICDIPTR96
    906 #define INTCICDIPTR97 INTC.ICDIPTR97
    907 #define INTCICDIPTR98 INTC.ICDIPTR98
    908 #define INTCICDIPTR99 INTC.ICDIPTR99
    909 #define INTCICDIPTR100 INTC.ICDIPTR100
    910 #define INTCICDIPTR101 INTC.ICDIPTR101
    911 #define INTCICDIPTR102 INTC.ICDIPTR102
    912 #define INTCICDIPTR103 INTC.ICDIPTR103
    913 #define INTCICDIPTR104 INTC.ICDIPTR104
    914 #define INTCICDIPTR105 INTC.ICDIPTR105
    915 #define INTCICDIPTR106 INTC.ICDIPTR106
    916 #define INTCICDIPTR107 INTC.ICDIPTR107
    917 #define INTCICDIPTR108 INTC.ICDIPTR108
    918 #define INTCICDIPTR109 INTC.ICDIPTR109
    919 #define INTCICDIPTR110 INTC.ICDIPTR110
    920 #define INTCICDIPTR111 INTC.ICDIPTR111
    921 #define INTCICDIPTR112 INTC.ICDIPTR112
    922 #define INTCICDIPTR113 INTC.ICDIPTR113
    923 #define INTCICDIPTR114 INTC.ICDIPTR114
    924 #define INTCICDIPTR115 INTC.ICDIPTR115
    925 #define INTCICDIPTR116 INTC.ICDIPTR116
    926 #define INTCICDIPTR117 INTC.ICDIPTR117
    927 #define INTCICDIPTR118 INTC.ICDIPTR118
    928 #define INTCICDIPTR119 INTC.ICDIPTR119
    929 #define INTCICDIPTR120 INTC.ICDIPTR120
    930 #define INTCICDIPTR121 INTC.ICDIPTR121
    931 #define INTCICDIPTR122 INTC.ICDIPTR122
    932 #define INTCICDIPTR123 INTC.ICDIPTR123
    933 #define INTCICDIPTR124 INTC.ICDIPTR124
    934 #define INTCICDIPTR125 INTC.ICDIPTR125
    935 #define INTCICDIPTR126 INTC.ICDIPTR126
    936 #define INTCICDIPTR127 INTC.ICDIPTR127
    937 #define INTCICDIPTR128 INTC.ICDIPTR128
    938 #define INTCICDIPTR129 INTC.ICDIPTR129
    939 #define INTCICDIPTR130 INTC.ICDIPTR130
    940 #define INTCICDIPTR131 INTC.ICDIPTR131
    941 #define INTCICDIPTR132 INTC.ICDIPTR132
    942 #define INTCICDIPTR133 INTC.ICDIPTR133
    943 #define INTCICDIPTR134 INTC.ICDIPTR134
    944 #define INTCICDIPTR135 INTC.ICDIPTR135
    945 #define INTCICDIPTR136 INTC.ICDIPTR136
    946 #define INTCICDIPTR137 INTC.ICDIPTR137
    947 #define INTCICDIPTR138 INTC.ICDIPTR138
    948 #define INTCICDIPTR139 INTC.ICDIPTR139
    949 #define INTCICDIPTR140 INTC.ICDIPTR140
    950 #define INTCICDIPTR141 INTC.ICDIPTR141
    951 #define INTCICDIPTR142 INTC.ICDIPTR142
    952 #define INTCICDIPTR143 INTC.ICDIPTR143
    953 #define INTCICDIPTR144 INTC.ICDIPTR144
    954 #define INTCICDIPTR145 INTC.ICDIPTR145
    955 #define INTCICDIPTR146 INTC.ICDIPTR146
    956 #define INTCICDICFR0 INTC.ICDICFR0
    957 #define INTCICDICFR1 INTC.ICDICFR1
    958 #define INTCICDICFR2 INTC.ICDICFR2
    959 #define INTCICDICFR3 INTC.ICDICFR3
    960 #define INTCICDICFR4 INTC.ICDICFR4
    961 #define INTCICDICFR5 INTC.ICDICFR5
    962 #define INTCICDICFR6 INTC.ICDICFR6
    963 #define INTCICDICFR7 INTC.ICDICFR7
    964 #define INTCICDICFR8 INTC.ICDICFR8
    965 #define INTCICDICFR9 INTC.ICDICFR9
    966 #define INTCICDICFR10 INTC.ICDICFR10
    967 #define INTCICDICFR11 INTC.ICDICFR11
    968 #define INTCICDICFR12 INTC.ICDICFR12
    969 #define INTCICDICFR13 INTC.ICDICFR13
    970 #define INTCICDICFR14 INTC.ICDICFR14
    971 #define INTCICDICFR15 INTC.ICDICFR15
    972 #define INTCICDICFR16 INTC.ICDICFR16
    973 #define INTCICDICFR17 INTC.ICDICFR17
    974 #define INTCICDICFR18 INTC.ICDICFR18
    975 #define INTCICDICFR19 INTC.ICDICFR19
    976 #define INTCICDICFR20 INTC.ICDICFR20
    977 #define INTCICDICFR21 INTC.ICDICFR21
    978 #define INTCICDICFR22 INTC.ICDICFR22
    979 #define INTCICDICFR23 INTC.ICDICFR23
    980 #define INTCICDICFR24 INTC.ICDICFR24
    981 #define INTCICDICFR25 INTC.ICDICFR25
    982 #define INTCICDICFR26 INTC.ICDICFR26
    983 #define INTCICDICFR27 INTC.ICDICFR27
    984 #define INTCICDICFR28 INTC.ICDICFR28
    985 #define INTCICDICFR29 INTC.ICDICFR29
    986 #define INTCICDICFR30 INTC.ICDICFR30
    987 #define INTCICDICFR31 INTC.ICDICFR31
    988 #define INTCICDICFR32 INTC.ICDICFR32
    989 #define INTCICDICFR33 INTC.ICDICFR33
    990 #define INTCICDICFR34 INTC.ICDICFR34
    991 #define INTCICDICFR35 INTC.ICDICFR35
    992 #define INTCICDICFR36 INTC.ICDICFR36
    993 #define INTCPPI_STATUS INTC.PPI_STATUS
    994 #define INTCSPI_STATUS0 INTC.SPI_STATUS0
    995 #define INTCSPI_STATUS1 INTC.SPI_STATUS1
    996 #define INTCSPI_STATUS2 INTC.SPI_STATUS2
    997 #define INTCSPI_STATUS3 INTC.SPI_STATUS3
    998 #define INTCSPI_STATUS4 INTC.SPI_STATUS4
    999 #define INTCSPI_STATUS5 INTC.SPI_STATUS5
    1000 #define INTCSPI_STATUS6 INTC.SPI_STATUS6
    1001 #define INTCSPI_STATUS7 INTC.SPI_STATUS7
    1002 #define INTCSPI_STATUS8 INTC.SPI_STATUS8
    1003 #define INTCSPI_STATUS9 INTC.SPI_STATUS9
    1004 #define INTCSPI_STATUS10 INTC.SPI_STATUS10
    1005 #define INTCSPI_STATUS11 INTC.SPI_STATUS11
    1006 #define INTCSPI_STATUS12 INTC.SPI_STATUS12
    1007 #define INTCSPI_STATUS13 INTC.SPI_STATUS13
    1008 #define INTCSPI_STATUS14 INTC.SPI_STATUS14
    1009 #define INTCSPI_STATUS15 INTC.SPI_STATUS15
    1010 #define INTCSPI_STATUS16 INTC.SPI_STATUS16
    1011 #define INTCICDSGIR INTC.ICDSGIR
    1012 #define INTCICCICR INTC.ICCICR
    1013 #define INTCICCPMR INTC.ICCPMR
    1014 #define INTCICCBPR INTC.ICCBPR
    1015 #define INTCICCIAR INTC.ICCIAR
    1016 #define INTCICCEOIR INTC.ICCEOIR
    1017 #define INTCICCRPR INTC.ICCRPR
    1018 #define INTCICCHPIR INTC.ICCHPIR
    1019 #define INTCICCABPR INTC.ICCABPR
    1020 #define INTCICCIIDR INTC.ICCIIDR
    1021 #define INTCICR0 INTC.ICR0
    1022 #define INTCICR1 INTC.ICR1
    1023 #define INTCIRQRR INTC.IRQRR
     1047} r_io_intc_t;
     1048
     1049
    10241050/* <-SEC M1.10.1 */
     1051/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     1052/* <-QAC 0857 */
    10251053/* <-QAC 0639 */
    10261054#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/irda_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef IRDA_IODEFINE_H
    3030#define IRDA_IODEFINE_H
    31 
    32 struct st_irda
    33 {                                                          /* IRDA             */
    34     volatile uint8_t   IRCR;                                   /*  IRCR            */
    35 };
    36 
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
     34/* ->SEC M1.10.1 : Not magic number */
    3735
    3836#define IRDA    (*(struct st_irda    *)0xE8014000uL) /* IRDA */
    3937
    4038
    41 #define IRDAIRCR IRDA.IRCR
     39#define IRDAIRCR (IRDA.IRCR)
     40
     41
     42typedef struct st_irda
     43{
     44                                                           /* IRDA             */
     45    volatile uint8_t   IRCR;                                   /*  IRCR            */
     46} r_io_irda_t;
     47
     48
     49/* <-SEC M1.10.1 */
     50/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     51/* <-QAC 0857 */
     52/* <-QAC 0639 */
    4253#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/jcu_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef JCU_IODEFINE_H
    3030#define JCU_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3134/* ->SEC M1.10.1 : Not magic number */
    3235
    33 struct st_jcu
    34 {                                                          /* JCU              */
     36#define JCU     (*(struct st_jcu     *)0xE8017000uL) /* JCU */
     37
     38
     39/* Start of channel array defines of JCU */
     40
     41/* Channel array defines of JCU_JCQTBL0 */
     42/*(Sample) value = JCU_JCQTBL0[ channel ]->JCQTBL0; */
     43#define JCU_JCQTBL0_COUNT  (4)
     44#define JCU_JCQTBL0_ADDRESS_LIST \
     45{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     46    &JCU_FROM_JCQTBL0, &JCU_FROM_JCQTBL1, &JCU_FROM_JCQTBL2, &JCU_FROM_JCQTBL3 \
     47}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     48#define JCU_FROM_JCQTBL0 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL0) /* JCU_FROM_JCQTBL0 */
     49#define JCU_FROM_JCQTBL1 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL1) /* JCU_FROM_JCQTBL1 */
     50#define JCU_FROM_JCQTBL2 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL2) /* JCU_FROM_JCQTBL2 */
     51#define JCU_FROM_JCQTBL3 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL3) /* JCU_FROM_JCQTBL3 */
     52
     53/* End of channel array defines of JCU */
     54
     55
     56#define JCUJCMOD (JCU.JCMOD)
     57#define JCUJCCMD (JCU.JCCMD)
     58#define JCUJCQTN (JCU.JCQTN)
     59#define JCUJCHTN (JCU.JCHTN)
     60#define JCUJCDRIU (JCU.JCDRIU)
     61#define JCUJCDRID (JCU.JCDRID)
     62#define JCUJCVSZU (JCU.JCVSZU)
     63#define JCUJCVSZD (JCU.JCVSZD)
     64#define JCUJCHSZU (JCU.JCHSZU)
     65#define JCUJCHSZD (JCU.JCHSZD)
     66#define JCUJCDTCU (JCU.JCDTCU)
     67#define JCUJCDTCM (JCU.JCDTCM)
     68#define JCUJCDTCD (JCU.JCDTCD)
     69#define JCUJINTE0 (JCU.JINTE0)
     70#define JCUJINTS0 (JCU.JINTS0)
     71#define JCUJCDERR (JCU.JCDERR)
     72#define JCUJCRST (JCU.JCRST)
     73#define JCUJIFECNT (JCU.JIFECNT)
     74#define JCUJIFESA (JCU.JIFESA)
     75#define JCUJIFESOFST (JCU.JIFESOFST)
     76#define JCUJIFEDA (JCU.JIFEDA)
     77#define JCUJIFESLC (JCU.JIFESLC)
     78#define JCUJIFEDDC (JCU.JIFEDDC)
     79#define JCUJIFDCNT (JCU.JIFDCNT)
     80#define JCUJIFDSA (JCU.JIFDSA)
     81#define JCUJIFDDOFST (JCU.JIFDDOFST)
     82#define JCUJIFDDA (JCU.JIFDDA)
     83#define JCUJIFDSDC (JCU.JIFDSDC)
     84#define JCUJIFDDLC (JCU.JIFDDLC)
     85#define JCUJIFDADT (JCU.JIFDADT)
     86#define JCUJINTE1 (JCU.JINTE1)
     87#define JCUJINTS1 (JCU.JINTS1)
     88#define JCUJIFESVSZ (JCU.JIFESVSZ)
     89#define JCUJIFESHSZ (JCU.JIFESHSZ)
     90#define JCUJCQTBL0 (JCU.JCQTBL0)
     91#define JCUJCQTBL1 (JCU.JCQTBL1)
     92#define JCUJCQTBL2 (JCU.JCQTBL2)
     93#define JCUJCQTBL3 (JCU.JCQTBL3)
     94#define JCUJCHTBD0 (JCU.JCHTBD0)
     95#define JCUJCHTBA0 (JCU.JCHTBA0)
     96#define JCUJCHTBD1 (JCU.JCHTBD1)
     97#define JCUJCHTBA1 (JCU.JCHTBA1)
     98
     99
     100typedef struct st_jcu
     101{
     102                                                           /* JCU              */
    35103    volatile uint8_t   JCMOD;                                  /*  JCMOD           */
    36104    volatile uint8_t   JCCMD;                                  /*  JCCMD           */
    … …  
    71139    volatile uint32_t  JIFESHSZ;                               /*  JIFESHSZ        */
    72140    volatile uint8_t   dummy148[100];                          /*                  */
     141
    73142/* start of struct st_jcu_from_jcqtbl0 */
    74143    volatile uint8_t   JCQTBL0;                                /*  JCQTBL0         */
    75144    volatile uint8_t   dummy149[63];                           /*                  */
     145
    76146/* end of struct st_jcu_from_jcqtbl0 */
     147
    77148/* start of struct st_jcu_from_jcqtbl0 */
    78149    volatile uint8_t   JCQTBL1;                                /*  JCQTBL1         */
    79150    volatile uint8_t   dummy150[63];                           /*                  */
     151
    80152/* end of struct st_jcu_from_jcqtbl0 */
     153
    81154/* start of struct st_jcu_from_jcqtbl0 */
    82155    volatile uint8_t   JCQTBL2;                                /*  JCQTBL2         */
    83156    volatile uint8_t   dummy151[63];                           /*                  */
     157
    84158/* end of struct st_jcu_from_jcqtbl0 */
     159
    85160/* start of struct st_jcu_from_jcqtbl0 */
    86161    volatile uint8_t   JCQTBL3;                                /*  JCQTBL3         */
    87162    volatile uint8_t   dummy152[63];                           /*                  */
     163
    88164/* end of struct st_jcu_from_jcqtbl0 */
    89165    volatile uint8_t   JCHTBD0;                                /*  JCHTBD0         */
    … …  
    94170    volatile uint8_t   dummy155[31];                           /*                  */
    95171    volatile uint8_t   JCHTBA1;                                /*  JCHTBA1         */
    96 };
     172} r_io_jcu_t;
    97173
    98174
    99 struct st_jcu_from_jcqtbl0
     175typedef struct st_jcu_from_jcqtbl0
    100176{
     177 
    101178    volatile uint8_t   JCQTBL0;                                /*  JCQTBL0         */
    102179    volatile uint8_t   dummy1[63];                             /*                  */
    103 };
     180} r_io_jcu_from_jcqtbl0_t;
    104181
    105182
    106 #define JCU     (*(struct st_jcu     *)0xE8017000uL) /* JCU */
     183/* Channel array defines of JCU (2)*/
     184#ifdef  DECLARE_JCU_JCQTBL0_CHANNELS
     185volatile struct st_jcu_from_jcqtbl0*  JCU_JCQTBL0[ JCU_JCQTBL0_COUNT ] =
     186    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     187    JCU_JCQTBL0_ADDRESS_LIST;
     188    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     189#endif  /* DECLARE_JCU_JCQTBL0_CHANNELS */
     190/* End of channel array defines of JCU (2)*/
    107191
    108192
    109 /* Start of channnel array defines of JCU */
    110 
    111 /* Channnel array defines of JCU_JCQTBL0 */
    112 /*(Sample) value = JCU_JCQTBL0[ channel ]->JCQTBL0; */
    113 #define JCU_JCQTBL0_COUNT  4
    114 #define JCU_JCQTBL0_ADDRESS_LIST \
    115 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    116     &JCU_FROM_JCQTBL0, &JCU_FROM_JCQTBL1, &JCU_FROM_JCQTBL2, &JCU_FROM_JCQTBL3 \
    117 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    118 #define JCU_FROM_JCQTBL0 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL0) /* JCU_FROM_JCQTBL0 */
    119 #define JCU_FROM_JCQTBL1 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL1) /* JCU_FROM_JCQTBL1 */
    120 #define JCU_FROM_JCQTBL2 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL2) /* JCU_FROM_JCQTBL2 */
    121 #define JCU_FROM_JCQTBL3 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL3) /* JCU_FROM_JCQTBL3 */
    122 
    123 /* End of channnel array defines of JCU */
    124 
    125 
    126 #define JCUJCMOD JCU.JCMOD
    127 #define JCUJCCMD JCU.JCCMD
    128 #define JCUJCQTN JCU.JCQTN
    129 #define JCUJCHTN JCU.JCHTN
    130 #define JCUJCDRIU JCU.JCDRIU
    131 #define JCUJCDRID JCU.JCDRID
    132 #define JCUJCVSZU JCU.JCVSZU
    133 #define JCUJCVSZD JCU.JCVSZD
    134 #define JCUJCHSZU JCU.JCHSZU
    135 #define JCUJCHSZD JCU.JCHSZD
    136 #define JCUJCDTCU JCU.JCDTCU
    137 #define JCUJCDTCM JCU.JCDTCM
    138 #define JCUJCDTCD JCU.JCDTCD
    139 #define JCUJINTE0 JCU.JINTE0
    140 #define JCUJINTS0 JCU.JINTS0
    141 #define JCUJCDERR JCU.JCDERR
    142 #define JCUJCRST JCU.JCRST
    143 #define JCUJIFECNT JCU.JIFECNT
    144 #define JCUJIFESA JCU.JIFESA
    145 #define JCUJIFESOFST JCU.JIFESOFST
    146 #define JCUJIFEDA JCU.JIFEDA
    147 #define JCUJIFESLC JCU.JIFESLC
    148 #define JCUJIFEDDC JCU.JIFEDDC
    149 #define JCUJIFDCNT JCU.JIFDCNT
    150 #define JCUJIFDSA JCU.JIFDSA
    151 #define JCUJIFDDOFST JCU.JIFDDOFST
    152 #define JCUJIFDDA JCU.JIFDDA
    153 #define JCUJIFDSDC JCU.JIFDSDC
    154 #define JCUJIFDDLC JCU.JIFDDLC
    155 #define JCUJIFDADT JCU.JIFDADT
    156 #define JCUJINTE1 JCU.JINTE1
    157 #define JCUJINTS1 JCU.JINTS1
    158 #define JCUJIFESVSZ JCU.JIFESVSZ
    159 #define JCUJIFESHSZ JCU.JIFESHSZ
    160 #define JCUJCQTBL0 JCU.JCQTBL0
    161 #define JCUJCQTBL1 JCU.JCQTBL1
    162 #define JCUJCQTBL2 JCU.JCQTBL2
    163 #define JCUJCQTBL3 JCU.JCQTBL3
    164 #define JCUJCHTBD0 JCU.JCHTBD0
    165 #define JCUJCHTBA0 JCU.JCHTBA0
    166 #define JCUJCHTBD1 JCU.JCHTBD1
    167 #define JCUJCHTBA1 JCU.JCHTBA1
    168193/* <-SEC M1.10.1 */
     194/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     195/* <-QAC 0857 */
     196/* <-QAC 0639 */
    169197#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/l2c_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef L2C_IODEFINE_H
    3030#define L2C_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3134/* ->SEC M1.10.1 : Not magic number */
    3235
    33 struct st_l2c
    34 {                                                          /* L2C              */
     36#define L2C     (*(struct st_l2c     *)0x3FFFF000uL) /* L2C */
     37
     38
     39/* Start of channel array defines of L2C */
     40
     41/* Channel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */
     42/*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */
     43#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT  (8)
     44#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \
     45{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     46    &L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \
     47}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     48#define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */
     49#define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */
     50#define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */
     51#define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */
     52#define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */
     53#define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */
     54#define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */
     55#define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */
     56
     57/* End of channel array defines of L2C */
     58
     59
     60#define L2CREG0_CACHE_ID (L2C.REG0_CACHE_ID)
     61#define L2CREG0_CACHE_TYPE (L2C.REG0_CACHE_TYPE)
     62#define L2CREG1_CONTROL (L2C.REG1_CONTROL)
     63#define L2CREG1_AUX_CONTROL (L2C.REG1_AUX_CONTROL)
     64#define L2CREG1_TAG_RAM_CONTROL (L2C.REG1_TAG_RAM_CONTROL)
     65#define L2CREG1_DATA_RAM_CONTROL (L2C.REG1_DATA_RAM_CONTROL)
     66#define L2CREG2_EV_COUNTER_CTRL (L2C.REG2_EV_COUNTER_CTRL)
     67#define L2CREG2_EV_COUNTER1_CFG (L2C.REG2_EV_COUNTER1_CFG)
     68#define L2CREG2_EV_COUNTER0_CFG (L2C.REG2_EV_COUNTER0_CFG)
     69#define L2CREG2_EV_COUNTER1 (L2C.REG2_EV_COUNTER1)
     70#define L2CREG2_EV_COUNTER0 (L2C.REG2_EV_COUNTER0)
     71#define L2CREG2_INT_MASK (L2C.REG2_INT_MASK)
     72#define L2CREG2_INT_MASK_STATUS (L2C.REG2_INT_MASK_STATUS)
     73#define L2CREG2_INT_RAW_STATUS (L2C.REG2_INT_RAW_STATUS)
     74#define L2CREG2_INT_CLEAR (L2C.REG2_INT_CLEAR)
     75#define L2CREG7_CACHE_SYNC (L2C.REG7_CACHE_SYNC)
     76#define L2CREG7_INV_PA (L2C.REG7_INV_PA)
     77#define L2CREG7_INV_WAY (L2C.REG7_INV_WAY)
     78#define L2CREG7_CLEAN_PA (L2C.REG7_CLEAN_PA)
     79#define L2CREG7_CLEAN_INDEX (L2C.REG7_CLEAN_INDEX)
     80#define L2CREG7_CLEAN_WAY (L2C.REG7_CLEAN_WAY)
     81#define L2CREG7_CLEAN_INV_PA (L2C.REG7_CLEAN_INV_PA)
     82#define L2CREG7_CLEAN_INV_INDEX (L2C.REG7_CLEAN_INV_INDEX)
     83#define L2CREG7_CLEAN_INV_WAY (L2C.REG7_CLEAN_INV_WAY)
     84#define L2CREG9_D_LOCKDOWN0 (L2C.REG9_D_LOCKDOWN0)
     85#define L2CREG9_I_LOCKDOWN0 (L2C.REG9_I_LOCKDOWN0)
     86#define L2CREG9_D_LOCKDOWN1 (L2C.REG9_D_LOCKDOWN1)
     87#define L2CREG9_I_LOCKDOWN1 (L2C.REG9_I_LOCKDOWN1)
     88#define L2CREG9_D_LOCKDOWN2 (L2C.REG9_D_LOCKDOWN2)
     89#define L2CREG9_I_LOCKDOWN2 (L2C.REG9_I_LOCKDOWN2)
     90#define L2CREG9_D_LOCKDOWN3 (L2C.REG9_D_LOCKDOWN3)
     91#define L2CREG9_I_LOCKDOWN3 (L2C.REG9_I_LOCKDOWN3)
     92#define L2CREG9_D_LOCKDOWN4 (L2C.REG9_D_LOCKDOWN4)
     93#define L2CREG9_I_LOCKDOWN4 (L2C.REG9_I_LOCKDOWN4)
     94#define L2CREG9_D_LOCKDOWN5 (L2C.REG9_D_LOCKDOWN5)
     95#define L2CREG9_I_LOCKDOWN5 (L2C.REG9_I_LOCKDOWN5)
     96#define L2CREG9_D_LOCKDOWN6 (L2C.REG9_D_LOCKDOWN6)
     97#define L2CREG9_I_LOCKDOWN6 (L2C.REG9_I_LOCKDOWN6)
     98#define L2CREG9_D_LOCKDOWN7 (L2C.REG9_D_LOCKDOWN7)
     99#define L2CREG9_I_LOCKDOWN7 (L2C.REG9_I_LOCKDOWN7)
     100#define L2CREG9_LOCK_LINE_EN (L2C.REG9_LOCK_LINE_EN)
     101#define L2CREG9_UNLOCK_WAY (L2C.REG9_UNLOCK_WAY)
     102#define L2CREG12_ADDR_FILTERING_START (L2C.REG12_ADDR_FILTERING_START)
     103#define L2CREG12_ADDR_FILTERING_END (L2C.REG12_ADDR_FILTERING_END)
     104#define L2CREG15_DEBUG_CTRL (L2C.REG15_DEBUG_CTRL)
     105#define L2CREG15_PREFETCH_CTRL (L2C.REG15_PREFETCH_CTRL)
     106#define L2CREG15_POWER_CTRL (L2C.REG15_POWER_CTRL)
     107
     108
     109typedef struct st_l2c
     110{
     111                                                           /* L2C              */
    35112    volatile uint32_t  REG0_CACHE_ID;                          /*  REG0_CACHE_ID   */
    36113    volatile uint32_t  REG0_CACHE_TYPE;                        /*  REG0_CACHE_TYPE */
    … …  
    67144    volatile uint32_t  REG7_CLEAN_INV_WAY;                     /*  REG7_CLEAN_INV_WAY */
    68145    volatile uint8_t   dummy17[256];                           /*                  */
     146
    69147/* start of struct st_l2c_from_reg9_d_lockdown0 */
    70148    volatile uint32_t  REG9_D_LOCKDOWN0;                       /*  REG9_D_LOCKDOWN0 */
    71149    volatile uint32_t  REG9_I_LOCKDOWN0;                       /*  REG9_I_LOCKDOWN0 */
    72 /* end of struct st_l2c_from_reg9_d_lockdown0 */
     150
     151/* end of struct st_l2c_from_reg9_d_lockdown0 */
     152
    73153/* start of struct st_l2c_from_reg9_d_lockdown0 */
    74154    volatile uint32_t  REG9_D_LOCKDOWN1;                       /*  REG9_D_LOCKDOWN1 */
    75155    volatile uint32_t  REG9_I_LOCKDOWN1;                       /*  REG9_I_LOCKDOWN1 */
    76 /* end of struct st_l2c_from_reg9_d_lockdown0 */
     156
     157/* end of struct st_l2c_from_reg9_d_lockdown0 */
     158
    77159/* start of struct st_l2c_from_reg9_d_lockdown0 */
    78160    volatile uint32_t  REG9_D_LOCKDOWN2;                       /*  REG9_D_LOCKDOWN2 */
    79161    volatile uint32_t  REG9_I_LOCKDOWN2;                       /*  REG9_I_LOCKDOWN2 */
    80 /* end of struct st_l2c_from_reg9_d_lockdown0 */
     162
     163/* end of struct st_l2c_from_reg9_d_lockdown0 */
     164
    81165/* start of struct st_l2c_from_reg9_d_lockdown0 */
    82166    volatile uint32_t  REG9_D_LOCKDOWN3;                       /*  REG9_D_LOCKDOWN3 */
    83167    volatile uint32_t  REG9_I_LOCKDOWN3;                       /*  REG9_I_LOCKDOWN3 */
    84 /* end of struct st_l2c_from_reg9_d_lockdown0 */
     168
     169/* end of struct st_l2c_from_reg9_d_lockdown0 */
     170
    85171/* start of struct st_l2c_from_reg9_d_lockdown0 */
    86172    volatile uint32_t  REG9_D_LOCKDOWN4;                       /*  REG9_D_LOCKDOWN4 */
    87173    volatile uint32_t  REG9_I_LOCKDOWN4;                       /*  REG9_I_LOCKDOWN4 */
    88 /* end of struct st_l2c_from_reg9_d_lockdown0 */
     174
     175/* end of struct st_l2c_from_reg9_d_lockdown0 */
     176
    89177/* start of struct st_l2c_from_reg9_d_lockdown0 */
    90178    volatile uint32_t  REG9_D_LOCKDOWN5;                       /*  REG9_D_LOCKDOWN5 */
    91179    volatile uint32_t  REG9_I_LOCKDOWN5;                       /*  REG9_I_LOCKDOWN5 */
    92 /* end of struct st_l2c_from_reg9_d_lockdown0 */
     180
     181/* end of struct st_l2c_from_reg9_d_lockdown0 */
     182
    93183/* start of struct st_l2c_from_reg9_d_lockdown0 */
    94184    volatile uint32_t  REG9_D_LOCKDOWN6;                       /*  REG9_D_LOCKDOWN6 */
    95185    volatile uint32_t  REG9_I_LOCKDOWN6;                       /*  REG9_I_LOCKDOWN6 */
    96 /* end of struct st_l2c_from_reg9_d_lockdown0 */
     186
     187/* end of struct st_l2c_from_reg9_d_lockdown0 */
     188
    97189/* start of struct st_l2c_from_reg9_d_lockdown0 */
    98190    volatile uint32_t  REG9_D_LOCKDOWN7;                       /*  REG9_D_LOCKDOWN7 */
    99191    volatile uint32_t  REG9_I_LOCKDOWN7;                       /*  REG9_I_LOCKDOWN7 */
     192
    100193/* end of struct st_l2c_from_reg9_d_lockdown0 */
    101194    volatile uint8_t   dummy18[16];                            /*                  */
    … …  
    111204    volatile uint8_t   dummy22[28];                            /*                  */
    112205    volatile uint32_t  REG15_POWER_CTRL;                       /*  REG15_POWER_CTRL */
    113 };
    114 
    115 
    116 struct st_l2c_from_reg9_d_lockdown0
     206} r_io_l2c_t;
     207
     208
     209typedef struct st_l2c_from_reg9_d_lockdown0
    117210{
     211 
    118212    volatile uint32_t  REG9_D_LOCKDOWN0;                       /*  REG9_D_LOCKDOWN0 */
    119213    volatile uint32_t  REG9_I_LOCKDOWN0;                       /*  REG9_I_LOCKDOWN0 */
    120 };
    121 
    122 
    123 #define L2C     (*(struct st_l2c     *)0x3FFFF000uL) /* L2C */
    124 
    125 
    126 /* Start of channnel array defines of L2C */
    127 
    128 /* Channnel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */
    129 /*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */
    130 #define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT  8
    131 #define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \
    132 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    133     &L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \
    134 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    135 #define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */
    136 #define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */
    137 #define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */
    138 #define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */
    139 #define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */
    140 #define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */
    141 #define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */
    142 #define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */
    143 
    144 /* End of channnel array defines of L2C */
    145 
    146 
    147 #define L2CREG0_CACHE_ID L2C.REG0_CACHE_ID
    148 #define L2CREG0_CACHE_TYPE L2C.REG0_CACHE_TYPE
    149 #define L2CREG1_CONTROL L2C.REG1_CONTROL
    150 #define L2CREG1_AUX_CONTROL L2C.REG1_AUX_CONTROL
    151 #define L2CREG1_TAG_RAM_CONTROL L2C.REG1_TAG_RAM_CONTROL
    152 #define L2CREG1_DATA_RAM_CONTROL L2C.REG1_DATA_RAM_CONTROL
    153 #define L2CREG2_EV_COUNTER_CTRL L2C.REG2_EV_COUNTER_CTRL
    154 #define L2CREG2_EV_COUNTER1_CFG L2C.REG2_EV_COUNTER1_CFG
    155 #define L2CREG2_EV_COUNTER0_CFG L2C.REG2_EV_COUNTER0_CFG
    156 #define L2CREG2_EV_COUNTER1 L2C.REG2_EV_COUNTER1
    157 #define L2CREG2_EV_COUNTER0 L2C.REG2_EV_COUNTER0
    158 #define L2CREG2_INT_MASK L2C.REG2_INT_MASK
    159 #define L2CREG2_INT_MASK_STATUS L2C.REG2_INT_MASK_STATUS
    160 #define L2CREG2_INT_RAW_STATUS L2C.REG2_INT_RAW_STATUS
    161 #define L2CREG2_INT_CLEAR L2C.REG2_INT_CLEAR
    162 #define L2CREG7_CACHE_SYNC L2C.REG7_CACHE_SYNC
    163 #define L2CREG7_INV_PA L2C.REG7_INV_PA
    164 #define L2CREG7_INV_WAY L2C.REG7_INV_WAY
    165 #define L2CREG7_CLEAN_PA L2C.REG7_CLEAN_PA
    166 #define L2CREG7_CLEAN_INDEX L2C.REG7_CLEAN_INDEX
    167 #define L2CREG7_CLEAN_WAY L2C.REG7_CLEAN_WAY
    168 #define L2CREG7_CLEAN_INV_PA L2C.REG7_CLEAN_INV_PA
    169 #define L2CREG7_CLEAN_INV_INDEX L2C.REG7_CLEAN_INV_INDEX
    170 #define L2CREG7_CLEAN_INV_WAY L2C.REG7_CLEAN_INV_WAY
    171 #define L2CREG9_D_LOCKDOWN0 L2C.REG9_D_LOCKDOWN0
    172 #define L2CREG9_I_LOCKDOWN0 L2C.REG9_I_LOCKDOWN0
    173 #define L2CREG9_D_LOCKDOWN1 L2C.REG9_D_LOCKDOWN1
    174 #define L2CREG9_I_LOCKDOWN1 L2C.REG9_I_LOCKDOWN1
    175 #define L2CREG9_D_LOCKDOWN2 L2C.REG9_D_LOCKDOWN2
    176 #define L2CREG9_I_LOCKDOWN2 L2C.REG9_I_LOCKDOWN2
    177 #define L2CREG9_D_LOCKDOWN3 L2C.REG9_D_LOCKDOWN3
    178 #define L2CREG9_I_LOCKDOWN3 L2C.REG9_I_LOCKDOWN3
    179 #define L2CREG9_D_LOCKDOWN4 L2C.REG9_D_LOCKDOWN4
    180 #define L2CREG9_I_LOCKDOWN4 L2C.REG9_I_LOCKDOWN4
    181 #define L2CREG9_D_LOCKDOWN5 L2C.REG9_D_LOCKDOWN5
    182 #define L2CREG9_I_LOCKDOWN5 L2C.REG9_I_LOCKDOWN5
    183 #define L2CREG9_D_LOCKDOWN6 L2C.REG9_D_LOCKDOWN6
    184 #define L2CREG9_I_LOCKDOWN6 L2C.REG9_I_LOCKDOWN6
    185 #define L2CREG9_D_LOCKDOWN7 L2C.REG9_D_LOCKDOWN7
    186 #define L2CREG9_I_LOCKDOWN7 L2C.REG9_I_LOCKDOWN7
    187 #define L2CREG9_LOCK_LINE_EN L2C.REG9_LOCK_LINE_EN
    188 #define L2CREG9_UNLOCK_WAY L2C.REG9_UNLOCK_WAY
    189 #define L2CREG12_ADDR_FILTERING_START L2C.REG12_ADDR_FILTERING_START
    190 #define L2CREG12_ADDR_FILTERING_END L2C.REG12_ADDR_FILTERING_END
    191 #define L2CREG15_DEBUG_CTRL L2C.REG15_DEBUG_CTRL
    192 #define L2CREG15_PREFETCH_CTRL L2C.REG15_PREFETCH_CTRL
    193 #define L2CREG15_POWER_CTRL L2C.REG15_POWER_CTRL
     214} r_io_l2c_from_reg9_d_lockdown_t /* Short of r_io_l2c_from_reg9_d_lockdown0_t */;
     215
     216
     217/* Channel array defines of L2C (2)*/
     218#ifdef  DECLARE_L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_CHANNELS
     219volatile struct st_l2c_from_reg9_d_lockdown0*  L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT ] =
     220    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     221    L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST;
     222    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     223#endif  /* DECLARE_L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_CHANNELS */
     224/* End of channel array defines of L2C (2)*/
     225
     226
    194227/* <-SEC M1.10.1 */
     228/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     229/* <-QAC 0857 */
     230/* <-QAC 0639 */
    195231#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/lin_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef LIN_IODEFINE_H
    3030#define LIN_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
    3133/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3234/* ->SEC M1.10.1 : Not magic number */
    3335
    34 struct st_lin
    35 {                                                          /* LIN              */
     36#define LIN0    (*(struct st_lin     *)0xFCFE9000uL) /* LIN0 */
     37#define LIN1    (*(struct st_lin     *)0xFCFE9800uL) /* LIN1 */
     38
     39
     40/* Start of channel array defines of LIN */
     41
     42/* Channel array defines of LIN */
     43/*(Sample) value = LIN[ channel ]->RLN3nLWBR; */
     44#define LIN_COUNT  (2)
     45#define LIN_ADDRESS_LIST \
     46{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     47    &LIN0, &LIN1 \
     48}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     49
     50/* End of channel array defines of LIN */
     51
     52
     53#define LIN0RLN30LWBR (LIN0.RLN3nLWBR)
     54#define LIN0RLN30LBRP0 (LIN0.RLN3nLBRP0)
     55#define LIN0RLN30LBRP1 (LIN0.RLN3nLBRP1)
     56#define LIN0RLN30LSTC (LIN0.RLN3nLSTC)
     57#define LIN0RLN30LMD (LIN0.RLN3nLMD)
     58#define LIN0RLN30LBFC (LIN0.RLN3nLBFC)
     59#define LIN0RLN30LSC (LIN0.RLN3nLSC)
     60#define LIN0RLN30LWUP (LIN0.RLN3nLWUP)
     61#define LIN0RLN30LIE (LIN0.RLN3nLIE)
     62#define LIN0RLN30LEDE (LIN0.RLN3nLEDE)
     63#define LIN0RLN30LCUC (LIN0.RLN3nLCUC)
     64#define LIN0RLN30LTRC (LIN0.RLN3nLTRC)
     65#define LIN0RLN30LMST (LIN0.RLN3nLMST)
     66#define LIN0RLN30LST (LIN0.RLN3nLST)
     67#define LIN0RLN30LEST (LIN0.RLN3nLEST)
     68#define LIN0RLN30LDFC (LIN0.RLN3nLDFC)
     69#define LIN0RLN30LIDB (LIN0.RLN3nLIDB)
     70#define LIN0RLN30LCBR (LIN0.RLN3nLCBR)
     71#define LIN0RLN30LDBR1 (LIN0.RLN3nLDBR1)
     72#define LIN0RLN30LDBR2 (LIN0.RLN3nLDBR2)
     73#define LIN0RLN30LDBR3 (LIN0.RLN3nLDBR3)
     74#define LIN0RLN30LDBR4 (LIN0.RLN3nLDBR4)
     75#define LIN0RLN30LDBR5 (LIN0.RLN3nLDBR5)
     76#define LIN0RLN30LDBR6 (LIN0.RLN3nLDBR6)
     77#define LIN0RLN30LDBR7 (LIN0.RLN3nLDBR7)
     78#define LIN0RLN30LDBR8 (LIN0.RLN3nLDBR8)
     79#define LIN1RLN31LWBR (LIN1.RLN3nLWBR)
     80#define LIN1RLN31LBRP0 (LIN1.RLN3nLBRP0)
     81#define LIN1RLN31LBRP1 (LIN1.RLN3nLBRP1)
     82#define LIN1RLN31LSTC (LIN1.RLN3nLSTC)
     83#define LIN1RLN31LMD (LIN1.RLN3nLMD)
     84#define LIN1RLN31LBFC (LIN1.RLN3nLBFC)
     85#define LIN1RLN31LSC (LIN1.RLN3nLSC)
     86#define LIN1RLN31LWUP (LIN1.RLN3nLWUP)
     87#define LIN1RLN31LIE (LIN1.RLN3nLIE)
     88#define LIN1RLN31LEDE (LIN1.RLN3nLEDE)
     89#define LIN1RLN31LCUC (LIN1.RLN3nLCUC)
     90#define LIN1RLN31LTRC (LIN1.RLN3nLTRC)
     91#define LIN1RLN31LMST (LIN1.RLN3nLMST)
     92#define LIN1RLN31LST (LIN1.RLN3nLST)
     93#define LIN1RLN31LEST (LIN1.RLN3nLEST)
     94#define LIN1RLN31LDFC (LIN1.RLN3nLDFC)
     95#define LIN1RLN31LIDB (LIN1.RLN3nLIDB)
     96#define LIN1RLN31LCBR (LIN1.RLN3nLCBR)
     97#define LIN1RLN31LDBR1 (LIN1.RLN3nLDBR1)
     98#define LIN1RLN31LDBR2 (LIN1.RLN3nLDBR2)
     99#define LIN1RLN31LDBR3 (LIN1.RLN3nLDBR3)
     100#define LIN1RLN31LDBR4 (LIN1.RLN3nLDBR4)
     101#define LIN1RLN31LDBR5 (LIN1.RLN3nLDBR5)
     102#define LIN1RLN31LDBR6 (LIN1.RLN3nLDBR6)
     103#define LIN1RLN31LDBR7 (LIN1.RLN3nLDBR7)
     104#define LIN1RLN31LDBR8 (LIN1.RLN3nLDBR8)
     105
     106#define LIN_LDBn_COUNT (8)
     107
     108
     109typedef struct st_lin
     110{
     111                                                           /* LIN              */
    36112    volatile uint8_t   dummy1[1];                              /*                  */
    37113    volatile uint8_t   RLN3nLWBR;                              /*  RLN3nLWBR       */
    38     union iodefine_reg16_8_t  RLN3nLBRP01;                     /*  RLN3nLBRP01 */
    39    
     114    volatile uint8_t   RLN3nLBRP0;                             /*  RLN3nLBRP0      */
     115    volatile uint8_t   RLN3nLBRP1;                             /*  RLN3nLBRP1      */
    40116    volatile uint8_t   RLN3nLSTC;                              /*  RLN3nLSTC       */
    41117    volatile uint8_t   dummy2[3];                              /*                  */
    … …  
    55131    volatile uint8_t   RLN3nLIDB;                              /*  RLN3nLIDB       */
    56132    volatile uint8_t   RLN3nLCBR;                              /*  RLN3nLCBR       */
    57     volatile uint8_t   RLN3nLUDB0;                             /*  RLN3nLUDB0      */
    58 #define LIN_LDBn_COUNT 8
     133    volatile uint8_t   dummy4[1];                              /*                  */
     134
     135/* #define LIN_LDBn_COUNT (8) */
    59136    volatile uint8_t   RLN3nLDBR1;                             /*  RLN3nLDBR1      */
    60137    volatile uint8_t   RLN3nLDBR2;                             /*  RLN3nLDBR2      */
    … …  
    65142    volatile uint8_t   RLN3nLDBR7;                             /*  RLN3nLDBR7      */
    66143    volatile uint8_t   RLN3nLDBR8;                             /*  RLN3nLDBR8      */
    67     volatile uint8_t   RLN3nLUOER;                             /*  RLN3nLUOER      */
    68     volatile uint8_t   RLN3nLUOR1;                             /*  RLN3nLUOR1      */
    69     volatile uint8_t   dummy4[2];                              /*                  */
    70     union iodefine_reg16_8_t  RLN3nLUTDR;                      /*  RLN3nLUTDR  */
    71     union iodefine_reg16_8_t  RLN3nLURDR;                      /*  RLN3nLURDR  */
    72     union iodefine_reg16_8_t  RLN3nLUWTDR;                     /*  RLN3nLUWTDR */
    73    
    74 };
     144} r_io_lin_t;
    75145
    76146
    77 #define LIN0    (*(struct st_lin     *)0xFCFE9000uL) /* LIN0 */
    78 #define LIN1    (*(struct st_lin     *)0xFCFE9800uL) /* LIN1 */
     147/* Channel array defines of LIN (2)*/
     148#ifdef  DECLARE_LIN_CHANNELS
     149volatile struct st_lin*  LIN[ LIN_COUNT ] =
     150    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     151    LIN_ADDRESS_LIST;
     152    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     153#endif  /* DECLARE_LIN_CHANNELS */
     154/* End of channel array defines of LIN (2)*/
    79155
    80156
    81 /* Start of channnel array defines of LIN */
    82 
    83 /* Channnel array defines of LIN */
    84 /*(Sample) value = LIN[ channel ]->RLN3nLWBR; */
    85 #define LIN_COUNT  2
    86 #define LIN_ADDRESS_LIST \
    87 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    88     &LIN0, &LIN1 \
    89 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    90 
    91 /* End of channnel array defines of LIN */
    92 
    93 
    94 #define LIN0RLN30LWBR LIN0.RLN3nLWBR
    95 #define LIN0RLN30LBRP01 LIN0.RLN3nLBRP01.UINT16
    96 #define LIN0RLN30LBRP0 LIN0.RLN3nLBRP01.UINT8[L]
    97 #define LIN0RLN30LBRP1 LIN0.RLN3nLBRP01.UINT8[H]
    98 #define LIN0RLN30LSTC LIN0.RLN3nLSTC
    99 #define LIN0RLN30LMD LIN0.RLN3nLMD
    100 #define LIN0RLN30LBFC LIN0.RLN3nLBFC
    101 #define LIN0RLN30LSC LIN0.RLN3nLSC
    102 #define LIN0RLN30LWUP LIN0.RLN3nLWUP
    103 #define LIN0RLN30LIE LIN0.RLN3nLIE
    104 #define LIN0RLN30LEDE LIN0.RLN3nLEDE
    105 #define LIN0RLN30LCUC LIN0.RLN3nLCUC
    106 #define LIN0RLN30LTRC LIN0.RLN3nLTRC
    107 #define LIN0RLN30LMST LIN0.RLN3nLMST
    108 #define LIN0RLN30LST LIN0.RLN3nLST
    109 #define LIN0RLN30LEST LIN0.RLN3nLEST
    110 #define LIN0RLN30LDFC LIN0.RLN3nLDFC
    111 #define LIN0RLN30LIDB LIN0.RLN3nLIDB
    112 #define LIN0RLN30LCBR LIN0.RLN3nLCBR
    113 #define LIN0RLN30LUDB0 LIN0.RLN3nLUDB0
    114 #define LIN0RLN30LDBR1 LIN0.RLN3nLDBR1
    115 #define LIN0RLN30LDBR2 LIN0.RLN3nLDBR2
    116 #define LIN0RLN30LDBR3 LIN0.RLN3nLDBR3
    117 #define LIN0RLN30LDBR4 LIN0.RLN3nLDBR4
    118 #define LIN0RLN30LDBR5 LIN0.RLN3nLDBR5
    119 #define LIN0RLN30LDBR6 LIN0.RLN3nLDBR6
    120 #define LIN0RLN30LDBR7 LIN0.RLN3nLDBR7
    121 #define LIN0RLN30LDBR8 LIN0.RLN3nLDBR8
    122 #define LIN0RLN30LUOER LIN0.RLN3nLUOER
    123 #define LIN0RLN30LUOR1 LIN0.RLN3nLUOR1
    124 #define LIN0RLN30LUTDR LIN0.RLN3nLUTDR.UINT16
    125 #define LIN0RLN30LUTDRL LIN0.RLN3nLUTDR.UINT8[L]
    126 #define LIN0RLN30LUTDRH LIN0.RLN3nLUTDR.UINT8[H]
    127 #define LIN0RLN30LURDR LIN0.RLN3nLURDR.UINT16
    128 #define LIN0RLN30LURDRL LIN0.RLN3nLURDR.UINT8[L]
    129 #define LIN0RLN30LURDRH LIN0.RLN3nLURDR.UINT8[H]
    130 #define LIN0RLN30LUWTDR LIN0.RLN3nLUWTDR.UINT16
    131 #define LIN0RLN30LUWTDRL LIN0.RLN3nLUWTDR.UINT8[L]
    132 #define LIN0RLN30LUWTDRH LIN0.RLN3nLUWTDR.UINT8[H]
    133 #define LIN1RLN31LWBR LIN1.RLN3nLWBR
    134 #define LIN1RLN31LBRP01 LIN1.RLN3nLBRP01.UINT16
    135 #define LIN1RLN31LBRP0 LIN1.RLN3nLBRP01.UINT8[L]
    136 #define LIN1RLN31LBRP1 LIN1.RLN3nLBRP01.UINT8[H]
    137 #define LIN1RLN31LSTC LIN1.RLN3nLSTC
    138 #define LIN1RLN31LMD LIN1.RLN3nLMD
    139 #define LIN1RLN31LBFC LIN1.RLN3nLBFC
    140 #define LIN1RLN31LSC LIN1.RLN3nLSC
    141 #define LIN1RLN31LWUP LIN1.RLN3nLWUP
    142 #define LIN1RLN31LIE LIN1.RLN3nLIE
    143 #define LIN1RLN31LEDE LIN1.RLN3nLEDE
    144 #define LIN1RLN31LCUC LIN1.RLN3nLCUC
    145 #define LIN1RLN31LTRC LIN1.RLN3nLTRC
    146 #define LIN1RLN31LMST LIN1.RLN3nLMST
    147 #define LIN1RLN31LST LIN1.RLN3nLST
    148 #define LIN1RLN31LEST LIN1.RLN3nLEST
    149 #define LIN1RLN31LDFC LIN1.RLN3nLDFC
    150 #define LIN1RLN31LIDB LIN1.RLN3nLIDB
    151 #define LIN1RLN31LCBR LIN1.RLN3nLCBR
    152 #define LIN1RLN31LUDB0 LIN1.RLN3nLUDB0
    153 #define LIN1RLN31LDBR1 LIN1.RLN3nLDBR1
    154 #define LIN1RLN31LDBR2 LIN1.RLN3nLDBR2
    155 #define LIN1RLN31LDBR3 LIN1.RLN3nLDBR3
    156 #define LIN1RLN31LDBR4 LIN1.RLN3nLDBR4
    157 #define LIN1RLN31LDBR5 LIN1.RLN3nLDBR5
    158 #define LIN1RLN31LDBR6 LIN1.RLN3nLDBR6
    159 #define LIN1RLN31LDBR7 LIN1.RLN3nLDBR7
    160 #define LIN1RLN31LDBR8 LIN1.RLN3nLDBR8
    161 #define LIN1RLN31LUOER LIN1.RLN3nLUOER
    162 #define LIN1RLN31LUOR1 LIN1.RLN3nLUOR1
    163 #define LIN1RLN31LUTDR LIN1.RLN3nLUTDR.UINT16
    164 #define LIN1RLN31LUTDRL LIN1.RLN3nLUTDR.UINT8[L]
    165 #define LIN1RLN31LUTDRH LIN1.RLN3nLUTDR.UINT8[H]
    166 #define LIN1RLN31LURDR LIN1.RLN3nLURDR.UINT16
    167 #define LIN1RLN31LURDRL LIN1.RLN3nLURDR.UINT8[L]
    168 #define LIN1RLN31LURDRH LIN1.RLN3nLURDR.UINT8[H]
    169 #define LIN1RLN31LUWTDR LIN1.RLN3nLUWTDR.UINT16
    170 #define LIN1RLN31LUWTDRL LIN1.RLN3nLUWTDR.UINT8[L]
    171 #define LIN1RLN31LUWTDRH LIN1.RLN3nLUWTDR.UINT8[H]
    172157/* <-SEC M1.10.1 */
    173158/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     159/* <-QAC 0857 */
     160/* <-QAC 0639 */
    174161#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/lvds_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.01a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef LVDS_IODEFINE_H
    3030#define LVDS_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3134/* ->SEC M1.10.1 : Not magic number */
    3235
    33 struct st_lvds
    34 {                                                          /* LVDS             */
     36#define LVDS    (*(struct st_lvds    *)0xFCFF7A30uL) /* LVDS */
     37
     38
     39#define LVDSLVDS_UPDATE (LVDS.LVDS_UPDATE)
     40#define LVDSLVDSFCL (LVDS.LVDSFCL)
     41#define LVDSLCLKSELR (LVDS.LCLKSELR)
     42#define LVDSLPLLSETR (LVDS.LPLLSETR)
     43#define LVDSLPHYACC (LVDS.LPHYACC)
     44
     45
     46typedef struct st_lvds
     47{
     48                                                           /* LVDS             */
    3549    volatile uint32_t  LVDS_UPDATE;                            /*  LVDS_UPDATE     */
    3650    volatile uint32_t  LVDSFCL;                                /*  LVDSFCL         */
    … …  
    4054    volatile uint8_t   dummy609[4];                            /*                  */
    4155    volatile uint32_t  LPHYACC;                                /*  LPHYACC         */
    42 };
     56} r_io_lvds_t;
    4357
    4458
    45 #define LVDS    (*(struct st_lvds    *)0xFCFF7A30uL) /* LVDS */
    46 
    47 
    48 #define LVDSLVDS_UPDATE LVDS.LVDS_UPDATE
    49 #define LVDSLVDSFCL LVDS.LVDSFCL
    50 #define LVDSLCLKSELR LVDS.LCLKSELR
    51 #define LVDSLPLLSETR LVDS.LPLLSETR
    52 #define LVDSLPHYACC LVDS.LPHYACC
    5359/* <-SEC M1.10.1 */
     60/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     61/* <-QAC 0857 */
     62/* <-QAC 0639 */
    5463#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/mlb_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef MLB_IODEFINE_H
    … …  
    3131/* ->QAC 0639 : Over 127 members (C90) */
    3232/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3334/* ->SEC M1.10.1 : Not magic number */
    3435
    35 struct st_mlb
    36 {                                                          /* MLB              */
    37     volatile uint32_t  DCCR;                                   /*  DCCR            */
    38     volatile uint32_t  SSCR;                                   /*  SSCR            */
    39     volatile uint32_t  SDCR;                                   /*  SDCR            */
    40     volatile uint32_t  SMCR;                                   /*  SMCR            */
    41     volatile uint8_t   dummy156[12];                           /*                  */
    42     volatile uint32_t  VCCR;                                   /*  VCCR            */
    43     volatile uint32_t  SBCR;                                   /*  SBCR            */
    44     volatile uint32_t  ABCR;                                   /*  ABCR            */
    45     volatile uint32_t  CBCR;                                   /*  CBCR            */
    46     volatile uint32_t  IBCR;                                   /*  IBCR            */
    47     volatile uint32_t  CICR;                                   /*  CICR            */
    48     volatile uint8_t   dummy157[12];                           /*                  */
    49 /* start of struct st_mlb_from_cecr0 */
    50     volatile uint32_t  CECR0;                                  /*  CECR0           */
    51     volatile uint32_t  CSCR0;                                  /*  CSCR0           */
    52     volatile uint32_t  CCBCR0;                                 /*  CCBCR0          */
    53     volatile uint32_t  CNBCR0;                                 /*  CNBCR0          */
    54 /* end of struct st_mlb_from_cecr0 */
    55 /* start of struct st_mlb_from_cecr0 */
    56     volatile uint32_t  CECR1;                                  /*  CECR1           */
    57     volatile uint32_t  CSCR1;                                  /*  CSCR1           */
    58     volatile uint32_t  CCBCR1;                                 /*  CCBCR1          */
    59     volatile uint32_t  CNBCR1;                                 /*  CNBCR1          */
    60 /* end of struct st_mlb_from_cecr0 */
    61 /* start of struct st_mlb_from_cecr0 */
    62     volatile uint32_t  CECR2;                                  /*  CECR2           */
    63     volatile uint32_t  CSCR2;                                  /*  CSCR2           */
    64     volatile uint32_t  CCBCR2;                                 /*  CCBCR2          */
    65     volatile uint32_t  CNBCR2;                                 /*  CNBCR2          */
    66 /* end of struct st_mlb_from_cecr0 */
    67 /* start of struct st_mlb_from_cecr0 */
    68     volatile uint32_t  CECR3;                                  /*  CECR3           */
    69     volatile uint32_t  CSCR3;                                  /*  CSCR3           */
    70     volatile uint32_t  CCBCR3;                                 /*  CCBCR3          */
    71     volatile uint32_t  CNBCR3;                                 /*  CNBCR3          */
    72 /* end of struct st_mlb_from_cecr0 */
    73 /* start of struct st_mlb_from_cecr0 */
    74     volatile uint32_t  CECR4;                                  /*  CECR4           */
    75     volatile uint32_t  CSCR4;                                  /*  CSCR4           */
    76     volatile uint32_t  CCBCR4;                                 /*  CCBCR4          */
    77     volatile uint32_t  CNBCR4;                                 /*  CNBCR4          */
    78 /* end of struct st_mlb_from_cecr0 */
    79 /* start of struct st_mlb_from_cecr0 */
    80     volatile uint32_t  CECR5;                                  /*  CECR5           */
    81     volatile uint32_t  CSCR5;                                  /*  CSCR5           */
    82     volatile uint32_t  CCBCR5;                                 /*  CCBCR5          */
    83     volatile uint32_t  CNBCR5;                                 /*  CNBCR5          */
    84 /* end of struct st_mlb_from_cecr0 */
    85 /* start of struct st_mlb_from_cecr0 */
    86     volatile uint32_t  CECR6;                                  /*  CECR6           */
    87     volatile uint32_t  CSCR6;                                  /*  CSCR6           */
    88     volatile uint32_t  CCBCR6;                                 /*  CCBCR6          */
    89     volatile uint32_t  CNBCR6;                                 /*  CNBCR6          */
    90 /* end of struct st_mlb_from_cecr0 */
    91 /* start of struct st_mlb_from_cecr0 */
    92     volatile uint32_t  CECR7;                                  /*  CECR7           */
    93     volatile uint32_t  CSCR7;                                  /*  CSCR7           */
    94     volatile uint32_t  CCBCR7;                                 /*  CCBCR7          */
    95     volatile uint32_t  CNBCR7;                                 /*  CNBCR7          */
    96 /* end of struct st_mlb_from_cecr0 */
    97 /* start of struct st_mlb_from_cecr0 */
    98     volatile uint32_t  CECR8;                                  /*  CECR8           */
    99     volatile uint32_t  CSCR8;                                  /*  CSCR8           */
    100     volatile uint32_t  CCBCR8;                                 /*  CCBCR8          */
    101     volatile uint32_t  CNBCR8;                                 /*  CNBCR8          */
    102 /* end of struct st_mlb_from_cecr0 */
    103 /* start of struct st_mlb_from_cecr0 */
    104     volatile uint32_t  CECR9;                                  /*  CECR9           */
    105     volatile uint32_t  CSCR9;                                  /*  CSCR9           */
    106     volatile uint32_t  CCBCR9;                                 /*  CCBCR9          */
    107     volatile uint32_t  CNBCR9;                                 /*  CNBCR9          */
    108 /* end of struct st_mlb_from_cecr0 */
    109 /* start of struct st_mlb_from_cecr0 */
    110     volatile uint32_t  CECR10;                                 /*  CECR10          */
    111     volatile uint32_t  CSCR10;                                 /*  CSCR10          */
    112     volatile uint32_t  CCBCR10;                                /*  CCBCR10         */
    113     volatile uint32_t  CNBCR10;                                /*  CNBCR10         */
    114 /* end of struct st_mlb_from_cecr0 */
    115 /* start of struct st_mlb_from_cecr0 */
    116     volatile uint32_t  CECR11;                                 /*  CECR11          */
    117     volatile uint32_t  CSCR11;                                 /*  CSCR11          */
    118     volatile uint32_t  CCBCR11;                                /*  CCBCR11         */
    119     volatile uint32_t  CNBCR11;                                /*  CNBCR11         */
    120 /* end of struct st_mlb_from_cecr0 */
    121 /* start of struct st_mlb_from_cecr0 */
    122     volatile uint32_t  CECR12;                                 /*  CECR12          */
    123     volatile uint32_t  CSCR12;                                 /*  CSCR12          */
    124     volatile uint32_t  CCBCR12;                                /*  CCBCR12         */
    125     volatile uint32_t  CNBCR12;                                /*  CNBCR12         */
    126 /* end of struct st_mlb_from_cecr0 */
    127 /* start of struct st_mlb_from_cecr0 */
    128     volatile uint32_t  CECR13;                                 /*  CECR13          */
    129     volatile uint32_t  CSCR13;                                 /*  CSCR13          */
    130     volatile uint32_t  CCBCR13;                                /*  CCBCR13         */
    131     volatile uint32_t  CNBCR13;                                /*  CNBCR13         */
    132 /* end of struct st_mlb_from_cecr0 */
    133 /* start of struct st_mlb_from_cecr0 */
    134     volatile uint32_t  CECR14;                                 /*  CECR14          */
    135     volatile uint32_t  CSCR14;                                 /*  CSCR14          */
    136     volatile uint32_t  CCBCR14;                                /*  CCBCR14         */
    137     volatile uint32_t  CNBCR14;                                /*  CNBCR14         */
    138 /* end of struct st_mlb_from_cecr0 */
    139 /* start of struct st_mlb_from_cecr0 */
    140     volatile uint32_t  CECR15;                                 /*  CECR15          */
    141     volatile uint32_t  CSCR15;                                 /*  CSCR15          */
    142     volatile uint32_t  CCBCR15;                                /*  CCBCR15         */
    143     volatile uint32_t  CNBCR15;                                /*  CNBCR15         */
    144 /* end of struct st_mlb_from_cecr0 */
    145 /* start of struct st_mlb_from_cecr0 */
    146     volatile uint32_t  CECR16;                                 /*  CECR16          */
    147     volatile uint32_t  CSCR16;                                 /*  CSCR16          */
    148     volatile uint32_t  CCBCR16;                                /*  CCBCR16         */
    149     volatile uint32_t  CNBCR16;                                /*  CNBCR16         */
    150 /* end of struct st_mlb_from_cecr0 */
    151 /* start of struct st_mlb_from_cecr0 */
    152     volatile uint32_t  CECR17;                                 /*  CECR17          */
    153     volatile uint32_t  CSCR17;                                 /*  CSCR17          */
    154     volatile uint32_t  CCBCR17;                                /*  CCBCR17         */
    155     volatile uint32_t  CNBCR17;                                /*  CNBCR17         */
    156 /* end of struct st_mlb_from_cecr0 */
    157 /* start of struct st_mlb_from_cecr0 */
    158     volatile uint32_t  CECR18;                                 /*  CECR18          */
    159     volatile uint32_t  CSCR18;                                 /*  CSCR18          */
    160     volatile uint32_t  CCBCR18;                                /*  CCBCR18         */
    161     volatile uint32_t  CNBCR18;                                /*  CNBCR18         */
    162 /* end of struct st_mlb_from_cecr0 */
    163 /* start of struct st_mlb_from_cecr0 */
    164     volatile uint32_t  CECR19;                                 /*  CECR19          */
    165     volatile uint32_t  CSCR19;                                 /*  CSCR19          */
    166     volatile uint32_t  CCBCR19;                                /*  CCBCR19         */
    167     volatile uint32_t  CNBCR19;                                /*  CNBCR19         */
    168 /* end of struct st_mlb_from_cecr0 */
    169 /* start of struct st_mlb_from_cecr0 */
    170     volatile uint32_t  CECR20;                                 /*  CECR20          */
    171     volatile uint32_t  CSCR20;                                 /*  CSCR20          */
    172     volatile uint32_t  CCBCR20;                                /*  CCBCR20         */
    173     volatile uint32_t  CNBCR20;                                /*  CNBCR20         */
    174 /* end of struct st_mlb_from_cecr0 */
    175 /* start of struct st_mlb_from_cecr0 */
    176     volatile uint32_t  CECR21;                                 /*  CECR21          */
    177     volatile uint32_t  CSCR21;                                 /*  CSCR21          */
    178     volatile uint32_t  CCBCR21;                                /*  CCBCR21         */
    179     volatile uint32_t  CNBCR21;                                /*  CNBCR21         */
    180 /* end of struct st_mlb_from_cecr0 */
    181 /* start of struct st_mlb_from_cecr0 */
    182     volatile uint32_t  CECR22;                                 /*  CECR22          */
    183     volatile uint32_t  CSCR22;                                 /*  CSCR22          */
    184     volatile uint32_t  CCBCR22;                                /*  CCBCR22         */
    185     volatile uint32_t  CNBCR22;                                /*  CNBCR22         */
    186 /* end of struct st_mlb_from_cecr0 */
    187 /* start of struct st_mlb_from_cecr0 */
    188     volatile uint32_t  CECR23;                                 /*  CECR23          */
    189     volatile uint32_t  CSCR23;                                 /*  CSCR23          */
    190     volatile uint32_t  CCBCR23;                                /*  CCBCR23         */
    191     volatile uint32_t  CNBCR23;                                /*  CNBCR23         */
    192 /* end of struct st_mlb_from_cecr0 */
    193 /* start of struct st_mlb_from_cecr0 */
    194     volatile uint32_t  CECR24;                                 /*  CECR24          */
    195     volatile uint32_t  CSCR24;                                 /*  CSCR24          */
    196     volatile uint32_t  CCBCR24;                                /*  CCBCR24         */
    197     volatile uint32_t  CNBCR24;                                /*  CNBCR24         */
    198 /* end of struct st_mlb_from_cecr0 */
    199 /* start of struct st_mlb_from_cecr0 */
    200     volatile uint32_t  CECR25;                                 /*  CECR25          */
    201     volatile uint32_t  CSCR25;                                 /*  CSCR25          */
    202     volatile uint32_t  CCBCR25;                                /*  CCBCR25         */
    203     volatile uint32_t  CNBCR25;                                /*  CNBCR25         */
    204 /* end of struct st_mlb_from_cecr0 */
    205 /* start of struct st_mlb_from_cecr0 */
    206     volatile uint32_t  CECR26;                                 /*  CECR26          */
    207     volatile uint32_t  CSCR26;                                 /*  CSCR26          */
    208     volatile uint32_t  CCBCR26;                                /*  CCBCR26         */
    209     volatile uint32_t  CNBCR26;                                /*  CNBCR26         */
    210 /* end of struct st_mlb_from_cecr0 */
    211 /* start of struct st_mlb_from_cecr0 */
    212     volatile uint32_t  CECR27;                                 /*  CECR27          */
    213     volatile uint32_t  CSCR27;                                 /*  CSCR27          */
    214     volatile uint32_t  CCBCR27;                                /*  CCBCR27         */
    215     volatile uint32_t  CNBCR27;                                /*  CNBCR27         */
    216 /* end of struct st_mlb_from_cecr0 */
    217 /* start of struct st_mlb_from_cecr0 */
    218     volatile uint32_t  CECR28;                                 /*  CECR28          */
    219     volatile uint32_t  CSCR28;                                 /*  CSCR28          */
    220     volatile uint32_t  CCBCR28;                                /*  CCBCR28         */
    221     volatile uint32_t  CNBCR28;                                /*  CNBCR28         */
    222 /* end of struct st_mlb_from_cecr0 */
    223 /* start of struct st_mlb_from_cecr0 */
    224     volatile uint32_t  CECR29;                                 /*  CECR29          */
    225     volatile uint32_t  CSCR29;                                 /*  CSCR29          */
    226     volatile uint32_t  CCBCR29;                                /*  CCBCR29         */
    227     volatile uint32_t  CNBCR29;                                /*  CNBCR29         */
    228 /* end of struct st_mlb_from_cecr0 */
    229 /* start of struct st_mlb_from_cecr0 */
    230     volatile uint32_t  CECR30;                                 /*  CECR30          */
    231     volatile uint32_t  CSCR30;                                 /*  CSCR30          */
    232     volatile uint32_t  CCBCR30;                                /*  CCBCR30         */
    233     volatile uint32_t  CNBCR30;                                /*  CNBCR30         */
    234 /* end of struct st_mlb_from_cecr0 */
    235     volatile uint8_t   dummy158[80];                           /*                  */
    236 #define MLB_LCBCR0_COUNT 31
    237     volatile uint32_t  LCBCR0;                                 /*  LCBCR0          */
    238     volatile uint32_t  LCBCR1;                                 /*  LCBCR1          */
    239     volatile uint32_t  LCBCR2;                                 /*  LCBCR2          */
    240     volatile uint32_t  LCBCR3;                                 /*  LCBCR3          */
    241     volatile uint32_t  LCBCR4;                                 /*  LCBCR4          */
    242     volatile uint32_t  LCBCR5;                                 /*  LCBCR5          */
    243     volatile uint32_t  LCBCR6;                                 /*  LCBCR6          */
    244     volatile uint32_t  LCBCR7;                                 /*  LCBCR7          */
    245     volatile uint32_t  LCBCR8;                                 /*  LCBCR8          */
    246     volatile uint32_t  LCBCR9;                                 /*  LCBCR9          */
    247     volatile uint32_t  LCBCR10;                                /*  LCBCR10         */
    248     volatile uint32_t  LCBCR11;                                /*  LCBCR11         */
    249     volatile uint32_t  LCBCR12;                                /*  LCBCR12         */
    250     volatile uint32_t  LCBCR13;                                /*  LCBCR13         */
    251     volatile uint32_t  LCBCR14;                                /*  LCBCR14         */
    252     volatile uint32_t  LCBCR15;                                /*  LCBCR15         */
    253     volatile uint32_t  LCBCR16;                                /*  LCBCR16         */
    254     volatile uint32_t  LCBCR17;                                /*  LCBCR17         */
    255     volatile uint32_t  LCBCR18;                                /*  LCBCR18         */
    256     volatile uint32_t  LCBCR19;                                /*  LCBCR19         */
    257     volatile uint32_t  LCBCR20;                                /*  LCBCR20         */
    258     volatile uint32_t  LCBCR21;                                /*  LCBCR21         */
    259     volatile uint32_t  LCBCR22;                                /*  LCBCR22         */
    260     volatile uint32_t  LCBCR23;                                /*  LCBCR23         */
    261     volatile uint32_t  LCBCR24;                                /*  LCBCR24         */
    262     volatile uint32_t  LCBCR25;                                /*  LCBCR25         */
    263     volatile uint32_t  LCBCR26;                                /*  LCBCR26         */
    264     volatile uint32_t  LCBCR27;                                /*  LCBCR27         */
    265     volatile uint32_t  LCBCR28;                                /*  LCBCR28         */
    266     volatile uint32_t  LCBCR29;                                /*  LCBCR29         */
    267     volatile uint32_t  LCBCR30;                                /*  LCBCR30         */
    268 };
    269 
    270 
    271 struct st_mlb_from_cecr0
    272 {
    273     volatile uint32_t  CECR0;                                  /*  CECR0           */
    274     volatile uint32_t  CSCR0;                                  /*  CSCR0           */
    275     volatile uint32_t  CCBCR0;                                 /*  CCBCR0          */
    276     volatile uint32_t  CNBCR0;                                 /*  CNBCR0          */
    277 };
    278 
    279 
    28036#define MLB     (*(struct st_mlb     *)0xE8034000uL) /* MLB */
    28137
    28238
    283 /* Start of channnel array defines of MLB */
    284 
    285 /* Channnel array defines of MLB_FROM_CECR0_ARRAY */
     39/* Start of channel array defines of MLB */
     40
     41/* Channel array defines of MLB_FROM_CECR0_ARRAY */
    28642/*(Sample) value = MLB_FROM_CECR0_ARRAY[ channel ]->CECR0; */
    287 #define MLB_FROM_CECR0_ARRAY_COUNT  31
     43#define MLB_FROM_CECR0_ARRAY_COUNT  (31)
    28844#define MLB_FROM_CECR0_ARRAY_ADDRESS_LIST \
    28945{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    … …  
    32581#define MLB_FROM_CECR30 (*(struct st_mlb_from_cecr0 *)&MLB.CECR30) /* MLB_FROM_CECR30 */
    32682
    327 /* End of channnel array defines of MLB */
    328 
    329 
    330 #define MLBDCCR MLB.DCCR
    331 #define MLBSSCR MLB.SSCR
    332 #define MLBSDCR MLB.SDCR
    333 #define MLBSMCR MLB.SMCR
    334 #define MLBVCCR MLB.VCCR
    335 #define MLBSBCR MLB.SBCR
    336 #define MLBABCR MLB.ABCR
    337 #define MLBCBCR MLB.CBCR
    338 #define MLBIBCR MLB.IBCR
    339 #define MLBCICR MLB.CICR
    340 #define MLBCECR0 MLB.CECR0
    341 #define MLBCSCR0 MLB.CSCR0
    342 #define MLBCCBCR0 MLB.CCBCR0
    343 #define MLBCNBCR0 MLB.CNBCR0
    344 #define MLBCECR1 MLB.CECR1
    345 #define MLBCSCR1 MLB.CSCR1
    346 #define MLBCCBCR1 MLB.CCBCR1
    347 #define MLBCNBCR1 MLB.CNBCR1
    348 #define MLBCECR2 MLB.CECR2
    349 #define MLBCSCR2 MLB.CSCR2
    350 #define MLBCCBCR2 MLB.CCBCR2
    351 #define MLBCNBCR2 MLB.CNBCR2
    352 #define MLBCECR3 MLB.CECR3
    353 #define MLBCSCR3 MLB.CSCR3
    354 #define MLBCCBCR3 MLB.CCBCR3
    355 #define MLBCNBCR3 MLB.CNBCR3
    356 #define MLBCECR4 MLB.CECR4
    357 #define MLBCSCR4 MLB.CSCR4
    358 #define MLBCCBCR4 MLB.CCBCR4
    359 #define MLBCNBCR4 MLB.CNBCR4
    360 #define MLBCECR5 MLB.CECR5
    361 #define MLBCSCR5 MLB.CSCR5
    362 #define MLBCCBCR5 MLB.CCBCR5
    363 #define MLBCNBCR5 MLB.CNBCR5
    364 #define MLBCECR6 MLB.CECR6
    365 #define MLBCSCR6 MLB.CSCR6
    366 #define MLBCCBCR6 MLB.CCBCR6
    367 #define MLBCNBCR6 MLB.CNBCR6
    368 #define MLBCECR7 MLB.CECR7
    369 #define MLBCSCR7 MLB.CSCR7
    370 #define MLBCCBCR7 MLB.CCBCR7
    371 #define MLBCNBCR7 MLB.CNBCR7
    372 #define MLBCECR8 MLB.CECR8
    373 #define MLBCSCR8 MLB.CSCR8
    374 #define MLBCCBCR8 MLB.CCBCR8
    375 #define MLBCNBCR8 MLB.CNBCR8
    376 #define MLBCECR9 MLB.CECR9
    377 #define MLBCSCR9 MLB.CSCR9
    378 #define MLBCCBCR9 MLB.CCBCR9
    379 #define MLBCNBCR9 MLB.CNBCR9
    380 #define MLBCECR10 MLB.CECR10
    381 #define MLBCSCR10 MLB.CSCR10
    382 #define MLBCCBCR10 MLB.CCBCR10
    383 #define MLBCNBCR10 MLB.CNBCR10
    384 #define MLBCECR11 MLB.CECR11
    385 #define MLBCSCR11 MLB.CSCR11
    386 #define MLBCCBCR11 MLB.CCBCR11
    387 #define MLBCNBCR11 MLB.CNBCR11
    388 #define MLBCECR12 MLB.CECR12
    389 #define MLBCSCR12 MLB.CSCR12
    390 #define MLBCCBCR12 MLB.CCBCR12
    391 #define MLBCNBCR12 MLB.CNBCR12
    392 #define MLBCECR13 MLB.CECR13
    393 #define MLBCSCR13 MLB.CSCR13
    394 #define MLBCCBCR13 MLB.CCBCR13
    395 #define MLBCNBCR13 MLB.CNBCR13
    396 #define MLBCECR14 MLB.CECR14
    397 #define MLBCSCR14 MLB.CSCR14
    398 #define MLBCCBCR14 MLB.CCBCR14
    399 #define MLBCNBCR14 MLB.CNBCR14
    400 #define MLBCECR15 MLB.CECR15
    401 #define MLBCSCR15 MLB.CSCR15
    402 #define MLBCCBCR15 MLB.CCBCR15
    403 #define MLBCNBCR15 MLB.CNBCR15
    404 #define MLBCECR16 MLB.CECR16
    405 #define MLBCSCR16 MLB.CSCR16
    406 #define MLBCCBCR16 MLB.CCBCR16
    407 #define MLBCNBCR16 MLB.CNBCR16
    408 #define MLBCECR17 MLB.CECR17
    409 #define MLBCSCR17 MLB.CSCR17
    410 #define MLBCCBCR17 MLB.CCBCR17
    411 #define MLBCNBCR17 MLB.CNBCR17
    412 #define MLBCECR18 MLB.CECR18
    413 #define MLBCSCR18 MLB.CSCR18
    414 #define MLBCCBCR18 MLB.CCBCR18
    415 #define MLBCNBCR18 MLB.CNBCR18
    416 #define MLBCECR19 MLB.CECR19
    417 #define MLBCSCR19 MLB.CSCR19
    418 #define MLBCCBCR19 MLB.CCBCR19
    419 #define MLBCNBCR19 MLB.CNBCR19
    420 #define MLBCECR20 MLB.CECR20
    421 #define MLBCSCR20 MLB.CSCR20
    422 #define MLBCCBCR20 MLB.CCBCR20
    423 #define MLBCNBCR20 MLB.CNBCR20
    424 #define MLBCECR21 MLB.CECR21
    425 #define MLBCSCR21 MLB.CSCR21
    426 #define MLBCCBCR21 MLB.CCBCR21
    427 #define MLBCNBCR21 MLB.CNBCR21
    428 #define MLBCECR22 MLB.CECR22
    429 #define MLBCSCR22 MLB.CSCR22
    430 #define MLBCCBCR22 MLB.CCBCR22
    431 #define MLBCNBCR22 MLB.CNBCR22
    432 #define MLBCECR23 MLB.CECR23
    433 #define MLBCSCR23 MLB.CSCR23
    434 #define MLBCCBCR23 MLB.CCBCR23
    435 #define MLBCNBCR23 MLB.CNBCR23
    436 #define MLBCECR24 MLB.CECR24
    437 #define MLBCSCR24 MLB.CSCR24
    438 #define MLBCCBCR24 MLB.CCBCR24
    439 #define MLBCNBCR24 MLB.CNBCR24
    440 #define MLBCECR25 MLB.CECR25
    441 #define MLBCSCR25 MLB.CSCR25
    442 #define MLBCCBCR25 MLB.CCBCR25
    443 #define MLBCNBCR25 MLB.CNBCR25
    444 #define MLBCECR26 MLB.CECR26
    445 #define MLBCSCR26 MLB.CSCR26
    446 #define MLBCCBCR26 MLB.CCBCR26
    447 #define MLBCNBCR26 MLB.CNBCR26
    448 #define MLBCECR27 MLB.CECR27
    449 #define MLBCSCR27 MLB.CSCR27
    450 #define MLBCCBCR27 MLB.CCBCR27
    451 #define MLBCNBCR27 MLB.CNBCR27
    452 #define MLBCECR28 MLB.CECR28
    453 #define MLBCSCR28 MLB.CSCR28
    454 #define MLBCCBCR28 MLB.CCBCR28
    455 #define MLBCNBCR28 MLB.CNBCR28
    456 #define MLBCECR29 MLB.CECR29
    457 #define MLBCSCR29 MLB.CSCR29
    458 #define MLBCCBCR29 MLB.CCBCR29
    459 #define MLBCNBCR29 MLB.CNBCR29
    460 #define MLBCECR30 MLB.CECR30
    461 #define MLBCSCR30 MLB.CSCR30
    462 #define MLBCCBCR30 MLB.CCBCR30
    463 #define MLBCNBCR30 MLB.CNBCR30
    464 #define MLBLCBCR0 MLB.LCBCR0
    465 #define MLBLCBCR1 MLB.LCBCR1
    466 #define MLBLCBCR2 MLB.LCBCR2
    467 #define MLBLCBCR3 MLB.LCBCR3
    468 #define MLBLCBCR4 MLB.LCBCR4
    469 #define MLBLCBCR5 MLB.LCBCR5
    470 #define MLBLCBCR6 MLB.LCBCR6
    471 #define MLBLCBCR7 MLB.LCBCR7
    472 #define MLBLCBCR8 MLB.LCBCR8
    473 #define MLBLCBCR9 MLB.LCBCR9
    474 #define MLBLCBCR10 MLB.LCBCR10
    475 #define MLBLCBCR11 MLB.LCBCR11
    476 #define MLBLCBCR12 MLB.LCBCR12
    477 #define MLBLCBCR13 MLB.LCBCR13
    478 #define MLBLCBCR14 MLB.LCBCR14
    479 #define MLBLCBCR15 MLB.LCBCR15
    480 #define MLBLCBCR16 MLB.LCBCR16
    481 #define MLBLCBCR17 MLB.LCBCR17
    482 #define MLBLCBCR18 MLB.LCBCR18
    483 #define MLBLCBCR19 MLB.LCBCR19
    484 #define MLBLCBCR20 MLB.LCBCR20
    485 #define MLBLCBCR21 MLB.LCBCR21
    486 #define MLBLCBCR22 MLB.LCBCR22
    487 #define MLBLCBCR23 MLB.LCBCR23
    488 #define MLBLCBCR24 MLB.LCBCR24
    489 #define MLBLCBCR25 MLB.LCBCR25
    490 #define MLBLCBCR26 MLB.LCBCR26
    491 #define MLBLCBCR27 MLB.LCBCR27
    492 #define MLBLCBCR28 MLB.LCBCR28
    493 #define MLBLCBCR29 MLB.LCBCR29
    494 #define MLBLCBCR30 MLB.LCBCR30
     83/* End of channel array defines of MLB */
     84
     85
     86#define MLBDCCR (MLB.DCCR)
     87#define MLBSSCR (MLB.SSCR)
     88#define MLBSDCR (MLB.SDCR)
     89#define MLBSMCR (MLB.SMCR)
     90#define MLBVCCR (MLB.VCCR)
     91#define MLBSBCR (MLB.SBCR)
     92#define MLBABCR (MLB.ABCR)
     93#define MLBCBCR (MLB.CBCR)
     94#define MLBIBCR (MLB.IBCR)
     95#define MLBCICR (MLB.CICR)
     96#define MLBCECR0 (MLB.CECR0)
     97#define MLBCSCR0 (MLB.CSCR0)
     98#define MLBCCBCR0 (MLB.CCBCR0)
     99#define MLBCNBCR0 (MLB.CNBCR0)
     100#define MLBCECR1 (MLB.CECR1)
     101#define MLBCSCR1 (MLB.CSCR1)
     102#define MLBCCBCR1 (MLB.CCBCR1)
     103#define MLBCNBCR1 (MLB.CNBCR1)
     104#define MLBCECR2 (MLB.CECR2)
     105#define MLBCSCR2 (MLB.CSCR2)
     106#define MLBCCBCR2 (MLB.CCBCR2)
     107#define MLBCNBCR2 (MLB.CNBCR2)
     108#define MLBCECR3 (MLB.CECR3)
     109#define MLBCSCR3 (MLB.CSCR3)
     110#define MLBCCBCR3 (MLB.CCBCR3)
     111#define MLBCNBCR3 (MLB.CNBCR3)
     112#define MLBCECR4 (MLB.CECR4)
     113#define MLBCSCR4 (MLB.CSCR4)
     114#define MLBCCBCR4 (MLB.CCBCR4)
     115#define MLBCNBCR4 (MLB.CNBCR4)
     116#define MLBCECR5 (MLB.CECR5)
     117#define MLBCSCR5 (MLB.CSCR5)
     118#define MLBCCBCR5 (MLB.CCBCR5)
     119#define MLBCNBCR5 (MLB.CNBCR5)
     120#define MLBCECR6 (MLB.CECR6)
     121#define MLBCSCR6 (MLB.CSCR6)
     122#define MLBCCBCR6 (MLB.CCBCR6)
     123#define MLBCNBCR6 (MLB.CNBCR6)
     124#define MLBCECR7 (MLB.CECR7)
     125#define MLBCSCR7 (MLB.CSCR7)
     126#define MLBCCBCR7 (MLB.CCBCR7)
     127#define MLBCNBCR7 (MLB.CNBCR7)
     128#define MLBCECR8 (MLB.CECR8)
     129#define MLBCSCR8 (MLB.CSCR8)
     130#define MLBCCBCR8 (MLB.CCBCR8)
     131#define MLBCNBCR8 (MLB.CNBCR8)
     132#define MLBCECR9 (MLB.CECR9)
     133#define MLBCSCR9 (MLB.CSCR9)
     134#define MLBCCBCR9 (MLB.CCBCR9)
     135#define MLBCNBCR9 (MLB.CNBCR9)
     136#define MLBCECR10 (MLB.CECR10)
     137#define MLBCSCR10 (MLB.CSCR10)
     138#define MLBCCBCR10 (MLB.CCBCR10)
     139#define MLBCNBCR10 (MLB.CNBCR10)
     140#define MLBCECR11 (MLB.CECR11)
     141#define MLBCSCR11 (MLB.CSCR11)
     142#define MLBCCBCR11 (MLB.CCBCR11)
     143#define MLBCNBCR11 (MLB.CNBCR11)
     144#define MLBCECR12 (MLB.CECR12)
     145#define MLBCSCR12 (MLB.CSCR12)
     146#define MLBCCBCR12 (MLB.CCBCR12)
     147#define MLBCNBCR12 (MLB.CNBCR12)
     148#define MLBCECR13 (MLB.CECR13)
     149#define MLBCSCR13 (MLB.CSCR13)
     150#define MLBCCBCR13 (MLB.CCBCR13)
     151#define MLBCNBCR13 (MLB.CNBCR13)
     152#define MLBCECR14 (MLB.CECR14)
     153#define MLBCSCR14 (MLB.CSCR14)
     154#define MLBCCBCR14 (MLB.CCBCR14)
     155#define MLBCNBCR14 (MLB.CNBCR14)
     156#define MLBCECR15 (MLB.CECR15)
     157#define MLBCSCR15 (MLB.CSCR15)
     158#define MLBCCBCR15 (MLB.CCBCR15)
     159#define MLBCNBCR15 (MLB.CNBCR15)
     160#define MLBCECR16 (MLB.CECR16)
     161#define MLBCSCR16 (MLB.CSCR16)
     162#define MLBCCBCR16 (MLB.CCBCR16)
     163#define MLBCNBCR16 (MLB.CNBCR16)
     164#define MLBCECR17 (MLB.CECR17)
     165#define MLBCSCR17 (MLB.CSCR17)
     166#define MLBCCBCR17 (MLB.CCBCR17)
     167#define MLBCNBCR17 (MLB.CNBCR17)
     168#define MLBCECR18 (MLB.CECR18)
     169#define MLBCSCR18 (MLB.CSCR18)
     170#define MLBCCBCR18 (MLB.CCBCR18)
     171#define MLBCNBCR18 (MLB.CNBCR18)
     172#define MLBCECR19 (MLB.CECR19)
     173#define MLBCSCR19 (MLB.CSCR19)
     174#define MLBCCBCR19 (MLB.CCBCR19)
     175#define MLBCNBCR19 (MLB.CNBCR19)
     176#define MLBCECR20 (MLB.CECR20)
     177#define MLBCSCR20 (MLB.CSCR20)
     178#define MLBCCBCR20 (MLB.CCBCR20)
     179#define MLBCNBCR20 (MLB.CNBCR20)
     180#define MLBCECR21 (MLB.CECR21)
     181#define MLBCSCR21 (MLB.CSCR21)
     182#define MLBCCBCR21 (MLB.CCBCR21)
     183#define MLBCNBCR21 (MLB.CNBCR21)
     184#define MLBCECR22 (MLB.CECR22)
     185#define MLBCSCR22 (MLB.CSCR22)
     186#define MLBCCBCR22 (MLB.CCBCR22)
     187#define MLBCNBCR22 (MLB.CNBCR22)
     188#define MLBCECR23 (MLB.CECR23)
     189#define MLBCSCR23 (MLB.CSCR23)
     190#define MLBCCBCR23 (MLB.CCBCR23)
     191#define MLBCNBCR23 (MLB.CNBCR23)
     192#define MLBCECR24 (MLB.CECR24)
     193#define MLBCSCR24 (MLB.CSCR24)
     194#define MLBCCBCR24 (MLB.CCBCR24)
     195#define MLBCNBCR24 (MLB.CNBCR24)
     196#define MLBCECR25 (MLB.CECR25)
     197#define MLBCSCR25 (MLB.CSCR25)
     198#define MLBCCBCR25 (MLB.CCBCR25)
     199#define MLBCNBCR25 (MLB.CNBCR25)
     200#define MLBCECR26 (MLB.CECR26)
     201#define MLBCSCR26 (MLB.CSCR26)
     202#define MLBCCBCR26 (MLB.CCBCR26)
     203#define MLBCNBCR26 (MLB.CNBCR26)
     204#define MLBCECR27 (MLB.CECR27)
     205#define MLBCSCR27 (MLB.CSCR27)
     206#define MLBCCBCR27 (MLB.CCBCR27)
     207#define MLBCNBCR27 (MLB.CNBCR27)
     208#define MLBCECR28 (MLB.CECR28)
     209#define MLBCSCR28 (MLB.CSCR28)
     210#define MLBCCBCR28 (MLB.CCBCR28)
     211#define MLBCNBCR28 (MLB.CNBCR28)
     212#define MLBCECR29 (MLB.CECR29)
     213#define MLBCSCR29 (MLB.CSCR29)
     214#define MLBCCBCR29 (MLB.CCBCR29)
     215#define MLBCNBCR29 (MLB.CNBCR29)
     216#define MLBCECR30 (MLB.CECR30)
     217#define MLBCSCR30 (MLB.CSCR30)
     218#define MLBCCBCR30 (MLB.CCBCR30)
     219#define MLBCNBCR30 (MLB.CNBCR30)
     220#define MLBLCBCR0 (MLB.LCBCR0)
     221#define MLBLCBCR1 (MLB.LCBCR1)
     222#define MLBLCBCR2 (MLB.LCBCR2)
     223#define MLBLCBCR3 (MLB.LCBCR3)
     224#define MLBLCBCR4 (MLB.LCBCR4)
     225#define MLBLCBCR5 (MLB.LCBCR5)
     226#define MLBLCBCR6 (MLB.LCBCR6)
     227#define MLBLCBCR7 (MLB.LCBCR7)
     228#define MLBLCBCR8 (MLB.LCBCR8)
     229#define MLBLCBCR9 (MLB.LCBCR9)
     230#define MLBLCBCR10 (MLB.LCBCR10)
     231#define MLBLCBCR11 (MLB.LCBCR11)
     232#define MLBLCBCR12 (MLB.LCBCR12)
     233#define MLBLCBCR13 (MLB.LCBCR13)
     234#define MLBLCBCR14 (MLB.LCBCR14)
     235#define MLBLCBCR15 (MLB.LCBCR15)
     236#define MLBLCBCR16 (MLB.LCBCR16)
     237#define MLBLCBCR17 (MLB.LCBCR17)
     238#define MLBLCBCR18 (MLB.LCBCR18)
     239#define MLBLCBCR19 (MLB.LCBCR19)
     240#define MLBLCBCR20 (MLB.LCBCR20)
     241#define MLBLCBCR21 (MLB.LCBCR21)
     242#define MLBLCBCR22 (MLB.LCBCR22)
     243#define MLBLCBCR23 (MLB.LCBCR23)
     244#define MLBLCBCR24 (MLB.LCBCR24)
     245#define MLBLCBCR25 (MLB.LCBCR25)
     246#define MLBLCBCR26 (MLB.LCBCR26)
     247#define MLBLCBCR27 (MLB.LCBCR27)
     248#define MLBLCBCR28 (MLB.LCBCR28)
     249#define MLBLCBCR29 (MLB.LCBCR29)
     250#define MLBLCBCR30 (MLB.LCBCR30)
     251
     252#define MLB_LCBCR0_COUNT (31)
     253
     254
     255typedef struct st_mlb
     256{
     257                                                           /* MLB              */
     258    volatile uint32_t  DCCR;                                   /*  DCCR            */
     259    volatile uint32_t  SSCR;                                   /*  SSCR            */
     260    volatile uint32_t  SDCR;                                   /*  SDCR            */
     261    volatile uint32_t  SMCR;                                   /*  SMCR            */
     262    volatile uint8_t   dummy156[12];                           /*                  */
     263    volatile uint32_t  VCCR;                                   /*  VCCR            */
     264    volatile uint32_t  SBCR;                                   /*  SBCR            */
     265    volatile uint32_t  ABCR;                                   /*  ABCR            */
     266    volatile uint32_t  CBCR;                                   /*  CBCR            */
     267    volatile uint32_t  IBCR;                                   /*  IBCR            */
     268    volatile uint32_t  CICR;                                   /*  CICR            */
     269    volatile uint8_t   dummy157[12];                           /*                  */
     270
     271/* start of struct st_mlb_from_cecr0 */
     272    volatile uint32_t  CECR0;                                  /*  CECR0           */
     273    volatile uint32_t  CSCR0;                                  /*  CSCR0           */
     274    volatile uint32_t  CCBCR0;                                 /*  CCBCR0          */
     275    volatile uint32_t  CNBCR0;                                 /*  CNBCR0          */
     276
     277/* end of struct st_mlb_from_cecr0 */
     278
     279/* start of struct st_mlb_from_cecr0 */
     280    volatile uint32_t  CECR1;                                  /*  CECR1           */
     281    volatile uint32_t  CSCR1;                                  /*  CSCR1           */
     282    volatile uint32_t  CCBCR1;                                 /*  CCBCR1          */
     283    volatile uint32_t  CNBCR1;                                 /*  CNBCR1          */
     284
     285/* end of struct st_mlb_from_cecr0 */
     286
     287/* start of struct st_mlb_from_cecr0 */
     288    volatile uint32_t  CECR2;                                  /*  CECR2           */
     289    volatile uint32_t  CSCR2;                                  /*  CSCR2           */
     290    volatile uint32_t  CCBCR2;                                 /*  CCBCR2          */
     291    volatile uint32_t  CNBCR2;                                 /*  CNBCR2          */
     292
     293/* end of struct st_mlb_from_cecr0 */
     294
     295/* start of struct st_mlb_from_cecr0 */
     296    volatile uint32_t  CECR3;                                  /*  CECR3           */
     297    volatile uint32_t  CSCR3;                                  /*  CSCR3           */
     298    volatile uint32_t  CCBCR3;                                 /*  CCBCR3          */
     299    volatile uint32_t  CNBCR3;                                 /*  CNBCR3          */
     300
     301/* end of struct st_mlb_from_cecr0 */
     302
     303/* start of struct st_mlb_from_cecr0 */
     304    volatile uint32_t  CECR4;                                  /*  CECR4           */
     305    volatile uint32_t  CSCR4;                                  /*  CSCR4           */
     306    volatile uint32_t  CCBCR4;                                 /*  CCBCR4          */
     307    volatile uint32_t  CNBCR4;                                 /*  CNBCR4          */
     308
     309/* end of struct st_mlb_from_cecr0 */
     310
     311/* start of struct st_mlb_from_cecr0 */
     312    volatile uint32_t  CECR5;                                  /*  CECR5           */
     313    volatile uint32_t  CSCR5;                                  /*  CSCR5           */
     314    volatile uint32_t  CCBCR5;                                 /*  CCBCR5          */
     315    volatile uint32_t  CNBCR5;                                 /*  CNBCR5          */
     316
     317/* end of struct st_mlb_from_cecr0 */
     318
     319/* start of struct st_mlb_from_cecr0 */
     320    volatile uint32_t  CECR6;                                  /*  CECR6           */
     321    volatile uint32_t  CSCR6;                                  /*  CSCR6           */
     322    volatile uint32_t  CCBCR6;                                 /*  CCBCR6          */
     323    volatile uint32_t  CNBCR6;                                 /*  CNBCR6          */
     324
     325/* end of struct st_mlb_from_cecr0 */
     326
     327/* start of struct st_mlb_from_cecr0 */
     328    volatile uint32_t  CECR7;                                  /*  CECR7           */
     329    volatile uint32_t  CSCR7;                                  /*  CSCR7           */
     330    volatile uint32_t  CCBCR7;                                 /*  CCBCR7          */
     331    volatile uint32_t  CNBCR7;                                 /*  CNBCR7          */
     332
     333/* end of struct st_mlb_from_cecr0 */
     334
     335/* start of struct st_mlb_from_cecr0 */
     336    volatile uint32_t  CECR8;                                  /*  CECR8           */
     337    volatile uint32_t  CSCR8;                                  /*  CSCR8           */
     338    volatile uint32_t  CCBCR8;                                 /*  CCBCR8          */
     339    volatile uint32_t  CNBCR8;                                 /*  CNBCR8          */
     340
     341/* end of struct st_mlb_from_cecr0 */
     342
     343/* start of struct st_mlb_from_cecr0 */
     344    volatile uint32_t  CECR9;                                  /*  CECR9           */
     345    volatile uint32_t  CSCR9;                                  /*  CSCR9           */
     346    volatile uint32_t  CCBCR9;                                 /*  CCBCR9          */
     347    volatile uint32_t  CNBCR9;                                 /*  CNBCR9          */
     348
     349/* end of struct st_mlb_from_cecr0 */
     350
     351/* start of struct st_mlb_from_cecr0 */
     352    volatile uint32_t  CECR10;                                 /*  CECR10          */
     353    volatile uint32_t  CSCR10;                                 /*  CSCR10          */
     354    volatile uint32_t  CCBCR10;                                /*  CCBCR10         */
     355    volatile uint32_t  CNBCR10;                                /*  CNBCR10         */
     356
     357/* end of struct st_mlb_from_cecr0 */
     358
     359/* start of struct st_mlb_from_cecr0 */
     360    volatile uint32_t  CECR11;                                 /*  CECR11          */
     361    volatile uint32_t  CSCR11;                                 /*  CSCR11          */
     362    volatile uint32_t  CCBCR11;                                /*  CCBCR11         */
     363    volatile uint32_t  CNBCR11;                                /*  CNBCR11         */
     364
     365/* end of struct st_mlb_from_cecr0 */
     366
     367/* start of struct st_mlb_from_cecr0 */
     368    volatile uint32_t  CECR12;                                 /*  CECR12          */
     369    volatile uint32_t  CSCR12;                                 /*  CSCR12          */
     370    volatile uint32_t  CCBCR12;                                /*  CCBCR12         */
     371    volatile uint32_t  CNBCR12;                                /*  CNBCR12         */
     372
     373/* end of struct st_mlb_from_cecr0 */
     374
     375/* start of struct st_mlb_from_cecr0 */
     376    volatile uint32_t  CECR13;                                 /*  CECR13          */
     377    volatile uint32_t  CSCR13;                                 /*  CSCR13          */
     378    volatile uint32_t  CCBCR13;                                /*  CCBCR13         */
     379    volatile uint32_t  CNBCR13;                                /*  CNBCR13         */
     380
     381/* end of struct st_mlb_from_cecr0 */
     382
     383/* start of struct st_mlb_from_cecr0 */
     384    volatile uint32_t  CECR14;                                 /*  CECR14          */
     385    volatile uint32_t  CSCR14;                                 /*  CSCR14          */
     386    volatile uint32_t  CCBCR14;                                /*  CCBCR14         */
     387    volatile uint32_t  CNBCR14;                                /*  CNBCR14         */
     388
     389/* end of struct st_mlb_from_cecr0 */
     390
     391/* start of struct st_mlb_from_cecr0 */
     392    volatile uint32_t  CECR15;                                 /*  CECR15          */
     393    volatile uint32_t  CSCR15;                                 /*  CSCR15          */
     394    volatile uint32_t  CCBCR15;                                /*  CCBCR15         */
     395    volatile uint32_t  CNBCR15;                                /*  CNBCR15         */
     396
     397/* end of struct st_mlb_from_cecr0 */
     398
     399/* start of struct st_mlb_from_cecr0 */
     400    volatile uint32_t  CECR16;                                 /*  CECR16          */
     401    volatile uint32_t  CSCR16;                                 /*  CSCR16          */
     402    volatile uint32_t  CCBCR16;                                /*  CCBCR16         */
     403    volatile uint32_t  CNBCR16;                                /*  CNBCR16         */
     404
     405/* end of struct st_mlb_from_cecr0 */
     406
     407/* start of struct st_mlb_from_cecr0 */
     408    volatile uint32_t  CECR17;                                 /*  CECR17          */
     409    volatile uint32_t  CSCR17;                                 /*  CSCR17          */
     410    volatile uint32_t  CCBCR17;                                /*  CCBCR17         */
     411    volatile uint32_t  CNBCR17;                                /*  CNBCR17         */
     412
     413/* end of struct st_mlb_from_cecr0 */
     414
     415/* start of struct st_mlb_from_cecr0 */
     416    volatile uint32_t  CECR18;                                 /*  CECR18          */
     417    volatile uint32_t  CSCR18;                                 /*  CSCR18          */
     418    volatile uint32_t  CCBCR18;                                /*  CCBCR18         */
     419    volatile uint32_t  CNBCR18;                                /*  CNBCR18         */
     420
     421/* end of struct st_mlb_from_cecr0 */
     422
     423/* start of struct st_mlb_from_cecr0 */
     424    volatile uint32_t  CECR19;                                 /*  CECR19          */
     425    volatile uint32_t  CSCR19;                                 /*  CSCR19          */
     426    volatile uint32_t  CCBCR19;                                /*  CCBCR19         */
     427    volatile uint32_t  CNBCR19;                                /*  CNBCR19         */
     428
     429/* end of struct st_mlb_from_cecr0 */
     430
     431/* start of struct st_mlb_from_cecr0 */
     432    volatile uint32_t  CECR20;                                 /*  CECR20          */
     433    volatile uint32_t  CSCR20;                                 /*  CSCR20          */
     434    volatile uint32_t  CCBCR20;                                /*  CCBCR20         */
     435    volatile uint32_t  CNBCR20;                                /*  CNBCR20         */
     436
     437/* end of struct st_mlb_from_cecr0 */
     438
     439/* start of struct st_mlb_from_cecr0 */
     440    volatile uint32_t  CECR21;                                 /*  CECR21          */
     441    volatile uint32_t  CSCR21;                                 /*  CSCR21          */
     442    volatile uint32_t  CCBCR21;                                /*  CCBCR21         */
     443    volatile uint32_t  CNBCR21;                                /*  CNBCR21         */
     444
     445/* end of struct st_mlb_from_cecr0 */
     446
     447/* start of struct st_mlb_from_cecr0 */
     448    volatile uint32_t  CECR22;                                 /*  CECR22          */
     449    volatile uint32_t  CSCR22;                                 /*  CSCR22          */
     450    volatile uint32_t  CCBCR22;                                /*  CCBCR22         */
     451    volatile uint32_t  CNBCR22;                                /*  CNBCR22         */
     452
     453/* end of struct st_mlb_from_cecr0 */
     454
     455/* start of struct st_mlb_from_cecr0 */
     456    volatile uint32_t  CECR23;                                 /*  CECR23          */
     457    volatile uint32_t  CSCR23;                                 /*  CSCR23          */
     458    volatile uint32_t  CCBCR23;                                /*  CCBCR23         */
     459    volatile uint32_t  CNBCR23;                                /*  CNBCR23         */
     460
     461/* end of struct st_mlb_from_cecr0 */
     462
     463/* start of struct st_mlb_from_cecr0 */
     464    volatile uint32_t  CECR24;                                 /*  CECR24          */
     465    volatile uint32_t  CSCR24;                                 /*  CSCR24          */
     466    volatile uint32_t  CCBCR24;                                /*  CCBCR24         */
     467    volatile uint32_t  CNBCR24;                                /*  CNBCR24         */
     468
     469/* end of struct st_mlb_from_cecr0 */
     470
     471/* start of struct st_mlb_from_cecr0 */
     472    volatile uint32_t  CECR25;                                 /*  CECR25          */
     473    volatile uint32_t  CSCR25;                                 /*  CSCR25          */
     474    volatile uint32_t  CCBCR25;                                /*  CCBCR25         */
     475    volatile uint32_t  CNBCR25;                                /*  CNBCR25         */
     476
     477/* end of struct st_mlb_from_cecr0 */
     478
     479/* start of struct st_mlb_from_cecr0 */
     480    volatile uint32_t  CECR26;                                 /*  CECR26          */
     481    volatile uint32_t  CSCR26;                                 /*  CSCR26          */
     482    volatile uint32_t  CCBCR26;                                /*  CCBCR26         */
     483    volatile uint32_t  CNBCR26;                                /*  CNBCR26         */
     484
     485/* end of struct st_mlb_from_cecr0 */
     486
     487/* start of struct st_mlb_from_cecr0 */
     488    volatile uint32_t  CECR27;                                 /*  CECR27          */
     489    volatile uint32_t  CSCR27;                                 /*  CSCR27          */
     490    volatile uint32_t  CCBCR27;                                /*  CCBCR27         */
     491    volatile uint32_t  CNBCR27;                                /*  CNBCR27         */
     492
     493/* end of struct st_mlb_from_cecr0 */
     494
     495/* start of struct st_mlb_from_cecr0 */
     496    volatile uint32_t  CECR28;                                 /*  CECR28          */
     497    volatile uint32_t  CSCR28;                                 /*  CSCR28          */
     498    volatile uint32_t  CCBCR28;                                /*  CCBCR28         */
     499    volatile uint32_t  CNBCR28;                                /*  CNBCR28         */
     500
     501/* end of struct st_mlb_from_cecr0 */
     502
     503/* start of struct st_mlb_from_cecr0 */
     504    volatile uint32_t  CECR29;                                 /*  CECR29          */
     505    volatile uint32_t  CSCR29;                                 /*  CSCR29          */
     506    volatile uint32_t  CCBCR29;                                /*  CCBCR29         */
     507    volatile uint32_t  CNBCR29;                                /*  CNBCR29         */
     508
     509/* end of struct st_mlb_from_cecr0 */
     510
     511/* start of struct st_mlb_from_cecr0 */
     512    volatile uint32_t  CECR30;                                 /*  CECR30          */
     513    volatile uint32_t  CSCR30;                                 /*  CSCR30          */
     514    volatile uint32_t  CCBCR30;                                /*  CCBCR30         */
     515    volatile uint32_t  CNBCR30;                                /*  CNBCR30         */
     516
     517/* end of struct st_mlb_from_cecr0 */
     518    volatile uint8_t   dummy158[80];                           /*                  */
     519
     520/* #define MLB_LCBCR0_COUNT (31) */
     521    volatile uint32_t  LCBCR0;                                 /*  LCBCR0          */
     522    volatile uint32_t  LCBCR1;                                 /*  LCBCR1          */
     523    volatile uint32_t  LCBCR2;                                 /*  LCBCR2          */
     524    volatile uint32_t  LCBCR3;                                 /*  LCBCR3          */
     525    volatile uint32_t  LCBCR4;                                 /*  LCBCR4          */
     526    volatile uint32_t  LCBCR5;                                 /*  LCBCR5          */
     527    volatile uint32_t  LCBCR6;                                 /*  LCBCR6          */
     528    volatile uint32_t  LCBCR7;                                 /*  LCBCR7          */
     529    volatile uint32_t  LCBCR8;                                 /*  LCBCR8          */
     530    volatile uint32_t  LCBCR9;                                 /*  LCBCR9          */
     531    volatile uint32_t  LCBCR10;                                /*  LCBCR10         */
     532    volatile uint32_t  LCBCR11;                                /*  LCBCR11         */
     533    volatile uint32_t  LCBCR12;                                /*  LCBCR12         */
     534    volatile uint32_t  LCBCR13;                                /*  LCBCR13         */
     535    volatile uint32_t  LCBCR14;                                /*  LCBCR14         */
     536    volatile uint32_t  LCBCR15;                                /*  LCBCR15         */
     537    volatile uint32_t  LCBCR16;                                /*  LCBCR16         */
     538    volatile uint32_t  LCBCR17;                                /*  LCBCR17         */
     539    volatile uint32_t  LCBCR18;                                /*  LCBCR18         */
     540    volatile uint32_t  LCBCR19;                                /*  LCBCR19         */
     541    volatile uint32_t  LCBCR20;                                /*  LCBCR20         */
     542    volatile uint32_t  LCBCR21;                                /*  LCBCR21         */
     543    volatile uint32_t  LCBCR22;                                /*  LCBCR22         */
     544    volatile uint32_t  LCBCR23;                                /*  LCBCR23         */
     545    volatile uint32_t  LCBCR24;                                /*  LCBCR24         */
     546    volatile uint32_t  LCBCR25;                                /*  LCBCR25         */
     547    volatile uint32_t  LCBCR26;                                /*  LCBCR26         */
     548    volatile uint32_t  LCBCR27;                                /*  LCBCR27         */
     549    volatile uint32_t  LCBCR28;                                /*  LCBCR28         */
     550    volatile uint32_t  LCBCR29;                                /*  LCBCR29         */
     551    volatile uint32_t  LCBCR30;                                /*  LCBCR30         */
     552} r_io_mlb_t;
     553
     554
     555typedef struct st_mlb_from_cecr0
     556{
     557 
     558    volatile uint32_t  CECR0;                                  /*  CECR0           */
     559    volatile uint32_t  CSCR0;                                  /*  CSCR0           */
     560    volatile uint32_t  CCBCR0;                                 /*  CCBCR0          */
     561    volatile uint32_t  CNBCR0;                                 /*  CNBCR0          */
     562} r_io_mlb_from_cecr0_t;
     563
     564
     565/* Channel array defines of MLB (2)*/
     566#ifdef  DECLARE_MLB_FROM_CECR0_ARRAY_CHANNELS
     567volatile struct st_mlb_from_cecr0*  MLB_FROM_CECR0_ARRAY[ MLB_FROM_CECR0_ARRAY_COUNT ] =
     568    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     569    MLB_FROM_CECR0_ARRAY_ADDRESS_LIST;
     570    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     571#endif  /* DECLARE_MLB_FROM_CECR0_ARRAY_CHANNELS */
     572/* End of channel array defines of MLB (2)*/
     573
     574
    495575/* <-SEC M1.10.1 */
     576/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
    496577/* <-QAC 0857 */
    497578/* <-QAC 0639 */

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/mmc_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef MMC_IODEFINE_H
    3030#define MMC_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3134/* ->SEC M1.10.1 : Not magic number */
    3235
    33 struct st_mmc
    34 {                                                          /* MMC              */
     36#define MMC     (*(struct st_mmc     *)0xE804C800uL) /* MMC */
     37
     38
     39#define MMCCE_CMD_SETH (MMC.CE_CMD_SETH)
     40#define MMCCE_CMD_SETL (MMC.CE_CMD_SETL)
     41#define MMCCE_ARG (MMC.CE_ARG)
     42#define MMCCE_ARG_CMD12 (MMC.CE_ARG_CMD12)
     43#define MMCCE_CMD_CTRL (MMC.CE_CMD_CTRL)
     44#define MMCCE_BLOCK_SET (MMC.CE_BLOCK_SET)
     45#define MMCCE_CLK_CTRL (MMC.CE_CLK_CTRL)
     46#define MMCCE_BUF_ACC (MMC.CE_BUF_ACC)
     47#define MMCCE_RESP3 (MMC.CE_RESP3)
     48#define MMCCE_RESP2 (MMC.CE_RESP2)
     49#define MMCCE_RESP1 (MMC.CE_RESP1)
     50#define MMCCE_RESP0 (MMC.CE_RESP0)
     51#define MMCCE_RESP_CMD12 (MMC.CE_RESP_CMD12)
     52#define MMCCE_DATA (MMC.CE_DATA)
     53#define MMCCE_INT (MMC.CE_INT)
     54#define MMCCE_INT_EN (MMC.CE_INT_EN)
     55#define MMCCE_HOST_STS1 (MMC.CE_HOST_STS1)
     56#define MMCCE_HOST_STS2 (MMC.CE_HOST_STS2)
     57#define MMCCE_DMA_MODE (MMC.CE_DMA_MODE)
     58#define MMCCE_DETECT (MMC.CE_DETECT)
     59#define MMCCE_ADD_MODE (MMC.CE_ADD_MODE)
     60#define MMCCE_VERSION (MMC.CE_VERSION)
     61
     62#define MMC_CE_RESPn_COUNT (4)
     63
     64
     65typedef struct st_mmc
     66{
     67                                                           /* MMC              */
    3568    volatile uint16_t CE_CMD_SETH;                      /*  CE_CMD_SETH */
    3669    volatile uint16_t CE_CMD_SETL;                      /*  CE_CMD_SETL */
    … …  
    4275    volatile uint32_t  CE_CLK_CTRL;                            /*  CE_CLK_CTRL     */
    4376    volatile uint32_t  CE_BUF_ACC;                             /*  CE_BUF_ACC      */
    44 #define MMC_CE_RESPn_COUNT 4
     77
     78/* #define MMC_CE_RESPn_COUNT (4) */
    4579    volatile uint32_t  CE_RESP3;                               /*  CE_RESP3        */
    4680    volatile uint32_t  CE_RESP2;                               /*  CE_RESP2        */
    … …  
    6195    volatile uint8_t   dummy186[4];                            /*                  */
    6296    volatile uint32_t  CE_VERSION;                             /*  CE_VERSION      */
    63 };
     97} r_io_mmc_t;
    6498
    6599
    66 #define MMC     (*(struct st_mmc     *)0xE804C800uL) /* MMC */
    67 
    68 
    69 #define MMCCE_CMD_SETH MMC.CE_CMD_SETH
    70 #define MMCCE_CMD_SETL MMC.CE_CMD_SETL
    71 #define MMCCE_ARG MMC.CE_ARG
    72 #define MMCCE_ARG_CMD12 MMC.CE_ARG_CMD12
    73 #define MMCCE_CMD_CTRL MMC.CE_CMD_CTRL
    74 #define MMCCE_BLOCK_SET MMC.CE_BLOCK_SET
    75 #define MMCCE_CLK_CTRL MMC.CE_CLK_CTRL
    76 #define MMCCE_BUF_ACC MMC.CE_BUF_ACC
    77 #define MMCCE_RESP3 MMC.CE_RESP3
    78 #define MMCCE_RESP2 MMC.CE_RESP2
    79 #define MMCCE_RESP1 MMC.CE_RESP1
    80 #define MMCCE_RESP0 MMC.CE_RESP0
    81 #define MMCCE_RESP_CMD12 MMC.CE_RESP_CMD12
    82 #define MMCCE_DATA MMC.CE_DATA
    83 #define MMCCE_INT MMC.CE_INT
    84 #define MMCCE_INT_EN MMC.CE_INT_EN
    85 #define MMCCE_HOST_STS1 MMC.CE_HOST_STS1
    86 #define MMCCE_HOST_STS2 MMC.CE_HOST_STS2
    87 #define MMCCE_DMA_MODE MMC.CE_DMA_MODE
    88 #define MMCCE_DETECT MMC.CE_DETECT
    89 #define MMCCE_ADD_MODE MMC.CE_ADD_MODE
    90 #define MMCCE_VERSION MMC.CE_VERSION
    91100/* <-SEC M1.10.1 */
     101/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     102/* <-QAC 0857 */
     103/* <-QAC 0639 */
    92104#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef MTU2_IODEFINE_H
    3030#define MTU2_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3134/* ->SEC M1.10.1 : Not magic number */
    3235
    33 struct st_mtu2
    34 {                                                          /* MTU2             */
     36#define MTU2    (*(struct st_mtu2    *)0xFCFF0000uL) /* MTU2 */
     37
     38
     39#define MTU2TCR_2 (MTU2.TCR_2)
     40#define MTU2TMDR_2 (MTU2.TMDR_2)
     41#define MTU2TIOR_2 (MTU2.TIOR_2)
     42#define MTU2TIER_2 (MTU2.TIER_2)
     43#define MTU2TSR_2 (MTU2.TSR_2)
     44#define MTU2TCNT_2 (MTU2.TCNT_2)
     45#define MTU2TGRA_2 (MTU2.TGRA_2)
     46#define MTU2TGRB_2 (MTU2.TGRB_2)
     47#define MTU2TCR_3 (MTU2.TCR_3)
     48#define MTU2TCR_4 (MTU2.TCR_4)
     49#define MTU2TMDR_3 (MTU2.TMDR_3)
     50#define MTU2TMDR_4 (MTU2.TMDR_4)
     51#define MTU2TIORH_3 (MTU2.TIORH_3)
     52#define MTU2TIORL_3 (MTU2.TIORL_3)
     53#define MTU2TIORH_4 (MTU2.TIORH_4)
     54#define MTU2TIORL_4 (MTU2.TIORL_4)
     55#define MTU2TIER_3 (MTU2.TIER_3)
     56#define MTU2TIER_4 (MTU2.TIER_4)
     57#define MTU2TOER (MTU2.TOER)
     58#define MTU2TGCR (MTU2.TGCR)
     59#define MTU2TOCR1 (MTU2.TOCR1)
     60#define MTU2TOCR2 (MTU2.TOCR2)
     61#define MTU2TCNT_3 (MTU2.TCNT_3)
     62#define MTU2TCNT_4 (MTU2.TCNT_4)
     63#define MTU2TCDR (MTU2.TCDR)
     64#define MTU2TDDR (MTU2.TDDR)
     65#define MTU2TGRA_3 (MTU2.TGRA_3)
     66#define MTU2TGRB_3 (MTU2.TGRB_3)
     67#define MTU2TGRA_4 (MTU2.TGRA_4)
     68#define MTU2TGRB_4 (MTU2.TGRB_4)
     69#define MTU2TCNTS (MTU2.TCNTS)
     70#define MTU2TCBR (MTU2.TCBR)
     71#define MTU2TGRC_3 (MTU2.TGRC_3)
     72#define MTU2TGRD_3 (MTU2.TGRD_3)
     73#define MTU2TGRC_4 (MTU2.TGRC_4)
     74#define MTU2TGRD_4 (MTU2.TGRD_4)
     75#define MTU2TSR_3 (MTU2.TSR_3)
     76#define MTU2TSR_4 (MTU2.TSR_4)
     77#define MTU2TITCR (MTU2.TITCR)
     78#define MTU2TITCNT (MTU2.TITCNT)
     79#define MTU2TBTER (MTU2.TBTER)
     80#define MTU2TDER (MTU2.TDER)
     81#define MTU2TOLBR (MTU2.TOLBR)
     82#define MTU2TBTM_3 (MTU2.TBTM_3)
     83#define MTU2TBTM_4 (MTU2.TBTM_4)
     84#define MTU2TADCR (MTU2.TADCR)
     85#define MTU2TADCORA_4 (MTU2.TADCORA_4)
     86#define MTU2TADCORB_4 (MTU2.TADCORB_4)
     87#define MTU2TADCOBRA_4 (MTU2.TADCOBRA_4)
     88#define MTU2TADCOBRB_4 (MTU2.TADCOBRB_4)
     89#define MTU2TWCR (MTU2.TWCR)
     90#define MTU2TSTR (MTU2.TSTR)
     91#define MTU2TSYR (MTU2.TSYR)
     92#define MTU2TRWER (MTU2.TRWER)
     93#define MTU2TCR_0 (MTU2.TCR_0)
     94#define MTU2TMDR_0 (MTU2.TMDR_0)
     95#define MTU2TIORH_0 (MTU2.TIORH_0)
     96#define MTU2TIORL_0 (MTU2.TIORL_0)
     97#define MTU2TIER_0 (MTU2.TIER_0)
     98#define MTU2TSR_0 (MTU2.TSR_0)
     99#define MTU2TCNT_0 (MTU2.TCNT_0)
     100#define MTU2TGRA_0 (MTU2.TGRA_0)
     101#define MTU2TGRB_0 (MTU2.TGRB_0)
     102#define MTU2TGRC_0 (MTU2.TGRC_0)
     103#define MTU2TGRD_0 (MTU2.TGRD_0)
     104#define MTU2TGRE_0 (MTU2.TGRE_0)
     105#define MTU2TGRF_0 (MTU2.TGRF_0)
     106#define MTU2TIER2_0 (MTU2.TIER2_0)
     107#define MTU2TSR2_0 (MTU2.TSR2_0)
     108#define MTU2TBTM_0 (MTU2.TBTM_0)
     109#define MTU2TCR_1 (MTU2.TCR_1)
     110#define MTU2TMDR_1 (MTU2.TMDR_1)
     111#define MTU2TIOR_1 (MTU2.TIOR_1)
     112#define MTU2TIER_1 (MTU2.TIER_1)
     113#define MTU2TSR_1 (MTU2.TSR_1)
     114#define MTU2TCNT_1 (MTU2.TCNT_1)
     115#define MTU2TGRA_1 (MTU2.TGRA_1)
     116#define MTU2TGRB_1 (MTU2.TGRB_1)
     117#define MTU2TICCR (MTU2.TICCR)
     118
     119
     120typedef struct st_mtu2
     121{
     122                                                           /* MTU2             */
    35123    volatile uint8_t   TCR_2;                                  /*  TCR_2           */
    36124    volatile uint8_t   TMDR_2;                                 /*  TMDR_2          */
    … …  
    129217    volatile uint8_t   dummy536[4];                            /*                  */
    130218    volatile uint8_t   TICCR;                                  /*  TICCR           */
    131 };
    132 
    133 
    134 #define MTU2    (*(struct st_mtu2    *)0xFCFF0000uL) /* MTU2 */
    135 
    136 
    137 #define MTU2TCR_2 MTU2.TCR_2
    138 #define MTU2TMDR_2 MTU2.TMDR_2
    139 #define MTU2TIOR_2 MTU2.TIOR_2
    140 #define MTU2TIER_2 MTU2.TIER_2
    141 #define MTU2TSR_2 MTU2.TSR_2
    142 #define MTU2TCNT_2 MTU2.TCNT_2
    143 #define MTU2TGRA_2 MTU2.TGRA_2
    144 #define MTU2TGRB_2 MTU2.TGRB_2
    145 #define MTU2TCR_3 MTU2.TCR_3
    146 #define MTU2TCR_4 MTU2.TCR_4
    147 #define MTU2TMDR_3 MTU2.TMDR_3
    148 #define MTU2TMDR_4 MTU2.TMDR_4
    149 #define MTU2TIORH_3 MTU2.TIORH_3
    150 #define MTU2TIORL_3 MTU2.TIORL_3
    151 #define MTU2TIORH_4 MTU2.TIORH_4
    152 #define MTU2TIORL_4 MTU2.TIORL_4
    153 #define MTU2TIER_3 MTU2.TIER_3
    154 #define MTU2TIER_4 MTU2.TIER_4
    155 #define MTU2TOER MTU2.TOER
    156 #define MTU2TGCR MTU2.TGCR
    157 #define MTU2TOCR1 MTU2.TOCR1
    158 #define MTU2TOCR2 MTU2.TOCR2
    159 #define MTU2TCNT_3 MTU2.TCNT_3
    160 #define MTU2TCNT_4 MTU2.TCNT_4
    161 #define MTU2TCDR MTU2.TCDR
    162 #define MTU2TDDR MTU2.TDDR
    163 #define MTU2TGRA_3 MTU2.TGRA_3
    164 #define MTU2TGRB_3 MTU2.TGRB_3
    165 #define MTU2TGRA_4 MTU2.TGRA_4
    166 #define MTU2TGRB_4 MTU2.TGRB_4
    167 #define MTU2TCNTS MTU2.TCNTS
    168 #define MTU2TCBR MTU2.TCBR
    169 #define MTU2TGRC_3 MTU2.TGRC_3
    170 #define MTU2TGRD_3 MTU2.TGRD_3
    171 #define MTU2TGRC_4 MTU2.TGRC_4
    172 #define MTU2TGRD_4 MTU2.TGRD_4
    173 #define MTU2TSR_3 MTU2.TSR_3
    174 #define MTU2TSR_4 MTU2.TSR_4
    175 #define MTU2TITCR MTU2.TITCR
    176 #define MTU2TITCNT MTU2.TITCNT
    177 #define MTU2TBTER MTU2.TBTER
    178 #define MTU2TDER MTU2.TDER
    179 #define MTU2TOLBR MTU2.TOLBR
    180 #define MTU2TBTM_3 MTU2.TBTM_3
    181 #define MTU2TBTM_4 MTU2.TBTM_4
    182 #define MTU2TADCR MTU2.TADCR
    183 #define MTU2TADCORA_4 MTU2.TADCORA_4
    184 #define MTU2TADCORB_4 MTU2.TADCORB_4
    185 #define MTU2TADCOBRA_4 MTU2.TADCOBRA_4
    186 #define MTU2TADCOBRB_4 MTU2.TADCOBRB_4
    187 #define MTU2TWCR MTU2.TWCR
    188 #define MTU2TSTR MTU2.TSTR
    189 #define MTU2TSYR MTU2.TSYR
    190 #define MTU2TRWER MTU2.TRWER
    191 #define MTU2TCR_0 MTU2.TCR_0
    192 #define MTU2TMDR_0 MTU2.TMDR_0
    193 #define MTU2TIORH_0 MTU2.TIORH_0
    194 #define MTU2TIORL_0 MTU2.TIORL_0
    195 #define MTU2TIER_0 MTU2.TIER_0
    196 #define MTU2TSR_0 MTU2.TSR_0
    197 #define MTU2TCNT_0 MTU2.TCNT_0
    198 #define MTU2TGRA_0 MTU2.TGRA_0
    199 #define MTU2TGRB_0 MTU2.TGRB_0
    200 #define MTU2TGRC_0 MTU2.TGRC_0
    201 #define MTU2TGRD_0 MTU2.TGRD_0
    202 #define MTU2TGRE_0 MTU2.TGRE_0
    203 #define MTU2TGRF_0 MTU2.TGRF_0
    204 #define MTU2TIER2_0 MTU2.TIER2_0
    205 #define MTU2TSR2_0 MTU2.TSR2_0
    206 #define MTU2TBTM_0 MTU2.TBTM_0
    207 #define MTU2TCR_1 MTU2.TCR_1
    208 #define MTU2TMDR_1 MTU2.TMDR_1
    209 #define MTU2TIOR_1 MTU2.TIOR_1
    210 #define MTU2TIER_1 MTU2.TIER_1
    211 #define MTU2TSR_1 MTU2.TSR_1
    212 #define MTU2TCNT_1 MTU2.TCNT_1
    213 #define MTU2TGRA_1 MTU2.TGRA_1
    214 #define MTU2TGRB_1 MTU2.TGRB_1
    215 #define MTU2TICCR MTU2.TICCR
     219} r_io_mtu2_t;
     220
     221
    216222/* <-SEC M1.10.1 */
     223/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     224/* <-QAC 0857 */
     225/* <-QAC 0639 */
    217226#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/ostm_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef OSTM_IODEFINE_H
    3030#define OSTM_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3134/* ->SEC M1.10.1 : Not magic number */
    3235
    33 struct st_ostm
    34 {                                                          /* OSTM             */
     36#define OSTM0   (*(struct st_ostm    *)0xFCFEC000uL) /* OSTM0 */
     37#define OSTM1   (*(struct st_ostm    *)0xFCFEC400uL) /* OSTM1 */
     38
     39
     40/* Start of channel array defines of OSTM */
     41
     42/* Channel array defines of OSTM */
     43/*(Sample) value = OSTM[ channel ]->OSTMnCMP; */
     44#define OSTM_COUNT  (2)
     45#define OSTM_ADDRESS_LIST \
     46{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     47    &OSTM0, &OSTM1 \
     48}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     49
     50/* End of channel array defines of OSTM */
     51
     52
     53#define OSTM0CMP (OSTM0.OSTMnCMP)
     54#define OSTM0CNT (OSTM0.OSTMnCNT)
     55#define OSTM0TE (OSTM0.OSTMnTE)
     56#define OSTM0TS (OSTM0.OSTMnTS)
     57#define OSTM0TT (OSTM0.OSTMnTT)
     58#define OSTM0CTL (OSTM0.OSTMnCTL)
     59#define OSTM1CMP (OSTM1.OSTMnCMP)
     60#define OSTM1CNT (OSTM1.OSTMnCNT)
     61#define OSTM1TE (OSTM1.OSTMnTE)
     62#define OSTM1TS (OSTM1.OSTMnTS)
     63#define OSTM1TT (OSTM1.OSTMnTT)
     64#define OSTM1CTL (OSTM1.OSTMnCTL)
     65
     66
     67typedef struct st_ostm
     68{
     69                                                           /* OSTM             */
    3570    volatile uint32_t  OSTMnCMP;                               /*  OSTMnCMP        */
    3671    volatile uint32_t  OSTMnCNT;                               /*  OSTMnCNT        */
    … …  
    4378    volatile uint8_t   dummy4[7];                              /*                  */
    4479    volatile uint8_t   OSTMnCTL;                               /*  OSTMnCTL        */
    45 };
     80} r_io_ostm_t;
    4681
    4782
    48 #define OSTM0   (*(struct st_ostm    *)0xFCFEC000uL) /* OSTM0 */
    49 #define OSTM1   (*(struct st_ostm    *)0xFCFEC400uL) /* OSTM1 */
     83/* Channel array defines of OSTM (2)*/
     84#ifdef  DECLARE_OSTM_CHANNELS
     85volatile struct st_ostm*  OSTM[ OSTM_COUNT ] =
     86    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     87    OSTM_ADDRESS_LIST;
     88    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     89#endif  /* DECLARE_OSTM_CHANNELS */
     90/* End of channel array defines of OSTM (2)*/
    5091
    5192
    52 /* Start of channnel array defines of OSTM */
    53 
    54 /* Channnel array defines of OSTM */
    55 /*(Sample) value = OSTM[ channel ]->OSTMnCMP; */
    56 #define OSTM_COUNT  2
    57 #define OSTM_ADDRESS_LIST \
    58 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    59     &OSTM0, &OSTM1 \
    60 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    61 
    62 /* End of channnel array defines of OSTM */
    63 
    64 
    65 #define OSTM0CMP OSTM0.OSTMnCMP
    66 #define OSTM0CNT OSTM0.OSTMnCNT
    67 #define OSTM0TE OSTM0.OSTMnTE
    68 #define OSTM0TS OSTM0.OSTMnTS
    69 #define OSTM0TT OSTM0.OSTMnTT
    70 #define OSTM0CTL OSTM0.OSTMnCTL
    71 #define OSTM1CMP OSTM1.OSTMnCMP
    72 #define OSTM1CNT OSTM1.OSTMnCNT
    73 #define OSTM1TE OSTM1.OSTMnTE
    74 #define OSTM1TS OSTM1.OSTMnTS
    75 #define OSTM1TT OSTM1.OSTMnTT
    76 #define OSTM1CTL OSTM1.OSTMnCTL
    7793/* <-SEC M1.10.1 */
     94/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     95/* <-QAC 0857 */
     96/* <-QAC 0639 */
    7897#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/pfv_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef PFV_IODEFINE_H
    3030#define PFV_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3134/* ->SEC M1.10.1 : Not magic number */
    3235
    33 struct st_pfv
    34 {                                                          /* PFV              */
     36#define PFV0    (*(struct st_pfv     *)0xE8205000uL) /* PFV0 */
     37#define PFV1    (*(struct st_pfv     *)0xE8205800uL) /* PFV1 */
     38
     39
     40/* Start of channel array defines of PFV */
     41
     42/* Channel array defines of PFV */
     43/*(Sample) value = PFV[ channel ]->PFVCR; */
     44#define PFV_COUNT  (2)
     45#define PFV_ADDRESS_LIST \
     46{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     47    &PFV0, &PFV1 \
     48}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     49
     50/* End of channel array defines of PFV */
     51
     52
     53#define PFV0PFVCR (PFV0.PFVCR)
     54#define PFV0PFVICR (PFV0.PFVICR)
     55#define PFV0PFVISR (PFV0.PFVISR)
     56#define PFV0PFVID0 (PFV0.PFVID0)
     57#define PFV0PFVID1 (PFV0.PFVID1)
     58#define PFV0PFVID2 (PFV0.PFVID2)
     59#define PFV0PFVID3 (PFV0.PFVID3)
     60#define PFV0PFVID4 (PFV0.PFVID4)
     61#define PFV0PFVID5 (PFV0.PFVID5)
     62#define PFV0PFVID6 (PFV0.PFVID6)
     63#define PFV0PFVID7 (PFV0.PFVID7)
     64#define PFV0PFVOD0 (PFV0.PFVOD0)
     65#define PFV0PFVOD1 (PFV0.PFVOD1)
     66#define PFV0PFVOD2 (PFV0.PFVOD2)
     67#define PFV0PFVOD3 (PFV0.PFVOD3)
     68#define PFV0PFVOD4 (PFV0.PFVOD4)
     69#define PFV0PFVOD5 (PFV0.PFVOD5)
     70#define PFV0PFVOD6 (PFV0.PFVOD6)
     71#define PFV0PFVOD7 (PFV0.PFVOD7)
     72#define PFV0PFVIFSR (PFV0.PFVIFSR)
     73#define PFV0PFVOFSR (PFV0.PFVOFSR)
     74#define PFV0PFVACR (PFV0.PFVACR)
     75#define PFV0PFV_MTX_MODE (PFV0.PFV_MTX_MODE)
     76#define PFV0PFV_MTX_YG_ADJ0 (PFV0.PFV_MTX_YG_ADJ0)
     77#define PFV0PFV_MTX_YG_ADJ1 (PFV0.PFV_MTX_YG_ADJ1)
     78#define PFV0PFV_MTX_CBB_ADJ0 (PFV0.PFV_MTX_CBB_ADJ0)
     79#define PFV0PFV_MTX_CBB_ADJ1 (PFV0.PFV_MTX_CBB_ADJ1)
     80#define PFV0PFV_MTX_CRR_ADJ0 (PFV0.PFV_MTX_CRR_ADJ0)
     81#define PFV0PFV_MTX_CRR_ADJ1 (PFV0.PFV_MTX_CRR_ADJ1)
     82#define PFV0PFVSZR (PFV0.PFVSZR)
     83#define PFV1PFVCR (PFV1.PFVCR)
     84#define PFV1PFVICR (PFV1.PFVICR)
     85#define PFV1PFVISR (PFV1.PFVISR)
     86#define PFV1PFVID0 (PFV1.PFVID0)
     87#define PFV1PFVID1 (PFV1.PFVID1)
     88#define PFV1PFVID2 (PFV1.PFVID2)
     89#define PFV1PFVID3 (PFV1.PFVID3)
     90#define PFV1PFVID4 (PFV1.PFVID4)
     91#define PFV1PFVID5 (PFV1.PFVID5)
     92#define PFV1PFVID6 (PFV1.PFVID6)
     93#define PFV1PFVID7 (PFV1.PFVID7)
     94#define PFV1PFVOD0 (PFV1.PFVOD0)
     95#define PFV1PFVOD1 (PFV1.PFVOD1)
     96#define PFV1PFVOD2 (PFV1.PFVOD2)
     97#define PFV1PFVOD3 (PFV1.PFVOD3)
     98#define PFV1PFVOD4 (PFV1.PFVOD4)
     99#define PFV1PFVOD5 (PFV1.PFVOD5)
     100#define PFV1PFVOD6 (PFV1.PFVOD6)
     101#define PFV1PFVOD7 (PFV1.PFVOD7)
     102#define PFV1PFVIFSR (PFV1.PFVIFSR)
     103#define PFV1PFVOFSR (PFV1.PFVOFSR)
     104#define PFV1PFVACR (PFV1.PFVACR)
     105#define PFV1PFV_MTX_MODE (PFV1.PFV_MTX_MODE)
     106#define PFV1PFV_MTX_YG_ADJ0 (PFV1.PFV_MTX_YG_ADJ0)
     107#define PFV1PFV_MTX_YG_ADJ1 (PFV1.PFV_MTX_YG_ADJ1)
     108#define PFV1PFV_MTX_CBB_ADJ0 (PFV1.PFV_MTX_CBB_ADJ0)
     109#define PFV1PFV_MTX_CBB_ADJ1 (PFV1.PFV_MTX_CBB_ADJ1)
     110#define PFV1PFV_MTX_CRR_ADJ0 (PFV1.PFV_MTX_CRR_ADJ0)
     111#define PFV1PFV_MTX_CRR_ADJ1 (PFV1.PFV_MTX_CRR_ADJ1)
     112#define PFV1PFVSZR (PFV1.PFVSZR)
     113
     114#define PFVID_COUNT (8)
     115#define PFVOD_COUNT (8)
     116
     117
     118typedef struct st_pfv
     119{
     120                                                           /* PFV              */
    35121    volatile uint32_t  PFVCR;                                  /*  PFVCR           */
    36122    volatile uint32_t  PFVICR;                                 /*  PFVICR          */
    37123    volatile uint32_t  PFVISR;                                 /*  PFVISR          */
    38124    volatile uint8_t   dummy1[20];                             /*                  */
    39 #define PFVID_COUNT 8
     125
     126/* #define PFVID_COUNT (8) */
    40127    volatile uint32_t  PFVID0;                                 /*  PFVID0          */
    41128    volatile uint32_t  PFVID1;                                 /*  PFVID1          */
    … …  
    46133    volatile uint32_t  PFVID6;                                 /*  PFVID6          */
    47134    volatile uint32_t  PFVID7;                                 /*  PFVID7          */
    48 #define PFVOD_COUNT 8
     135
     136/* #define PFVOD_COUNT (8) */
    49137    volatile uint32_t  PFVOD0;                                 /*  PFVOD0          */
    50138    volatile uint32_t  PFVOD1;                                 /*  PFVOD1          */
    … …  
    67155    volatile uint32_t  PFV_MTX_CRR_ADJ1;                       /*  PFV_MTX_CRR_ADJ1 */
    68156    volatile uint32_t  PFVSZR;                                 /*  PFVSZR          */
    69 };
     157} r_io_pfv_t;
    70158
    71159
    72 #define PFV0    (*(struct st_pfv     *)0xE8205000uL) /* PFV0 */
    73 #define PFV1    (*(struct st_pfv     *)0xE8205800uL) /* PFV1 */
     160/* Channel array defines of PFV (2)*/
     161#ifdef  DECLARE_PFV_CHANNELS
     162volatile struct st_pfv*  PFV[ PFV_COUNT ] =
     163    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     164    PFV_ADDRESS_LIST;
     165    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     166#endif  /* DECLARE_PFV_CHANNELS */
     167/* End of channel array defines of PFV (2)*/
    74168
    75169
    76 /* Start of channnel array defines of PFV */
    77 
    78 /* Channnel array defines of PFV */
    79 /*(Sample) value = PFV[ channel ]->PFVCR; */
    80 #define PFV_COUNT  2
    81 #define PFV_ADDRESS_LIST \
    82 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    83     &PFV0, &PFV1 \
    84 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    85 
    86 /* End of channnel array defines of PFV */
    87 
    88 
    89 #define PFV0PFVCR PFV0.PFVCR
    90 #define PFV0PFVICR PFV0.PFVICR
    91 #define PFV0PFVISR PFV0.PFVISR
    92 #define PFV0PFVID0 PFV0.PFVID0
    93 #define PFV0PFVID1 PFV0.PFVID1
    94 #define PFV0PFVID2 PFV0.PFVID2
    95 #define PFV0PFVID3 PFV0.PFVID3
    96 #define PFV0PFVID4 PFV0.PFVID4
    97 #define PFV0PFVID5 PFV0.PFVID5
    98 #define PFV0PFVID6 PFV0.PFVID6
    99 #define PFV0PFVID7 PFV0.PFVID7
    100 #define PFV0PFVOD0 PFV0.PFVOD0
    101 #define PFV0PFVOD1 PFV0.PFVOD1
    102 #define PFV0PFVOD2 PFV0.PFVOD2
    103 #define PFV0PFVOD3 PFV0.PFVOD3
    104 #define PFV0PFVOD4 PFV0.PFVOD4
    105 #define PFV0PFVOD5 PFV0.PFVOD5
    106 #define PFV0PFVOD6 PFV0.PFVOD6
    107 #define PFV0PFVOD7 PFV0.PFVOD7
    108 #define PFV0PFVIFSR PFV0.PFVIFSR
    109 #define PFV0PFVOFSR PFV0.PFVOFSR
    110 #define PFV0PFVACR PFV0.PFVACR
    111 #define PFV0PFV_MTX_MODE PFV0.PFV_MTX_MODE
    112 #define PFV0PFV_MTX_YG_ADJ0 PFV0.PFV_MTX_YG_ADJ0
    113 #define PFV0PFV_MTX_YG_ADJ1 PFV0.PFV_MTX_YG_ADJ1
    114 #define PFV0PFV_MTX_CBB_ADJ0 PFV0.PFV_MTX_CBB_ADJ0
    115 #define PFV0PFV_MTX_CBB_ADJ1 PFV0.PFV_MTX_CBB_ADJ1
    116 #define PFV0PFV_MTX_CRR_ADJ0 PFV0.PFV_MTX_CRR_ADJ0
    117 #define PFV0PFV_MTX_CRR_ADJ1 PFV0.PFV_MTX_CRR_ADJ1
    118 #define PFV0PFVSZR PFV0.PFVSZR
    119 #define PFV1PFVCR PFV1.PFVCR
    120 #define PFV1PFVICR PFV1.PFVICR
    121 #define PFV1PFVISR PFV1.PFVISR
    122 #define PFV1PFVID0 PFV1.PFVID0
    123 #define PFV1PFVID1 PFV1.PFVID1
    124 #define PFV1PFVID2 PFV1.PFVID2
    125 #define PFV1PFVID3 PFV1.PFVID3
    126 #define PFV1PFVID4 PFV1.PFVID4
    127 #define PFV1PFVID5 PFV1.PFVID5
    128 #define PFV1PFVID6 PFV1.PFVID6
    129 #define PFV1PFVID7 PFV1.PFVID7
    130 #define PFV1PFVOD0 PFV1.PFVOD0
    131 #define PFV1PFVOD1 PFV1.PFVOD1
    132 #define PFV1PFVOD2 PFV1.PFVOD2
    133 #define PFV1PFVOD3 PFV1.PFVOD3
    134 #define PFV1PFVOD4 PFV1.PFVOD4
    135 #define PFV1PFVOD5 PFV1.PFVOD5
    136 #define PFV1PFVOD6 PFV1.PFVOD6
    137 #define PFV1PFVOD7 PFV1.PFVOD7
    138 #define PFV1PFVIFSR PFV1.PFVIFSR
    139 #define PFV1PFVOFSR PFV1.PFVOFSR
    140 #define PFV1PFVACR PFV1.PFVACR
    141 #define PFV1PFV_MTX_MODE PFV1.PFV_MTX_MODE
    142 #define PFV1PFV_MTX_YG_ADJ0 PFV1.PFV_MTX_YG_ADJ0
    143 #define PFV1PFV_MTX_YG_ADJ1 PFV1.PFV_MTX_YG_ADJ1
    144 #define PFV1PFV_MTX_CBB_ADJ0 PFV1.PFV_MTX_CBB_ADJ0
    145 #define PFV1PFV_MTX_CBB_ADJ1 PFV1.PFV_MTX_CBB_ADJ1
    146 #define PFV1PFV_MTX_CRR_ADJ0 PFV1.PFV_MTX_CRR_ADJ0
    147 #define PFV1PFV_MTX_CRR_ADJ1 PFV1.PFV_MTX_CRR_ADJ1
    148 #define PFV1PFVSZR PFV1.PFVSZR
    149170/* <-SEC M1.10.1 */
     171/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     172/* <-QAC 0857 */
     173/* <-QAC 0639 */
    150174#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/pwm_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef PWM_IODEFINE_H
    3030#define PWM_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
    3133/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3234/* ->SEC M1.10.1 : Not magic number */
    33 
    34 union reg16_8_t
    35 {
    36     volatile uint16_t  UINT16;                                  /*  16-bit Access   */
    37     volatile uint8_t   UINT8[2];                                /*  8-bit Access    */
    38 };
    39 
    40 struct st_pwm
    41 {                                                          /* PWM              */
    42     volatile uint8_t   dummy559[2];                            /*                  */
    43     union reg16_8_t  PWBTCR;                          /*  PWBTCR      */
    44    
    45     volatile uint8_t   dummy560[216];                          /*                  */
    46    
    47 /* start of struct st_pwm_common */
    48     union reg16_8_t  PWCR_1;                          /*  PWCR_1      */
    49    
    50     volatile uint8_t   dummy561[2];                            /*                  */
    51     union reg16_8_t  PWPR_1;                          /*  PWPR_1      */
    52    
    53     volatile uint16_t PWCYR_1;                                /*  PWCYR_1         */
    54     volatile uint16_t PWBFR_1A;                               /*  PWBFR_1A        */
    55     volatile uint16_t PWBFR_1C;                               /*  PWBFR_1C        */
    56     volatile uint16_t PWBFR_1E;                               /*  PWBFR_1E        */
    57     volatile uint16_t PWBFR_1G;                               /*  PWBFR_1G        */
    58 /* end of struct st_pwm_common */
    59    
    60 /* start of struct st_pwm_common */
    61     union reg16_8_t  PWCR_2;                          /*  PWCR_2      */
    62    
    63     volatile uint8_t   dummy562[2];                            /*                  */
    64     union reg16_8_t  PWPR_2;                          /*  PWPR_2      */
    65    
    66     volatile uint16_t PWCYR_2;                                /*  PWCYR_2         */
    67     volatile uint16_t PWBFR_2A;                               /*  PWBFR_2A        */
    68     volatile uint16_t PWBFR_2C;                               /*  PWBFR_2C        */
    69     volatile uint16_t PWBFR_2E;                               /*  PWBFR_2E        */
    70     volatile uint16_t PWBFR_2G;                               /*  PWBFR_2G        */
    71 /* end of struct st_pwm_common */
    72 };
    73 
    74 
    75 struct st_pwm_common
    76 {
    77     union reg16_8_t  PWCR_1;                          /*  PWCR_1      */
    78    
    79     volatile uint8_t   dummy572[2];                            /*                  */
    80     union reg16_8_t  PWPR_1;                          /*  PWPR_1      */
    81    
    82     volatile uint16_t PWCYR_1;                                /*  PWCYR_1         */
    83     volatile uint16_t PWBFR_1A;                               /*  PWBFR_1A        */
    84     volatile uint16_t PWBFR_1C;                               /*  PWBFR_1C        */
    85     volatile uint16_t PWBFR_1E;                               /*  PWBFR_1E        */
    86     volatile uint16_t PWBFR_1G;                               /*  PWBFR_1G        */
    87 };
    88 
    8935
    9036#define PWM     (*(struct st_pwm     *)0xFCFF5004uL) /* PWM */
    9137
    9238
    93 /* Start of channnel array defines of PWM */
     39/* Start of channel array defines of PWM */
    9440
    95 /* Channnel array defines of PWMn */
    96 /*(Sample) value = PWMn[ channel ]->PWCR_1.UINT16; */
    97 #define PWMn_COUNT  2
     41/* Channel array defines of PWMn */
     42/*(Sample) value = PWMn[ channel ]->PWCR_1; */
     43#define PWMn_COUNT  (2)
    9844#define PWMn_ADDRESS_LIST \
    9945{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    … …  
    10349#define PWM2    (*(struct st_pwm_common *)&PWM.PWCR_2)           /* PWM2 */
    10450
    105 /* End of channnel array defines of PWM */
     51/* End of channel array defines of PWM */
    10652
    10753
    108 #define PWMPWBTCR PWM.PWBTCR.UINT16
    109 #define PWMPWBTCR_BYTE_L PWM.PWBTCR.UINT8[0]
    110 #define PWMPWBTCR_BYTE_H PWM.PWBTCR.UINT8[1]
    111 #define PWMPWCR_1 PWM.PWCR_1.UINT16
    112 #define PWMPWCR_1_BYTE_L PWM.PWCR_1.UINT8[0]
    113 #define PWMPWCR_1_BYTE_H PWM.PWCR_1.UINT8[1]
    114 #define PWMPWPR_1 PWM.PWPR_1.UINT16
    115 #define PWMPWPR_1_BYTE_L PWM.PWPR_1.UINT8[0]
    116 #define PWMPWPR_1_BYTE_H PWM.PWPR_1.UINT8[1]
    117 #define PWMPWCYR_1 PWM.PWCYR_1
    118 #define PWMPWBFR_1A PWM.PWBFR_1A
    119 #define PWMPWBFR_1C PWM.PWBFR_1C
    120 #define PWMPWBFR_1E PWM.PWBFR_1E
    121 #define PWMPWBFR_1G PWM.PWBFR_1G
    122 #define PWMPWCR_2 PWM.PWCR_2.UINT16
    123 #define PWMPWCR_2_BYTE_L PWM.PWCR_2.UINT8[0]
    124 #define PWMPWCR_2_BYTE_H PWM.PWCR_2.UINT8[1]
    125 #define PWMPWPR_2 PWM.PWPR_2.UINT16
    126 #define PWMPWPR_2_BYTE_L PWM.PWPR_2.UINT8[0]
    127 #define PWMPWPR_2_BYTE_H PWM.PWPR_2.UINT8[1]
    128 #define PWMPWCYR_2 PWM.PWCYR_2
    129 #define PWMPWBFR_2A PWM.PWBFR_2A
    130 #define PWMPWBFR_2C PWM.PWBFR_2C
    131 #define PWMPWBFR_2E PWM.PWBFR_2E
    132 #define PWMPWBFR_2G PWM.PWBFR_2G
     54#define PWMPWBTCR (PWM.PWBTCR)
     55#define PWMPWCR_1 (PWM.PWCR_1)
     56#define PWMPWPR_1 (PWM.PWPR_1)
     57#define PWMPWCYR_1 (PWM.PWCYR_1)
     58#define PWMPWBFR_1A (PWM.PWBFR_1A)
     59#define PWMPWBFR_1C (PWM.PWBFR_1C)
     60#define PWMPWBFR_1E (PWM.PWBFR_1E)
     61#define PWMPWBFR_1G (PWM.PWBFR_1G)
     62#define PWMPWCR_2 (PWM.PWCR_2)
     63#define PWMPWPR_2 (PWM.PWPR_2)
     64#define PWMPWCYR_2 (PWM.PWCYR_2)
     65#define PWMPWBFR_2A (PWM.PWBFR_2A)
     66#define PWMPWBFR_2C (PWM.PWBFR_2C)
     67#define PWMPWBFR_2E (PWM.PWBFR_2E)
     68#define PWMPWBFR_2G (PWM.PWBFR_2G)
     69
     70
     71typedef struct st_pwm
     72{
     73                                                           /* PWM              */
     74    volatile uint8_t   dummy559[2];                            /*                  */
     75    volatile uint8_t   PWBTCR;                                 /*  PWBTCR          */
     76    volatile uint8_t   dummy560[217];                          /*                  */
     77
     78/* start of struct st_pwm_common */
     79    volatile uint8_t   PWCR_1;                                 /*  PWCR_1          */
     80    volatile uint8_t   dummy561[3];                            /*                  */
     81    volatile uint8_t   PWPR_1;                                 /*  PWPR_1          */
     82    volatile uint8_t   dummy562[1];                            /*                  */
     83    volatile uint16_t PWCYR_1;                                /*  PWCYR_1         */
     84    volatile uint16_t PWBFR_1A;                               /*  PWBFR_1A        */
     85    volatile uint16_t PWBFR_1C;                               /*  PWBFR_1C        */
     86    volatile uint16_t PWBFR_1E;                               /*  PWBFR_1E        */
     87    volatile uint16_t PWBFR_1G;                               /*  PWBFR_1G        */
     88
     89/* end of struct st_pwm_common */
     90
     91/* start of struct st_pwm_common */
     92    volatile uint8_t   PWCR_2;                                 /*  PWCR_2          */
     93    volatile uint8_t   dummy563[3];                            /*                  */
     94    volatile uint8_t   PWPR_2;                                 /*  PWPR_2          */
     95    volatile uint8_t   dummy564[1];                            /*                  */
     96    volatile uint16_t PWCYR_2;                                /*  PWCYR_2         */
     97    volatile uint16_t PWBFR_2A;                               /*  PWBFR_2A        */
     98    volatile uint16_t PWBFR_2C;                               /*  PWBFR_2C        */
     99    volatile uint16_t PWBFR_2E;                               /*  PWBFR_2E        */
     100    volatile uint16_t PWBFR_2G;                               /*  PWBFR_2G        */
     101
     102/* end of struct st_pwm_common */
     103} r_io_pwm_t;
     104
     105
     106typedef struct st_pwm_common
     107{
     108 
     109    volatile uint8_t   PWCR_1;                                 /*  PWCR_1          */
     110    volatile uint8_t   dummy562[3];                            /*                  */
     111    volatile uint8_t   PWPR_1;                                 /*  PWPR_1          */
     112    volatile uint8_t   dummy563[1];                            /*                  */
     113    volatile uint16_t PWCYR_1;                                /*  PWCYR_1         */
     114    volatile uint16_t PWBFR_1A;                               /*  PWBFR_1A        */
     115    volatile uint16_t PWBFR_1C;                               /*  PWBFR_1C        */
     116    volatile uint16_t PWBFR_1E;                               /*  PWBFR_1E        */
     117    volatile uint16_t PWBFR_1G;                               /*  PWBFR_1G        */
     118} r_io_pwm_common_t;
     119
     120
     121/* Channel array defines of PWMn (2)*/
     122#ifdef  DECLARE_PWMn_CHANNELS
     123volatile struct st_pwm_common*  PWMn[ PWMn_COUNT ] =
     124    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     125    PWMn_ADDRESS_LIST;
     126    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     127#endif  /* DECLARE_PWMn_CHANNELS */
     128/* End of channel array defines of PWMn (2)*/
     129
     130
    133131/* <-SEC M1.10.1 */
    134132/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     133/* <-QAC 0857 */
     134/* <-QAC 0639 */
    135135#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/riic_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef RIIC_IODEFINE_H
    3030#define RIIC_IODEFINE_H
    31 
    32 #include "reg32_t.h"
    33 
    34 struct st_riic
    35 {                                                          /* RIIC             */
    36 #define RIICnCRm_COUNT 2
    37     union reg32_t  RIICnCR1;                      /*  RIICnCR1        */
    38     union reg32_t  RIICnCR2;                      /*  RIICnCR2        */
    39 #define RIICnMRm_COUNT 3
    40     union reg32_t  RIICnMR1;                      /*  RIICnMR1        */
    41     union reg32_t  RIICnMR2;                      /*  RIICnMR2        */
    42     union reg32_t  RIICnMR3;                      /*  RIICnMR3        */
    43     union reg32_t  RIICnFER;                      /*  RIICnFER        */
    44     union reg32_t  RIICnSER;                      /*  RIICnSER        */
    45     union reg32_t  RIICnIER;                      /*  RIICnIER        */
    46 #define RIICnSRm_COUNT 2
    47     union reg32_t  RIICnSR1;                      /*  RIICnSR1        */
    48     union reg32_t  RIICnSR2;                      /*  RIICnSR2        */
    49 #define RIICnSARm_COUNT 3
    50     union reg32_t  RIICnSAR0;                     /*  RIICnSAR0       */
    51     union reg32_t  RIICnSAR1;                     /*  RIICnSAR1       */
    52     union reg32_t  RIICnSAR2;                     /*  RIICnSAR2       */
    53     union reg32_t  RIICnBRL;                      /*  RIICnBRL        */
    54     union reg32_t  RIICnBRH;                      /*  RIICnBRH        */
    55     union reg32_t  RIICnDRT;                      /*  RIICnDRT        */
    56     union reg32_t  RIICnDRR;                      /*  RIICnDRR        */
    57    
    58 };
    59 
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
     34/* ->SEC M1.10.1 : Not magic number */
    6035
    6136#define RIIC0   (*(struct st_riic    *)0xFCFEE000uL) /* RIIC0 */
    … …  
    6540
    6641
    67 /* Start of channnel array defines of RIIC */
    68 
    69 /* Channnel array defines of RIIC */
     42/* Start of channel array defines of RIIC */
     43
     44/* Channel array defines of RIIC */
    7045/*(Sample) value = RIIC[ channel ]->RIICnCR1.UINT32; */
    71 #define RIIC_COUNT  4
     46#define RIIC_COUNT  (4)
    7247#define RIIC_ADDRESS_LIST \
    7348{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    … …  
    7550}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    7651
    77 /* End of channnel array defines of RIIC */
    78 
    79 
    80 #define RIIC0CR1 RIIC0.RIICnCR1.UINT32
    81 #define RIIC0CR1L RIIC0.RIICnCR1.UINT16[L]
    82 #define RIIC0CR1LL RIIC0.RIICnCR1.UINT8[LL]
    83 #define RIIC0CR1LH RIIC0.RIICnCR1.UINT8[LH]
    84 #define RIIC0CR1H RIIC0.RIICnCR1.UINT16[H]
    85 #define RIIC0CR1HL RIIC0.RIICnCR1.UINT8[HL]
    86 #define RIIC0CR1HH RIIC0.RIICnCR1.UINT8[HH]
    87 #define RIIC0CR2 RIIC0.RIICnCR2.UINT32
    88 #define RIIC0CR2L RIIC0.RIICnCR2.UINT16[L]
    89 #define RIIC0CR2LL RIIC0.RIICnCR2.UINT8[LL]
    90 #define RIIC0CR2LH RIIC0.RIICnCR2.UINT8[LH]
    91 #define RIIC0CR2H RIIC0.RIICnCR2.UINT16[H]
    92 #define RIIC0CR2HL RIIC0.RIICnCR2.UINT8[HL]
    93 #define RIIC0CR2HH RIIC0.RIICnCR2.UINT8[HH]
    94 #define RIIC0MR1 RIIC0.RIICnMR1.UINT32
    95 #define RIIC0MR1L RIIC0.RIICnMR1.UINT16[L]
    96 #define RIIC0MR1LL RIIC0.RIICnMR1.UINT8[LL]
    97 #define RIIC0MR1LH RIIC0.RIICnMR1.UINT8[LH]
    98 #define RIIC0MR1H RIIC0.RIICnMR1.UINT16[H]
    99 #define RIIC0MR1HL RIIC0.RIICnMR1.UINT8[HL]
    100 #define RIIC0MR1HH RIIC0.RIICnMR1.UINT8[HH]
    101 #define RIIC0MR2 RIIC0.RIICnMR2.UINT32
    102 #define RIIC0MR2L RIIC0.RIICnMR2.UINT16[L]
    103 #define RIIC0MR2LL RIIC0.RIICnMR2.UINT8[LL]
    104 #define RIIC0MR2LH RIIC0.RIICnMR2.UINT8[LH]
    105 #define RIIC0MR2H RIIC0.RIICnMR2.UINT16[H]
    106 #define RIIC0MR2HL RIIC0.RIICnMR2.UINT8[HL]
    107 #define RIIC0MR2HH RIIC0.RIICnMR2.UINT8[HH]
    108 #define RIIC0MR3 RIIC0.RIICnMR3.UINT32
    109 #define RIIC0MR3L RIIC0.RIICnMR3.UINT16[L]
    110 #define RIIC0MR3LL RIIC0.RIICnMR3.UINT8[LL]
    111 #define RIIC0MR3LH RIIC0.RIICnMR3.UINT8[LH]
    112 #define RIIC0MR3H RIIC0.RIICnMR3.UINT16[H]
    113 #define RIIC0MR3HL RIIC0.RIICnMR3.UINT8[HL]
    114 #define RIIC0MR3HH RIIC0.RIICnMR3.UINT8[HH]
    115 #define RIIC0FER RIIC0.RIICnFER.UINT32
    116 #define RIIC0FERL RIIC0.RIICnFER.UINT16[L]
    117 #define RIIC0FERLL RIIC0.RIICnFER.UINT8[LL]
    118 #define RIIC0FERLH RIIC0.RIICnFER.UINT8[LH]
    119 #define RIIC0FERH RIIC0.RIICnFER.UINT16[H]
    120 #define RIIC0FERHL RIIC0.RIICnFER.UINT8[HL]
    121 #define RIIC0FERHH RIIC0.RIICnFER.UINT8[HH]
    122 #define RIIC0SER RIIC0.RIICnSER.UINT32
    123 #define RIIC0SERL RIIC0.RIICnSER.UINT16[L]
    124 #define RIIC0SERLL RIIC0.RIICnSER.UINT8[LL]
    125 #define RIIC0SERLH RIIC0.RIICnSER.UINT8[LH]
    126 #define RIIC0SERH RIIC0.RIICnSER.UINT16[H]
    127 #define RIIC0SERHL RIIC0.RIICnSER.UINT8[HL]
    128 #define RIIC0SERHH RIIC0.RIICnSER.UINT8[HH]
    129 #define RIIC0IER RIIC0.RIICnIER.UINT32
    130 #define RIIC0IERL RIIC0.RIICnIER.UINT16[L]
    131 #define RIIC0IERLL RIIC0.RIICnIER.UINT8[LL]
    132 #define RIIC0IERLH RIIC0.RIICnIER.UINT8[LH]
    133 #define RIIC0IERH RIIC0.RIICnIER.UINT16[H]
    134 #define RIIC0IERHL RIIC0.RIICnIER.UINT8[HL]
    135 #define RIIC0IERHH RIIC0.RIICnIER.UINT8[HH]
    136 #define RIIC0SR1 RIIC0.RIICnSR1.UINT32
    137 #define RIIC0SR1L RIIC0.RIICnSR1.UINT16[L]
    138 #define RIIC0SR1LL RIIC0.RIICnSR1.UINT8[LL]
    139 #define RIIC0SR1LH RIIC0.RIICnSR1.UINT8[LH]
    140 #define RIIC0SR1H RIIC0.RIICnSR1.UINT16[H]
    141 #define RIIC0SR1HL RIIC0.RIICnSR1.UINT8[HL]
    142 #define RIIC0SR1HH RIIC0.RIICnSR1.UINT8[HH]
    143 #define RIIC0SR2 RIIC0.RIICnSR2.UINT32
    144 #define RIIC0SR2L RIIC0.RIICnSR2.UINT16[L]
    145 #define RIIC0SR2LL RIIC0.RIICnSR2.UINT8[LL]
    146 #define RIIC0SR2LH RIIC0.RIICnSR2.UINT8[LH]
    147 #define RIIC0SR2H RIIC0.RIICnSR2.UINT16[H]
    148 #define RIIC0SR2HL RIIC0.RIICnSR2.UINT8[HL]
    149 #define RIIC0SR2HH RIIC0.RIICnSR2.UINT8[HH]
    150 #define RIIC0SAR0 RIIC0.RIICnSAR0.UINT32
    151 #define RIIC0SAR0L RIIC0.RIICnSAR0.UINT16[L]
    152 #define RIIC0SAR0LL RIIC0.RIICnSAR0.UINT8[LL]
    153 #define RIIC0SAR0LH RIIC0.RIICnSAR0.UINT8[LH]
    154 #define RIIC0SAR0H RIIC0.RIICnSAR0.UINT16[H]
    155 #define RIIC0SAR0HL RIIC0.RIICnSAR0.UINT8[HL]
    156 #define RIIC0SAR0HH RIIC0.RIICnSAR0.UINT8[HH]
    157 #define RIIC0SAR1 RIIC0.RIICnSAR1.UINT32
    158 #define RIIC0SAR1L RIIC0.RIICnSAR1.UINT16[L]
    159 #define RIIC0SAR1LL RIIC0.RIICnSAR1.UINT8[LL]
    160 #define RIIC0SAR1LH RIIC0.RIICnSAR1.UINT8[LH]
    161 #define RIIC0SAR1H RIIC0.RIICnSAR1.UINT16[H]
    162 #define RIIC0SAR1HL RIIC0.RIICnSAR1.UINT8[HL]
    163 #define RIIC0SAR1HH RIIC0.RIICnSAR1.UINT8[HH]
    164 #define RIIC0SAR2 RIIC0.RIICnSAR2.UINT32
    165 #define RIIC0SAR2L RIIC0.RIICnSAR2.UINT16[L]
    166 #define RIIC0SAR2LL RIIC0.RIICnSAR2.UINT8[LL]
    167 #define RIIC0SAR2LH RIIC0.RIICnSAR2.UINT8[LH]
    168 #define RIIC0SAR2H RIIC0.RIICnSAR2.UINT16[H]
    169 #define RIIC0SAR2HL RIIC0.RIICnSAR2.UINT8[HL]
    170 #define RIIC0SAR2HH RIIC0.RIICnSAR2.UINT8[HH]
    171 #define RIIC0BRL RIIC0.RIICnBRL.UINT32
    172 #define RIIC0BRLL RIIC0.RIICnBRL.UINT16[L]
    173 #define RIIC0BRLLL RIIC0.RIICnBRL.UINT8[LL]
    174 #define RIIC0BRLLH RIIC0.RIICnBRL.UINT8[LH]
    175 #define RIIC0BRLH RIIC0.RIICnBRL.UINT16[H]
    176 #define RIIC0BRLHL RIIC0.RIICnBRL.UINT8[HL]
    177 #define RIIC0BRLHH RIIC0.RIICnBRL.UINT8[HH]
    178 #define RIIC0BRH RIIC0.RIICnBRH.UINT32
    179 #define RIIC0BRHL RIIC0.RIICnBRH.UINT16[L]
    180 #define RIIC0BRHLL RIIC0.RIICnBRH.UINT8[LL]
    181 #define RIIC0BRHLH RIIC0.RIICnBRH.UINT8[LH]
    182 #define RIIC0BRHH RIIC0.RIICnBRH.UINT16[H]
    183 #define RIIC0BRHHL RIIC0.RIICnBRH.UINT8[HL]
    184 #define RIIC0BRHHH RIIC0.RIICnBRH.UINT8[HH]
    185 #define RIIC0DRT RIIC0.RIICnDRT.UINT32
    186 #define RIIC0DRTL RIIC0.RIICnDRT.UINT16[L]
    187 #define RIIC0DRTLL RIIC0.RIICnDRT.UINT8[LL]
    188 #define RIIC0DRTLH RIIC0.RIICnDRT.UINT8[LH]
    189 #define RIIC0DRTH RIIC0.RIICnDRT.UINT16[H]
    190 #define RIIC0DRTHL RIIC0.RIICnDRT.UINT8[HL]
    191 #define RIIC0DRTHH RIIC0.RIICnDRT.UINT8[HH]
    192 #define RIIC0DRR RIIC0.RIICnDRR.UINT32
    193 #define RIIC0DRRL RIIC0.RIICnDRR.UINT16[L]
    194 #define RIIC0DRRLL RIIC0.RIICnDRR.UINT8[LL]
    195 #define RIIC0DRRLH RIIC0.RIICnDRR.UINT8[LH]
    196 #define RIIC0DRRH RIIC0.RIICnDRR.UINT16[H]
    197 #define RIIC0DRRHL RIIC0.RIICnDRR.UINT8[HL]
    198 #define RIIC0DRRHH RIIC0.RIICnDRR.UINT8[HH]
    199 #define RIIC1CR1 RIIC1.RIICnCR1.UINT32
    200 #define RIIC1CR1L RIIC1.RIICnCR1.UINT16[L]
    201 #define RIIC1CR1LL RIIC1.RIICnCR1.UINT8[LL]
    202 #define RIIC1CR1LH RIIC1.RIICnCR1.UINT8[LH]
    203 #define RIIC1CR1H RIIC1.RIICnCR1.UINT16[H]
    204 #define RIIC1CR1HL RIIC1.RIICnCR1.UINT8[HL]
    205 #define RIIC1CR1HH RIIC1.RIICnCR1.UINT8[HH]
    206 #define RIIC1CR2 RIIC1.RIICnCR2.UINT32
    207 #define RIIC1CR2L RIIC1.RIICnCR2.UINT16[L]
    208 #define RIIC1CR2LL RIIC1.RIICnCR2.UINT8[LL]
    209 #define RIIC1CR2LH RIIC1.RIICnCR2.UINT8[LH]
    210 #define RIIC1CR2H RIIC1.RIICnCR2.UINT16[H]
    211 #define RIIC1CR2HL RIIC1.RIICnCR2.UINT8[HL]
    212 #define RIIC1CR2HH RIIC1.RIICnCR2.UINT8[HH]
    213 #define RIIC1MR1 RIIC1.RIICnMR1.UINT32
    214 #define RIIC1MR1L RIIC1.RIICnMR1.UINT16[L]
    215 #define RIIC1MR1LL RIIC1.RIICnMR1.UINT8[LL]
    216 #define RIIC1MR1LH RIIC1.RIICnMR1.UINT8[LH]
    217 #define RIIC1MR1H RIIC1.RIICnMR1.UINT16[H]
    218 #define RIIC1MR1HL RIIC1.RIICnMR1.UINT8[HL]
    219 #define RIIC1MR1HH RIIC1.RIICnMR1.UINT8[HH]
    220 #define RIIC1MR2 RIIC1.RIICnMR2.UINT32
    221 #define RIIC1MR2L RIIC1.RIICnMR2.UINT16[L]
    222 #define RIIC1MR2LL RIIC1.RIICnMR2.UINT8[LL]
    223 #define RIIC1MR2LH RIIC1.RIICnMR2.UINT8[LH]
    224 #define RIIC1MR2H RIIC1.RIICnMR2.UINT16[H]
    225 #define RIIC1MR2HL RIIC1.RIICnMR2.UINT8[HL]
    226 #define RIIC1MR2HH RIIC1.RIICnMR2.UINT8[HH]
    227 #define RIIC1MR3 RIIC1.RIICnMR3.UINT32
    228 #define RIIC1MR3L RIIC1.RIICnMR3.UINT16[L]
    229 #define RIIC1MR3LL RIIC1.RIICnMR3.UINT8[LL]
    230 #define RIIC1MR3LH RIIC1.RIICnMR3.UINT8[LH]
    231 #define RIIC1MR3H RIIC1.RIICnMR3.UINT16[H]
    232 #define RIIC1MR3HL RIIC1.RIICnMR3.UINT8[HL]
    233 #define RIIC1MR3HH RIIC1.RIICnMR3.UINT8[HH]
    234 #define RIIC1FER RIIC1.RIICnFER.UINT32
    235 #define RIIC1FERL RIIC1.RIICnFER.UINT16[L]
    236 #define RIIC1FERLL RIIC1.RIICnFER.UINT8[LL]
    237 #define RIIC1FERLH RIIC1.RIICnFER.UINT8[LH]
    238 #define RIIC1FERH RIIC1.RIICnFER.UINT16[H]
    239 #define RIIC1FERHL RIIC1.RIICnFER.UINT8[HL]
    240 #define RIIC1FERHH RIIC1.RIICnFER.UINT8[HH]
    241 #define RIIC1SER RIIC1.RIICnSER.UINT32
    242 #define RIIC1SERL RIIC1.RIICnSER.UINT16[L]
    243 #define RIIC1SERLL RIIC1.RIICnSER.UINT8[LL]
    244 #define RIIC1SERLH RIIC1.RIICnSER.UINT8[LH]
    245 #define RIIC1SERH RIIC1.RIICnSER.UINT16[H]
    246 #define RIIC1SERHL RIIC1.RIICnSER.UINT8[HL]
    247 #define RIIC1SERHH RIIC1.RIICnSER.UINT8[HH]
    248 #define RIIC1IER RIIC1.RIICnIER.UINT32
    249 #define RIIC1IERL RIIC1.RIICnIER.UINT16[L]
    250 #define RIIC1IERLL RIIC1.RIICnIER.UINT8[LL]
    251 #define RIIC1IERLH RIIC1.RIICnIER.UINT8[LH]
    252 #define RIIC1IERH RIIC1.RIICnIER.UINT16[H]
    253 #define RIIC1IERHL RIIC1.RIICnIER.UINT8[HL]
    254 #define RIIC1IERHH RIIC1.RIICnIER.UINT8[HH]
    255 #define RIIC1SR1 RIIC1.RIICnSR1.UINT32
    256 #define RIIC1SR1L RIIC1.RIICnSR1.UINT16[L]
    257 #define RIIC1SR1LL RIIC1.RIICnSR1.UINT8[LL]
    258 #define RIIC1SR1LH RIIC1.RIICnSR1.UINT8[LH]
    259 #define RIIC1SR1H RIIC1.RIICnSR1.UINT16[H]
    260 #define RIIC1SR1HL RIIC1.RIICnSR1.UINT8[HL]
    261 #define RIIC1SR1HH RIIC1.RIICnSR1.UINT8[HH]
    262 #define RIIC1SR2 RIIC1.RIICnSR2.UINT32
    263 #define RIIC1SR2L RIIC1.RIICnSR2.UINT16[L]
    264 #define RIIC1SR2LL RIIC1.RIICnSR2.UINT8[LL]
    265 #define RIIC1SR2LH RIIC1.RIICnSR2.UINT8[LH]
    266 #define RIIC1SR2H RIIC1.RIICnSR2.UINT16[H]
    267 #define RIIC1SR2HL RIIC1.RIICnSR2.UINT8[HL]
    268 #define RIIC1SR2HH RIIC1.RIICnSR2.UINT8[HH]
    269 #define RIIC1SAR0 RIIC1.RIICnSAR0.UINT32
    270 #define RIIC1SAR0L RIIC1.RIICnSAR0.UINT16[L]
    271 #define RIIC1SAR0LL RIIC1.RIICnSAR0.UINT8[LL]
    272 #define RIIC1SAR0LH RIIC1.RIICnSAR0.UINT8[LH]
    273 #define RIIC1SAR0H RIIC1.RIICnSAR0.UINT16[H]
    274 #define RIIC1SAR0HL RIIC1.RIICnSAR0.UINT8[HL]
    275 #define RIIC1SAR0HH RIIC1.RIICnSAR0.UINT8[HH]
    276 #define RIIC1SAR1 RIIC1.RIICnSAR1.UINT32
    277 #define RIIC1SAR1L RIIC1.RIICnSAR1.UINT16[L]
    278 #define RIIC1SAR1LL RIIC1.RIICnSAR1.UINT8[LL]
    279 #define RIIC1SAR1LH RIIC1.RIICnSAR1.UINT8[LH]
    280 #define RIIC1SAR1H RIIC1.RIICnSAR1.UINT16[H]
    281 #define RIIC1SAR1HL RIIC1.RIICnSAR1.UINT8[HL]
    282 #define RIIC1SAR1HH RIIC1.RIICnSAR1.UINT8[HH]
    283 #define RIIC1SAR2 RIIC1.RIICnSAR2.UINT32
    284 #define RIIC1SAR2L RIIC1.RIICnSAR2.UINT16[L]
    285 #define RIIC1SAR2LL RIIC1.RIICnSAR2.UINT8[LL]
    286 #define RIIC1SAR2LH RIIC1.RIICnSAR2.UINT8[LH]
    287 #define RIIC1SAR2H RIIC1.RIICnSAR2.UINT16[H]
    288 #define RIIC1SAR2HL RIIC1.RIICnSAR2.UINT8[HL]
    289 #define RIIC1SAR2HH RIIC1.RIICnSAR2.UINT8[HH]
    290 #define RIIC1BRL RIIC1.RIICnBRL.UINT32
    291 #define RIIC1BRLL RIIC1.RIICnBRL.UINT16[L]
    292 #define RIIC1BRLLL RIIC1.RIICnBRL.UINT8[LL]
    293 #define RIIC1BRLLH RIIC1.RIICnBRL.UINT8[LH]
    294 #define RIIC1BRLH RIIC1.RIICnBRL.UINT16[H]
    295 #define RIIC1BRLHL RIIC1.RIICnBRL.UINT8[HL]
    296 #define RIIC1BRLHH RIIC1.RIICnBRL.UINT8[HH]
    297 #define RIIC1BRH RIIC1.RIICnBRH.UINT32
    298 #define RIIC1BRHL RIIC1.RIICnBRH.UINT16[L]
    299 #define RIIC1BRHLL RIIC1.RIICnBRH.UINT8[LL]
    300 #define RIIC1BRHLH RIIC1.RIICnBRH.UINT8[LH]
    301 #define RIIC1BRHH RIIC1.RIICnBRH.UINT16[H]
    302 #define RIIC1BRHHL RIIC1.RIICnBRH.UINT8[HL]
    303 #define RIIC1BRHHH RIIC1.RIICnBRH.UINT8[HH]
    304 #define RIIC1DRT RIIC1.RIICnDRT.UINT32
    305 #define RIIC1DRTL RIIC1.RIICnDRT.UINT16[L]
    306 #define RIIC1DRTLL RIIC1.RIICnDRT.UINT8[LL]
    307 #define RIIC1DRTLH RIIC1.RIICnDRT.UINT8[LH]
    308 #define RIIC1DRTH RIIC1.RIICnDRT.UINT16[H]
    309 #define RIIC1DRTHL RIIC1.RIICnDRT.UINT8[HL]
    310 #define RIIC1DRTHH RIIC1.RIICnDRT.UINT8[HH]
    311 #define RIIC1DRR RIIC1.RIICnDRR.UINT32
    312 #define RIIC1DRRL RIIC1.RIICnDRR.UINT16[L]
    313 #define RIIC1DRRLL RIIC1.RIICnDRR.UINT8[LL]
    314 #define RIIC1DRRLH RIIC1.RIICnDRR.UINT8[LH]
    315 #define RIIC1DRRH RIIC1.RIICnDRR.UINT16[H]
    316 #define RIIC1DRRHL RIIC1.RIICnDRR.UINT8[HL]
    317 #define RIIC1DRRHH RIIC1.RIICnDRR.UINT8[HH]
    318 #define RIIC2CR1 RIIC2.RIICnCR1.UINT32
    319 #define RIIC2CR1L RIIC2.RIICnCR1.UINT16[L]
    320 #define RIIC2CR1LL RIIC2.RIICnCR1.UINT8[LL]
    321 #define RIIC2CR1LH RIIC2.RIICnCR1.UINT8[LH]
    322 #define RIIC2CR1H RIIC2.RIICnCR1.UINT16[H]
    323 #define RIIC2CR1HL RIIC2.RIICnCR1.UINT8[HL]
    324 #define RIIC2CR1HH RIIC2.RIICnCR1.UINT8[HH]
    325 #define RIIC2CR2 RIIC2.RIICnCR2.UINT32
    326 #define RIIC2CR2L RIIC2.RIICnCR2.UINT16[L]
    327 #define RIIC2CR2LL RIIC2.RIICnCR2.UINT8[LL]
    328 #define RIIC2CR2LH RIIC2.RIICnCR2.UINT8[LH]
    329 #define RIIC2CR2H RIIC2.RIICnCR2.UINT16[H]
    330 #define RIIC2CR2HL RIIC2.RIICnCR2.UINT8[HL]
    331 #define RIIC2CR2HH RIIC2.RIICnCR2.UINT8[HH]
    332 #define RIIC2MR1 RIIC2.RIICnMR1.UINT32
    333 #define RIIC2MR1L RIIC2.RIICnMR1.UINT16[L]
    334 #define RIIC2MR1LL RIIC2.RIICnMR1.UINT8[LL]
    335 #define RIIC2MR1LH RIIC2.RIICnMR1.UINT8[LH]
    336 #define RIIC2MR1H RIIC2.RIICnMR1.UINT16[H]
    337 #define RIIC2MR1HL RIIC2.RIICnMR1.UINT8[HL]
    338 #define RIIC2MR1HH RIIC2.RIICnMR1.UINT8[HH]
    339 #define RIIC2MR2 RIIC2.RIICnMR2.UINT32
    340 #define RIIC2MR2L RIIC2.RIICnMR2.UINT16[L]
    341 #define RIIC2MR2LL RIIC2.RIICnMR2.UINT8[LL]
    342 #define RIIC2MR2LH RIIC2.RIICnMR2.UINT8[LH]
    343 #define RIIC2MR2H RIIC2.RIICnMR2.UINT16[H]
    344 #define RIIC2MR2HL RIIC2.RIICnMR2.UINT8[HL]
    345 #define RIIC2MR2HH RIIC2.RIICnMR2.UINT8[HH]
    346 #define RIIC2MR3 RIIC2.RIICnMR3.UINT32
    347 #define RIIC2MR3L RIIC2.RIICnMR3.UINT16[L]
    348 #define RIIC2MR3LL RIIC2.RIICnMR3.UINT8[LL]
    349 #define RIIC2MR3LH RIIC2.RIICnMR3.UINT8[LH]
    350 #define RIIC2MR3H RIIC2.RIICnMR3.UINT16[H]
    351 #define RIIC2MR3HL RIIC2.RIICnMR3.UINT8[HL]
    352 #define RIIC2MR3HH RIIC2.RIICnMR3.UINT8[HH]
    353 #define RIIC2FER RIIC2.RIICnFER.UINT32
    354 #define RIIC2FERL RIIC2.RIICnFER.UINT16[L]
    355 #define RIIC2FERLL RIIC2.RIICnFER.UINT8[LL]
    356 #define RIIC2FERLH RIIC2.RIICnFER.UINT8[LH]
    357 #define RIIC2FERH RIIC2.RIICnFER.UINT16[H]
    358 #define RIIC2FERHL RIIC2.RIICnFER.UINT8[HL]
    359 #define RIIC2FERHH RIIC2.RIICnFER.UINT8[HH]
    360 #define RIIC2SER RIIC2.RIICnSER.UINT32
    361 #define RIIC2SERL RIIC2.RIICnSER.UINT16[L]
    362 #define RIIC2SERLL RIIC2.RIICnSER.UINT8[LL]
    363 #define RIIC2SERLH RIIC2.RIICnSER.UINT8[LH]
    364 #define RIIC2SERH RIIC2.RIICnSER.UINT16[H]
    365 #define RIIC2SERHL RIIC2.RIICnSER.UINT8[HL]
    366 #define RIIC2SERHH RIIC2.RIICnSER.UINT8[HH]
    367 #define RIIC2IER RIIC2.RIICnIER.UINT32
    368 #define RIIC2IERL RIIC2.RIICnIER.UINT16[L]
    369 #define RIIC2IERLL RIIC2.RIICnIER.UINT8[LL]
    370 #define RIIC2IERLH RIIC2.RIICnIER.UINT8[LH]
    371 #define RIIC2IERH RIIC2.RIICnIER.UINT16[H]
    372 #define RIIC2IERHL RIIC2.RIICnIER.UINT8[HL]
    373 #define RIIC2IERHH RIIC2.RIICnIER.UINT8[HH]
    374 #define RIIC2SR1 RIIC2.RIICnSR1.UINT32
    375 #define RIIC2SR1L RIIC2.RIICnSR1.UINT16[L]
    376 #define RIIC2SR1LL RIIC2.RIICnSR1.UINT8[LL]
    377 #define RIIC2SR1LH RIIC2.RIICnSR1.UINT8[LH]
    378 #define RIIC2SR1H RIIC2.RIICnSR1.UINT16[H]
    379 #define RIIC2SR1HL RIIC2.RIICnSR1.UINT8[HL]
    380 #define RIIC2SR1HH RIIC2.RIICnSR1.UINT8[HH]
    381 #define RIIC2SR2 RIIC2.RIICnSR2.UINT32
    382 #define RIIC2SR2L RIIC2.RIICnSR2.UINT16[L]
    383 #define RIIC2SR2LL RIIC2.RIICnSR2.UINT8[LL]
    384 #define RIIC2SR2LH RIIC2.RIICnSR2.UINT8[LH]
    385 #define RIIC2SR2H RIIC2.RIICnSR2.UINT16[H]
    386 #define RIIC2SR2HL RIIC2.RIICnSR2.UINT8[HL]
    387 #define RIIC2SR2HH RIIC2.RIICnSR2.UINT8[HH]
    388 #define RIIC2SAR0 RIIC2.RIICnSAR0.UINT32
    389 #define RIIC2SAR0L RIIC2.RIICnSAR0.UINT16[L]
    390 #define RIIC2SAR0LL RIIC2.RIICnSAR0.UINT8[LL]
    391 #define RIIC2SAR0LH RIIC2.RIICnSAR0.UINT8[LH]
    392 #define RIIC2SAR0H RIIC2.RIICnSAR0.UINT16[H]
    393 #define RIIC2SAR0HL RIIC2.RIICnSAR0.UINT8[HL]
    394 #define RIIC2SAR0HH RIIC2.RIICnSAR0.UINT8[HH]
    395 #define RIIC2SAR1 RIIC2.RIICnSAR1.UINT32
    396 #define RIIC2SAR1L RIIC2.RIICnSAR1.UINT16[L]
    397 #define RIIC2SAR1LL RIIC2.RIICnSAR1.UINT8[LL]
    398 #define RIIC2SAR1LH RIIC2.RIICnSAR1.UINT8[LH]
    399 #define RIIC2SAR1H RIIC2.RIICnSAR1.UINT16[H]
    400 #define RIIC2SAR1HL RIIC2.RIICnSAR1.UINT8[HL]
    401 #define RIIC2SAR1HH RIIC2.RIICnSAR1.UINT8[HH]
    402 #define RIIC2SAR2 RIIC2.RIICnSAR2.UINT32
    403 #define RIIC2SAR2L RIIC2.RIICnSAR2.UINT16[L]
    404 #define RIIC2SAR2LL RIIC2.RIICnSAR2.UINT8[LL]
    405 #define RIIC2SAR2LH RIIC2.RIICnSAR2.UINT8[LH]
    406 #define RIIC2SAR2H RIIC2.RIICnSAR2.UINT16[H]
    407 #define RIIC2SAR2HL RIIC2.RIICnSAR2.UINT8[HL]
    408 #define RIIC2SAR2HH RIIC2.RIICnSAR2.UINT8[HH]
    409 #define RIIC2BRL RIIC2.RIICnBRL.UINT32
    410 #define RIIC2BRLL RIIC2.RIICnBRL.UINT16[L]
    411 #define RIIC2BRLLL RIIC2.RIICnBRL.UINT8[LL]
    412 #define RIIC2BRLLH RIIC2.RIICnBRL.UINT8[LH]
    413 #define RIIC2BRLH RIIC2.RIICnBRL.UINT16[H]
    414 #define RIIC2BRLHL RIIC2.RIICnBRL.UINT8[HL]
    415 #define RIIC2BRLHH RIIC2.RIICnBRL.UINT8[HH]
    416 #define RIIC2BRH RIIC2.RIICnBRH.UINT32
    417 #define RIIC2BRHL RIIC2.RIICnBRH.UINT16[L]
    418 #define RIIC2BRHLL RIIC2.RIICnBRH.UINT8[LL]
    419 #define RIIC2BRHLH RIIC2.RIICnBRH.UINT8[LH]
    420 #define RIIC2BRHH RIIC2.RIICnBRH.UINT16[H]
    421 #define RIIC2BRHHL RIIC2.RIICnBRH.UINT8[HL]
    422 #define RIIC2BRHHH RIIC2.RIICnBRH.UINT8[HH]
    423 #define RIIC2DRT RIIC2.RIICnDRT.UINT32
    424 #define RIIC2DRTL RIIC2.RIICnDRT.UINT16[L]
    425 #define RIIC2DRTLL RIIC2.RIICnDRT.UINT8[LL]
    426 #define RIIC2DRTLH RIIC2.RIICnDRT.UINT8[LH]
    427 #define RIIC2DRTH RIIC2.RIICnDRT.UINT16[H]
    428 #define RIIC2DRTHL RIIC2.RIICnDRT.UINT8[HL]
    429 #define RIIC2DRTHH RIIC2.RIICnDRT.UINT8[HH]
    430 #define RIIC2DRR RIIC2.RIICnDRR.UINT32
    431 #define RIIC2DRRL RIIC2.RIICnDRR.UINT16[L]
    432 #define RIIC2DRRLL RIIC2.RIICnDRR.UINT8[LL]
    433 #define RIIC2DRRLH RIIC2.RIICnDRR.UINT8[LH]
    434 #define RIIC2DRRH RIIC2.RIICnDRR.UINT16[H]
    435 #define RIIC2DRRHL RIIC2.RIICnDRR.UINT8[HL]
    436 #define RIIC2DRRHH RIIC2.RIICnDRR.UINT8[HH]
    437 #define RIIC3CR1 RIIC3.RIICnCR1.UINT32
    438 #define RIIC3CR1L RIIC3.RIICnCR1.UINT16[L]
    439 #define RIIC3CR1LL RIIC3.RIICnCR1.UINT8[LL]
    440 #define RIIC3CR1LH RIIC3.RIICnCR1.UINT8[LH]
    441 #define RIIC3CR1H RIIC3.RIICnCR1.UINT16[H]
    442 #define RIIC3CR1HL RIIC3.RIICnCR1.UINT8[HL]
    443 #define RIIC3CR1HH RIIC3.RIICnCR1.UINT8[HH]
    444 #define RIIC3CR2 RIIC3.RIICnCR2.UINT32
    445 #define RIIC3CR2L RIIC3.RIICnCR2.UINT16[L]
    446 #define RIIC3CR2LL RIIC3.RIICnCR2.UINT8[LL]
    447 #define RIIC3CR2LH RIIC3.RIICnCR2.UINT8[LH]
    448 #define RIIC3CR2H RIIC3.RIICnCR2.UINT16[H]
    449 #define RIIC3CR2HL RIIC3.RIICnCR2.UINT8[HL]
    450 #define RIIC3CR2HH RIIC3.RIICnCR2.UINT8[HH]
    451 #define RIIC3MR1 RIIC3.RIICnMR1.UINT32
    452 #define RIIC3MR1L RIIC3.RIICnMR1.UINT16[L]
    453 #define RIIC3MR1LL RIIC3.RIICnMR1.UINT8[LL]
    454 #define RIIC3MR1LH RIIC3.RIICnMR1.UINT8[LH]
    455 #define RIIC3MR1H RIIC3.RIICnMR1.UINT16[H]
    456 #define RIIC3MR1HL RIIC3.RIICnMR1.UINT8[HL]
    457 #define RIIC3MR1HH RIIC3.RIICnMR1.UINT8[HH]
    458 #define RIIC3MR2 RIIC3.RIICnMR2.UINT32
    459 #define RIIC3MR2L RIIC3.RIICnMR2.UINT16[L]
    460 #define RIIC3MR2LL RIIC3.RIICnMR2.UINT8[LL]
    461 #define RIIC3MR2LH RIIC3.RIICnMR2.UINT8[LH]
    462 #define RIIC3MR2H RIIC3.RIICnMR2.UINT16[H]
    463 #define RIIC3MR2HL RIIC3.RIICnMR2.UINT8[HL]
    464 #define RIIC3MR2HH RIIC3.RIICnMR2.UINT8[HH]
    465 #define RIIC3MR3 RIIC3.RIICnMR3.UINT32
    466 #define RIIC3MR3L RIIC3.RIICnMR3.UINT16[L]
    467 #define RIIC3MR3LL RIIC3.RIICnMR3.UINT8[LL]
    468 #define RIIC3MR3LH RIIC3.RIICnMR3.UINT8[LH]
    469 #define RIIC3MR3H RIIC3.RIICnMR3.UINT16[H]
    470 #define RIIC3MR3HL RIIC3.RIICnMR3.UINT8[HL]
    471 #define RIIC3MR3HH RIIC3.RIICnMR3.UINT8[HH]
    472 #define RIIC3FER RIIC3.RIICnFER.UINT32
    473 #define RIIC3FERL RIIC3.RIICnFER.UINT16[L]
    474 #define RIIC3FERLL RIIC3.RIICnFER.UINT8[LL]
    475 #define RIIC3FERLH RIIC3.RIICnFER.UINT8[LH]
    476 #define RIIC3FERH RIIC3.RIICnFER.UINT16[H]
    477 #define RIIC3FERHL RIIC3.RIICnFER.UINT8[HL]
    478 #define RIIC3FERHH RIIC3.RIICnFER.UINT8[HH]
    479 #define RIIC3SER RIIC3.RIICnSER.UINT32
    480 #define RIIC3SERL RIIC3.RIICnSER.UINT16[L]
    481 #define RIIC3SERLL RIIC3.RIICnSER.UINT8[LL]
    482 #define RIIC3SERLH RIIC3.RIICnSER.UINT8[LH]
    483 #define RIIC3SERH RIIC3.RIICnSER.UINT16[H]
    484 #define RIIC3SERHL RIIC3.RIICnSER.UINT8[HL]
    485 #define RIIC3SERHH RIIC3.RIICnSER.UINT8[HH]
    486 #define RIIC3IER RIIC3.RIICnIER.UINT32
    487 #define RIIC3IERL RIIC3.RIICnIER.UINT16[L]
    488 #define RIIC3IERLL RIIC3.RIICnIER.UINT8[LL]
    489 #define RIIC3IERLH RIIC3.RIICnIER.UINT8[LH]
    490 #define RIIC3IERH RIIC3.RIICnIER.UINT16[H]
    491 #define RIIC3IERHL RIIC3.RIICnIER.UINT8[HL]
    492 #define RIIC3IERHH RIIC3.RIICnIER.UINT8[HH]
    493 #define RIIC3SR1 RIIC3.RIICnSR1.UINT32
    494 #define RIIC3SR1L RIIC3.RIICnSR1.UINT16[L]
    495 #define RIIC3SR1LL RIIC3.RIICnSR1.UINT8[LL]
    496 #define RIIC3SR1LH RIIC3.RIICnSR1.UINT8[LH]
    497 #define RIIC3SR1H RIIC3.RIICnSR1.UINT16[H]
    498 #define RIIC3SR1HL RIIC3.RIICnSR1.UINT8[HL]
    499 #define RIIC3SR1HH RIIC3.RIICnSR1.UINT8[HH]
    500 #define RIIC3SR2 RIIC3.RIICnSR2.UINT32
    501 #define RIIC3SR2L RIIC3.RIICnSR2.UINT16[L]
    502 #define RIIC3SR2LL RIIC3.RIICnSR2.UINT8[LL]
    503 #define RIIC3SR2LH RIIC3.RIICnSR2.UINT8[LH]
    504 #define RIIC3SR2H RIIC3.RIICnSR2.UINT16[H]
    505 #define RIIC3SR2HL RIIC3.RIICnSR2.UINT8[HL]
    506 #define RIIC3SR2HH RIIC3.RIICnSR2.UINT8[HH]
    507 #define RIIC3SAR0 RIIC3.RIICnSAR0.UINT32
    508 #define RIIC3SAR0L RIIC3.RIICnSAR0.UINT16[L]
    509 #define RIIC3SAR0LL RIIC3.RIICnSAR0.UINT8[LL]
    510 #define RIIC3SAR0LH RIIC3.RIICnSAR0.UINT8[LH]
    511 #define RIIC3SAR0H RIIC3.RIICnSAR0.UINT16[H]
    512 #define RIIC3SAR0HL RIIC3.RIICnSAR0.UINT8[HL]
    513 #define RIIC3SAR0HH RIIC3.RIICnSAR0.UINT8[HH]
    514 #define RIIC3SAR1 RIIC3.RIICnSAR1.UINT32
    515 #define RIIC3SAR1L RIIC3.RIICnSAR1.UINT16[L]
    516 #define RIIC3SAR1LL RIIC3.RIICnSAR1.UINT8[LL]
    517 #define RIIC3SAR1LH RIIC3.RIICnSAR1.UINT8[LH]
    518 #define RIIC3SAR1H RIIC3.RIICnSAR1.UINT16[H]
    519 #define RIIC3SAR1HL RIIC3.RIICnSAR1.UINT8[HL]
    520 #define RIIC3SAR1HH RIIC3.RIICnSAR1.UINT8[HH]
    521 #define RIIC3SAR2 RIIC3.RIICnSAR2.UINT32
    522 #define RIIC3SAR2L RIIC3.RIICnSAR2.UINT16[L]
    523 #define RIIC3SAR2LL RIIC3.RIICnSAR2.UINT8[LL]
    524 #define RIIC3SAR2LH RIIC3.RIICnSAR2.UINT8[LH]
    525 #define RIIC3SAR2H RIIC3.RIICnSAR2.UINT16[H]
    526 #define RIIC3SAR2HL RIIC3.RIICnSAR2.UINT8[HL]
    527 #define RIIC3SAR2HH RIIC3.RIICnSAR2.UINT8[HH]
    528 #define RIIC3BRL RIIC3.RIICnBRL.UINT32
    529 #define RIIC3BRLL RIIC3.RIICnBRL.UINT16[L]
    530 #define RIIC3BRLLL RIIC3.RIICnBRL.UINT8[LL]
    531 #define RIIC3BRLLH RIIC3.RIICnBRL.UINT8[LH]
    532 #define RIIC3BRLH RIIC3.RIICnBRL.UINT16[H]
    533 #define RIIC3BRLHL RIIC3.RIICnBRL.UINT8[HL]
    534 #define RIIC3BRLHH RIIC3.RIICnBRL.UINT8[HH]
    535 #define RIIC3BRH RIIC3.RIICnBRH.UINT32
    536 #define RIIC3BRHL RIIC3.RIICnBRH.UINT16[L]
    537 #define RIIC3BRHLL RIIC3.RIICnBRH.UINT8[LL]
    538 #define RIIC3BRHLH RIIC3.RIICnBRH.UINT8[LH]
    539 #define RIIC3BRHH RIIC3.RIICnBRH.UINT16[H]
    540 #define RIIC3BRHHL RIIC3.RIICnBRH.UINT8[HL]
    541 #define RIIC3BRHHH RIIC3.RIICnBRH.UINT8[HH]
    542 #define RIIC3DRT RIIC3.RIICnDRT.UINT32
    543 #define RIIC3DRTL RIIC3.RIICnDRT.UINT16[L]
    544 #define RIIC3DRTLL RIIC3.RIICnDRT.UINT8[LL]
    545 #define RIIC3DRTLH RIIC3.RIICnDRT.UINT8[LH]
    546 #define RIIC3DRTH RIIC3.RIICnDRT.UINT16[H]
    547 #define RIIC3DRTHL RIIC3.RIICnDRT.UINT8[HL]
    548 #define RIIC3DRTHH RIIC3.RIICnDRT.UINT8[HH]
    549 #define RIIC3DRR RIIC3.RIICnDRR.UINT32
    550 #define RIIC3DRRL RIIC3.RIICnDRR.UINT16[L]
    551 #define RIIC3DRRLL RIIC3.RIICnDRR.UINT8[LL]
    552 #define RIIC3DRRLH RIIC3.RIICnDRR.UINT8[LH]
    553 #define RIIC3DRRH RIIC3.RIICnDRR.UINT16[H]
    554 #define RIIC3DRRHL RIIC3.RIICnDRR.UINT8[HL]
    555 #define RIIC3DRRHH RIIC3.RIICnDRR.UINT8[HH]
     52/* End of channel array defines of RIIC */
     53
     54
     55#define RIIC0CR1 (RIIC0.RIICnCR1.UINT32)
     56#define RIIC0CR1L (RIIC0.RIICnCR1.UINT16[R_IO_L])
     57#define RIIC0CR1LL (RIIC0.RIICnCR1.UINT8[R_IO_LL])
     58#define RIIC0CR1LH (RIIC0.RIICnCR1.UINT8[R_IO_LH])
     59#define RIIC0CR1H (RIIC0.RIICnCR1.UINT16[R_IO_H])
     60#define RIIC0CR1HL (RIIC0.RIICnCR1.UINT8[R_IO_HL])
     61#define RIIC0CR1HH (RIIC0.RIICnCR1.UINT8[R_IO_HH])
     62#define RIIC0CR2 (RIIC0.RIICnCR2.UINT32)
     63#define RIIC0CR2L (RIIC0.RIICnCR2.UINT16[R_IO_L])
     64#define RIIC0CR2LL (RIIC0.RIICnCR2.UINT8[R_IO_LL])
     65#define RIIC0CR2LH (RIIC0.RIICnCR2.UINT8[R_IO_LH])
     66#define RIIC0CR2H (RIIC0.RIICnCR2.UINT16[R_IO_H])
     67#define RIIC0CR2HL (RIIC0.RIICnCR2.UINT8[R_IO_HL])
     68#define RIIC0CR2HH (RIIC0.RIICnCR2.UINT8[R_IO_HH])
     69#define RIIC0MR1 (RIIC0.RIICnMR1.UINT32)
     70#define RIIC0MR1L (RIIC0.RIICnMR1.UINT16[R_IO_L])
     71#define RIIC0MR1LL (RIIC0.RIICnMR1.UINT8[R_IO_LL])
     72#define RIIC0MR1LH (RIIC0.RIICnMR1.UINT8[R_IO_LH])
     73#define RIIC0MR1H (RIIC0.RIICnMR1.UINT16[R_IO_H])
     74#define RIIC0MR1HL (RIIC0.RIICnMR1.UINT8[R_IO_HL])
     75#define RIIC0MR1HH (RIIC0.RIICnMR1.UINT8[R_IO_HH])
     76#define RIIC0MR2 (RIIC0.RIICnMR2.UINT32)
     77#define RIIC0MR2L (RIIC0.RIICnMR2.UINT16[R_IO_L])
     78#define RIIC0MR2LL (RIIC0.RIICnMR2.UINT8[R_IO_LL])
     79#define RIIC0MR2LH (RIIC0.RIICnMR2.UINT8[R_IO_LH])
     80#define RIIC0MR2H (RIIC0.RIICnMR2.UINT16[R_IO_H])
     81#define RIIC0MR2HL (RIIC0.RIICnMR2.UINT8[R_IO_HL])
     82#define RIIC0MR2HH (RIIC0.RIICnMR2.UINT8[R_IO_HH])
     83#define RIIC0MR3 (RIIC0.RIICnMR3.UINT32)
     84#define RIIC0MR3L (RIIC0.RIICnMR3.UINT16[R_IO_L])
     85#define RIIC0MR3LL (RIIC0.RIICnMR3.UINT8[R_IO_LL])
     86#define RIIC0MR3LH (RIIC0.RIICnMR3.UINT8[R_IO_LH])
     87#define RIIC0MR3H (RIIC0.RIICnMR3.UINT16[R_IO_H])
     88#define RIIC0MR3HL (RIIC0.RIICnMR3.UINT8[R_IO_HL])
     89#define RIIC0MR3HH (RIIC0.RIICnMR3.UINT8[R_IO_HH])
     90#define RIIC0FER (RIIC0.RIICnFER.UINT32)
     91#define RIIC0FERL (RIIC0.RIICnFER.UINT16[R_IO_L])
     92#define RIIC0FERLL (RIIC0.RIICnFER.UINT8[R_IO_LL])
     93#define RIIC0FERLH (RIIC0.RIICnFER.UINT8[R_IO_LH])
     94#define RIIC0FERH (RIIC0.RIICnFER.UINT16[R_IO_H])
     95#define RIIC0FERHL (RIIC0.RIICnFER.UINT8[R_IO_HL])
     96#define RIIC0FERHH (RIIC0.RIICnFER.UINT8[R_IO_HH])
     97#define RIIC0SER (RIIC0.RIICnSER.UINT32)
     98#define RIIC0SERL (RIIC0.RIICnSER.UINT16[R_IO_L])
     99#define RIIC0SERLL (RIIC0.RIICnSER.UINT8[R_IO_LL])
     100#define RIIC0SERLH (RIIC0.RIICnSER.UINT8[R_IO_LH])
     101#define RIIC0SERH (RIIC0.RIICnSER.UINT16[R_IO_H])
     102#define RIIC0SERHL (RIIC0.RIICnSER.UINT8[R_IO_HL])
     103#define RIIC0SERHH (RIIC0.RIICnSER.UINT8[R_IO_HH])
     104#define RIIC0IER (RIIC0.RIICnIER.UINT32)
     105#define RIIC0IERL (RIIC0.RIICnIER.UINT16[R_IO_L])
     106#define RIIC0IERLL (RIIC0.RIICnIER.UINT8[R_IO_LL])
     107#define RIIC0IERLH (RIIC0.RIICnIER.UINT8[R_IO_LH])
     108#define RIIC0IERH (RIIC0.RIICnIER.UINT16[R_IO_H])
     109#define RIIC0IERHL (RIIC0.RIICnIER.UINT8[R_IO_HL])
     110#define RIIC0IERHH (RIIC0.RIICnIER.UINT8[R_IO_HH])
     111#define RIIC0SR1 (RIIC0.RIICnSR1.UINT32)
     112#define RIIC0SR1L (RIIC0.RIICnSR1.UINT16[R_IO_L])
     113#define RIIC0SR1LL (RIIC0.RIICnSR1.UINT8[R_IO_LL])
     114#define RIIC0SR1LH (RIIC0.RIICnSR1.UINT8[R_IO_LH])
     115#define RIIC0SR1H (RIIC0.RIICnSR1.UINT16[R_IO_H])
     116#define RIIC0SR1HL (RIIC0.RIICnSR1.UINT8[R_IO_HL])
     117#define RIIC0SR1HH (RIIC0.RIICnSR1.UINT8[R_IO_HH])
     118#define RIIC0SR2 (RIIC0.RIICnSR2.UINT32)
     119#define RIIC0SR2L (RIIC0.RIICnSR2.UINT16[R_IO_L])
     120#define RIIC0SR2LL (RIIC0.RIICnSR2.UINT8[R_IO_LL])
     121#define RIIC0SR2LH (RIIC0.RIICnSR2.UINT8[R_IO_LH])
     122#define RIIC0SR2H (RIIC0.RIICnSR2.UINT16[R_IO_H])
     123#define RIIC0SR2HL (RIIC0.RIICnSR2.UINT8[R_IO_HL])
     124#define RIIC0SR2HH (RIIC0.RIICnSR2.UINT8[R_IO_HH])
     125#define RIIC0SAR0 (RIIC0.RIICnSAR0.UINT32)
     126#define RIIC0SAR0L (RIIC0.RIICnSAR0.UINT16[R_IO_L])
     127#define RIIC0SAR0LL (RIIC0.RIICnSAR0.UINT8[R_IO_LL])
     128#define RIIC0SAR0LH (RIIC0.RIICnSAR0.UINT8[R_IO_LH])
     129#define RIIC0SAR0H (RIIC0.RIICnSAR0.UINT16[R_IO_H])
     130#define RIIC0SAR0HL (RIIC0.RIICnSAR0.UINT8[R_IO_HL])
     131#define RIIC0SAR0HH (RIIC0.RIICnSAR0.UINT8[R_IO_HH])
     132#define RIIC0SAR1 (RIIC0.RIICnSAR1.UINT32)
     133#define RIIC0SAR1L (RIIC0.RIICnSAR1.UINT16[R_IO_L])
     134#define RIIC0SAR1LL (RIIC0.RIICnSAR1.UINT8[R_IO_LL])
     135#define RIIC0SAR1LH (RIIC0.RIICnSAR1.UINT8[R_IO_LH])
     136#define RIIC0SAR1H (RIIC0.RIICnSAR1.UINT16[R_IO_H])
     137#define RIIC0SAR1HL (RIIC0.RIICnSAR1.UINT8[R_IO_HL])
     138#define RIIC0SAR1HH (RIIC0.RIICnSAR1.UINT8[R_IO_HH])
     139#define RIIC0SAR2 (RIIC0.RIICnSAR2.UINT32)
     140#define RIIC0SAR2L (RIIC0.RIICnSAR2.UINT16[R_IO_L])
     141#define RIIC0SAR2LL (RIIC0.RIICnSAR2.UINT8[R_IO_LL])
     142#define RIIC0SAR2LH (RIIC0.RIICnSAR2.UINT8[R_IO_LH])
     143#define RIIC0SAR2H (RIIC0.RIICnSAR2.UINT16[R_IO_H])
     144#define RIIC0SAR2HL (RIIC0.RIICnSAR2.UINT8[R_IO_HL])
     145#define RIIC0SAR2HH (RIIC0.RIICnSAR2.UINT8[R_IO_HH])
     146#define RIIC0BRL (RIIC0.RIICnBRL.UINT32)
     147#define RIIC0BRLL (RIIC0.RIICnBRL.UINT16[R_IO_L])
     148#define RIIC0BRLLL (RIIC0.RIICnBRL.UINT8[R_IO_LL])
     149#define RIIC0BRLLH (RIIC0.RIICnBRL.UINT8[R_IO_LH])
     150#define RIIC0BRLH (RIIC0.RIICnBRL.UINT16[R_IO_H])
     151#define RIIC0BRLHL (RIIC0.RIICnBRL.UINT8[R_IO_HL])
     152#define RIIC0BRLHH (RIIC0.RIICnBRL.UINT8[R_IO_HH])
     153#define RIIC0BRH (RIIC0.RIICnBRH.UINT32)
     154#define RIIC0BRHL (RIIC0.RIICnBRH.UINT16[R_IO_L])
     155#define RIIC0BRHLL (RIIC0.RIICnBRH.UINT8[R_IO_LL])
     156#define RIIC0BRHLH (RIIC0.RIICnBRH.UINT8[R_IO_LH])
     157#define RIIC0BRHH (RIIC0.RIICnBRH.UINT16[R_IO_H])
     158#define RIIC0BRHHL (RIIC0.RIICnBRH.UINT8[R_IO_HL])
     159#define RIIC0BRHHH (RIIC0.RIICnBRH.UINT8[R_IO_HH])
     160#define RIIC0DRT (RIIC0.RIICnDRT.UINT32)
     161#define RIIC0DRTL (RIIC0.RIICnDRT.UINT16[R_IO_L])
     162#define RIIC0DRTLL (RIIC0.RIICnDRT.UINT8[R_IO_LL])
     163#define RIIC0DRTLH (RIIC0.RIICnDRT.UINT8[R_IO_LH])
     164#define RIIC0DRTH (RIIC0.RIICnDRT.UINT16[R_IO_H])
     165#define RIIC0DRTHL (RIIC0.RIICnDRT.UINT8[R_IO_HL])
     166#define RIIC0DRTHH (RIIC0.RIICnDRT.UINT8[R_IO_HH])
     167#define RIIC0DRR (RIIC0.RIICnDRR.UINT32)
     168#define RIIC0DRRL (RIIC0.RIICnDRR.UINT16[R_IO_L])
     169#define RIIC0DRRLL (RIIC0.RIICnDRR.UINT8[R_IO_LL])
     170#define RIIC0DRRLH (RIIC0.RIICnDRR.UINT8[R_IO_LH])
     171#define RIIC0DRRH (RIIC0.RIICnDRR.UINT16[R_IO_H])
     172#define RIIC0DRRHL (RIIC0.RIICnDRR.UINT8[R_IO_HL])
     173#define RIIC0DRRHH (RIIC0.RIICnDRR.UINT8[R_IO_HH])
     174#define RIIC1CR1 (RIIC1.RIICnCR1.UINT32)
     175#define RIIC1CR1L (RIIC1.RIICnCR1.UINT16[R_IO_L])
     176#define RIIC1CR1LL (RIIC1.RIICnCR1.UINT8[R_IO_LL])
     177#define RIIC1CR1LH (RIIC1.RIICnCR1.UINT8[R_IO_LH])
     178#define RIIC1CR1H (RIIC1.RIICnCR1.UINT16[R_IO_H])
     179#define RIIC1CR1HL (RIIC1.RIICnCR1.UINT8[R_IO_HL])
     180#define RIIC1CR1HH (RIIC1.RIICnCR1.UINT8[R_IO_HH])
     181#define RIIC1CR2 (RIIC1.RIICnCR2.UINT32)
     182#define RIIC1CR2L (RIIC1.RIICnCR2.UINT16[R_IO_L])
     183#define RIIC1CR2LL (RIIC1.RIICnCR2.UINT8[R_IO_LL])
     184#define RIIC1CR2LH (RIIC1.RIICnCR2.UINT8[R_IO_LH])
     185#define RIIC1CR2H (RIIC1.RIICnCR2.UINT16[R_IO_H])
     186#define RIIC1CR2HL (RIIC1.RIICnCR2.UINT8[R_IO_HL])
     187#define RIIC1CR2HH (RIIC1.RIICnCR2.UINT8[R_IO_HH])
     188#define RIIC1MR1 (RIIC1.RIICnMR1.UINT32)
     189#define RIIC1MR1L (RIIC1.RIICnMR1.UINT16[R_IO_L])
     190#define RIIC1MR1LL (RIIC1.RIICnMR1.UINT8[R_IO_LL])
     191#define RIIC1MR1LH (RIIC1.RIICnMR1.UINT8[R_IO_LH])
     192#define RIIC1MR1H (RIIC1.RIICnMR1.UINT16[R_IO_H])
     193#define RIIC1MR1HL (RIIC1.RIICnMR1.UINT8[R_IO_HL])
     194#define RIIC1MR1HH (RIIC1.RIICnMR1.UINT8[R_IO_HH])
     195#define RIIC1MR2 (RIIC1.RIICnMR2.UINT32)
     196#define RIIC1MR2L (RIIC1.RIICnMR2.UINT16[R_IO_L])
     197#define RIIC1MR2LL (RIIC1.RIICnMR2.UINT8[R_IO_LL])
     198#define RIIC1MR2LH (RIIC1.RIICnMR2.UINT8[R_IO_LH])
     199#define RIIC1MR2H (RIIC1.RIICnMR2.UINT16[R_IO_H])
     200#define RIIC1MR2HL (RIIC1.RIICnMR2.UINT8[R_IO_HL])
     201#define RIIC1MR2HH (RIIC1.RIICnMR2.UINT8[R_IO_HH])
     202#define RIIC1MR3 (RIIC1.RIICnMR3.UINT32)
     203#define RIIC1MR3L (RIIC1.RIICnMR3.UINT16[R_IO_L])
     204#define RIIC1MR3LL (RIIC1.RIICnMR3.UINT8[R_IO_LL])
     205#define RIIC1MR3LH (RIIC1.RIICnMR3.UINT8[R_IO_LH])
     206#define RIIC1MR3H (RIIC1.RIICnMR3.UINT16[R_IO_H])
     207#define RIIC1MR3HL (RIIC1.RIICnMR3.UINT8[R_IO_HL])
     208#define RIIC1MR3HH (RIIC1.RIICnMR3.UINT8[R_IO_HH])
     209#define RIIC1FER (RIIC1.RIICnFER.UINT32)
     210#define RIIC1FERL (RIIC1.RIICnFER.UINT16[R_IO_L])
     211#define RIIC1FERLL (RIIC1.RIICnFER.UINT8[R_IO_LL])
     212#define RIIC1FERLH (RIIC1.RIICnFER.UINT8[R_IO_LH])
     213#define RIIC1FERH (RIIC1.RIICnFER.UINT16[R_IO_H])
     214#define RIIC1FERHL (RIIC1.RIICnFER.UINT8[R_IO_HL])
     215#define RIIC1FERHH (RIIC1.RIICnFER.UINT8[R_IO_HH])
     216#define RIIC1SER (RIIC1.RIICnSER.UINT32)
     217#define RIIC1SERL (RIIC1.RIICnSER.UINT16[R_IO_L])
     218#define RIIC1SERLL (RIIC1.RIICnSER.UINT8[R_IO_LL])
     219#define RIIC1SERLH (RIIC1.RIICnSER.UINT8[R_IO_LH])
     220#define RIIC1SERH (RIIC1.RIICnSER.UINT16[R_IO_H])
     221#define RIIC1SERHL (RIIC1.RIICnSER.UINT8[R_IO_HL])
     222#define RIIC1SERHH (RIIC1.RIICnSER.UINT8[R_IO_HH])
     223#define RIIC1IER (RIIC1.RIICnIER.UINT32)
     224#define RIIC1IERL (RIIC1.RIICnIER.UINT16[R_IO_L])
     225#define RIIC1IERLL (RIIC1.RIICnIER.UINT8[R_IO_LL])
     226#define RIIC1IERLH (RIIC1.RIICnIER.UINT8[R_IO_LH])
     227#define RIIC1IERH (RIIC1.RIICnIER.UINT16[R_IO_H])
     228#define RIIC1IERHL (RIIC1.RIICnIER.UINT8[R_IO_HL])
     229#define RIIC1IERHH (RIIC1.RIICnIER.UINT8[R_IO_HH])
     230#define RIIC1SR1 (RIIC1.RIICnSR1.UINT32)
     231#define RIIC1SR1L (RIIC1.RIICnSR1.UINT16[R_IO_L])
     232#define RIIC1SR1LL (RIIC1.RIICnSR1.UINT8[R_IO_LL])
     233#define RIIC1SR1LH (RIIC1.RIICnSR1.UINT8[R_IO_LH])
     234#define RIIC1SR1H (RIIC1.RIICnSR1.UINT16[R_IO_H])
     235#define RIIC1SR1HL (RIIC1.RIICnSR1.UINT8[R_IO_HL])
     236#define RIIC1SR1HH (RIIC1.RIICnSR1.UINT8[R_IO_HH])
     237#define RIIC1SR2 (RIIC1.RIICnSR2.UINT32)
     238#define RIIC1SR2L (RIIC1.RIICnSR2.UINT16[R_IO_L])
     239#define RIIC1SR2LL (RIIC1.RIICnSR2.UINT8[R_IO_LL])
     240#define RIIC1SR2LH (RIIC1.RIICnSR2.UINT8[R_IO_LH])
     241#define RIIC1SR2H (RIIC1.RIICnSR2.UINT16[R_IO_H])
     242#define RIIC1SR2HL (RIIC1.RIICnSR2.UINT8[R_IO_HL])
     243#define RIIC1SR2HH (RIIC1.RIICnSR2.UINT8[R_IO_HH])
     244#define RIIC1SAR0 (RIIC1.RIICnSAR0.UINT32)
     245#define RIIC1SAR0L (RIIC1.RIICnSAR0.UINT16[R_IO_L])
     246#define RIIC1SAR0LL (RIIC1.RIICnSAR0.UINT8[R_IO_LL])
     247#define RIIC1SAR0LH (RIIC1.RIICnSAR0.UINT8[R_IO_LH])
     248#define RIIC1SAR0H (RIIC1.RIICnSAR0.UINT16[R_IO_H])
     249#define RIIC1SAR0HL (RIIC1.RIICnSAR0.UINT8[R_IO_HL])
     250#define RIIC1SAR0HH (RIIC1.RIICnSAR0.UINT8[R_IO_HH])
     251#define RIIC1SAR1 (RIIC1.RIICnSAR1.UINT32)
     252#define RIIC1SAR1L (RIIC1.RIICnSAR1.UINT16[R_IO_L])
     253#define RIIC1SAR1LL (RIIC1.RIICnSAR1.UINT8[R_IO_LL])
     254#define RIIC1SAR1LH (RIIC1.RIICnSAR1.UINT8[R_IO_LH])
     255#define RIIC1SAR1H (RIIC1.RIICnSAR1.UINT16[R_IO_H])
     256#define RIIC1SAR1HL (RIIC1.RIICnSAR1.UINT8[R_IO_HL])
     257#define RIIC1SAR1HH (RIIC1.RIICnSAR1.UINT8[R_IO_HH])
     258#define RIIC1SAR2 (RIIC1.RIICnSAR2.UINT32)
     259#define RIIC1SAR2L (RIIC1.RIICnSAR2.UINT16[R_IO_L])
     260#define RIIC1SAR2LL (RIIC1.RIICnSAR2.UINT8[R_IO_LL])
     261#define RIIC1SAR2LH (RIIC1.RIICnSAR2.UINT8[R_IO_LH])
     262#define RIIC1SAR2H (RIIC1.RIICnSAR2.UINT16[R_IO_H])
     263#define RIIC1SAR2HL (RIIC1.RIICnSAR2.UINT8[R_IO_HL])
     264#define RIIC1SAR2HH (RIIC1.RIICnSAR2.UINT8[R_IO_HH])
     265#define RIIC1BRL (RIIC1.RIICnBRL.UINT32)
     266#define RIIC1BRLL (RIIC1.RIICnBRL.UINT16[R_IO_L])
     267#define RIIC1BRLLL (RIIC1.RIICnBRL.UINT8[R_IO_LL])
     268#define RIIC1BRLLH (RIIC1.RIICnBRL.UINT8[R_IO_LH])
     269#define RIIC1BRLH (RIIC1.RIICnBRL.UINT16[R_IO_H])
     270#define RIIC1BRLHL (RIIC1.RIICnBRL.UINT8[R_IO_HL])
     271#define RIIC1BRLHH (RIIC1.RIICnBRL.UINT8[R_IO_HH])
     272#define RIIC1BRH (RIIC1.RIICnBRH.UINT32)
     273#define RIIC1BRHL (RIIC1.RIICnBRH.UINT16[R_IO_L])
     274#define RIIC1BRHLL (RIIC1.RIICnBRH.UINT8[R_IO_LL])
     275#define RIIC1BRHLH (RIIC1.RIICnBRH.UINT8[R_IO_LH])
     276#define RIIC1BRHH (RIIC1.RIICnBRH.UINT16[R_IO_H])
     277#define RIIC1BRHHL (RIIC1.RIICnBRH.UINT8[R_IO_HL])
     278#define RIIC1BRHHH (RIIC1.RIICnBRH.UINT8[R_IO_HH])
     279#define RIIC1DRT (RIIC1.RIICnDRT.UINT32)
     280#define RIIC1DRTL (RIIC1.RIICnDRT.UINT16[R_IO_L])
     281#define RIIC1DRTLL (RIIC1.RIICnDRT.UINT8[R_IO_LL])
     282#define RIIC1DRTLH (RIIC1.RIICnDRT.UINT8[R_IO_LH])
     283#define RIIC1DRTH (RIIC1.RIICnDRT.UINT16[R_IO_H])
     284#define RIIC1DRTHL (RIIC1.RIICnDRT.UINT8[R_IO_HL])
     285#define RIIC1DRTHH (RIIC1.RIICnDRT.UINT8[R_IO_HH])
     286#define RIIC1DRR (RIIC1.RIICnDRR.UINT32)
     287#define RIIC1DRRL (RIIC1.RIICnDRR.UINT16[R_IO_L])
     288#define RIIC1DRRLL (RIIC1.RIICnDRR.UINT8[R_IO_LL])
     289#define RIIC1DRRLH (RIIC1.RIICnDRR.UINT8[R_IO_LH])
     290#define RIIC1DRRH (RIIC1.RIICnDRR.UINT16[R_IO_H])
     291#define RIIC1DRRHL (RIIC1.RIICnDRR.UINT8[R_IO_HL])
     292#define RIIC1DRRHH (RIIC1.RIICnDRR.UINT8[R_IO_HH])
     293#define RIIC2CR1 (RIIC2.RIICnCR1.UINT32)
     294#define RIIC2CR1L (RIIC2.RIICnCR1.UINT16[R_IO_L])
     295#define RIIC2CR1LL (RIIC2.RIICnCR1.UINT8[R_IO_LL])
     296#define RIIC2CR1LH (RIIC2.RIICnCR1.UINT8[R_IO_LH])
     297#define RIIC2CR1H (RIIC2.RIICnCR1.UINT16[R_IO_H])
     298#define RIIC2CR1HL (RIIC2.RIICnCR1.UINT8[R_IO_HL])
     299#define RIIC2CR1HH (RIIC2.RIICnCR1.UINT8[R_IO_HH])
     300#define RIIC2CR2 (RIIC2.RIICnCR2.UINT32)
     301#define RIIC2CR2L (RIIC2.RIICnCR2.UINT16[R_IO_L])
     302#define RIIC2CR2LL (RIIC2.RIICnCR2.UINT8[R_IO_LL])
     303#define RIIC2CR2LH (RIIC2.RIICnCR2.UINT8[R_IO_LH])
     304#define RIIC2CR2H (RIIC2.RIICnCR2.UINT16[R_IO_H])
     305#define RIIC2CR2HL (RIIC2.RIICnCR2.UINT8[R_IO_HL])
     306#define RIIC2CR2HH (RIIC2.RIICnCR2.UINT8[R_IO_HH])
     307#define RIIC2MR1 (RIIC2.RIICnMR1.UINT32)
     308#define RIIC2MR1L (RIIC2.RIICnMR1.UINT16[R_IO_L])
     309#define RIIC2MR1LL (RIIC2.RIICnMR1.UINT8[R_IO_LL])
     310#define RIIC2MR1LH (RIIC2.RIICnMR1.UINT8[R_IO_LH])
     311#define RIIC2MR1H (RIIC2.RIICnMR1.UINT16[R_IO_H])
     312#define RIIC2MR1HL (RIIC2.RIICnMR1.UINT8[R_IO_HL])
     313#define RIIC2MR1HH (RIIC2.RIICnMR1.UINT8[R_IO_HH])
     314#define RIIC2MR2 (RIIC2.RIICnMR2.UINT32)
     315#define RIIC2MR2L (RIIC2.RIICnMR2.UINT16[R_IO_L])
     316#define RIIC2MR2LL (RIIC2.RIICnMR2.UINT8[R_IO_LL])
     317#define RIIC2MR2LH (RIIC2.RIICnMR2.UINT8[R_IO_LH])
     318#define RIIC2MR2H (RIIC2.RIICnMR2.UINT16[R_IO_H])
     319#define RIIC2MR2HL (RIIC2.RIICnMR2.UINT8[R_IO_HL])
     320#define RIIC2MR2HH (RIIC2.RIICnMR2.UINT8[R_IO_HH])
     321#define RIIC2MR3 (RIIC2.RIICnMR3.UINT32)
     322#define RIIC2MR3L (RIIC2.RIICnMR3.UINT16[R_IO_L])
     323#define RIIC2MR3LL (RIIC2.RIICnMR3.UINT8[R_IO_LL])
     324#define RIIC2MR3LH (RIIC2.RIICnMR3.UINT8[R_IO_LH])
     325#define RIIC2MR3H (RIIC2.RIICnMR3.UINT16[R_IO_H])
     326#define RIIC2MR3HL (RIIC2.RIICnMR3.UINT8[R_IO_HL])
     327#define RIIC2MR3HH (RIIC2.RIICnMR3.UINT8[R_IO_HH])
     328#define RIIC2FER (RIIC2.RIICnFER.UINT32)
     329#define RIIC2FERL (RIIC2.RIICnFER.UINT16[R_IO_L])
     330#define RIIC2FERLL (RIIC2.RIICnFER.UINT8[R_IO_LL])
     331#define RIIC2FERLH (RIIC2.RIICnFER.UINT8[R_IO_LH])
     332#define RIIC2FERH (RIIC2.RIICnFER.UINT16[R_IO_H])
     333#define RIIC2FERHL (RIIC2.RIICnFER.UINT8[R_IO_HL])
     334#define RIIC2FERHH (RIIC2.RIICnFER.UINT8[R_IO_HH])
     335#define RIIC2SER (RIIC2.RIICnSER.UINT32)
     336#define RIIC2SERL (RIIC2.RIICnSER.UINT16[R_IO_L])
     337#define RIIC2SERLL (RIIC2.RIICnSER.UINT8[R_IO_LL])
     338#define RIIC2SERLH (RIIC2.RIICnSER.UINT8[R_IO_LH])
     339#define RIIC2SERH (RIIC2.RIICnSER.UINT16[R_IO_H])
     340#define RIIC2SERHL (RIIC2.RIICnSER.UINT8[R_IO_HL])
     341#define RIIC2SERHH (RIIC2.RIICnSER.UINT8[R_IO_HH])
     342#define RIIC2IER (RIIC2.RIICnIER.UINT32)
     343#define RIIC2IERL (RIIC2.RIICnIER.UINT16[R_IO_L])
     344#define RIIC2IERLL (RIIC2.RIICnIER.UINT8[R_IO_LL])
     345#define RIIC2IERLH (RIIC2.RIICnIER.UINT8[R_IO_LH])
     346#define RIIC2IERH (RIIC2.RIICnIER.UINT16[R_IO_H])
     347#define RIIC2IERHL (RIIC2.RIICnIER.UINT8[R_IO_HL])
     348#define RIIC2IERHH (RIIC2.RIICnIER.UINT8[R_IO_HH])
     349#define RIIC2SR1 (RIIC2.RIICnSR1.UINT32)
     350#define RIIC2SR1L (RIIC2.RIICnSR1.UINT16[R_IO_L])
     351#define RIIC2SR1LL (RIIC2.RIICnSR1.UINT8[R_IO_LL])
     352#define RIIC2SR1LH (RIIC2.RIICnSR1.UINT8[R_IO_LH])
     353#define RIIC2SR1H (RIIC2.RIICnSR1.UINT16[R_IO_H])
     354#define RIIC2SR1HL (RIIC2.RIICnSR1.UINT8[R_IO_HL])
     355#define RIIC2SR1HH (RIIC2.RIICnSR1.UINT8[R_IO_HH])
     356#define RIIC2SR2 (RIIC2.RIICnSR2.UINT32)
     357#define RIIC2SR2L (RIIC2.RIICnSR2.UINT16[R_IO_L])
     358#define RIIC2SR2LL (RIIC2.RIICnSR2.UINT8[R_IO_LL])
     359#define RIIC2SR2LH (RIIC2.RIICnSR2.UINT8[R_IO_LH])
     360#define RIIC2SR2H (RIIC2.RIICnSR2.UINT16[R_IO_H])
     361#define RIIC2SR2HL (RIIC2.RIICnSR2.UINT8[R_IO_HL])
     362#define RIIC2SR2HH (RIIC2.RIICnSR2.UINT8[R_IO_HH])
     363#define RIIC2SAR0 (RIIC2.RIICnSAR0.UINT32)
     364#define RIIC2SAR0L (RIIC2.RIICnSAR0.UINT16[R_IO_L])
     365#define RIIC2SAR0LL (RIIC2.RIICnSAR0.UINT8[R_IO_LL])
     366#define RIIC2SAR0LH (RIIC2.RIICnSAR0.UINT8[R_IO_LH])
     367#define RIIC2SAR0H (RIIC2.RIICnSAR0.UINT16[R_IO_H])
     368#define RIIC2SAR0HL (RIIC2.RIICnSAR0.UINT8[R_IO_HL])
     369#define RIIC2SAR0HH (RIIC2.RIICnSAR0.UINT8[R_IO_HH])
     370#define RIIC2SAR1 (RIIC2.RIICnSAR1.UINT32)
     371#define RIIC2SAR1L (RIIC2.RIICnSAR1.UINT16[R_IO_L])
     372#define RIIC2SAR1LL (RIIC2.RIICnSAR1.UINT8[R_IO_LL])
     373#define RIIC2SAR1LH (RIIC2.RIICnSAR1.UINT8[R_IO_LH])
     374#define RIIC2SAR1H (RIIC2.RIICnSAR1.UINT16[R_IO_H])
     375#define RIIC2SAR1HL (RIIC2.RIICnSAR1.UINT8[R_IO_HL])
     376#define RIIC2SAR1HH (RIIC2.RIICnSAR1.UINT8[R_IO_HH])
     377#define RIIC2SAR2 (RIIC2.RIICnSAR2.UINT32)
     378#define RIIC2SAR2L (RIIC2.RIICnSAR2.UINT16[R_IO_L])
     379#define RIIC2SAR2LL (RIIC2.RIICnSAR2.UINT8[R_IO_LL])
     380#define RIIC2SAR2LH (RIIC2.RIICnSAR2.UINT8[R_IO_LH])
     381#define RIIC2SAR2H (RIIC2.RIICnSAR2.UINT16[R_IO_H])
     382#define RIIC2SAR2HL (RIIC2.RIICnSAR2.UINT8[R_IO_HL])
     383#define RIIC2SAR2HH (RIIC2.RIICnSAR2.UINT8[R_IO_HH])
     384#define RIIC2BRL (RIIC2.RIICnBRL.UINT32)
     385#define RIIC2BRLL (RIIC2.RIICnBRL.UINT16[R_IO_L])
     386#define RIIC2BRLLL (RIIC2.RIICnBRL.UINT8[R_IO_LL])
     387#define RIIC2BRLLH (RIIC2.RIICnBRL.UINT8[R_IO_LH])
     388#define RIIC2BRLH (RIIC2.RIICnBRL.UINT16[R_IO_H])
     389#define RIIC2BRLHL (RIIC2.RIICnBRL.UINT8[R_IO_HL])
     390#define RIIC2BRLHH (RIIC2.RIICnBRL.UINT8[R_IO_HH])
     391#define RIIC2BRH (RIIC2.RIICnBRH.UINT32)
     392#define RIIC2BRHL (RIIC2.RIICnBRH.UINT16[R_IO_L])
     393#define RIIC2BRHLL (RIIC2.RIICnBRH.UINT8[R_IO_LL])
     394#define RIIC2BRHLH (RIIC2.RIICnBRH.UINT8[R_IO_LH])
     395#define RIIC2BRHH (RIIC2.RIICnBRH.UINT16[R_IO_H])
     396#define RIIC2BRHHL (RIIC2.RIICnBRH.UINT8[R_IO_HL])
     397#define RIIC2BRHHH (RIIC2.RIICnBRH.UINT8[R_IO_HH])
     398#define RIIC2DRT (RIIC2.RIICnDRT.UINT32)
     399#define RIIC2DRTL (RIIC2.RIICnDRT.UINT16[R_IO_L])
     400#define RIIC2DRTLL (RIIC2.RIICnDRT.UINT8[R_IO_LL])
     401#define RIIC2DRTLH (RIIC2.RIICnDRT.UINT8[R_IO_LH])
     402#define RIIC2DRTH (RIIC2.RIICnDRT.UINT16[R_IO_H])
     403#define RIIC2DRTHL (RIIC2.RIICnDRT.UINT8[R_IO_HL])
     404#define RIIC2DRTHH (RIIC2.RIICnDRT.UINT8[R_IO_HH])
     405#define RIIC2DRR (RIIC2.RIICnDRR.UINT32)
     406#define RIIC2DRRL (RIIC2.RIICnDRR.UINT16[R_IO_L])
     407#define RIIC2DRRLL (RIIC2.RIICnDRR.UINT8[R_IO_LL])
     408#define RIIC2DRRLH (RIIC2.RIICnDRR.UINT8[R_IO_LH])
     409#define RIIC2DRRH (RIIC2.RIICnDRR.UINT16[R_IO_H])
     410#define RIIC2DRRHL (RIIC2.RIICnDRR.UINT8[R_IO_HL])
     411#define RIIC2DRRHH (RIIC2.RIICnDRR.UINT8[R_IO_HH])
     412#define RIIC3CR1 (RIIC3.RIICnCR1.UINT32)
     413#define RIIC3CR1L (RIIC3.RIICnCR1.UINT16[R_IO_L])
     414#define RIIC3CR1LL (RIIC3.RIICnCR1.UINT8[R_IO_LL])
     415#define RIIC3CR1LH (RIIC3.RIICnCR1.UINT8[R_IO_LH])
     416#define RIIC3CR1H (RIIC3.RIICnCR1.UINT16[R_IO_H])
     417#define RIIC3CR1HL (RIIC3.RIICnCR1.UINT8[R_IO_HL])
     418#define RIIC3CR1HH (RIIC3.RIICnCR1.UINT8[R_IO_HH])
     419#define RIIC3CR2 (RIIC3.RIICnCR2.UINT32)
     420#define RIIC3CR2L (RIIC3.RIICnCR2.UINT16[R_IO_L])
     421#define RIIC3CR2LL (RIIC3.RIICnCR2.UINT8[R_IO_LL])
     422#define RIIC3CR2LH (RIIC3.RIICnCR2.UINT8[R_IO_LH])
     423#define RIIC3CR2H (RIIC3.RIICnCR2.UINT16[R_IO_H])
     424#define RIIC3CR2HL (RIIC3.RIICnCR2.UINT8[R_IO_HL])
     425#define RIIC3CR2HH (RIIC3.RIICnCR2.UINT8[R_IO_HH])
     426#define RIIC3MR1 (RIIC3.RIICnMR1.UINT32)
     427#define RIIC3MR1L (RIIC3.RIICnMR1.UINT16[R_IO_L])
     428#define RIIC3MR1LL (RIIC3.RIICnMR1.UINT8[R_IO_LL])
     429#define RIIC3MR1LH (RIIC3.RIICnMR1.UINT8[R_IO_LH])
     430#define RIIC3MR1H (RIIC3.RIICnMR1.UINT16[R_IO_H])
     431#define RIIC3MR1HL (RIIC3.RIICnMR1.UINT8[R_IO_HL])
     432#define RIIC3MR1HH (RIIC3.RIICnMR1.UINT8[R_IO_HH])
     433#define RIIC3MR2 (RIIC3.RIICnMR2.UINT32)
     434#define RIIC3MR2L (RIIC3.RIICnMR2.UINT16[R_IO_L])
     435#define RIIC3MR2LL (RIIC3.RIICnMR2.UINT8[R_IO_LL])
     436#define RIIC3MR2LH (RIIC3.RIICnMR2.UINT8[R_IO_LH])
     437#define RIIC3MR2H (RIIC3.RIICnMR2.UINT16[R_IO_H])
     438#define RIIC3MR2HL (RIIC3.RIICnMR2.UINT8[R_IO_HL])
     439#define RIIC3MR2HH (RIIC3.RIICnMR2.UINT8[R_IO_HH])
     440#define RIIC3MR3 (RIIC3.RIICnMR3.UINT32)
     441#define RIIC3MR3L (RIIC3.RIICnMR3.UINT16[R_IO_L])
     442#define RIIC3MR3LL (RIIC3.RIICnMR3.UINT8[R_IO_LL])
     443#define RIIC3MR3LH (RIIC3.RIICnMR3.UINT8[R_IO_LH])
     444#define RIIC3MR3H (RIIC3.RIICnMR3.UINT16[R_IO_H])
     445#define RIIC3MR3HL (RIIC3.RIICnMR3.UINT8[R_IO_HL])
     446#define RIIC3MR3HH (RIIC3.RIICnMR3.UINT8[R_IO_HH])
     447#define RIIC3FER (RIIC3.RIICnFER.UINT32)
     448#define RIIC3FERL (RIIC3.RIICnFER.UINT16[R_IO_L])
     449#define RIIC3FERLL (RIIC3.RIICnFER.UINT8[R_IO_LL])
     450#define RIIC3FERLH (RIIC3.RIICnFER.UINT8[R_IO_LH])
     451#define RIIC3FERH (RIIC3.RIICnFER.UINT16[R_IO_H])
     452#define RIIC3FERHL (RIIC3.RIICnFER.UINT8[R_IO_HL])
     453#define RIIC3FERHH (RIIC3.RIICnFER.UINT8[R_IO_HH])
     454#define RIIC3SER (RIIC3.RIICnSER.UINT32)
     455#define RIIC3SERL (RIIC3.RIICnSER.UINT16[R_IO_L])
     456#define RIIC3SERLL (RIIC3.RIICnSER.UINT8[R_IO_LL])
     457#define RIIC3SERLH (RIIC3.RIICnSER.UINT8[R_IO_LH])
     458#define RIIC3SERH (RIIC3.RIICnSER.UINT16[R_IO_H])
     459#define RIIC3SERHL (RIIC3.RIICnSER.UINT8[R_IO_HL])
     460#define RIIC3SERHH (RIIC3.RIICnSER.UINT8[R_IO_HH])
     461#define RIIC3IER (RIIC3.RIICnIER.UINT32)
     462#define RIIC3IERL (RIIC3.RIICnIER.UINT16[R_IO_L])
     463#define RIIC3IERLL (RIIC3.RIICnIER.UINT8[R_IO_LL])
     464#define RIIC3IERLH (RIIC3.RIICnIER.UINT8[R_IO_LH])
     465#define RIIC3IERH (RIIC3.RIICnIER.UINT16[R_IO_H])
     466#define RIIC3IERHL (RIIC3.RIICnIER.UINT8[R_IO_HL])
     467#define RIIC3IERHH (RIIC3.RIICnIER.UINT8[R_IO_HH])
     468#define RIIC3SR1 (RIIC3.RIICnSR1.UINT32)
     469#define RIIC3SR1L (RIIC3.RIICnSR1.UINT16[R_IO_L])
     470#define RIIC3SR1LL (RIIC3.RIICnSR1.UINT8[R_IO_LL])
     471#define RIIC3SR1LH (RIIC3.RIICnSR1.UINT8[R_IO_LH])
     472#define RIIC3SR1H (RIIC3.RIICnSR1.UINT16[R_IO_H])
     473#define RIIC3SR1HL (RIIC3.RIICnSR1.UINT8[R_IO_HL])
     474#define RIIC3SR1HH (RIIC3.RIICnSR1.UINT8[R_IO_HH])
     475#define RIIC3SR2 (RIIC3.RIICnSR2.UINT32)
     476#define RIIC3SR2L (RIIC3.RIICnSR2.UINT16[R_IO_L])
     477#define RIIC3SR2LL (RIIC3.RIICnSR2.UINT8[R_IO_LL])
     478#define RIIC3SR2LH (RIIC3.RIICnSR2.UINT8[R_IO_LH])
     479#define RIIC3SR2H (RIIC3.RIICnSR2.UINT16[R_IO_H])
     480#define RIIC3SR2HL (RIIC3.RIICnSR2.UINT8[R_IO_HL])
     481#define RIIC3SR2HH (RIIC3.RIICnSR2.UINT8[R_IO_HH])
     482#define RIIC3SAR0 (RIIC3.RIICnSAR0.UINT32)
     483#define RIIC3SAR0L (RIIC3.RIICnSAR0.UINT16[R_IO_L])
     484#define RIIC3SAR0LL (RIIC3.RIICnSAR0.UINT8[R_IO_LL])
     485#define RIIC3SAR0LH (RIIC3.RIICnSAR0.UINT8[R_IO_LH])
     486#define RIIC3SAR0H (RIIC3.RIICnSAR0.UINT16[R_IO_H])
     487#define RIIC3SAR0HL (RIIC3.RIICnSAR0.UINT8[R_IO_HL])
     488#define RIIC3SAR0HH (RIIC3.RIICnSAR0.UINT8[R_IO_HH])
     489#define RIIC3SAR1 (RIIC3.RIICnSAR1.UINT32)
     490#define RIIC3SAR1L (RIIC3.RIICnSAR1.UINT16[R_IO_L])
     491#define RIIC3SAR1LL (RIIC3.RIICnSAR1.UINT8[R_IO_LL])
     492#define RIIC3SAR1LH (RIIC3.RIICnSAR1.UINT8[R_IO_LH])
     493#define RIIC3SAR1H (RIIC3.RIICnSAR1.UINT16[R_IO_H])
     494#define RIIC3SAR1HL (RIIC3.RIICnSAR1.UINT8[R_IO_HL])
     495#define RIIC3SAR1HH (RIIC3.RIICnSAR1.UINT8[R_IO_HH])
     496#define RIIC3SAR2 (RIIC3.RIICnSAR2.UINT32)
     497#define RIIC3SAR2L (RIIC3.RIICnSAR2.UINT16[R_IO_L])
     498#define RIIC3SAR2LL (RIIC3.RIICnSAR2.UINT8[R_IO_LL])
     499#define RIIC3SAR2LH (RIIC3.RIICnSAR2.UINT8[R_IO_LH])
     500#define RIIC3SAR2H (RIIC3.RIICnSAR2.UINT16[R_IO_H])
     501#define RIIC3SAR2HL (RIIC3.RIICnSAR2.UINT8[R_IO_HL])
     502#define RIIC3SAR2HH (RIIC3.RIICnSAR2.UINT8[R_IO_HH])
     503#define RIIC3BRL (RIIC3.RIICnBRL.UINT32)
     504#define RIIC3BRLL (RIIC3.RIICnBRL.UINT16[R_IO_L])
     505#define RIIC3BRLLL (RIIC3.RIICnBRL.UINT8[R_IO_LL])
     506#define RIIC3BRLLH (RIIC3.RIICnBRL.UINT8[R_IO_LH])
     507#define RIIC3BRLH (RIIC3.RIICnBRL.UINT16[R_IO_H])
     508#define RIIC3BRLHL (RIIC3.RIICnBRL.UINT8[R_IO_HL])
     509#define RIIC3BRLHH (RIIC3.RIICnBRL.UINT8[R_IO_HH])
     510#define RIIC3BRH (RIIC3.RIICnBRH.UINT32)
     511#define RIIC3BRHL (RIIC3.RIICnBRH.UINT16[R_IO_L])
     512#define RIIC3BRHLL (RIIC3.RIICnBRH.UINT8[R_IO_LL])
     513#define RIIC3BRHLH (RIIC3.RIICnBRH.UINT8[R_IO_LH])
     514#define RIIC3BRHH (RIIC3.RIICnBRH.UINT16[R_IO_H])
     515#define RIIC3BRHHL (RIIC3.RIICnBRH.UINT8[R_IO_HL])
     516#define RIIC3BRHHH (RIIC3.RIICnBRH.UINT8[R_IO_HH])
     517#define RIIC3DRT (RIIC3.RIICnDRT.UINT32)
     518#define RIIC3DRTL (RIIC3.RIICnDRT.UINT16[R_IO_L])
     519#define RIIC3DRTLL (RIIC3.RIICnDRT.UINT8[R_IO_LL])
     520#define RIIC3DRTLH (RIIC3.RIICnDRT.UINT8[R_IO_LH])
     521#define RIIC3DRTH (RIIC3.RIICnDRT.UINT16[R_IO_H])
     522#define RIIC3DRTHL (RIIC3.RIICnDRT.UINT8[R_IO_HL])
     523#define RIIC3DRTHH (RIIC3.RIICnDRT.UINT8[R_IO_HH])
     524#define RIIC3DRR (RIIC3.RIICnDRR.UINT32)
     525#define RIIC3DRRL (RIIC3.RIICnDRR.UINT16[R_IO_L])
     526#define RIIC3DRRLL (RIIC3.RIICnDRR.UINT8[R_IO_LL])
     527#define RIIC3DRRLH (RIIC3.RIICnDRR.UINT8[R_IO_LH])
     528#define RIIC3DRRH (RIIC3.RIICnDRR.UINT16[R_IO_H])
     529#define RIIC3DRRHL (RIIC3.RIICnDRR.UINT8[R_IO_HL])
     530#define RIIC3DRRHH (RIIC3.RIICnDRR.UINT8[R_IO_HH])
     531
     532#define RIICnCRm_COUNT (2)
     533#define RIICnMRm_COUNT (3)
     534#define RIICnSRm_COUNT (2)
     535#define RIICnSARm_COUNT (3)
     536
     537
     538typedef struct st_riic
     539{
     540                                                           /* RIIC             */
     541
     542/* #define RIICnCRm_COUNT (2) */
     543    union iodefine_reg32_t  RIICnCR1;                      /*  RIICnCR1        */
     544    union iodefine_reg32_t  RIICnCR2;                      /*  RIICnCR2        */
     545
     546/* #define RIICnMRm_COUNT (3) */
     547    union iodefine_reg32_t  RIICnMR1;                      /*  RIICnMR1        */
     548    union iodefine_reg32_t  RIICnMR2;                      /*  RIICnMR2        */
     549    union iodefine_reg32_t  RIICnMR3;                      /*  RIICnMR3        */
     550    union iodefine_reg32_t  RIICnFER;                      /*  RIICnFER        */
     551    union iodefine_reg32_t  RIICnSER;                      /*  RIICnSER        */
     552    union iodefine_reg32_t  RIICnIER;                      /*  RIICnIER        */
     553
     554/* #define RIICnSRm_COUNT (2) */
     555    union iodefine_reg32_t  RIICnSR1;                      /*  RIICnSR1        */
     556    union iodefine_reg32_t  RIICnSR2;                      /*  RIICnSR2        */
     557
     558/* #define RIICnSARm_COUNT (3) */
     559    union iodefine_reg32_t  RIICnSAR0;                     /*  RIICnSAR0       */
     560    union iodefine_reg32_t  RIICnSAR1;                     /*  RIICnSAR1       */
     561    union iodefine_reg32_t  RIICnSAR2;                     /*  RIICnSAR2       */
     562    union iodefine_reg32_t  RIICnBRL;                      /*  RIICnBRL        */
     563    union iodefine_reg32_t  RIICnBRH;                      /*  RIICnBRH        */
     564    union iodefine_reg32_t  RIICnDRT;                      /*  RIICnDRT        */
     565    union iodefine_reg32_t  RIICnDRR;                      /*  RIICnDRR        */
     566   
     567} r_io_riic_t;
     568
     569
     570/* Channel array defines of RIIC (2)*/
     571#ifdef  DECLARE_RIIC_CHANNELS
     572volatile struct st_riic*  RIIC[ RIIC_COUNT ] =
     573    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     574    RIIC_ADDRESS_LIST;
     575    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     576#endif  /* DECLARE_RIIC_CHANNELS */
     577/* End of channel array defines of RIIC (2)*/
     578
     579
     580/* <-SEC M1.10.1 */
     581/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     582/* <-QAC 0857 */
     583/* <-QAC 0639 */
    556584#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/romdec_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef ROMDEC_IODEFINE_H
    3030#define ROMDEC_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3134/* ->SEC M1.10.1 : Not magic number */
    3235
    33 struct st_romdec
    34 {                                                          /* ROMDEC           */
     36#define ROMDEC  (*(struct st_romdec  *)0xE8005000uL) /* ROMDEC */
     37
     38
     39#define ROMDECCROMEN (ROMDEC.CROMEN)
     40#define ROMDECCROMSY0 (ROMDEC.CROMSY0)
     41#define ROMDECCROMCTL0 (ROMDEC.CROMCTL0)
     42#define ROMDECCROMCTL1 (ROMDEC.CROMCTL1)
     43#define ROMDECCROMCTL3 (ROMDEC.CROMCTL3)
     44#define ROMDECCROMCTL4 (ROMDEC.CROMCTL4)
     45#define ROMDECCROMCTL5 (ROMDEC.CROMCTL5)
     46#define ROMDECCROMST0 (ROMDEC.CROMST0)
     47#define ROMDECCROMST1 (ROMDEC.CROMST1)
     48#define ROMDECCROMST3 (ROMDEC.CROMST3)
     49#define ROMDECCROMST4 (ROMDEC.CROMST4)
     50#define ROMDECCROMST5 (ROMDEC.CROMST5)
     51#define ROMDECCROMST6 (ROMDEC.CROMST6)
     52#define ROMDECCBUFST0 (ROMDEC.CBUFST0)
     53#define ROMDECCBUFST1 (ROMDEC.CBUFST1)
     54#define ROMDECCBUFST2 (ROMDEC.CBUFST2)
     55#define ROMDECHEAD00 (ROMDEC.HEAD00)
     56#define ROMDECHEAD01 (ROMDEC.HEAD01)
     57#define ROMDECHEAD02 (ROMDEC.HEAD02)
     58#define ROMDECHEAD03 (ROMDEC.HEAD03)
     59#define ROMDECSHEAD00 (ROMDEC.SHEAD00)
     60#define ROMDECSHEAD01 (ROMDEC.SHEAD01)
     61#define ROMDECSHEAD02 (ROMDEC.SHEAD02)
     62#define ROMDECSHEAD03 (ROMDEC.SHEAD03)
     63#define ROMDECSHEAD04 (ROMDEC.SHEAD04)
     64#define ROMDECSHEAD05 (ROMDEC.SHEAD05)
     65#define ROMDECSHEAD06 (ROMDEC.SHEAD06)
     66#define ROMDECSHEAD07 (ROMDEC.SHEAD07)
     67#define ROMDECHEAD20 (ROMDEC.HEAD20)
     68#define ROMDECHEAD21 (ROMDEC.HEAD21)
     69#define ROMDECHEAD22 (ROMDEC.HEAD22)
     70#define ROMDECHEAD23 (ROMDEC.HEAD23)
     71#define ROMDECSHEAD20 (ROMDEC.SHEAD20)
     72#define ROMDECSHEAD21 (ROMDEC.SHEAD21)
     73#define ROMDECSHEAD22 (ROMDEC.SHEAD22)
     74#define ROMDECSHEAD23 (ROMDEC.SHEAD23)
     75#define ROMDECSHEAD24 (ROMDEC.SHEAD24)
     76#define ROMDECSHEAD25 (ROMDEC.SHEAD25)
     77#define ROMDECSHEAD26 (ROMDEC.SHEAD26)
     78#define ROMDECSHEAD27 (ROMDEC.SHEAD27)
     79#define ROMDECCBUFCTL0 (ROMDEC.CBUFCTL0)
     80#define ROMDECCBUFCTL1 (ROMDEC.CBUFCTL1)
     81#define ROMDECCBUFCTL2 (ROMDEC.CBUFCTL2)
     82#define ROMDECCBUFCTL3 (ROMDEC.CBUFCTL3)
     83#define ROMDECCROMST0M (ROMDEC.CROMST0M)
     84#define ROMDECROMDECRST (ROMDEC.ROMDECRST)
     85#define ROMDECRSTSTAT (ROMDEC.RSTSTAT)
     86#define ROMDECSSI (ROMDEC.SSI)
     87#define ROMDECINTHOLD (ROMDEC.INTHOLD)
     88#define ROMDECINHINT (ROMDEC.INHINT)
     89#define ROMDECSTRMDIN0 (ROMDEC.STRMDIN0)
     90#define ROMDECSTRMDIN2 (ROMDEC.STRMDIN2)
     91#define ROMDECSTRMDOUT0 (ROMDEC.STRMDOUT0)
     92
     93#define ROMDEC_CROMCTL0_COUNT (2)
     94#define ROMDEC_CROMST0_COUNT (2)
     95#define ROMDEC_CBUFST0_COUNT (3)
     96#define ROMDEC_HEAD00_COUNT (4)
     97#define ROMDEC_SHEAD00_COUNT (8)
     98#define ROMDEC_HEAD20_COUNT (4)
     99#define ROMDEC_SHEAD20_COUNT (8)
     100#define ROMDEC_CBUFCTL0_COUNT (4)
     101#define ROMDEC_STRMDIN0_COUNT (2)
     102
     103
     104typedef struct st_romdec
     105{
     106                                                           /* ROMDEC           */
    35107    volatile uint8_t   CROMEN;                                 /*  CROMEN          */
    36108    volatile uint8_t   CROMSY0;                                /*  CROMSY0         */
    37 #define ROMDEC_CROMCTL0_COUNT 2
     109
     110/* #define ROMDEC_CROMCTL0_COUNT (2) */
    38111    volatile uint8_t   CROMCTL0;                               /*  CROMCTL0        */
    39112    volatile uint8_t   CROMCTL1;                               /*  CROMCTL1        */
    … …  
    42115    volatile uint8_t   CROMCTL4;                               /*  CROMCTL4        */
    43116    volatile uint8_t   CROMCTL5;                               /*  CROMCTL5        */
    44 #define ROMDEC_CROMST0_COUNT 2
     117
     118/* #define ROMDEC_CROMST0_COUNT (2) */
    45119    volatile uint8_t   CROMST0;                                /*  CROMST0         */
    46120    volatile uint8_t   CROMST1;                                /*  CROMST1         */
    … …  
    51125    volatile uint8_t   CROMST6;                                /*  CROMST6         */
    52126    volatile uint8_t   dummy25[5];                             /*                  */
    53 #define ROMDEC_CBUFST0_COUNT 3
     127
     128/* #define ROMDEC_CBUFST0_COUNT (3) */
    54129    volatile uint8_t   CBUFST0;                                /*  CBUFST0         */
    55130    volatile uint8_t   CBUFST1;                                /*  CBUFST1         */
    56131    volatile uint8_t   CBUFST2;                                /*  CBUFST2         */
    57132    volatile uint8_t   dummy26[1];                             /*                  */
    58 #define ROMDEC_HEAD00_COUNT 4
     133
     134/* #define ROMDEC_HEAD00_COUNT (4) */
    59135    volatile uint8_t   HEAD00;                                 /*  HEAD00          */
    60136    volatile uint8_t   HEAD01;                                 /*  HEAD01          */
    61137    volatile uint8_t   HEAD02;                                 /*  HEAD02          */
    62138    volatile uint8_t   HEAD03;                                 /*  HEAD03          */
    63 #define ROMDEC_SHEAD00_COUNT 8
     139
     140/* #define ROMDEC_SHEAD00_COUNT (8) */
    64141    volatile uint8_t   SHEAD00;                                /*  SHEAD00         */
    65142    volatile uint8_t   SHEAD01;                                /*  SHEAD01         */
    … …  
    70147    volatile uint8_t   SHEAD06;                                /*  SHEAD06         */
    71148    volatile uint8_t   SHEAD07;                                /*  SHEAD07         */
    72 #define ROMDEC_HEAD20_COUNT 4
     149
     150/* #define ROMDEC_HEAD20_COUNT (4) */
    73151    volatile uint8_t   HEAD20;                                 /*  HEAD20          */
    74152    volatile uint8_t   HEAD21;                                 /*  HEAD21          */
    75153    volatile uint8_t   HEAD22;                                 /*  HEAD22          */
    76154    volatile uint8_t   HEAD23;                                 /*  HEAD23          */
    77 #define ROMDEC_SHEAD20_COUNT 8
     155
     156/* #define ROMDEC_SHEAD20_COUNT (8) */
    78157    volatile uint8_t   SHEAD20;                                /*  SHEAD20         */
    79158    volatile uint8_t   SHEAD21;                                /*  SHEAD21         */
    … …  
    85164    volatile uint8_t   SHEAD27;                                /*  SHEAD27         */
    86165    volatile uint8_t   dummy27[16];                            /*                  */
    87 #define ROMDEC_CBUFCTL0_COUNT 4
     166
     167/* #define ROMDEC_CBUFCTL0_COUNT (4) */
    88168    volatile uint8_t   CBUFCTL0;                               /*  CBUFCTL0        */
    89169    volatile uint8_t   CBUFCTL1;                               /*  CBUFCTL1        */
    … …  
    100180    volatile uint8_t   INHINT;                                 /*  INHINT          */
    101181    volatile uint8_t   dummy31[246];                           /*                  */
    102 #define ROMDEC_STRMDIN0_COUNT 2
     182
     183/* #define ROMDEC_STRMDIN0_COUNT (2) */
    103184    volatile uint16_t STRMDIN0;                               /*  STRMDIN0        */
    104185    volatile uint16_t STRMDIN2;                               /*  STRMDIN2        */
    105186    volatile uint16_t STRMDOUT0;                              /*  STRMDOUT0       */
    106 };
     187} r_io_romdec_t;
    107188
    108189
    109 #define ROMDEC  (*(struct st_romdec  *)0xE8005000uL) /* ROMDEC */
    110 
    111 
    112 #define ROMDECCROMEN ROMDEC.CROMEN
    113 #define ROMDECCROMSY0 ROMDEC.CROMSY0
    114 #define ROMDECCROMCTL0 ROMDEC.CROMCTL0
    115 #define ROMDECCROMCTL1 ROMDEC.CROMCTL1
    116 #define ROMDECCROMCTL3 ROMDEC.CROMCTL3
    117 #define ROMDECCROMCTL4 ROMDEC.CROMCTL4
    118 #define ROMDECCROMCTL5 ROMDEC.CROMCTL5
    119 #define ROMDECCROMST0 ROMDEC.CROMST0
    120 #define ROMDECCROMST1 ROMDEC.CROMST1
    121 #define ROMDECCROMST3 ROMDEC.CROMST3
    122 #define ROMDECCROMST4 ROMDEC.CROMST4
    123 #define ROMDECCROMST5 ROMDEC.CROMST5
    124 #define ROMDECCROMST6 ROMDEC.CROMST6
    125 #define ROMDECCBUFST0 ROMDEC.CBUFST0
    126 #define ROMDECCBUFST1 ROMDEC.CBUFST1
    127 #define ROMDECCBUFST2 ROMDEC.CBUFST2
    128 #define ROMDECHEAD00 ROMDEC.HEAD00
    129 #define ROMDECHEAD01 ROMDEC.HEAD01
    130 #define ROMDECHEAD02 ROMDEC.HEAD02
    131 #define ROMDECHEAD03 ROMDEC.HEAD03
    132 #define ROMDECSHEAD00 ROMDEC.SHEAD00
    133 #define ROMDECSHEAD01 ROMDEC.SHEAD01
    134 #define ROMDECSHEAD02 ROMDEC.SHEAD02
    135 #define ROMDECSHEAD03 ROMDEC.SHEAD03
    136 #define ROMDECSHEAD04 ROMDEC.SHEAD04
    137 #define ROMDECSHEAD05 ROMDEC.SHEAD05
    138 #define ROMDECSHEAD06 ROMDEC.SHEAD06
    139 #define ROMDECSHEAD07 ROMDEC.SHEAD07
    140 #define ROMDECHEAD20 ROMDEC.HEAD20
    141 #define ROMDECHEAD21 ROMDEC.HEAD21
    142 #define ROMDECHEAD22 ROMDEC.HEAD22
    143 #define ROMDECHEAD23 ROMDEC.HEAD23
    144 #define ROMDECSHEAD20 ROMDEC.SHEAD20
    145 #define ROMDECSHEAD21 ROMDEC.SHEAD21
    146 #define ROMDECSHEAD22 ROMDEC.SHEAD22
    147 #define ROMDECSHEAD23 ROMDEC.SHEAD23
    148 #define ROMDECSHEAD24 ROMDEC.SHEAD24
    149 #define ROMDECSHEAD25 ROMDEC.SHEAD25
    150 #define ROMDECSHEAD26 ROMDEC.SHEAD26
    151 #define ROMDECSHEAD27 ROMDEC.SHEAD27
    152 #define ROMDECCBUFCTL0 ROMDEC.CBUFCTL0
    153 #define ROMDECCBUFCTL1 ROMDEC.CBUFCTL1
    154 #define ROMDECCBUFCTL2 ROMDEC.CBUFCTL2
    155 #define ROMDECCBUFCTL3 ROMDEC.CBUFCTL3
    156 #define ROMDECCROMST0M ROMDEC.CROMST0M
    157 #define ROMDECROMDECRST ROMDEC.ROMDECRST
    158 #define ROMDECRSTSTAT ROMDEC.RSTSTAT
    159 #define ROMDECSSI ROMDEC.SSI
    160 #define ROMDECINTHOLD ROMDEC.INTHOLD
    161 #define ROMDECINHINT ROMDEC.INHINT
    162 #define ROMDECSTRMDIN0 ROMDEC.STRMDIN0
    163 #define ROMDECSTRMDIN2 ROMDEC.STRMDIN2
    164 #define ROMDECSTRMDOUT0 ROMDEC.STRMDOUT0
    165190/* <-SEC M1.10.1 */
     191/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     192/* <-QAC 0857 */
     193/* <-QAC 0639 */
    166194#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef RSCAN0_IODEFINE_H
    … …  
    3131/* ->QAC 0639 : Over 127 members (C90) */
    3232/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3334/* ->SEC M1.10.1 : Not magic number */
    3435
    35 struct st_rscan0
    36 {                                                          /* RSCAN0           */
    37 /* start of struct st_rscan_from_rscan0cncfg */
    38     union iodefine_reg32_t  C0CFG;                         /*  C0CFG           */
    39     union iodefine_reg32_t  C0CTR;                         /*  C0CTR           */
    40     union iodefine_reg32_t  C0STS;                         /*  C0STS           */
    41     union iodefine_reg32_t  C0ERFL;                        /*  C0ERFL          */
    42 /* end of struct st_rscan_from_rscan0cncfg */
    43    
    44 /* start of struct st_rscan_from_rscan0cncfg */
    45     union iodefine_reg32_t  C1CFG;                         /*  C1CFG           */
    46     union iodefine_reg32_t  C1CTR;                         /*  C1CTR           */
    47     union iodefine_reg32_t  C1STS;                         /*  C1STS           */
    48     union iodefine_reg32_t  C1ERFL;                        /*  C1ERFL          */
    49 /* end of struct st_rscan_from_rscan0cncfg */
    50    
    51 /* start of struct st_rscan_from_rscan0cncfg */
    52     union iodefine_reg32_t  C2CFG;                         /*  C2CFG           */
    53     union iodefine_reg32_t  C2CTR;                         /*  C2CTR           */
    54     union iodefine_reg32_t  C2STS;                         /*  C2STS           */
    55     union iodefine_reg32_t  C2ERFL;                        /*  C2ERFL          */
    56 /* end of struct st_rscan_from_rscan0cncfg */
    57    
    58 /* start of struct st_rscan_from_rscan0cncfg */
    59     union iodefine_reg32_t  C3CFG;                         /*  C3CFG           */
    60     union iodefine_reg32_t  C3CTR;                         /*  C3CTR           */
    61     union iodefine_reg32_t  C3STS;                         /*  C3STS           */
    62     union iodefine_reg32_t  C3ERFL;                        /*  C3ERFL          */
    63 /* end of struct st_rscan_from_rscan0cncfg */
    64    
    65 /* start of struct st_rscan_from_rscan0cncfg */
    66     union iodefine_reg32_t  C4CFG;                         /*  C4CFG           */
    67     union iodefine_reg32_t  C4CTR;                         /*  C4CTR           */
    68     union iodefine_reg32_t  C4STS;                         /*  C4STS           */
    69     union iodefine_reg32_t  C4ERFL;                        /*  C4ERFL          */
    70 /* end of struct st_rscan_from_rscan0cncfg */
    71    
    72     volatile uint8_t   dummy159[52];                           /*                  */
    73     union iodefine_reg32_t  GCFG;                          /*  GCFG            */
    74     union iodefine_reg32_t  GCTR;                          /*  GCTR            */
    75     union iodefine_reg32_t  GSTS;                          /*  GSTS            */
    76     union iodefine_reg32_t  GERFL;                         /*  GERFL           */
    77     union iodefine_reg32_16_t  GTSC;                       /*  GTSC            */
    78     union iodefine_reg32_t  GAFLECTR;                      /*  GAFLECTR        */
    79 #define RSCAN0_GAFLCFG0_COUNT 2
    80     union iodefine_reg32_t  GAFLCFG0;                      /*  GAFLCFG0        */
    81     union iodefine_reg32_t  GAFLCFG1;                      /*  GAFLCFG1        */
    82     union iodefine_reg32_t  RMNB;                          /*  RMNB            */
    83 #define RSCAN0_RMND0_COUNT 3
    84     union iodefine_reg32_t  RMND0;                         /*  RMND0           */
    85     union iodefine_reg32_t  RMND1;                         /*  RMND1           */
    86     union iodefine_reg32_t  RMND2;                         /*  RMND2           */
    87    
    88     volatile uint8_t   dummy160[4];                            /*                  */
    89 #define RSCAN0_RFCC0_COUNT 8
    90     union iodefine_reg32_t  RFCC0;                         /*  RFCC0           */
    91     union iodefine_reg32_t  RFCC1;                         /*  RFCC1           */
    92     union iodefine_reg32_t  RFCC2;                         /*  RFCC2           */
    93     union iodefine_reg32_t  RFCC3;                         /*  RFCC3           */
    94     union iodefine_reg32_t  RFCC4;                         /*  RFCC4           */
    95     union iodefine_reg32_t  RFCC5;                         /*  RFCC5           */
    96     union iodefine_reg32_t  RFCC6;                         /*  RFCC6           */
    97     union iodefine_reg32_t  RFCC7;                         /*  RFCC7           */
    98 #define RSCAN0_RFSTS0_COUNT 8
    99     union iodefine_reg32_t  RFSTS0;                        /*  RFSTS0          */
    100     union iodefine_reg32_t  RFSTS1;                        /*  RFSTS1          */
    101     union iodefine_reg32_t  RFSTS2;                        /*  RFSTS2          */
    102     union iodefine_reg32_t  RFSTS3;                        /*  RFSTS3          */
    103     union iodefine_reg32_t  RFSTS4;                        /*  RFSTS4          */
    104     union iodefine_reg32_t  RFSTS5;                        /*  RFSTS5          */
    105     union iodefine_reg32_t  RFSTS6;                        /*  RFSTS6          */
    106     union iodefine_reg32_t  RFSTS7;                        /*  RFSTS7          */
    107 #define RSCAN0_RFPCTR0_COUNT 8
    108     union iodefine_reg32_t  RFPCTR0;                       /*  RFPCTR0         */
    109     union iodefine_reg32_t  RFPCTR1;                       /*  RFPCTR1         */
    110     union iodefine_reg32_t  RFPCTR2;                       /*  RFPCTR2         */
    111     union iodefine_reg32_t  RFPCTR3;                       /*  RFPCTR3         */
    112     union iodefine_reg32_t  RFPCTR4;                       /*  RFPCTR4         */
    113     union iodefine_reg32_t  RFPCTR5;                       /*  RFPCTR5         */
    114     union iodefine_reg32_t  RFPCTR6;                       /*  RFPCTR6         */
    115     union iodefine_reg32_t  RFPCTR7;                       /*  RFPCTR7         */
    116 #define RSCAN0_CFCC0_COUNT 15
    117     union iodefine_reg32_t  CFCC0;                         /*  CFCC0           */
    118     union iodefine_reg32_t  CFCC1;                         /*  CFCC1           */
    119     union iodefine_reg32_t  CFCC2;                         /*  CFCC2           */
    120     union iodefine_reg32_t  CFCC3;                         /*  CFCC3           */
    121     union iodefine_reg32_t  CFCC4;                         /*  CFCC4           */
    122     union iodefine_reg32_t  CFCC5;                         /*  CFCC5           */
    123     union iodefine_reg32_t  CFCC6;                         /*  CFCC6           */
    124     union iodefine_reg32_t  CFCC7;                         /*  CFCC7           */
    125     union iodefine_reg32_t  CFCC8;                         /*  CFCC8           */
    126     union iodefine_reg32_t  CFCC9;                         /*  CFCC9           */
    127     union iodefine_reg32_t  CFCC10;                        /*  CFCC10          */
    128     union iodefine_reg32_t  CFCC11;                        /*  CFCC11          */
    129     union iodefine_reg32_t  CFCC12;                        /*  CFCC12          */
    130     union iodefine_reg32_t  CFCC13;                        /*  CFCC13          */
    131     union iodefine_reg32_t  CFCC14;                        /*  CFCC14          */
    132    
    133     volatile uint8_t   dummy161[36];                           /*                  */
    134 #define RSCAN0_CFSTS0_COUNT 15
    135     union iodefine_reg32_t  CFSTS0;                        /*  CFSTS0          */
    136     union iodefine_reg32_t  CFSTS1;                        /*  CFSTS1          */
    137     union iodefine_reg32_t  CFSTS2;                        /*  CFSTS2          */
    138     union iodefine_reg32_t  CFSTS3;                        /*  CFSTS3          */
    139     union iodefine_reg32_t  CFSTS4;                        /*  CFSTS4          */
    140     union iodefine_reg32_t  CFSTS5;                        /*  CFSTS5          */
    141     union iodefine_reg32_t  CFSTS6;                        /*  CFSTS6          */
    142     union iodefine_reg32_t  CFSTS7;                        /*  CFSTS7          */
    143     union iodefine_reg32_t  CFSTS8;                        /*  CFSTS8          */
    144     union iodefine_reg32_t  CFSTS9;                        /*  CFSTS9          */
    145     union iodefine_reg32_t  CFSTS10;                       /*  CFSTS10         */
    146     union iodefine_reg32_t  CFSTS11;                       /*  CFSTS11         */
    147     union iodefine_reg32_t  CFSTS12;                       /*  CFSTS12         */
    148     union iodefine_reg32_t  CFSTS13;                       /*  CFSTS13         */
    149     union iodefine_reg32_t  CFSTS14;                       /*  CFSTS14         */
    150    
    151     volatile uint8_t   dummy162[36];                           /*                  */
    152 #define RSCAN0_CFPCTR0_COUNT 15
    153     union iodefine_reg32_t  CFPCTR0;                       /*  CFPCTR0         */
    154     union iodefine_reg32_t  CFPCTR1;                       /*  CFPCTR1         */
    155     union iodefine_reg32_t  CFPCTR2;                       /*  CFPCTR2         */
    156     union iodefine_reg32_t  CFPCTR3;                       /*  CFPCTR3         */
    157     union iodefine_reg32_t  CFPCTR4;                       /*  CFPCTR4         */
    158     union iodefine_reg32_t  CFPCTR5;                       /*  CFPCTR5         */
    159     union iodefine_reg32_t  CFPCTR6;                       /*  CFPCTR6         */
    160     union iodefine_reg32_t  CFPCTR7;                       /*  CFPCTR7         */
    161     union iodefine_reg32_t  CFPCTR8;                       /*  CFPCTR8         */
    162     union iodefine_reg32_t  CFPCTR9;                       /*  CFPCTR9         */
    163     union iodefine_reg32_t  CFPCTR10;                      /*  CFPCTR10        */
    164     union iodefine_reg32_t  CFPCTR11;                      /*  CFPCTR11        */
    165     union iodefine_reg32_t  CFPCTR12;                      /*  CFPCTR12        */
    166     union iodefine_reg32_t  CFPCTR13;                      /*  CFPCTR13        */
    167     union iodefine_reg32_t  CFPCTR14;                      /*  CFPCTR14        */
    168    
    169     volatile uint8_t   dummy163[36];                           /*                  */
    170     union iodefine_reg32_t  FESTS;                         /*  FESTS           */
    171     union iodefine_reg32_t  FFSTS;                         /*  FFSTS           */
    172     union iodefine_reg32_t  FMSTS;                         /*  FMSTS           */
    173     union iodefine_reg32_t  RFISTS;                        /*  RFISTS          */
    174     union iodefine_reg32_t  CFRISTS;                       /*  CFRISTS         */
    175     union iodefine_reg32_t  CFTISTS;                       /*  CFTISTS         */
    176    
    177 #define RSCAN0_TMC0_COUNT 80
    178     volatile uint8_t   TMC0;                                   /*  TMC0            */
    179     volatile uint8_t   TMC1;                                   /*  TMC1            */
    180     volatile uint8_t   TMC2;                                   /*  TMC2            */
    181     volatile uint8_t   TMC3;                                   /*  TMC3            */
    182     volatile uint8_t   TMC4;                                   /*  TMC4            */
    183     volatile uint8_t   TMC5;                                   /*  TMC5            */
    184     volatile uint8_t   TMC6;                                   /*  TMC6            */
    185     volatile uint8_t   TMC7;                                   /*  TMC7            */
    186     volatile uint8_t   TMC8;                                   /*  TMC8            */
    187     volatile uint8_t   TMC9;                                   /*  TMC9            */
    188     volatile uint8_t   TMC10;                                  /*  TMC10           */
    189     volatile uint8_t   TMC11;                                  /*  TMC11           */
    190     volatile uint8_t   TMC12;                                  /*  TMC12           */
    191     volatile uint8_t   TMC13;                                  /*  TMC13           */
    192     volatile uint8_t   TMC14;                                  /*  TMC14           */
    193     volatile uint8_t   TMC15;                                  /*  TMC15           */
    194     volatile uint8_t   TMC16;                                  /*  TMC16           */
    195     volatile uint8_t   TMC17;                                  /*  TMC17           */
    196     volatile uint8_t   TMC18;                                  /*  TMC18           */
    197     volatile uint8_t   TMC19;                                  /*  TMC19           */
    198     volatile uint8_t   TMC20;                                  /*  TMC20           */
    199     volatile uint8_t   TMC21;                                  /*  TMC21           */
    200     volatile uint8_t   TMC22;                                  /*  TMC22           */
    201     volatile uint8_t   TMC23;                                  /*  TMC23           */
    202     volatile uint8_t   TMC24;                                  /*  TMC24           */
    203     volatile uint8_t   TMC25;                                  /*  TMC25           */
    204     volatile uint8_t   TMC26;                                  /*  TMC26           */
    205     volatile uint8_t   TMC27;                                  /*  TMC27           */
    206     volatile uint8_t   TMC28;                                  /*  TMC28           */
    207     volatile uint8_t   TMC29;                                  /*  TMC29           */
    208     volatile uint8_t   TMC30;                                  /*  TMC30           */
    209     volatile uint8_t   TMC31;                                  /*  TMC31           */
    210     volatile uint8_t   TMC32;                                  /*  TMC32           */
    211     volatile uint8_t   TMC33;                                  /*  TMC33           */
    212     volatile uint8_t   TMC34;                                  /*  TMC34           */
    213     volatile uint8_t   TMC35;                                  /*  TMC35           */
    214     volatile uint8_t   TMC36;                                  /*  TMC36           */
    215     volatile uint8_t   TMC37;                                  /*  TMC37           */
    216     volatile uint8_t   TMC38;                                  /*  TMC38           */
    217     volatile uint8_t   TMC39;                                  /*  TMC39           */
    218     volatile uint8_t   TMC40;                                  /*  TMC40           */
    219     volatile uint8_t   TMC41;                                  /*  TMC41           */
    220     volatile uint8_t   TMC42;                                  /*  TMC42           */
    221     volatile uint8_t   TMC43;                                  /*  TMC43           */
    222     volatile uint8_t   TMC44;                                  /*  TMC44           */
    223     volatile uint8_t   TMC45;                                  /*  TMC45           */
    224     volatile uint8_t   TMC46;                                  /*  TMC46           */
    225     volatile uint8_t   TMC47;                                  /*  TMC47           */
    226     volatile uint8_t   TMC48;                                  /*  TMC48           */
    227     volatile uint8_t   TMC49;                                  /*  TMC49           */
    228     volatile uint8_t   TMC50;                                  /*  TMC50           */
    229     volatile uint8_t   TMC51;                                  /*  TMC51           */
    230     volatile uint8_t   TMC52;                                  /*  TMC52           */
    231     volatile uint8_t   TMC53;                                  /*  TMC53           */
    232     volatile uint8_t   TMC54;                                  /*  TMC54           */
    233     volatile uint8_t   TMC55;                                  /*  TMC55           */
    234     volatile uint8_t   TMC56;                                  /*  TMC56           */
    235     volatile uint8_t   TMC57;                                  /*  TMC57           */
    236     volatile uint8_t   TMC58;                                  /*  TMC58           */
    237     volatile uint8_t   TMC59;                                  /*  TMC59           */
    238     volatile uint8_t   TMC60;                                  /*  TMC60           */
    239     volatile uint8_t   TMC61;                                  /*  TMC61           */
    240     volatile uint8_t   TMC62;                                  /*  TMC62           */
    241     volatile uint8_t   TMC63;                                  /*  TMC63           */
    242     volatile uint8_t   TMC64;                                  /*  TMC64           */
    243     volatile uint8_t   TMC65;                                  /*  TMC65           */
    244     volatile uint8_t   TMC66;                                  /*  TMC66           */
    245     volatile uint8_t   TMC67;                                  /*  TMC67           */
    246     volatile uint8_t   TMC68;                                  /*  TMC68           */
    247     volatile uint8_t   TMC69;                                  /*  TMC69           */
    248     volatile uint8_t   TMC70;                                  /*  TMC70           */
    249     volatile uint8_t   TMC71;                                  /*  TMC71           */
    250     volatile uint8_t   TMC72;                                  /*  TMC72           */
    251     volatile uint8_t   TMC73;                                  /*  TMC73           */
    252     volatile uint8_t   TMC74;                                  /*  TMC74           */
    253     volatile uint8_t   TMC75;                                  /*  TMC75           */
    254     volatile uint8_t   TMC76;                                  /*  TMC76           */
    255     volatile uint8_t   TMC77;                                  /*  TMC77           */
    256     volatile uint8_t   TMC78;                                  /*  TMC78           */
    257     volatile uint8_t   TMC79;                                  /*  TMC79           */
    258     volatile uint8_t   dummy164[48];                           /*                  */
    259 #define RSCAN0_TMSTS0_COUNT 80
    260     volatile uint8_t   TMSTS0;                                 /*  TMSTS0          */
    261     volatile uint8_t   TMSTS1;                                 /*  TMSTS1          */
    262     volatile uint8_t   TMSTS2;                                 /*  TMSTS2          */
    263     volatile uint8_t   TMSTS3;                                 /*  TMSTS3          */
    264     volatile uint8_t   TMSTS4;                                 /*  TMSTS4          */
    265     volatile uint8_t   TMSTS5;                                 /*  TMSTS5          */
    266     volatile uint8_t   TMSTS6;                                 /*  TMSTS6          */
    267     volatile uint8_t   TMSTS7;                                 /*  TMSTS7          */
    268     volatile uint8_t   TMSTS8;                                 /*  TMSTS8          */
    269     volatile uint8_t   TMSTS9;                                 /*  TMSTS9          */
    270     volatile uint8_t   TMSTS10;                                /*  TMSTS10         */
    271     volatile uint8_t   TMSTS11;                                /*  TMSTS11         */
    272     volatile uint8_t   TMSTS12;                                /*  TMSTS12         */
    273     volatile uint8_t   TMSTS13;                                /*  TMSTS13         */
    274     volatile uint8_t   TMSTS14;                                /*  TMSTS14         */
    275     volatile uint8_t   TMSTS15;                                /*  TMSTS15         */
    276     volatile uint8_t   TMSTS16;                                /*  TMSTS16         */
    277     volatile uint8_t   TMSTS17;                                /*  TMSTS17         */
    278     volatile uint8_t   TMSTS18;                                /*  TMSTS18         */
    279     volatile uint8_t   TMSTS19;                                /*  TMSTS19         */
    280     volatile uint8_t   TMSTS20;                                /*  TMSTS20         */
    281     volatile uint8_t   TMSTS21;                                /*  TMSTS21         */
    282     volatile uint8_t   TMSTS22;                                /*  TMSTS22         */
    283     volatile uint8_t   TMSTS23;                                /*  TMSTS23         */
    284     volatile uint8_t   TMSTS24;                                /*  TMSTS24         */
    285     volatile uint8_t   TMSTS25;                                /*  TMSTS25         */
    286     volatile uint8_t   TMSTS26;                                /*  TMSTS26         */
    287     volatile uint8_t   TMSTS27;                                /*  TMSTS27         */
    288     volatile uint8_t   TMSTS28;                                /*  TMSTS28         */
    289     volatile uint8_t   TMSTS29;                                /*  TMSTS29         */
    290     volatile uint8_t   TMSTS30;                                /*  TMSTS30         */
    291     volatile uint8_t   TMSTS31;                                /*  TMSTS31         */
    292     volatile uint8_t   TMSTS32;                                /*  TMSTS32         */
    293     volatile uint8_t   TMSTS33;                                /*  TMSTS33         */
    294     volatile uint8_t   TMSTS34;                                /*  TMSTS34         */
    295     volatile uint8_t   TMSTS35;                                /*  TMSTS35         */
    296     volatile uint8_t   TMSTS36;                                /*  TMSTS36         */
    297     volatile uint8_t   TMSTS37;                                /*  TMSTS37         */
    298     volatile uint8_t   TMSTS38;                                /*  TMSTS38         */
    299     volatile uint8_t   TMSTS39;                                /*  TMSTS39         */
    300     volatile uint8_t   TMSTS40;                                /*  TMSTS40         */
    301     volatile uint8_t   TMSTS41;                                /*  TMSTS41         */
    302     volatile uint8_t   TMSTS42;                                /*  TMSTS42         */
    303     volatile uint8_t   TMSTS43;                                /*  TMSTS43         */
    304     volatile uint8_t   TMSTS44;                                /*  TMSTS44         */
    305     volatile uint8_t   TMSTS45;                                /*  TMSTS45         */
    306     volatile uint8_t   TMSTS46;                                /*  TMSTS46         */
    307     volatile uint8_t   TMSTS47;                                /*  TMSTS47         */
    308     volatile uint8_t   TMSTS48;                                /*  TMSTS48         */
    309     volatile uint8_t   TMSTS49;                                /*  TMSTS49         */
    310     volatile uint8_t   TMSTS50;                                /*  TMSTS50         */
    311     volatile uint8_t   TMSTS51;                                /*  TMSTS51         */
    312     volatile uint8_t   TMSTS52;                                /*  TMSTS52         */
    313     volatile uint8_t   TMSTS53;                                /*  TMSTS53         */
    314     volatile uint8_t   TMSTS54;                                /*  TMSTS54         */
    315     volatile uint8_t   TMSTS55;                                /*  TMSTS55         */
    316     volatile uint8_t   TMSTS56;                                /*  TMSTS56         */
    317     volatile uint8_t   TMSTS57;                                /*  TMSTS57         */
    318     volatile uint8_t   TMSTS58;                                /*  TMSTS58         */
    319     volatile uint8_t   TMSTS59;                                /*  TMSTS59         */
    320     volatile uint8_t   TMSTS60;                                /*  TMSTS60         */
    321     volatile uint8_t   TMSTS61;                                /*  TMSTS61         */
    322     volatile uint8_t   TMSTS62;                                /*  TMSTS62         */
    323     volatile uint8_t   TMSTS63;                                /*  TMSTS63         */
    324     volatile uint8_t   TMSTS64;                                /*  TMSTS64         */
    325     volatile uint8_t   TMSTS65;                                /*  TMSTS65         */
    326     volatile uint8_t   TMSTS66;                                /*  TMSTS66         */
    327     volatile uint8_t   TMSTS67;                                /*  TMSTS67         */
    328     volatile uint8_t   TMSTS68;                                /*  TMSTS68         */
    329     volatile uint8_t   TMSTS69;                                /*  TMSTS69         */
    330     volatile uint8_t   TMSTS70;                                /*  TMSTS70         */
    331     volatile uint8_t   TMSTS71;                                /*  TMSTS71         */
    332     volatile uint8_t   TMSTS72;                                /*  TMSTS72         */
    333     volatile uint8_t   TMSTS73;                                /*  TMSTS73         */
    334     volatile uint8_t   TMSTS74;                                /*  TMSTS74         */
    335     volatile uint8_t   TMSTS75;                                /*  TMSTS75         */
    336     volatile uint8_t   TMSTS76;                                /*  TMSTS76         */
    337     volatile uint8_t   TMSTS77;                                /*  TMSTS77         */
    338     volatile uint8_t   TMSTS78;                                /*  TMSTS78         */
    339     volatile uint8_t   TMSTS79;                                /*  TMSTS79         */
    340     volatile uint8_t   dummy165[48];                           /*                  */
    341 #define RSCAN0_TMTRSTS0_COUNT 3
    342     union iodefine_reg32_t  TMTRSTS0;                      /*  TMTRSTS0        */
    343     union iodefine_reg32_t  TMTRSTS1;                      /*  TMTRSTS1        */
    344     union iodefine_reg32_t  TMTRSTS2;                      /*  TMTRSTS2        */
    345    
    346     volatile uint8_t   dummy166[4];                            /*                  */
    347 #define RSCAN0_TMTARSTS0_COUNT 3
    348     union iodefine_reg32_t  TMTARSTS0;                     /*  TMTARSTS0       */
    349     union iodefine_reg32_t  TMTARSTS1;                     /*  TMTARSTS1       */
    350     union iodefine_reg32_t  TMTARSTS2;                     /*  TMTARSTS2       */
    351    
    352     volatile uint8_t   dummy167[4];                            /*                  */
    353 #define RSCAN0_TMTCSTS0_COUNT 3
    354     union iodefine_reg32_t  TMTCSTS0;                      /*  TMTCSTS0        */
    355     union iodefine_reg32_t  TMTCSTS1;                      /*  TMTCSTS1        */
    356     union iodefine_reg32_t  TMTCSTS2;                      /*  TMTCSTS2        */
    357    
    358     volatile uint8_t   dummy168[4];                            /*                  */
    359 #define RSCAN0_TMTASTS0_COUNT 3
    360     union iodefine_reg32_t  TMTASTS0;                      /*  TMTASTS0        */
    361     union iodefine_reg32_t  TMTASTS1;                      /*  TMTASTS1        */
    362     union iodefine_reg32_t  TMTASTS2;                      /*  TMTASTS2        */
    363    
    364     volatile uint8_t   dummy169[4];                            /*                  */
    365 #define RSCAN0_TMIEC0_COUNT 3
    366     union iodefine_reg32_t  TMIEC0;                        /*  TMIEC0          */
    367     union iodefine_reg32_t  TMIEC1;                        /*  TMIEC1          */
    368     union iodefine_reg32_t  TMIEC2;                        /*  TMIEC2          */
    369    
    370     volatile uint8_t   dummy170[4];                            /*                  */
    371 #define RSCAN0_TXQCC0_COUNT 5
    372     union iodefine_reg32_t  TXQCC0;                        /*  TXQCC0          */
    373     union iodefine_reg32_t  TXQCC1;                        /*  TXQCC1          */
    374     union iodefine_reg32_t  TXQCC2;                        /*  TXQCC2          */
    375     union iodefine_reg32_t  TXQCC3;                        /*  TXQCC3          */
    376     union iodefine_reg32_t  TXQCC4;                        /*  TXQCC4          */
    377    
    378     volatile uint8_t   dummy171[12];                           /*                  */
    379 #define RSCAN0_TXQSTS0_COUNT 5
    380     union iodefine_reg32_t  TXQSTS0;                       /*  TXQSTS0         */
    381     union iodefine_reg32_t  TXQSTS1;                       /*  TXQSTS1         */
    382     union iodefine_reg32_t  TXQSTS2;                       /*  TXQSTS2         */
    383     union iodefine_reg32_t  TXQSTS3;                       /*  TXQSTS3         */
    384     union iodefine_reg32_t  TXQSTS4;                       /*  TXQSTS4         */
    385    
    386     volatile uint8_t   dummy172[12];                           /*                  */
    387 #define RSCAN0_TXQPCTR0_COUNT 5
    388     union iodefine_reg32_t  TXQPCTR0;                      /*  TXQPCTR0        */
    389     union iodefine_reg32_t  TXQPCTR1;                      /*  TXQPCTR1        */
    390     union iodefine_reg32_t  TXQPCTR2;                      /*  TXQPCTR2        */
    391     union iodefine_reg32_t  TXQPCTR3;                      /*  TXQPCTR3        */
    392     union iodefine_reg32_t  TXQPCTR4;                      /*  TXQPCTR4        */
    393    
    394     volatile uint8_t   dummy173[12];                           /*                  */
    395 #define RSCAN0_THLCC0_COUNT 5
    396     union iodefine_reg32_t  THLCC0;                        /*  THLCC0          */
    397     union iodefine_reg32_t  THLCC1;                        /*  THLCC1          */
    398     union iodefine_reg32_t  THLCC2;                        /*  THLCC2          */
    399     union iodefine_reg32_t  THLCC3;                        /*  THLCC3          */
    400     union iodefine_reg32_t  THLCC4;                        /*  THLCC4          */
    401    
    402     volatile uint8_t   dummy174[12];                           /*                  */
    403 #define RSCAN0_THLSTS0_COUNT 5
    404     union iodefine_reg32_t  THLSTS0;                       /*  THLSTS0         */
    405     union iodefine_reg32_t  THLSTS1;                       /*  THLSTS1         */
    406     union iodefine_reg32_t  THLSTS2;                       /*  THLSTS2         */
    407     union iodefine_reg32_t  THLSTS3;                       /*  THLSTS3         */
    408     union iodefine_reg32_t  THLSTS4;                       /*  THLSTS4         */
    409    
    410     volatile uint8_t   dummy175[12];                           /*                  */
    411 #define RSCAN0_THLPCTR0_COUNT 5
    412     union iodefine_reg32_t  THLPCTR0;                      /*  THLPCTR0        */
    413     union iodefine_reg32_t  THLPCTR1;                      /*  THLPCTR1        */
    414     union iodefine_reg32_t  THLPCTR2;                      /*  THLPCTR2        */
    415     union iodefine_reg32_t  THLPCTR3;                      /*  THLPCTR3        */
    416     union iodefine_reg32_t  THLPCTR4;                      /*  THLPCTR4        */
    417    
    418     volatile uint8_t   dummy176[12];                           /*                  */
    419 #define RSCAN0_GTINTSTS0_COUNT 2
    420     union iodefine_reg32_t  GTINTSTS0;                     /*  GTINTSTS0       */
    421     union iodefine_reg32_t  GTINTSTS1;                     /*  GTINTSTS1       */
    422     union iodefine_reg32_t  GTSTCFG;                       /*  GTSTCFG         */
    423     union iodefine_reg32_t  GTSTCTR;                       /*  GTSTCTR         */
    424    
    425     volatile uint8_t   dummy177[12];                           /*                  */
    426     union iodefine_reg32_16_t  GLOCKK;                     /*  GLOCKK          */
    427    
    428     volatile uint8_t   dummy178[128];                          /*                  */
    429    
    430 /* start of struct st_rscan_from_rscan0gaflidj */
    431     union iodefine_reg32_t  GAFLID0;                       /*  GAFLID0         */
    432     union iodefine_reg32_t  GAFLM0;                        /*  GAFLM0          */
    433     union iodefine_reg32_t  GAFLP00;                       /*  GAFLP00         */
    434     union iodefine_reg32_t  GAFLP10;                       /*  GAFLP10         */
    435 /* end of struct st_rscan_from_rscan0gaflidj */
    436    
    437 /* start of struct st_rscan_from_rscan0gaflidj */
    438     union iodefine_reg32_t  GAFLID1;                       /*  GAFLID1         */
    439     union iodefine_reg32_t  GAFLM1;                        /*  GAFLM1          */
    440     union iodefine_reg32_t  GAFLP01;                       /*  GAFLP01         */
    441     union iodefine_reg32_t  GAFLP11;                       /*  GAFLP11         */
    442 /* end of struct st_rscan_from_rscan0gaflidj */
    443    
    444 /* start of struct st_rscan_from_rscan0gaflidj */
    445     union iodefine_reg32_t  GAFLID2;                       /*  GAFLID2         */
    446     union iodefine_reg32_t  GAFLM2;                        /*  GAFLM2          */
    447     union iodefine_reg32_t  GAFLP02;                       /*  GAFLP02         */
    448     union iodefine_reg32_t  GAFLP12;                       /*  GAFLP12         */
    449 /* end of struct st_rscan_from_rscan0gaflidj */
    450    
    451 /* start of struct st_rscan_from_rscan0gaflidj */
    452     union iodefine_reg32_t  GAFLID3;                       /*  GAFLID3         */
    453     union iodefine_reg32_t  GAFLM3;                        /*  GAFLM3          */
    454     union iodefine_reg32_t  GAFLP03;                       /*  GAFLP03         */
    455     union iodefine_reg32_t  GAFLP13;                       /*  GAFLP13         */
    456 /* end of struct st_rscan_from_rscan0gaflidj */
    457    
    458 /* start of struct st_rscan_from_rscan0gaflidj */
    459     union iodefine_reg32_t  GAFLID4;                       /*  GAFLID4         */
    460     union iodefine_reg32_t  GAFLM4;                        /*  GAFLM4          */
    461     union iodefine_reg32_t  GAFLP04;                       /*  GAFLP04         */
    462     union iodefine_reg32_t  GAFLP14;                       /*  GAFLP14         */
    463 /* end of struct st_rscan_from_rscan0gaflidj */
    464    
    465 /* start of struct st_rscan_from_rscan0gaflidj */
    466     union iodefine_reg32_t  GAFLID5;                       /*  GAFLID5         */
    467     union iodefine_reg32_t  GAFLM5;                        /*  GAFLM5          */
    468     union iodefine_reg32_t  GAFLP05;                       /*  GAFLP05         */
    469     union iodefine_reg32_t  GAFLP15;                       /*  GAFLP15         */
    470 /* end of struct st_rscan_from_rscan0gaflidj */
    471    
    472 /* start of struct st_rscan_from_rscan0gaflidj */
    473     union iodefine_reg32_t  GAFLID6;                       /*  GAFLID6         */
    474     union iodefine_reg32_t  GAFLM6;                        /*  GAFLM6          */
    475     union iodefine_reg32_t  GAFLP06;                       /*  GAFLP06         */
    476     union iodefine_reg32_t  GAFLP16;                       /*  GAFLP16         */
    477 /* end of struct st_rscan_from_rscan0gaflidj */
    478    
    479 /* start of struct st_rscan_from_rscan0gaflidj */
    480     union iodefine_reg32_t  GAFLID7;                       /*  GAFLID7         */
    481     union iodefine_reg32_t  GAFLM7;                        /*  GAFLM7          */
    482     union iodefine_reg32_t  GAFLP07;                       /*  GAFLP07         */
    483     union iodefine_reg32_t  GAFLP17;                       /*  GAFLP17         */
    484 /* end of struct st_rscan_from_rscan0gaflidj */
    485    
    486 /* start of struct st_rscan_from_rscan0gaflidj */
    487     union iodefine_reg32_t  GAFLID8;                       /*  GAFLID8         */
    488     union iodefine_reg32_t  GAFLM8;                        /*  GAFLM8          */
    489     union iodefine_reg32_t  GAFLP08;                       /*  GAFLP08         */
    490     union iodefine_reg32_t  GAFLP18;                       /*  GAFLP18         */
    491 /* end of struct st_rscan_from_rscan0gaflidj */
    492    
    493 /* start of struct st_rscan_from_rscan0gaflidj */
    494     union iodefine_reg32_t  GAFLID9;                       /*  GAFLID9         */
    495     union iodefine_reg32_t  GAFLM9;                        /*  GAFLM9          */
    496     union iodefine_reg32_t  GAFLP09;                       /*  GAFLP09         */
    497     union iodefine_reg32_t  GAFLP19;                       /*  GAFLP19         */
    498 /* end of struct st_rscan_from_rscan0gaflidj */
    499    
    500 /* start of struct st_rscan_from_rscan0gaflidj */
    501     union iodefine_reg32_t  GAFLID10;                      /*  GAFLID10        */
    502     union iodefine_reg32_t  GAFLM10;                       /*  GAFLM10         */
    503     union iodefine_reg32_t  GAFLP010;                      /*  GAFLP010        */
    504     union iodefine_reg32_t  GAFLP110;                      /*  GAFLP110        */
    505 /* end of struct st_rscan_from_rscan0gaflidj */
    506    
    507 /* start of struct st_rscan_from_rscan0gaflidj */
    508     union iodefine_reg32_t  GAFLID11;                      /*  GAFLID11        */
    509     union iodefine_reg32_t  GAFLM11;                       /*  GAFLM11         */
    510     union iodefine_reg32_t  GAFLP011;                      /*  GAFLP011        */
    511     union iodefine_reg32_t  GAFLP111;                      /*  GAFLP111        */
    512 /* end of struct st_rscan_from_rscan0gaflidj */
    513    
    514 /* start of struct st_rscan_from_rscan0gaflidj */
    515     union iodefine_reg32_t  GAFLID12;                      /*  GAFLID12        */
    516     union iodefine_reg32_t  GAFLM12;                       /*  GAFLM12         */
    517     union iodefine_reg32_t  GAFLP012;                      /*  GAFLP012        */
    518     union iodefine_reg32_t  GAFLP112;                      /*  GAFLP112        */
    519 /* end of struct st_rscan_from_rscan0gaflidj */
    520    
    521 /* start of struct st_rscan_from_rscan0gaflidj */
    522     union iodefine_reg32_t  GAFLID13;                      /*  GAFLID13        */
    523     union iodefine_reg32_t  GAFLM13;                       /*  GAFLM13         */
    524     union iodefine_reg32_t  GAFLP013;                      /*  GAFLP013        */
    525     union iodefine_reg32_t  GAFLP113;                      /*  GAFLP113        */
    526 /* end of struct st_rscan_from_rscan0gaflidj */
    527    
    528 /* start of struct st_rscan_from_rscan0gaflidj */
    529     union iodefine_reg32_t  GAFLID14;                      /*  GAFLID14        */
    530     union iodefine_reg32_t  GAFLM14;                       /*  GAFLM14         */
    531     union iodefine_reg32_t  GAFLP014;                      /*  GAFLP014        */
    532     union iodefine_reg32_t  GAFLP114;                      /*  GAFLP114        */
    533 /* end of struct st_rscan_from_rscan0gaflidj */
    534    
    535 /* start of struct st_rscan_from_rscan0gaflidj */
    536     union iodefine_reg32_t  GAFLID15;                      /*  GAFLID15        */
    537     union iodefine_reg32_t  GAFLM15;                       /*  GAFLM15         */
    538     union iodefine_reg32_t  GAFLP015;                      /*  GAFLP015        */
    539     union iodefine_reg32_t  GAFLP115;                      /*  GAFLP115        */
    540 /* end of struct st_rscan_from_rscan0gaflidj */
    541    
    542 /* start of struct st_rscan_from_rscan0rmidp */
    543     union iodefine_reg32_t  RMID0;                         /*  RMID0           */
    544     union iodefine_reg32_t  RMPTR0;                        /*  RMPTR0          */
    545     union iodefine_reg32_t  RMDF00;                        /*  RMDF00          */
    546     union iodefine_reg32_t  RMDF10;                        /*  RMDF10          */
    547 /* end of struct st_rscan_from_rscan0rmidp */
    548    
    549 /* start of struct st_rscan_from_rscan0rmidp */
    550     union iodefine_reg32_t  RMID1;                         /*  RMID1           */
    551     union iodefine_reg32_t  RMPTR1;                        /*  RMPTR1          */
    552     union iodefine_reg32_t  RMDF01;                        /*  RMDF01          */
    553     union iodefine_reg32_t  RMDF11;                        /*  RMDF11          */
    554 /* end of struct st_rscan_from_rscan0rmidp */
    555    
    556 /* start of struct st_rscan_from_rscan0rmidp */
    557     union iodefine_reg32_t  RMID2;                         /*  RMID2           */
    558     union iodefine_reg32_t  RMPTR2;                        /*  RMPTR2          */
    559     union iodefine_reg32_t  RMDF02;                        /*  RMDF02          */
    560     union iodefine_reg32_t  RMDF12;                        /*  RMDF12          */
    561 /* end of struct st_rscan_from_rscan0rmidp */
    562    
    563 /* start of struct st_rscan_from_rscan0rmidp */
    564     union iodefine_reg32_t  RMID3;                         /*  RMID3           */
    565     union iodefine_reg32_t  RMPTR3;                        /*  RMPTR3          */
    566     union iodefine_reg32_t  RMDF03;                        /*  RMDF03          */
    567     union iodefine_reg32_t  RMDF13;                        /*  RMDF13          */
    568 /* end of struct st_rscan_from_rscan0rmidp */
    569    
    570 /* start of struct st_rscan_from_rscan0rmidp */
    571     union iodefine_reg32_t  RMID4;                         /*  RMID4           */
    572     union iodefine_reg32_t  RMPTR4;                        /*  RMPTR4          */
    573     union iodefine_reg32_t  RMDF04;                        /*  RMDF04          */
    574     union iodefine_reg32_t  RMDF14;                        /*  RMDF14          */
    575 /* end of struct st_rscan_from_rscan0rmidp */
    576    
    577 /* start of struct st_rscan_from_rscan0rmidp */
    578     union iodefine_reg32_t  RMID5;                         /*  RMID5           */
    579     union iodefine_reg32_t  RMPTR5;                        /*  RMPTR5          */
    580     union iodefine_reg32_t  RMDF05;                        /*  RMDF05          */
    581     union iodefine_reg32_t  RMDF15;                        /*  RMDF15          */
    582 /* end of struct st_rscan_from_rscan0rmidp */
    583    
    584 /* start of struct st_rscan_from_rscan0rmidp */
    585     union iodefine_reg32_t  RMID6;                         /*  RMID6           */
    586     union iodefine_reg32_t  RMPTR6;                        /*  RMPTR6          */
    587     union iodefine_reg32_t  RMDF06;                        /*  RMDF06          */
    588     union iodefine_reg32_t  RMDF16;                        /*  RMDF16          */
    589 /* end of struct st_rscan_from_rscan0rmidp */
    590    
    591 /* start of struct st_rscan_from_rscan0rmidp */
    592     union iodefine_reg32_t  RMID7;                         /*  RMID7           */
    593     union iodefine_reg32_t  RMPTR7;                        /*  RMPTR7          */
    594     union iodefine_reg32_t  RMDF07;                        /*  RMDF07          */
    595     union iodefine_reg32_t  RMDF17;                        /*  RMDF17          */
    596 /* end of struct st_rscan_from_rscan0rmidp */
    597    
    598 /* start of struct st_rscan_from_rscan0rmidp */
    599     union iodefine_reg32_t  RMID8;                         /*  RMID8           */
    600     union iodefine_reg32_t  RMPTR8;                        /*  RMPTR8          */
    601     union iodefine_reg32_t  RMDF08;                        /*  RMDF08          */
    602     union iodefine_reg32_t  RMDF18;                        /*  RMDF18          */
    603 /* end of struct st_rscan_from_rscan0rmidp */
    604    
    605 /* start of struct st_rscan_from_rscan0rmidp */
    606     union iodefine_reg32_t  RMID9;                         /*  RMID9           */
    607     union iodefine_reg32_t  RMPTR9;                        /*  RMPTR9          */
    608     union iodefine_reg32_t  RMDF09;                        /*  RMDF09          */
    609     union iodefine_reg32_t  RMDF19;                        /*  RMDF19          */
    610 /* end of struct st_rscan_from_rscan0rmidp */
    611    
    612 /* start of struct st_rscan_from_rscan0rmidp */
    613     union iodefine_reg32_t  RMID10;                        /*  RMID10          */
    614     union iodefine_reg32_t  RMPTR10;                       /*  RMPTR10         */
    615     union iodefine_reg32_t  RMDF010;                       /*  RMDF010         */
    616     union iodefine_reg32_t  RMDF110;                       /*  RMDF110         */
    617 /* end of struct st_rscan_from_rscan0rmidp */
    618    
    619 /* start of struct st_rscan_from_rscan0rmidp */
    620     union iodefine_reg32_t  RMID11;                        /*  RMID11          */
    621     union iodefine_reg32_t  RMPTR11;                       /*  RMPTR11         */
    622     union iodefine_reg32_t  RMDF011;                       /*  RMDF011         */
    623     union iodefine_reg32_t  RMDF111;                       /*  RMDF111         */
    624 /* end of struct st_rscan_from_rscan0rmidp */
    625    
    626 /* start of struct st_rscan_from_rscan0rmidp */
    627     union iodefine_reg32_t  RMID12;                        /*  RMID12          */
    628     union iodefine_reg32_t  RMPTR12;                       /*  RMPTR12         */
    629     union iodefine_reg32_t  RMDF012;                       /*  RMDF012         */
    630     union iodefine_reg32_t  RMDF112;                       /*  RMDF112         */
    631 /* end of struct st_rscan_from_rscan0rmidp */
    632    
    633 /* start of struct st_rscan_from_rscan0rmidp */
    634     union iodefine_reg32_t  RMID13;                        /*  RMID13          */
    635     union iodefine_reg32_t  RMPTR13;                       /*  RMPTR13         */
    636     union iodefine_reg32_t  RMDF013;                       /*  RMDF013         */
    637     union iodefine_reg32_t  RMDF113;                       /*  RMDF113         */
    638 /* end of struct st_rscan_from_rscan0rmidp */
    639    
    640 /* start of struct st_rscan_from_rscan0rmidp */
    641     union iodefine_reg32_t  RMID14;                        /*  RMID14          */
    642     union iodefine_reg32_t  RMPTR14;                       /*  RMPTR14         */
    643     union iodefine_reg32_t  RMDF014;                       /*  RMDF014         */
    644     union iodefine_reg32_t  RMDF114;                       /*  RMDF114         */
    645 /* end of struct st_rscan_from_rscan0rmidp */
    646    
    647 /* start of struct st_rscan_from_rscan0rmidp */
    648     union iodefine_reg32_t  RMID15;                        /*  RMID15          */
    649     union iodefine_reg32_t  RMPTR15;                       /*  RMPTR15         */
    650     union iodefine_reg32_t  RMDF015;                       /*  RMDF015         */
    651     union iodefine_reg32_t  RMDF115;                       /*  RMDF115         */
    652 /* end of struct st_rscan_from_rscan0rmidp */
    653    
    654 /* start of struct st_rscan_from_rscan0rmidp */
    655     union iodefine_reg32_t  RMID16;                        /*  RMID16          */
    656     union iodefine_reg32_t  RMPTR16;                       /*  RMPTR16         */
    657     union iodefine_reg32_t  RMDF016;                       /*  RMDF016         */
    658     union iodefine_reg32_t  RMDF116;                       /*  RMDF116         */
    659 /* end of struct st_rscan_from_rscan0rmidp */
    660    
    661 /* start of struct st_rscan_from_rscan0rmidp */
    662     union iodefine_reg32_t  RMID17;                        /*  RMID17          */
    663     union iodefine_reg32_t  RMPTR17;                       /*  RMPTR17         */
    664     union iodefine_reg32_t  RMDF017;                       /*  RMDF017         */
    665     union iodefine_reg32_t  RMDF117;                       /*  RMDF117         */
    666 /* end of struct st_rscan_from_rscan0rmidp */
    667    
    668 /* start of struct st_rscan_from_rscan0rmidp */
    669     union iodefine_reg32_t  RMID18;                        /*  RMID18          */
    670     union iodefine_reg32_t  RMPTR18;                       /*  RMPTR18         */
    671     union iodefine_reg32_t  RMDF018;                       /*  RMDF018         */
    672     union iodefine_reg32_t  RMDF118;                       /*  RMDF118         */
    673 /* end of struct st_rscan_from_rscan0rmidp */
    674    
    675 /* start of struct st_rscan_from_rscan0rmidp */
    676     union iodefine_reg32_t  RMID19;                        /*  RMID19          */
    677     union iodefine_reg32_t  RMPTR19;                       /*  RMPTR19         */
    678     union iodefine_reg32_t  RMDF019;                       /*  RMDF019         */
    679     union iodefine_reg32_t  RMDF119;                       /*  RMDF119         */
    680 /* end of struct st_rscan_from_rscan0rmidp */
    681    
    682 /* start of struct st_rscan_from_rscan0rmidp */
    683     union iodefine_reg32_t  RMID20;                        /*  RMID20          */
    684     union iodefine_reg32_t  RMPTR20;                       /*  RMPTR20         */
    685     union iodefine_reg32_t  RMDF020;                       /*  RMDF020         */
    686     union iodefine_reg32_t  RMDF120;                       /*  RMDF120         */
    687 /* end of struct st_rscan_from_rscan0rmidp */
    688    
    689 /* start of struct st_rscan_from_rscan0rmidp */
    690     union iodefine_reg32_t  RMID21;                        /*  RMID21          */
    691     union iodefine_reg32_t  RMPTR21;                       /*  RMPTR21         */
    692     union iodefine_reg32_t  RMDF021;                       /*  RMDF021         */
    693     union iodefine_reg32_t  RMDF121;                       /*  RMDF121         */
    694 /* end of struct st_rscan_from_rscan0rmidp */
    695    
    696 /* start of struct st_rscan_from_rscan0rmidp */
    697     union iodefine_reg32_t  RMID22;                        /*  RMID22          */
    698     union iodefine_reg32_t  RMPTR22;                       /*  RMPTR22         */
    699     union iodefine_reg32_t  RMDF022;                       /*  RMDF022         */
    700     union iodefine_reg32_t  RMDF122;                       /*  RMDF122         */
    701 /* end of struct st_rscan_from_rscan0rmidp */
    702    
    703 /* start of struct st_rscan_from_rscan0rmidp */
    704     union iodefine_reg32_t  RMID23;                        /*  RMID23          */
    705     union iodefine_reg32_t  RMPTR23;                       /*  RMPTR23         */
    706     union iodefine_reg32_t  RMDF023;                       /*  RMDF023         */
    707     union iodefine_reg32_t  RMDF123;                       /*  RMDF123         */
    708 /* end of struct st_rscan_from_rscan0rmidp */
    709    
    710 /* start of struct st_rscan_from_rscan0rmidp */
    711     union iodefine_reg32_t  RMID24;                        /*  RMID24          */
    712     union iodefine_reg32_t  RMPTR24;                       /*  RMPTR24         */
    713     union iodefine_reg32_t  RMDF024;                       /*  RMDF024         */
    714     union iodefine_reg32_t  RMDF124;                       /*  RMDF124         */
    715 /* end of struct st_rscan_from_rscan0rmidp */
    716    
    717 /* start of struct st_rscan_from_rscan0rmidp */
    718     union iodefine_reg32_t  RMID25;                        /*  RMID25          */
    719     union iodefine_reg32_t  RMPTR25;                       /*  RMPTR25         */
    720     union iodefine_reg32_t  RMDF025;                       /*  RMDF025         */
    721     union iodefine_reg32_t  RMDF125;                       /*  RMDF125         */
    722 /* end of struct st_rscan_from_rscan0rmidp */
    723    
    724 /* start of struct st_rscan_from_rscan0rmidp */
    725     union iodefine_reg32_t  RMID26;                        /*  RMID26          */
    726     union iodefine_reg32_t  RMPTR26;                       /*  RMPTR26         */
    727     union iodefine_reg32_t  RMDF026;                       /*  RMDF026         */
    728     union iodefine_reg32_t  RMDF126;                       /*  RMDF126         */
    729 /* end of struct st_rscan_from_rscan0rmidp */
    730    
    731 /* start of struct st_rscan_from_rscan0rmidp */
    732     union iodefine_reg32_t  RMID27;                        /*  RMID27          */
    733     union iodefine_reg32_t  RMPTR27;                       /*  RMPTR27         */
    734     union iodefine_reg32_t  RMDF027;                       /*  RMDF027         */
    735     union iodefine_reg32_t  RMDF127;                       /*  RMDF127         */
    736 /* end of struct st_rscan_from_rscan0rmidp */
    737    
    738 /* start of struct st_rscan_from_rscan0rmidp */
    739     union iodefine_reg32_t  RMID28;                        /*  RMID28          */
    740     union iodefine_reg32_t  RMPTR28;                       /*  RMPTR28         */
    741     union iodefine_reg32_t  RMDF028;                       /*  RMDF028         */
    742     union iodefine_reg32_t  RMDF128;                       /*  RMDF128         */
    743 /* end of struct st_rscan_from_rscan0rmidp */
    744    
    745 /* start of struct st_rscan_from_rscan0rmidp */
    746     union iodefine_reg32_t  RMID29;                        /*  RMID29          */
    747     union iodefine_reg32_t  RMPTR29;                       /*  RMPTR29         */
    748     union iodefine_reg32_t  RMDF029;                       /*  RMDF029         */
    749     union iodefine_reg32_t  RMDF129;                       /*  RMDF129         */
    750 /* end of struct st_rscan_from_rscan0rmidp */
    751    
    752 /* start of struct st_rscan_from_rscan0rmidp */
    753     union iodefine_reg32_t  RMID30;                        /*  RMID30          */
    754     union iodefine_reg32_t  RMPTR30;                       /*  RMPTR30         */
    755     union iodefine_reg32_t  RMDF030;                       /*  RMDF030         */
    756     union iodefine_reg32_t  RMDF130;                       /*  RMDF130         */
    757 /* end of struct st_rscan_from_rscan0rmidp */
    758    
    759 /* start of struct st_rscan_from_rscan0rmidp */
    760     union iodefine_reg32_t  RMID31;                        /*  RMID31          */
    761     union iodefine_reg32_t  RMPTR31;                       /*  RMPTR31         */
    762     union iodefine_reg32_t  RMDF031;                       /*  RMDF031         */
    763     union iodefine_reg32_t  RMDF131;                       /*  RMDF131         */
    764 /* end of struct st_rscan_from_rscan0rmidp */
    765    
    766 /* start of struct st_rscan_from_rscan0rmidp */
    767     union iodefine_reg32_t  RMID32;                        /*  RMID32          */
    768     union iodefine_reg32_t  RMPTR32;                       /*  RMPTR32         */
    769     union iodefine_reg32_t  RMDF032;                       /*  RMDF032         */
    770     union iodefine_reg32_t  RMDF132;                       /*  RMDF132         */
    771 /* end of struct st_rscan_from_rscan0rmidp */
    772    
    773 /* start of struct st_rscan_from_rscan0rmidp */
    774     union iodefine_reg32_t  RMID33;                        /*  RMID33          */
    775     union iodefine_reg32_t  RMPTR33;                       /*  RMPTR33         */
    776     union iodefine_reg32_t  RMDF033;                       /*  RMDF033         */
    777     union iodefine_reg32_t  RMDF133;                       /*  RMDF133         */
    778 /* end of struct st_rscan_from_rscan0rmidp */
    779    
    780 /* start of struct st_rscan_from_rscan0rmidp */
    781     union iodefine_reg32_t  RMID34;                        /*  RMID34          */
    782     union iodefine_reg32_t  RMPTR34;                       /*  RMPTR34         */
    783     union iodefine_reg32_t  RMDF034;                       /*  RMDF034         */
    784     union iodefine_reg32_t  RMDF134;                       /*  RMDF134         */
    785 /* end of struct st_rscan_from_rscan0rmidp */
    786    
    787 /* start of struct st_rscan_from_rscan0rmidp */
    788     union iodefine_reg32_t  RMID35;                        /*  RMID35          */
    789     union iodefine_reg32_t  RMPTR35;                       /*  RMPTR35         */
    790     union iodefine_reg32_t  RMDF035;                       /*  RMDF035         */
    791     union iodefine_reg32_t  RMDF135;                       /*  RMDF135         */
    792 /* end of struct st_rscan_from_rscan0rmidp */
    793    
    794 /* start of struct st_rscan_from_rscan0rmidp */
    795     union iodefine_reg32_t  RMID36;                        /*  RMID36          */
    796     union iodefine_reg32_t  RMPTR36;                       /*  RMPTR36         */
    797     union iodefine_reg32_t  RMDF036;                       /*  RMDF036         */
    798     union iodefine_reg32_t  RMDF136;                       /*  RMDF136         */
    799 /* end of struct st_rscan_from_rscan0rmidp */
    800    
    801 /* start of struct st_rscan_from_rscan0rmidp */
    802     union iodefine_reg32_t  RMID37;                        /*  RMID37          */
    803     union iodefine_reg32_t  RMPTR37;                       /*  RMPTR37         */
    804     union iodefine_reg32_t  RMDF037;                       /*  RMDF037         */
    805     union iodefine_reg32_t  RMDF137;                       /*  RMDF137         */
    806 /* end of struct st_rscan_from_rscan0rmidp */
    807    
    808 /* start of struct st_rscan_from_rscan0rmidp */
    809     union iodefine_reg32_t  RMID38;                        /*  RMID38          */
    810     union iodefine_reg32_t  RMPTR38;                       /*  RMPTR38         */
    811     union iodefine_reg32_t  RMDF038;                       /*  RMDF038         */
    812     union iodefine_reg32_t  RMDF138;                       /*  RMDF138         */
    813 /* end of struct st_rscan_from_rscan0rmidp */
    814    
    815 /* start of struct st_rscan_from_rscan0rmidp */
    816     union iodefine_reg32_t  RMID39;                        /*  RMID39          */
    817     union iodefine_reg32_t  RMPTR39;                       /*  RMPTR39         */
    818     union iodefine_reg32_t  RMDF039;                       /*  RMDF039         */
    819     union iodefine_reg32_t  RMDF139;                       /*  RMDF139         */
    820 /* end of struct st_rscan_from_rscan0rmidp */
    821    
    822 /* start of struct st_rscan_from_rscan0rmidp */
    823     union iodefine_reg32_t  RMID40;                        /*  RMID40          */
    824     union iodefine_reg32_t  RMPTR40;                       /*  RMPTR40         */
    825     union iodefine_reg32_t  RMDF040;                       /*  RMDF040         */
    826     union iodefine_reg32_t  RMDF140;                       /*  RMDF140         */
    827 /* end of struct st_rscan_from_rscan0rmidp */
    828    
    829 /* start of struct st_rscan_from_rscan0rmidp */
    830     union iodefine_reg32_t  RMID41;                        /*  RMID41          */
    831     union iodefine_reg32_t  RMPTR41;                       /*  RMPTR41         */
    832     union iodefine_reg32_t  RMDF041;                       /*  RMDF041         */
    833     union iodefine_reg32_t  RMDF141;                       /*  RMDF141         */
    834 /* end of struct st_rscan_from_rscan0rmidp */
    835    
    836 /* start of struct st_rscan_from_rscan0rmidp */
    837     union iodefine_reg32_t  RMID42;                        /*  RMID42          */
    838     union iodefine_reg32_t  RMPTR42;                       /*  RMPTR42         */
    839     union iodefine_reg32_t  RMDF042;                       /*  RMDF042         */
    840     union iodefine_reg32_t  RMDF142;                       /*  RMDF142         */
    841 /* end of struct st_rscan_from_rscan0rmidp */
    842    
    843 /* start of struct st_rscan_from_rscan0rmidp */
    844     union iodefine_reg32_t  RMID43;                        /*  RMID43          */
    845     union iodefine_reg32_t  RMPTR43;                       /*  RMPTR43         */
    846     union iodefine_reg32_t  RMDF043;                       /*  RMDF043         */
    847     union iodefine_reg32_t  RMDF143;                       /*  RMDF143         */
    848 /* end of struct st_rscan_from_rscan0rmidp */
    849    
    850 /* start of struct st_rscan_from_rscan0rmidp */
    851     union iodefine_reg32_t  RMID44;                        /*  RMID44          */
    852     union iodefine_reg32_t  RMPTR44;                       /*  RMPTR44         */
    853     union iodefine_reg32_t  RMDF044;                       /*  RMDF044         */
    854     union iodefine_reg32_t  RMDF144;                       /*  RMDF144         */
    855 /* end of struct st_rscan_from_rscan0rmidp */
    856    
    857 /* start of struct st_rscan_from_rscan0rmidp */
    858     union iodefine_reg32_t  RMID45;                        /*  RMID45          */
    859     union iodefine_reg32_t  RMPTR45;                       /*  RMPTR45         */
    860     union iodefine_reg32_t  RMDF045;                       /*  RMDF045         */
    861     union iodefine_reg32_t  RMDF145;                       /*  RMDF145         */
    862 /* end of struct st_rscan_from_rscan0rmidp */
    863    
    864 /* start of struct st_rscan_from_rscan0rmidp */
    865     union iodefine_reg32_t  RMID46;                        /*  RMID46          */
    866     union iodefine_reg32_t  RMPTR46;                       /*  RMPTR46         */
    867     union iodefine_reg32_t  RMDF046;                       /*  RMDF046         */
    868     union iodefine_reg32_t  RMDF146;                       /*  RMDF146         */
    869 /* end of struct st_rscan_from_rscan0rmidp */
    870    
    871 /* start of struct st_rscan_from_rscan0rmidp */
    872     union iodefine_reg32_t  RMID47;                        /*  RMID47          */
    873     union iodefine_reg32_t  RMPTR47;                       /*  RMPTR47         */
    874     union iodefine_reg32_t  RMDF047;                       /*  RMDF047         */
    875     union iodefine_reg32_t  RMDF147;                       /*  RMDF147         */
    876 /* end of struct st_rscan_from_rscan0rmidp */
    877    
    878 /* start of struct st_rscan_from_rscan0rmidp */
    879     union iodefine_reg32_t  RMID48;                        /*  RMID48          */
    880     union iodefine_reg32_t  RMPTR48;                       /*  RMPTR48         */
    881     union iodefine_reg32_t  RMDF048;                       /*  RMDF048         */
    882     union iodefine_reg32_t  RMDF148;                       /*  RMDF148         */
    883 /* end of struct st_rscan_from_rscan0rmidp */
    884    
    885 /* start of struct st_rscan_from_rscan0rmidp */
    886     union iodefine_reg32_t  RMID49;                        /*  RMID49          */
    887     union iodefine_reg32_t  RMPTR49;                       /*  RMPTR49         */
    888     union iodefine_reg32_t  RMDF049;                       /*  RMDF049         */
    889     union iodefine_reg32_t  RMDF149;                       /*  RMDF149         */
    890 /* end of struct st_rscan_from_rscan0rmidp */
    891    
    892 /* start of struct st_rscan_from_rscan0rmidp */
    893     union iodefine_reg32_t  RMID50;                        /*  RMID50          */
    894     union iodefine_reg32_t  RMPTR50;                       /*  RMPTR50         */
    895     union iodefine_reg32_t  RMDF050;                       /*  RMDF050         */
    896     union iodefine_reg32_t  RMDF150;                       /*  RMDF150         */
    897 /* end of struct st_rscan_from_rscan0rmidp */
    898    
    899 /* start of struct st_rscan_from_rscan0rmidp */
    900     union iodefine_reg32_t  RMID51;                        /*  RMID51          */
    901     union iodefine_reg32_t  RMPTR51;                       /*  RMPTR51         */
    902     union iodefine_reg32_t  RMDF051;                       /*  RMDF051         */
    903     union iodefine_reg32_t  RMDF151;                       /*  RMDF151         */
    904 /* end of struct st_rscan_from_rscan0rmidp */
    905    
    906 /* start of struct st_rscan_from_rscan0rmidp */
    907     union iodefine_reg32_t  RMID52;                        /*  RMID52          */
    908     union iodefine_reg32_t  RMPTR52;                       /*  RMPTR52         */
    909     union iodefine_reg32_t  RMDF052;                       /*  RMDF052         */
    910     union iodefine_reg32_t  RMDF152;                       /*  RMDF152         */
    911 /* end of struct st_rscan_from_rscan0rmidp */
    912    
    913 /* start of struct st_rscan_from_rscan0rmidp */
    914     union iodefine_reg32_t  RMID53;                        /*  RMID53          */
    915     union iodefine_reg32_t  RMPTR53;                       /*  RMPTR53         */
    916     union iodefine_reg32_t  RMDF053;                       /*  RMDF053         */
    917     union iodefine_reg32_t  RMDF153;                       /*  RMDF153         */
    918 /* end of struct st_rscan_from_rscan0rmidp */
    919    
    920 /* start of struct st_rscan_from_rscan0rmidp */
    921     union iodefine_reg32_t  RMID54;                        /*  RMID54          */
    922     union iodefine_reg32_t  RMPTR54;                       /*  RMPTR54         */
    923     union iodefine_reg32_t  RMDF054;                       /*  RMDF054         */
    924     union iodefine_reg32_t  RMDF154;                       /*  RMDF154         */
    925 /* end of struct st_rscan_from_rscan0rmidp */
    926    
    927 /* start of struct st_rscan_from_rscan0rmidp */
    928     union iodefine_reg32_t  RMID55;                        /*  RMID55          */
    929     union iodefine_reg32_t  RMPTR55;                       /*  RMPTR55         */
    930     union iodefine_reg32_t  RMDF055;                       /*  RMDF055         */
    931     union iodefine_reg32_t  RMDF155;                       /*  RMDF155         */
    932 /* end of struct st_rscan_from_rscan0rmidp */
    933    
    934 /* start of struct st_rscan_from_rscan0rmidp */
    935     union iodefine_reg32_t  RMID56;                        /*  RMID56          */
    936     union iodefine_reg32_t  RMPTR56;                       /*  RMPTR56         */
    937     union iodefine_reg32_t  RMDF056;                       /*  RMDF056         */
    938     union iodefine_reg32_t  RMDF156;                       /*  RMDF156         */
    939 /* end of struct st_rscan_from_rscan0rmidp */
    940    
    941 /* start of struct st_rscan_from_rscan0rmidp */
    942     union iodefine_reg32_t  RMID57;                        /*  RMID57          */
    943     union iodefine_reg32_t  RMPTR57;                       /*  RMPTR57         */
    944     union iodefine_reg32_t  RMDF057;                       /*  RMDF057         */
    945     union iodefine_reg32_t  RMDF157;                       /*  RMDF157         */
    946 /* end of struct st_rscan_from_rscan0rmidp */
    947    
    948 /* start of struct st_rscan_from_rscan0rmidp */
    949     union iodefine_reg32_t  RMID58;                        /*  RMID58          */
    950     union iodefine_reg32_t  RMPTR58;                       /*  RMPTR58         */
    951     union iodefine_reg32_t  RMDF058;                       /*  RMDF058         */
    952     union iodefine_reg32_t  RMDF158;                       /*  RMDF158         */
    953 /* end of struct st_rscan_from_rscan0rmidp */
    954    
    955 /* start of struct st_rscan_from_rscan0rmidp */
    956     union iodefine_reg32_t  RMID59;                        /*  RMID59          */
    957     union iodefine_reg32_t  RMPTR59;                       /*  RMPTR59         */
    958     union iodefine_reg32_t  RMDF059;                       /*  RMDF059         */
    959     union iodefine_reg32_t  RMDF159;                       /*  RMDF159         */
    960 /* end of struct st_rscan_from_rscan0rmidp */
    961    
    962 /* start of struct st_rscan_from_rscan0rmidp */
    963     union iodefine_reg32_t  RMID60;                        /*  RMID60          */
    964     union iodefine_reg32_t  RMPTR60;                       /*  RMPTR60         */
    965     union iodefine_reg32_t  RMDF060;                       /*  RMDF060         */
    966     union iodefine_reg32_t  RMDF160;                       /*  RMDF160         */
    967 /* end of struct st_rscan_from_rscan0rmidp */
    968    
    969 /* start of struct st_rscan_from_rscan0rmidp */
    970     union iodefine_reg32_t  RMID61;                        /*  RMID61          */
    971     union iodefine_reg32_t  RMPTR61;                       /*  RMPTR61         */
    972     union iodefine_reg32_t  RMDF061;                       /*  RMDF061         */
    973     union iodefine_reg32_t  RMDF161;                       /*  RMDF161         */
    974 /* end of struct st_rscan_from_rscan0rmidp */
    975    
    976 /* start of struct st_rscan_from_rscan0rmidp */
    977     union iodefine_reg32_t  RMID62;                        /*  RMID62          */
    978     union iodefine_reg32_t  RMPTR62;                       /*  RMPTR62         */
    979     union iodefine_reg32_t  RMDF062;                       /*  RMDF062         */
    980     union iodefine_reg32_t  RMDF162;                       /*  RMDF162         */
    981 /* end of struct st_rscan_from_rscan0rmidp */
    982    
    983 /* start of struct st_rscan_from_rscan0rmidp */
    984     union iodefine_reg32_t  RMID63;                        /*  RMID63          */
    985     union iodefine_reg32_t  RMPTR63;                       /*  RMPTR63         */
    986     union iodefine_reg32_t  RMDF063;                       /*  RMDF063         */
    987     union iodefine_reg32_t  RMDF163;                       /*  RMDF163         */
    988 /* end of struct st_rscan_from_rscan0rmidp */
    989    
    990 /* start of struct st_rscan_from_rscan0rmidp */
    991     union iodefine_reg32_t  RMID64;                        /*  RMID64          */
    992     union iodefine_reg32_t  RMPTR64;                       /*  RMPTR64         */
    993     union iodefine_reg32_t  RMDF064;                       /*  RMDF064         */
    994     union iodefine_reg32_t  RMDF164;                       /*  RMDF164         */
    995 /* end of struct st_rscan_from_rscan0rmidp */
    996    
    997 /* start of struct st_rscan_from_rscan0rmidp */
    998     union iodefine_reg32_t  RMID65;                        /*  RMID65          */
    999     union iodefine_reg32_t  RMPTR65;                       /*  RMPTR65         */
    1000     union iodefine_reg32_t  RMDF065;                       /*  RMDF065         */
    1001     union iodefine_reg32_t  RMDF165;                       /*  RMDF165         */
    1002 /* end of struct st_rscan_from_rscan0rmidp */
    1003    
    1004 /* start of struct st_rscan_from_rscan0rmidp */
    1005     union iodefine_reg32_t  RMID66;                        /*  RMID66          */
    1006     union iodefine_reg32_t  RMPTR66;                       /*  RMPTR66         */
    1007     union iodefine_reg32_t  RMDF066;                       /*  RMDF066         */
    1008     union iodefine_reg32_t  RMDF166;                       /*  RMDF166         */
    1009 /* end of struct st_rscan_from_rscan0rmidp */
    1010    
    1011 /* start of struct st_rscan_from_rscan0rmidp */
    1012     union iodefine_reg32_t  RMID67;                        /*  RMID67          */
    1013     union iodefine_reg32_t  RMPTR67;                       /*  RMPTR67         */
    1014     union iodefine_reg32_t  RMDF067;                       /*  RMDF067         */
    1015     union iodefine_reg32_t  RMDF167;                       /*  RMDF167         */
    1016 /* end of struct st_rscan_from_rscan0rmidp */
    1017    
    1018 /* start of struct st_rscan_from_rscan0rmidp */
    1019     union iodefine_reg32_t  RMID68;                        /*  RMID68          */
    1020     union iodefine_reg32_t  RMPTR68;                       /*  RMPTR68         */
    1021     union iodefine_reg32_t  RMDF068;                       /*  RMDF068         */
    1022     union iodefine_reg32_t  RMDF168;                       /*  RMDF168         */
    1023 /* end of struct st_rscan_from_rscan0rmidp */
    1024    
    1025 /* start of struct st_rscan_from_rscan0rmidp */
    1026     union iodefine_reg32_t  RMID69;                        /*  RMID69          */
    1027     union iodefine_reg32_t  RMPTR69;                       /*  RMPTR69         */
    1028     union iodefine_reg32_t  RMDF069;                       /*  RMDF069         */
    1029     union iodefine_reg32_t  RMDF169;                       /*  RMDF169         */
    1030 /* end of struct st_rscan_from_rscan0rmidp */
    1031    
    1032 /* start of struct st_rscan_from_rscan0rmidp */
    1033     union iodefine_reg32_t  RMID70;                        /*  RMID70          */
    1034     union iodefine_reg32_t  RMPTR70;                       /*  RMPTR70         */
    1035     union iodefine_reg32_t  RMDF070;                       /*  RMDF070         */
    1036     union iodefine_reg32_t  RMDF170;                       /*  RMDF170         */
    1037 /* end of struct st_rscan_from_rscan0rmidp */
    1038    
    1039 /* start of struct st_rscan_from_rscan0rmidp */
    1040     union iodefine_reg32_t  RMID71;                        /*  RMID71          */
    1041     union iodefine_reg32_t  RMPTR71;                       /*  RMPTR71         */
    1042     union iodefine_reg32_t  RMDF071;                       /*  RMDF071         */
    1043     union iodefine_reg32_t  RMDF171;                       /*  RMDF171         */
    1044 /* end of struct st_rscan_from_rscan0rmidp */
    1045    
    1046 /* start of struct st_rscan_from_rscan0rmidp */
    1047     union iodefine_reg32_t  RMID72;                        /*  RMID72          */
    1048     union iodefine_reg32_t  RMPTR72;                       /*  RMPTR72         */
    1049     union iodefine_reg32_t  RMDF072;                       /*  RMDF072         */
    1050     union iodefine_reg32_t  RMDF172;                       /*  RMDF172         */
    1051 /* end of struct st_rscan_from_rscan0rmidp */
    1052    
    1053 /* start of struct st_rscan_from_rscan0rmidp */
    1054     union iodefine_reg32_t  RMID73;                        /*  RMID73          */
    1055     union iodefine_reg32_t  RMPTR73;                       /*  RMPTR73         */
    1056     union iodefine_reg32_t  RMDF073;                       /*  RMDF073         */
    1057     union iodefine_reg32_t  RMDF173;                       /*  RMDF173         */
    1058 /* end of struct st_rscan_from_rscan0rmidp */
    1059    
    1060 /* start of struct st_rscan_from_rscan0rmidp */
    1061     union iodefine_reg32_t  RMID74;                        /*  RMID74          */
    1062     union iodefine_reg32_t  RMPTR74;                       /*  RMPTR74         */
    1063     union iodefine_reg32_t  RMDF074;                       /*  RMDF074         */
    1064     union iodefine_reg32_t  RMDF174;                       /*  RMDF174         */
    1065 /* end of struct st_rscan_from_rscan0rmidp */
    1066    
    1067 /* start of struct st_rscan_from_rscan0rmidp */
    1068     union iodefine_reg32_t  RMID75;                        /*  RMID75          */
    1069     union iodefine_reg32_t  RMPTR75;                       /*  RMPTR75         */
    1070     union iodefine_reg32_t  RMDF075;                       /*  RMDF075         */
    1071     union iodefine_reg32_t  RMDF175;                       /*  RMDF175         */
    1072 /* end of struct st_rscan_from_rscan0rmidp */
    1073    
    1074 /* start of struct st_rscan_from_rscan0rmidp */
    1075     union iodefine_reg32_t  RMID76;                        /*  RMID76          */
    1076     union iodefine_reg32_t  RMPTR76;                       /*  RMPTR76         */
    1077     union iodefine_reg32_t  RMDF076;                       /*  RMDF076         */
    1078     union iodefine_reg32_t  RMDF176;                       /*  RMDF176         */
    1079 /* end of struct st_rscan_from_rscan0rmidp */
    1080    
    1081 /* start of struct st_rscan_from_rscan0rmidp */
    1082     union iodefine_reg32_t  RMID77;                        /*  RMID77          */
    1083     union iodefine_reg32_t  RMPTR77;                       /*  RMPTR77         */
    1084     union iodefine_reg32_t  RMDF077;                       /*  RMDF077         */
    1085     union iodefine_reg32_t  RMDF177;                       /*  RMDF177         */
    1086 /* end of struct st_rscan_from_rscan0rmidp */
    1087    
    1088 /* start of struct st_rscan_from_rscan0rmidp */
    1089     union iodefine_reg32_t  RMID78;                        /*  RMID78          */
    1090     union iodefine_reg32_t  RMPTR78;                       /*  RMPTR78         */
    1091     union iodefine_reg32_t  RMDF078;                       /*  RMDF078         */
    1092     union iodefine_reg32_t  RMDF178;                       /*  RMDF178         */
    1093 /* end of struct st_rscan_from_rscan0rmidp */
    1094    
    1095 /* start of struct st_rscan_from_rscan0rmidp */
    1096     union iodefine_reg32_t  RMID79;                        /*  RMID79          */
    1097     union iodefine_reg32_t  RMPTR79;                       /*  RMPTR79         */
    1098     union iodefine_reg32_t  RMDF079;                       /*  RMDF079         */
    1099     union iodefine_reg32_t  RMDF179;                       /*  RMDF179         */
    1100 /* end of struct st_rscan_from_rscan0rmidp */
    1101    
    1102     volatile uint8_t   dummy179[768];                          /*                  */
    1103    
    1104 /* start of struct st_rscan_from_rscan0rfidm */
    1105     union iodefine_reg32_t  RFID0;                         /*  RFID0           */
    1106     union iodefine_reg32_t  RFPTR0;                        /*  RFPTR0          */
    1107     union iodefine_reg32_t  RFDF00;                        /*  RFDF00          */
    1108     union iodefine_reg32_t  RFDF10;                        /*  RFDF10          */
    1109 /* end of struct st_rscan_from_rscan0rfidm */
    1110    
    1111 /* start of struct st_rscan_from_rscan0rfidm */
    1112     union iodefine_reg32_t  RFID1;                         /*  RFID1           */
    1113     union iodefine_reg32_t  RFPTR1;                        /*  RFPTR1          */
    1114     union iodefine_reg32_t  RFDF01;                        /*  RFDF01          */
    1115     union iodefine_reg32_t  RFDF11;                        /*  RFDF11          */
    1116 /* end of struct st_rscan_from_rscan0rfidm */
    1117    
    1118 /* start of struct st_rscan_from_rscan0rfidm */
    1119     union iodefine_reg32_t  RFID2;                         /*  RFID2           */
    1120     union iodefine_reg32_t  RFPTR2;                        /*  RFPTR2          */
    1121     union iodefine_reg32_t  RFDF02;                        /*  RFDF02          */
    1122     union iodefine_reg32_t  RFDF12;                        /*  RFDF12          */
    1123 /* end of struct st_rscan_from_rscan0rfidm */
    1124    
    1125 /* start of struct st_rscan_from_rscan0rfidm */
    1126     union iodefine_reg32_t  RFID3;                         /*  RFID3           */
    1127     union iodefine_reg32_t  RFPTR3;                        /*  RFPTR3          */
    1128     union iodefine_reg32_t  RFDF03;                        /*  RFDF03          */
    1129     union iodefine_reg32_t  RFDF13;                        /*  RFDF13          */
    1130 /* end of struct st_rscan_from_rscan0rfidm */
    1131    
    1132 /* start of struct st_rscan_from_rscan0rfidm */
    1133     union iodefine_reg32_t  RFID4;                         /*  RFID4           */
    1134     union iodefine_reg32_t  RFPTR4;                        /*  RFPTR4          */
    1135     union iodefine_reg32_t  RFDF04;                        /*  RFDF04          */
    1136     union iodefine_reg32_t  RFDF14;                        /*  RFDF14          */
    1137 /* end of struct st_rscan_from_rscan0rfidm */
    1138    
    1139 /* start of struct st_rscan_from_rscan0rfidm */
    1140     union iodefine_reg32_t  RFID5;                         /*  RFID5           */
    1141     union iodefine_reg32_t  RFPTR5;                        /*  RFPTR5          */
    1142     union iodefine_reg32_t  RFDF05;                        /*  RFDF05          */
    1143     union iodefine_reg32_t  RFDF15;                        /*  RFDF15          */
    1144 /* end of struct st_rscan_from_rscan0rfidm */
    1145    
    1146 /* start of struct st_rscan_from_rscan0rfidm */
    1147     union iodefine_reg32_t  RFID6;                         /*  RFID6           */
    1148     union iodefine_reg32_t  RFPTR6;                        /*  RFPTR6          */
    1149     union iodefine_reg32_t  RFDF06;                        /*  RFDF06          */
    1150     union iodefine_reg32_t  RFDF16;                        /*  RFDF16          */
    1151 /* end of struct st_rscan_from_rscan0rfidm */
    1152    
    1153 /* start of struct st_rscan_from_rscan0rfidm */
    1154     union iodefine_reg32_t  RFID7;                         /*  RFID7           */
    1155     union iodefine_reg32_t  RFPTR7;                        /*  RFPTR7          */
    1156     union iodefine_reg32_t  RFDF07;                        /*  RFDF07          */
    1157     union iodefine_reg32_t  RFDF17;                        /*  RFDF17          */
    1158 /* end of struct st_rscan_from_rscan0rfidm */
    1159    
    1160 /* start of struct st_rscan_from_rscan0cfidm */
    1161     union iodefine_reg32_t  CFID0;                         /*  CFID0           */
    1162     union iodefine_reg32_t  CFPTR0;                        /*  CFPTR0          */
    1163     union iodefine_reg32_t  CFDF00;                        /*  CFDF00          */
    1164     union iodefine_reg32_t  CFDF10;                        /*  CFDF10          */
    1165 /* end of struct st_rscan_from_rscan0cfidm */
    1166    
    1167 /* start of struct st_rscan_from_rscan0cfidm */
    1168     union iodefine_reg32_t  CFID1;                         /*  CFID1           */
    1169     union iodefine_reg32_t  CFPTR1;                        /*  CFPTR1          */
    1170     union iodefine_reg32_t  CFDF01;                        /*  CFDF01          */
    1171     union iodefine_reg32_t  CFDF11;                        /*  CFDF11          */
    1172 /* end of struct st_rscan_from_rscan0cfidm */
    1173    
    1174 /* start of struct st_rscan_from_rscan0cfidm */
    1175     union iodefine_reg32_t  CFID2;                         /*  CFID2           */
    1176     union iodefine_reg32_t  CFPTR2;                        /*  CFPTR2          */
    1177     union iodefine_reg32_t  CFDF02;                        /*  CFDF02          */
    1178     union iodefine_reg32_t  CFDF12;                        /*  CFDF12          */
    1179 /* end of struct st_rscan_from_rscan0cfidm */
    1180    
    1181 /* start of struct st_rscan_from_rscan0cfidm */
    1182     union iodefine_reg32_t  CFID3;                         /*  CFID3           */
    1183     union iodefine_reg32_t  CFPTR3;                        /*  CFPTR3          */
    1184     union iodefine_reg32_t  CFDF03;                        /*  CFDF03          */
    1185     union iodefine_reg32_t  CFDF13;                        /*  CFDF13          */
    1186 /* end of struct st_rscan_from_rscan0cfidm */
    1187    
    1188 /* start of struct st_rscan_from_rscan0cfidm */
    1189     union iodefine_reg32_t  CFID4;                         /*  CFID4           */
    1190     union iodefine_reg32_t  CFPTR4;                        /*  CFPTR4          */
    1191     union iodefine_reg32_t  CFDF04;                        /*  CFDF04          */
    1192     union iodefine_reg32_t  CFDF14;                        /*  CFDF14          */
    1193 /* end of struct st_rscan_from_rscan0cfidm */
    1194    
    1195 /* start of struct st_rscan_from_rscan0cfidm */
    1196     union iodefine_reg32_t  CFID5;                         /*  CFID5           */
    1197     union iodefine_reg32_t  CFPTR5;                        /*  CFPTR5          */
    1198     union iodefine_reg32_t  CFDF05;                        /*  CFDF05          */
    1199     union iodefine_reg32_t  CFDF15;                        /*  CFDF15          */
    1200 /* end of struct st_rscan_from_rscan0cfidm */
    1201    
    1202 /* start of struct st_rscan_from_rscan0cfidm */
    1203     union iodefine_reg32_t  CFID6;                         /*  CFID6           */
    1204     union iodefine_reg32_t  CFPTR6;                        /*  CFPTR6          */
    1205     union iodefine_reg32_t  CFDF06;                        /*  CFDF06          */
    1206     union iodefine_reg32_t  CFDF16;                        /*  CFDF16          */
    1207 /* end of struct st_rscan_from_rscan0cfidm */
    1208    
    1209 /* start of struct st_rscan_from_rscan0cfidm */
    1210     union iodefine_reg32_t  CFID7;                         /*  CFID7           */
    1211     union iodefine_reg32_t  CFPTR7;                        /*  CFPTR7          */
    1212     union iodefine_reg32_t  CFDF07;                        /*  CFDF07          */
    1213     union iodefine_reg32_t  CFDF17;                        /*  CFDF17          */
    1214 /* end of struct st_rscan_from_rscan0cfidm */
    1215    
    1216 /* start of struct st_rscan_from_rscan0cfidm */
    1217     union iodefine_reg32_t  CFID8;                         /*  CFID8           */
    1218     union iodefine_reg32_t  CFPTR8;                        /*  CFPTR8          */
    1219     union iodefine_reg32_t  CFDF08;                        /*  CFDF08          */
    1220     union iodefine_reg32_t  CFDF18;                        /*  CFDF18          */
    1221 /* end of struct st_rscan_from_rscan0cfidm */
    1222    
    1223 /* start of struct st_rscan_from_rscan0cfidm */
    1224     union iodefine_reg32_t  CFID9;                         /*  CFID9           */
    1225     union iodefine_reg32_t  CFPTR9;                        /*  CFPTR9          */
    1226     union iodefine_reg32_t  CFDF09;                        /*  CFDF09          */
    1227     union iodefine_reg32_t  CFDF19;                        /*  CFDF19          */
    1228 /* end of struct st_rscan_from_rscan0cfidm */
    1229    
    1230 /* start of struct st_rscan_from_rscan0cfidm */
    1231     union iodefine_reg32_t  CFID10;                        /*  CFID10          */
    1232     union iodefine_reg32_t  CFPTR10;                       /*  CFPTR10         */
    1233     union iodefine_reg32_t  CFDF010;                       /*  CFDF010         */
    1234     union iodefine_reg32_t  CFDF110;                       /*  CFDF110         */
    1235 /* end of struct st_rscan_from_rscan0cfidm */
    1236    
    1237 /* start of struct st_rscan_from_rscan0cfidm */
    1238     union iodefine_reg32_t  CFID11;                        /*  CFID11          */
    1239     union iodefine_reg32_t  CFPTR11;                       /*  CFPTR11         */
    1240     union iodefine_reg32_t  CFDF011;                       /*  CFDF011         */
    1241     union iodefine_reg32_t  CFDF111;                       /*  CFDF111         */
    1242 /* end of struct st_rscan_from_rscan0cfidm */
    1243    
    1244 /* start of struct st_rscan_from_rscan0cfidm */
    1245     union iodefine_reg32_t  CFID12;                        /*  CFID12          */
    1246     union iodefine_reg32_t  CFPTR12;                       /*  CFPTR12         */
    1247     union iodefine_reg32_t  CFDF012;                       /*  CFDF012         */
    1248     union iodefine_reg32_t  CFDF112;                       /*  CFDF112         */
    1249 /* end of struct st_rscan_from_rscan0cfidm */
    1250    
    1251 /* start of struct st_rscan_from_rscan0cfidm */
    1252     union iodefine_reg32_t  CFID13;                        /*  CFID13          */
    1253     union iodefine_reg32_t  CFPTR13;                       /*  CFPTR13         */
    1254     union iodefine_reg32_t  CFDF013;                       /*  CFDF013         */
    1255     union iodefine_reg32_t  CFDF113;                       /*  CFDF113         */
    1256 /* end of struct st_rscan_from_rscan0cfidm */
    1257    
    1258 /* start of struct st_rscan_from_rscan0cfidm */
    1259     union iodefine_reg32_t  CFID14;                        /*  CFID14          */
    1260     union iodefine_reg32_t  CFPTR14;                       /*  CFPTR14         */
    1261     union iodefine_reg32_t  CFDF014;                       /*  CFDF014         */
    1262     union iodefine_reg32_t  CFDF114;                       /*  CFDF114         */
    1263 /* end of struct st_rscan_from_rscan0cfidm */
    1264    
    1265     volatile uint8_t   dummy180[144];                          /*                  */
    1266    
    1267 /* start of struct st_rscan_from_rscan0tmidp */
    1268     union iodefine_reg32_t  TMID0;                         /*  TMID0           */
    1269     union iodefine_reg32_t  TMPTR0;                        /*  TMPTR0          */
    1270     union iodefine_reg32_t  TMDF00;                        /*  TMDF00          */
    1271     union iodefine_reg32_t  TMDF10;                        /*  TMDF10          */
    1272 /* end of struct st_rscan_from_rscan0tmidp */
    1273    
    1274 /* start of struct st_rscan_from_rscan0tmidp */
    1275     union iodefine_reg32_t  TMID1;                         /*  TMID1           */
    1276     union iodefine_reg32_t  TMPTR1;                        /*  TMPTR1          */
    1277     union iodefine_reg32_t  TMDF01;                        /*  TMDF01          */
    1278     union iodefine_reg32_t  TMDF11;                        /*  TMDF11          */
    1279 /* end of struct st_rscan_from_rscan0tmidp */
    1280    
    1281 /* start of struct st_rscan_from_rscan0tmidp */
    1282     union iodefine_reg32_t  TMID2;                         /*  TMID2           */
    1283     union iodefine_reg32_t  TMPTR2;                        /*  TMPTR2          */
    1284     union iodefine_reg32_t  TMDF02;                        /*  TMDF02          */
    1285     union iodefine_reg32_t  TMDF12;                        /*  TMDF12          */
    1286 /* end of struct st_rscan_from_rscan0tmidp */
    1287    
    1288 /* start of struct st_rscan_from_rscan0tmidp */
    1289     union iodefine_reg32_t  TMID3;                         /*  TMID3           */
    1290     union iodefine_reg32_t  TMPTR3;                        /*  TMPTR3          */
    1291     union iodefine_reg32_t  TMDF03;                        /*  TMDF03          */
    1292     union iodefine_reg32_t  TMDF13;                        /*  TMDF13          */
    1293 /* end of struct st_rscan_from_rscan0tmidp */
    1294    
    1295 /* start of struct st_rscan_from_rscan0tmidp */
    1296     union iodefine_reg32_t  TMID4;                         /*  TMID4           */
    1297     union iodefine_reg32_t  TMPTR4;                        /*  TMPTR4          */
    1298     union iodefine_reg32_t  TMDF04;                        /*  TMDF04          */
    1299     union iodefine_reg32_t  TMDF14;                        /*  TMDF14          */
    1300 /* end of struct st_rscan_from_rscan0tmidp */
    1301    
    1302 /* start of struct st_rscan_from_rscan0tmidp */
    1303     union iodefine_reg32_t  TMID5;                         /*  TMID5           */
    1304     union iodefine_reg32_t  TMPTR5;                        /*  TMPTR5          */
    1305     union iodefine_reg32_t  TMDF05;                        /*  TMDF05          */
    1306     union iodefine_reg32_t  TMDF15;                        /*  TMDF15          */
    1307 /* end of struct st_rscan_from_rscan0tmidp */
    1308    
    1309 /* start of struct st_rscan_from_rscan0tmidp */
    1310     union iodefine_reg32_t  TMID6;                         /*  TMID6           */
    1311     union iodefine_reg32_t  TMPTR6;                        /*  TMPTR6          */
    1312     union iodefine_reg32_t  TMDF06;                        /*  TMDF06          */
    1313     union iodefine_reg32_t  TMDF16;                        /*  TMDF16          */
    1314 /* end of struct st_rscan_from_rscan0tmidp */
    1315    
    1316 /* start of struct st_rscan_from_rscan0tmidp */
    1317     union iodefine_reg32_t  TMID7;                         /*  TMID7           */
    1318     union iodefine_reg32_t  TMPTR7;                        /*  TMPTR7          */
    1319     union iodefine_reg32_t  TMDF07;                        /*  TMDF07          */
    1320     union iodefine_reg32_t  TMDF17;                        /*  TMDF17          */
    1321 /* end of struct st_rscan_from_rscan0tmidp */
    1322    
    1323 /* start of struct st_rscan_from_rscan0tmidp */
    1324     union iodefine_reg32_t  TMID8;                         /*  TMID8           */
    1325     union iodefine_reg32_t  TMPTR8;                        /*  TMPTR8          */
    1326     union iodefine_reg32_t  TMDF08;                        /*  TMDF08          */
    1327     union iodefine_reg32_t  TMDF18;                        /*  TMDF18          */
    1328 /* end of struct st_rscan_from_rscan0tmidp */
    1329    
    1330 /* start of struct st_rscan_from_rscan0tmidp */
    1331     union iodefine_reg32_t  TMID9;                         /*  TMID9           */
    1332     union iodefine_reg32_t  TMPTR9;                        /*  TMPTR9          */
    1333     union iodefine_reg32_t  TMDF09;                        /*  TMDF09          */
    1334     union iodefine_reg32_t  TMDF19;                        /*  TMDF19          */
    1335 /* end of struct st_rscan_from_rscan0tmidp */
    1336    
    1337 /* start of struct st_rscan_from_rscan0tmidp */
    1338     union iodefine_reg32_t  TMID10;                        /*  TMID10          */
    1339     union iodefine_reg32_t  TMPTR10;                       /*  TMPTR10         */
    1340     union iodefine_reg32_t  TMDF010;                       /*  TMDF010         */
    1341     union iodefine_reg32_t  TMDF110;                       /*  TMDF110         */
    1342 /* end of struct st_rscan_from_rscan0tmidp */
    1343    
    1344 /* start of struct st_rscan_from_rscan0tmidp */
    1345     union iodefine_reg32_t  TMID11;                        /*  TMID11          */
    1346     union iodefine_reg32_t  TMPTR11;                       /*  TMPTR11         */
    1347     union iodefine_reg32_t  TMDF011;                       /*  TMDF011         */
    1348     union iodefine_reg32_t  TMDF111;                       /*  TMDF111         */
    1349 /* end of struct st_rscan_from_rscan0tmidp */
    1350    
    1351 /* start of struct st_rscan_from_rscan0tmidp */
    1352     union iodefine_reg32_t  TMID12;                        /*  TMID12          */
    1353     union iodefine_reg32_t  TMPTR12;                       /*  TMPTR12         */
    1354     union iodefine_reg32_t  TMDF012;                       /*  TMDF012         */
    1355     union iodefine_reg32_t  TMDF112;                       /*  TMDF112         */
    1356 /* end of struct st_rscan_from_rscan0tmidp */
    1357    
    1358 /* start of struct st_rscan_from_rscan0tmidp */
    1359     union iodefine_reg32_t  TMID13;                        /*  TMID13          */
    1360     union iodefine_reg32_t  TMPTR13;                       /*  TMPTR13         */
    1361     union iodefine_reg32_t  TMDF013;                       /*  TMDF013         */
    1362     union iodefine_reg32_t  TMDF113;                       /*  TMDF113         */
    1363 /* end of struct st_rscan_from_rscan0tmidp */
    1364    
    1365 /* start of struct st_rscan_from_rscan0tmidp */
    1366     union iodefine_reg32_t  TMID14;                        /*  TMID14          */
    1367     union iodefine_reg32_t  TMPTR14;                       /*  TMPTR14         */
    1368     union iodefine_reg32_t  TMDF014;                       /*  TMDF014         */
    1369     union iodefine_reg32_t  TMDF114;                       /*  TMDF114         */
    1370 /* end of struct st_rscan_from_rscan0tmidp */
    1371    
    1372 /* start of struct st_rscan_from_rscan0tmidp */
    1373     union iodefine_reg32_t  TMID15;                        /*  TMID15          */
    1374     union iodefine_reg32_t  TMPTR15;                       /*  TMPTR15         */
    1375     union iodefine_reg32_t  TMDF015;                       /*  TMDF015         */
    1376     union iodefine_reg32_t  TMDF115;                       /*  TMDF115         */
    1377 /* end of struct st_rscan_from_rscan0tmidp */
    1378    
    1379 /* start of struct st_rscan_from_rscan0tmidp */
    1380     union iodefine_reg32_t  TMID16;                        /*  TMID16          */
    1381     union iodefine_reg32_t  TMPTR16;                       /*  TMPTR16         */
    1382     union iodefine_reg32_t  TMDF016;                       /*  TMDF016         */
    1383     union iodefine_reg32_t  TMDF116;                       /*  TMDF116         */
    1384 /* end of struct st_rscan_from_rscan0tmidp */
    1385    
    1386 /* start of struct st_rscan_from_rscan0tmidp */
    1387     union iodefine_reg32_t  TMID17;                        /*  TMID17          */
    1388     union iodefine_reg32_t  TMPTR17;                       /*  TMPTR17         */
    1389     union iodefine_reg32_t  TMDF017;                       /*  TMDF017         */
    1390     union iodefine_reg32_t  TMDF117;                       /*  TMDF117         */
    1391 /* end of struct st_rscan_from_rscan0tmidp */
    1392    
    1393 /* start of struct st_rscan_from_rscan0tmidp */
    1394     union iodefine_reg32_t  TMID18;                        /*  TMID18          */
    1395     union iodefine_reg32_t  TMPTR18;                       /*  TMPTR18         */
    1396     union iodefine_reg32_t  TMDF018;                       /*  TMDF018         */
    1397     union iodefine_reg32_t  TMDF118;                       /*  TMDF118         */
    1398 /* end of struct st_rscan_from_rscan0tmidp */
    1399    
    1400 /* start of struct st_rscan_from_rscan0tmidp */
    1401     union iodefine_reg32_t  TMID19;                        /*  TMID19          */
    1402     union iodefine_reg32_t  TMPTR19;                       /*  TMPTR19         */
    1403     union iodefine_reg32_t  TMDF019;                       /*  TMDF019         */
    1404     union iodefine_reg32_t  TMDF119;                       /*  TMDF119         */
    1405 /* end of struct st_rscan_from_rscan0tmidp */
    1406    
    1407 /* start of struct st_rscan_from_rscan0tmidp */
    1408     union iodefine_reg32_t  TMID20;                        /*  TMID20          */
    1409     union iodefine_reg32_t  TMPTR20;                       /*  TMPTR20         */
    1410     union iodefine_reg32_t  TMDF020;                       /*  TMDF020         */
    1411     union iodefine_reg32_t  TMDF120;                       /*  TMDF120         */
    1412 /* end of struct st_rscan_from_rscan0tmidp */
    1413    
    1414 /* start of struct st_rscan_from_rscan0tmidp */
    1415     union iodefine_reg32_t  TMID21;                        /*  TMID21          */
    1416     union iodefine_reg32_t  TMPTR21;                       /*  TMPTR21         */
    1417     union iodefine_reg32_t  TMDF021;                       /*  TMDF021         */
    1418     union iodefine_reg32_t  TMDF121;                       /*  TMDF121         */
    1419 /* end of struct st_rscan_from_rscan0tmidp */
    1420    
    1421 /* start of struct st_rscan_from_rscan0tmidp */
    1422     union iodefine_reg32_t  TMID22;                        /*  TMID22          */
    1423     union iodefine_reg32_t  TMPTR22;                       /*  TMPTR22         */
    1424     union iodefine_reg32_t  TMDF022;                       /*  TMDF022         */
    1425     union iodefine_reg32_t  TMDF122;                       /*  TMDF122         */
    1426 /* end of struct st_rscan_from_rscan0tmidp */
    1427    
    1428 /* start of struct st_rscan_from_rscan0tmidp */
    1429     union iodefine_reg32_t  TMID23;                        /*  TMID23          */
    1430     union iodefine_reg32_t  TMPTR23;                       /*  TMPTR23         */
    1431     union iodefine_reg32_t  TMDF023;                       /*  TMDF023         */
    1432     union iodefine_reg32_t  TMDF123;                       /*  TMDF123         */
    1433 /* end of struct st_rscan_from_rscan0tmidp */
    1434    
    1435 /* start of struct st_rscan_from_rscan0tmidp */
    1436     union iodefine_reg32_t  TMID24;                        /*  TMID24          */
    1437     union iodefine_reg32_t  TMPTR24;                       /*  TMPTR24         */
    1438     union iodefine_reg32_t  TMDF024;                       /*  TMDF024         */
    1439     union iodefine_reg32_t  TMDF124;                       /*  TMDF124         */
    1440 /* end of struct st_rscan_from_rscan0tmidp */
    1441    
    1442 /* start of struct st_rscan_from_rscan0tmidp */
    1443     union iodefine_reg32_t  TMID25;                        /*  TMID25          */
    1444     union iodefine_reg32_t  TMPTR25;                       /*  TMPTR25         */
    1445     union iodefine_reg32_t  TMDF025;                       /*  TMDF025         */
    1446     union iodefine_reg32_t  TMDF125;                       /*  TMDF125         */
    1447 /* end of struct st_rscan_from_rscan0tmidp */
    1448    
    1449 /* start of struct st_rscan_from_rscan0tmidp */
    1450     union iodefine_reg32_t  TMID26;                        /*  TMID26          */
    1451     union iodefine_reg32_t  TMPTR26;                       /*  TMPTR26         */
    1452     union iodefine_reg32_t  TMDF026;                       /*  TMDF026         */
    1453     union iodefine_reg32_t  TMDF126;                       /*  TMDF126         */
    1454 /* end of struct st_rscan_from_rscan0tmidp */
    1455    
    1456 /* start of struct st_rscan_from_rscan0tmidp */
    1457     union iodefine_reg32_t  TMID27;                        /*  TMID27          */
    1458     union iodefine_reg32_t  TMPTR27;                       /*  TMPTR27         */
    1459     union iodefine_reg32_t  TMDF027;                       /*  TMDF027         */
    1460     union iodefine_reg32_t  TMDF127;                       /*  TMDF127         */
    1461 /* end of struct st_rscan_from_rscan0tmidp */
    1462    
    1463 /* start of struct st_rscan_from_rscan0tmidp */
    1464     union iodefine_reg32_t  TMID28;                        /*  TMID28          */
    1465     union iodefine_reg32_t  TMPTR28;                       /*  TMPTR28         */
    1466     union iodefine_reg32_t  TMDF028;                       /*  TMDF028         */
    1467     union iodefine_reg32_t  TMDF128;                       /*  TMDF128         */
    1468 /* end of struct st_rscan_from_rscan0tmidp */
    1469    
    1470 /* start of struct st_rscan_from_rscan0tmidp */
    1471     union iodefine_reg32_t  TMID29;                        /*  TMID29          */
    1472     union iodefine_reg32_t  TMPTR29;                       /*  TMPTR29         */
    1473     union iodefine_reg32_t  TMDF029;                       /*  TMDF029         */
    1474     union iodefine_reg32_t  TMDF129;                       /*  TMDF129         */
    1475 /* end of struct st_rscan_from_rscan0tmidp */
    1476    
    1477 /* start of struct st_rscan_from_rscan0tmidp */
    1478     union iodefine_reg32_t  TMID30;                        /*  TMID30          */
    1479     union iodefine_reg32_t  TMPTR30;                       /*  TMPTR30         */
    1480     union iodefine_reg32_t  TMDF030;                       /*  TMDF030         */
    1481     union iodefine_reg32_t  TMDF130;                       /*  TMDF130         */
    1482 /* end of struct st_rscan_from_rscan0tmidp */
    1483    
    1484 /* start of struct st_rscan_from_rscan0tmidp */
    1485     union iodefine_reg32_t  TMID31;                        /*  TMID31          */
    1486     union iodefine_reg32_t  TMPTR31;                       /*  TMPTR31         */
    1487     union iodefine_reg32_t  TMDF031;                       /*  TMDF031         */
    1488     union iodefine_reg32_t  TMDF131;                       /*  TMDF131         */
    1489 /* end of struct st_rscan_from_rscan0tmidp */
    1490    
    1491 /* start of struct st_rscan_from_rscan0tmidp */
    1492     union iodefine_reg32_t  TMID32;                        /*  TMID32          */
    1493     union iodefine_reg32_t  TMPTR32;                       /*  TMPTR32         */
    1494     union iodefine_reg32_t  TMDF032;                       /*  TMDF032         */
    1495     union iodefine_reg32_t  TMDF132;                       /*  TMDF132         */
    1496 /* end of struct st_rscan_from_rscan0tmidp */
    1497    
    1498 /* start of struct st_rscan_from_rscan0tmidp */
    1499     union iodefine_reg32_t  TMID33;                        /*  TMID33          */
    1500     union iodefine_reg32_t  TMPTR33;                       /*  TMPTR33         */
    1501     union iodefine_reg32_t  TMDF033;                       /*  TMDF033         */
    1502     union iodefine_reg32_t  TMDF133;                       /*  TMDF133         */
    1503 /* end of struct st_rscan_from_rscan0tmidp */
    1504    
    1505 /* start of struct st_rscan_from_rscan0tmidp */
    1506     union iodefine_reg32_t  TMID34;                        /*  TMID34          */
    1507     union iodefine_reg32_t  TMPTR34;                       /*  TMPTR34         */
    1508     union iodefine_reg32_t  TMDF034;                       /*  TMDF034         */
    1509     union iodefine_reg32_t  TMDF134;                       /*  TMDF134         */
    1510 /* end of struct st_rscan_from_rscan0tmidp */
    1511    
    1512 /* start of struct st_rscan_from_rscan0tmidp */
    1513     union iodefine_reg32_t  TMID35;                        /*  TMID35          */
    1514     union iodefine_reg32_t  TMPTR35;                       /*  TMPTR35         */
    1515     union iodefine_reg32_t  TMDF035;                       /*  TMDF035         */
    1516     union iodefine_reg32_t  TMDF135;                       /*  TMDF135         */
    1517 /* end of struct st_rscan_from_rscan0tmidp */
    1518    
    1519 /* start of struct st_rscan_from_rscan0tmidp */
    1520     union iodefine_reg32_t  TMID36;                        /*  TMID36          */
    1521     union iodefine_reg32_t  TMPTR36;                       /*  TMPTR36         */
    1522     union iodefine_reg32_t  TMDF036;                       /*  TMDF036         */
    1523     union iodefine_reg32_t  TMDF136;                       /*  TMDF136         */
    1524 /* end of struct st_rscan_from_rscan0tmidp */
    1525    
    1526 /* start of struct st_rscan_from_rscan0tmidp */
    1527     union iodefine_reg32_t  TMID37;                        /*  TMID37          */
    1528     union iodefine_reg32_t  TMPTR37;                       /*  TMPTR37         */
    1529     union iodefine_reg32_t  TMDF037;                       /*  TMDF037         */
    1530     union iodefine_reg32_t  TMDF137;                       /*  TMDF137         */
    1531 /* end of struct st_rscan_from_rscan0tmidp */
    1532    
    1533 /* start of struct st_rscan_from_rscan0tmidp */
    1534     union iodefine_reg32_t  TMID38;                        /*  TMID38          */
    1535     union iodefine_reg32_t  TMPTR38;                       /*  TMPTR38         */
    1536     union iodefine_reg32_t  TMDF038;                       /*  TMDF038         */
    1537     union iodefine_reg32_t  TMDF138;                       /*  TMDF138         */
    1538 /* end of struct st_rscan_from_rscan0tmidp */
    1539    
    1540 /* start of struct st_rscan_from_rscan0tmidp */
    1541     union iodefine_reg32_t  TMID39;                        /*  TMID39          */
    1542     union iodefine_reg32_t  TMPTR39;                       /*  TMPTR39         */
    1543     union iodefine_reg32_t  TMDF039;                       /*  TMDF039         */
    1544     union iodefine_reg32_t  TMDF139;                       /*  TMDF139         */
    1545 /* end of struct st_rscan_from_rscan0tmidp */
    1546    
    1547 /* start of struct st_rscan_from_rscan0tmidp */
    1548     union iodefine_reg32_t  TMID40;                        /*  TMID40          */
    1549     union iodefine_reg32_t  TMPTR40;                       /*  TMPTR40         */
    1550     union iodefine_reg32_t  TMDF040;                       /*  TMDF040         */
    1551     union iodefine_reg32_t  TMDF140;                       /*  TMDF140         */
    1552 /* end of struct st_rscan_from_rscan0tmidp */
    1553    
    1554 /* start of struct st_rscan_from_rscan0tmidp */
    1555     union iodefine_reg32_t  TMID41;                        /*  TMID41          */
    1556     union iodefine_reg32_t  TMPTR41;                       /*  TMPTR41         */
    1557     union iodefine_reg32_t  TMDF041;                       /*  TMDF041         */
    1558     union iodefine_reg32_t  TMDF141;                       /*  TMDF141         */
    1559 /* end of struct st_rscan_from_rscan0tmidp */
    1560    
    1561 /* start of struct st_rscan_from_rscan0tmidp */
    1562     union iodefine_reg32_t  TMID42;                        /*  TMID42          */
    1563     union iodefine_reg32_t  TMPTR42;                       /*  TMPTR42         */
    1564     union iodefine_reg32_t  TMDF042;                       /*  TMDF042         */
    1565     union iodefine_reg32_t  TMDF142;                       /*  TMDF142         */
    1566 /* end of struct st_rscan_from_rscan0tmidp */
    1567    
    1568 /* start of struct st_rscan_from_rscan0tmidp */
    1569     union iodefine_reg32_t  TMID43;                        /*  TMID43          */
    1570     union iodefine_reg32_t  TMPTR43;                       /*  TMPTR43         */
    1571     union iodefine_reg32_t  TMDF043;                       /*  TMDF043         */
    1572     union iodefine_reg32_t  TMDF143;                       /*  TMDF143         */
    1573 /* end of struct st_rscan_from_rscan0tmidp */
    1574    
    1575 /* start of struct st_rscan_from_rscan0tmidp */
    1576     union iodefine_reg32_t  TMID44;                        /*  TMID44          */
    1577     union iodefine_reg32_t  TMPTR44;                       /*  TMPTR44         */
    1578     union iodefine_reg32_t  TMDF044;                       /*  TMDF044         */
    1579     union iodefine_reg32_t  TMDF144;                       /*  TMDF144         */
    1580 /* end of struct st_rscan_from_rscan0tmidp */
    1581    
    1582 /* start of struct st_rscan_from_rscan0tmidp */
    1583     union iodefine_reg32_t  TMID45;                        /*  TMID45          */
    1584     union iodefine_reg32_t  TMPTR45;                       /*  TMPTR45         */
    1585     union iodefine_reg32_t  TMDF045;                       /*  TMDF045         */
    1586     union iodefine_reg32_t  TMDF145;                       /*  TMDF145         */
    1587 /* end of struct st_rscan_from_rscan0tmidp */
    1588    
    1589 /* start of struct st_rscan_from_rscan0tmidp */
    1590     union iodefine_reg32_t  TMID46;                        /*  TMID46          */
    1591     union iodefine_reg32_t  TMPTR46;                       /*  TMPTR46         */
    1592     union iodefine_reg32_t  TMDF046;                       /*  TMDF046         */
    1593     union iodefine_reg32_t  TMDF146;                       /*  TMDF146         */
    1594 /* end of struct st_rscan_from_rscan0tmidp */
    1595    
    1596 /* start of struct st_rscan_from_rscan0tmidp */
    1597     union iodefine_reg32_t  TMID47;                        /*  TMID47          */
    1598     union iodefine_reg32_t  TMPTR47;                       /*  TMPTR47         */
    1599     union iodefine_reg32_t  TMDF047;                       /*  TMDF047         */
    1600     union iodefine_reg32_t  TMDF147;                       /*  TMDF147         */
    1601 /* end of struct st_rscan_from_rscan0tmidp */
    1602    
    1603 /* start of struct st_rscan_from_rscan0tmidp */
    1604     union iodefine_reg32_t  TMID48;                        /*  TMID48          */
    1605     union iodefine_reg32_t  TMPTR48;                       /*  TMPTR48         */
    1606     union iodefine_reg32_t  TMDF048;                       /*  TMDF048         */
    1607     union iodefine_reg32_t  TMDF148;                       /*  TMDF148         */
    1608 /* end of struct st_rscan_from_rscan0tmidp */
    1609    
    1610 /* start of struct st_rscan_from_rscan0tmidp */
    1611     union iodefine_reg32_t  TMID49;                        /*  TMID49          */
    1612     union iodefine_reg32_t  TMPTR49;                       /*  TMPTR49         */
    1613     union iodefine_reg32_t  TMDF049;                       /*  TMDF049         */
    1614     union iodefine_reg32_t  TMDF149;                       /*  TMDF149         */
    1615 /* end of struct st_rscan_from_rscan0tmidp */
    1616    
    1617 /* start of struct st_rscan_from_rscan0tmidp */
    1618     union iodefine_reg32_t  TMID50;                        /*  TMID50          */
    1619     union iodefine_reg32_t  TMPTR50;                       /*  TMPTR50         */
    1620     union iodefine_reg32_t  TMDF050;                       /*  TMDF050         */
    1621     union iodefine_reg32_t  TMDF150;                       /*  TMDF150         */
    1622 /* end of struct st_rscan_from_rscan0tmidp */
    1623    
    1624 /* start of struct st_rscan_from_rscan0tmidp */
    1625     union iodefine_reg32_t  TMID51;                        /*  TMID51          */
    1626     union iodefine_reg32_t  TMPTR51;                       /*  TMPTR51         */
    1627     union iodefine_reg32_t  TMDF051;                       /*  TMDF051         */
    1628     union iodefine_reg32_t  TMDF151;                       /*  TMDF151         */
    1629 /* end of struct st_rscan_from_rscan0tmidp */
    1630    
    1631 /* start of struct st_rscan_from_rscan0tmidp */
    1632     union iodefine_reg32_t  TMID52;                        /*  TMID52          */
    1633     union iodefine_reg32_t  TMPTR52;                       /*  TMPTR52         */
    1634     union iodefine_reg32_t  TMDF052;                       /*  TMDF052         */
    1635     union iodefine_reg32_t  TMDF152;                       /*  TMDF152         */
    1636 /* end of struct st_rscan_from_rscan0tmidp */
    1637    
    1638 /* start of struct st_rscan_from_rscan0tmidp */
    1639     union iodefine_reg32_t  TMID53;                        /*  TMID53          */
    1640     union iodefine_reg32_t  TMPTR53;                       /*  TMPTR53         */
    1641     union iodefine_reg32_t  TMDF053;                       /*  TMDF053         */
    1642     union iodefine_reg32_t  TMDF153;                       /*  TMDF153         */
    1643 /* end of struct st_rscan_from_rscan0tmidp */
    1644    
    1645 /* start of struct st_rscan_from_rscan0tmidp */
    1646     union iodefine_reg32_t  TMID54;                        /*  TMID54          */
    1647     union iodefine_reg32_t  TMPTR54;                       /*  TMPTR54         */
    1648     union iodefine_reg32_t  TMDF054;                       /*  TMDF054         */
    1649     union iodefine_reg32_t  TMDF154;                       /*  TMDF154         */
    1650 /* end of struct st_rscan_from_rscan0tmidp */
    1651    
    1652 /* start of struct st_rscan_from_rscan0tmidp */
    1653     union iodefine_reg32_t  TMID55;                        /*  TMID55          */
    1654     union iodefine_reg32_t  TMPTR55;                       /*  TMPTR55         */
    1655     union iodefine_reg32_t  TMDF055;                       /*  TMDF055         */
    1656     union iodefine_reg32_t  TMDF155;                       /*  TMDF155         */
    1657 /* end of struct st_rscan_from_rscan0tmidp */
    1658    
    1659 /* start of struct st_rscan_from_rscan0tmidp */
    1660     union iodefine_reg32_t  TMID56;                        /*  TMID56          */
    1661     union iodefine_reg32_t  TMPTR56;                       /*  TMPTR56         */
    1662     union iodefine_reg32_t  TMDF056;                       /*  TMDF056         */
    1663     union iodefine_reg32_t  TMDF156;                       /*  TMDF156         */
    1664 /* end of struct st_rscan_from_rscan0tmidp */
    1665    
    1666 /* start of struct st_rscan_from_rscan0tmidp */
    1667     union iodefine_reg32_t  TMID57;                        /*  TMID57          */
    1668     union iodefine_reg32_t  TMPTR57;                       /*  TMPTR57         */
    1669     union iodefine_reg32_t  TMDF057;                       /*  TMDF057         */
    1670     union iodefine_reg32_t  TMDF157;                       /*  TMDF157         */
    1671 /* end of struct st_rscan_from_rscan0tmidp */
    1672    
    1673 /* start of struct st_rscan_from_rscan0tmidp */
    1674     union iodefine_reg32_t  TMID58;                        /*  TMID58          */
    1675     union iodefine_reg32_t  TMPTR58;                       /*  TMPTR58         */
    1676     union iodefine_reg32_t  TMDF058;                       /*  TMDF058         */
    1677     union iodefine_reg32_t  TMDF158;                       /*  TMDF158         */
    1678 /* end of struct st_rscan_from_rscan0tmidp */
    1679    
    1680 /* start of struct st_rscan_from_rscan0tmidp */
    1681     union iodefine_reg32_t  TMID59;                        /*  TMID59          */
    1682     union iodefine_reg32_t  TMPTR59;                       /*  TMPTR59         */
    1683     union iodefine_reg32_t  TMDF059;                       /*  TMDF059         */
    1684     union iodefine_reg32_t  TMDF159;                       /*  TMDF159         */
    1685 /* end of struct st_rscan_from_rscan0tmidp */
    1686    
    1687 /* start of struct st_rscan_from_rscan0tmidp */
    1688     union iodefine_reg32_t  TMID60;                        /*  TMID60          */
    1689     union iodefine_reg32_t  TMPTR60;                       /*  TMPTR60         */
    1690     union iodefine_reg32_t  TMDF060;                       /*  TMDF060         */
    1691     union iodefine_reg32_t  TMDF160;                       /*  TMDF160         */
    1692 /* end of struct st_rscan_from_rscan0tmidp */
    1693    
    1694 /* start of struct st_rscan_from_rscan0tmidp */
    1695     union iodefine_reg32_t  TMID61;                        /*  TMID61          */
    1696     union iodefine_reg32_t  TMPTR61;                       /*  TMPTR61         */
    1697     union iodefine_reg32_t  TMDF061;                       /*  TMDF061         */
    1698     union iodefine_reg32_t  TMDF161;                       /*  TMDF161         */
    1699 /* end of struct st_rscan_from_rscan0tmidp */
    1700    
    1701 /* start of struct st_rscan_from_rscan0tmidp */
    1702     union iodefine_reg32_t  TMID62;                        /*  TMID62          */
    1703     union iodefine_reg32_t  TMPTR62;                       /*  TMPTR62         */
    1704     union iodefine_reg32_t  TMDF062;                       /*  TMDF062         */
    1705     union iodefine_reg32_t  TMDF162;                       /*  TMDF162         */
    1706 /* end of struct st_rscan_from_rscan0tmidp */
    1707    
    1708 /* start of struct st_rscan_from_rscan0tmidp */
    1709     union iodefine_reg32_t  TMID63;                        /*  TMID63          */
    1710     union iodefine_reg32_t  TMPTR63;                       /*  TMPTR63         */
    1711     union iodefine_reg32_t  TMDF063;                       /*  TMDF063         */
    1712     union iodefine_reg32_t  TMDF163;                       /*  TMDF163         */
    1713 /* end of struct st_rscan_from_rscan0tmidp */
    1714    
    1715 /* start of struct st_rscan_from_rscan0tmidp */
    1716     union iodefine_reg32_t  TMID64;                        /*  TMID64          */
    1717     union iodefine_reg32_t  TMPTR64;                       /*  TMPTR64         */
    1718     union iodefine_reg32_t  TMDF064;                       /*  TMDF064         */
    1719     union iodefine_reg32_t  TMDF164;                       /*  TMDF164         */
    1720 /* end of struct st_rscan_from_rscan0tmidp */
    1721    
    1722 /* start of struct st_rscan_from_rscan0tmidp */
    1723     union iodefine_reg32_t  TMID65;                        /*  TMID65          */
    1724     union iodefine_reg32_t  TMPTR65;                       /*  TMPTR65         */
    1725     union iodefine_reg32_t  TMDF065;                       /*  TMDF065         */
    1726     union iodefine_reg32_t  TMDF165;                       /*  TMDF165         */
    1727 /* end of struct st_rscan_from_rscan0tmidp */
    1728    
    1729 /* start of struct st_rscan_from_rscan0tmidp */
    1730     union iodefine_reg32_t  TMID66;                        /*  TMID66          */
    1731     union iodefine_reg32_t  TMPTR66;                       /*  TMPTR66         */
    1732     union iodefine_reg32_t  TMDF066;                       /*  TMDF066         */
    1733     union iodefine_reg32_t  TMDF166;                       /*  TMDF166         */
    1734 /* end of struct st_rscan_from_rscan0tmidp */
    1735    
    1736 /* start of struct st_rscan_from_rscan0tmidp */
    1737     union iodefine_reg32_t  TMID67;                        /*  TMID67          */
    1738     union iodefine_reg32_t  TMPTR67;                       /*  TMPTR67         */
    1739     union iodefine_reg32_t  TMDF067;                       /*  TMDF067         */
    1740     union iodefine_reg32_t  TMDF167;                       /*  TMDF167         */
    1741 /* end of struct st_rscan_from_rscan0tmidp */
    1742    
    1743 /* start of struct st_rscan_from_rscan0tmidp */
    1744     union iodefine_reg32_t  TMID68;                        /*  TMID68          */
    1745     union iodefine_reg32_t  TMPTR68;                       /*  TMPTR68         */
    1746     union iodefine_reg32_t  TMDF068;                       /*  TMDF068         */
    1747     union iodefine_reg32_t  TMDF168;                       /*  TMDF168         */
    1748 /* end of struct st_rscan_from_rscan0tmidp */
    1749    
    1750 /* start of struct st_rscan_from_rscan0tmidp */
    1751     union iodefine_reg32_t  TMID69;                        /*  TMID69          */
    1752     union iodefine_reg32_t  TMPTR69;                       /*  TMPTR69         */
    1753     union iodefine_reg32_t  TMDF069;                       /*  TMDF069         */
    1754     union iodefine_reg32_t  TMDF169;                       /*  TMDF169         */
    1755 /* end of struct st_rscan_from_rscan0tmidp */
    1756    
    1757 /* start of struct st_rscan_from_rscan0tmidp */
    1758     union iodefine_reg32_t  TMID70;                        /*  TMID70          */
    1759     union iodefine_reg32_t  TMPTR70;                       /*  TMPTR70         */
    1760     union iodefine_reg32_t  TMDF070;                       /*  TMDF070         */
    1761     union iodefine_reg32_t  TMDF170;                       /*  TMDF170         */
    1762 /* end of struct st_rscan_from_rscan0tmidp */
    1763    
    1764 /* start of struct st_rscan_from_rscan0tmidp */
    1765     union iodefine_reg32_t  TMID71;                        /*  TMID71          */
    1766     union iodefine_reg32_t  TMPTR71;                       /*  TMPTR71         */
    1767     union iodefine_reg32_t  TMDF071;                       /*  TMDF071         */
    1768     union iodefine_reg32_t  TMDF171;                       /*  TMDF171         */
    1769 /* end of struct st_rscan_from_rscan0tmidp */
    1770    
    1771 /* start of struct st_rscan_from_rscan0tmidp */
    1772     union iodefine_reg32_t  TMID72;                        /*  TMID72          */
    1773     union iodefine_reg32_t  TMPTR72;                       /*  TMPTR72         */
    1774     union iodefine_reg32_t  TMDF072;                       /*  TMDF072         */
    1775     union iodefine_reg32_t  TMDF172;                       /*  TMDF172         */
    1776 /* end of struct st_rscan_from_rscan0tmidp */
    1777    
    1778 /* start of struct st_rscan_from_rscan0tmidp */
    1779     union iodefine_reg32_t  TMID73;                        /*  TMID73          */
    1780     union iodefine_reg32_t  TMPTR73;                       /*  TMPTR73         */
    1781     union iodefine_reg32_t  TMDF073;                       /*  TMDF073         */
    1782     union iodefine_reg32_t  TMDF173;                       /*  TMDF173         */
    1783 /* end of struct st_rscan_from_rscan0tmidp */
    1784    
    1785 /* start of struct st_rscan_from_rscan0tmidp */
    1786     union iodefine_reg32_t  TMID74;                        /*  TMID74          */
    1787     union iodefine_reg32_t  TMPTR74;                       /*  TMPTR74         */
    1788     union iodefine_reg32_t  TMDF074;                       /*  TMDF074         */
    1789     union iodefine_reg32_t  TMDF174;                       /*  TMDF174         */
    1790 /* end of struct st_rscan_from_rscan0tmidp */
    1791    
    1792 /* start of struct st_rscan_from_rscan0tmidp */
    1793     union iodefine_reg32_t  TMID75;                        /*  TMID75          */
    1794     union iodefine_reg32_t  TMPTR75;                       /*  TMPTR75         */
    1795     union iodefine_reg32_t  TMDF075;                       /*  TMDF075         */
    1796     union iodefine_reg32_t  TMDF175;                       /*  TMDF175         */
    1797 /* end of struct st_rscan_from_rscan0tmidp */
    1798    
    1799 /* start of struct st_rscan_from_rscan0tmidp */
    1800     union iodefine_reg32_t  TMID76;                        /*  TMID76          */
    1801     union iodefine_reg32_t  TMPTR76;                       /*  TMPTR76         */
    1802     union iodefine_reg32_t  TMDF076;                       /*  TMDF076         */
    1803     union iodefine_reg32_t  TMDF176;                       /*  TMDF176         */
    1804 /* end of struct st_rscan_from_rscan0tmidp */
    1805    
    1806 /* start of struct st_rscan_from_rscan0tmidp */
    1807     union iodefine_reg32_t  TMID77;                        /*  TMID77          */
    1808     union iodefine_reg32_t  TMPTR77;                       /*  TMPTR77         */
    1809     union iodefine_reg32_t  TMDF077;                       /*  TMDF077         */
    1810     union iodefine_reg32_t  TMDF177;                       /*  TMDF177         */
    1811 /* end of struct st_rscan_from_rscan0tmidp */
    1812    
    1813 /* start of struct st_rscan_from_rscan0tmidp */
    1814     union iodefine_reg32_t  TMID78;                        /*  TMID78          */
    1815     union iodefine_reg32_t  TMPTR78;                       /*  TMPTR78         */
    1816     union iodefine_reg32_t  TMDF078;                       /*  TMDF078         */
    1817     union iodefine_reg32_t  TMDF178;                       /*  TMDF178         */
    1818 /* end of struct st_rscan_from_rscan0tmidp */
    1819    
    1820 /* start of struct st_rscan_from_rscan0tmidp */
    1821     union iodefine_reg32_t  TMID79;                        /*  TMID79          */
    1822     union iodefine_reg32_t  TMPTR79;                       /*  TMPTR79         */
    1823     union iodefine_reg32_t  TMDF079;                       /*  TMDF079         */
    1824     union iodefine_reg32_t  TMDF179;                       /*  TMDF179         */
    1825 /* end of struct st_rscan_from_rscan0tmidp */
    1826    
    1827     volatile uint8_t   dummy181[768];                          /*                  */
    1828 #define RSCAN0_THLACC0_COUNT 5
    1829     union iodefine_reg32_t  THLACC0;                       /*  THLACC0         */
    1830     union iodefine_reg32_t  THLACC1;                       /*  THLACC1         */
    1831     union iodefine_reg32_t  THLACC2;                       /*  THLACC2         */
    1832     union iodefine_reg32_t  THLACC3;                       /*  THLACC3         */
    1833     union iodefine_reg32_t  THLACC4;                       /*  THLACC4         */
    1834    
    1835 };
    1836 
    1837 
    1838 struct st_rscan_from_rscan0cncfg
    1839 {
    1840     union iodefine_reg32_t  CnCFG;                         /*  CnCFG           */
    1841     union iodefine_reg32_t  CnCTR;                         /*  CnCTR           */
    1842     union iodefine_reg32_t  CnSTS;                         /*  CnSTS           */
    1843     union iodefine_reg32_t  CnERFL;                        /*  CnERFL          */
    1844 };
    1845 
    1846 
    1847 struct st_rscan_from_rscan0gaflidj
    1848 {
    1849     union iodefine_reg32_t  GAFLIDj;                       /*  GAFLIDj         */
    1850     union iodefine_reg32_t  GAFLMj;                        /*  GAFLMj          */
    1851     union iodefine_reg32_t  GAFLP0j;                       /*  GAFLP0j         */
    1852     union iodefine_reg32_t  GAFLP1j;                       /*  GAFLP1j         */
    1853 };
    1854 
    1855 
    1856 struct st_rscan_from_rscan0rmidp
    1857 {
    1858     union iodefine_reg32_t  RMIDp;                         /*  RMIDp           */
    1859     union iodefine_reg32_t  RMPTRp;                        /*  RMPTRp          */
    1860     union iodefine_reg32_t  RMDF0p;                        /*  RMDF0p          */
    1861     union iodefine_reg32_t  RMDF1p;                        /*  RMDF1p          */
    1862 };
    1863 
    1864 
    1865 struct st_rscan_from_rscan0rfidm
    1866 {
    1867     union iodefine_reg32_t  RFIDm;                         /*  RFIDm           */
    1868     union iodefine_reg32_t  RFPTRm;                        /*  RFPTRm          */
    1869     union iodefine_reg32_t  RFDF0m;                        /*  RFDF0m          */
    1870     union iodefine_reg32_t  RFDF1m;                        /*  RFDF1m          */
    1871 };
    1872 
    1873 
    1874 struct st_rscan_from_rscan0tmidp
    1875 {
    1876     union iodefine_reg32_t  TMIDp;                         /*  TMIDp           */
    1877     union iodefine_reg32_t  TMPTRp;                        /*  TMPTRp          */
    1878     union iodefine_reg32_t  TMDF0p;                        /*  TMDF0p          */
    1879     union iodefine_reg32_t  TMDF1p;                        /*  TMDF1p          */
    1880 };
    1881 
    1882 
    1883 struct st_rscan_from_rscan0cfidm
    1884 {
    1885     union iodefine_reg32_t  CFIDm;                         /*  CFIDm           */
    1886     union iodefine_reg32_t  CFPTRm;                        /*  CFPTRm          */
    1887     union iodefine_reg32_t  CFDF0m;                        /*  CFDF0m          */
    1888     union iodefine_reg32_t  CFDF1m;                        /*  CFDF1m          */
    1889 };
    1890 
    1891 
    189236#define RSCAN0  (*(struct st_rscan0  *)0xE803A000uL) /* RSCAN0 */
    189337
    189438
    1895 /* Start of channnel array defines of RSCAN0 */
    1896 
    1897 /* Channnel array defines of RSCAN_FROM_RSCAN0CFIDm */
    1898 /*(Sample) value = RSCAN_FROM_RSCAN0CFIDm[ channel ]->CFIDm.UINT32; */
    1899 #define RSCAN_FROM_RSCAN0CFIDm_COUNT  15
    1900 #define RSCAN_FROM_RSCAN0CFIDm_ADDRESS_LIST \
     39/* Start of channel array defines of RSCAN0 */
     40
     41/* Channel array defines of RSCAN_FROM_RSCAN0_CFIDm */
     42/*(Sample) value = RSCAN_FROM_RSCAN0_CFIDm[ channel ]->CFIDm.UINT32; */
     43#define RSCAN_FROM_RSCAN0_CFIDm_COUNT  (15)
     44#define RSCAN_FROM_RSCAN0_CFIDm_ADDRESS_LIST \
    190145{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    190246    &RSCAN_FROM_RSCAN0CFID0, &RSCAN_FROM_RSCAN0CFID1, &RSCAN_FROM_RSCAN0CFID2, &RSCAN_FROM_RSCAN0CFID3, &RSCAN_FROM_RSCAN0CFID4, &RSCAN_FROM_RSCAN0CFID5, &RSCAN_FROM_RSCAN0CFID6, &RSCAN_FROM_RSCAN0CFID7, \
    … …  
    192064
    192165
    1922 /* Channnel array defines of RSCAN_FROM_RSCAN0TMIDp */
    1923 /*(Sample) value = RSCAN_FROM_RSCAN0TMIDp[ channel ]->TMIDp.UINT32; */
    1924 #define RSCAN_FROM_RSCAN0TMIDp_COUNT  80
    1925 #define RSCAN_FROM_RSCAN0TMIDp_ADDRESS_LIST \
     66/* Channel array defines of RSCAN_FROM_RSCAN0_TMIDp */
     67/*(Sample) value = RSCAN_FROM_RSCAN0_TMIDp[ channel ]->TMIDp.UINT32; */
     68#define RSCAN_FROM_RSCAN0_TMIDp_COUNT  (80)
     69#define RSCAN_FROM_RSCAN0_TMIDp_ADDRESS_LIST \
    192670{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    192771    &RSCAN_FROM_RSCAN0TMID0, &RSCAN_FROM_RSCAN0TMID1, &RSCAN_FROM_RSCAN0TMID2, &RSCAN_FROM_RSCAN0TMID3, &RSCAN_FROM_RSCAN0TMID4, &RSCAN_FROM_RSCAN0TMID5, &RSCAN_FROM_RSCAN0TMID6, &RSCAN_FROM_RSCAN0TMID7, \
    … …  
    2018162
    2019163
    2020 /* Channnel array defines of RSCAN_FROM_RSCAN0RFIDm */
    2021 /*(Sample) value = RSCAN_FROM_RSCAN0RFIDm[ channel ]->RFIDm.UINT32; */
    2022 #define RSCAN_FROM_RSCAN0RFIDm_COUNT  8
    2023 #define RSCAN_FROM_RSCAN0RFIDm_ADDRESS_LIST \
     164/* Channel array defines of RSCAN_FROM_RSCAN0_RFIDm */
     165/*(Sample) value = RSCAN_FROM_RSCAN0_RFIDm[ channel ]->RFIDm.UINT32; */
     166#define RSCAN_FROM_RSCAN0_RFIDm_COUNT  (8)
     167#define RSCAN_FROM_RSCAN0_RFIDm_ADDRESS_LIST \
    2024168{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    2025169    &RSCAN_FROM_RSCAN0RFID0, &RSCAN_FROM_RSCAN0RFID1, &RSCAN_FROM_RSCAN0RFID2, &RSCAN_FROM_RSCAN0RFID3, &RSCAN_FROM_RSCAN0RFID4, &RSCAN_FROM_RSCAN0RFID5, &RSCAN_FROM_RSCAN0RFID6, &RSCAN_FROM_RSCAN0RFID7 \
    … …  
    2035179
    2036180
    2037 /* Channnel array defines of RSCAN_FROM_RSCAN0RMIDp */
    2038 /*(Sample) value = RSCAN_FROM_RSCAN0RMIDp[ channel ]->RMIDp.UINT32; */
    2039 #define RSCAN_FROM_RSCAN0RMIDp_COUNT  80
    2040 #define RSCAN_FROM_RSCAN0RMIDp_ADDRESS_LIST \
     181/* Channel array defines of RSCAN_FROM_RSCAN0_RMIDp */
     182/*(Sample) value = RSCAN_FROM_RSCAN0_RMIDp[ channel ]->RMIDp.UINT32; */
     183#define RSCAN_FROM_RSCAN0_RMIDp_COUNT  (80)
     184#define RSCAN_FROM_RSCAN0_RMIDp_ADDRESS_LIST \
    2041185{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    2042186    &RSCAN_FROM_RSCAN0RMID0, &RSCAN_FROM_RSCAN0RMID1, &RSCAN_FROM_RSCAN0RMID2, &RSCAN_FROM_RSCAN0RMID3, &RSCAN_FROM_RSCAN0RMID4, &RSCAN_FROM_RSCAN0RMID5, &RSCAN_FROM_RSCAN0RMID6, &RSCAN_FROM_RSCAN0RMID7, \
    … …  
    2133277
    2134278
    2135 /* Channnel array defines of RSCAN_FROM_RSCAN0GAFLIDj */
    2136 /*(Sample) value = RSCAN_FROM_RSCAN0GAFLIDj[ channel ]->GAFLIDj.UINT32; */
    2137 #define RSCAN_FROM_RSCAN0GAFLIDj_COUNT  16
    2138 #define RSCAN_FROM_RSCAN0GAFLIDj_ADDRESS_LIST \
     279/* Channel array defines of RSCAN_FROM_RSCAN0_GAFLIDj */
     280/*(Sample) value = RSCAN_FROM_RSCAN0_GAFLIDj[ channel ]->GAFLIDj.UINT32; */
     281#define RSCAN_FROM_RSCAN0_GAFLIDj_COUNT  (16)
     282#define RSCAN_FROM_RSCAN0_GAFLIDj_ADDRESS_LIST \
    2139283{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    2140284    &RSCAN_FROM_RSCAN0GAFLID0, &RSCAN_FROM_RSCAN0GAFLID1, &RSCAN_FROM_RSCAN0GAFLID2, &RSCAN_FROM_RSCAN0GAFLID3, &RSCAN_FROM_RSCAN0GAFLID4, &RSCAN_FROM_RSCAN0GAFLID5, &RSCAN_FROM_RSCAN0GAFLID6, &RSCAN_FROM_RSCAN0GAFLID7, \
    … …  
    2159303
    2160304
    2161 /* Channnel array defines of RSCAN_FROM_RSCAN0CnCFG */
    2162 /*(Sample) value = RSCAN_FROM_RSCAN0CnCFG[ channel ]->CnCFG.UINT32; */
    2163 #define RSCAN_FROM_RSCAN0CnCFG_COUNT  5
    2164 #define RSCAN_FROM_RSCAN0CnCFG_ADDRESS_LIST \
     305/* Channel array defines of RSCAN_FROM_RSCAN0_CnCFG */
     306/*(Sample) value = RSCAN_FROM_RSCAN0_CnCFG[ channel ]->CnCFG.UINT32; */
     307#define RSCAN_FROM_RSCAN0_CnCFG_COUNT  (5)
     308#define RSCAN_FROM_RSCAN0_CnCFG_ADDRESS_LIST \
    2165309{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    2166310    &RSCAN_FROM_RSCAN0C0CFG, &RSCAN_FROM_RSCAN0C1CFG, &RSCAN_FROM_RSCAN0C2CFG, &RSCAN_FROM_RSCAN0C3CFG, &RSCAN_FROM_RSCAN0C4CFG \
    … …  
    2172316#define RSCAN_FROM_RSCAN0C4CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C4CFG) /* RSCAN_FROM_RSCAN0C4CFG */
    2173317
    2174 /* End of channnel array defines of RSCAN0 */
    2175 
    2176 
    2177 #define RSCAN0C0CFG RSCAN0.C0CFG.UINT32
    2178 #define RSCAN0C0CFGL RSCAN0.C0CFG.UINT16[L]
    2179 #define RSCAN0C0CFGLL RSCAN0.C0CFG.UINT8[LL]
    2180 #define RSCAN0C0CFGLH RSCAN0.C0CFG.UINT8[LH]
    2181 #define RSCAN0C0CFGH RSCAN0.C0CFG.UINT16[H]
    2182 #define RSCAN0C0CFGHL RSCAN0.C0CFG.UINT8[HL]
    2183 #define RSCAN0C0CFGHH RSCAN0.C0CFG.UINT8[HH]
    2184 #define RSCAN0C0CTR RSCAN0.C0CTR.UINT32
    2185 #define RSCAN0C0CTRL RSCAN0.C0CTR.UINT16[L]
    2186 #define RSCAN0C0CTRLL RSCAN0.C0CTR.UINT8[LL]
    2187 #define RSCAN0C0CTRLH RSCAN0.C0CTR.UINT8[LH]
    2188 #define RSCAN0C0CTRH RSCAN0.C0CTR.UINT16[H]
    2189 #define RSCAN0C0CTRHL RSCAN0.C0CTR.UINT8[HL]
    2190 #define RSCAN0C0CTRHH RSCAN0.C0CTR.UINT8[HH]
    2191 #define RSCAN0C0STS RSCAN0.C0STS.UINT32
    2192 #define RSCAN0C0STSL RSCAN0.C0STS.UINT16[L]
    2193 #define RSCAN0C0STSLL RSCAN0.C0STS.UINT8[LL]
    2194 #define RSCAN0C0STSLH RSCAN0.C0STS.UINT8[LH]
    2195 #define RSCAN0C0STSH RSCAN0.C0STS.UINT16[H]
    2196 #define RSCAN0C0STSHL RSCAN0.C0STS.UINT8[HL]
    2197 #define RSCAN0C0STSHH RSCAN0.C0STS.UINT8[HH]
    2198 #define RSCAN0C0ERFL RSCAN0.C0ERFL.UINT32
    2199 #define RSCAN0C0ERFLL RSCAN0.C0ERFL.UINT16[L]
    2200 #define RSCAN0C0ERFLLL RSCAN0.C0ERFL.UINT8[LL]
    2201 #define RSCAN0C0ERFLLH RSCAN0.C0ERFL.UINT8[LH]
    2202 #define RSCAN0C0ERFLH RSCAN0.C0ERFL.UINT16[H]
    2203 #define RSCAN0C0ERFLHL RSCAN0.C0ERFL.UINT8[HL]
    2204 #define RSCAN0C0ERFLHH RSCAN0.C0ERFL.UINT8[HH]
    2205 #define RSCAN0C1CFG RSCAN0.C1CFG.UINT32
    2206 #define RSCAN0C1CFGL RSCAN0.C1CFG.UINT16[L]
    2207 #define RSCAN0C1CFGLL RSCAN0.C1CFG.UINT8[LL]
    2208 #define RSCAN0C1CFGLH RSCAN0.C1CFG.UINT8[LH]
    2209 #define RSCAN0C1CFGH RSCAN0.C1CFG.UINT16[H]
    2210 #define RSCAN0C1CFGHL RSCAN0.C1CFG.UINT8[HL]
    2211 #define RSCAN0C1CFGHH RSCAN0.C1CFG.UINT8[HH]
    2212 #define RSCAN0C1CTR RSCAN0.C1CTR.UINT32
    2213 #define RSCAN0C1CTRL RSCAN0.C1CTR.UINT16[L]
    2214 #define RSCAN0C1CTRLL RSCAN0.C1CTR.UINT8[LL]
    2215 #define RSCAN0C1CTRLH RSCAN0.C1CTR.UINT8[LH]
    2216 #define RSCAN0C1CTRH RSCAN0.C1CTR.UINT16[H]
    2217 #define RSCAN0C1CTRHL RSCAN0.C1CTR.UINT8[HL]
    2218 #define RSCAN0C1CTRHH RSCAN0.C1CTR.UINT8[HH]
    2219 #define RSCAN0C1STS RSCAN0.C1STS.UINT32
    2220 #define RSCAN0C1STSL RSCAN0.C1STS.UINT16[L]
    2221 #define RSCAN0C1STSLL RSCAN0.C1STS.UINT8[LL]
    2222 #define RSCAN0C1STSLH RSCAN0.C1STS.UINT8[LH]
    2223 #define RSCAN0C1STSH RSCAN0.C1STS.UINT16[H]
    2224 #define RSCAN0C1STSHL RSCAN0.C1STS.UINT8[HL]
    2225 #define RSCAN0C1STSHH RSCAN0.C1STS.UINT8[HH]
    2226 #define RSCAN0C1ERFL RSCAN0.C1ERFL.UINT32
    2227 #define RSCAN0C1ERFLL RSCAN0.C1ERFL.UINT16[L]
    2228 #define RSCAN0C1ERFLLL RSCAN0.C1ERFL.UINT8[LL]
    2229 #define RSCAN0C1ERFLLH RSCAN0.C1ERFL.UINT8[LH]
    2230 #define RSCAN0C1ERFLH RSCAN0.C1ERFL.UINT16[H]
    2231 #define RSCAN0C1ERFLHL RSCAN0.C1ERFL.UINT8[HL]
    2232 #define RSCAN0C1ERFLHH RSCAN0.C1ERFL.UINT8[HH]
    2233 #define RSCAN0C2CFG RSCAN0.C2CFG.UINT32
    2234 #define RSCAN0C2CFGL RSCAN0.C2CFG.UINT16[L]
    2235 #define RSCAN0C2CFGLL RSCAN0.C2CFG.UINT8[LL]
    2236 #define RSCAN0C2CFGLH RSCAN0.C2CFG.UINT8[LH]
    2237 #define RSCAN0C2CFGH RSCAN0.C2CFG.UINT16[H]
    2238 #define RSCAN0C2CFGHL RSCAN0.C2CFG.UINT8[HL]
    2239 #define RSCAN0C2CFGHH RSCAN0.C2CFG.UINT8[HH]
    2240 #define RSCAN0C2CTR RSCAN0.C2CTR.UINT32
    2241 #define RSCAN0C2CTRL RSCAN0.C2CTR.UINT16[L]
    2242 #define RSCAN0C2CTRLL RSCAN0.C2CTR.UINT8[LL]
    2243 #define RSCAN0C2CTRLH RSCAN0.C2CTR.UINT8[LH]
    2244 #define RSCAN0C2CTRH RSCAN0.C2CTR.UINT16[H]
    2245 #define RSCAN0C2CTRHL RSCAN0.C2CTR.UINT8[HL]
    2246 #define RSCAN0C2CTRHH RSCAN0.C2CTR.UINT8[HH]
    2247 #define RSCAN0C2STS RSCAN0.C2STS.UINT32
    2248 #define RSCAN0C2STSL RSCAN0.C2STS.UINT16[L]
    2249 #define RSCAN0C2STSLL RSCAN0.C2STS.UINT8[LL]
    2250 #define RSCAN0C2STSLH RSCAN0.C2STS.UINT8[LH]
    2251 #define RSCAN0C2STSH RSCAN0.C2STS.UINT16[H]
    2252 #define RSCAN0C2STSHL RSCAN0.C2STS.UINT8[HL]
    2253 #define RSCAN0C2STSHH RSCAN0.C2STS.UINT8[HH]
    2254 #define RSCAN0C2ERFL RSCAN0.C2ERFL.UINT32
    2255 #define RSCAN0C2ERFLL RSCAN0.C2ERFL.UINT16[L]
    2256 #define RSCAN0C2ERFLLL RSCAN0.C2ERFL.UINT8[LL]
    2257 #define RSCAN0C2ERFLLH RSCAN0.C2ERFL.UINT8[LH]
    2258 #define RSCAN0C2ERFLH RSCAN0.C2ERFL.UINT16[H]
    2259 #define RSCAN0C2ERFLHL RSCAN0.C2ERFL.UINT8[HL]
    2260 #define RSCAN0C2ERFLHH RSCAN0.C2ERFL.UINT8[HH]
    2261 #define RSCAN0C3CFG RSCAN0.C3CFG.UINT32
    2262 #define RSCAN0C3CFGL RSCAN0.C3CFG.UINT16[L]
    2263 #define RSCAN0C3CFGLL RSCAN0.C3CFG.UINT8[LL]
    2264 #define RSCAN0C3CFGLH RSCAN0.C3CFG.UINT8[LH]
    2265 #define RSCAN0C3CFGH RSCAN0.C3CFG.UINT16[H]
    2266 #define RSCAN0C3CFGHL RSCAN0.C3CFG.UINT8[HL]
    2267 #define RSCAN0C3CFGHH RSCAN0.C3CFG.UINT8[HH]
    2268 #define RSCAN0C3CTR RSCAN0.C3CTR.UINT32
    2269 #define RSCAN0C3CTRL RSCAN0.C3CTR.UINT16[L]
    2270 #define RSCAN0C3CTRLL RSCAN0.C3CTR.UINT8[LL]
    2271 #define RSCAN0C3CTRLH RSCAN0.C3CTR.UINT8[LH]
    2272 #define RSCAN0C3CTRH RSCAN0.C3CTR.UINT16[H]
    2273 #define RSCAN0C3CTRHL RSCAN0.C3CTR.UINT8[HL]
    2274 #define RSCAN0C3CTRHH RSCAN0.C3CTR.UINT8[HH]
    2275 #define RSCAN0C3STS RSCAN0.C3STS.UINT32
    2276 #define RSCAN0C3STSL RSCAN0.C3STS.UINT16[L]
    2277 #define RSCAN0C3STSLL RSCAN0.C3STS.UINT8[LL]
    2278 #define RSCAN0C3STSLH RSCAN0.C3STS.UINT8[LH]
    2279 #define RSCAN0C3STSH RSCAN0.C3STS.UINT16[H]
    2280 #define RSCAN0C3STSHL RSCAN0.C3STS.UINT8[HL]
    2281 #define RSCAN0C3STSHH RSCAN0.C3STS.UINT8[HH]
    2282 #define RSCAN0C3ERFL RSCAN0.C3ERFL.UINT32
    2283 #define RSCAN0C3ERFLL RSCAN0.C3ERFL.UINT16[L]
    2284 #define RSCAN0C3ERFLLL RSCAN0.C3ERFL.UINT8[LL]
    2285 #define RSCAN0C3ERFLLH RSCAN0.C3ERFL.UINT8[LH]
    2286 #define RSCAN0C3ERFLH RSCAN0.C3ERFL.UINT16[H]
    2287 #define RSCAN0C3ERFLHL RSCAN0.C3ERFL.UINT8[HL]
    2288 #define RSCAN0C3ERFLHH RSCAN0.C3ERFL.UINT8[HH]
    2289 #define RSCAN0C4CFG RSCAN0.C4CFG.UINT32
    2290 #define RSCAN0C4CFGL RSCAN0.C4CFG.UINT16[L]
    2291 #define RSCAN0C4CFGLL RSCAN0.C4CFG.UINT8[LL]
    2292 #define RSCAN0C4CFGLH RSCAN0.C4CFG.UINT8[LH]
    2293 #define RSCAN0C4CFGH RSCAN0.C4CFG.UINT16[H]
    2294 #define RSCAN0C4CFGHL RSCAN0.C4CFG.UINT8[HL]
    2295 #define RSCAN0C4CFGHH RSCAN0.C4CFG.UINT8[HH]
    2296 #define RSCAN0C4CTR RSCAN0.C4CTR.UINT32
    2297 #define RSCAN0C4CTRL RSCAN0.C4CTR.UINT16[L]
    2298 #define RSCAN0C4CTRLL RSCAN0.C4CTR.UINT8[LL]
    2299 #define RSCAN0C4CTRLH RSCAN0.C4CTR.UINT8[LH]
    2300 #define RSCAN0C4CTRH RSCAN0.C4CTR.UINT16[H]
    2301 #define RSCAN0C4CTRHL RSCAN0.C4CTR.UINT8[HL]
    2302 #define RSCAN0C4CTRHH RSCAN0.C4CTR.UINT8[HH]
    2303 #define RSCAN0C4STS RSCAN0.C4STS.UINT32
    2304 #define RSCAN0C4STSL RSCAN0.C4STS.UINT16[L]
    2305 #define RSCAN0C4STSLL RSCAN0.C4STS.UINT8[LL]
    2306 #define RSCAN0C4STSLH RSCAN0.C4STS.UINT8[LH]
    2307 #define RSCAN0C4STSH RSCAN0.C4STS.UINT16[H]
    2308 #define RSCAN0C4STSHL RSCAN0.C4STS.UINT8[HL]
    2309 #define RSCAN0C4STSHH RSCAN0.C4STS.UINT8[HH]
    2310 #define RSCAN0C4ERFL RSCAN0.C4ERFL.UINT32
    2311 #define RSCAN0C4ERFLL RSCAN0.C4ERFL.UINT16[L]
    2312 #define RSCAN0C4ERFLLL RSCAN0.C4ERFL.UINT8[LL]
    2313 #define RSCAN0C4ERFLLH RSCAN0.C4ERFL.UINT8[LH]
    2314 #define RSCAN0C4ERFLH RSCAN0.C4ERFL.UINT16[H]
    2315 #define RSCAN0C4ERFLHL RSCAN0.C4ERFL.UINT8[HL]
    2316 #define RSCAN0C4ERFLHH RSCAN0.C4ERFL.UINT8[HH]
    2317 #define RSCAN0GCFG RSCAN0.GCFG.UINT32
    2318 #define RSCAN0GCFGL RSCAN0.GCFG.UINT16[L]
    2319 #define RSCAN0GCFGLL RSCAN0.GCFG.UINT8[LL]
    2320 #define RSCAN0GCFGLH RSCAN0.GCFG.UINT8[LH]
    2321 #define RSCAN0GCFGH RSCAN0.GCFG.UINT16[H]
    2322 #define RSCAN0GCFGHL RSCAN0.GCFG.UINT8[HL]
    2323 #define RSCAN0GCFGHH RSCAN0.GCFG.UINT8[HH]
    2324 #define RSCAN0GCTR RSCAN0.GCTR.UINT32
    2325 #define RSCAN0GCTRL RSCAN0.GCTR.UINT16[L]
    2326 #define RSCAN0GCTRLL RSCAN0.GCTR.UINT8[LL]
    2327 #define RSCAN0GCTRLH RSCAN0.GCTR.UINT8[LH]
    2328 #define RSCAN0GCTRH RSCAN0.GCTR.UINT16[H]
    2329 #define RSCAN0GCTRHL RSCAN0.GCTR.UINT8[HL]
    2330 #define RSCAN0GCTRHH RSCAN0.GCTR.UINT8[HH]
    2331 #define RSCAN0GSTS RSCAN0.GSTS.UINT32
    2332 #define RSCAN0GSTSL RSCAN0.GSTS.UINT16[L]
    2333 #define RSCAN0GSTSLL RSCAN0.GSTS.UINT8[LL]
    2334 #define RSCAN0GSTSLH RSCAN0.GSTS.UINT8[LH]
    2335 #define RSCAN0GSTSH RSCAN0.GSTS.UINT16[H]
    2336 #define RSCAN0GSTSHL RSCAN0.GSTS.UINT8[HL]
    2337 #define RSCAN0GSTSHH RSCAN0.GSTS.UINT8[HH]
    2338 #define RSCAN0GERFL RSCAN0.GERFL.UINT32
    2339 #define RSCAN0GERFLL RSCAN0.GERFL.UINT16[L]
    2340 #define RSCAN0GERFLLL RSCAN0.GERFL.UINT8[LL]
    2341 #define RSCAN0GERFLLH RSCAN0.GERFL.UINT8[LH]
    2342 #define RSCAN0GERFLH RSCAN0.GERFL.UINT16[H]
    2343 #define RSCAN0GERFLHL RSCAN0.GERFL.UINT8[HL]
    2344 #define RSCAN0GERFLHH RSCAN0.GERFL.UINT8[HH]
    2345 #define RSCAN0GTSC RSCAN0.GTSC.UINT32
    2346 #define RSCAN0GTSCL RSCAN0.GTSC.UINT16[L]
    2347 #define RSCAN0GTSCH RSCAN0.GTSC.UINT16[H]
    2348 #define RSCAN0GAFLECTR RSCAN0.GAFLECTR.UINT32
    2349 #define RSCAN0GAFLECTRL RSCAN0.GAFLECTR.UINT16[L]
    2350 #define RSCAN0GAFLECTRLL RSCAN0.GAFLECTR.UINT8[LL]
    2351 #define RSCAN0GAFLECTRLH RSCAN0.GAFLECTR.UINT8[LH]
    2352 #define RSCAN0GAFLECTRH RSCAN0.GAFLECTR.UINT16[H]
    2353 #define RSCAN0GAFLECTRHL RSCAN0.GAFLECTR.UINT8[HL]
    2354 #define RSCAN0GAFLECTRHH RSCAN0.GAFLECTR.UINT8[HH]
    2355 #define RSCAN0GAFLCFG0 RSCAN0.GAFLCFG0.UINT32
    2356 #define RSCAN0GAFLCFG0L RSCAN0.GAFLCFG0.UINT16[L]
    2357 #define RSCAN0GAFLCFG0LL RSCAN0.GAFLCFG0.UINT8[LL]
    2358 #define RSCAN0GAFLCFG0LH RSCAN0.GAFLCFG0.UINT8[LH]
    2359 #define RSCAN0GAFLCFG0H RSCAN0.GAFLCFG0.UINT16[H]
    2360 #define RSCAN0GAFLCFG0HL RSCAN0.GAFLCFG0.UINT8[HL]
    2361 #define RSCAN0GAFLCFG0HH RSCAN0.GAFLCFG0.UINT8[HH]
    2362 #define RSCAN0GAFLCFG1 RSCAN0.GAFLCFG1.UINT32
    2363 #define RSCAN0GAFLCFG1L RSCAN0.GAFLCFG1.UINT16[L]
    2364 #define RSCAN0GAFLCFG1LL RSCAN0.GAFLCFG1.UINT8[LL]
    2365 #define RSCAN0GAFLCFG1LH RSCAN0.GAFLCFG1.UINT8[LH]
    2366 #define RSCAN0GAFLCFG1H RSCAN0.GAFLCFG1.UINT16[H]
    2367 #define RSCAN0GAFLCFG1HL RSCAN0.GAFLCFG1.UINT8[HL]
    2368 #define RSCAN0GAFLCFG1HH RSCAN0.GAFLCFG1.UINT8[HH]
    2369 #define RSCAN0RMNB RSCAN0.RMNB.UINT32
    2370 #define RSCAN0RMNBL RSCAN0.RMNB.UINT16[L]
    2371 #define RSCAN0RMNBLL RSCAN0.RMNB.UINT8[LL]
    2372 #define RSCAN0RMNBLH RSCAN0.RMNB.UINT8[LH]
    2373 #define RSCAN0RMNBH RSCAN0.RMNB.UINT16[H]
    2374 #define RSCAN0RMNBHL RSCAN0.RMNB.UINT8[HL]
    2375 #define RSCAN0RMNBHH RSCAN0.RMNB.UINT8[HH]
    2376 #define RSCAN0RMND0 RSCAN0.RMND0.UINT32
    2377 #define RSCAN0RMND0L RSCAN0.RMND0.UINT16[L]
    2378 #define RSCAN0RMND0LL RSCAN0.RMND0.UINT8[LL]
    2379 #define RSCAN0RMND0LH RSCAN0.RMND0.UINT8[LH]
    2380 #define RSCAN0RMND0H RSCAN0.RMND0.UINT16[H]
    2381 #define RSCAN0RMND0HL RSCAN0.RMND0.UINT8[HL]
    2382 #define RSCAN0RMND0HH RSCAN0.RMND0.UINT8[HH]
    2383 #define RSCAN0RMND1 RSCAN0.RMND1.UINT32
    2384 #define RSCAN0RMND1L RSCAN0.RMND1.UINT16[L]
    2385 #define RSCAN0RMND1LL RSCAN0.RMND1.UINT8[LL]
    2386 #define RSCAN0RMND1LH RSCAN0.RMND1.UINT8[LH]
    2387 #define RSCAN0RMND1H RSCAN0.RMND1.UINT16[H]
    2388 #define RSCAN0RMND1HL RSCAN0.RMND1.UINT8[HL]
    2389 #define RSCAN0RMND1HH RSCAN0.RMND1.UINT8[HH]
    2390 #define RSCAN0RMND2 RSCAN0.RMND2.UINT32
    2391 #define RSCAN0RMND2L RSCAN0.RMND2.UINT16[L]
    2392 #define RSCAN0RMND2LL RSCAN0.RMND2.UINT8[LL]
    2393 #define RSCAN0RMND2LH RSCAN0.RMND2.UINT8[LH]
    2394 #define RSCAN0RMND2H RSCAN0.RMND2.UINT16[H]
    2395 #define RSCAN0RMND2HL RSCAN0.RMND2.UINT8[HL]
    2396 #define RSCAN0RMND2HH RSCAN0.RMND2.UINT8[HH]
    2397 #define RSCAN0RFCC0 RSCAN0.RFCC0.UINT32
    2398 #define RSCAN0RFCC0L RSCAN0.RFCC0.UINT16[L]
    2399 #define RSCAN0RFCC0LL RSCAN0.RFCC0.UINT8[LL]
    2400 #define RSCAN0RFCC0LH RSCAN0.RFCC0.UINT8[LH]
    2401 #define RSCAN0RFCC0H RSCAN0.RFCC0.UINT16[H]
    2402 #define RSCAN0RFCC0HL RSCAN0.RFCC0.UINT8[HL]
    2403 #define RSCAN0RFCC0HH RSCAN0.RFCC0.UINT8[HH]
    2404 #define RSCAN0RFCC1 RSCAN0.RFCC1.UINT32
    2405 #define RSCAN0RFCC1L RSCAN0.RFCC1.UINT16[L]
    2406 #define RSCAN0RFCC1LL RSCAN0.RFCC1.UINT8[LL]
    2407 #define RSCAN0RFCC1LH RSCAN0.RFCC1.UINT8[LH]
    2408 #define RSCAN0RFCC1H RSCAN0.RFCC1.UINT16[H]
    2409 #define RSCAN0RFCC1HL RSCAN0.RFCC1.UINT8[HL]
    2410 #define RSCAN0RFCC1HH RSCAN0.RFCC1.UINT8[HH]
    2411 #define RSCAN0RFCC2 RSCAN0.RFCC2.UINT32
    2412 #define RSCAN0RFCC2L RSCAN0.RFCC2.UINT16[L]
    2413 #define RSCAN0RFCC2LL RSCAN0.RFCC2.UINT8[LL]
    2414 #define RSCAN0RFCC2LH RSCAN0.RFCC2.UINT8[LH]
    2415 #define RSCAN0RFCC2H RSCAN0.RFCC2.UINT16[H]
    2416 #define RSCAN0RFCC2HL RSCAN0.RFCC2.UINT8[HL]
    2417 #define RSCAN0RFCC2HH RSCAN0.RFCC2.UINT8[HH]
    2418 #define RSCAN0RFCC3 RSCAN0.RFCC3.UINT32
    2419 #define RSCAN0RFCC3L RSCAN0.RFCC3.UINT16[L]
    2420 #define RSCAN0RFCC3LL RSCAN0.RFCC3.UINT8[LL]
    2421 #define RSCAN0RFCC3LH RSCAN0.RFCC3.UINT8[LH]
    2422 #define RSCAN0RFCC3H RSCAN0.RFCC3.UINT16[H]
    2423 #define RSCAN0RFCC3HL RSCAN0.RFCC3.UINT8[HL]
    2424 #define RSCAN0RFCC3HH RSCAN0.RFCC3.UINT8[HH]
    2425 #define RSCAN0RFCC4 RSCAN0.RFCC4.UINT32
    2426 #define RSCAN0RFCC4L RSCAN0.RFCC4.UINT16[L]
    2427 #define RSCAN0RFCC4LL RSCAN0.RFCC4.UINT8[LL]
    2428 #define RSCAN0RFCC4LH RSCAN0.RFCC4.UINT8[LH]
    2429 #define RSCAN0RFCC4H RSCAN0.RFCC4.UINT16[H]
    2430 #define RSCAN0RFCC4HL RSCAN0.RFCC4.UINT8[HL]
    2431 #define RSCAN0RFCC4HH RSCAN0.RFCC4.UINT8[HH]
    2432 #define RSCAN0RFCC5 RSCAN0.RFCC5.UINT32
    2433 #define RSCAN0RFCC5L RSCAN0.RFCC5.UINT16[L]
    2434 #define RSCAN0RFCC5LL RSCAN0.RFCC5.UINT8[LL]
    2435 #define RSCAN0RFCC5LH RSCAN0.RFCC5.UINT8[LH]
    2436 #define RSCAN0RFCC5H RSCAN0.RFCC5.UINT16[H]
    2437 #define RSCAN0RFCC5HL RSCAN0.RFCC5.UINT8[HL]
    2438 #define RSCAN0RFCC5HH RSCAN0.RFCC5.UINT8[HH]
    2439 #define RSCAN0RFCC6 RSCAN0.RFCC6.UINT32
    2440 #define RSCAN0RFCC6L RSCAN0.RFCC6.UINT16[L]
    2441 #define RSCAN0RFCC6LL RSCAN0.RFCC6.UINT8[LL]
    2442 #define RSCAN0RFCC6LH RSCAN0.RFCC6.UINT8[LH]
    2443 #define RSCAN0RFCC6H RSCAN0.RFCC6.UINT16[H]
    2444 #define RSCAN0RFCC6HL RSCAN0.RFCC6.UINT8[HL]
    2445 #define RSCAN0RFCC6HH RSCAN0.RFCC6.UINT8[HH]
    2446 #define RSCAN0RFCC7 RSCAN0.RFCC7.UINT32
    2447 #define RSCAN0RFCC7L RSCAN0.RFCC7.UINT16[L]
    2448 #define RSCAN0RFCC7LL RSCAN0.RFCC7.UINT8[LL]
    2449 #define RSCAN0RFCC7LH RSCAN0.RFCC7.UINT8[LH]
    2450 #define RSCAN0RFCC7H RSCAN0.RFCC7.UINT16[H]
    2451 #define RSCAN0RFCC7HL RSCAN0.RFCC7.UINT8[HL]
    2452 #define RSCAN0RFCC7HH RSCAN0.RFCC7.UINT8[HH]
    2453 #define RSCAN0RFSTS0 RSCAN0.RFSTS0.UINT32
    2454 #define RSCAN0RFSTS0L RSCAN0.RFSTS0.UINT16[L]
    2455 #define RSCAN0RFSTS0LL RSCAN0.RFSTS0.UINT8[LL]
    2456 #define RSCAN0RFSTS0LH RSCAN0.RFSTS0.UINT8[LH]
    2457 #define RSCAN0RFSTS0H RSCAN0.RFSTS0.UINT16[H]
    2458 #define RSCAN0RFSTS0HL RSCAN0.RFSTS0.UINT8[HL]
    2459 #define RSCAN0RFSTS0HH RSCAN0.RFSTS0.UINT8[HH]
    2460 #define RSCAN0RFSTS1 RSCAN0.RFSTS1.UINT32
    2461 #define RSCAN0RFSTS1L RSCAN0.RFSTS1.UINT16[L]
    2462 #define RSCAN0RFSTS1LL RSCAN0.RFSTS1.UINT8[LL]
    2463 #define RSCAN0RFSTS1LH RSCAN0.RFSTS1.UINT8[LH]
    2464 #define RSCAN0RFSTS1H RSCAN0.RFSTS1.UINT16[H]
    2465 #define RSCAN0RFSTS1HL RSCAN0.RFSTS1.UINT8[HL]
    2466 #define RSCAN0RFSTS1HH RSCAN0.RFSTS1.UINT8[HH]
    2467 #define RSCAN0RFSTS2 RSCAN0.RFSTS2.UINT32
    2468 #define RSCAN0RFSTS2L RSCAN0.RFSTS2.UINT16[L]
    2469 #define RSCAN0RFSTS2LL RSCAN0.RFSTS2.UINT8[LL]
    2470 #define RSCAN0RFSTS2LH RSCAN0.RFSTS2.UINT8[LH]
    2471 #define RSCAN0RFSTS2H RSCAN0.RFSTS2.UINT16[H]
    2472 #define RSCAN0RFSTS2HL RSCAN0.RFSTS2.UINT8[HL]
    2473 #define RSCAN0RFSTS2HH RSCAN0.RFSTS2.UINT8[HH]
    2474 #define RSCAN0RFSTS3 RSCAN0.RFSTS3.UINT32
    2475 #define RSCAN0RFSTS3L RSCAN0.RFSTS3.UINT16[L]
    2476 #define RSCAN0RFSTS3LL RSCAN0.RFSTS3.UINT8[LL]
    2477 #define RSCAN0RFSTS3LH RSCAN0.RFSTS3.UINT8[LH]
    2478 #define RSCAN0RFSTS3H RSCAN0.RFSTS3.UINT16[H]
    2479 #define RSCAN0RFSTS3HL RSCAN0.RFSTS3.UINT8[HL]
    2480 #define RSCAN0RFSTS3HH RSCAN0.RFSTS3.UINT8[HH]
    2481 #define RSCAN0RFSTS4 RSCAN0.RFSTS4.UINT32
    2482 #define RSCAN0RFSTS4L RSCAN0.RFSTS4.UINT16[L]
    2483 #define RSCAN0RFSTS4LL RSCAN0.RFSTS4.UINT8[LL]
    2484 #define RSCAN0RFSTS4LH RSCAN0.RFSTS4.UINT8[LH]
    2485 #define RSCAN0RFSTS4H RSCAN0.RFSTS4.UINT16[H]
    2486 #define RSCAN0RFSTS4HL RSCAN0.RFSTS4.UINT8[HL]
    2487 #define RSCAN0RFSTS4HH RSCAN0.RFSTS4.UINT8[HH]
    2488 #define RSCAN0RFSTS5 RSCAN0.RFSTS5.UINT32
    2489 #define RSCAN0RFSTS5L RSCAN0.RFSTS5.UINT16[L]
    2490 #define RSCAN0RFSTS5LL RSCAN0.RFSTS5.UINT8[LL]
    2491 #define RSCAN0RFSTS5LH RSCAN0.RFSTS5.UINT8[LH]
    2492 #define RSCAN0RFSTS5H RSCAN0.RFSTS5.UINT16[H]
    2493 #define RSCAN0RFSTS5HL RSCAN0.RFSTS5.UINT8[HL]
    2494 #define RSCAN0RFSTS5HH RSCAN0.RFSTS5.UINT8[HH]
    2495 #define RSCAN0RFSTS6 RSCAN0.RFSTS6.UINT32
    2496 #define RSCAN0RFSTS6L RSCAN0.RFSTS6.UINT16[L]
    2497 #define RSCAN0RFSTS6LL RSCAN0.RFSTS6.UINT8[LL]
    2498 #define RSCAN0RFSTS6LH RSCAN0.RFSTS6.UINT8[LH]
    2499 #define RSCAN0RFSTS6H RSCAN0.RFSTS6.UINT16[H]
    2500 #define RSCAN0RFSTS6HL RSCAN0.RFSTS6.UINT8[HL]
    2501 #define RSCAN0RFSTS6HH RSCAN0.RFSTS6.UINT8[HH]
    2502 #define RSCAN0RFSTS7 RSCAN0.RFSTS7.UINT32
    2503 #define RSCAN0RFSTS7L RSCAN0.RFSTS7.UINT16[L]
    2504 #define RSCAN0RFSTS7LL RSCAN0.RFSTS7.UINT8[LL]
    2505 #define RSCAN0RFSTS7LH RSCAN0.RFSTS7.UINT8[LH]
    2506 #define RSCAN0RFSTS7H RSCAN0.RFSTS7.UINT16[H]
    2507 #define RSCAN0RFSTS7HL RSCAN0.RFSTS7.UINT8[HL]
    2508 #define RSCAN0RFSTS7HH RSCAN0.RFSTS7.UINT8[HH]
    2509 #define RSCAN0RFPCTR0 RSCAN0.RFPCTR0.UINT32
    2510 #define RSCAN0RFPCTR0L RSCAN0.RFPCTR0.UINT16[L]
    2511 #define RSCAN0RFPCTR0LL RSCAN0.RFPCTR0.UINT8[LL]
    2512 #define RSCAN0RFPCTR0LH RSCAN0.RFPCTR0.UINT8[LH]
    2513 #define RSCAN0RFPCTR0H RSCAN0.RFPCTR0.UINT16[H]
    2514 #define RSCAN0RFPCTR0HL RSCAN0.RFPCTR0.UINT8[HL]
    2515 #define RSCAN0RFPCTR0HH RSCAN0.RFPCTR0.UINT8[HH]
    2516 #define RSCAN0RFPCTR1 RSCAN0.RFPCTR1.UINT32
    2517 #define RSCAN0RFPCTR1L RSCAN0.RFPCTR1.UINT16[L]
    2518 #define RSCAN0RFPCTR1LL RSCAN0.RFPCTR1.UINT8[LL]
    2519 #define RSCAN0RFPCTR1LH RSCAN0.RFPCTR1.UINT8[LH]
    2520 #define RSCAN0RFPCTR1H RSCAN0.RFPCTR1.UINT16[H]
    2521 #define RSCAN0RFPCTR1HL RSCAN0.RFPCTR1.UINT8[HL]
    2522 #define RSCAN0RFPCTR1HH RSCAN0.RFPCTR1.UINT8[HH]
    2523 #define RSCAN0RFPCTR2 RSCAN0.RFPCTR2.UINT32
    2524 #define RSCAN0RFPCTR2L RSCAN0.RFPCTR2.UINT16[L]
    2525 #define RSCAN0RFPCTR2LL RSCAN0.RFPCTR2.UINT8[LL]
    2526 #define RSCAN0RFPCTR2LH RSCAN0.RFPCTR2.UINT8[LH]
    2527 #define RSCAN0RFPCTR2H RSCAN0.RFPCTR2.UINT16[H]
    2528 #define RSCAN0RFPCTR2HL RSCAN0.RFPCTR2.UINT8[HL]
    2529 #define RSCAN0RFPCTR2HH RSCAN0.RFPCTR2.UINT8[HH]
    2530 #define RSCAN0RFPCTR3 RSCAN0.RFPCTR3.UINT32
    2531 #define RSCAN0RFPCTR3L RSCAN0.RFPCTR3.UINT16[L]
    2532 #define RSCAN0RFPCTR3LL RSCAN0.RFPCTR3.UINT8[LL]
    2533 #define RSCAN0RFPCTR3LH RSCAN0.RFPCTR3.UINT8[LH]
    2534 #define RSCAN0RFPCTR3H RSCAN0.RFPCTR3.UINT16[H]
    2535 #define RSCAN0RFPCTR3HL RSCAN0.RFPCTR3.UINT8[HL]
    2536 #define RSCAN0RFPCTR3HH RSCAN0.RFPCTR3.UINT8[HH]
    2537 #define RSCAN0RFPCTR4 RSCAN0.RFPCTR4.UINT32
    2538 #define RSCAN0RFPCTR4L RSCAN0.RFPCTR4.UINT16[L]
    2539 #define RSCAN0RFPCTR4LL RSCAN0.RFPCTR4.UINT8[LL]
    2540 #define RSCAN0RFPCTR4LH RSCAN0.RFPCTR4.UINT8[LH]
    2541 #define RSCAN0RFPCTR4H RSCAN0.RFPCTR4.UINT16[H]
    2542 #define RSCAN0RFPCTR4HL RSCAN0.RFPCTR4.UINT8[HL]
    2543 #define RSCAN0RFPCTR4HH RSCAN0.RFPCTR4.UINT8[HH]
    2544 #define RSCAN0RFPCTR5 RSCAN0.RFPCTR5.UINT32
    2545 #define RSCAN0RFPCTR5L RSCAN0.RFPCTR5.UINT16[L]
    2546 #define RSCAN0RFPCTR5LL RSCAN0.RFPCTR5.UINT8[LL]
    2547 #define RSCAN0RFPCTR5LH RSCAN0.RFPCTR5.UINT8[LH]
    2548 #define RSCAN0RFPCTR5H RSCAN0.RFPCTR5.UINT16[H]
    2549 #define RSCAN0RFPCTR5HL RSCAN0.RFPCTR5.UINT8[HL]
    2550 #define RSCAN0RFPCTR5HH RSCAN0.RFPCTR5.UINT8[HH]
    2551 #define RSCAN0RFPCTR6 RSCAN0.RFPCTR6.UINT32
    2552 #define RSCAN0RFPCTR6L RSCAN0.RFPCTR6.UINT16[L]
    2553 #define RSCAN0RFPCTR6LL RSCAN0.RFPCTR6.UINT8[LL]
    2554 #define RSCAN0RFPCTR6LH RSCAN0.RFPCTR6.UINT8[LH]
    2555 #define RSCAN0RFPCTR6H RSCAN0.RFPCTR6.UINT16[H]
    2556 #define RSCAN0RFPCTR6HL RSCAN0.RFPCTR6.UINT8[HL]
    2557 #define RSCAN0RFPCTR6HH RSCAN0.RFPCTR6.UINT8[HH]
    2558 #define RSCAN0RFPCTR7 RSCAN0.RFPCTR7.UINT32
    2559 #define RSCAN0RFPCTR7L RSCAN0.RFPCTR7.UINT16[L]
    2560 #define RSCAN0RFPCTR7LL RSCAN0.RFPCTR7.UINT8[LL]
    2561 #define RSCAN0RFPCTR7LH RSCAN0.RFPCTR7.UINT8[LH]
    2562 #define RSCAN0RFPCTR7H RSCAN0.RFPCTR7.UINT16[H]
    2563 #define RSCAN0RFPCTR7HL RSCAN0.RFPCTR7.UINT8[HL]
    2564 #define RSCAN0RFPCTR7HH RSCAN0.RFPCTR7.UINT8[HH]
    2565 #define RSCAN0CFCC0 RSCAN0.CFCC0.UINT32
    2566 #define RSCAN0CFCC0L RSCAN0.CFCC0.UINT16[L]
    2567 #define RSCAN0CFCC0LL RSCAN0.CFCC0.UINT8[LL]
    2568 #define RSCAN0CFCC0LH RSCAN0.CFCC0.UINT8[LH]
    2569 #define RSCAN0CFCC0H RSCAN0.CFCC0.UINT16[H]
    2570 #define RSCAN0CFCC0HL RSCAN0.CFCC0.UINT8[HL]
    2571 #define RSCAN0CFCC0HH RSCAN0.CFCC0.UINT8[HH]
    2572 #define RSCAN0CFCC1 RSCAN0.CFCC1.UINT32
    2573 #define RSCAN0CFCC1L RSCAN0.CFCC1.UINT16[L]
    2574 #define RSCAN0CFCC1LL RSCAN0.CFCC1.UINT8[LL]
    2575 #define RSCAN0CFCC1LH RSCAN0.CFCC1.UINT8[LH]
    2576 #define RSCAN0CFCC1H RSCAN0.CFCC1.UINT16[H]
    2577 #define RSCAN0CFCC1HL RSCAN0.CFCC1.UINT8[HL]
    2578 #define RSCAN0CFCC1HH RSCAN0.CFCC1.UINT8[HH]
    2579 #define RSCAN0CFCC2 RSCAN0.CFCC2.UINT32
    2580 #define RSCAN0CFCC2L RSCAN0.CFCC2.UINT16[L]
    2581 #define RSCAN0CFCC2LL RSCAN0.CFCC2.UINT8[LL]
    2582 #define RSCAN0CFCC2LH RSCAN0.CFCC2.UINT8[LH]
    2583 #define RSCAN0CFCC2H RSCAN0.CFCC2.UINT16[H]
    2584 #define RSCAN0CFCC2HL RSCAN0.CFCC2.UINT8[HL]
    2585 #define RSCAN0CFCC2HH RSCAN0.CFCC2.UINT8[HH]
    2586 #define RSCAN0CFCC3 RSCAN0.CFCC3.UINT32
    2587 #define RSCAN0CFCC3L RSCAN0.CFCC3.UINT16[L]
    2588 #define RSCAN0CFCC3LL RSCAN0.CFCC3.UINT8[LL]
    2589 #define RSCAN0CFCC3LH RSCAN0.CFCC3.UINT8[LH]
    2590 #define RSCAN0CFCC3H RSCAN0.CFCC3.UINT16[H]
    2591 #define RSCAN0CFCC3HL RSCAN0.CFCC3.UINT8[HL]
    2592 #define RSCAN0CFCC3HH RSCAN0.CFCC3.UINT8[HH]
    2593 #define RSCAN0CFCC4 RSCAN0.CFCC4.UINT32
    2594 #define RSCAN0CFCC4L RSCAN0.CFCC4.UINT16[L]
    2595 #define RSCAN0CFCC4LL RSCAN0.CFCC4.UINT8[LL]
    2596 #define RSCAN0CFCC4LH RSCAN0.CFCC4.UINT8[LH]
    2597 #define RSCAN0CFCC4H RSCAN0.CFCC4.UINT16[H]
    2598 #define RSCAN0CFCC4HL RSCAN0.CFCC4.UINT8[HL]
    2599 #define RSCAN0CFCC4HH RSCAN0.CFCC4.UINT8[HH]
    2600 #define RSCAN0CFCC5 RSCAN0.CFCC5.UINT32
    2601 #define RSCAN0CFCC5L RSCAN0.CFCC5.UINT16[L]
    2602 #define RSCAN0CFCC5LL RSCAN0.CFCC5.UINT8[LL]
    2603 #define RSCAN0CFCC5LH RSCAN0.CFCC5.UINT8[LH]
    2604 #define RSCAN0CFCC5H RSCAN0.CFCC5.UINT16[H]
    2605 #define RSCAN0CFCC5HL RSCAN0.CFCC5.UINT8[HL]
    2606 #define RSCAN0CFCC5HH RSCAN0.CFCC5.UINT8[HH]
    2607 #define RSCAN0CFCC6 RSCAN0.CFCC6.UINT32
    2608 #define RSCAN0CFCC6L RSCAN0.CFCC6.UINT16[L]
    2609 #define RSCAN0CFCC6LL RSCAN0.CFCC6.UINT8[LL]
    2610 #define RSCAN0CFCC6LH RSCAN0.CFCC6.UINT8[LH]
    2611 #define RSCAN0CFCC6H RSCAN0.CFCC6.UINT16[H]
    2612 #define RSCAN0CFCC6HL RSCAN0.CFCC6.UINT8[HL]
    2613 #define RSCAN0CFCC6HH RSCAN0.CFCC6.UINT8[HH]
    2614 #define RSCAN0CFCC7 RSCAN0.CFCC7.UINT32
    2615 #define RSCAN0CFCC7L RSCAN0.CFCC7.UINT16[L]
    2616 #define RSCAN0CFCC7LL RSCAN0.CFCC7.UINT8[LL]
    2617 #define RSCAN0CFCC7LH RSCAN0.CFCC7.UINT8[LH]
    2618 #define RSCAN0CFCC7H RSCAN0.CFCC7.UINT16[H]
    2619 #define RSCAN0CFCC7HL RSCAN0.CFCC7.UINT8[HL]
    2620 #define RSCAN0CFCC7HH RSCAN0.CFCC7.UINT8[HH]
    2621 #define RSCAN0CFCC8 RSCAN0.CFCC8.UINT32
    2622 #define RSCAN0CFCC8L RSCAN0.CFCC8.UINT16[L]
    2623 #define RSCAN0CFCC8LL RSCAN0.CFCC8.UINT8[LL]
    2624 #define RSCAN0CFCC8LH RSCAN0.CFCC8.UINT8[LH]
    2625 #define RSCAN0CFCC8H RSCAN0.CFCC8.UINT16[H]
    2626 #define RSCAN0CFCC8HL RSCAN0.CFCC8.UINT8[HL]
    2627 #define RSCAN0CFCC8HH RSCAN0.CFCC8.UINT8[HH]
    2628 #define RSCAN0CFCC9 RSCAN0.CFCC9.UINT32
    2629 #define RSCAN0CFCC9L RSCAN0.CFCC9.UINT16[L]
    2630 #define RSCAN0CFCC9LL RSCAN0.CFCC9.UINT8[LL]
    2631 #define RSCAN0CFCC9LH RSCAN0.CFCC9.UINT8[LH]
    2632 #define RSCAN0CFCC9H RSCAN0.CFCC9.UINT16[H]
    2633 #define RSCAN0CFCC9HL RSCAN0.CFCC9.UINT8[HL]
    2634 #define RSCAN0CFCC9HH RSCAN0.CFCC9.UINT8[HH]
    2635 #define RSCAN0CFCC10 RSCAN0.CFCC10.UINT32
    2636 #define RSCAN0CFCC10L RSCAN0.CFCC10.UINT16[L]
    2637 #define RSCAN0CFCC10LL RSCAN0.CFCC10.UINT8[LL]
    2638 #define RSCAN0CFCC10LH RSCAN0.CFCC10.UINT8[LH]
    2639 #define RSCAN0CFCC10H RSCAN0.CFCC10.UINT16[H]
    2640 #define RSCAN0CFCC10HL RSCAN0.CFCC10.UINT8[HL]
    2641 #define RSCAN0CFCC10HH RSCAN0.CFCC10.UINT8[HH]
    2642 #define RSCAN0CFCC11 RSCAN0.CFCC11.UINT32
    2643 #define RSCAN0CFCC11L RSCAN0.CFCC11.UINT16[L]
    2644 #define RSCAN0CFCC11LL RSCAN0.CFCC11.UINT8[LL]
    2645 #define RSCAN0CFCC11LH RSCAN0.CFCC11.UINT8[LH]
    2646 #define RSCAN0CFCC11H RSCAN0.CFCC11.UINT16[H]
    2647 #define RSCAN0CFCC11HL RSCAN0.CFCC11.UINT8[HL]
    2648 #define RSCAN0CFCC11HH RSCAN0.CFCC11.UINT8[HH]
    2649 #define RSCAN0CFCC12 RSCAN0.CFCC12.UINT32
    2650 #define RSCAN0CFCC12L RSCAN0.CFCC12.UINT16[L]
    2651 #define RSCAN0CFCC12LL RSCAN0.CFCC12.UINT8[LL]
    2652 #define RSCAN0CFCC12LH RSCAN0.CFCC12.UINT8[LH]
    2653 #define RSCAN0CFCC12H RSCAN0.CFCC12.UINT16[H]
    2654 #define RSCAN0CFCC12HL RSCAN0.CFCC12.UINT8[HL]
    2655 #define RSCAN0CFCC12HH RSCAN0.CFCC12.UINT8[HH]
    2656 #define RSCAN0CFCC13 RSCAN0.CFCC13.UINT32
    2657 #define RSCAN0CFCC13L RSCAN0.CFCC13.UINT16[L]
    2658 #define RSCAN0CFCC13LL RSCAN0.CFCC13.UINT8[LL]
    2659 #define RSCAN0CFCC13LH RSCAN0.CFCC13.UINT8[LH]
    2660 #define RSCAN0CFCC13H RSCAN0.CFCC13.UINT16[H]
    2661 #define RSCAN0CFCC13HL RSCAN0.CFCC13.UINT8[HL]
    2662 #define RSCAN0CFCC13HH RSCAN0.CFCC13.UINT8[HH]
    2663 #define RSCAN0CFCC14 RSCAN0.CFCC14.UINT32
    2664 #define RSCAN0CFCC14L RSCAN0.CFCC14.UINT16[L]
    2665 #define RSCAN0CFCC14LL RSCAN0.CFCC14.UINT8[LL]
    2666 #define RSCAN0CFCC14LH RSCAN0.CFCC14.UINT8[LH]
    2667 #define RSCAN0CFCC14H RSCAN0.CFCC14.UINT16[H]
    2668 #define RSCAN0CFCC14HL RSCAN0.CFCC14.UINT8[HL]
    2669 #define RSCAN0CFCC14HH RSCAN0.CFCC14.UINT8[HH]
    2670 #define RSCAN0CFSTS0 RSCAN0.CFSTS0.UINT32
    2671 #define RSCAN0CFSTS0L RSCAN0.CFSTS0.UINT16[L]
    2672 #define RSCAN0CFSTS0LL RSCAN0.CFSTS0.UINT8[LL]
    2673 #define RSCAN0CFSTS0LH RSCAN0.CFSTS0.UINT8[LH]
    2674 #define RSCAN0CFSTS0H RSCAN0.CFSTS0.UINT16[H]
    2675 #define RSCAN0CFSTS0HL RSCAN0.CFSTS0.UINT8[HL]
    2676 #define RSCAN0CFSTS0HH RSCAN0.CFSTS0.UINT8[HH]
    2677 #define RSCAN0CFSTS1 RSCAN0.CFSTS1.UINT32
    2678 #define RSCAN0CFSTS1L RSCAN0.CFSTS1.UINT16[L]
    2679 #define RSCAN0CFSTS1LL RSCAN0.CFSTS1.UINT8[LL]
    2680 #define RSCAN0CFSTS1LH RSCAN0.CFSTS1.UINT8[LH]
    2681 #define RSCAN0CFSTS1H RSCAN0.CFSTS1.UINT16[H]
    2682 #define RSCAN0CFSTS1HL RSCAN0.CFSTS1.UINT8[HL]
    2683 #define RSCAN0CFSTS1HH RSCAN0.CFSTS1.UINT8[HH]
    2684 #define RSCAN0CFSTS2 RSCAN0.CFSTS2.UINT32
    2685 #define RSCAN0CFSTS2L RSCAN0.CFSTS2.UINT16[L]
    2686 #define RSCAN0CFSTS2LL RSCAN0.CFSTS2.UINT8[LL]
    2687 #define RSCAN0CFSTS2LH RSCAN0.CFSTS2.UINT8[LH]
    2688 #define RSCAN0CFSTS2H RSCAN0.CFSTS2.UINT16[H]
    2689 #define RSCAN0CFSTS2HL RSCAN0.CFSTS2.UINT8[HL]
    2690 #define RSCAN0CFSTS2HH RSCAN0.CFSTS2.UINT8[HH]
    2691 #define RSCAN0CFSTS3 RSCAN0.CFSTS3.UINT32
    2692 #define RSCAN0CFSTS3L RSCAN0.CFSTS3.UINT16[L]
    2693 #define RSCAN0CFSTS3LL RSCAN0.CFSTS3.UINT8[LL]
    2694 #define RSCAN0CFSTS3LH RSCAN0.CFSTS3.UINT8[LH]
    2695 #define RSCAN0CFSTS3H RSCAN0.CFSTS3.UINT16[H]
    2696 #define RSCAN0CFSTS3HL RSCAN0.CFSTS3.UINT8[HL]
    2697 #define RSCAN0CFSTS3HH RSCAN0.CFSTS3.UINT8[HH]
    2698 #define RSCAN0CFSTS4 RSCAN0.CFSTS4.UINT32
    2699 #define RSCAN0CFSTS4L RSCAN0.CFSTS4.UINT16[L]
    2700 #define RSCAN0CFSTS4LL RSCAN0.CFSTS4.UINT8[LL]
    2701 #define RSCAN0CFSTS4LH RSCAN0.CFSTS4.UINT8[LH]
    2702 #define RSCAN0CFSTS4H RSCAN0.CFSTS4.UINT16[H]
    2703 #define RSCAN0CFSTS4HL RSCAN0.CFSTS4.UINT8[HL]
    2704 #define RSCAN0CFSTS4HH RSCAN0.CFSTS4.UINT8[HH]
    2705 #define RSCAN0CFSTS5 RSCAN0.CFSTS5.UINT32
    2706 #define RSCAN0CFSTS5L RSCAN0.CFSTS5.UINT16[L]
    2707 #define RSCAN0CFSTS5LL RSCAN0.CFSTS5.UINT8[LL]
    2708 #define RSCAN0CFSTS5LH RSCAN0.CFSTS5.UINT8[LH]
    2709 #define RSCAN0CFSTS5H RSCAN0.CFSTS5.UINT16[H]
    2710 #define RSCAN0CFSTS5HL RSCAN0.CFSTS5.UINT8[HL]
    2711 #define RSCAN0CFSTS5HH RSCAN0.CFSTS5.UINT8[HH]
    2712 #define RSCAN0CFSTS6 RSCAN0.CFSTS6.UINT32
    2713 #define RSCAN0CFSTS6L RSCAN0.CFSTS6.UINT16[L]
    2714 #define RSCAN0CFSTS6LL RSCAN0.CFSTS6.UINT8[LL]
    2715 #define RSCAN0CFSTS6LH RSCAN0.CFSTS6.UINT8[LH]
    2716 #define RSCAN0CFSTS6H RSCAN0.CFSTS6.UINT16[H]
    2717 #define RSCAN0CFSTS6HL RSCAN0.CFSTS6.UINT8[HL]
    2718 #define RSCAN0CFSTS6HH RSCAN0.CFSTS6.UINT8[HH]
    2719 #define RSCAN0CFSTS7 RSCAN0.CFSTS7.UINT32
    2720 #define RSCAN0CFSTS7L RSCAN0.CFSTS7.UINT16[L]
    2721 #define RSCAN0CFSTS7LL RSCAN0.CFSTS7.UINT8[LL]
    2722 #define RSCAN0CFSTS7LH RSCAN0.CFSTS7.UINT8[LH]
    2723 #define RSCAN0CFSTS7H RSCAN0.CFSTS7.UINT16[H]
    2724 #define RSCAN0CFSTS7HL RSCAN0.CFSTS7.UINT8[HL]
    2725 #define RSCAN0CFSTS7HH RSCAN0.CFSTS7.UINT8[HH]
    2726 #define RSCAN0CFSTS8 RSCAN0.CFSTS8.UINT32
    2727 #define RSCAN0CFSTS8L RSCAN0.CFSTS8.UINT16[L]
    2728 #define RSCAN0CFSTS8LL RSCAN0.CFSTS8.UINT8[LL]
    2729 #define RSCAN0CFSTS8LH RSCAN0.CFSTS8.UINT8[LH]
    2730 #define RSCAN0CFSTS8H RSCAN0.CFSTS8.UINT16[H]
    2731 #define RSCAN0CFSTS8HL RSCAN0.CFSTS8.UINT8[HL]
    2732 #define RSCAN0CFSTS8HH RSCAN0.CFSTS8.UINT8[HH]
    2733 #define RSCAN0CFSTS9 RSCAN0.CFSTS9.UINT32
    2734 #define RSCAN0CFSTS9L RSCAN0.CFSTS9.UINT16[L]
    2735 #define RSCAN0CFSTS9LL RSCAN0.CFSTS9.UINT8[LL]
    2736 #define RSCAN0CFSTS9LH RSCAN0.CFSTS9.UINT8[LH]
    2737 #define RSCAN0CFSTS9H RSCAN0.CFSTS9.UINT16[H]
    2738 #define RSCAN0CFSTS9HL RSCAN0.CFSTS9.UINT8[HL]
    2739 #define RSCAN0CFSTS9HH RSCAN0.CFSTS9.UINT8[HH]
    2740 #define RSCAN0CFSTS10 RSCAN0.CFSTS10.UINT32
    2741 #define RSCAN0CFSTS10L RSCAN0.CFSTS10.UINT16[L]
    2742 #define RSCAN0CFSTS10LL RSCAN0.CFSTS10.UINT8[LL]
    2743 #define RSCAN0CFSTS10LH RSCAN0.CFSTS10.UINT8[LH]
    2744 #define RSCAN0CFSTS10H RSCAN0.CFSTS10.UINT16[H]
    2745 #define RSCAN0CFSTS10HL RSCAN0.CFSTS10.UINT8[HL]
    2746 #define RSCAN0CFSTS10HH RSCAN0.CFSTS10.UINT8[HH]
    2747 #define RSCAN0CFSTS11 RSCAN0.CFSTS11.UINT32
    2748 #define RSCAN0CFSTS11L RSCAN0.CFSTS11.UINT16[L]
    2749 #define RSCAN0CFSTS11LL RSCAN0.CFSTS11.UINT8[LL]
    2750 #define RSCAN0CFSTS11LH RSCAN0.CFSTS11.UINT8[LH]
    2751 #define RSCAN0CFSTS11H RSCAN0.CFSTS11.UINT16[H]
    2752 #define RSCAN0CFSTS11HL RSCAN0.CFSTS11.UINT8[HL]
    2753 #define RSCAN0CFSTS11HH RSCAN0.CFSTS11.UINT8[HH]
    2754 #define RSCAN0CFSTS12 RSCAN0.CFSTS12.UINT32
    2755 #define RSCAN0CFSTS12L RSCAN0.CFSTS12.UINT16[L]
    2756 #define RSCAN0CFSTS12LL RSCAN0.CFSTS12.UINT8[LL]
    2757 #define RSCAN0CFSTS12LH RSCAN0.CFSTS12.UINT8[LH]
    2758 #define RSCAN0CFSTS12H RSCAN0.CFSTS12.UINT16[H]
    2759 #define RSCAN0CFSTS12HL RSCAN0.CFSTS12.UINT8[HL]
    2760 #define RSCAN0CFSTS12HH RSCAN0.CFSTS12.UINT8[HH]
    2761 #define RSCAN0CFSTS13 RSCAN0.CFSTS13.UINT32
    2762 #define RSCAN0CFSTS13L RSCAN0.CFSTS13.UINT16[L]
    2763 #define RSCAN0CFSTS13LL RSCAN0.CFSTS13.UINT8[LL]
    2764 #define RSCAN0CFSTS13LH RSCAN0.CFSTS13.UINT8[LH]
    2765 #define RSCAN0CFSTS13H RSCAN0.CFSTS13.UINT16[H]
    2766 #define RSCAN0CFSTS13HL RSCAN0.CFSTS13.UINT8[HL]
    2767 #define RSCAN0CFSTS13HH RSCAN0.CFSTS13.UINT8[HH]
    2768 #define RSCAN0CFSTS14 RSCAN0.CFSTS14.UINT32
    2769 #define RSCAN0CFSTS14L RSCAN0.CFSTS14.UINT16[L]
    2770 #define RSCAN0CFSTS14LL RSCAN0.CFSTS14.UINT8[LL]
    2771 #define RSCAN0CFSTS14LH RSCAN0.CFSTS14.UINT8[LH]
    2772 #define RSCAN0CFSTS14H RSCAN0.CFSTS14.UINT16[H]
    2773 #define RSCAN0CFSTS14HL RSCAN0.CFSTS14.UINT8[HL]
    2774 #define RSCAN0CFSTS14HH RSCAN0.CFSTS14.UINT8[HH]
    2775 #define RSCAN0CFPCTR0 RSCAN0.CFPCTR0.UINT32
    2776 #define RSCAN0CFPCTR0L RSCAN0.CFPCTR0.UINT16[L]
    2777 #define RSCAN0CFPCTR0LL RSCAN0.CFPCTR0.UINT8[LL]
    2778 #define RSCAN0CFPCTR0LH RSCAN0.CFPCTR0.UINT8[LH]
    2779 #define RSCAN0CFPCTR0H RSCAN0.CFPCTR0.UINT16[H]
    2780 #define RSCAN0CFPCTR0HL RSCAN0.CFPCTR0.UINT8[HL]
    2781 #define RSCAN0CFPCTR0HH RSCAN0.CFPCTR0.UINT8[HH]
    2782 #define RSCAN0CFPCTR1 RSCAN0.CFPCTR1.UINT32
    2783 #define RSCAN0CFPCTR1L RSCAN0.CFPCTR1.UINT16[L]
    2784 #define RSCAN0CFPCTR1LL RSCAN0.CFPCTR1.UINT8[LL]
    2785 #define RSCAN0CFPCTR1LH RSCAN0.CFPCTR1.UINT8[LH]
    2786 #define RSCAN0CFPCTR1H RSCAN0.CFPCTR1.UINT16[H]
    2787 #define RSCAN0CFPCTR1HL RSCAN0.CFPCTR1.UINT8[HL]
    2788 #define RSCAN0CFPCTR1HH RSCAN0.CFPCTR1.UINT8[HH]
    2789 #define RSCAN0CFPCTR2 RSCAN0.CFPCTR2.UINT32
    2790 #define RSCAN0CFPCTR2L RSCAN0.CFPCTR2.UINT16[L]
    2791 #define RSCAN0CFPCTR2LL RSCAN0.CFPCTR2.UINT8[LL]
    2792 #define RSCAN0CFPCTR2LH RSCAN0.CFPCTR2.UINT8[LH]
    2793 #define RSCAN0CFPCTR2H RSCAN0.CFPCTR2.UINT16[H]
    2794 #define RSCAN0CFPCTR2HL RSCAN0.CFPCTR2.UINT8[HL]
    2795 #define RSCAN0CFPCTR2HH RSCAN0.CFPCTR2.UINT8[HH]
    2796 #define RSCAN0CFPCTR3 RSCAN0.CFPCTR3.UINT32
    2797 #define RSCAN0CFPCTR3L RSCAN0.CFPCTR3.UINT16[L]
    2798 #define RSCAN0CFPCTR3LL RSCAN0.CFPCTR3.UINT8[LL]
    2799 #define RSCAN0CFPCTR3LH RSCAN0.CFPCTR3.UINT8[LH]
    2800 #define RSCAN0CFPCTR3H RSCAN0.CFPCTR3.UINT16[H]
    2801 #define RSCAN0CFPCTR3HL RSCAN0.CFPCTR3.UINT8[HL]
    2802 #define RSCAN0CFPCTR3HH RSCAN0.CFPCTR3.UINT8[HH]
    2803 #define RSCAN0CFPCTR4 RSCAN0.CFPCTR4.UINT32
    2804 #define RSCAN0CFPCTR4L RSCAN0.CFPCTR4.UINT16[L]
    2805 #define RSCAN0CFPCTR4LL RSCAN0.CFPCTR4.UINT8[LL]
    2806 #define RSCAN0CFPCTR4LH RSCAN0.CFPCTR4.UINT8[LH]
    2807 #define RSCAN0CFPCTR4H RSCAN0.CFPCTR4.UINT16[H]
    2808 #define RSCAN0CFPCTR4HL RSCAN0.CFPCTR4.UINT8[HL]
    2809 #define RSCAN0CFPCTR4HH RSCAN0.CFPCTR4.UINT8[HH]
    2810 #define RSCAN0CFPCTR5 RSCAN0.CFPCTR5.UINT32
    2811 #define RSCAN0CFPCTR5L RSCAN0.CFPCTR5.UINT16[L]
    2812 #define RSCAN0CFPCTR5LL RSCAN0.CFPCTR5.UINT8[LL]
    2813 #define RSCAN0CFPCTR5LH RSCAN0.CFPCTR5.UINT8[LH]
    2814 #define RSCAN0CFPCTR5H RSCAN0.CFPCTR5.UINT16[H]
    2815 #define RSCAN0CFPCTR5HL RSCAN0.CFPCTR5.UINT8[HL]
    2816 #define RSCAN0CFPCTR5HH RSCAN0.CFPCTR5.UINT8[HH]
    2817 #define RSCAN0CFPCTR6 RSCAN0.CFPCTR6.UINT32
    2818 #define RSCAN0CFPCTR6L RSCAN0.CFPCTR6.UINT16[L]
    2819 #define RSCAN0CFPCTR6LL RSCAN0.CFPCTR6.UINT8[LL]
    2820 #define RSCAN0CFPCTR6LH RSCAN0.CFPCTR6.UINT8[LH]
    2821 #define RSCAN0CFPCTR6H RSCAN0.CFPCTR6.UINT16[H]
    2822 #define RSCAN0CFPCTR6HL RSCAN0.CFPCTR6.UINT8[HL]
    2823 #define RSCAN0CFPCTR6HH RSCAN0.CFPCTR6.UINT8[HH]
    2824 #define RSCAN0CFPCTR7 RSCAN0.CFPCTR7.UINT32
    2825 #define RSCAN0CFPCTR7L RSCAN0.CFPCTR7.UINT16[L]
    2826 #define RSCAN0CFPCTR7LL RSCAN0.CFPCTR7.UINT8[LL]
    2827 #define RSCAN0CFPCTR7LH RSCAN0.CFPCTR7.UINT8[LH]
    2828 #define RSCAN0CFPCTR7H RSCAN0.CFPCTR7.UINT16[H]
    2829 #define RSCAN0CFPCTR7HL RSCAN0.CFPCTR7.UINT8[HL]
    2830 #define RSCAN0CFPCTR7HH RSCAN0.CFPCTR7.UINT8[HH]
    2831 #define RSCAN0CFPCTR8 RSCAN0.CFPCTR8.UINT32
    2832 #define RSCAN0CFPCTR8L RSCAN0.CFPCTR8.UINT16[L]
    2833 #define RSCAN0CFPCTR8LL RSCAN0.CFPCTR8.UINT8[LL]
    2834 #define RSCAN0CFPCTR8LH RSCAN0.CFPCTR8.UINT8[LH]
    2835 #define RSCAN0CFPCTR8H RSCAN0.CFPCTR8.UINT16[H]
    2836 #define RSCAN0CFPCTR8HL RSCAN0.CFPCTR8.UINT8[HL]
    2837 #define RSCAN0CFPCTR8HH RSCAN0.CFPCTR8.UINT8[HH]
    2838 #define RSCAN0CFPCTR9 RSCAN0.CFPCTR9.UINT32
    2839 #define RSCAN0CFPCTR9L RSCAN0.CFPCTR9.UINT16[L]
    2840 #define RSCAN0CFPCTR9LL RSCAN0.CFPCTR9.UINT8[LL]
    2841 #define RSCAN0CFPCTR9LH RSCAN0.CFPCTR9.UINT8[LH]
    2842 #define RSCAN0CFPCTR9H RSCAN0.CFPCTR9.UINT16[H]
    2843 #define RSCAN0CFPCTR9HL RSCAN0.CFPCTR9.UINT8[HL]
    2844 #define RSCAN0CFPCTR9HH RSCAN0.CFPCTR9.UINT8[HH]
    2845 #define RSCAN0CFPCTR10 RSCAN0.CFPCTR10.UINT32
    2846 #define RSCAN0CFPCTR10L RSCAN0.CFPCTR10.UINT16[L]
    2847 #define RSCAN0CFPCTR10LL RSCAN0.CFPCTR10.UINT8[LL]
    2848 #define RSCAN0CFPCTR10LH RSCAN0.CFPCTR10.UINT8[LH]
    2849 #define RSCAN0CFPCTR10H RSCAN0.CFPCTR10.UINT16[H]
    2850 #define RSCAN0CFPCTR10HL RSCAN0.CFPCTR10.UINT8[HL]
    2851 #define RSCAN0CFPCTR10HH RSCAN0.CFPCTR10.UINT8[HH]
    2852 #define RSCAN0CFPCTR11 RSCAN0.CFPCTR11.UINT32
    2853 #define RSCAN0CFPCTR11L RSCAN0.CFPCTR11.UINT16[L]
    2854 #define RSCAN0CFPCTR11LL RSCAN0.CFPCTR11.UINT8[LL]
    2855 #define RSCAN0CFPCTR11LH RSCAN0.CFPCTR11.UINT8[LH]
    2856 #define RSCAN0CFPCTR11H RSCAN0.CFPCTR11.UINT16[H]
    2857 #define RSCAN0CFPCTR11HL RSCAN0.CFPCTR11.UINT8[HL]
    2858 #define RSCAN0CFPCTR11HH RSCAN0.CFPCTR11.UINT8[HH]
    2859 #define RSCAN0CFPCTR12 RSCAN0.CFPCTR12.UINT32
    2860 #define RSCAN0CFPCTR12L RSCAN0.CFPCTR12.UINT16[L]
    2861 #define RSCAN0CFPCTR12LL RSCAN0.CFPCTR12.UINT8[LL]
    2862 #define RSCAN0CFPCTR12LH RSCAN0.CFPCTR12.UINT8[LH]
    2863 #define RSCAN0CFPCTR12H RSCAN0.CFPCTR12.UINT16[H]
    2864 #define RSCAN0CFPCTR12HL RSCAN0.CFPCTR12.UINT8[HL]
    2865 #define RSCAN0CFPCTR12HH RSCAN0.CFPCTR12.UINT8[HH]
    2866 #define RSCAN0CFPCTR13 RSCAN0.CFPCTR13.UINT32
    2867 #define RSCAN0CFPCTR13L RSCAN0.CFPCTR13.UINT16[L]
    2868 #define RSCAN0CFPCTR13LL RSCAN0.CFPCTR13.UINT8[LL]
    2869 #define RSCAN0CFPCTR13LH RSCAN0.CFPCTR13.UINT8[LH]
    2870 #define RSCAN0CFPCTR13H RSCAN0.CFPCTR13.UINT16[H]
    2871 #define RSCAN0CFPCTR13HL RSCAN0.CFPCTR13.UINT8[HL]
    2872 #define RSCAN0CFPCTR13HH RSCAN0.CFPCTR13.UINT8[HH]
    2873 #define RSCAN0CFPCTR14 RSCAN0.CFPCTR14.UINT32
    2874 #define RSCAN0CFPCTR14L RSCAN0.CFPCTR14.UINT16[L]
    2875 #define RSCAN0CFPCTR14LL RSCAN0.CFPCTR14.UINT8[LL]
    2876 #define RSCAN0CFPCTR14LH RSCAN0.CFPCTR14.UINT8[LH]
    2877 #define RSCAN0CFPCTR14H RSCAN0.CFPCTR14.UINT16[H]
    2878 #define RSCAN0CFPCTR14HL RSCAN0.CFPCTR14.UINT8[HL]
    2879 #define RSCAN0CFPCTR14HH RSCAN0.CFPCTR14.UINT8[HH]
    2880 #define RSCAN0FESTS RSCAN0.FESTS.UINT32
    2881 #define RSCAN0FESTSL RSCAN0.FESTS.UINT16[L]
    2882 #define RSCAN0FESTSLL RSCAN0.FESTS.UINT8[LL]
    2883 #define RSCAN0FESTSLH RSCAN0.FESTS.UINT8[LH]
    2884 #define RSCAN0FESTSH RSCAN0.FESTS.UINT16[H]
    2885 #define RSCAN0FESTSHL RSCAN0.FESTS.UINT8[HL]
    2886 #define RSCAN0FESTSHH RSCAN0.FESTS.UINT8[HH]
    2887 #define RSCAN0FFSTS RSCAN0.FFSTS.UINT32
    2888 #define RSCAN0FFSTSL RSCAN0.FFSTS.UINT16[L]
    2889 #define RSCAN0FFSTSLL RSCAN0.FFSTS.UINT8[LL]
    2890 #define RSCAN0FFSTSLH RSCAN0.FFSTS.UINT8[LH]
    2891 #define RSCAN0FFSTSH RSCAN0.FFSTS.UINT16[H]
    2892 #define RSCAN0FFSTSHL RSCAN0.FFSTS.UINT8[HL]
    2893 #define RSCAN0FFSTSHH RSCAN0.FFSTS.UINT8[HH]
    2894 #define RSCAN0FMSTS RSCAN0.FMSTS.UINT32
    2895 #define RSCAN0FMSTSL RSCAN0.FMSTS.UINT16[L]
    2896 #define RSCAN0FMSTSLL RSCAN0.FMSTS.UINT8[LL]
    2897 #define RSCAN0FMSTSLH RSCAN0.FMSTS.UINT8[LH]
    2898 #define RSCAN0FMSTSH RSCAN0.FMSTS.UINT16[H]
    2899 #define RSCAN0FMSTSHL RSCAN0.FMSTS.UINT8[HL]
    2900 #define RSCAN0FMSTSHH RSCAN0.FMSTS.UINT8[HH]
    2901 #define RSCAN0RFISTS RSCAN0.RFISTS.UINT32
    2902 #define RSCAN0RFISTSL RSCAN0.RFISTS.UINT16[L]
    2903 #define RSCAN0RFISTSLL RSCAN0.RFISTS.UINT8[LL]
    2904 #define RSCAN0RFISTSLH RSCAN0.RFISTS.UINT8[LH]
    2905 #define RSCAN0RFISTSH RSCAN0.RFISTS.UINT16[H]
    2906 #define RSCAN0RFISTSHL RSCAN0.RFISTS.UINT8[HL]
    2907 #define RSCAN0RFISTSHH RSCAN0.RFISTS.UINT8[HH]
    2908 #define RSCAN0CFRISTS RSCAN0.CFRISTS.UINT32
    2909 #define RSCAN0CFRISTSL RSCAN0.CFRISTS.UINT16[L]
    2910 #define RSCAN0CFRISTSLL RSCAN0.CFRISTS.UINT8[LL]
    2911 #define RSCAN0CFRISTSLH RSCAN0.CFRISTS.UINT8[LH]
    2912 #define RSCAN0CFRISTSH RSCAN0.CFRISTS.UINT16[H]
    2913 #define RSCAN0CFRISTSHL RSCAN0.CFRISTS.UINT8[HL]
    2914 #define RSCAN0CFRISTSHH RSCAN0.CFRISTS.UINT8[HH]
    2915 #define RSCAN0CFTISTS RSCAN0.CFTISTS.UINT32
    2916 #define RSCAN0CFTISTSL RSCAN0.CFTISTS.UINT16[L]
    2917 #define RSCAN0CFTISTSLL RSCAN0.CFTISTS.UINT8[LL]
    2918 #define RSCAN0CFTISTSLH RSCAN0.CFTISTS.UINT8[LH]
    2919 #define RSCAN0CFTISTSH RSCAN0.CFTISTS.UINT16[H]
    2920 #define RSCAN0CFTISTSHL RSCAN0.CFTISTS.UINT8[HL]
    2921 #define RSCAN0CFTISTSHH RSCAN0.CFTISTS.UINT8[HH]
    2922 #define RSCAN0TMC0 RSCAN0.TMC0
    2923 #define RSCAN0TMC1 RSCAN0.TMC1
    2924 #define RSCAN0TMC2 RSCAN0.TMC2
    2925 #define RSCAN0TMC3 RSCAN0.TMC3
    2926 #define RSCAN0TMC4 RSCAN0.TMC4
    2927 #define RSCAN0TMC5 RSCAN0.TMC5
    2928 #define RSCAN0TMC6 RSCAN0.TMC6
    2929 #define RSCAN0TMC7 RSCAN0.TMC7
    2930 #define RSCAN0TMC8 RSCAN0.TMC8
    2931 #define RSCAN0TMC9 RSCAN0.TMC9
    2932 #define RSCAN0TMC10 RSCAN0.TMC10
    2933 #define RSCAN0TMC11 RSCAN0.TMC11
    2934 #define RSCAN0TMC12 RSCAN0.TMC12
    2935 #define RSCAN0TMC13 RSCAN0.TMC13
    2936 #define RSCAN0TMC14 RSCAN0.TMC14
    2937 #define RSCAN0TMC15 RSCAN0.TMC15
    2938 #define RSCAN0TMC16 RSCAN0.TMC16
    2939 #define RSCAN0TMC17 RSCAN0.TMC17
    2940 #define RSCAN0TMC18 RSCAN0.TMC18
    2941 #define RSCAN0TMC19 RSCAN0.TMC19
    2942 #define RSCAN0TMC20 RSCAN0.TMC20
    2943 #define RSCAN0TMC21 RSCAN0.TMC21
    2944 #define RSCAN0TMC22 RSCAN0.TMC22
    2945 #define RSCAN0TMC23 RSCAN0.TMC23
    2946 #define RSCAN0TMC24 RSCAN0.TMC24
    2947 #define RSCAN0TMC25 RSCAN0.TMC25
    2948 #define RSCAN0TMC26 RSCAN0.TMC26
    2949 #define RSCAN0TMC27 RSCAN0.TMC27
    2950 #define RSCAN0TMC28 RSCAN0.TMC28
    2951 #define RSCAN0TMC29 RSCAN0.TMC29
    2952 #define RSCAN0TMC30 RSCAN0.TMC30
    2953 #define RSCAN0TMC31 RSCAN0.TMC31
    2954 #define RSCAN0TMC32 RSCAN0.TMC32
    2955 #define RSCAN0TMC33 RSCAN0.TMC33
    2956 #define RSCAN0TMC34 RSCAN0.TMC34
    2957 #define RSCAN0TMC35 RSCAN0.TMC35
    2958 #define RSCAN0TMC36 RSCAN0.TMC36
    2959 #define RSCAN0TMC37 RSCAN0.TMC37
    2960 #define RSCAN0TMC38 RSCAN0.TMC38
    2961 #define RSCAN0TMC39 RSCAN0.TMC39
    2962 #define RSCAN0TMC40 RSCAN0.TMC40
    2963 #define RSCAN0TMC41 RSCAN0.TMC41
    2964 #define RSCAN0TMC42 RSCAN0.TMC42
    2965 #define RSCAN0TMC43 RSCAN0.TMC43
    2966 #define RSCAN0TMC44 RSCAN0.TMC44
    2967 #define RSCAN0TMC45 RSCAN0.TMC45
    2968 #define RSCAN0TMC46 RSCAN0.TMC46
    2969 #define RSCAN0TMC47 RSCAN0.TMC47
    2970 #define RSCAN0TMC48 RSCAN0.TMC48
    2971 #define RSCAN0TMC49 RSCAN0.TMC49
    2972 #define RSCAN0TMC50 RSCAN0.TMC50
    2973 #define RSCAN0TMC51 RSCAN0.TMC51
    2974 #define RSCAN0TMC52 RSCAN0.TMC52
    2975 #define RSCAN0TMC53 RSCAN0.TMC53
    2976 #define RSCAN0TMC54 RSCAN0.TMC54
    2977 #define RSCAN0TMC55 RSCAN0.TMC55
    2978 #define RSCAN0TMC56 RSCAN0.TMC56
    2979 #define RSCAN0TMC57 RSCAN0.TMC57
    2980 #define RSCAN0TMC58 RSCAN0.TMC58
    2981 #define RSCAN0TMC59 RSCAN0.TMC59
    2982 #define RSCAN0TMC60 RSCAN0.TMC60
    2983 #define RSCAN0TMC61 RSCAN0.TMC61
    2984 #define RSCAN0TMC62 RSCAN0.TMC62
    2985 #define RSCAN0TMC63 RSCAN0.TMC63
    2986 #define RSCAN0TMC64 RSCAN0.TMC64
    2987 #define RSCAN0TMC65 RSCAN0.TMC65
    2988 #define RSCAN0TMC66 RSCAN0.TMC66
    2989 #define RSCAN0TMC67 RSCAN0.TMC67
    2990 #define RSCAN0TMC68 RSCAN0.TMC68
    2991 #define RSCAN0TMC69 RSCAN0.TMC69
    2992 #define RSCAN0TMC70 RSCAN0.TMC70
    2993 #define RSCAN0TMC71 RSCAN0.TMC71
    2994 #define RSCAN0TMC72 RSCAN0.TMC72
    2995 #define RSCAN0TMC73 RSCAN0.TMC73
    2996 #define RSCAN0TMC74 RSCAN0.TMC74
    2997 #define RSCAN0TMC75 RSCAN0.TMC75
    2998 #define RSCAN0TMC76 RSCAN0.TMC76
    2999 #define RSCAN0TMC77 RSCAN0.TMC77
    3000 #define RSCAN0TMC78 RSCAN0.TMC78
    3001 #define RSCAN0TMC79 RSCAN0.TMC79
    3002 #define RSCAN0TMSTS0 RSCAN0.TMSTS0
    3003 #define RSCAN0TMSTS1 RSCAN0.TMSTS1
    3004 #define RSCAN0TMSTS2 RSCAN0.TMSTS2
    3005 #define RSCAN0TMSTS3 RSCAN0.TMSTS3
    3006 #define RSCAN0TMSTS4 RSCAN0.TMSTS4
    3007 #define RSCAN0TMSTS5 RSCAN0.TMSTS5
    3008 #define RSCAN0TMSTS6 RSCAN0.TMSTS6
    3009 #define RSCAN0TMSTS7 RSCAN0.TMSTS7
    3010 #define RSCAN0TMSTS8 RSCAN0.TMSTS8
    3011 #define RSCAN0TMSTS9 RSCAN0.TMSTS9
    3012 #define RSCAN0TMSTS10 RSCAN0.TMSTS10
    3013 #define RSCAN0TMSTS11 RSCAN0.TMSTS11
    3014 #define RSCAN0TMSTS12 RSCAN0.TMSTS12
    3015 #define RSCAN0TMSTS13 RSCAN0.TMSTS13
    3016 #define RSCAN0TMSTS14 RSCAN0.TMSTS14
    3017 #define RSCAN0TMSTS15 RSCAN0.TMSTS15
    3018 #define RSCAN0TMSTS16 RSCAN0.TMSTS16
    3019 #define RSCAN0TMSTS17 RSCAN0.TMSTS17
    3020 #define RSCAN0TMSTS18 RSCAN0.TMSTS18
    3021 #define RSCAN0TMSTS19 RSCAN0.TMSTS19
    3022 #define RSCAN0TMSTS20 RSCAN0.TMSTS20
    3023 #define RSCAN0TMSTS21 RSCAN0.TMSTS21
    3024 #define RSCAN0TMSTS22 RSCAN0.TMSTS22
    3025 #define RSCAN0TMSTS23 RSCAN0.TMSTS23
    3026 #define RSCAN0TMSTS24 RSCAN0.TMSTS24
    3027 #define RSCAN0TMSTS25 RSCAN0.TMSTS25
    3028 #define RSCAN0TMSTS26 RSCAN0.TMSTS26
    3029 #define RSCAN0TMSTS27 RSCAN0.TMSTS27
    3030 #define RSCAN0TMSTS28 RSCAN0.TMSTS28
    3031 #define RSCAN0TMSTS29 RSCAN0.TMSTS29
    3032 #define RSCAN0TMSTS30 RSCAN0.TMSTS30
    3033 #define RSCAN0TMSTS31 RSCAN0.TMSTS31
    3034 #define RSCAN0TMSTS32 RSCAN0.TMSTS32
    3035 #define RSCAN0TMSTS33 RSCAN0.TMSTS33
    3036 #define RSCAN0TMSTS34 RSCAN0.TMSTS34
    3037 #define RSCAN0TMSTS35 RSCAN0.TMSTS35
    3038 #define RSCAN0TMSTS36 RSCAN0.TMSTS36
    3039 #define RSCAN0TMSTS37 RSCAN0.TMSTS37
    3040 #define RSCAN0TMSTS38 RSCAN0.TMSTS38
    3041 #define RSCAN0TMSTS39 RSCAN0.TMSTS39
    3042 #define RSCAN0TMSTS40 RSCAN0.TMSTS40
    3043 #define RSCAN0TMSTS41 RSCAN0.TMSTS41
    3044 #define RSCAN0TMSTS42 RSCAN0.TMSTS42
    3045 #define RSCAN0TMSTS43 RSCAN0.TMSTS43
    3046 #define RSCAN0TMSTS44 RSCAN0.TMSTS44
    3047 #define RSCAN0TMSTS45 RSCAN0.TMSTS45
    3048 #define RSCAN0TMSTS46 RSCAN0.TMSTS46
    3049 #define RSCAN0TMSTS47 RSCAN0.TMSTS47
    3050 #define RSCAN0TMSTS48 RSCAN0.TMSTS48
    3051 #define RSCAN0TMSTS49 RSCAN0.TMSTS49
    3052 #define RSCAN0TMSTS50 RSCAN0.TMSTS50
    3053 #define RSCAN0TMSTS51 RSCAN0.TMSTS51
    3054 #define RSCAN0TMSTS52 RSCAN0.TMSTS52
    3055 #define RSCAN0TMSTS53 RSCAN0.TMSTS53
    3056 #define RSCAN0TMSTS54 RSCAN0.TMSTS54
    3057 #define RSCAN0TMSTS55 RSCAN0.TMSTS55
    3058 #define RSCAN0TMSTS56 RSCAN0.TMSTS56
    3059 #define RSCAN0TMSTS57 RSCAN0.TMSTS57
    3060 #define RSCAN0TMSTS58 RSCAN0.TMSTS58
    3061 #define RSCAN0TMSTS59 RSCAN0.TMSTS59
    3062 #define RSCAN0TMSTS60 RSCAN0.TMSTS60
    3063 #define RSCAN0TMSTS61 RSCAN0.TMSTS61
    3064 #define RSCAN0TMSTS62 RSCAN0.TMSTS62
    3065 #define RSCAN0TMSTS63 RSCAN0.TMSTS63
    3066 #define RSCAN0TMSTS64 RSCAN0.TMSTS64
    3067 #define RSCAN0TMSTS65 RSCAN0.TMSTS65
    3068 #define RSCAN0TMSTS66 RSCAN0.TMSTS66
    3069 #define RSCAN0TMSTS67 RSCAN0.TMSTS67
    3070 #define RSCAN0TMSTS68 RSCAN0.TMSTS68
    3071 #define RSCAN0TMSTS69 RSCAN0.TMSTS69
    3072 #define RSCAN0TMSTS70 RSCAN0.TMSTS70
    3073 #define RSCAN0TMSTS71 RSCAN0.TMSTS71
    3074 #define RSCAN0TMSTS72 RSCAN0.TMSTS72
    3075 #define RSCAN0TMSTS73 RSCAN0.TMSTS73
    3076 #define RSCAN0TMSTS74 RSCAN0.TMSTS74
    3077 #define RSCAN0TMSTS75 RSCAN0.TMSTS75
    3078 #define RSCAN0TMSTS76 RSCAN0.TMSTS76
    3079 #define RSCAN0TMSTS77 RSCAN0.TMSTS77
    3080 #define RSCAN0TMSTS78 RSCAN0.TMSTS78
    3081 #define RSCAN0TMSTS79 RSCAN0.TMSTS79
    3082 #define RSCAN0TMTRSTS0 RSCAN0.TMTRSTS0.UINT32
    3083 #define RSCAN0TMTRSTS0L RSCAN0.TMTRSTS0.UINT16[L]
    3084 #define RSCAN0TMTRSTS0LL RSCAN0.TMTRSTS0.UINT8[LL]
    3085 #define RSCAN0TMTRSTS0LH RSCAN0.TMTRSTS0.UINT8[LH]
    3086 #define RSCAN0TMTRSTS0H RSCAN0.TMTRSTS0.UINT16[H]
    3087 #define RSCAN0TMTRSTS0HL RSCAN0.TMTRSTS0.UINT8[HL]
    3088 #define RSCAN0TMTRSTS0HH RSCAN0.TMTRSTS0.UINT8[HH]
    3089 #define RSCAN0TMTRSTS1 RSCAN0.TMTRSTS1.UINT32
    3090 #define RSCAN0TMTRSTS1L RSCAN0.TMTRSTS1.UINT16[L]
    3091 #define RSCAN0TMTRSTS1LL RSCAN0.TMTRSTS1.UINT8[LL]
    3092 #define RSCAN0TMTRSTS1LH RSCAN0.TMTRSTS1.UINT8[LH]
    3093 #define RSCAN0TMTRSTS1H RSCAN0.TMTRSTS1.UINT16[H]
    3094 #define RSCAN0TMTRSTS1HL RSCAN0.TMTRSTS1.UINT8[HL]
    3095 #define RSCAN0TMTRSTS1HH RSCAN0.TMTRSTS1.UINT8[HH]
    3096 #define RSCAN0TMTRSTS2 RSCAN0.TMTRSTS2.UINT32
    3097 #define RSCAN0TMTRSTS2L RSCAN0.TMTRSTS2.UINT16[L]
    3098 #define RSCAN0TMTRSTS2LL RSCAN0.TMTRSTS2.UINT8[LL]
    3099 #define RSCAN0TMTRSTS2LH RSCAN0.TMTRSTS2.UINT8[LH]
    3100 #define RSCAN0TMTRSTS2H RSCAN0.TMTRSTS2.UINT16[H]
    3101 #define RSCAN0TMTRSTS2HL RSCAN0.TMTRSTS2.UINT8[HL]
    3102 #define RSCAN0TMTRSTS2HH RSCAN0.TMTRSTS2.UINT8[HH]
    3103 #define RSCAN0TMTARSTS0 RSCAN0.TMTARSTS0.UINT32
    3104 #define RSCAN0TMTARSTS0L RSCAN0.TMTARSTS0.UINT16[L]
    3105 #define RSCAN0TMTARSTS0LL RSCAN0.TMTARSTS0.UINT8[LL]
    3106 #define RSCAN0TMTARSTS0LH RSCAN0.TMTARSTS0.UINT8[LH]
    3107 #define RSCAN0TMTARSTS0H RSCAN0.TMTARSTS0.UINT16[H]
    3108 #define RSCAN0TMTARSTS0HL RSCAN0.TMTARSTS0.UINT8[HL]
    3109 #define RSCAN0TMTARSTS0HH RSCAN0.TMTARSTS0.UINT8[HH]
    3110 #define RSCAN0TMTARSTS1 RSCAN0.TMTARSTS1.UINT32
    3111 #define RSCAN0TMTARSTS1L RSCAN0.TMTARSTS1.UINT16[L]
    3112 #define RSCAN0TMTARSTS1LL RSCAN0.TMTARSTS1.UINT8[LL]
    3113 #define RSCAN0TMTARSTS1LH RSCAN0.TMTARSTS1.UINT8[LH]
    3114 #define RSCAN0TMTARSTS1H RSCAN0.TMTARSTS1.UINT16[H]
    3115 #define RSCAN0TMTARSTS1HL RSCAN0.TMTARSTS1.UINT8[HL]
    3116 #define RSCAN0TMTARSTS1HH RSCAN0.TMTARSTS1.UINT8[HH]
    3117 #define RSCAN0TMTARSTS2 RSCAN0.TMTARSTS2.UINT32
    3118 #define RSCAN0TMTARSTS2L RSCAN0.TMTARSTS2.UINT16[L]
    3119 #define RSCAN0TMTARSTS2LL RSCAN0.TMTARSTS2.UINT8[LL]
    3120 #define RSCAN0TMTARSTS2LH RSCAN0.TMTARSTS2.UINT8[LH]
    3121 #define RSCAN0TMTARSTS2H RSCAN0.TMTARSTS2.UINT16[H]
    3122 #define RSCAN0TMTARSTS2HL RSCAN0.TMTARSTS2.UINT8[HL]
    3123 #define RSCAN0TMTARSTS2HH RSCAN0.TMTARSTS2.UINT8[HH]
    3124 #define RSCAN0TMTCSTS0 RSCAN0.TMTCSTS0.UINT32
    3125 #define RSCAN0TMTCSTS0L RSCAN0.TMTCSTS0.UINT16[L]
    3126 #define RSCAN0TMTCSTS0LL RSCAN0.TMTCSTS0.UINT8[LL]
    3127 #define RSCAN0TMTCSTS0LH RSCAN0.TMTCSTS0.UINT8[LH]
    3128 #define RSCAN0TMTCSTS0H RSCAN0.TMTCSTS0.UINT16[H]
    3129 #define RSCAN0TMTCSTS0HL RSCAN0.TMTCSTS0.UINT8[HL]
    3130 #define RSCAN0TMTCSTS0HH RSCAN0.TMTCSTS0.UINT8[HH]
    3131 #define RSCAN0TMTCSTS1 RSCAN0.TMTCSTS1.UINT32
    3132 #define RSCAN0TMTCSTS1L RSCAN0.TMTCSTS1.UINT16[L]
    3133 #define RSCAN0TMTCSTS1LL RSCAN0.TMTCSTS1.UINT8[LL]
    3134 #define RSCAN0TMTCSTS1LH RSCAN0.TMTCSTS1.UINT8[LH]
    3135 #define RSCAN0TMTCSTS1H RSCAN0.TMTCSTS1.UINT16[H]
    3136 #define RSCAN0TMTCSTS1HL RSCAN0.TMTCSTS1.UINT8[HL]
    3137 #define RSCAN0TMTCSTS1HH RSCAN0.TMTCSTS1.UINT8[HH]
    3138 #define RSCAN0TMTCSTS2 RSCAN0.TMTCSTS2.UINT32
    3139 #define RSCAN0TMTCSTS2L RSCAN0.TMTCSTS2.UINT16[L]
    3140 #define RSCAN0TMTCSTS2LL RSCAN0.TMTCSTS2.UINT8[LL]
    3141 #define RSCAN0TMTCSTS2LH RSCAN0.TMTCSTS2.UINT8[LH]
    3142 #define RSCAN0TMTCSTS2H RSCAN0.TMTCSTS2.UINT16[H]
    3143 #define RSCAN0TMTCSTS2HL RSCAN0.TMTCSTS2.UINT8[HL]
    3144 #define RSCAN0TMTCSTS2HH RSCAN0.TMTCSTS2.UINT8[HH]
    3145 #define RSCAN0TMTASTS0 RSCAN0.TMTASTS0.UINT32
    3146 #define RSCAN0TMTASTS0L RSCAN0.TMTASTS0.UINT16[L]
    3147 #define RSCAN0TMTASTS0LL RSCAN0.TMTASTS0.UINT8[LL]
    3148 #define RSCAN0TMTASTS0LH RSCAN0.TMTASTS0.UINT8[LH]
    3149 #define RSCAN0TMTASTS0H RSCAN0.TMTASTS0.UINT16[H]
    3150 #define RSCAN0TMTASTS0HL RSCAN0.TMTASTS0.UINT8[HL]
    3151 #define RSCAN0TMTASTS0HH RSCAN0.TMTASTS0.UINT8[HH]
    3152 #define RSCAN0TMTASTS1 RSCAN0.TMTASTS1.UINT32
    3153 #define RSCAN0TMTASTS1L RSCAN0.TMTASTS1.UINT16[L]
    3154 #define RSCAN0TMTASTS1LL RSCAN0.TMTASTS1.UINT8[LL]
    3155 #define RSCAN0TMTASTS1LH RSCAN0.TMTASTS1.UINT8[LH]
    3156 #define RSCAN0TMTASTS1H RSCAN0.TMTASTS1.UINT16[H]
    3157 #define RSCAN0TMTASTS1HL RSCAN0.TMTASTS1.UINT8[HL]
    3158 #define RSCAN0TMTASTS1HH RSCAN0.TMTASTS1.UINT8[HH]
    3159 #define RSCAN0TMTASTS2 RSCAN0.TMTASTS2.UINT32
    3160 #define RSCAN0TMTASTS2L RSCAN0.TMTASTS2.UINT16[L]
    3161 #define RSCAN0TMTASTS2LL RSCAN0.TMTASTS2.UINT8[LL]
    3162 #define RSCAN0TMTASTS2LH RSCAN0.TMTASTS2.UINT8[LH]
    3163 #define RSCAN0TMTASTS2H RSCAN0.TMTASTS2.UINT16[H]
    3164 #define RSCAN0TMTASTS2HL RSCAN0.TMTASTS2.UINT8[HL]
    3165 #define RSCAN0TMTASTS2HH RSCAN0.TMTASTS2.UINT8[HH]
    3166 #define RSCAN0TMIEC0 RSCAN0.TMIEC0.UINT32
    3167 #define RSCAN0TMIEC0L RSCAN0.TMIEC0.UINT16[L]
    3168 #define RSCAN0TMIEC0LL RSCAN0.TMIEC0.UINT8[LL]
    3169 #define RSCAN0TMIEC0LH RSCAN0.TMIEC0.UINT8[LH]
    3170 #define RSCAN0TMIEC0H RSCAN0.TMIEC0.UINT16[H]
    3171 #define RSCAN0TMIEC0HL RSCAN0.TMIEC0.UINT8[HL]
    3172 #define RSCAN0TMIEC0HH RSCAN0.TMIEC0.UINT8[HH]
    3173 #define RSCAN0TMIEC1 RSCAN0.TMIEC1.UINT32
    3174 #define RSCAN0TMIEC1L RSCAN0.TMIEC1.UINT16[L]
    3175 #define RSCAN0TMIEC1LL RSCAN0.TMIEC1.UINT8[LL]
    3176 #define RSCAN0TMIEC1LH RSCAN0.TMIEC1.UINT8[LH]
    3177 #define RSCAN0TMIEC1H RSCAN0.TMIEC1.UINT16[H]
    3178 #define RSCAN0TMIEC1HL RSCAN0.TMIEC1.UINT8[HL]
    3179 #define RSCAN0TMIEC1HH RSCAN0.TMIEC1.UINT8[HH]
    3180 #define RSCAN0TMIEC2 RSCAN0.TMIEC2.UINT32
    3181 #define RSCAN0TMIEC2L RSCAN0.TMIEC2.UINT16[L]
    3182 #define RSCAN0TMIEC2LL RSCAN0.TMIEC2.UINT8[LL]
    3183 #define RSCAN0TMIEC2LH RSCAN0.TMIEC2.UINT8[LH]
    3184 #define RSCAN0TMIEC2H RSCAN0.TMIEC2.UINT16[H]
    3185 #define RSCAN0TMIEC2HL RSCAN0.TMIEC2.UINT8[HL]
    3186 #define RSCAN0TMIEC2HH RSCAN0.TMIEC2.UINT8[HH]
    3187 #define RSCAN0TXQCC0 RSCAN0.TXQCC0.UINT32
    3188 #define RSCAN0TXQCC0L RSCAN0.TXQCC0.UINT16[L]
    3189 #define RSCAN0TXQCC0LL RSCAN0.TXQCC0.UINT8[LL]
    3190 #define RSCAN0TXQCC0LH RSCAN0.TXQCC0.UINT8[LH]
    3191 #define RSCAN0TXQCC0H RSCAN0.TXQCC0.UINT16[H]
    3192 #define RSCAN0TXQCC0HL RSCAN0.TXQCC0.UINT8[HL]
    3193 #define RSCAN0TXQCC0HH RSCAN0.TXQCC0.UINT8[HH]
    3194 #define RSCAN0TXQCC1 RSCAN0.TXQCC1.UINT32
    3195 #define RSCAN0TXQCC1L RSCAN0.TXQCC1.UINT16[L]
    3196 #define RSCAN0TXQCC1LL RSCAN0.TXQCC1.UINT8[LL]
    3197 #define RSCAN0TXQCC1LH RSCAN0.TXQCC1.UINT8[LH]
    3198 #define RSCAN0TXQCC1H RSCAN0.TXQCC1.UINT16[H]
    3199 #define RSCAN0TXQCC1HL RSCAN0.TXQCC1.UINT8[HL]
    3200 #define RSCAN0TXQCC1HH RSCAN0.TXQCC1.UINT8[HH]
    3201 #define RSCAN0TXQCC2 RSCAN0.TXQCC2.UINT32
    3202 #define RSCAN0TXQCC2L RSCAN0.TXQCC2.UINT16[L]
    3203 #define RSCAN0TXQCC2LL RSCAN0.TXQCC2.UINT8[LL]
    3204 #define RSCAN0TXQCC2LH RSCAN0.TXQCC2.UINT8[LH]
    3205 #define RSCAN0TXQCC2H RSCAN0.TXQCC2.UINT16[H]
    3206 #define RSCAN0TXQCC2HL RSCAN0.TXQCC2.UINT8[HL]
    3207 #define RSCAN0TXQCC2HH RSCAN0.TXQCC2.UINT8[HH]
    3208 #define RSCAN0TXQCC3 RSCAN0.TXQCC3.UINT32
    3209 #define RSCAN0TXQCC3L RSCAN0.TXQCC3.UINT16[L]
    3210 #define RSCAN0TXQCC3LL RSCAN0.TXQCC3.UINT8[LL]
    3211 #define RSCAN0TXQCC3LH RSCAN0.TXQCC3.UINT8[LH]
    3212 #define RSCAN0TXQCC3H RSCAN0.TXQCC3.UINT16[H]
    3213 #define RSCAN0TXQCC3HL RSCAN0.TXQCC3.UINT8[HL]
    3214 #define RSCAN0TXQCC3HH RSCAN0.TXQCC3.UINT8[HH]
    3215 #define RSCAN0TXQCC4 RSCAN0.TXQCC4.UINT32
    3216 #define RSCAN0TXQCC4L RSCAN0.TXQCC4.UINT16[L]
    3217 #define RSCAN0TXQCC4LL RSCAN0.TXQCC4.UINT8[LL]
    3218 #define RSCAN0TXQCC4LH RSCAN0.TXQCC4.UINT8[LH]
    3219 #define RSCAN0TXQCC4H RSCAN0.TXQCC4.UINT16[H]
    3220 #define RSCAN0TXQCC4HL RSCAN0.TXQCC4.UINT8[HL]
    3221 #define RSCAN0TXQCC4HH RSCAN0.TXQCC4.UINT8[HH]
    3222 #define RSCAN0TXQSTS0 RSCAN0.TXQSTS0.UINT32
    3223 #define RSCAN0TXQSTS0L RSCAN0.TXQSTS0.UINT16[L]
    3224 #define RSCAN0TXQSTS0LL RSCAN0.TXQSTS0.UINT8[LL]
    3225 #define RSCAN0TXQSTS0LH RSCAN0.TXQSTS0.UINT8[LH]
    3226 #define RSCAN0TXQSTS0H RSCAN0.TXQSTS0.UINT16[H]
    3227 #define RSCAN0TXQSTS0HL RSCAN0.TXQSTS0.UINT8[HL]
    3228 #define RSCAN0TXQSTS0HH RSCAN0.TXQSTS0.UINT8[HH]
    3229 #define RSCAN0TXQSTS1 RSCAN0.TXQSTS1.UINT32
    3230 #define RSCAN0TXQSTS1L RSCAN0.TXQSTS1.UINT16[L]
    3231 #define RSCAN0TXQSTS1LL RSCAN0.TXQSTS1.UINT8[LL]
    3232 #define RSCAN0TXQSTS1LH RSCAN0.TXQSTS1.UINT8[LH]
    3233 #define RSCAN0TXQSTS1H RSCAN0.TXQSTS1.UINT16[H]
    3234 #define RSCAN0TXQSTS1HL RSCAN0.TXQSTS1.UINT8[HL]
    3235 #define RSCAN0TXQSTS1HH RSCAN0.TXQSTS1.UINT8[HH]
    3236 #define RSCAN0TXQSTS2 RSCAN0.TXQSTS2.UINT32
    3237 #define RSCAN0TXQSTS2L RSCAN0.TXQSTS2.UINT16[L]
    3238 #define RSCAN0TXQSTS2LL RSCAN0.TXQSTS2.UINT8[LL]
    3239 #define RSCAN0TXQSTS2LH RSCAN0.TXQSTS2.UINT8[LH]
    3240 #define RSCAN0TXQSTS2H RSCAN0.TXQSTS2.UINT16[H]
    3241 #define RSCAN0TXQSTS2HL RSCAN0.TXQSTS2.UINT8[HL]
    3242 #define RSCAN0TXQSTS2HH RSCAN0.TXQSTS2.UINT8[HH]
    3243 #define RSCAN0TXQSTS3 RSCAN0.TXQSTS3.UINT32
    3244 #define RSCAN0TXQSTS3L RSCAN0.TXQSTS3.UINT16[L]
    3245 #define RSCAN0TXQSTS3LL RSCAN0.TXQSTS3.UINT8[LL]
    3246 #define RSCAN0TXQSTS3LH RSCAN0.TXQSTS3.UINT8[LH]
    3247 #define RSCAN0TXQSTS3H RSCAN0.TXQSTS3.UINT16[H]
    3248 #define RSCAN0TXQSTS3HL RSCAN0.TXQSTS3.UINT8[HL]
    3249 #define RSCAN0TXQSTS3HH RSCAN0.TXQSTS3.UINT8[HH]
    3250 #define RSCAN0TXQSTS4 RSCAN0.TXQSTS4.UINT32
    3251 #define RSCAN0TXQSTS4L RSCAN0.TXQSTS4.UINT16[L]
    3252 #define RSCAN0TXQSTS4LL RSCAN0.TXQSTS4.UINT8[LL]
    3253 #define RSCAN0TXQSTS4LH RSCAN0.TXQSTS4.UINT8[LH]
    3254 #define RSCAN0TXQSTS4H RSCAN0.TXQSTS4.UINT16[H]
    3255 #define RSCAN0TXQSTS4HL RSCAN0.TXQSTS4.UINT8[HL]
    3256 #define RSCAN0TXQSTS4HH RSCAN0.TXQSTS4.UINT8[HH]
    3257 #define RSCAN0TXQPCTR0 RSCAN0.TXQPCTR0.UINT32
    3258 #define RSCAN0TXQPCTR0L RSCAN0.TXQPCTR0.UINT16[L]
    3259 #define RSCAN0TXQPCTR0LL RSCAN0.TXQPCTR0.UINT8[LL]
    3260 #define RSCAN0TXQPCTR0LH RSCAN0.TXQPCTR0.UINT8[LH]
    3261 #define RSCAN0TXQPCTR0H RSCAN0.TXQPCTR0.UINT16[H]
    3262 #define RSCAN0TXQPCTR0HL RSCAN0.TXQPCTR0.UINT8[HL]
    3263 #define RSCAN0TXQPCTR0HH RSCAN0.TXQPCTR0.UINT8[HH]
    3264 #define RSCAN0TXQPCTR1 RSCAN0.TXQPCTR1.UINT32
    3265 #define RSCAN0TXQPCTR1L RSCAN0.TXQPCTR1.UINT16[L]
    3266 #define RSCAN0TXQPCTR1LL RSCAN0.TXQPCTR1.UINT8[LL]
    3267 #define RSCAN0TXQPCTR1LH RSCAN0.TXQPCTR1.UINT8[LH]
    3268 #define RSCAN0TXQPCTR1H RSCAN0.TXQPCTR1.UINT16[H]
    3269 #define RSCAN0TXQPCTR1HL RSCAN0.TXQPCTR1.UINT8[HL]
    3270 #define RSCAN0TXQPCTR1HH RSCAN0.TXQPCTR1.UINT8[HH]
    3271 #define RSCAN0TXQPCTR2 RSCAN0.TXQPCTR2.UINT32
    3272 #define RSCAN0TXQPCTR2L RSCAN0.TXQPCTR2.UINT16[L]
    3273 #define RSCAN0TXQPCTR2LL RSCAN0.TXQPCTR2.UINT8[LL]
    3274 #define RSCAN0TXQPCTR2LH RSCAN0.TXQPCTR2.UINT8[LH]
    3275 #define RSCAN0TXQPCTR2H RSCAN0.TXQPCTR2.UINT16[H]
    3276 #define RSCAN0TXQPCTR2HL RSCAN0.TXQPCTR2.UINT8[HL]
    3277 #define RSCAN0TXQPCTR2HH RSCAN0.TXQPCTR2.UINT8[HH]
    3278 #define RSCAN0TXQPCTR3 RSCAN0.TXQPCTR3.UINT32
    3279 #define RSCAN0TXQPCTR3L RSCAN0.TXQPCTR3.UINT16[L]
    3280 #define RSCAN0TXQPCTR3LL RSCAN0.TXQPCTR3.UINT8[LL]
    3281 #define RSCAN0TXQPCTR3LH RSCAN0.TXQPCTR3.UINT8[LH]
    3282 #define RSCAN0TXQPCTR3H RSCAN0.TXQPCTR3.UINT16[H]
    3283 #define RSCAN0TXQPCTR3HL RSCAN0.TXQPCTR3.UINT8[HL]
    3284 #define RSCAN0TXQPCTR3HH RSCAN0.TXQPCTR3.UINT8[HH]
    3285 #define RSCAN0TXQPCTR4 RSCAN0.TXQPCTR4.UINT32
    3286 #define RSCAN0TXQPCTR4L RSCAN0.TXQPCTR4.UINT16[L]
    3287 #define RSCAN0TXQPCTR4LL RSCAN0.TXQPCTR4.UINT8[LL]
    3288 #define RSCAN0TXQPCTR4LH RSCAN0.TXQPCTR4.UINT8[LH]
    3289 #define RSCAN0TXQPCTR4H RSCAN0.TXQPCTR4.UINT16[H]
    3290 #define RSCAN0TXQPCTR4HL RSCAN0.TXQPCTR4.UINT8[HL]
    3291 #define RSCAN0TXQPCTR4HH RSCAN0.TXQPCTR4.UINT8[HH]
    3292 #define RSCAN0THLCC0 RSCAN0.THLCC0.UINT32
    3293 #define RSCAN0THLCC0L RSCAN0.THLCC0.UINT16[L]
    3294 #define RSCAN0THLCC0LL RSCAN0.THLCC0.UINT8[LL]
    3295 #define RSCAN0THLCC0LH RSCAN0.THLCC0.UINT8[LH]
    3296 #define RSCAN0THLCC0H RSCAN0.THLCC0.UINT16[H]
    3297 #define RSCAN0THLCC0HL RSCAN0.THLCC0.UINT8[HL]
    3298 #define RSCAN0THLCC0HH RSCAN0.THLCC0.UINT8[HH]
    3299 #define RSCAN0THLCC1 RSCAN0.THLCC1.UINT32
    3300 #define RSCAN0THLCC1L RSCAN0.THLCC1.UINT16[L]
    3301 #define RSCAN0THLCC1LL RSCAN0.THLCC1.UINT8[LL]
    3302 #define RSCAN0THLCC1LH RSCAN0.THLCC1.UINT8[LH]
    3303 #define RSCAN0THLCC1H RSCAN0.THLCC1.UINT16[H]
    3304 #define RSCAN0THLCC1HL RSCAN0.THLCC1.UINT8[HL]
    3305 #define RSCAN0THLCC1HH RSCAN0.THLCC1.UINT8[HH]
    3306 #define RSCAN0THLCC2 RSCAN0.THLCC2.UINT32
    3307 #define RSCAN0THLCC2L RSCAN0.THLCC2.UINT16[L]
    3308 #define RSCAN0THLCC2LL RSCAN0.THLCC2.UINT8[LL]
    3309 #define RSCAN0THLCC2LH RSCAN0.THLCC2.UINT8[LH]
    3310 #define RSCAN0THLCC2H RSCAN0.THLCC2.UINT16[H]
    3311 #define RSCAN0THLCC2HL RSCAN0.THLCC2.UINT8[HL]
    3312 #define RSCAN0THLCC2HH RSCAN0.THLCC2.UINT8[HH]
    3313 #define RSCAN0THLCC3 RSCAN0.THLCC3.UINT32
    3314 #define RSCAN0THLCC3L RSCAN0.THLCC3.UINT16[L]
    3315 #define RSCAN0THLCC3LL RSCAN0.THLCC3.UINT8[LL]
    3316 #define RSCAN0THLCC3LH RSCAN0.THLCC3.UINT8[LH]
    3317 #define RSCAN0THLCC3H RSCAN0.THLCC3.UINT16[H]
    3318 #define RSCAN0THLCC3HL RSCAN0.THLCC3.UINT8[HL]
    3319 #define RSCAN0THLCC3HH RSCAN0.THLCC3.UINT8[HH]
    3320 #define RSCAN0THLCC4 RSCAN0.THLCC4.UINT32
    3321 #define RSCAN0THLCC4L RSCAN0.THLCC4.UINT16[L]
    3322 #define RSCAN0THLCC4LL RSCAN0.THLCC4.UINT8[LL]
    3323 #define RSCAN0THLCC4LH RSCAN0.THLCC4.UINT8[LH]
    3324 #define RSCAN0THLCC4H RSCAN0.THLCC4.UINT16[H]
    3325 #define RSCAN0THLCC4HL RSCAN0.THLCC4.UINT8[HL]
    3326 #define RSCAN0THLCC4HH RSCAN0.THLCC4.UINT8[HH]
    3327 #define RSCAN0THLSTS0 RSCAN0.THLSTS0.UINT32
    3328 #define RSCAN0THLSTS0L RSCAN0.THLSTS0.UINT16[L]
    3329 #define RSCAN0THLSTS0LL RSCAN0.THLSTS0.UINT8[LL]
    3330 #define RSCAN0THLSTS0LH RSCAN0.THLSTS0.UINT8[LH]
    3331 #define RSCAN0THLSTS0H RSCAN0.THLSTS0.UINT16[H]
    3332 #define RSCAN0THLSTS0HL RSCAN0.THLSTS0.UINT8[HL]
    3333 #define RSCAN0THLSTS0HH RSCAN0.THLSTS0.UINT8[HH]
    3334 #define RSCAN0THLSTS1 RSCAN0.THLSTS1.UINT32
    3335 #define RSCAN0THLSTS1L RSCAN0.THLSTS1.UINT16[L]
    3336 #define RSCAN0THLSTS1LL RSCAN0.THLSTS1.UINT8[LL]
    3337 #define RSCAN0THLSTS1LH RSCAN0.THLSTS1.UINT8[LH]
    3338 #define RSCAN0THLSTS1H RSCAN0.THLSTS1.UINT16[H]
    3339 #define RSCAN0THLSTS1HL RSCAN0.THLSTS1.UINT8[HL]
    3340 #define RSCAN0THLSTS1HH RSCAN0.THLSTS1.UINT8[HH]
    3341 #define RSCAN0THLSTS2 RSCAN0.THLSTS2.UINT32
    3342 #define RSCAN0THLSTS2L RSCAN0.THLSTS2.UINT16[L]
    3343 #define RSCAN0THLSTS2LL RSCAN0.THLSTS2.UINT8[LL]
    3344 #define RSCAN0THLSTS2LH RSCAN0.THLSTS2.UINT8[LH]
    3345 #define RSCAN0THLSTS2H RSCAN0.THLSTS2.UINT16[H]
    3346 #define RSCAN0THLSTS2HL RSCAN0.THLSTS2.UINT8[HL]
    3347 #define RSCAN0THLSTS2HH RSCAN0.THLSTS2.UINT8[HH]
    3348 #define RSCAN0THLSTS3 RSCAN0.THLSTS3.UINT32
    3349 #define RSCAN0THLSTS3L RSCAN0.THLSTS3.UINT16[L]
    3350 #define RSCAN0THLSTS3LL RSCAN0.THLSTS3.UINT8[LL]
    3351 #define RSCAN0THLSTS3LH RSCAN0.THLSTS3.UINT8[LH]
    3352 #define RSCAN0THLSTS3H RSCAN0.THLSTS3.UINT16[H]
    3353 #define RSCAN0THLSTS3HL RSCAN0.THLSTS3.UINT8[HL]
    3354 #define RSCAN0THLSTS3HH RSCAN0.THLSTS3.UINT8[HH]
    3355 #define RSCAN0THLSTS4 RSCAN0.THLSTS4.UINT32
    3356 #define RSCAN0THLSTS4L RSCAN0.THLSTS4.UINT16[L]
    3357 #define RSCAN0THLSTS4LL RSCAN0.THLSTS4.UINT8[LL]
    3358 #define RSCAN0THLSTS4LH RSCAN0.THLSTS4.UINT8[LH]
    3359 #define RSCAN0THLSTS4H RSCAN0.THLSTS4.UINT16[H]
    3360 #define RSCAN0THLSTS4HL RSCAN0.THLSTS4.UINT8[HL]
    3361 #define RSCAN0THLSTS4HH RSCAN0.THLSTS4.UINT8[HH]
    3362 #define RSCAN0THLPCTR0 RSCAN0.THLPCTR0.UINT32
    3363 #define RSCAN0THLPCTR0L RSCAN0.THLPCTR0.UINT16[L]
    3364 #define RSCAN0THLPCTR0LL RSCAN0.THLPCTR0.UINT8[LL]
    3365 #define RSCAN0THLPCTR0LH RSCAN0.THLPCTR0.UINT8[LH]
    3366 #define RSCAN0THLPCTR0H RSCAN0.THLPCTR0.UINT16[H]
    3367 #define RSCAN0THLPCTR0HL RSCAN0.THLPCTR0.UINT8[HL]
    3368 #define RSCAN0THLPCTR0HH RSCAN0.THLPCTR0.UINT8[HH]
    3369 #define RSCAN0THLPCTR1 RSCAN0.THLPCTR1.UINT32
    3370 #define RSCAN0THLPCTR1L RSCAN0.THLPCTR1.UINT16[L]
    3371 #define RSCAN0THLPCTR1LL RSCAN0.THLPCTR1.UINT8[LL]
    3372 #define RSCAN0THLPCTR1LH RSCAN0.THLPCTR1.UINT8[LH]
    3373 #define RSCAN0THLPCTR1H RSCAN0.THLPCTR1.UINT16[H]
    3374 #define RSCAN0THLPCTR1HL RSCAN0.THLPCTR1.UINT8[HL]
    3375 #define RSCAN0THLPCTR1HH RSCAN0.THLPCTR1.UINT8[HH]
    3376 #define RSCAN0THLPCTR2 RSCAN0.THLPCTR2.UINT32
    3377 #define RSCAN0THLPCTR2L RSCAN0.THLPCTR2.UINT16[L]
    3378 #define RSCAN0THLPCTR2LL RSCAN0.THLPCTR2.UINT8[LL]
    3379 #define RSCAN0THLPCTR2LH RSCAN0.THLPCTR2.UINT8[LH]
    3380 #define RSCAN0THLPCTR2H RSCAN0.THLPCTR2.UINT16[H]
    3381 #define RSCAN0THLPCTR2HL RSCAN0.THLPCTR2.UINT8[HL]
    3382 #define RSCAN0THLPCTR2HH RSCAN0.THLPCTR2.UINT8[HH]
    3383 #define RSCAN0THLPCTR3 RSCAN0.THLPCTR3.UINT32
    3384 #define RSCAN0THLPCTR3L RSCAN0.THLPCTR3.UINT16[L]
    3385 #define RSCAN0THLPCTR3LL RSCAN0.THLPCTR3.UINT8[LL]
    3386 #define RSCAN0THLPCTR3LH RSCAN0.THLPCTR3.UINT8[LH]
    3387 #define RSCAN0THLPCTR3H RSCAN0.THLPCTR3.UINT16[H]
    3388 #define RSCAN0THLPCTR3HL RSCAN0.THLPCTR3.UINT8[HL]
    3389 #define RSCAN0THLPCTR3HH RSCAN0.THLPCTR3.UINT8[HH]
    3390 #define RSCAN0THLPCTR4 RSCAN0.THLPCTR4.UINT32
    3391 #define RSCAN0THLPCTR4L RSCAN0.THLPCTR4.UINT16[L]
    3392 #define RSCAN0THLPCTR4LL RSCAN0.THLPCTR4.UINT8[LL]
    3393 #define RSCAN0THLPCTR4LH RSCAN0.THLPCTR4.UINT8[LH]
    3394 #define RSCAN0THLPCTR4H RSCAN0.THLPCTR4.UINT16[H]
    3395 #define RSCAN0THLPCTR4HL RSCAN0.THLPCTR4.UINT8[HL]
    3396 #define RSCAN0THLPCTR4HH RSCAN0.THLPCTR4.UINT8[HH]
    3397 #define RSCAN0GTINTSTS0 RSCAN0.GTINTSTS0.UINT32
    3398 #define RSCAN0GTINTSTS0L RSCAN0.GTINTSTS0.UINT16[L]
    3399 #define RSCAN0GTINTSTS0LL RSCAN0.GTINTSTS0.UINT8[LL]
    3400 #define RSCAN0GTINTSTS0LH RSCAN0.GTINTSTS0.UINT8[LH]
    3401 #define RSCAN0GTINTSTS0H RSCAN0.GTINTSTS0.UINT16[H]
    3402 #define RSCAN0GTINTSTS0HL RSCAN0.GTINTSTS0.UINT8[HL]
    3403 #define RSCAN0GTINTSTS0HH RSCAN0.GTINTSTS0.UINT8[HH]
    3404 #define RSCAN0GTINTSTS1 RSCAN0.GTINTSTS1.UINT32
    3405 #define RSCAN0GTINTSTS1L RSCAN0.GTINTSTS1.UINT16[L]
    3406 #define RSCAN0GTINTSTS1LL RSCAN0.GTINTSTS1.UINT8[LL]
    3407 #define RSCAN0GTINTSTS1LH RSCAN0.GTINTSTS1.UINT8[LH]
    3408 #define RSCAN0GTINTSTS1H RSCAN0.GTINTSTS1.UINT16[H]
    3409 #define RSCAN0GTINTSTS1HL RSCAN0.GTINTSTS1.UINT8[HL]
    3410 #define RSCAN0GTINTSTS1HH RSCAN0.GTINTSTS1.UINT8[HH]
    3411 #define RSCAN0GTSTCFG RSCAN0.GTSTCFG.UINT32
    3412 #define RSCAN0GTSTCFGL RSCAN0.GTSTCFG.UINT16[L]
    3413 #define RSCAN0GTSTCFGLL RSCAN0.GTSTCFG.UINT8[LL]
    3414 #define RSCAN0GTSTCFGLH RSCAN0.GTSTCFG.UINT8[LH]
    3415 #define RSCAN0GTSTCFGH RSCAN0.GTSTCFG.UINT16[H]
    3416 #define RSCAN0GTSTCFGHL RSCAN0.GTSTCFG.UINT8[HL]
    3417 #define RSCAN0GTSTCFGHH RSCAN0.GTSTCFG.UINT8[HH]
    3418 #define RSCAN0GTSTCTR RSCAN0.GTSTCTR.UINT32
    3419 #define RSCAN0GTSTCTRL RSCAN0.GTSTCTR.UINT16[L]
    3420 #define RSCAN0GTSTCTRLL RSCAN0.GTSTCTR.UINT8[LL]
    3421 #define RSCAN0GTSTCTRLH RSCAN0.GTSTCTR.UINT8[LH]
    3422 #define RSCAN0GTSTCTRH RSCAN0.GTSTCTR.UINT16[H]
    3423 #define RSCAN0GTSTCTRHL RSCAN0.GTSTCTR.UINT8[HL]
    3424 #define RSCAN0GTSTCTRHH RSCAN0.GTSTCTR.UINT8[HH]
    3425 #define RSCAN0GLOCKK RSCAN0.GLOCKK.UINT32
    3426 #define RSCAN0GLOCKKL RSCAN0.GLOCKK.UINT16[L]
    3427 #define RSCAN0GLOCKKH RSCAN0.GLOCKK.UINT16[H]
    3428 #define RSCAN0GAFLID0 RSCAN0.GAFLID0.UINT32
    3429 #define RSCAN0GAFLID0L RSCAN0.GAFLID0.UINT16[L]
    3430 #define RSCAN0GAFLID0LL RSCAN0.GAFLID0.UINT8[LL]
    3431 #define RSCAN0GAFLID0LH RSCAN0.GAFLID0.UINT8[LH]
    3432 #define RSCAN0GAFLID0H RSCAN0.GAFLID0.UINT16[H]
    3433 #define RSCAN0GAFLID0HL RSCAN0.GAFLID0.UINT8[HL]
    3434 #define RSCAN0GAFLID0HH RSCAN0.GAFLID0.UINT8[HH]
    3435 #define RSCAN0GAFLM0 RSCAN0.GAFLM0.UINT32
    3436 #define RSCAN0GAFLM0L RSCAN0.GAFLM0.UINT16[L]
    3437 #define RSCAN0GAFLM0LL RSCAN0.GAFLM0.UINT8[LL]
    3438 #define RSCAN0GAFLM0LH RSCAN0.GAFLM0.UINT8[LH]
    3439 #define RSCAN0GAFLM0H RSCAN0.GAFLM0.UINT16[H]
    3440 #define RSCAN0GAFLM0HL RSCAN0.GAFLM0.UINT8[HL]
    3441 #define RSCAN0GAFLM0HH RSCAN0.GAFLM0.UINT8[HH]
    3442 #define RSCAN0GAFLP00 RSCAN0.GAFLP00.UINT32
    3443 #define RSCAN0GAFLP00L RSCAN0.GAFLP00.UINT16[L]
    3444 #define RSCAN0GAFLP00LL RSCAN0.GAFLP00.UINT8[LL]
    3445 #define RSCAN0GAFLP00LH RSCAN0.GAFLP00.UINT8[LH]
    3446 #define RSCAN0GAFLP00H RSCAN0.GAFLP00.UINT16[H]
    3447 #define RSCAN0GAFLP00HL RSCAN0.GAFLP00.UINT8[HL]
    3448 #define RSCAN0GAFLP00HH RSCAN0.GAFLP00.UINT8[HH]
    3449 #define RSCAN0GAFLP10 RSCAN0.GAFLP10.UINT32
    3450 #define RSCAN0GAFLP10L RSCAN0.GAFLP10.UINT16[L]
    3451 #define RSCAN0GAFLP10LL RSCAN0.GAFLP10.UINT8[LL]
    3452 #define RSCAN0GAFLP10LH RSCAN0.GAFLP10.UINT8[LH]
    3453 #define RSCAN0GAFLP10H RSCAN0.GAFLP10.UINT16[H]
    3454 #define RSCAN0GAFLP10HL RSCAN0.GAFLP10.UINT8[HL]
    3455 #define RSCAN0GAFLP10HH RSCAN0.GAFLP10.UINT8[HH]
    3456 #define RSCAN0GAFLID1 RSCAN0.GAFLID1.UINT32
    3457 #define RSCAN0GAFLID1L RSCAN0.GAFLID1.UINT16[L]
    3458 #define RSCAN0GAFLID1LL RSCAN0.GAFLID1.UINT8[LL]
    3459 #define RSCAN0GAFLID1LH RSCAN0.GAFLID1.UINT8[LH]
    3460 #define RSCAN0GAFLID1H RSCAN0.GAFLID1.UINT16[H]
    3461 #define RSCAN0GAFLID1HL RSCAN0.GAFLID1.UINT8[HL]
    3462 #define RSCAN0GAFLID1HH RSCAN0.GAFLID1.UINT8[HH]
    3463 #define RSCAN0GAFLM1 RSCAN0.GAFLM1.UINT32
    3464 #define RSCAN0GAFLM1L RSCAN0.GAFLM1.UINT16[L]
    3465 #define RSCAN0GAFLM1LL RSCAN0.GAFLM1.UINT8[LL]
    3466 #define RSCAN0GAFLM1LH RSCAN0.GAFLM1.UINT8[LH]
    3467 #define RSCAN0GAFLM1H RSCAN0.GAFLM1.UINT16[H]
    3468 #define RSCAN0GAFLM1HL RSCAN0.GAFLM1.UINT8[HL]
    3469 #define RSCAN0GAFLM1HH RSCAN0.GAFLM1.UINT8[HH]
    3470 #define RSCAN0GAFLP01 RSCAN0.GAFLP01.UINT32
    3471 #define RSCAN0GAFLP01L RSCAN0.GAFLP01.UINT16[L]
    3472 #define RSCAN0GAFLP01LL RSCAN0.GAFLP01.UINT8[LL]
    3473 #define RSCAN0GAFLP01LH RSCAN0.GAFLP01.UINT8[LH]
    3474 #define RSCAN0GAFLP01H RSCAN0.GAFLP01.UINT16[H]
    3475 #define RSCAN0GAFLP01HL RSCAN0.GAFLP01.UINT8[HL]
    3476 #define RSCAN0GAFLP01HH RSCAN0.GAFLP01.UINT8[HH]
    3477 #define RSCAN0GAFLP11 RSCAN0.GAFLP11.UINT32
    3478 #define RSCAN0GAFLP11L RSCAN0.GAFLP11.UINT16[L]
    3479 #define RSCAN0GAFLP11LL RSCAN0.GAFLP11.UINT8[LL]
    3480 #define RSCAN0GAFLP11LH RSCAN0.GAFLP11.UINT8[LH]
    3481 #define RSCAN0GAFLP11H RSCAN0.GAFLP11.UINT16[H]
    3482 #define RSCAN0GAFLP11HL RSCAN0.GAFLP11.UINT8[HL]
    3483 #define RSCAN0GAFLP11HH RSCAN0.GAFLP11.UINT8[HH]
    3484 #define RSCAN0GAFLID2 RSCAN0.GAFLID2.UINT32
    3485 #define RSCAN0GAFLID2L RSCAN0.GAFLID2.UINT16[L]
    3486 #define RSCAN0GAFLID2LL RSCAN0.GAFLID2.UINT8[LL]
    3487 #define RSCAN0GAFLID2LH RSCAN0.GAFLID2.UINT8[LH]
    3488 #define RSCAN0GAFLID2H RSCAN0.GAFLID2.UINT16[H]
    3489 #define RSCAN0GAFLID2HL RSCAN0.GAFLID2.UINT8[HL]
    3490 #define RSCAN0GAFLID2HH RSCAN0.GAFLID2.UINT8[HH]
    3491 #define RSCAN0GAFLM2 RSCAN0.GAFLM2.UINT32
    3492 #define RSCAN0GAFLM2L RSCAN0.GAFLM2.UINT16[L]
    3493 #define RSCAN0GAFLM2LL RSCAN0.GAFLM2.UINT8[LL]
    3494 #define RSCAN0GAFLM2LH RSCAN0.GAFLM2.UINT8[LH]
    3495 #define RSCAN0GAFLM2H RSCAN0.GAFLM2.UINT16[H]
    3496 #define RSCAN0GAFLM2HL RSCAN0.GAFLM2.UINT8[HL]
    3497 #define RSCAN0GAFLM2HH RSCAN0.GAFLM2.UINT8[HH]
    3498 #define RSCAN0GAFLP02 RSCAN0.GAFLP02.UINT32
    3499 #define RSCAN0GAFLP02L RSCAN0.GAFLP02.UINT16[L]
    3500 #define RSCAN0GAFLP02LL RSCAN0.GAFLP02.UINT8[LL]
    3501 #define RSCAN0GAFLP02LH RSCAN0.GAFLP02.UINT8[LH]
    3502 #define RSCAN0GAFLP02H RSCAN0.GAFLP02.UINT16[H]
    3503 #define RSCAN0GAFLP02HL RSCAN0.GAFLP02.UINT8[HL]
    3504 #define RSCAN0GAFLP02HH RSCAN0.GAFLP02.UINT8[HH]
    3505 #define RSCAN0GAFLP12 RSCAN0.GAFLP12.UINT32
    3506 #define RSCAN0GAFLP12L RSCAN0.GAFLP12.UINT16[L]
    3507 #define RSCAN0GAFLP12LL RSCAN0.GAFLP12.UINT8[LL]
    3508 #define RSCAN0GAFLP12LH RSCAN0.GAFLP12.UINT8[LH]
    3509 #define RSCAN0GAFLP12H RSCAN0.GAFLP12.UINT16[H]
    3510 #define RSCAN0GAFLP12HL RSCAN0.GAFLP12.UINT8[HL]
    3511 #define RSCAN0GAFLP12HH RSCAN0.GAFLP12.UINT8[HH]
    3512 #define RSCAN0GAFLID3 RSCAN0.GAFLID3.UINT32
    3513 #define RSCAN0GAFLID3L RSCAN0.GAFLID3.UINT16[L]
    3514 #define RSCAN0GAFLID3LL RSCAN0.GAFLID3.UINT8[LL]
    3515 #define RSCAN0GAFLID3LH RSCAN0.GAFLID3.UINT8[LH]
    3516 #define RSCAN0GAFLID3H RSCAN0.GAFLID3.UINT16[H]
    3517 #define RSCAN0GAFLID3HL RSCAN0.GAFLID3.UINT8[HL]
    3518 #define RSCAN0GAFLID3HH RSCAN0.GAFLID3.UINT8[HH]
    3519 #define RSCAN0GAFLM3 RSCAN0.GAFLM3.UINT32
    3520 #define RSCAN0GAFLM3L RSCAN0.GAFLM3.UINT16[L]
    3521 #define RSCAN0GAFLM3LL RSCAN0.GAFLM3.UINT8[LL]
    3522 #define RSCAN0GAFLM3LH RSCAN0.GAFLM3.UINT8[LH]
    3523 #define RSCAN0GAFLM3H RSCAN0.GAFLM3.UINT16[H]
    3524 #define RSCAN0GAFLM3HL RSCAN0.GAFLM3.UINT8[HL]
    3525 #define RSCAN0GAFLM3HH RSCAN0.GAFLM3.UINT8[HH]
    3526 #define RSCAN0GAFLP03 RSCAN0.GAFLP03.UINT32
    3527 #define RSCAN0GAFLP03L RSCAN0.GAFLP03.UINT16[L]
    3528 #define RSCAN0GAFLP03LL RSCAN0.GAFLP03.UINT8[LL]
    3529 #define RSCAN0GAFLP03LH RSCAN0.GAFLP03.UINT8[LH]
    3530 #define RSCAN0GAFLP03H RSCAN0.GAFLP03.UINT16[H]
    3531 #define RSCAN0GAFLP03HL RSCAN0.GAFLP03.UINT8[HL]
    3532 #define RSCAN0GAFLP03HH RSCAN0.GAFLP03.UINT8[HH]
    3533 #define RSCAN0GAFLP13 RSCAN0.GAFLP13.UINT32
    3534 #define RSCAN0GAFLP13L RSCAN0.GAFLP13.UINT16[L]
    3535 #define RSCAN0GAFLP13LL RSCAN0.GAFLP13.UINT8[LL]
    3536 #define RSCAN0GAFLP13LH RSCAN0.GAFLP13.UINT8[LH]
    3537 #define RSCAN0GAFLP13H RSCAN0.GAFLP13.UINT16[H]
    3538 #define RSCAN0GAFLP13HL RSCAN0.GAFLP13.UINT8[HL]
    3539 #define RSCAN0GAFLP13HH RSCAN0.GAFLP13.UINT8[HH]
    3540 #define RSCAN0GAFLID4 RSCAN0.GAFLID4.UINT32
    3541 #define RSCAN0GAFLID4L RSCAN0.GAFLID4.UINT16[L]
    3542 #define RSCAN0GAFLID4LL RSCAN0.GAFLID4.UINT8[LL]
    3543 #define RSCAN0GAFLID4LH RSCAN0.GAFLID4.UINT8[LH]
    3544 #define RSCAN0GAFLID4H RSCAN0.GAFLID4.UINT16[H]
    3545 #define RSCAN0GAFLID4HL RSCAN0.GAFLID4.UINT8[HL]
    3546 #define RSCAN0GAFLID4HH RSCAN0.GAFLID4.UINT8[HH]
    3547 #define RSCAN0GAFLM4 RSCAN0.GAFLM4.UINT32
    3548 #define RSCAN0GAFLM4L RSCAN0.GAFLM4.UINT16[L]
    3549 #define RSCAN0GAFLM4LL RSCAN0.GAFLM4.UINT8[LL]
    3550 #define RSCAN0GAFLM4LH RSCAN0.GAFLM4.UINT8[LH]
    3551 #define RSCAN0GAFLM4H RSCAN0.GAFLM4.UINT16[H]
    3552 #define RSCAN0GAFLM4HL RSCAN0.GAFLM4.UINT8[HL]
    3553 #define RSCAN0GAFLM4HH RSCAN0.GAFLM4.UINT8[HH]
    3554 #define RSCAN0GAFLP04 RSCAN0.GAFLP04.UINT32
    3555 #define RSCAN0GAFLP04L RSCAN0.GAFLP04.UINT16[L]
    3556 #define RSCAN0GAFLP04LL RSCAN0.GAFLP04.UINT8[LL]
    3557 #define RSCAN0GAFLP04LH RSCAN0.GAFLP04.UINT8[LH]
    3558 #define RSCAN0GAFLP04H RSCAN0.GAFLP04.UINT16[H]
    3559 #define RSCAN0GAFLP04HL RSCAN0.GAFLP04.UINT8[HL]
    3560 #define RSCAN0GAFLP04HH RSCAN0.GAFLP04.UINT8[HH]
    3561 #define RSCAN0GAFLP14 RSCAN0.GAFLP14.UINT32
    3562 #define RSCAN0GAFLP14L RSCAN0.GAFLP14.UINT16[L]
    3563 #define RSCAN0GAFLP14LL RSCAN0.GAFLP14.UINT8[LL]
    3564 #define RSCAN0GAFLP14LH RSCAN0.GAFLP14.UINT8[LH]
    3565 #define RSCAN0GAFLP14H RSCAN0.GAFLP14.UINT16[H]
    3566 #define RSCAN0GAFLP14HL RSCAN0.GAFLP14.UINT8[HL]
    3567 #define RSCAN0GAFLP14HH RSCAN0.GAFLP14.UINT8[HH]
    3568 #define RSCAN0GAFLID5 RSCAN0.GAFLID5.UINT32
    3569 #define RSCAN0GAFLID5L RSCAN0.GAFLID5.UINT16[L]
    3570 #define RSCAN0GAFLID5LL RSCAN0.GAFLID5.UINT8[LL]
    3571 #define RSCAN0GAFLID5LH RSCAN0.GAFLID5.UINT8[LH]
    3572 #define RSCAN0GAFLID5H RSCAN0.GAFLID5.UINT16[H]
    3573 #define RSCAN0GAFLID5HL RSCAN0.GAFLID5.UINT8[HL]
    3574 #define RSCAN0GAFLID5HH RSCAN0.GAFLID5.UINT8[HH]
    3575 #define RSCAN0GAFLM5 RSCAN0.GAFLM5.UINT32
    3576 #define RSCAN0GAFLM5L RSCAN0.GAFLM5.UINT16[L]
    3577 #define RSCAN0GAFLM5LL RSCAN0.GAFLM5.UINT8[LL]
    3578 #define RSCAN0GAFLM5LH RSCAN0.GAFLM5.UINT8[LH]
    3579 #define RSCAN0GAFLM5H RSCAN0.GAFLM5.UINT16[H]
    3580 #define RSCAN0GAFLM5HL RSCAN0.GAFLM5.UINT8[HL]
    3581 #define RSCAN0GAFLM5HH RSCAN0.GAFLM5.UINT8[HH]
    3582 #define RSCAN0GAFLP05 RSCAN0.GAFLP05.UINT32
    3583 #define RSCAN0GAFLP05L RSCAN0.GAFLP05.UINT16[L]
    3584 #define RSCAN0GAFLP05LL RSCAN0.GAFLP05.UINT8[LL]
    3585 #define RSCAN0GAFLP05LH RSCAN0.GAFLP05.UINT8[LH]
    3586 #define RSCAN0GAFLP05H RSCAN0.GAFLP05.UINT16[H]
    3587 #define RSCAN0GAFLP05HL RSCAN0.GAFLP05.UINT8[HL]
    3588 #define RSCAN0GAFLP05HH RSCAN0.GAFLP05.UINT8[HH]
    3589 #define RSCAN0GAFLP15 RSCAN0.GAFLP15.UINT32
    3590 #define RSCAN0GAFLP15L RSCAN0.GAFLP15.UINT16[L]
    3591 #define RSCAN0GAFLP15LL RSCAN0.GAFLP15.UINT8[LL]
    3592 #define RSCAN0GAFLP15LH RSCAN0.GAFLP15.UINT8[LH]
    3593 #define RSCAN0GAFLP15H RSCAN0.GAFLP15.UINT16[H]
    3594 #define RSCAN0GAFLP15HL RSCAN0.GAFLP15.UINT8[HL]
    3595 #define RSCAN0GAFLP15HH RSCAN0.GAFLP15.UINT8[HH]
    3596 #define RSCAN0GAFLID6 RSCAN0.GAFLID6.UINT32
    3597 #define RSCAN0GAFLID6L RSCAN0.GAFLID6.UINT16[L]
    3598 #define RSCAN0GAFLID6LL RSCAN0.GAFLID6.UINT8[LL]
    3599 #define RSCAN0GAFLID6LH RSCAN0.GAFLID6.UINT8[LH]
    3600 #define RSCAN0GAFLID6H RSCAN0.GAFLID6.UINT16[H]
    3601 #define RSCAN0GAFLID6HL RSCAN0.GAFLID6.UINT8[HL]
    3602 #define RSCAN0GAFLID6HH RSCAN0.GAFLID6.UINT8[HH]
    3603 #define RSCAN0GAFLM6 RSCAN0.GAFLM6.UINT32
    3604 #define RSCAN0GAFLM6L RSCAN0.GAFLM6.UINT16[L]
    3605 #define RSCAN0GAFLM6LL RSCAN0.GAFLM6.UINT8[LL]
    3606 #define RSCAN0GAFLM6LH RSCAN0.GAFLM6.UINT8[LH]
    3607 #define RSCAN0GAFLM6H RSCAN0.GAFLM6.UINT16[H]
    3608 #define RSCAN0GAFLM6HL RSCAN0.GAFLM6.UINT8[HL]
    3609 #define RSCAN0GAFLM6HH RSCAN0.GAFLM6.UINT8[HH]
    3610 #define RSCAN0GAFLP06 RSCAN0.GAFLP06.UINT32
    3611 #define RSCAN0GAFLP06L RSCAN0.GAFLP06.UINT16[L]
    3612 #define RSCAN0GAFLP06LL RSCAN0.GAFLP06.UINT8[LL]
    3613 #define RSCAN0GAFLP06LH RSCAN0.GAFLP06.UINT8[LH]
    3614 #define RSCAN0GAFLP06H RSCAN0.GAFLP06.UINT16[H]
    3615 #define RSCAN0GAFLP06HL RSCAN0.GAFLP06.UINT8[HL]
    3616 #define RSCAN0GAFLP06HH RSCAN0.GAFLP06.UINT8[HH]
    3617 #define RSCAN0GAFLP16 RSCAN0.GAFLP16.UINT32
    3618 #define RSCAN0GAFLP16L RSCAN0.GAFLP16.UINT16[L]
    3619 #define RSCAN0GAFLP16LL RSCAN0.GAFLP16.UINT8[LL]
    3620 #define RSCAN0GAFLP16LH RSCAN0.GAFLP16.UINT8[LH]
    3621 #define RSCAN0GAFLP16H RSCAN0.GAFLP16.UINT16[H]
    3622 #define RSCAN0GAFLP16HL RSCAN0.GAFLP16.UINT8[HL]
    3623 #define RSCAN0GAFLP16HH RSCAN0.GAFLP16.UINT8[HH]
    3624 #define RSCAN0GAFLID7 RSCAN0.GAFLID7.UINT32
    3625 #define RSCAN0GAFLID7L RSCAN0.GAFLID7.UINT16[L]
    3626 #define RSCAN0GAFLID7LL RSCAN0.GAFLID7.UINT8[LL]
    3627 #define RSCAN0GAFLID7LH RSCAN0.GAFLID7.UINT8[LH]
    3628 #define RSCAN0GAFLID7H RSCAN0.GAFLID7.UINT16[H]
    3629 #define RSCAN0GAFLID7HL RSCAN0.GAFLID7.UINT8[HL]
    3630 #define RSCAN0GAFLID7HH RSCAN0.GAFLID7.UINT8[HH]
    3631 #define RSCAN0GAFLM7 RSCAN0.GAFLM7.UINT32
    3632 #define RSCAN0GAFLM7L RSCAN0.GAFLM7.UINT16[L]
    3633 #define RSCAN0GAFLM7LL RSCAN0.GAFLM7.UINT8[LL]
    3634 #define RSCAN0GAFLM7LH RSCAN0.GAFLM7.UINT8[LH]
    3635 #define RSCAN0GAFLM7H RSCAN0.GAFLM7.UINT16[H]
    3636 #define RSCAN0GAFLM7HL RSCAN0.GAFLM7.UINT8[HL]
    3637 #define RSCAN0GAFLM7HH RSCAN0.GAFLM7.UINT8[HH]
    3638 #define RSCAN0GAFLP07 RSCAN0.GAFLP07.UINT32
    3639 #define RSCAN0GAFLP07L RSCAN0.GAFLP07.UINT16[L]
    3640 #define RSCAN0GAFLP07LL RSCAN0.GAFLP07.UINT8[LL]
    3641 #define RSCAN0GAFLP07LH RSCAN0.GAFLP07.UINT8[LH]
    3642 #define RSCAN0GAFLP07H RSCAN0.GAFLP07.UINT16[H]
    3643 #define RSCAN0GAFLP07HL RSCAN0.GAFLP07.UINT8[HL]
    3644 #define RSCAN0GAFLP07HH RSCAN0.GAFLP07.UINT8[HH]
    3645 #define RSCAN0GAFLP17 RSCAN0.GAFLP17.UINT32
    3646 #define RSCAN0GAFLP17L RSCAN0.GAFLP17.UINT16[L]
    3647 #define RSCAN0GAFLP17LL RSCAN0.GAFLP17.UINT8[LL]
    3648 #define RSCAN0GAFLP17LH RSCAN0.GAFLP17.UINT8[LH]
    3649 #define RSCAN0GAFLP17H RSCAN0.GAFLP17.UINT16[H]
    3650 #define RSCAN0GAFLP17HL RSCAN0.GAFLP17.UINT8[HL]
    3651 #define RSCAN0GAFLP17HH RSCAN0.GAFLP17.UINT8[HH]
    3652 #define RSCAN0GAFLID8 RSCAN0.GAFLID8.UINT32
    3653 #define RSCAN0GAFLID8L RSCAN0.GAFLID8.UINT16[L]
    3654 #define RSCAN0GAFLID8LL RSCAN0.GAFLID8.UINT8[LL]
    3655 #define RSCAN0GAFLID8LH RSCAN0.GAFLID8.UINT8[LH]
    3656 #define RSCAN0GAFLID8H RSCAN0.GAFLID8.UINT16[H]
    3657 #define RSCAN0GAFLID8HL RSCAN0.GAFLID8.UINT8[HL]
    3658 #define RSCAN0GAFLID8HH RSCAN0.GAFLID8.UINT8[HH]
    3659 #define RSCAN0GAFLM8 RSCAN0.GAFLM8.UINT32
    3660 #define RSCAN0GAFLM8L RSCAN0.GAFLM8.UINT16[L]
    3661 #define RSCAN0GAFLM8LL RSCAN0.GAFLM8.UINT8[LL]
    3662 #define RSCAN0GAFLM8LH RSCAN0.GAFLM8.UINT8[LH]
    3663 #define RSCAN0GAFLM8H RSCAN0.GAFLM8.UINT16[H]
    3664 #define RSCAN0GAFLM8HL RSCAN0.GAFLM8.UINT8[HL]
    3665 #define RSCAN0GAFLM8HH RSCAN0.GAFLM8.UINT8[HH]
    3666 #define RSCAN0GAFLP08 RSCAN0.GAFLP08.UINT32
    3667 #define RSCAN0GAFLP08L RSCAN0.GAFLP08.UINT16[L]
    3668 #define RSCAN0GAFLP08LL RSCAN0.GAFLP08.UINT8[LL]
    3669 #define RSCAN0GAFLP08LH RSCAN0.GAFLP08.UINT8[LH]
    3670 #define RSCAN0GAFLP08H RSCAN0.GAFLP08.UINT16[H]
    3671 #define RSCAN0GAFLP08HL RSCAN0.GAFLP08.UINT8[HL]
    3672 #define RSCAN0GAFLP08HH RSCAN0.GAFLP08.UINT8[HH]
    3673 #define RSCAN0GAFLP18 RSCAN0.GAFLP18.UINT32
    3674 #define RSCAN0GAFLP18L RSCAN0.GAFLP18.UINT16[L]
    3675 #define RSCAN0GAFLP18LL RSCAN0.GAFLP18.UINT8[LL]
    3676 #define RSCAN0GAFLP18LH RSCAN0.GAFLP18.UINT8[LH]
    3677 #define RSCAN0GAFLP18H RSCAN0.GAFLP18.UINT16[H]
    3678 #define RSCAN0GAFLP18HL RSCAN0.GAFLP18.UINT8[HL]
    3679 #define RSCAN0GAFLP18HH RSCAN0.GAFLP18.UINT8[HH]
    3680 #define RSCAN0GAFLID9 RSCAN0.GAFLID9.UINT32
    3681 #define RSCAN0GAFLID9L RSCAN0.GAFLID9.UINT16[L]
    3682 #define RSCAN0GAFLID9LL RSCAN0.GAFLID9.UINT8[LL]
    3683 #define RSCAN0GAFLID9LH RSCAN0.GAFLID9.UINT8[LH]
    3684 #define RSCAN0GAFLID9H RSCAN0.GAFLID9.UINT16[H]
    3685 #define RSCAN0GAFLID9HL RSCAN0.GAFLID9.UINT8[HL]
    3686 #define RSCAN0GAFLID9HH RSCAN0.GAFLID9.UINT8[HH]
    3687 #define RSCAN0GAFLM9 RSCAN0.GAFLM9.UINT32
    3688 #define RSCAN0GAFLM9L RSCAN0.GAFLM9.UINT16[L]
    3689 #define RSCAN0GAFLM9LL RSCAN0.GAFLM9.UINT8[LL]
    3690 #define RSCAN0GAFLM9LH RSCAN0.GAFLM9.UINT8[LH]
    3691 #define RSCAN0GAFLM9H RSCAN0.GAFLM9.UINT16[H]
    3692 #define RSCAN0GAFLM9HL RSCAN0.GAFLM9.UINT8[HL]
    3693 #define RSCAN0GAFLM9HH RSCAN0.GAFLM9.UINT8[HH]
    3694 #define RSCAN0GAFLP09 RSCAN0.GAFLP09.UINT32
    3695 #define RSCAN0GAFLP09L RSCAN0.GAFLP09.UINT16[L]
    3696 #define RSCAN0GAFLP09LL RSCAN0.GAFLP09.UINT8[LL]
    3697 #define RSCAN0GAFLP09LH RSCAN0.GAFLP09.UINT8[LH]
    3698 #define RSCAN0GAFLP09H RSCAN0.GAFLP09.UINT16[H]
    3699 #define RSCAN0GAFLP09HL RSCAN0.GAFLP09.UINT8[HL]
    3700 #define RSCAN0GAFLP09HH RSCAN0.GAFLP09.UINT8[HH]
    3701 #define RSCAN0GAFLP19 RSCAN0.GAFLP19.UINT32
    3702 #define RSCAN0GAFLP19L RSCAN0.GAFLP19.UINT16[L]
    3703 #define RSCAN0GAFLP19LL RSCAN0.GAFLP19.UINT8[LL]
    3704 #define RSCAN0GAFLP19LH RSCAN0.GAFLP19.UINT8[LH]
    3705 #define RSCAN0GAFLP19H RSCAN0.GAFLP19.UINT16[H]
    3706 #define RSCAN0GAFLP19HL RSCAN0.GAFLP19.UINT8[HL]
    3707 #define RSCAN0GAFLP19HH RSCAN0.GAFLP19.UINT8[HH]
    3708 #define RSCAN0GAFLID10 RSCAN0.GAFLID10.UINT32
    3709 #define RSCAN0GAFLID10L RSCAN0.GAFLID10.UINT16[L]
    3710 #define RSCAN0GAFLID10LL RSCAN0.GAFLID10.UINT8[LL]
    3711 #define RSCAN0GAFLID10LH RSCAN0.GAFLID10.UINT8[LH]
    3712 #define RSCAN0GAFLID10H RSCAN0.GAFLID10.UINT16[H]
    3713 #define RSCAN0GAFLID10HL RSCAN0.GAFLID10.UINT8[HL]
    3714 #define RSCAN0GAFLID10HH RSCAN0.GAFLID10.UINT8[HH]
    3715 #define RSCAN0GAFLM10 RSCAN0.GAFLM10.UINT32
    3716 #define RSCAN0GAFLM10L RSCAN0.GAFLM10.UINT16[L]
    3717 #define RSCAN0GAFLM10LL RSCAN0.GAFLM10.UINT8[LL]
    3718 #define RSCAN0GAFLM10LH RSCAN0.GAFLM10.UINT8[LH]
    3719 #define RSCAN0GAFLM10H RSCAN0.GAFLM10.UINT16[H]
    3720 #define RSCAN0GAFLM10HL RSCAN0.GAFLM10.UINT8[HL]
    3721 #define RSCAN0GAFLM10HH RSCAN0.GAFLM10.UINT8[HH]
    3722 #define RSCAN0GAFLP010 RSCAN0.GAFLP010.UINT32
    3723 #define RSCAN0GAFLP010L RSCAN0.GAFLP010.UINT16[L]
    3724 #define RSCAN0GAFLP010LL RSCAN0.GAFLP010.UINT8[LL]
    3725 #define RSCAN0GAFLP010LH RSCAN0.GAFLP010.UINT8[LH]
    3726 #define RSCAN0GAFLP010H RSCAN0.GAFLP010.UINT16[H]
    3727 #define RSCAN0GAFLP010HL RSCAN0.GAFLP010.UINT8[HL]
    3728 #define RSCAN0GAFLP010HH RSCAN0.GAFLP010.UINT8[HH]
    3729 #define RSCAN0GAFLP110 RSCAN0.GAFLP110.UINT32
    3730 #define RSCAN0GAFLP110L RSCAN0.GAFLP110.UINT16[L]
    3731 #define RSCAN0GAFLP110LL RSCAN0.GAFLP110.UINT8[LL]
    3732 #define RSCAN0GAFLP110LH RSCAN0.GAFLP110.UINT8[LH]
    3733 #define RSCAN0GAFLP110H RSCAN0.GAFLP110.UINT16[H]
    3734 #define RSCAN0GAFLP110HL RSCAN0.GAFLP110.UINT8[HL]
    3735 #define RSCAN0GAFLP110HH RSCAN0.GAFLP110.UINT8[HH]
    3736 #define RSCAN0GAFLID11 RSCAN0.GAFLID11.UINT32
    3737 #define RSCAN0GAFLID11L RSCAN0.GAFLID11.UINT16[L]
    3738 #define RSCAN0GAFLID11LL RSCAN0.GAFLID11.UINT8[LL]
    3739 #define RSCAN0GAFLID11LH RSCAN0.GAFLID11.UINT8[LH]
    3740 #define RSCAN0GAFLID11H RSCAN0.GAFLID11.UINT16[H]
    3741 #define RSCAN0GAFLID11HL RSCAN0.GAFLID11.UINT8[HL]
    3742 #define RSCAN0GAFLID11HH RSCAN0.GAFLID11.UINT8[HH]
    3743 #define RSCAN0GAFLM11 RSCAN0.GAFLM11.UINT32
    3744 #define RSCAN0GAFLM11L RSCAN0.GAFLM11.UINT16[L]
    3745 #define RSCAN0GAFLM11LL RSCAN0.GAFLM11.UINT8[LL]
    3746 #define RSCAN0GAFLM11LH RSCAN0.GAFLM11.UINT8[LH]
    3747 #define RSCAN0GAFLM11H RSCAN0.GAFLM11.UINT16[H]
    3748 #define RSCAN0GAFLM11HL RSCAN0.GAFLM11.UINT8[HL]
    3749 #define RSCAN0GAFLM11HH RSCAN0.GAFLM11.UINT8[HH]
    3750 #define RSCAN0GAFLP011 RSCAN0.GAFLP011.UINT32
    3751 #define RSCAN0GAFLP011L RSCAN0.GAFLP011.UINT16[L]
    3752 #define RSCAN0GAFLP011LL RSCAN0.GAFLP011.UINT8[LL]
    3753 #define RSCAN0GAFLP011LH RSCAN0.GAFLP011.UINT8[LH]
    3754 #define RSCAN0GAFLP011H RSCAN0.GAFLP011.UINT16[H]
    3755 #define RSCAN0GAFLP011HL RSCAN0.GAFLP011.UINT8[HL]
    3756 #define RSCAN0GAFLP011HH RSCAN0.GAFLP011.UINT8[HH]
    3757 #define RSCAN0GAFLP111 RSCAN0.GAFLP111.UINT32
    3758 #define RSCAN0GAFLP111L RSCAN0.GAFLP111.UINT16[L]
    3759 #define RSCAN0GAFLP111LL RSCAN0.GAFLP111.UINT8[LL]
    3760 #define RSCAN0GAFLP111LH RSCAN0.GAFLP111.UINT8[LH]
    3761 #define RSCAN0GAFLP111H RSCAN0.GAFLP111.UINT16[H]
    3762 #define RSCAN0GAFLP111HL RSCAN0.GAFLP111.UINT8[HL]
    3763 #define RSCAN0GAFLP111HH RSCAN0.GAFLP111.UINT8[HH]
    3764 #define RSCAN0GAFLID12 RSCAN0.GAFLID12.UINT32
    3765 #define RSCAN0GAFLID12L RSCAN0.GAFLID12.UINT16[L]
    3766 #define RSCAN0GAFLID12LL RSCAN0.GAFLID12.UINT8[LL]
    3767 #define RSCAN0GAFLID12LH RSCAN0.GAFLID12.UINT8[LH]
    3768 #define RSCAN0GAFLID12H RSCAN0.GAFLID12.UINT16[H]
    3769 #define RSCAN0GAFLID12HL RSCAN0.GAFLID12.UINT8[HL]
    3770 #define RSCAN0GAFLID12HH RSCAN0.GAFLID12.UINT8[HH]
    3771 #define RSCAN0GAFLM12 RSCAN0.GAFLM12.UINT32
    3772 #define RSCAN0GAFLM12L RSCAN0.GAFLM12.UINT16[L]
    3773 #define RSCAN0GAFLM12LL RSCAN0.GAFLM12.UINT8[LL]
    3774 #define RSCAN0GAFLM12LH RSCAN0.GAFLM12.UINT8[LH]
    3775 #define RSCAN0GAFLM12H RSCAN0.GAFLM12.UINT16[H]
    3776 #define RSCAN0GAFLM12HL RSCAN0.GAFLM12.UINT8[HL]
    3777 #define RSCAN0GAFLM12HH RSCAN0.GAFLM12.UINT8[HH]
    3778 #define RSCAN0GAFLP012 RSCAN0.GAFLP012.UINT32
    3779 #define RSCAN0GAFLP012L RSCAN0.GAFLP012.UINT16[L]
    3780 #define RSCAN0GAFLP012LL RSCAN0.GAFLP012.UINT8[LL]
    3781 #define RSCAN0GAFLP012LH RSCAN0.GAFLP012.UINT8[LH]
    3782 #define RSCAN0GAFLP012H RSCAN0.GAFLP012.UINT16[H]
    3783 #define RSCAN0GAFLP012HL RSCAN0.GAFLP012.UINT8[HL]
    3784 #define RSCAN0GAFLP012HH RSCAN0.GAFLP012.UINT8[HH]
    3785 #define RSCAN0GAFLP112 RSCAN0.GAFLP112.UINT32
    3786 #define RSCAN0GAFLP112L RSCAN0.GAFLP112.UINT16[L]
    3787 #define RSCAN0GAFLP112LL RSCAN0.GAFLP112.UINT8[LL]
    3788 #define RSCAN0GAFLP112LH RSCAN0.GAFLP112.UINT8[LH]
    3789 #define RSCAN0GAFLP112H RSCAN0.GAFLP112.UINT16[H]
    3790 #define RSCAN0GAFLP112HL RSCAN0.GAFLP112.UINT8[HL]
    3791 #define RSCAN0GAFLP112HH RSCAN0.GAFLP112.UINT8[HH]
    3792 #define RSCAN0GAFLID13 RSCAN0.GAFLID13.UINT32
    3793 #define RSCAN0GAFLID13L RSCAN0.GAFLID13.UINT16[L]
    3794 #define RSCAN0GAFLID13LL RSCAN0.GAFLID13.UINT8[LL]
    3795 #define RSCAN0GAFLID13LH RSCAN0.GAFLID13.UINT8[LH]
    3796 #define RSCAN0GAFLID13H RSCAN0.GAFLID13.UINT16[H]
    3797 #define RSCAN0GAFLID13HL RSCAN0.GAFLID13.UINT8[HL]
    3798 #define RSCAN0GAFLID13HH RSCAN0.GAFLID13.UINT8[HH]
    3799 #define RSCAN0GAFLM13 RSCAN0.GAFLM13.UINT32
    3800 #define RSCAN0GAFLM13L RSCAN0.GAFLM13.UINT16[L]
    3801 #define RSCAN0GAFLM13LL RSCAN0.GAFLM13.UINT8[LL]
    3802 #define RSCAN0GAFLM13LH RSCAN0.GAFLM13.UINT8[LH]
    3803 #define RSCAN0GAFLM13H RSCAN0.GAFLM13.UINT16[H]
    3804 #define RSCAN0GAFLM13HL RSCAN0.GAFLM13.UINT8[HL]
    3805 #define RSCAN0GAFLM13HH RSCAN0.GAFLM13.UINT8[HH]
    3806 #define RSCAN0GAFLP013 RSCAN0.GAFLP013.UINT32
    3807 #define RSCAN0GAFLP013L RSCAN0.GAFLP013.UINT16[L]
    3808 #define RSCAN0GAFLP013LL RSCAN0.GAFLP013.UINT8[LL]
    3809 #define RSCAN0GAFLP013LH RSCAN0.GAFLP013.UINT8[LH]
    3810 #define RSCAN0GAFLP013H RSCAN0.GAFLP013.UINT16[H]
    3811 #define RSCAN0GAFLP013HL RSCAN0.GAFLP013.UINT8[HL]
    3812 #define RSCAN0GAFLP013HH RSCAN0.GAFLP013.UINT8[HH]
    3813 #define RSCAN0GAFLP113 RSCAN0.GAFLP113.UINT32
    3814 #define RSCAN0GAFLP113L RSCAN0.GAFLP113.UINT16[L]
    3815 #define RSCAN0GAFLP113LL RSCAN0.GAFLP113.UINT8[LL]
    3816 #define RSCAN0GAFLP113LH RSCAN0.GAFLP113.UINT8[LH]
    3817 #define RSCAN0GAFLP113H RSCAN0.GAFLP113.UINT16[H]
    3818 #define RSCAN0GAFLP113HL RSCAN0.GAFLP113.UINT8[HL]
    3819 #define RSCAN0GAFLP113HH RSCAN0.GAFLP113.UINT8[HH]
    3820 #define RSCAN0GAFLID14 RSCAN0.GAFLID14.UINT32
    3821 #define RSCAN0GAFLID14L RSCAN0.GAFLID14.UINT16[L]
    3822 #define RSCAN0GAFLID14LL RSCAN0.GAFLID14.UINT8[LL]
    3823 #define RSCAN0GAFLID14LH RSCAN0.GAFLID14.UINT8[LH]
    3824 #define RSCAN0GAFLID14H RSCAN0.GAFLID14.UINT16[H]
    3825 #define RSCAN0GAFLID14HL RSCAN0.GAFLID14.UINT8[HL]
    3826 #define RSCAN0GAFLID14HH RSCAN0.GAFLID14.UINT8[HH]
    3827 #define RSCAN0GAFLM14 RSCAN0.GAFLM14.UINT32
    3828 #define RSCAN0GAFLM14L RSCAN0.GAFLM14.UINT16[L]
    3829 #define RSCAN0GAFLM14LL RSCAN0.GAFLM14.UINT8[LL]
    3830 #define RSCAN0GAFLM14LH RSCAN0.GAFLM14.UINT8[LH]
    3831 #define RSCAN0GAFLM14H RSCAN0.GAFLM14.UINT16[H]
    3832 #define RSCAN0GAFLM14HL RSCAN0.GAFLM14.UINT8[HL]
    3833 #define RSCAN0GAFLM14HH RSCAN0.GAFLM14.UINT8[HH]
    3834 #define RSCAN0GAFLP014 RSCAN0.GAFLP014.UINT32
    3835 #define RSCAN0GAFLP014L RSCAN0.GAFLP014.UINT16[L]
    3836 #define RSCAN0GAFLP014LL RSCAN0.GAFLP014.UINT8[LL]
    3837 #define RSCAN0GAFLP014LH RSCAN0.GAFLP014.UINT8[LH]
    3838 #define RSCAN0GAFLP014H RSCAN0.GAFLP014.UINT16[H]
    3839 #define RSCAN0GAFLP014HL RSCAN0.GAFLP014.UINT8[HL]
    3840 #define RSCAN0GAFLP014HH RSCAN0.GAFLP014.UINT8[HH]
    3841 #define RSCAN0GAFLP114 RSCAN0.GAFLP114.UINT32
    3842 #define RSCAN0GAFLP114L RSCAN0.GAFLP114.UINT16[L]
    3843 #define RSCAN0GAFLP114LL RSCAN0.GAFLP114.UINT8[LL]
    3844 #define RSCAN0GAFLP114LH RSCAN0.GAFLP114.UINT8[LH]
    3845 #define RSCAN0GAFLP114H RSCAN0.GAFLP114.UINT16[H]
    3846 #define RSCAN0GAFLP114HL RSCAN0.GAFLP114.UINT8[HL]
    3847 #define RSCAN0GAFLP114HH RSCAN0.GAFLP114.UINT8[HH]
    3848 #define RSCAN0GAFLID15 RSCAN0.GAFLID15.UINT32
    3849 #define RSCAN0GAFLID15L RSCAN0.GAFLID15.UINT16[L]
    3850 #define RSCAN0GAFLID15LL RSCAN0.GAFLID15.UINT8[LL]
    3851 #define RSCAN0GAFLID15LH RSCAN0.GAFLID15.UINT8[LH]
    3852 #define RSCAN0GAFLID15H RSCAN0.GAFLID15.UINT16[H]
    3853 #define RSCAN0GAFLID15HL RSCAN0.GAFLID15.UINT8[HL]
    3854 #define RSCAN0GAFLID15HH RSCAN0.GAFLID15.UINT8[HH]
    3855 #define RSCAN0GAFLM15 RSCAN0.GAFLM15.UINT32
    3856 #define RSCAN0GAFLM15L RSCAN0.GAFLM15.UINT16[L]
    3857 #define RSCAN0GAFLM15LL RSCAN0.GAFLM15.UINT8[LL]
    3858 #define RSCAN0GAFLM15LH RSCAN0.GAFLM15.UINT8[LH]
    3859 #define RSCAN0GAFLM15H RSCAN0.GAFLM15.UINT16[H]
    3860 #define RSCAN0GAFLM15HL RSCAN0.GAFLM15.UINT8[HL]
    3861 #define RSCAN0GAFLM15HH RSCAN0.GAFLM15.UINT8[HH]
    3862 #define RSCAN0GAFLP015 RSCAN0.GAFLP015.UINT32
    3863 #define RSCAN0GAFLP015L RSCAN0.GAFLP015.UINT16[L]
    3864 #define RSCAN0GAFLP015LL RSCAN0.GAFLP015.UINT8[LL]
    3865 #define RSCAN0GAFLP015LH RSCAN0.GAFLP015.UINT8[LH]
    3866 #define RSCAN0GAFLP015H RSCAN0.GAFLP015.UINT16[H]
    3867 #define RSCAN0GAFLP015HL RSCAN0.GAFLP015.UINT8[HL]
    3868 #define RSCAN0GAFLP015HH RSCAN0.GAFLP015.UINT8[HH]
    3869 #define RSCAN0GAFLP115 RSCAN0.GAFLP115.UINT32
    3870 #define RSCAN0GAFLP115L RSCAN0.GAFLP115.UINT16[L]
    3871 #define RSCAN0GAFLP115LL RSCAN0.GAFLP115.UINT8[LL]
    3872 #define RSCAN0GAFLP115LH RSCAN0.GAFLP115.UINT8[LH]
    3873 #define RSCAN0GAFLP115H RSCAN0.GAFLP115.UINT16[H]
    3874 #define RSCAN0GAFLP115HL RSCAN0.GAFLP115.UINT8[HL]
    3875 #define RSCAN0GAFLP115HH RSCAN0.GAFLP115.UINT8[HH]
    3876 #define RSCAN0RMID0 RSCAN0.RMID0.UINT32
    3877 #define RSCAN0RMID0L RSCAN0.RMID0.UINT16[L]
    3878 #define RSCAN0RMID0LL RSCAN0.RMID0.UINT8[LL]
    3879 #define RSCAN0RMID0LH RSCAN0.RMID0.UINT8[LH]
    3880 #define RSCAN0RMID0H RSCAN0.RMID0.UINT16[H]
    3881 #define RSCAN0RMID0HL RSCAN0.RMID0.UINT8[HL]
    3882 #define RSCAN0RMID0HH RSCAN0.RMID0.UINT8[HH]
    3883 #define RSCAN0RMPTR0 RSCAN0.RMPTR0.UINT32
    3884 #define RSCAN0RMPTR0L RSCAN0.RMPTR0.UINT16[L]
    3885 #define RSCAN0RMPTR0LL RSCAN0.RMPTR0.UINT8[LL]
    3886 #define RSCAN0RMPTR0LH RSCAN0.RMPTR0.UINT8[LH]
    3887 #define RSCAN0RMPTR0H RSCAN0.RMPTR0.UINT16[H]
    3888 #define RSCAN0RMPTR0HL RSCAN0.RMPTR0.UINT8[HL]
    3889 #define RSCAN0RMPTR0HH RSCAN0.RMPTR0.UINT8[HH]
    3890 #define RSCAN0RMDF00 RSCAN0.RMDF00.UINT32
    3891 #define RSCAN0RMDF00L RSCAN0.RMDF00.UINT16[L]
    3892 #define RSCAN0RMDF00LL RSCAN0.RMDF00.UINT8[LL]
    3893 #define RSCAN0RMDF00LH RSCAN0.RMDF00.UINT8[LH]
    3894 #define RSCAN0RMDF00H RSCAN0.RMDF00.UINT16[H]
    3895 #define RSCAN0RMDF00HL RSCAN0.RMDF00.UINT8[HL]
    3896 #define RSCAN0RMDF00HH RSCAN0.RMDF00.UINT8[HH]
    3897 #define RSCAN0RMDF10 RSCAN0.RMDF10.UINT32
    3898 #define RSCAN0RMDF10L RSCAN0.RMDF10.UINT16[L]
    3899 #define RSCAN0RMDF10LL RSCAN0.RMDF10.UINT8[LL]
    3900 #define RSCAN0RMDF10LH RSCAN0.RMDF10.UINT8[LH]
    3901 #define RSCAN0RMDF10H RSCAN0.RMDF10.UINT16[H]
    3902 #define RSCAN0RMDF10HL RSCAN0.RMDF10.UINT8[HL]
    3903 #define RSCAN0RMDF10HH RSCAN0.RMDF10.UINT8[HH]
    3904 #define RSCAN0RMID1 RSCAN0.RMID1.UINT32
    3905 #define RSCAN0RMID1L RSCAN0.RMID1.UINT16[L]
    3906 #define RSCAN0RMID1LL RSCAN0.RMID1.UINT8[LL]
    3907 #define RSCAN0RMID1LH RSCAN0.RMID1.UINT8[LH]
    3908 #define RSCAN0RMID1H RSCAN0.RMID1.UINT16[H]
    3909 #define RSCAN0RMID1HL RSCAN0.RMID1.UINT8[HL]
    3910 #define RSCAN0RMID1HH RSCAN0.RMID1.UINT8[HH]
    3911 #define RSCAN0RMPTR1 RSCAN0.RMPTR1.UINT32
    3912 #define RSCAN0RMPTR1L RSCAN0.RMPTR1.UINT16[L]
    3913 #define RSCAN0RMPTR1LL RSCAN0.RMPTR1.UINT8[LL]
    3914 #define RSCAN0RMPTR1LH RSCAN0.RMPTR1.UINT8[LH]
    3915 #define RSCAN0RMPTR1H RSCAN0.RMPTR1.UINT16[H]
    3916 #define RSCAN0RMPTR1HL RSCAN0.RMPTR1.UINT8[HL]
    3917 #define RSCAN0RMPTR1HH RSCAN0.RMPTR1.UINT8[HH]
    3918 #define RSCAN0RMDF01 RSCAN0.RMDF01.UINT32
    3919 #define RSCAN0RMDF01L RSCAN0.RMDF01.UINT16[L]
    3920 #define RSCAN0RMDF01LL RSCAN0.RMDF01.UINT8[LL]
    3921 #define RSCAN0RMDF01LH RSCAN0.RMDF01.UINT8[LH]
    3922 #define RSCAN0RMDF01H RSCAN0.RMDF01.UINT16[H]
    3923 #define RSCAN0RMDF01HL RSCAN0.RMDF01.UINT8[HL]
    3924 #define RSCAN0RMDF01HH RSCAN0.RMDF01.UINT8[HH]
    3925 #define RSCAN0RMDF11 RSCAN0.RMDF11.UINT32
    3926 #define RSCAN0RMDF11L RSCAN0.RMDF11.UINT16[L]
    3927 #define RSCAN0RMDF11LL RSCAN0.RMDF11.UINT8[LL]
    3928 #define RSCAN0RMDF11LH RSCAN0.RMDF11.UINT8[LH]
    3929 #define RSCAN0RMDF11H RSCAN0.RMDF11.UINT16[H]
    3930 #define RSCAN0RMDF11HL RSCAN0.RMDF11.UINT8[HL]
    3931 #define RSCAN0RMDF11HH RSCAN0.RMDF11.UINT8[HH]
    3932 #define RSCAN0RMID2 RSCAN0.RMID2.UINT32
    3933 #define RSCAN0RMID2L RSCAN0.RMID2.UINT16[L]
    3934 #define RSCAN0RMID2LL RSCAN0.RMID2.UINT8[LL]
    3935 #define RSCAN0RMID2LH RSCAN0.RMID2.UINT8[LH]
    3936 #define RSCAN0RMID2H RSCAN0.RMID2.UINT16[H]
    3937 #define RSCAN0RMID2HL RSCAN0.RMID2.UINT8[HL]
    3938 #define RSCAN0RMID2HH RSCAN0.RMID2.UINT8[HH]
    3939 #define RSCAN0RMPTR2 RSCAN0.RMPTR2.UINT32
    3940 #define RSCAN0RMPTR2L RSCAN0.RMPTR2.UINT16[L]
    3941 #define RSCAN0RMPTR2LL RSCAN0.RMPTR2.UINT8[LL]
    3942 #define RSCAN0RMPTR2LH RSCAN0.RMPTR2.UINT8[LH]
    3943 #define RSCAN0RMPTR2H RSCAN0.RMPTR2.UINT16[H]
    3944 #define RSCAN0RMPTR2HL RSCAN0.RMPTR2.UINT8[HL]
    3945 #define RSCAN0RMPTR2HH RSCAN0.RMPTR2.UINT8[HH]
    3946 #define RSCAN0RMDF02 RSCAN0.RMDF02.UINT32
    3947 #define RSCAN0RMDF02L RSCAN0.RMDF02.UINT16[L]
    3948 #define RSCAN0RMDF02LL RSCAN0.RMDF02.UINT8[LL]
    3949 #define RSCAN0RMDF02LH RSCAN0.RMDF02.UINT8[LH]
    3950 #define RSCAN0RMDF02H RSCAN0.RMDF02.UINT16[H]
    3951 #define RSCAN0RMDF02HL RSCAN0.RMDF02.UINT8[HL]
    3952 #define RSCAN0RMDF02HH RSCAN0.RMDF02.UINT8[HH]
    3953 #define RSCAN0RMDF12 RSCAN0.RMDF12.UINT32
    3954 #define RSCAN0RMDF12L RSCAN0.RMDF12.UINT16[L]
    3955 #define RSCAN0RMDF12LL RSCAN0.RMDF12.UINT8[LL]
    3956 #define RSCAN0RMDF12LH RSCAN0.RMDF12.UINT8[LH]
    3957 #define RSCAN0RMDF12H RSCAN0.RMDF12.UINT16[H]
    3958 #define RSCAN0RMDF12HL RSCAN0.RMDF12.UINT8[HL]
    3959 #define RSCAN0RMDF12HH RSCAN0.RMDF12.UINT8[HH]
    3960 #define RSCAN0RMID3 RSCAN0.RMID3.UINT32
    3961 #define RSCAN0RMID3L RSCAN0.RMID3.UINT16[L]
    3962 #define RSCAN0RMID3LL RSCAN0.RMID3.UINT8[LL]
    3963 #define RSCAN0RMID3LH RSCAN0.RMID3.UINT8[LH]
    3964 #define RSCAN0RMID3H RSCAN0.RMID3.UINT16[H]
    3965 #define RSCAN0RMID3HL RSCAN0.RMID3.UINT8[HL]
    3966 #define RSCAN0RMID3HH RSCAN0.RMID3.UINT8[HH]
    3967 #define RSCAN0RMPTR3 RSCAN0.RMPTR3.UINT32
    3968 #define RSCAN0RMPTR3L RSCAN0.RMPTR3.UINT16[L]
    3969 #define RSCAN0RMPTR3LL RSCAN0.RMPTR3.UINT8[LL]
    3970 #define RSCAN0RMPTR3LH RSCAN0.RMPTR3.UINT8[LH]
    3971 #define RSCAN0RMPTR3H RSCAN0.RMPTR3.UINT16[H]
    3972 #define RSCAN0RMPTR3HL RSCAN0.RMPTR3.UINT8[HL]
    3973 #define RSCAN0RMPTR3HH RSCAN0.RMPTR3.UINT8[HH]
    3974 #define RSCAN0RMDF03 RSCAN0.RMDF03.UINT32
    3975 #define RSCAN0RMDF03L RSCAN0.RMDF03.UINT16[L]
    3976 #define RSCAN0RMDF03LL RSCAN0.RMDF03.UINT8[LL]
    3977 #define RSCAN0RMDF03LH RSCAN0.RMDF03.UINT8[LH]
    3978 #define RSCAN0RMDF03H RSCAN0.RMDF03.UINT16[H]
    3979 #define RSCAN0RMDF03HL RSCAN0.RMDF03.UINT8[HL]
    3980 #define RSCAN0RMDF03HH RSCAN0.RMDF03.UINT8[HH]
    3981 #define RSCAN0RMDF13 RSCAN0.RMDF13.UINT32
    3982 #define RSCAN0RMDF13L RSCAN0.RMDF13.UINT16[L]
    3983 #define RSCAN0RMDF13LL RSCAN0.RMDF13.UINT8[LL]
    3984 #define RSCAN0RMDF13LH RSCAN0.RMDF13.UINT8[LH]
    3985 #define RSCAN0RMDF13H RSCAN0.RMDF13.UINT16[H]
    3986 #define RSCAN0RMDF13HL RSCAN0.RMDF13.UINT8[HL]
    3987 #define RSCAN0RMDF13HH RSCAN0.RMDF13.UINT8[HH]
    3988 #define RSCAN0RMID4 RSCAN0.RMID4.UINT32
    3989 #define RSCAN0RMID4L RSCAN0.RMID4.UINT16[L]
    3990 #define RSCAN0RMID4LL RSCAN0.RMID4.UINT8[LL]
    3991 #define RSCAN0RMID4LH RSCAN0.RMID4.UINT8[LH]
    3992 #define RSCAN0RMID4H RSCAN0.RMID4.UINT16[H]
    3993 #define RSCAN0RMID4HL RSCAN0.RMID4.UINT8[HL]
    3994 #define RSCAN0RMID4HH RSCAN0.RMID4.UINT8[HH]
    3995 #define RSCAN0RMPTR4 RSCAN0.RMPTR4.UINT32
    3996 #define RSCAN0RMPTR4L RSCAN0.RMPTR4.UINT16[L]
    3997 #define RSCAN0RMPTR4LL RSCAN0.RMPTR4.UINT8[LL]
    3998 #define RSCAN0RMPTR4LH RSCAN0.RMPTR4.UINT8[LH]
    3999 #define RSCAN0RMPTR4H RSCAN0.RMPTR4.UINT16[H]
    4000 #define RSCAN0RMPTR4HL RSCAN0.RMPTR4.UINT8[HL]
    4001 #define RSCAN0RMPTR4HH RSCAN0.RMPTR4.UINT8[HH]
    4002 #define RSCAN0RMDF04 RSCAN0.RMDF04.UINT32
    4003 #define RSCAN0RMDF04L RSCAN0.RMDF04.UINT16[L]
    4004 #define RSCAN0RMDF04LL RSCAN0.RMDF04.UINT8[LL]
    4005 #define RSCAN0RMDF04LH RSCAN0.RMDF04.UINT8[LH]
    4006 #define RSCAN0RMDF04H RSCAN0.RMDF04.UINT16[H]
    4007 #define RSCAN0RMDF04HL RSCAN0.RMDF04.UINT8[HL]
    4008 #define RSCAN0RMDF04HH RSCAN0.RMDF04.UINT8[HH]
    4009 #define RSCAN0RMDF14 RSCAN0.RMDF14.UINT32
    4010 #define RSCAN0RMDF14L RSCAN0.RMDF14.UINT16[L]
    4011 #define RSCAN0RMDF14LL RSCAN0.RMDF14.UINT8[LL]
    4012 #define RSCAN0RMDF14LH RSCAN0.RMDF14.UINT8[LH]
    4013 #define RSCAN0RMDF14H RSCAN0.RMDF14.UINT16[H]
    4014 #define RSCAN0RMDF14HL RSCAN0.RMDF14.UINT8[HL]
    4015 #define RSCAN0RMDF14HH RSCAN0.RMDF14.UINT8[HH]
    4016 #define RSCAN0RMID5 RSCAN0.RMID5.UINT32
    4017 #define RSCAN0RMID5L RSCAN0.RMID5.UINT16[L]
    4018 #define RSCAN0RMID5LL RSCAN0.RMID5.UINT8[LL]
    4019 #define RSCAN0RMID5LH RSCAN0.RMID5.UINT8[LH]
    4020 #define RSCAN0RMID5H RSCAN0.RMID5.UINT16[H]
    4021 #define RSCAN0RMID5HL RSCAN0.RMID5.UINT8[HL]
    4022 #define RSCAN0RMID5HH RSCAN0.RMID5.UINT8[HH]
    4023 #define RSCAN0RMPTR5 RSCAN0.RMPTR5.UINT32
    4024 #define RSCAN0RMPTR5L RSCAN0.RMPTR5.UINT16[L]
    4025 #define RSCAN0RMPTR5LL RSCAN0.RMPTR5.UINT8[LL]
    4026 #define RSCAN0RMPTR5LH RSCAN0.RMPTR5.UINT8[LH]
    4027 #define RSCAN0RMPTR5H RSCAN0.RMPTR5.UINT16[H]
    4028 #define RSCAN0RMPTR5HL RSCAN0.RMPTR5.UINT8[HL]
    4029 #define RSCAN0RMPTR5HH RSCAN0.RMPTR5.UINT8[HH]
    4030 #define RSCAN0RMDF05 RSCAN0.RMDF05.UINT32
    4031 #define RSCAN0RMDF05L RSCAN0.RMDF05.UINT16[L]
    4032 #define RSCAN0RMDF05LL RSCAN0.RMDF05.UINT8[LL]
    4033 #define RSCAN0RMDF05LH RSCAN0.RMDF05.UINT8[LH]
    4034 #define RSCAN0RMDF05H RSCAN0.RMDF05.UINT16[H]
    4035 #define RSCAN0RMDF05HL RSCAN0.RMDF05.UINT8[HL]
    4036 #define RSCAN0RMDF05HH RSCAN0.RMDF05.UINT8[HH]
    4037 #define RSCAN0RMDF15 RSCAN0.RMDF15.UINT32
    4038 #define RSCAN0RMDF15L RSCAN0.RMDF15.UINT16[L]
    4039 #define RSCAN0RMDF15LL RSCAN0.RMDF15.UINT8[LL]
    4040 #define RSCAN0RMDF15LH RSCAN0.RMDF15.UINT8[LH]
    4041 #define RSCAN0RMDF15H RSCAN0.RMDF15.UINT16[H]
    4042 #define RSCAN0RMDF15HL RSCAN0.RMDF15.UINT8[HL]
    4043 #define RSCAN0RMDF15HH RSCAN0.RMDF15.UINT8[HH]
    4044 #define RSCAN0RMID6 RSCAN0.RMID6.UINT32
    4045 #define RSCAN0RMID6L RSCAN0.RMID6.UINT16[L]
    4046 #define RSCAN0RMID6LL RSCAN0.RMID6.UINT8[LL]
    4047 #define RSCAN0RMID6LH RSCAN0.RMID6.UINT8[LH]
    4048 #define RSCAN0RMID6H RSCAN0.RMID6.UINT16[H]
    4049 #define RSCAN0RMID6HL RSCAN0.RMID6.UINT8[HL]
    4050 #define RSCAN0RMID6HH RSCAN0.RMID6.UINT8[HH]
    4051 #define RSCAN0RMPTR6 RSCAN0.RMPTR6.UINT32
    4052 #define RSCAN0RMPTR6L RSCAN0.RMPTR6.UINT16[L]
    4053 #define RSCAN0RMPTR6LL RSCAN0.RMPTR6.UINT8[LL]
    4054 #define RSCAN0RMPTR6LH RSCAN0.RMPTR6.UINT8[LH]
    4055 #define RSCAN0RMPTR6H RSCAN0.RMPTR6.UINT16[H]
    4056 #define RSCAN0RMPTR6HL RSCAN0.RMPTR6.UINT8[HL]
    4057 #define RSCAN0RMPTR6HH RSCAN0.RMPTR6.UINT8[HH]
    4058 #define RSCAN0RMDF06 RSCAN0.RMDF06.UINT32
    4059 #define RSCAN0RMDF06L RSCAN0.RMDF06.UINT16[L]
    4060 #define RSCAN0RMDF06LL RSCAN0.RMDF06.UINT8[LL]
    4061 #define RSCAN0RMDF06LH RSCAN0.RMDF06.UINT8[LH]
    4062 #define RSCAN0RMDF06H RSCAN0.RMDF06.UINT16[H]
    4063 #define RSCAN0RMDF06HL RSCAN0.RMDF06.UINT8[HL]
    4064 #define RSCAN0RMDF06HH RSCAN0.RMDF06.UINT8[HH]
    4065 #define RSCAN0RMDF16 RSCAN0.RMDF16.UINT32
    4066 #define RSCAN0RMDF16L RSCAN0.RMDF16.UINT16[L]
    4067 #define RSCAN0RMDF16LL RSCAN0.RMDF16.UINT8[LL]
    4068 #define RSCAN0RMDF16LH RSCAN0.RMDF16.UINT8[LH]
    4069 #define RSCAN0RMDF16H RSCAN0.RMDF16.UINT16[H]
    4070 #define RSCAN0RMDF16HL RSCAN0.RMDF16.UINT8[HL]
    4071 #define RSCAN0RMDF16HH RSCAN0.RMDF16.UINT8[HH]
    4072 #define RSCAN0RMID7 RSCAN0.RMID7.UINT32
    4073 #define RSCAN0RMID7L RSCAN0.RMID7.UINT16[L]
    4074 #define RSCAN0RMID7LL RSCAN0.RMID7.UINT8[LL]
    4075 #define RSCAN0RMID7LH RSCAN0.RMID7.UINT8[LH]
    4076 #define RSCAN0RMID7H RSCAN0.RMID7.UINT16[H]
    4077 #define RSCAN0RMID7HL RSCAN0.RMID7.UINT8[HL]
    4078 #define RSCAN0RMID7HH RSCAN0.RMID7.UINT8[HH]
    4079 #define RSCAN0RMPTR7 RSCAN0.RMPTR7.UINT32
    4080 #define RSCAN0RMPTR7L RSCAN0.RMPTR7.UINT16[L]
    4081 #define RSCAN0RMPTR7LL RSCAN0.RMPTR7.UINT8[LL]
    4082 #define RSCAN0RMPTR7LH RSCAN0.RMPTR7.UINT8[LH]
    4083 #define RSCAN0RMPTR7H RSCAN0.RMPTR7.UINT16[H]
    4084 #define RSCAN0RMPTR7HL RSCAN0.RMPTR7.UINT8[HL]
    4085 #define RSCAN0RMPTR7HH RSCAN0.RMPTR7.UINT8[HH]
    4086 #define RSCAN0RMDF07 RSCAN0.RMDF07.UINT32
    4087 #define RSCAN0RMDF07L RSCAN0.RMDF07.UINT16[L]
    4088 #define RSCAN0RMDF07LL RSCAN0.RMDF07.UINT8[LL]
    4089 #define RSCAN0RMDF07LH RSCAN0.RMDF07.UINT8[LH]
    4090 #define RSCAN0RMDF07H RSCAN0.RMDF07.UINT16[H]
    4091 #define RSCAN0RMDF07HL RSCAN0.RMDF07.UINT8[HL]
    4092 #define RSCAN0RMDF07HH RSCAN0.RMDF07.UINT8[HH]
    4093 #define RSCAN0RMDF17 RSCAN0.RMDF17.UINT32
    4094 #define RSCAN0RMDF17L RSCAN0.RMDF17.UINT16[L]
    4095 #define RSCAN0RMDF17LL RSCAN0.RMDF17.UINT8[LL]
    4096 #define RSCAN0RMDF17LH RSCAN0.RMDF17.UINT8[LH]
    4097 #define RSCAN0RMDF17H RSCAN0.RMDF17.UINT16[H]
    4098 #define RSCAN0RMDF17HL RSCAN0.RMDF17.UINT8[HL]
    4099 #define RSCAN0RMDF17HH RSCAN0.RMDF17.UINT8[HH]
    4100 #define RSCAN0RMID8 RSCAN0.RMID8.UINT32
    4101 #define RSCAN0RMID8L RSCAN0.RMID8.UINT16[L]
    4102 #define RSCAN0RMID8LL RSCAN0.RMID8.UINT8[LL]
    4103 #define RSCAN0RMID8LH RSCAN0.RMID8.UINT8[LH]
    4104 #define RSCAN0RMID8H RSCAN0.RMID8.UINT16[H]
    4105 #define RSCAN0RMID8HL RSCAN0.RMID8.UINT8[HL]
    4106 #define RSCAN0RMID8HH RSCAN0.RMID8.UINT8[HH]
    4107 #define RSCAN0RMPTR8 RSCAN0.RMPTR8.UINT32
    4108 #define RSCAN0RMPTR8L RSCAN0.RMPTR8.UINT16[L]
    4109 #define RSCAN0RMPTR8LL RSCAN0.RMPTR8.UINT8[LL]
    4110 #define RSCAN0RMPTR8LH RSCAN0.RMPTR8.UINT8[LH]
    4111 #define RSCAN0RMPTR8H RSCAN0.RMPTR8.UINT16[H]
    4112 #define RSCAN0RMPTR8HL RSCAN0.RMPTR8.UINT8[HL]
    4113 #define RSCAN0RMPTR8HH RSCAN0.RMPTR8.UINT8[HH]
    4114 #define RSCAN0RMDF08 RSCAN0.RMDF08.UINT32
    4115 #define RSCAN0RMDF08L RSCAN0.RMDF08.UINT16[L]
    4116 #define RSCAN0RMDF08LL RSCAN0.RMDF08.UINT8[LL]
    4117 #define RSCAN0RMDF08LH RSCAN0.RMDF08.UINT8[LH]
    4118 #define RSCAN0RMDF08H RSCAN0.RMDF08.UINT16[H]
    4119 #define RSCAN0RMDF08HL RSCAN0.RMDF08.UINT8[HL]
    4120 #define RSCAN0RMDF08HH RSCAN0.RMDF08.UINT8[HH]
    4121 #define RSCAN0RMDF18 RSCAN0.RMDF18.UINT32
    4122 #define RSCAN0RMDF18L RSCAN0.RMDF18.UINT16[L]
    4123 #define RSCAN0RMDF18LL RSCAN0.RMDF18.UINT8[LL]
    4124 #define RSCAN0RMDF18LH RSCAN0.RMDF18.UINT8[LH]
    4125 #define RSCAN0RMDF18H RSCAN0.RMDF18.UINT16[H]
    4126 #define RSCAN0RMDF18HL RSCAN0.RMDF18.UINT8[HL]
    4127 #define RSCAN0RMDF18HH RSCAN0.RMDF18.UINT8[HH]
    4128 #define RSCAN0RMID9 RSCAN0.RMID9.UINT32
    4129 #define RSCAN0RMID9L RSCAN0.RMID9.UINT16[L]
    4130 #define RSCAN0RMID9LL RSCAN0.RMID9.UINT8[LL]
    4131 #define RSCAN0RMID9LH RSCAN0.RMID9.UINT8[LH]
    4132 #define RSCAN0RMID9H RSCAN0.RMID9.UINT16[H]
    4133 #define RSCAN0RMID9HL RSCAN0.RMID9.UINT8[HL]
    4134 #define RSCAN0RMID9HH RSCAN0.RMID9.UINT8[HH]
    4135 #define RSCAN0RMPTR9 RSCAN0.RMPTR9.UINT32
    4136 #define RSCAN0RMPTR9L RSCAN0.RMPTR9.UINT16[L]
    4137 #define RSCAN0RMPTR9LL RSCAN0.RMPTR9.UINT8[LL]
    4138 #define RSCAN0RMPTR9LH RSCAN0.RMPTR9.UINT8[LH]
    4139 #define RSCAN0RMPTR9H RSCAN0.RMPTR9.UINT16[H]
    4140 #define RSCAN0RMPTR9HL RSCAN0.RMPTR9.UINT8[HL]
    4141 #define RSCAN0RMPTR9HH RSCAN0.RMPTR9.UINT8[HH]
    4142 #define RSCAN0RMDF09 RSCAN0.RMDF09.UINT32
    4143 #define RSCAN0RMDF09L RSCAN0.RMDF09.UINT16[L]
    4144 #define RSCAN0RMDF09LL RSCAN0.RMDF09.UINT8[LL]
    4145 #define RSCAN0RMDF09LH RSCAN0.RMDF09.UINT8[LH]
    4146 #define RSCAN0RMDF09H RSCAN0.RMDF09.UINT16[H]
    4147 #define RSCAN0RMDF09HL RSCAN0.RMDF09.UINT8[HL]
    4148 #define RSCAN0RMDF09HH RSCAN0.RMDF09.UINT8[HH]
    4149 #define RSCAN0RMDF19 RSCAN0.RMDF19.UINT32
    4150 #define RSCAN0RMDF19L RSCAN0.RMDF19.UINT16[L]
    4151 #define RSCAN0RMDF19LL RSCAN0.RMDF19.UINT8[LL]
    4152 #define RSCAN0RMDF19LH RSCAN0.RMDF19.UINT8[LH]
    4153 #define RSCAN0RMDF19H RSCAN0.RMDF19.UINT16[H]
    4154 #define RSCAN0RMDF19HL RSCAN0.RMDF19.UINT8[HL]
    4155 #define RSCAN0RMDF19HH RSCAN0.RMDF19.UINT8[HH]
    4156 #define RSCAN0RMID10 RSCAN0.RMID10.UINT32
    4157 #define RSCAN0RMID10L RSCAN0.RMID10.UINT16[L]
    4158 #define RSCAN0RMID10LL RSCAN0.RMID10.UINT8[LL]
    4159 #define RSCAN0RMID10LH RSCAN0.RMID10.UINT8[LH]
    4160 #define RSCAN0RMID10H RSCAN0.RMID10.UINT16[H]
    4161 #define RSCAN0RMID10HL RSCAN0.RMID10.UINT8[HL]
    4162 #define RSCAN0RMID10HH RSCAN0.RMID10.UINT8[HH]
    4163 #define RSCAN0RMPTR10 RSCAN0.RMPTR10.UINT32
    4164 #define RSCAN0RMPTR10L RSCAN0.RMPTR10.UINT16[L]
    4165 #define RSCAN0RMPTR10LL RSCAN0.RMPTR10.UINT8[LL]
    4166 #define RSCAN0RMPTR10LH RSCAN0.RMPTR10.UINT8[LH]
    4167 #define RSCAN0RMPTR10H RSCAN0.RMPTR10.UINT16[H]
    4168 #define RSCAN0RMPTR10HL RSCAN0.RMPTR10.UINT8[HL]
    4169 #define RSCAN0RMPTR10HH RSCAN0.RMPTR10.UINT8[HH]
    4170 #define RSCAN0RMDF010 RSCAN0.RMDF010.UINT32
    4171 #define RSCAN0RMDF010L RSCAN0.RMDF010.UINT16[L]
    4172 #define RSCAN0RMDF010LL RSCAN0.RMDF010.UINT8[LL]
    4173 #define RSCAN0RMDF010LH RSCAN0.RMDF010.UINT8[LH]
    4174 #define RSCAN0RMDF010H RSCAN0.RMDF010.UINT16[H]
    4175 #define RSCAN0RMDF010HL RSCAN0.RMDF010.UINT8[HL]
    4176 #define RSCAN0RMDF010HH RSCAN0.RMDF010.UINT8[HH]
    4177 #define RSCAN0RMDF110 RSCAN0.RMDF110.UINT32
    4178 #define RSCAN0RMDF110L RSCAN0.RMDF110.UINT16[L]
    4179 #define RSCAN0RMDF110LL RSCAN0.RMDF110.UINT8[LL]
    4180 #define RSCAN0RMDF110LH RSCAN0.RMDF110.UINT8[LH]
    4181 #define RSCAN0RMDF110H RSCAN0.RMDF110.UINT16[H]
    4182 #define RSCAN0RMDF110HL RSCAN0.RMDF110.UINT8[HL]
    4183 #define RSCAN0RMDF110HH RSCAN0.RMDF110.UINT8[HH]
    4184 #define RSCAN0RMID11 RSCAN0.RMID11.UINT32
    4185 #define RSCAN0RMID11L RSCAN0.RMID11.UINT16[L]
    4186 #define RSCAN0RMID11LL RSCAN0.RMID11.UINT8[LL]
    4187 #define RSCAN0RMID11LH RSCAN0.RMID11.UINT8[LH]
    4188 #define RSCAN0RMID11H RSCAN0.RMID11.UINT16[H]
    4189 #define RSCAN0RMID11HL RSCAN0.RMID11.UINT8[HL]
    4190 #define RSCAN0RMID11HH RSCAN0.RMID11.UINT8[HH]
    4191 #define RSCAN0RMPTR11 RSCAN0.RMPTR11.UINT32
    4192 #define RSCAN0RMPTR11L RSCAN0.RMPTR11.UINT16[L]
    4193 #define RSCAN0RMPTR11LL RSCAN0.RMPTR11.UINT8[LL]
    4194 #define RSCAN0RMPTR11LH RSCAN0.RMPTR11.UINT8[LH]
    4195 #define RSCAN0RMPTR11H RSCAN0.RMPTR11.UINT16[H]
    4196 #define RSCAN0RMPTR11HL RSCAN0.RMPTR11.UINT8[HL]
    4197 #define RSCAN0RMPTR11HH RSCAN0.RMPTR11.UINT8[HH]
    4198 #define RSCAN0RMDF011 RSCAN0.RMDF011.UINT32
    4199 #define RSCAN0RMDF011L RSCAN0.RMDF011.UINT16[L]
    4200 #define RSCAN0RMDF011LL RSCAN0.RMDF011.UINT8[LL]
    4201 #define RSCAN0RMDF011LH RSCAN0.RMDF011.UINT8[LH]
    4202 #define RSCAN0RMDF011H RSCAN0.RMDF011.UINT16[H]
    4203 #define RSCAN0RMDF011HL RSCAN0.RMDF011.UINT8[HL]
    4204 #define RSCAN0RMDF011HH RSCAN0.RMDF011.UINT8[HH]
    4205 #define RSCAN0RMDF111 RSCAN0.RMDF111.UINT32
    4206 #define RSCAN0RMDF111L RSCAN0.RMDF111.UINT16[L]
    4207 #define RSCAN0RMDF111LL RSCAN0.RMDF111.UINT8[LL]
    4208 #define RSCAN0RMDF111LH RSCAN0.RMDF111.UINT8[LH]
    4209 #define RSCAN0RMDF111H RSCAN0.RMDF111.UINT16[H]
    4210 #define RSCAN0RMDF111HL RSCAN0.RMDF111.UINT8[HL]
    4211 #define RSCAN0RMDF111HH RSCAN0.RMDF111.UINT8[HH]
    4212 #define RSCAN0RMID12 RSCAN0.RMID12.UINT32
    4213 #define RSCAN0RMID12L RSCAN0.RMID12.UINT16[L]
    4214 #define RSCAN0RMID12LL RSCAN0.RMID12.UINT8[LL]
    4215 #define RSCAN0RMID12LH RSCAN0.RMID12.UINT8[LH]
    4216 #define RSCAN0RMID12H RSCAN0.RMID12.UINT16[H]
    4217 #define RSCAN0RMID12HL RSCAN0.RMID12.UINT8[HL]
    4218 #define RSCAN0RMID12HH RSCAN0.RMID12.UINT8[HH]
    4219 #define RSCAN0RMPTR12 RSCAN0.RMPTR12.UINT32
    4220 #define RSCAN0RMPTR12L RSCAN0.RMPTR12.UINT16[L]
    4221 #define RSCAN0RMPTR12LL RSCAN0.RMPTR12.UINT8[LL]
    4222 #define RSCAN0RMPTR12LH RSCAN0.RMPTR12.UINT8[LH]
    4223 #define RSCAN0RMPTR12H RSCAN0.RMPTR12.UINT16[H]
    4224 #define RSCAN0RMPTR12HL RSCAN0.RMPTR12.UINT8[HL]
    4225 #define RSCAN0RMPTR12HH RSCAN0.RMPTR12.UINT8[HH]
    4226 #define RSCAN0RMDF012 RSCAN0.RMDF012.UINT32
    4227 #define RSCAN0RMDF012L RSCAN0.RMDF012.UINT16[L]
    4228 #define RSCAN0RMDF012LL RSCAN0.RMDF012.UINT8[LL]
    4229 #define RSCAN0RMDF012LH RSCAN0.RMDF012.UINT8[LH]
    4230 #define RSCAN0RMDF012H RSCAN0.RMDF012.UINT16[H]
    4231 #define RSCAN0RMDF012HL RSCAN0.RMDF012.UINT8[HL]
    4232 #define RSCAN0RMDF012HH RSCAN0.RMDF012.UINT8[HH]
    4233 #define RSCAN0RMDF112 RSCAN0.RMDF112.UINT32
    4234 #define RSCAN0RMDF112L RSCAN0.RMDF112.UINT16[L]
    4235 #define RSCAN0RMDF112LL RSCAN0.RMDF112.UINT8[LL]
    4236 #define RSCAN0RMDF112LH RSCAN0.RMDF112.UINT8[LH]
    4237 #define RSCAN0RMDF112H RSCAN0.RMDF112.UINT16[H]
    4238 #define RSCAN0RMDF112HL RSCAN0.RMDF112.UINT8[HL]
    4239 #define RSCAN0RMDF112HH RSCAN0.RMDF112.UINT8[HH]
    4240 #define RSCAN0RMID13 RSCAN0.RMID13.UINT32
    4241 #define RSCAN0RMID13L RSCAN0.RMID13.UINT16[L]
    4242 #define RSCAN0RMID13LL RSCAN0.RMID13.UINT8[LL]
    4243 #define RSCAN0RMID13LH RSCAN0.RMID13.UINT8[LH]
    4244 #define RSCAN0RMID13H RSCAN0.RMID13.UINT16[H]
    4245 #define RSCAN0RMID13HL RSCAN0.RMID13.UINT8[HL]
    4246 #define RSCAN0RMID13HH RSCAN0.RMID13.UINT8[HH]
    4247 #define RSCAN0RMPTR13 RSCAN0.RMPTR13.UINT32
    4248 #define RSCAN0RMPTR13L RSCAN0.RMPTR13.UINT16[L]
    4249 #define RSCAN0RMPTR13LL RSCAN0.RMPTR13.UINT8[LL]
    4250 #define RSCAN0RMPTR13LH RSCAN0.RMPTR13.UINT8[LH]
    4251 #define RSCAN0RMPTR13H RSCAN0.RMPTR13.UINT16[H]
    4252 #define RSCAN0RMPTR13HL RSCAN0.RMPTR13.UINT8[HL]
    4253 #define RSCAN0RMPTR13HH RSCAN0.RMPTR13.UINT8[HH]
    4254 #define RSCAN0RMDF013 RSCAN0.RMDF013.UINT32
    4255 #define RSCAN0RMDF013L RSCAN0.RMDF013.UINT16[L]
    4256 #define RSCAN0RMDF013LL RSCAN0.RMDF013.UINT8[LL]
    4257 #define RSCAN0RMDF013LH RSCAN0.RMDF013.UINT8[LH]
    4258 #define RSCAN0RMDF013H RSCAN0.RMDF013.UINT16[H]
    4259 #define RSCAN0RMDF013HL RSCAN0.RMDF013.UINT8[HL]
    4260 #define RSCAN0RMDF013HH RSCAN0.RMDF013.UINT8[HH]
    4261 #define RSCAN0RMDF113 RSCAN0.RMDF113.UINT32
    4262 #define RSCAN0RMDF113L RSCAN0.RMDF113.UINT16[L]
    4263 #define RSCAN0RMDF113LL RSCAN0.RMDF113.UINT8[LL]
    4264 #define RSCAN0RMDF113LH RSCAN0.RMDF113.UINT8[LH]
    4265 #define RSCAN0RMDF113H RSCAN0.RMDF113.UINT16[H]
    4266 #define RSCAN0RMDF113HL RSCAN0.RMDF113.UINT8[HL]
    4267 #define RSCAN0RMDF113HH RSCAN0.RMDF113.UINT8[HH]
    4268 #define RSCAN0RMID14 RSCAN0.RMID14.UINT32
    4269 #define RSCAN0RMID14L RSCAN0.RMID14.UINT16[L]
    4270 #define RSCAN0RMID14LL RSCAN0.RMID14.UINT8[LL]
    4271 #define RSCAN0RMID14LH RSCAN0.RMID14.UINT8[LH]
    4272 #define RSCAN0RMID14H RSCAN0.RMID14.UINT16[H]
    4273 #define RSCAN0RMID14HL RSCAN0.RMID14.UINT8[HL]
    4274 #define RSCAN0RMID14HH RSCAN0.RMID14.UINT8[HH]
    4275 #define RSCAN0RMPTR14 RSCAN0.RMPTR14.UINT32
    4276 #define RSCAN0RMPTR14L RSCAN0.RMPTR14.UINT16[L]
    4277 #define RSCAN0RMPTR14LL RSCAN0.RMPTR14.UINT8[LL]
    4278 #define RSCAN0RMPTR14LH RSCAN0.RMPTR14.UINT8[LH]
    4279 #define RSCAN0RMPTR14H RSCAN0.RMPTR14.UINT16[H]
    4280 #define RSCAN0RMPTR14HL RSCAN0.RMPTR14.UINT8[HL]
    4281 #define RSCAN0RMPTR14HH RSCAN0.RMPTR14.UINT8[HH]
    4282 #define RSCAN0RMDF014 RSCAN0.RMDF014.UINT32
    4283 #define RSCAN0RMDF014L RSCAN0.RMDF014.UINT16[L]
    4284 #define RSCAN0RMDF014LL RSCAN0.RMDF014.UINT8[LL]
    4285 #define RSCAN0RMDF014LH RSCAN0.RMDF014.UINT8[LH]
    4286 #define RSCAN0RMDF014H RSCAN0.RMDF014.UINT16[H]
    4287 #define RSCAN0RMDF014HL RSCAN0.RMDF014.UINT8[HL]
    4288 #define RSCAN0RMDF014HH RSCAN0.RMDF014.UINT8[HH]
    4289 #define RSCAN0RMDF114 RSCAN0.RMDF114.UINT32
    4290 #define RSCAN0RMDF114L RSCAN0.RMDF114.UINT16[L]
    4291 #define RSCAN0RMDF114LL RSCAN0.RMDF114.UINT8[LL]
    4292 #define RSCAN0RMDF114LH RSCAN0.RMDF114.UINT8[LH]
    4293 #define RSCAN0RMDF114H RSCAN0.RMDF114.UINT16[H]
    4294 #define RSCAN0RMDF114HL RSCAN0.RMDF114.UINT8[HL]
    4295 #define RSCAN0RMDF114HH RSCAN0.RMDF114.UINT8[HH]
    4296 #define RSCAN0RMID15 RSCAN0.RMID15.UINT32
    4297 #define RSCAN0RMID15L RSCAN0.RMID15.UINT16[L]
    4298 #define RSCAN0RMID15LL RSCAN0.RMID15.UINT8[LL]
    4299 #define RSCAN0RMID15LH RSCAN0.RMID15.UINT8[LH]
    4300 #define RSCAN0RMID15H RSCAN0.RMID15.UINT16[H]
    4301 #define RSCAN0RMID15HL RSCAN0.RMID15.UINT8[HL]
    4302 #define RSCAN0RMID15HH RSCAN0.RMID15.UINT8[HH]
    4303 #define RSCAN0RMPTR15 RSCAN0.RMPTR15.UINT32
    4304 #define RSCAN0RMPTR15L RSCAN0.RMPTR15.UINT16[L]
    4305 #define RSCAN0RMPTR15LL RSCAN0.RMPTR15.UINT8[LL]
    4306 #define RSCAN0RMPTR15LH RSCAN0.RMPTR15.UINT8[LH]
    4307 #define RSCAN0RMPTR15H RSCAN0.RMPTR15.UINT16[H]
    4308 #define RSCAN0RMPTR15HL RSCAN0.RMPTR15.UINT8[HL]
    4309 #define RSCAN0RMPTR15HH RSCAN0.RMPTR15.UINT8[HH]
    4310 #define RSCAN0RMDF015 RSCAN0.RMDF015.UINT32
    4311 #define RSCAN0RMDF015L RSCAN0.RMDF015.UINT16[L]
    4312 #define RSCAN0RMDF015LL RSCAN0.RMDF015.UINT8[LL]
    4313 #define RSCAN0RMDF015LH RSCAN0.RMDF015.UINT8[LH]
    4314 #define RSCAN0RMDF015H RSCAN0.RMDF015.UINT16[H]
    4315 #define RSCAN0RMDF015HL RSCAN0.RMDF015.UINT8[HL]
    4316 #define RSCAN0RMDF015HH RSCAN0.RMDF015.UINT8[HH]
    4317 #define RSCAN0RMDF115 RSCAN0.RMDF115.UINT32
    4318 #define RSCAN0RMDF115L RSCAN0.RMDF115.UINT16[L]
    4319 #define RSCAN0RMDF115LL RSCAN0.RMDF115.UINT8[LL]
    4320 #define RSCAN0RMDF115LH RSCAN0.RMDF115.UINT8[LH]
    4321 #define RSCAN0RMDF115H RSCAN0.RMDF115.UINT16[H]
    4322 #define RSCAN0RMDF115HL RSCAN0.RMDF115.UINT8[HL]
    4323 #define RSCAN0RMDF115HH RSCAN0.RMDF115.UINT8[HH]
    4324 #define RSCAN0RMID16 RSCAN0.RMID16.UINT32
    4325 #define RSCAN0RMID16L RSCAN0.RMID16.UINT16[L]
    4326 #define RSCAN0RMID16LL RSCAN0.RMID16.UINT8[LL]
    4327 #define RSCAN0RMID16LH RSCAN0.RMID16.UINT8[LH]
    4328 #define RSCAN0RMID16H RSCAN0.RMID16.UINT16[H]
    4329 #define RSCAN0RMID16HL RSCAN0.RMID16.UINT8[HL]
    4330 #define RSCAN0RMID16HH RSCAN0.RMID16.UINT8[HH]
    4331 #define RSCAN0RMPTR16 RSCAN0.RMPTR16.UINT32
    4332 #define RSCAN0RMPTR16L RSCAN0.RMPTR16.UINT16[L]
    4333 #define RSCAN0RMPTR16LL RSCAN0.RMPTR16.UINT8[LL]
    4334 #define RSCAN0RMPTR16LH RSCAN0.RMPTR16.UINT8[LH]
    4335 #define RSCAN0RMPTR16H RSCAN0.RMPTR16.UINT16[H]
    4336 #define RSCAN0RMPTR16HL RSCAN0.RMPTR16.UINT8[HL]
    4337 #define RSCAN0RMPTR16HH RSCAN0.RMPTR16.UINT8[HH]
    4338 #define RSCAN0RMDF016 RSCAN0.RMDF016.UINT32
    4339 #define RSCAN0RMDF016L RSCAN0.RMDF016.UINT16[L]
    4340 #define RSCAN0RMDF016LL RSCAN0.RMDF016.UINT8[LL]
    4341 #define RSCAN0RMDF016LH RSCAN0.RMDF016.UINT8[LH]
    4342 #define RSCAN0RMDF016H RSCAN0.RMDF016.UINT16[H]
    4343 #define RSCAN0RMDF016HL RSCAN0.RMDF016.UINT8[HL]
    4344 #define RSCAN0RMDF016HH RSCAN0.RMDF016.UINT8[HH]
    4345 #define RSCAN0RMDF116 RSCAN0.RMDF116.UINT32
    4346 #define RSCAN0RMDF116L RSCAN0.RMDF116.UINT16[L]
    4347 #define RSCAN0RMDF116LL RSCAN0.RMDF116.UINT8[LL]
    4348 #define RSCAN0RMDF116LH RSCAN0.RMDF116.UINT8[LH]
    4349 #define RSCAN0RMDF116H RSCAN0.RMDF116.UINT16[H]
    4350 #define RSCAN0RMDF116HL RSCAN0.RMDF116.UINT8[HL]
    4351 #define RSCAN0RMDF116HH RSCAN0.RMDF116.UINT8[HH]
    4352 #define RSCAN0RMID17 RSCAN0.RMID17.UINT32
    4353 #define RSCAN0RMID17L RSCAN0.RMID17.UINT16[L]
    4354 #define RSCAN0RMID17LL RSCAN0.RMID17.UINT8[LL]
    4355 #define RSCAN0RMID17LH RSCAN0.RMID17.UINT8[LH]
    4356 #define RSCAN0RMID17H RSCAN0.RMID17.UINT16[H]
    4357 #define RSCAN0RMID17HL RSCAN0.RMID17.UINT8[HL]
    4358 #define RSCAN0RMID17HH RSCAN0.RMID17.UINT8[HH]
    4359 #define RSCAN0RMPTR17 RSCAN0.RMPTR17.UINT32
    4360 #define RSCAN0RMPTR17L RSCAN0.RMPTR17.UINT16[L]
    4361 #define RSCAN0RMPTR17LL RSCAN0.RMPTR17.UINT8[LL]
    4362 #define RSCAN0RMPTR17LH RSCAN0.RMPTR17.UINT8[LH]
    4363 #define RSCAN0RMPTR17H RSCAN0.RMPTR17.UINT16[H]
    4364 #define RSCAN0RMPTR17HL RSCAN0.RMPTR17.UINT8[HL]
    4365 #define RSCAN0RMPTR17HH RSCAN0.RMPTR17.UINT8[HH]
    4366 #define RSCAN0RMDF017 RSCAN0.RMDF017.UINT32
    4367 #define RSCAN0RMDF017L RSCAN0.RMDF017.UINT16[L]
    4368 #define RSCAN0RMDF017LL RSCAN0.RMDF017.UINT8[LL]
    4369 #define RSCAN0RMDF017LH RSCAN0.RMDF017.UINT8[LH]
    4370 #define RSCAN0RMDF017H RSCAN0.RMDF017.UINT16[H]
    4371 #define RSCAN0RMDF017HL RSCAN0.RMDF017.UINT8[HL]
    4372 #define RSCAN0RMDF017HH RSCAN0.RMDF017.UINT8[HH]
    4373 #define RSCAN0RMDF117 RSCAN0.RMDF117.UINT32
    4374 #define RSCAN0RMDF117L RSCAN0.RMDF117.UINT16[L]
    4375 #define RSCAN0RMDF117LL RSCAN0.RMDF117.UINT8[LL]
    4376 #define RSCAN0RMDF117LH RSCAN0.RMDF117.UINT8[LH]
    4377 #define RSCAN0RMDF117H RSCAN0.RMDF117.UINT16[H]
    4378 #define RSCAN0RMDF117HL RSCAN0.RMDF117.UINT8[HL]
    4379 #define RSCAN0RMDF117HH RSCAN0.RMDF117.UINT8[HH]
    4380 #define RSCAN0RMID18 RSCAN0.RMID18.UINT32
    4381 #define RSCAN0RMID18L RSCAN0.RMID18.UINT16[L]
    4382 #define RSCAN0RMID18LL RSCAN0.RMID18.UINT8[LL]
    4383 #define RSCAN0RMID18LH RSCAN0.RMID18.UINT8[LH]
    4384 #define RSCAN0RMID18H RSCAN0.RMID18.UINT16[H]
    4385 #define RSCAN0RMID18HL RSCAN0.RMID18.UINT8[HL]
    4386 #define RSCAN0RMID18HH RSCAN0.RMID18.UINT8[HH]
    4387 #define RSCAN0RMPTR18 RSCAN0.RMPTR18.UINT32
    4388 #define RSCAN0RMPTR18L RSCAN0.RMPTR18.UINT16[L]
    4389 #define RSCAN0RMPTR18LL RSCAN0.RMPTR18.UINT8[LL]
    4390 #define RSCAN0RMPTR18LH RSCAN0.RMPTR18.UINT8[LH]
    4391 #define RSCAN0RMPTR18H RSCAN0.RMPTR18.UINT16[H]
    4392 #define RSCAN0RMPTR18HL RSCAN0.RMPTR18.UINT8[HL]
    4393 #define RSCAN0RMPTR18HH RSCAN0.RMPTR18.UINT8[HH]
    4394 #define RSCAN0RMDF018 RSCAN0.RMDF018.UINT32
    4395 #define RSCAN0RMDF018L RSCAN0.RMDF018.UINT16[L]
    4396 #define RSCAN0RMDF018LL RSCAN0.RMDF018.UINT8[LL]
    4397 #define RSCAN0RMDF018LH RSCAN0.RMDF018.UINT8[LH]
    4398 #define RSCAN0RMDF018H RSCAN0.RMDF018.UINT16[H]
    4399 #define RSCAN0RMDF018HL RSCAN0.RMDF018.UINT8[HL]
    4400 #define RSCAN0RMDF018HH RSCAN0.RMDF018.UINT8[HH]
    4401 #define RSCAN0RMDF118 RSCAN0.RMDF118.UINT32
    4402 #define RSCAN0RMDF118L RSCAN0.RMDF118.UINT16[L]
    4403 #define RSCAN0RMDF118LL RSCAN0.RMDF118.UINT8[LL]
    4404 #define RSCAN0RMDF118LH RSCAN0.RMDF118.UINT8[LH]
    4405 #define RSCAN0RMDF118H RSCAN0.RMDF118.UINT16[H]
    4406 #define RSCAN0RMDF118HL RSCAN0.RMDF118.UINT8[HL]
    4407 #define RSCAN0RMDF118HH RSCAN0.RMDF118.UINT8[HH]
    4408 #define RSCAN0RMID19 RSCAN0.RMID19.UINT32
    4409 #define RSCAN0RMID19L RSCAN0.RMID19.UINT16[L]
    4410 #define RSCAN0RMID19LL RSCAN0.RMID19.UINT8[LL]
    4411 #define RSCAN0RMID19LH RSCAN0.RMID19.UINT8[LH]
    4412 #define RSCAN0RMID19H RSCAN0.RMID19.UINT16[H]
    4413 #define RSCAN0RMID19HL RSCAN0.RMID19.UINT8[HL]
    4414 #define RSCAN0RMID19HH RSCAN0.RMID19.UINT8[HH]
    4415 #define RSCAN0RMPTR19 RSCAN0.RMPTR19.UINT32
    4416 #define RSCAN0RMPTR19L RSCAN0.RMPTR19.UINT16[L]
    4417 #define RSCAN0RMPTR19LL RSCAN0.RMPTR19.UINT8[LL]
    4418 #define RSCAN0RMPTR19LH RSCAN0.RMPTR19.UINT8[LH]
    4419 #define RSCAN0RMPTR19H RSCAN0.RMPTR19.UINT16[H]
    4420 #define RSCAN0RMPTR19HL RSCAN0.RMPTR19.UINT8[HL]
    4421 #define RSCAN0RMPTR19HH RSCAN0.RMPTR19.UINT8[HH]
    4422 #define RSCAN0RMDF019 RSCAN0.RMDF019.UINT32
    4423 #define RSCAN0RMDF019L RSCAN0.RMDF019.UINT16[L]
    4424 #define RSCAN0RMDF019LL RSCAN0.RMDF019.UINT8[LL]
    4425 #define RSCAN0RMDF019LH RSCAN0.RMDF019.UINT8[LH]
    4426 #define RSCAN0RMDF019H RSCAN0.RMDF019.UINT16[H]
    4427 #define RSCAN0RMDF019HL RSCAN0.RMDF019.UINT8[HL]
    4428 #define RSCAN0RMDF019HH RSCAN0.RMDF019.UINT8[HH]
    4429 #define RSCAN0RMDF119 RSCAN0.RMDF119.UINT32
    4430 #define RSCAN0RMDF119L RSCAN0.RMDF119.UINT16[L]
    4431 #define RSCAN0RMDF119LL RSCAN0.RMDF119.UINT8[LL]
    4432 #define RSCAN0RMDF119LH RSCAN0.RMDF119.UINT8[LH]
    4433 #define RSCAN0RMDF119H RSCAN0.RMDF119.UINT16[H]
    4434 #define RSCAN0RMDF119HL RSCAN0.RMDF119.UINT8[HL]
    4435 #define RSCAN0RMDF119HH RSCAN0.RMDF119.UINT8[HH]
    4436 #define RSCAN0RMID20 RSCAN0.RMID20.UINT32
    4437 #define RSCAN0RMID20L RSCAN0.RMID20.UINT16[L]
    4438 #define RSCAN0RMID20LL RSCAN0.RMID20.UINT8[LL]
    4439 #define RSCAN0RMID20LH RSCAN0.RMID20.UINT8[LH]
    4440 #define RSCAN0RMID20H RSCAN0.RMID20.UINT16[H]
    4441 #define RSCAN0RMID20HL RSCAN0.RMID20.UINT8[HL]
    4442 #define RSCAN0RMID20HH RSCAN0.RMID20.UINT8[HH]
    4443 #define RSCAN0RMPTR20 RSCAN0.RMPTR20.UINT32
    4444 #define RSCAN0RMPTR20L RSCAN0.RMPTR20.UINT16[L]
    4445 #define RSCAN0RMPTR20LL RSCAN0.RMPTR20.UINT8[LL]
    4446 #define RSCAN0RMPTR20LH RSCAN0.RMPTR20.UINT8[LH]
    4447 #define RSCAN0RMPTR20H RSCAN0.RMPTR20.UINT16[H]
    4448 #define RSCAN0RMPTR20HL RSCAN0.RMPTR20.UINT8[HL]
    4449 #define RSCAN0RMPTR20HH RSCAN0.RMPTR20.UINT8[HH]
    4450 #define RSCAN0RMDF020 RSCAN0.RMDF020.UINT32
    4451 #define RSCAN0RMDF020L RSCAN0.RMDF020.UINT16[L]
    4452 #define RSCAN0RMDF020LL RSCAN0.RMDF020.UINT8[LL]
    4453 #define RSCAN0RMDF020LH RSCAN0.RMDF020.UINT8[LH]
    4454 #define RSCAN0RMDF020H RSCAN0.RMDF020.UINT16[H]
    4455 #define RSCAN0RMDF020HL RSCAN0.RMDF020.UINT8[HL]
    4456 #define RSCAN0RMDF020HH RSCAN0.RMDF020.UINT8[HH]
    4457 #define RSCAN0RMDF120 RSCAN0.RMDF120.UINT32
    4458 #define RSCAN0RMDF120L RSCAN0.RMDF120.UINT16[L]
    4459 #define RSCAN0RMDF120LL RSCAN0.RMDF120.UINT8[LL]
    4460 #define RSCAN0RMDF120LH RSCAN0.RMDF120.UINT8[LH]
    4461 #define RSCAN0RMDF120H RSCAN0.RMDF120.UINT16[H]
    4462 #define RSCAN0RMDF120HL RSCAN0.RMDF120.UINT8[HL]
    4463 #define RSCAN0RMDF120HH RSCAN0.RMDF120.UINT8[HH]
    4464 #define RSCAN0RMID21 RSCAN0.RMID21.UINT32
    4465 #define RSCAN0RMID21L RSCAN0.RMID21.UINT16[L]
    4466 #define RSCAN0RMID21LL RSCAN0.RMID21.UINT8[LL]
    4467 #define RSCAN0RMID21LH RSCAN0.RMID21.UINT8[LH]
    4468 #define RSCAN0RMID21H RSCAN0.RMID21.UINT16[H]
    4469 #define RSCAN0RMID21HL RSCAN0.RMID21.UINT8[HL]
    4470 #define RSCAN0RMID21HH RSCAN0.RMID21.UINT8[HH]
    4471 #define RSCAN0RMPTR21 RSCAN0.RMPTR21.UINT32
    4472 #define RSCAN0RMPTR21L RSCAN0.RMPTR21.UINT16[L]
    4473 #define RSCAN0RMPTR21LL RSCAN0.RMPTR21.UINT8[LL]
    4474 #define RSCAN0RMPTR21LH RSCAN0.RMPTR21.UINT8[LH]
    4475 #define RSCAN0RMPTR21H RSCAN0.RMPTR21.UINT16[H]
    4476 #define RSCAN0RMPTR21HL RSCAN0.RMPTR21.UINT8[HL]
    4477 #define RSCAN0RMPTR21HH RSCAN0.RMPTR21.UINT8[HH]
    4478 #define RSCAN0RMDF021 RSCAN0.RMDF021.UINT32
    4479 #define RSCAN0RMDF021L RSCAN0.RMDF021.UINT16[L]
    4480 #define RSCAN0RMDF021LL RSCAN0.RMDF021.UINT8[LL]
    4481 #define RSCAN0RMDF021LH RSCAN0.RMDF021.UINT8[LH]
    4482 #define RSCAN0RMDF021H RSCAN0.RMDF021.UINT16[H]
    4483 #define RSCAN0RMDF021HL RSCAN0.RMDF021.UINT8[HL]
    4484 #define RSCAN0RMDF021HH RSCAN0.RMDF021.UINT8[HH]
    4485 #define RSCAN0RMDF121 RSCAN0.RMDF121.UINT32
    4486 #define RSCAN0RMDF121L RSCAN0.RMDF121.UINT16[L]
    4487 #define RSCAN0RMDF121LL RSCAN0.RMDF121.UINT8[LL]
    4488 #define RSCAN0RMDF121LH RSCAN0.RMDF121.UINT8[LH]
    4489 #define RSCAN0RMDF121H RSCAN0.RMDF121.UINT16[H]
    4490 #define RSCAN0RMDF121HL RSCAN0.RMDF121.UINT8[HL]
    4491 #define RSCAN0RMDF121HH RSCAN0.RMDF121.UINT8[HH]
    4492 #define RSCAN0RMID22 RSCAN0.RMID22.UINT32
    4493 #define RSCAN0RMID22L RSCAN0.RMID22.UINT16[L]
    4494 #define RSCAN0RMID22LL RSCAN0.RMID22.UINT8[LL]
    4495 #define RSCAN0RMID22LH RSCAN0.RMID22.UINT8[LH]
    4496 #define RSCAN0RMID22H RSCAN0.RMID22.UINT16[H]
    4497 #define RSCAN0RMID22HL RSCAN0.RMID22.UINT8[HL]
    4498 #define RSCAN0RMID22HH RSCAN0.RMID22.UINT8[HH]
    4499 #define RSCAN0RMPTR22 RSCAN0.RMPTR22.UINT32
    4500 #define RSCAN0RMPTR22L RSCAN0.RMPTR22.UINT16[L]
    4501 #define RSCAN0RMPTR22LL RSCAN0.RMPTR22.UINT8[LL]
    4502 #define RSCAN0RMPTR22LH RSCAN0.RMPTR22.UINT8[LH]
    4503 #define RSCAN0RMPTR22H RSCAN0.RMPTR22.UINT16[H]
    4504 #define RSCAN0RMPTR22HL RSCAN0.RMPTR22.UINT8[HL]
    4505 #define RSCAN0RMPTR22HH RSCAN0.RMPTR22.UINT8[HH]
    4506 #define RSCAN0RMDF022 RSCAN0.RMDF022.UINT32
    4507 #define RSCAN0RMDF022L RSCAN0.RMDF022.UINT16[L]
    4508 #define RSCAN0RMDF022LL RSCAN0.RMDF022.UINT8[LL]
    4509 #define RSCAN0RMDF022LH RSCAN0.RMDF022.UINT8[LH]
    4510 #define RSCAN0RMDF022H RSCAN0.RMDF022.UINT16[H]
    4511 #define RSCAN0RMDF022HL RSCAN0.RMDF022.UINT8[HL]
    4512 #define RSCAN0RMDF022HH RSCAN0.RMDF022.UINT8[HH]
    4513 #define RSCAN0RMDF122 RSCAN0.RMDF122.UINT32
    4514 #define RSCAN0RMDF122L RSCAN0.RMDF122.UINT16[L]
    4515 #define RSCAN0RMDF122LL RSCAN0.RMDF122.UINT8[LL]
    4516 #define RSCAN0RMDF122LH RSCAN0.RMDF122.UINT8[LH]
    4517 #define RSCAN0RMDF122H RSCAN0.RMDF122.UINT16[H]
    4518 #define RSCAN0RMDF122HL RSCAN0.RMDF122.UINT8[HL]
    4519 #define RSCAN0RMDF122HH RSCAN0.RMDF122.UINT8[HH]
    4520 #define RSCAN0RMID23 RSCAN0.RMID23.UINT32
    4521 #define RSCAN0RMID23L RSCAN0.RMID23.UINT16[L]
    4522 #define RSCAN0RMID23LL RSCAN0.RMID23.UINT8[LL]
    4523 #define RSCAN0RMID23LH RSCAN0.RMID23.UINT8[LH]
    4524 #define RSCAN0RMID23H RSCAN0.RMID23.UINT16[H]
    4525 #define RSCAN0RMID23HL RSCAN0.RMID23.UINT8[HL]
    4526 #define RSCAN0RMID23HH RSCAN0.RMID23.UINT8[HH]
    4527 #define RSCAN0RMPTR23 RSCAN0.RMPTR23.UINT32
    4528 #define RSCAN0RMPTR23L RSCAN0.RMPTR23.UINT16[L]
    4529 #define RSCAN0RMPTR23LL RSCAN0.RMPTR23.UINT8[LL]
    4530 #define RSCAN0RMPTR23LH RSCAN0.RMPTR23.UINT8[LH]
    4531 #define RSCAN0RMPTR23H RSCAN0.RMPTR23.UINT16[H]
    4532 #define RSCAN0RMPTR23HL RSCAN0.RMPTR23.UINT8[HL]
    4533 #define RSCAN0RMPTR23HH RSCAN0.RMPTR23.UINT8[HH]
    4534 #define RSCAN0RMDF023 RSCAN0.RMDF023.UINT32
    4535 #define RSCAN0RMDF023L RSCAN0.RMDF023.UINT16[L]
    4536 #define RSCAN0RMDF023LL RSCAN0.RMDF023.UINT8[LL]
    4537 #define RSCAN0RMDF023LH RSCAN0.RMDF023.UINT8[LH]
    4538 #define RSCAN0RMDF023H RSCAN0.RMDF023.UINT16[H]
    4539 #define RSCAN0RMDF023HL RSCAN0.RMDF023.UINT8[HL]
    4540 #define RSCAN0RMDF023HH RSCAN0.RMDF023.UINT8[HH]
    4541 #define RSCAN0RMDF123 RSCAN0.RMDF123.UINT32
    4542 #define RSCAN0RMDF123L RSCAN0.RMDF123.UINT16[L]
    4543 #define RSCAN0RMDF123LL RSCAN0.RMDF123.UINT8[LL]
    4544 #define RSCAN0RMDF123LH RSCAN0.RMDF123.UINT8[LH]
    4545 #define RSCAN0RMDF123H RSCAN0.RMDF123.UINT16[H]
    4546 #define RSCAN0RMDF123HL RSCAN0.RMDF123.UINT8[HL]
    4547 #define RSCAN0RMDF123HH RSCAN0.RMDF123.UINT8[HH]
    4548 #define RSCAN0RMID24 RSCAN0.RMID24.UINT32
    4549 #define RSCAN0RMID24L RSCAN0.RMID24.UINT16[L]
    4550 #define RSCAN0RMID24LL RSCAN0.RMID24.UINT8[LL]
    4551 #define RSCAN0RMID24LH RSCAN0.RMID24.UINT8[LH]
    4552 #define RSCAN0RMID24H RSCAN0.RMID24.UINT16[H]
    4553 #define RSCAN0RMID24HL RSCAN0.RMID24.UINT8[HL]
    4554 #define RSCAN0RMID24HH RSCAN0.RMID24.UINT8[HH]
    4555 #define RSCAN0RMPTR24 RSCAN0.RMPTR24.UINT32
    4556 #define RSCAN0RMPTR24L RSCAN0.RMPTR24.UINT16[L]
    4557 #define RSCAN0RMPTR24LL RSCAN0.RMPTR24.UINT8[LL]
    4558 #define RSCAN0RMPTR24LH RSCAN0.RMPTR24.UINT8[LH]
    4559 #define RSCAN0RMPTR24H RSCAN0.RMPTR24.UINT16[H]
    4560 #define RSCAN0RMPTR24HL RSCAN0.RMPTR24.UINT8[HL]
    4561 #define RSCAN0RMPTR24HH RSCAN0.RMPTR24.UINT8[HH]
    4562 #define RSCAN0RMDF024 RSCAN0.RMDF024.UINT32
    4563 #define RSCAN0RMDF024L RSCAN0.RMDF024.UINT16[L]
    4564 #define RSCAN0RMDF024LL RSCAN0.RMDF024.UINT8[LL]
    4565 #define RSCAN0RMDF024LH RSCAN0.RMDF024.UINT8[LH]
    4566 #define RSCAN0RMDF024H RSCAN0.RMDF024.UINT16[H]
    4567 #define RSCAN0RMDF024HL RSCAN0.RMDF024.UINT8[HL]
    4568 #define RSCAN0RMDF024HH RSCAN0.RMDF024.UINT8[HH]
    4569 #define RSCAN0RMDF124 RSCAN0.RMDF124.UINT32
    4570 #define RSCAN0RMDF124L RSCAN0.RMDF124.UINT16[L]
    4571 #define RSCAN0RMDF124LL RSCAN0.RMDF124.UINT8[LL]
    4572 #define RSCAN0RMDF124LH RSCAN0.RMDF124.UINT8[LH]
    4573 #define RSCAN0RMDF124H RSCAN0.RMDF124.UINT16[H]
    4574 #define RSCAN0RMDF124HL RSCAN0.RMDF124.UINT8[HL]
    4575 #define RSCAN0RMDF124HH RSCAN0.RMDF124.UINT8[HH]
    4576 #define RSCAN0RMID25 RSCAN0.RMID25.UINT32
    4577 #define RSCAN0RMID25L RSCAN0.RMID25.UINT16[L]
    4578 #define RSCAN0RMID25LL RSCAN0.RMID25.UINT8[LL]
    4579 #define RSCAN0RMID25LH RSCAN0.RMID25.UINT8[LH]
    4580 #define RSCAN0RMID25H RSCAN0.RMID25.UINT16[H]
    4581 #define RSCAN0RMID25HL RSCAN0.RMID25.UINT8[HL]
    4582 #define RSCAN0RMID25HH RSCAN0.RMID25.UINT8[HH]
    4583 #define RSCAN0RMPTR25 RSCAN0.RMPTR25.UINT32
    4584 #define RSCAN0RMPTR25L RSCAN0.RMPTR25.UINT16[L]
    4585 #define RSCAN0RMPTR25LL RSCAN0.RMPTR25.UINT8[LL]
    4586 #define RSCAN0RMPTR25LH RSCAN0.RMPTR25.UINT8[LH]
    4587 #define RSCAN0RMPTR25H RSCAN0.RMPTR25.UINT16[H]
    4588 #define RSCAN0RMPTR25HL RSCAN0.RMPTR25.UINT8[HL]
    4589 #define RSCAN0RMPTR25HH RSCAN0.RMPTR25.UINT8[HH]
    4590 #define RSCAN0RMDF025 RSCAN0.RMDF025.UINT32
    4591 #define RSCAN0RMDF025L RSCAN0.RMDF025.UINT16[L]
    4592 #define RSCAN0RMDF025LL RSCAN0.RMDF025.UINT8[LL]
    4593 #define RSCAN0RMDF025LH RSCAN0.RMDF025.UINT8[LH]
    4594 #define RSCAN0RMDF025H RSCAN0.RMDF025.UINT16[H]
    4595 #define RSCAN0RMDF025HL RSCAN0.RMDF025.UINT8[HL]
    4596 #define RSCAN0RMDF025HH RSCAN0.RMDF025.UINT8[HH]
    4597 #define RSCAN0RMDF125 RSCAN0.RMDF125.UINT32
    4598 #define RSCAN0RMDF125L RSCAN0.RMDF125.UINT16[L]
    4599 #define RSCAN0RMDF125LL RSCAN0.RMDF125.UINT8[LL]
    4600 #define RSCAN0RMDF125LH RSCAN0.RMDF125.UINT8[LH]
    4601 #define RSCAN0RMDF125H RSCAN0.RMDF125.UINT16[H]
    4602 #define RSCAN0RMDF125HL RSCAN0.RMDF125.UINT8[HL]
    4603 #define RSCAN0RMDF125HH RSCAN0.RMDF125.UINT8[HH]
    4604 #define RSCAN0RMID26 RSCAN0.RMID26.UINT32
    4605 #define RSCAN0RMID26L RSCAN0.RMID26.UINT16[L]
    4606 #define RSCAN0RMID26LL RSCAN0.RMID26.UINT8[LL]
    4607 #define RSCAN0RMID26LH RSCAN0.RMID26.UINT8[LH]
    4608 #define RSCAN0RMID26H RSCAN0.RMID26.UINT16[H]
    4609 #define RSCAN0RMID26HL RSCAN0.RMID26.UINT8[HL]
    4610 #define RSCAN0RMID26HH RSCAN0.RMID26.UINT8[HH]
    4611 #define RSCAN0RMPTR26 RSCAN0.RMPTR26.UINT32
    4612 #define RSCAN0RMPTR26L RSCAN0.RMPTR26.UINT16[L]
    4613 #define RSCAN0RMPTR26LL RSCAN0.RMPTR26.UINT8[LL]
    4614 #define RSCAN0RMPTR26LH RSCAN0.RMPTR26.UINT8[LH]
    4615 #define RSCAN0RMPTR26H RSCAN0.RMPTR26.UINT16[H]
    4616 #define RSCAN0RMPTR26HL RSCAN0.RMPTR26.UINT8[HL]
    4617 #define RSCAN0RMPTR26HH RSCAN0.RMPTR26.UINT8[HH]
    4618 #define RSCAN0RMDF026 RSCAN0.RMDF026.UINT32
    4619 #define RSCAN0RMDF026L RSCAN0.RMDF026.UINT16[L]
    4620 #define RSCAN0RMDF026LL RSCAN0.RMDF026.UINT8[LL]
    4621 #define RSCAN0RMDF026LH RSCAN0.RMDF026.UINT8[LH]
    4622 #define RSCAN0RMDF026H RSCAN0.RMDF026.UINT16[H]
    4623 #define RSCAN0RMDF026HL RSCAN0.RMDF026.UINT8[HL]
    4624 #define RSCAN0RMDF026HH RSCAN0.RMDF026.UINT8[HH]
    4625 #define RSCAN0RMDF126 RSCAN0.RMDF126.UINT32
    4626 #define RSCAN0RMDF126L RSCAN0.RMDF126.UINT16[L]
    4627 #define RSCAN0RMDF126LL RSCAN0.RMDF126.UINT8[LL]
    4628 #define RSCAN0RMDF126LH RSCAN0.RMDF126.UINT8[LH]
    4629 #define RSCAN0RMDF126H RSCAN0.RMDF126.UINT16[H]
    4630 #define RSCAN0RMDF126HL RSCAN0.RMDF126.UINT8[HL]
    4631 #define RSCAN0RMDF126HH RSCAN0.RMDF126.UINT8[HH]
    4632 #define RSCAN0RMID27 RSCAN0.RMID27.UINT32
    4633 #define RSCAN0RMID27L RSCAN0.RMID27.UINT16[L]
    4634 #define RSCAN0RMID27LL RSCAN0.RMID27.UINT8[LL]
    4635 #define RSCAN0RMID27LH RSCAN0.RMID27.UINT8[LH]
    4636 #define RSCAN0RMID27H RSCAN0.RMID27.UINT16[H]
    4637 #define RSCAN0RMID27HL RSCAN0.RMID27.UINT8[HL]
    4638 #define RSCAN0RMID27HH RSCAN0.RMID27.UINT8[HH]
    4639 #define RSCAN0RMPTR27 RSCAN0.RMPTR27.UINT32
    4640 #define RSCAN0RMPTR27L RSCAN0.RMPTR27.UINT16[L]
    4641 #define RSCAN0RMPTR27LL RSCAN0.RMPTR27.UINT8[LL]
    4642 #define RSCAN0RMPTR27LH RSCAN0.RMPTR27.UINT8[LH]
    4643 #define RSCAN0RMPTR27H RSCAN0.RMPTR27.UINT16[H]
    4644 #define RSCAN0RMPTR27HL RSCAN0.RMPTR27.UINT8[HL]
    4645 #define RSCAN0RMPTR27HH RSCAN0.RMPTR27.UINT8[HH]
    4646 #define RSCAN0RMDF027 RSCAN0.RMDF027.UINT32
    4647 #define RSCAN0RMDF027L RSCAN0.RMDF027.UINT16[L]
    4648 #define RSCAN0RMDF027LL RSCAN0.RMDF027.UINT8[LL]
    4649 #define RSCAN0RMDF027LH RSCAN0.RMDF027.UINT8[LH]
    4650 #define RSCAN0RMDF027H RSCAN0.RMDF027.UINT16[H]
    4651 #define RSCAN0RMDF027HL RSCAN0.RMDF027.UINT8[HL]
    4652 #define RSCAN0RMDF027HH RSCAN0.RMDF027.UINT8[HH]
    4653 #define RSCAN0RMDF127 RSCAN0.RMDF127.UINT32
    4654 #define RSCAN0RMDF127L RSCAN0.RMDF127.UINT16[L]
    4655 #define RSCAN0RMDF127LL RSCAN0.RMDF127.UINT8[LL]
    4656 #define RSCAN0RMDF127LH RSCAN0.RMDF127.UINT8[LH]
    4657 #define RSCAN0RMDF127H RSCAN0.RMDF127.UINT16[H]
    4658 #define RSCAN0RMDF127HL RSCAN0.RMDF127.UINT8[HL]
    4659 #define RSCAN0RMDF127HH RSCAN0.RMDF127.UINT8[HH]
    4660 #define RSCAN0RMID28 RSCAN0.RMID28.UINT32
    4661 #define RSCAN0RMID28L RSCAN0.RMID28.UINT16[L]
    4662 #define RSCAN0RMID28LL RSCAN0.RMID28.UINT8[LL]
    4663 #define RSCAN0RMID28LH RSCAN0.RMID28.UINT8[LH]
    4664 #define RSCAN0RMID28H RSCAN0.RMID28.UINT16[H]
    4665 #define RSCAN0RMID28HL RSCAN0.RMID28.UINT8[HL]
    4666 #define RSCAN0RMID28HH RSCAN0.RMID28.UINT8[HH]
    4667 #define RSCAN0RMPTR28 RSCAN0.RMPTR28.UINT32
    4668 #define RSCAN0RMPTR28L RSCAN0.RMPTR28.UINT16[L]
    4669 #define RSCAN0RMPTR28LL RSCAN0.RMPTR28.UINT8[LL]
    4670 #define RSCAN0RMPTR28LH RSCAN0.RMPTR28.UINT8[LH]
    4671 #define RSCAN0RMPTR28H RSCAN0.RMPTR28.UINT16[H]
    4672 #define RSCAN0RMPTR28HL RSCAN0.RMPTR28.UINT8[HL]
    4673 #define RSCAN0RMPTR28HH RSCAN0.RMPTR28.UINT8[HH]
    4674 #define RSCAN0RMDF028 RSCAN0.RMDF028.UINT32
    4675 #define RSCAN0RMDF028L RSCAN0.RMDF028.UINT16[L]
    4676 #define RSCAN0RMDF028LL RSCAN0.RMDF028.UINT8[LL]
    4677 #define RSCAN0RMDF028LH RSCAN0.RMDF028.UINT8[LH]
    4678 #define RSCAN0RMDF028H RSCAN0.RMDF028.UINT16[H]
    4679 #define RSCAN0RMDF028HL RSCAN0.RMDF028.UINT8[HL]
    4680 #define RSCAN0RMDF028HH RSCAN0.RMDF028.UINT8[HH]
    4681 #define RSCAN0RMDF128 RSCAN0.RMDF128.UINT32
    4682 #define RSCAN0RMDF128L RSCAN0.RMDF128.UINT16[L]
    4683 #define RSCAN0RMDF128LL RSCAN0.RMDF128.UINT8[LL]
    4684 #define RSCAN0RMDF128LH RSCAN0.RMDF128.UINT8[LH]
    4685 #define RSCAN0RMDF128H RSCAN0.RMDF128.UINT16[H]
    4686 #define RSCAN0RMDF128HL RSCAN0.RMDF128.UINT8[HL]
    4687 #define RSCAN0RMDF128HH RSCAN0.RMDF128.UINT8[HH]
    4688 #define RSCAN0RMID29 RSCAN0.RMID29.UINT32
    4689 #define RSCAN0RMID29L RSCAN0.RMID29.UINT16[L]
    4690 #define RSCAN0RMID29LL RSCAN0.RMID29.UINT8[LL]
    4691 #define RSCAN0RMID29LH RSCAN0.RMID29.UINT8[LH]
    4692 #define RSCAN0RMID29H RSCAN0.RMID29.UINT16[H]
    4693 #define RSCAN0RMID29HL RSCAN0.RMID29.UINT8[HL]
    4694 #define RSCAN0RMID29HH RSCAN0.RMID29.UINT8[HH]
    4695 #define RSCAN0RMPTR29 RSCAN0.RMPTR29.UINT32
    4696 #define RSCAN0RMPTR29L RSCAN0.RMPTR29.UINT16[L]
    4697 #define RSCAN0RMPTR29LL RSCAN0.RMPTR29.UINT8[LL]
    4698 #define RSCAN0RMPTR29LH RSCAN0.RMPTR29.UINT8[LH]
    4699 #define RSCAN0RMPTR29H RSCAN0.RMPTR29.UINT16[H]
    4700 #define RSCAN0RMPTR29HL RSCAN0.RMPTR29.UINT8[HL]
    4701 #define RSCAN0RMPTR29HH RSCAN0.RMPTR29.UINT8[HH]
    4702 #define RSCAN0RMDF029 RSCAN0.RMDF029.UINT32
    4703 #define RSCAN0RMDF029L RSCAN0.RMDF029.UINT16[L]
    4704 #define RSCAN0RMDF029LL RSCAN0.RMDF029.UINT8[LL]
    4705 #define RSCAN0RMDF029LH RSCAN0.RMDF029.UINT8[LH]
    4706 #define RSCAN0RMDF029H RSCAN0.RMDF029.UINT16[H]
    4707 #define RSCAN0RMDF029HL RSCAN0.RMDF029.UINT8[HL]
    4708 #define RSCAN0RMDF029HH RSCAN0.RMDF029.UINT8[HH]
    4709 #define RSCAN0RMDF129 RSCAN0.RMDF129.UINT32
    4710 #define RSCAN0RMDF129L RSCAN0.RMDF129.UINT16[L]
    4711 #define RSCAN0RMDF129LL RSCAN0.RMDF129.UINT8[LL]
    4712 #define RSCAN0RMDF129LH RSCAN0.RMDF129.UINT8[LH]
    4713 #define RSCAN0RMDF129H RSCAN0.RMDF129.UINT16[H]
    4714 #define RSCAN0RMDF129HL RSCAN0.RMDF129.UINT8[HL]
    4715 #define RSCAN0RMDF129HH RSCAN0.RMDF129.UINT8[HH]
    4716 #define RSCAN0RMID30 RSCAN0.RMID30.UINT32
    4717 #define RSCAN0RMID30L RSCAN0.RMID30.UINT16[L]
    4718 #define RSCAN0RMID30LL RSCAN0.RMID30.UINT8[LL]
    4719 #define RSCAN0RMID30LH RSCAN0.RMID30.UINT8[LH]
    4720 #define RSCAN0RMID30H RSCAN0.RMID30.UINT16[H]
    4721 #define RSCAN0RMID30HL RSCAN0.RMID30.UINT8[HL]
    4722 #define RSCAN0RMID30HH RSCAN0.RMID30.UINT8[HH]
    4723 #define RSCAN0RMPTR30 RSCAN0.RMPTR30.UINT32
    4724 #define RSCAN0RMPTR30L RSCAN0.RMPTR30.UINT16[L]
    4725 #define RSCAN0RMPTR30LL RSCAN0.RMPTR30.UINT8[LL]
    4726 #define RSCAN0RMPTR30LH RSCAN0.RMPTR30.UINT8[LH]
    4727 #define RSCAN0RMPTR30H RSCAN0.RMPTR30.UINT16[H]
    4728 #define RSCAN0RMPTR30HL RSCAN0.RMPTR30.UINT8[HL]
    4729 #define RSCAN0RMPTR30HH RSCAN0.RMPTR30.UINT8[HH]
    4730 #define RSCAN0RMDF030 RSCAN0.RMDF030.UINT32
    4731 #define RSCAN0RMDF030L RSCAN0.RMDF030.UINT16[L]
    4732 #define RSCAN0RMDF030LL RSCAN0.RMDF030.UINT8[LL]
    4733 #define RSCAN0RMDF030LH RSCAN0.RMDF030.UINT8[LH]
    4734 #define RSCAN0RMDF030H RSCAN0.RMDF030.UINT16[H]
    4735 #define RSCAN0RMDF030HL RSCAN0.RMDF030.UINT8[HL]
    4736 #define RSCAN0RMDF030HH RSCAN0.RMDF030.UINT8[HH]
    4737 #define RSCAN0RMDF130 RSCAN0.RMDF130.UINT32
    4738 #define RSCAN0RMDF130L RSCAN0.RMDF130.UINT16[L]
    4739 #define RSCAN0RMDF130LL RSCAN0.RMDF130.UINT8[LL]
    4740 #define RSCAN0RMDF130LH RSCAN0.RMDF130.UINT8[LH]
    4741 #define RSCAN0RMDF130H RSCAN0.RMDF130.UINT16[H]
    4742 #define RSCAN0RMDF130HL RSCAN0.RMDF130.UINT8[HL]
    4743 #define RSCAN0RMDF130HH RSCAN0.RMDF130.UINT8[HH]
    4744 #define RSCAN0RMID31 RSCAN0.RMID31.UINT32
    4745 #define RSCAN0RMID31L RSCAN0.RMID31.UINT16[L]
    4746 #define RSCAN0RMID31LL RSCAN0.RMID31.UINT8[LL]
    4747 #define RSCAN0RMID31LH RSCAN0.RMID31.UINT8[LH]
    4748 #define RSCAN0RMID31H RSCAN0.RMID31.UINT16[H]
    4749 #define RSCAN0RMID31HL RSCAN0.RMID31.UINT8[HL]
    4750 #define RSCAN0RMID31HH RSCAN0.RMID31.UINT8[HH]
    4751 #define RSCAN0RMPTR31 RSCAN0.RMPTR31.UINT32
    4752 #define RSCAN0RMPTR31L RSCAN0.RMPTR31.UINT16[L]
    4753 #define RSCAN0RMPTR31LL RSCAN0.RMPTR31.UINT8[LL]
    4754 #define RSCAN0RMPTR31LH RSCAN0.RMPTR31.UINT8[LH]
    4755 #define RSCAN0RMPTR31H RSCAN0.RMPTR31.UINT16[H]
    4756 #define RSCAN0RMPTR31HL RSCAN0.RMPTR31.UINT8[HL]
    4757 #define RSCAN0RMPTR31HH RSCAN0.RMPTR31.UINT8[HH]
    4758 #define RSCAN0RMDF031 RSCAN0.RMDF031.UINT32
    4759 #define RSCAN0RMDF031L RSCAN0.RMDF031.UINT16[L]
    4760 #define RSCAN0RMDF031LL RSCAN0.RMDF031.UINT8[LL]
    4761 #define RSCAN0RMDF031LH RSCAN0.RMDF031.UINT8[LH]
    4762 #define RSCAN0RMDF031H RSCAN0.RMDF031.UINT16[H]
    4763 #define RSCAN0RMDF031HL RSCAN0.RMDF031.UINT8[HL]
    4764 #define RSCAN0RMDF031HH RSCAN0.RMDF031.UINT8[HH]
    4765 #define RSCAN0RMDF131 RSCAN0.RMDF131.UINT32
    4766 #define RSCAN0RMDF131L RSCAN0.RMDF131.UINT16[L]
    4767 #define RSCAN0RMDF131LL RSCAN0.RMDF131.UINT8[LL]
    4768 #define RSCAN0RMDF131LH RSCAN0.RMDF131.UINT8[LH]
    4769 #define RSCAN0RMDF131H RSCAN0.RMDF131.UINT16[H]
    4770 #define RSCAN0RMDF131HL RSCAN0.RMDF131.UINT8[HL]
    4771 #define RSCAN0RMDF131HH RSCAN0.RMDF131.UINT8[HH]
    4772 #define RSCAN0RMID32 RSCAN0.RMID32.UINT32
    4773 #define RSCAN0RMID32L RSCAN0.RMID32.UINT16[L]
    4774 #define RSCAN0RMID32LL RSCAN0.RMID32.UINT8[LL]
    4775 #define RSCAN0RMID32LH RSCAN0.RMID32.UINT8[LH]
    4776 #define RSCAN0RMID32H RSCAN0.RMID32.UINT16[H]
    4777 #define RSCAN0RMID32HL RSCAN0.RMID32.UINT8[HL]
    4778 #define RSCAN0RMID32HH RSCAN0.RMID32.UINT8[HH]
    4779 #define RSCAN0RMPTR32 RSCAN0.RMPTR32.UINT32
    4780 #define RSCAN0RMPTR32L RSCAN0.RMPTR32.UINT16[L]
    4781 #define RSCAN0RMPTR32LL RSCAN0.RMPTR32.UINT8[LL]
    4782 #define RSCAN0RMPTR32LH RSCAN0.RMPTR32.UINT8[LH]
    4783 #define RSCAN0RMPTR32H RSCAN0.RMPTR32.UINT16[H]
    4784 #define RSCAN0RMPTR32HL RSCAN0.RMPTR32.UINT8[HL]
    4785 #define RSCAN0RMPTR32HH RSCAN0.RMPTR32.UINT8[HH]
    4786 #define RSCAN0RMDF032 RSCAN0.RMDF032.UINT32
    4787 #define RSCAN0RMDF032L RSCAN0.RMDF032.UINT16[L]
    4788 #define RSCAN0RMDF032LL RSCAN0.RMDF032.UINT8[LL]
    4789 #define RSCAN0RMDF032LH RSCAN0.RMDF032.UINT8[LH]
    4790 #define RSCAN0RMDF032H RSCAN0.RMDF032.UINT16[H]
    4791 #define RSCAN0RMDF032HL RSCAN0.RMDF032.UINT8[HL]
    4792 #define RSCAN0RMDF032HH RSCAN0.RMDF032.UINT8[HH]
    4793 #define RSCAN0RMDF132 RSCAN0.RMDF132.UINT32
    4794 #define RSCAN0RMDF132L RSCAN0.RMDF132.UINT16[L]
    4795 #define RSCAN0RMDF132LL RSCAN0.RMDF132.UINT8[LL]
    4796 #define RSCAN0RMDF132LH RSCAN0.RMDF132.UINT8[LH]
    4797 #define RSCAN0RMDF132H RSCAN0.RMDF132.UINT16[H]
    4798 #define RSCAN0RMDF132HL RSCAN0.RMDF132.UINT8[HL]
    4799 #define RSCAN0RMDF132HH RSCAN0.RMDF132.UINT8[HH]
    4800 #define RSCAN0RMID33 RSCAN0.RMID33.UINT32
    4801 #define RSCAN0RMID33L RSCAN0.RMID33.UINT16[L]
    4802 #define RSCAN0RMID33LL RSCAN0.RMID33.UINT8[LL]
    4803 #define RSCAN0RMID33LH RSCAN0.RMID33.UINT8[LH]
    4804 #define RSCAN0RMID33H RSCAN0.RMID33.UINT16[H]
    4805 #define RSCAN0RMID33HL RSCAN0.RMID33.UINT8[HL]
    4806 #define RSCAN0RMID33HH RSCAN0.RMID33.UINT8[HH]
    4807 #define RSCAN0RMPTR33 RSCAN0.RMPTR33.UINT32
    4808 #define RSCAN0RMPTR33L RSCAN0.RMPTR33.UINT16[L]
    4809 #define RSCAN0RMPTR33LL RSCAN0.RMPTR33.UINT8[LL]
    4810 #define RSCAN0RMPTR33LH RSCAN0.RMPTR33.UINT8[LH]
    4811 #define RSCAN0RMPTR33H RSCAN0.RMPTR33.UINT16[H]
    4812 #define RSCAN0RMPTR33HL RSCAN0.RMPTR33.UINT8[HL]
    4813 #define RSCAN0RMPTR33HH RSCAN0.RMPTR33.UINT8[HH]
    4814 #define RSCAN0RMDF033 RSCAN0.RMDF033.UINT32
    4815 #define RSCAN0RMDF033L RSCAN0.RMDF033.UINT16[L]
    4816 #define RSCAN0RMDF033LL RSCAN0.RMDF033.UINT8[LL]
    4817 #define RSCAN0RMDF033LH RSCAN0.RMDF033.UINT8[LH]
    4818 #define RSCAN0RMDF033H RSCAN0.RMDF033.UINT16[H]
    4819 #define RSCAN0RMDF033HL RSCAN0.RMDF033.UINT8[HL]
    4820 #define RSCAN0RMDF033HH RSCAN0.RMDF033.UINT8[HH]
    4821 #define RSCAN0RMDF133 RSCAN0.RMDF133.UINT32
    4822 #define RSCAN0RMDF133L RSCAN0.RMDF133.UINT16[L]
    4823 #define RSCAN0RMDF133LL RSCAN0.RMDF133.UINT8[LL]
    4824 #define RSCAN0RMDF133LH RSCAN0.RMDF133.UINT8[LH]
    4825 #define RSCAN0RMDF133H RSCAN0.RMDF133.UINT16[H]
    4826 #define RSCAN0RMDF133HL RSCAN0.RMDF133.UINT8[HL]
    4827 #define RSCAN0RMDF133HH RSCAN0.RMDF133.UINT8[HH]
    4828 #define RSCAN0RMID34 RSCAN0.RMID34.UINT32
    4829 #define RSCAN0RMID34L RSCAN0.RMID34.UINT16[L]
    4830 #define RSCAN0RMID34LL RSCAN0.RMID34.UINT8[LL]
    4831 #define RSCAN0RMID34LH RSCAN0.RMID34.UINT8[LH]
    4832 #define RSCAN0RMID34H RSCAN0.RMID34.UINT16[H]
    4833 #define RSCAN0RMID34HL RSCAN0.RMID34.UINT8[HL]
    4834 #define RSCAN0RMID34HH RSCAN0.RMID34.UINT8[HH]
    4835 #define RSCAN0RMPTR34 RSCAN0.RMPTR34.UINT32
    4836 #define RSCAN0RMPTR34L RSCAN0.RMPTR34.UINT16[L]
    4837 #define RSCAN0RMPTR34LL RSCAN0.RMPTR34.UINT8[LL]
    4838 #define RSCAN0RMPTR34LH RSCAN0.RMPTR34.UINT8[LH]
    4839 #define RSCAN0RMPTR34H RSCAN0.RMPTR34.UINT16[H]
    4840 #define RSCAN0RMPTR34HL RSCAN0.RMPTR34.UINT8[HL]
    4841 #define RSCAN0RMPTR34HH RSCAN0.RMPTR34.UINT8[HH]
    4842 #define RSCAN0RMDF034 RSCAN0.RMDF034.UINT32
    4843 #define RSCAN0RMDF034L RSCAN0.RMDF034.UINT16[L]
    4844 #define RSCAN0RMDF034LL RSCAN0.RMDF034.UINT8[LL]
    4845 #define RSCAN0RMDF034LH RSCAN0.RMDF034.UINT8[LH]
    4846 #define RSCAN0RMDF034H RSCAN0.RMDF034.UINT16[H]
    4847 #define RSCAN0RMDF034HL RSCAN0.RMDF034.UINT8[HL]
    4848 #define RSCAN0RMDF034HH RSCAN0.RMDF034.UINT8[HH]
    4849 #define RSCAN0RMDF134 RSCAN0.RMDF134.UINT32
    4850 #define RSCAN0RMDF134L RSCAN0.RMDF134.UINT16[L]
    4851 #define RSCAN0RMDF134LL RSCAN0.RMDF134.UINT8[LL]
    4852 #define RSCAN0RMDF134LH RSCAN0.RMDF134.UINT8[LH]
    4853 #define RSCAN0RMDF134H RSCAN0.RMDF134.UINT16[H]
    4854 #define RSCAN0RMDF134HL RSCAN0.RMDF134.UINT8[HL]
    4855 #define RSCAN0RMDF134HH RSCAN0.RMDF134.UINT8[HH]
    4856 #define RSCAN0RMID35 RSCAN0.RMID35.UINT32
    4857 #define RSCAN0RMID35L RSCAN0.RMID35.UINT16[L]
    4858 #define RSCAN0RMID35LL RSCAN0.RMID35.UINT8[LL]
    4859 #define RSCAN0RMID35LH RSCAN0.RMID35.UINT8[LH]
    4860 #define RSCAN0RMID35H RSCAN0.RMID35.UINT16[H]
    4861 #define RSCAN0RMID35HL RSCAN0.RMID35.UINT8[HL]
    4862 #define RSCAN0RMID35HH RSCAN0.RMID35.UINT8[HH]
    4863 #define RSCAN0RMPTR35 RSCAN0.RMPTR35.UINT32
    4864 #define RSCAN0RMPTR35L RSCAN0.RMPTR35.UINT16[L]
    4865 #define RSCAN0RMPTR35LL RSCAN0.RMPTR35.UINT8[LL]
    4866 #define RSCAN0RMPTR35LH RSCAN0.RMPTR35.UINT8[LH]
    4867 #define RSCAN0RMPTR35H RSCAN0.RMPTR35.UINT16[H]
    4868 #define RSCAN0RMPTR35HL RSCAN0.RMPTR35.UINT8[HL]
    4869 #define RSCAN0RMPTR35HH RSCAN0.RMPTR35.UINT8[HH]
    4870 #define RSCAN0RMDF035 RSCAN0.RMDF035.UINT32
    4871 #define RSCAN0RMDF035L RSCAN0.RMDF035.UINT16[L]
    4872 #define RSCAN0RMDF035LL RSCAN0.RMDF035.UINT8[LL]
    4873 #define RSCAN0RMDF035LH RSCAN0.RMDF035.UINT8[LH]
    4874 #define RSCAN0RMDF035H RSCAN0.RMDF035.UINT16[H]
    4875 #define RSCAN0RMDF035HL RSCAN0.RMDF035.UINT8[HL]
    4876 #define RSCAN0RMDF035HH RSCAN0.RMDF035.UINT8[HH]
    4877 #define RSCAN0RMDF135 RSCAN0.RMDF135.UINT32
    4878 #define RSCAN0RMDF135L RSCAN0.RMDF135.UINT16[L]
    4879 #define RSCAN0RMDF135LL RSCAN0.RMDF135.UINT8[LL]
    4880 #define RSCAN0RMDF135LH RSCAN0.RMDF135.UINT8[LH]
    4881 #define RSCAN0RMDF135H RSCAN0.RMDF135.UINT16[H]
    4882 #define RSCAN0RMDF135HL RSCAN0.RMDF135.UINT8[HL]
    4883 #define RSCAN0RMDF135HH RSCAN0.RMDF135.UINT8[HH]
    4884 #define RSCAN0RMID36 RSCAN0.RMID36.UINT32
    4885 #define RSCAN0RMID36L RSCAN0.RMID36.UINT16[L]
    4886 #define RSCAN0RMID36LL RSCAN0.RMID36.UINT8[LL]
    4887 #define RSCAN0RMID36LH RSCAN0.RMID36.UINT8[LH]
    4888 #define RSCAN0RMID36H RSCAN0.RMID36.UINT16[H]
    4889 #define RSCAN0RMID36HL RSCAN0.RMID36.UINT8[HL]
    4890 #define RSCAN0RMID36HH RSCAN0.RMID36.UINT8[HH]
    4891 #define RSCAN0RMPTR36 RSCAN0.RMPTR36.UINT32
    4892 #define RSCAN0RMPTR36L RSCAN0.RMPTR36.UINT16[L]
    4893 #define RSCAN0RMPTR36LL RSCAN0.RMPTR36.UINT8[LL]
    4894 #define RSCAN0RMPTR36LH RSCAN0.RMPTR36.UINT8[LH]
    4895 #define RSCAN0RMPTR36H RSCAN0.RMPTR36.UINT16[H]
    4896 #define RSCAN0RMPTR36HL RSCAN0.RMPTR36.UINT8[HL]
    4897 #define RSCAN0RMPTR36HH RSCAN0.RMPTR36.UINT8[HH]
    4898 #define RSCAN0RMDF036 RSCAN0.RMDF036.UINT32
    4899 #define RSCAN0RMDF036L RSCAN0.RMDF036.UINT16[L]
    4900 #define RSCAN0RMDF036LL RSCAN0.RMDF036.UINT8[LL]
    4901 #define RSCAN0RMDF036LH RSCAN0.RMDF036.UINT8[LH]
    4902 #define RSCAN0RMDF036H RSCAN0.RMDF036.UINT16[H]
    4903 #define RSCAN0RMDF036HL RSCAN0.RMDF036.UINT8[HL]
    4904 #define RSCAN0RMDF036HH RSCAN0.RMDF036.UINT8[HH]
    4905 #define RSCAN0RMDF136 RSCAN0.RMDF136.UINT32
    4906 #define RSCAN0RMDF136L RSCAN0.RMDF136.UINT16[L]
    4907 #define RSCAN0RMDF136LL RSCAN0.RMDF136.UINT8[LL]
    4908 #define RSCAN0RMDF136LH RSCAN0.RMDF136.UINT8[LH]
    4909 #define RSCAN0RMDF136H RSCAN0.RMDF136.UINT16[H]
    4910 #define RSCAN0RMDF136HL RSCAN0.RMDF136.UINT8[HL]
    4911 #define RSCAN0RMDF136HH RSCAN0.RMDF136.UINT8[HH]
    4912 #define RSCAN0RMID37 RSCAN0.RMID37.UINT32
    4913 #define RSCAN0RMID37L RSCAN0.RMID37.UINT16[L]
    4914 #define RSCAN0RMID37LL RSCAN0.RMID37.UINT8[LL]
    4915 #define RSCAN0RMID37LH RSCAN0.RMID37.UINT8[LH]
    4916 #define RSCAN0RMID37H RSCAN0.RMID37.UINT16[H]
    4917 #define RSCAN0RMID37HL RSCAN0.RMID37.UINT8[HL]
    4918 #define RSCAN0RMID37HH RSCAN0.RMID37.UINT8[HH]
    4919 #define RSCAN0RMPTR37 RSCAN0.RMPTR37.UINT32
    4920 #define RSCAN0RMPTR37L RSCAN0.RMPTR37.UINT16[L]
    4921 #define RSCAN0RMPTR37LL RSCAN0.RMPTR37.UINT8[LL]
    4922 #define RSCAN0RMPTR37LH RSCAN0.RMPTR37.UINT8[LH]
    4923 #define RSCAN0RMPTR37H RSCAN0.RMPTR37.UINT16[H]
    4924 #define RSCAN0RMPTR37HL RSCAN0.RMPTR37.UINT8[HL]
    4925 #define RSCAN0RMPTR37HH RSCAN0.RMPTR37.UINT8[HH]
    4926 #define RSCAN0RMDF037 RSCAN0.RMDF037.UINT32
    4927 #define RSCAN0RMDF037L RSCAN0.RMDF037.UINT16[L]
    4928 #define RSCAN0RMDF037LL RSCAN0.RMDF037.UINT8[LL]
    4929 #define RSCAN0RMDF037LH RSCAN0.RMDF037.UINT8[LH]
    4930 #define RSCAN0RMDF037H RSCAN0.RMDF037.UINT16[H]
    4931 #define RSCAN0RMDF037HL RSCAN0.RMDF037.UINT8[HL]
    4932 #define RSCAN0RMDF037HH RSCAN0.RMDF037.UINT8[HH]
    4933 #define RSCAN0RMDF137 RSCAN0.RMDF137.UINT32
    4934 #define RSCAN0RMDF137L RSCAN0.RMDF137.UINT16[L]
    4935 #define RSCAN0RMDF137LL RSCAN0.RMDF137.UINT8[LL]
    4936 #define RSCAN0RMDF137LH RSCAN0.RMDF137.UINT8[LH]
    4937 #define RSCAN0RMDF137H RSCAN0.RMDF137.UINT16[H]
    4938 #define RSCAN0RMDF137HL RSCAN0.RMDF137.UINT8[HL]
    4939 #define RSCAN0RMDF137HH RSCAN0.RMDF137.UINT8[HH]
    4940 #define RSCAN0RMID38 RSCAN0.RMID38.UINT32
    4941 #define RSCAN0RMID38L RSCAN0.RMID38.UINT16[L]
    4942 #define RSCAN0RMID38LL RSCAN0.RMID38.UINT8[LL]
    4943 #define RSCAN0RMID38LH RSCAN0.RMID38.UINT8[LH]
    4944 #define RSCAN0RMID38H RSCAN0.RMID38.UINT16[H]
    4945 #define RSCAN0RMID38HL RSCAN0.RMID38.UINT8[HL]
    4946 #define RSCAN0RMID38HH RSCAN0.RMID38.UINT8[HH]
    4947 #define RSCAN0RMPTR38 RSCAN0.RMPTR38.UINT32
    4948 #define RSCAN0RMPTR38L RSCAN0.RMPTR38.UINT16[L]
    4949 #define RSCAN0RMPTR38LL RSCAN0.RMPTR38.UINT8[LL]
    4950 #define RSCAN0RMPTR38LH RSCAN0.RMPTR38.UINT8[LH]
    4951 #define RSCAN0RMPTR38H RSCAN0.RMPTR38.UINT16[H]
    4952 #define RSCAN0RMPTR38HL RSCAN0.RMPTR38.UINT8[HL]
    4953 #define RSCAN0RMPTR38HH RSCAN0.RMPTR38.UINT8[HH]
    4954 #define RSCAN0RMDF038 RSCAN0.RMDF038.UINT32
    4955 #define RSCAN0RMDF038L RSCAN0.RMDF038.UINT16[L]
    4956 #define RSCAN0RMDF038LL RSCAN0.RMDF038.UINT8[LL]
    4957 #define RSCAN0RMDF038LH RSCAN0.RMDF038.UINT8[LH]
    4958 #define RSCAN0RMDF038H RSCAN0.RMDF038.UINT16[H]
    4959 #define RSCAN0RMDF038HL RSCAN0.RMDF038.UINT8[HL]
    4960 #define RSCAN0RMDF038HH RSCAN0.RMDF038.UINT8[HH]
    4961 #define RSCAN0RMDF138 RSCAN0.RMDF138.UINT32
    4962 #define RSCAN0RMDF138L RSCAN0.RMDF138.UINT16[L]
    4963 #define RSCAN0RMDF138LL RSCAN0.RMDF138.UINT8[LL]
    4964 #define RSCAN0RMDF138LH RSCAN0.RMDF138.UINT8[LH]
    4965 #define RSCAN0RMDF138H RSCAN0.RMDF138.UINT16[H]
    4966 #define RSCAN0RMDF138HL RSCAN0.RMDF138.UINT8[HL]
    4967 #define RSCAN0RMDF138HH RSCAN0.RMDF138.UINT8[HH]
    4968 #define RSCAN0RMID39 RSCAN0.RMID39.UINT32
    4969 #define RSCAN0RMID39L RSCAN0.RMID39.UINT16[L]
    4970 #define RSCAN0RMID39LL RSCAN0.RMID39.UINT8[LL]
    4971 #define RSCAN0RMID39LH RSCAN0.RMID39.UINT8[LH]
    4972 #define RSCAN0RMID39H RSCAN0.RMID39.UINT16[H]
    4973 #define RSCAN0RMID39HL RSCAN0.RMID39.UINT8[HL]
    4974 #define RSCAN0RMID39HH RSCAN0.RMID39.UINT8[HH]
    4975 #define RSCAN0RMPTR39 RSCAN0.RMPTR39.UINT32
    4976 #define RSCAN0RMPTR39L RSCAN0.RMPTR39.UINT16[L]
    4977 #define RSCAN0RMPTR39LL RSCAN0.RMPTR39.UINT8[LL]
    4978 #define RSCAN0RMPTR39LH RSCAN0.RMPTR39.UINT8[LH]
    4979 #define RSCAN0RMPTR39H RSCAN0.RMPTR39.UINT16[H]
    4980 #define RSCAN0RMPTR39HL RSCAN0.RMPTR39.UINT8[HL]
    4981 #define RSCAN0RMPTR39HH RSCAN0.RMPTR39.UINT8[HH]
    4982 #define RSCAN0RMDF039 RSCAN0.RMDF039.UINT32
    4983 #define RSCAN0RMDF039L RSCAN0.RMDF039.UINT16[L]
    4984 #define RSCAN0RMDF039LL RSCAN0.RMDF039.UINT8[LL]
    4985 #define RSCAN0RMDF039LH RSCAN0.RMDF039.UINT8[LH]
    4986 #define RSCAN0RMDF039H RSCAN0.RMDF039.UINT16[H]
    4987 #define RSCAN0RMDF039HL RSCAN0.RMDF039.UINT8[HL]
    4988 #define RSCAN0RMDF039HH RSCAN0.RMDF039.UINT8[HH]
    4989 #define RSCAN0RMDF139 RSCAN0.RMDF139.UINT32
    4990 #define RSCAN0RMDF139L RSCAN0.RMDF139.UINT16[L]
    4991 #define RSCAN0RMDF139LL RSCAN0.RMDF139.UINT8[LL]
    4992 #define RSCAN0RMDF139LH RSCAN0.RMDF139.UINT8[LH]
    4993 #define RSCAN0RMDF139H RSCAN0.RMDF139.UINT16[H]
    4994 #define RSCAN0RMDF139HL RSCAN0.RMDF139.UINT8[HL]
    4995 #define RSCAN0RMDF139HH RSCAN0.RMDF139.UINT8[HH]
    4996 #define RSCAN0RMID40 RSCAN0.RMID40.UINT32
    4997 #define RSCAN0RMID40L RSCAN0.RMID40.UINT16[L]
    4998 #define RSCAN0RMID40LL RSCAN0.RMID40.UINT8[LL]
    4999 #define RSCAN0RMID40LH RSCAN0.RMID40.UINT8[LH]
    5000 #define RSCAN0RMID40H RSCAN0.RMID40.UINT16[H]
    5001 #define RSCAN0RMID40HL RSCAN0.RMID40.UINT8[HL]
    5002 #define RSCAN0RMID40HH RSCAN0.RMID40.UINT8[HH]
    5003 #define RSCAN0RMPTR40 RSCAN0.RMPTR40.UINT32
    5004 #define RSCAN0RMPTR40L RSCAN0.RMPTR40.UINT16[L]
    5005 #define RSCAN0RMPTR40LL RSCAN0.RMPTR40.UINT8[LL]
    5006 #define RSCAN0RMPTR40LH RSCAN0.RMPTR40.UINT8[LH]
    5007 #define RSCAN0RMPTR40H RSCAN0.RMPTR40.UINT16[H]
    5008 #define RSCAN0RMPTR40HL RSCAN0.RMPTR40.UINT8[HL]
    5009 #define RSCAN0RMPTR40HH RSCAN0.RMPTR40.UINT8[HH]
    5010 #define RSCAN0RMDF040 RSCAN0.RMDF040.UINT32
    5011 #define RSCAN0RMDF040L RSCAN0.RMDF040.UINT16[L]
    5012 #define RSCAN0RMDF040LL RSCAN0.RMDF040.UINT8[LL]
    5013 #define RSCAN0RMDF040LH RSCAN0.RMDF040.UINT8[LH]
    5014 #define RSCAN0RMDF040H RSCAN0.RMDF040.UINT16[H]
    5015 #define RSCAN0RMDF040HL RSCAN0.RMDF040.UINT8[HL]
    5016 #define RSCAN0RMDF040HH RSCAN0.RMDF040.UINT8[HH]
    5017 #define RSCAN0RMDF140 RSCAN0.RMDF140.UINT32
    5018 #define RSCAN0RMDF140L RSCAN0.RMDF140.UINT16[L]
    5019 #define RSCAN0RMDF140LL RSCAN0.RMDF140.UINT8[LL]
    5020 #define RSCAN0RMDF140LH RSCAN0.RMDF140.UINT8[LH]
    5021 #define RSCAN0RMDF140H RSCAN0.RMDF140.UINT16[H]
    5022 #define RSCAN0RMDF140HL RSCAN0.RMDF140.UINT8[HL]
    5023 #define RSCAN0RMDF140HH RSCAN0.RMDF140.UINT8[HH]
    5024 #define RSCAN0RMID41 RSCAN0.RMID41.UINT32
    5025 #define RSCAN0RMID41L RSCAN0.RMID41.UINT16[L]
    5026 #define RSCAN0RMID41LL RSCAN0.RMID41.UINT8[LL]
    5027 #define RSCAN0RMID41LH RSCAN0.RMID41.UINT8[LH]
    5028 #define RSCAN0RMID41H RSCAN0.RMID41.UINT16[H]
    5029 #define RSCAN0RMID41HL RSCAN0.RMID41.UINT8[HL]
    5030 #define RSCAN0RMID41HH RSCAN0.RMID41.UINT8[HH]
    5031 #define RSCAN0RMPTR41 RSCAN0.RMPTR41.UINT32
    5032 #define RSCAN0RMPTR41L RSCAN0.RMPTR41.UINT16[L]
    5033 #define RSCAN0RMPTR41LL RSCAN0.RMPTR41.UINT8[LL]
    5034 #define RSCAN0RMPTR41LH RSCAN0.RMPTR41.UINT8[LH]
    5035 #define RSCAN0RMPTR41H RSCAN0.RMPTR41.UINT16[H]
    5036 #define RSCAN0RMPTR41HL RSCAN0.RMPTR41.UINT8[HL]
    5037 #define RSCAN0RMPTR41HH RSCAN0.RMPTR41.UINT8[HH]
    5038 #define RSCAN0RMDF041 RSCAN0.RMDF041.UINT32
    5039 #define RSCAN0RMDF041L RSCAN0.RMDF041.UINT16[L]
    5040 #define RSCAN0RMDF041LL RSCAN0.RMDF041.UINT8[LL]
    5041 #define RSCAN0RMDF041LH RSCAN0.RMDF041.UINT8[LH]
    5042 #define RSCAN0RMDF041H RSCAN0.RMDF041.UINT16[H]
    5043 #define RSCAN0RMDF041HL RSCAN0.RMDF041.UINT8[HL]
    5044 #define RSCAN0RMDF041HH RSCAN0.RMDF041.UINT8[HH]
    5045 #define RSCAN0RMDF141 RSCAN0.RMDF141.UINT32
    5046 #define RSCAN0RMDF141L RSCAN0.RMDF141.UINT16[L]
    5047 #define RSCAN0RMDF141LL RSCAN0.RMDF141.UINT8[LL]
    5048 #define RSCAN0RMDF141LH RSCAN0.RMDF141.UINT8[LH]
    5049 #define RSCAN0RMDF141H RSCAN0.RMDF141.UINT16[H]
    5050 #define RSCAN0RMDF141HL RSCAN0.RMDF141.UINT8[HL]
    5051 #define RSCAN0RMDF141HH RSCAN0.RMDF141.UINT8[HH]
    5052 #define RSCAN0RMID42 RSCAN0.RMID42.UINT32
    5053 #define RSCAN0RMID42L RSCAN0.RMID42.UINT16[L]
    5054 #define RSCAN0RMID42LL RSCAN0.RMID42.UINT8[LL]
    5055 #define RSCAN0RMID42LH RSCAN0.RMID42.UINT8[LH]
    5056 #define RSCAN0RMID42H RSCAN0.RMID42.UINT16[H]
    5057 #define RSCAN0RMID42HL RSCAN0.RMID42.UINT8[HL]
    5058 #define RSCAN0RMID42HH RSCAN0.RMID42.UINT8[HH]
    5059 #define RSCAN0RMPTR42 RSCAN0.RMPTR42.UINT32
    5060 #define RSCAN0RMPTR42L RSCAN0.RMPTR42.UINT16[L]
    5061 #define RSCAN0RMPTR42LL RSCAN0.RMPTR42.UINT8[LL]
    5062 #define RSCAN0RMPTR42LH RSCAN0.RMPTR42.UINT8[LH]
    5063 #define RSCAN0RMPTR42H RSCAN0.RMPTR42.UINT16[H]
    5064 #define RSCAN0RMPTR42HL RSCAN0.RMPTR42.UINT8[HL]
    5065 #define RSCAN0RMPTR42HH RSCAN0.RMPTR42.UINT8[HH]
    5066 #define RSCAN0RMDF042 RSCAN0.RMDF042.UINT32
    5067 #define RSCAN0RMDF042L RSCAN0.RMDF042.UINT16[L]
    5068 #define RSCAN0RMDF042LL RSCAN0.RMDF042.UINT8[LL]
    5069 #define RSCAN0RMDF042LH RSCAN0.RMDF042.UINT8[LH]
    5070 #define RSCAN0RMDF042H RSCAN0.RMDF042.UINT16[H]
    5071 #define RSCAN0RMDF042HL RSCAN0.RMDF042.UINT8[HL]
    5072 #define RSCAN0RMDF042HH RSCAN0.RMDF042.UINT8[HH]
    5073 #define RSCAN0RMDF142 RSCAN0.RMDF142.UINT32
    5074 #define RSCAN0RMDF142L RSCAN0.RMDF142.UINT16[L]
    5075 #define RSCAN0RMDF142LL RSCAN0.RMDF142.UINT8[LL]
    5076 #define RSCAN0RMDF142LH RSCAN0.RMDF142.UINT8[LH]
    5077 #define RSCAN0RMDF142H RSCAN0.RMDF142.UINT16[H]
    5078 #define RSCAN0RMDF142HL RSCAN0.RMDF142.UINT8[HL]
    5079 #define RSCAN0RMDF142HH RSCAN0.RMDF142.UINT8[HH]
    5080 #define RSCAN0RMID43 RSCAN0.RMID43.UINT32
    5081 #define RSCAN0RMID43L RSCAN0.RMID43.UINT16[L]
    5082 #define RSCAN0RMID43LL RSCAN0.RMID43.UINT8[LL]
    5083 #define RSCAN0RMID43LH RSCAN0.RMID43.UINT8[LH]
    5084 #define RSCAN0RMID43H RSCAN0.RMID43.UINT16[H]
    5085 #define RSCAN0RMID43HL RSCAN0.RMID43.UINT8[HL]
    5086 #define RSCAN0RMID43HH RSCAN0.RMID43.UINT8[HH]
    5087 #define RSCAN0RMPTR43 RSCAN0.RMPTR43.UINT32
    5088 #define RSCAN0RMPTR43L RSCAN0.RMPTR43.UINT16[L]
    5089 #define RSCAN0RMPTR43LL RSCAN0.RMPTR43.UINT8[LL]
    5090 #define RSCAN0RMPTR43LH RSCAN0.RMPTR43.UINT8[LH]
    5091 #define RSCAN0RMPTR43H RSCAN0.RMPTR43.UINT16[H]
    5092 #define RSCAN0RMPTR43HL RSCAN0.RMPTR43.UINT8[HL]
    5093 #define RSCAN0RMPTR43HH RSCAN0.RMPTR43.UINT8[HH]
    5094 #define RSCAN0RMDF043 RSCAN0.RMDF043.UINT32
    5095 #define RSCAN0RMDF043L RSCAN0.RMDF043.UINT16[L]
    5096 #define RSCAN0RMDF043LL RSCAN0.RMDF043.UINT8[LL]
    5097 #define RSCAN0RMDF043LH RSCAN0.RMDF043.UINT8[LH]
    5098 #define RSCAN0RMDF043H RSCAN0.RMDF043.UINT16[H]
    5099 #define RSCAN0RMDF043HL RSCAN0.RMDF043.UINT8[HL]
    5100 #define RSCAN0RMDF043HH RSCAN0.RMDF043.UINT8[HH]
    5101 #define RSCAN0RMDF143 RSCAN0.RMDF143.UINT32
    5102 #define RSCAN0RMDF143L RSCAN0.RMDF143.UINT16[L]
    5103 #define RSCAN0RMDF143LL RSCAN0.RMDF143.UINT8[LL]
    5104 #define RSCAN0RMDF143LH RSCAN0.RMDF143.UINT8[LH]
    5105 #define RSCAN0RMDF143H RSCAN0.RMDF143.UINT16[H]
    5106 #define RSCAN0RMDF143HL RSCAN0.RMDF143.UINT8[HL]
    5107 #define RSCAN0RMDF143HH RSCAN0.RMDF143.UINT8[HH]
    5108 #define RSCAN0RMID44 RSCAN0.RMID44.UINT32
    5109 #define RSCAN0RMID44L RSCAN0.RMID44.UINT16[L]
    5110 #define RSCAN0RMID44LL RSCAN0.RMID44.UINT8[LL]
    5111 #define RSCAN0RMID44LH RSCAN0.RMID44.UINT8[LH]
    5112 #define RSCAN0RMID44H RSCAN0.RMID44.UINT16[H]
    5113 #define RSCAN0RMID44HL RSCAN0.RMID44.UINT8[HL]
    5114 #define RSCAN0RMID44HH RSCAN0.RMID44.UINT8[HH]
    5115 #define RSCAN0RMPTR44 RSCAN0.RMPTR44.UINT32
    5116 #define RSCAN0RMPTR44L RSCAN0.RMPTR44.UINT16[L]
    5117 #define RSCAN0RMPTR44LL RSCAN0.RMPTR44.UINT8[LL]
    5118 #define RSCAN0RMPTR44LH RSCAN0.RMPTR44.UINT8[LH]
    5119 #define RSCAN0RMPTR44H RSCAN0.RMPTR44.UINT16[H]
    5120 #define RSCAN0RMPTR44HL RSCAN0.RMPTR44.UINT8[HL]
    5121 #define RSCAN0RMPTR44HH RSCAN0.RMPTR44.UINT8[HH]
    5122 #define RSCAN0RMDF044 RSCAN0.RMDF044.UINT32
    5123 #define RSCAN0RMDF044L RSCAN0.RMDF044.UINT16[L]
    5124 #define RSCAN0RMDF044LL RSCAN0.RMDF044.UINT8[LL]
    5125 #define RSCAN0RMDF044LH RSCAN0.RMDF044.UINT8[LH]
    5126 #define RSCAN0RMDF044H RSCAN0.RMDF044.UINT16[H]
    5127 #define RSCAN0RMDF044HL RSCAN0.RMDF044.UINT8[HL]
    5128 #define RSCAN0RMDF044HH RSCAN0.RMDF044.UINT8[HH]
    5129 #define RSCAN0RMDF144 RSCAN0.RMDF144.UINT32
    5130 #define RSCAN0RMDF144L RSCAN0.RMDF144.UINT16[L]
    5131 #define RSCAN0RMDF144LL RSCAN0.RMDF144.UINT8[LL]
    5132 #define RSCAN0RMDF144LH RSCAN0.RMDF144.UINT8[LH]
    5133 #define RSCAN0RMDF144H RSCAN0.RMDF144.UINT16[H]
    5134 #define RSCAN0RMDF144HL RSCAN0.RMDF144.UINT8[HL]
    5135 #define RSCAN0RMDF144HH RSCAN0.RMDF144.UINT8[HH]
    5136 #define RSCAN0RMID45 RSCAN0.RMID45.UINT32
    5137 #define RSCAN0RMID45L RSCAN0.RMID45.UINT16[L]
    5138 #define RSCAN0RMID45LL RSCAN0.RMID45.UINT8[LL]
    5139 #define RSCAN0RMID45LH RSCAN0.RMID45.UINT8[LH]
    5140 #define RSCAN0RMID45H RSCAN0.RMID45.UINT16[H]
    5141 #define RSCAN0RMID45HL RSCAN0.RMID45.UINT8[HL]
    5142 #define RSCAN0RMID45HH RSCAN0.RMID45.UINT8[HH]
    5143 #define RSCAN0RMPTR45 RSCAN0.RMPTR45.UINT32
    5144 #define RSCAN0RMPTR45L RSCAN0.RMPTR45.UINT16[L]
    5145 #define RSCAN0RMPTR45LL RSCAN0.RMPTR45.UINT8[LL]
    5146 #define RSCAN0RMPTR45LH RSCAN0.RMPTR45.UINT8[LH]
    5147 #define RSCAN0RMPTR45H RSCAN0.RMPTR45.UINT16[H]
    5148 #define RSCAN0RMPTR45HL RSCAN0.RMPTR45.UINT8[HL]
    5149 #define RSCAN0RMPTR45HH RSCAN0.RMPTR45.UINT8[HH]
    5150 #define RSCAN0RMDF045 RSCAN0.RMDF045.UINT32
    5151 #define RSCAN0RMDF045L RSCAN0.RMDF045.UINT16[L]
    5152 #define RSCAN0RMDF045LL RSCAN0.RMDF045.UINT8[LL]
    5153 #define RSCAN0RMDF045LH RSCAN0.RMDF045.UINT8[LH]
    5154 #define RSCAN0RMDF045H RSCAN0.RMDF045.UINT16[H]
    5155 #define RSCAN0RMDF045HL RSCAN0.RMDF045.UINT8[HL]
    5156 #define RSCAN0RMDF045HH RSCAN0.RMDF045.UINT8[HH]
    5157 #define RSCAN0RMDF145 RSCAN0.RMDF145.UINT32
    5158 #define RSCAN0RMDF145L RSCAN0.RMDF145.UINT16[L]
    5159 #define RSCAN0RMDF145LL RSCAN0.RMDF145.UINT8[LL]
    5160 #define RSCAN0RMDF145LH RSCAN0.RMDF145.UINT8[LH]
    5161 #define RSCAN0RMDF145H RSCAN0.RMDF145.UINT16[H]
    5162 #define RSCAN0RMDF145HL RSCAN0.RMDF145.UINT8[HL]
    5163 #define RSCAN0RMDF145HH RSCAN0.RMDF145.UINT8[HH]
    5164 #define RSCAN0RMID46 RSCAN0.RMID46.UINT32
    5165 #define RSCAN0RMID46L RSCAN0.RMID46.UINT16[L]
    5166 #define RSCAN0RMID46LL RSCAN0.RMID46.UINT8[LL]
    5167 #define RSCAN0RMID46LH RSCAN0.RMID46.UINT8[LH]
    5168 #define RSCAN0RMID46H RSCAN0.RMID46.UINT16[H]
    5169 #define RSCAN0RMID46HL RSCAN0.RMID46.UINT8[HL]
    5170 #define RSCAN0RMID46HH RSCAN0.RMID46.UINT8[HH]
    5171 #define RSCAN0RMPTR46 RSCAN0.RMPTR46.UINT32
    5172 #define RSCAN0RMPTR46L RSCAN0.RMPTR46.UINT16[L]
    5173 #define RSCAN0RMPTR46LL RSCAN0.RMPTR46.UINT8[LL]
    5174 #define RSCAN0RMPTR46LH RSCAN0.RMPTR46.UINT8[LH]
    5175 #define RSCAN0RMPTR46H RSCAN0.RMPTR46.UINT16[H]
    5176 #define RSCAN0RMPTR46HL RSCAN0.RMPTR46.UINT8[HL]
    5177 #define RSCAN0RMPTR46HH RSCAN0.RMPTR46.UINT8[HH]
    5178 #define RSCAN0RMDF046 RSCAN0.RMDF046.UINT32
    5179 #define RSCAN0RMDF046L RSCAN0.RMDF046.UINT16[L]
    5180 #define RSCAN0RMDF046LL RSCAN0.RMDF046.UINT8[LL]
    5181 #define RSCAN0RMDF046LH RSCAN0.RMDF046.UINT8[LH]
    5182 #define RSCAN0RMDF046H RSCAN0.RMDF046.UINT16[H]
    5183 #define RSCAN0RMDF046HL RSCAN0.RMDF046.UINT8[HL]
    5184 #define RSCAN0RMDF046HH RSCAN0.RMDF046.UINT8[HH]
    5185 #define RSCAN0RMDF146 RSCAN0.RMDF146.UINT32
    5186 #define RSCAN0RMDF146L RSCAN0.RMDF146.UINT16[L]
    5187 #define RSCAN0RMDF146LL RSCAN0.RMDF146.UINT8[LL]
    5188 #define RSCAN0RMDF146LH RSCAN0.RMDF146.UINT8[LH]
    5189 #define RSCAN0RMDF146H RSCAN0.RMDF146.UINT16[H]
    5190 #define RSCAN0RMDF146HL RSCAN0.RMDF146.UINT8[HL]
    5191 #define RSCAN0RMDF146HH RSCAN0.RMDF146.UINT8[HH]
    5192 #define RSCAN0RMID47 RSCAN0.RMID47.UINT32
    5193 #define RSCAN0RMID47L RSCAN0.RMID47.UINT16[L]
    5194 #define RSCAN0RMID47LL RSCAN0.RMID47.UINT8[LL]
    5195 #define RSCAN0RMID47LH RSCAN0.RMID47.UINT8[LH]
    5196 #define RSCAN0RMID47H RSCAN0.RMID47.UINT16[H]
    5197 #define RSCAN0RMID47HL RSCAN0.RMID47.UINT8[HL]
    5198 #define RSCAN0RMID47HH RSCAN0.RMID47.UINT8[HH]
    5199 #define RSCAN0RMPTR47 RSCAN0.RMPTR47.UINT32
    5200 #define RSCAN0RMPTR47L RSCAN0.RMPTR47.UINT16[L]
    5201 #define RSCAN0RMPTR47LL RSCAN0.RMPTR47.UINT8[LL]
    5202 #define RSCAN0RMPTR47LH RSCAN0.RMPTR47.UINT8[LH]
    5203 #define RSCAN0RMPTR47H RSCAN0.RMPTR47.UINT16[H]
    5204 #define RSCAN0RMPTR47HL RSCAN0.RMPTR47.UINT8[HL]
    5205 #define RSCAN0RMPTR47HH RSCAN0.RMPTR47.UINT8[HH]
    5206 #define RSCAN0RMDF047 RSCAN0.RMDF047.UINT32
    5207 #define RSCAN0RMDF047L RSCAN0.RMDF047.UINT16[L]
    5208 #define RSCAN0RMDF047LL RSCAN0.RMDF047.UINT8[LL]
    5209 #define RSCAN0RMDF047LH RSCAN0.RMDF047.UINT8[LH]
    5210 #define RSCAN0RMDF047H RSCAN0.RMDF047.UINT16[H]
    5211 #define RSCAN0RMDF047HL RSCAN0.RMDF047.UINT8[HL]
    5212 #define RSCAN0RMDF047HH RSCAN0.RMDF047.UINT8[HH]
    5213 #define RSCAN0RMDF147 RSCAN0.RMDF147.UINT32
    5214 #define RSCAN0RMDF147L RSCAN0.RMDF147.UINT16[L]
    5215 #define RSCAN0RMDF147LL RSCAN0.RMDF147.UINT8[LL]
    5216 #define RSCAN0RMDF147LH RSCAN0.RMDF147.UINT8[LH]
    5217 #define RSCAN0RMDF147H RSCAN0.RMDF147.UINT16[H]
    5218 #define RSCAN0RMDF147HL RSCAN0.RMDF147.UINT8[HL]
    5219 #define RSCAN0RMDF147HH RSCAN0.RMDF147.UINT8[HH]
    5220 #define RSCAN0RMID48 RSCAN0.RMID48.UINT32
    5221 #define RSCAN0RMID48L RSCAN0.RMID48.UINT16[L]
    5222 #define RSCAN0RMID48LL RSCAN0.RMID48.UINT8[LL]
    5223 #define RSCAN0RMID48LH RSCAN0.RMID48.UINT8[LH]
    5224 #define RSCAN0RMID48H RSCAN0.RMID48.UINT16[H]
    5225 #define RSCAN0RMID48HL RSCAN0.RMID48.UINT8[HL]
    5226 #define RSCAN0RMID48HH RSCAN0.RMID48.UINT8[HH]
    5227 #define RSCAN0RMPTR48 RSCAN0.RMPTR48.UINT32
    5228 #define RSCAN0RMPTR48L RSCAN0.RMPTR48.UINT16[L]
    5229 #define RSCAN0RMPTR48LL RSCAN0.RMPTR48.UINT8[LL]
    5230 #define RSCAN0RMPTR48LH RSCAN0.RMPTR48.UINT8[LH]
    5231 #define RSCAN0RMPTR48H RSCAN0.RMPTR48.UINT16[H]
    5232 #define RSCAN0RMPTR48HL RSCAN0.RMPTR48.UINT8[HL]
    5233 #define RSCAN0RMPTR48HH RSCAN0.RMPTR48.UINT8[HH]
    5234 #define RSCAN0RMDF048 RSCAN0.RMDF048.UINT32
    5235 #define RSCAN0RMDF048L RSCAN0.RMDF048.UINT16[L]
    5236 #define RSCAN0RMDF048LL RSCAN0.RMDF048.UINT8[LL]
    5237 #define RSCAN0RMDF048LH RSCAN0.RMDF048.UINT8[LH]
    5238 #define RSCAN0RMDF048H RSCAN0.RMDF048.UINT16[H]
    5239 #define RSCAN0RMDF048HL RSCAN0.RMDF048.UINT8[HL]
    5240 #define RSCAN0RMDF048HH RSCAN0.RMDF048.UINT8[HH]
    5241 #define RSCAN0RMDF148 RSCAN0.RMDF148.UINT32
    5242 #define RSCAN0RMDF148L RSCAN0.RMDF148.UINT16[L]
    5243 #define RSCAN0RMDF148LL RSCAN0.RMDF148.UINT8[LL]
    5244 #define RSCAN0RMDF148LH RSCAN0.RMDF148.UINT8[LH]
    5245 #define RSCAN0RMDF148H RSCAN0.RMDF148.UINT16[H]
    5246 #define RSCAN0RMDF148HL RSCAN0.RMDF148.UINT8[HL]
    5247 #define RSCAN0RMDF148HH RSCAN0.RMDF148.UINT8[HH]
    5248 #define RSCAN0RMID49 RSCAN0.RMID49.UINT32
    5249 #define RSCAN0RMID49L RSCAN0.RMID49.UINT16[L]
    5250 #define RSCAN0RMID49LL RSCAN0.RMID49.UINT8[LL]
    5251 #define RSCAN0RMID49LH RSCAN0.RMID49.UINT8[LH]
    5252 #define RSCAN0RMID49H RSCAN0.RMID49.UINT16[H]
    5253 #define RSCAN0RMID49HL RSCAN0.RMID49.UINT8[HL]
    5254 #define RSCAN0RMID49HH RSCAN0.RMID49.UINT8[HH]
    5255 #define RSCAN0RMPTR49 RSCAN0.RMPTR49.UINT32
    5256 #define RSCAN0RMPTR49L RSCAN0.RMPTR49.UINT16[L]
    5257 #define RSCAN0RMPTR49LL RSCAN0.RMPTR49.UINT8[LL]
    5258 #define RSCAN0RMPTR49LH RSCAN0.RMPTR49.UINT8[LH]
    5259 #define RSCAN0RMPTR49H RSCAN0.RMPTR49.UINT16[H]
    5260 #define RSCAN0RMPTR49HL RSCAN0.RMPTR49.UINT8[HL]
    5261 #define RSCAN0RMPTR49HH RSCAN0.RMPTR49.UINT8[HH]
    5262 #define RSCAN0RMDF049 RSCAN0.RMDF049.UINT32
    5263 #define RSCAN0RMDF049L RSCAN0.RMDF049.UINT16[L]
    5264 #define RSCAN0RMDF049LL RSCAN0.RMDF049.UINT8[LL]
    5265 #define RSCAN0RMDF049LH RSCAN0.RMDF049.UINT8[LH]
    5266 #define RSCAN0RMDF049H RSCAN0.RMDF049.UINT16[H]
    5267 #define RSCAN0RMDF049HL RSCAN0.RMDF049.UINT8[HL]
    5268 #define RSCAN0RMDF049HH RSCAN0.RMDF049.UINT8[HH]
    5269 #define RSCAN0RMDF149 RSCAN0.RMDF149.UINT32
    5270 #define RSCAN0RMDF149L RSCAN0.RMDF149.UINT16[L]
    5271 #define RSCAN0RMDF149LL RSCAN0.RMDF149.UINT8[LL]
    5272 #define RSCAN0RMDF149LH RSCAN0.RMDF149.UINT8[LH]
    5273 #define RSCAN0RMDF149H RSCAN0.RMDF149.UINT16[H]
    5274 #define RSCAN0RMDF149HL RSCAN0.RMDF149.UINT8[HL]
    5275 #define RSCAN0RMDF149HH RSCAN0.RMDF149.UINT8[HH]
    5276 #define RSCAN0RMID50 RSCAN0.RMID50.UINT32
    5277 #define RSCAN0RMID50L RSCAN0.RMID50.UINT16[L]
    5278 #define RSCAN0RMID50LL RSCAN0.RMID50.UINT8[LL]
    5279 #define RSCAN0RMID50LH RSCAN0.RMID50.UINT8[LH]
    5280 #define RSCAN0RMID50H RSCAN0.RMID50.UINT16[H]
    5281 #define RSCAN0RMID50HL RSCAN0.RMID50.UINT8[HL]
    5282 #define RSCAN0RMID50HH RSCAN0.RMID50.UINT8[HH]
    5283 #define RSCAN0RMPTR50 RSCAN0.RMPTR50.UINT32
    5284 #define RSCAN0RMPTR50L RSCAN0.RMPTR50.UINT16[L]
    5285 #define RSCAN0RMPTR50LL RSCAN0.RMPTR50.UINT8[LL]
    5286 #define RSCAN0RMPTR50LH RSCAN0.RMPTR50.UINT8[LH]
    5287 #define RSCAN0RMPTR50H RSCAN0.RMPTR50.UINT16[H]
    5288 #define RSCAN0RMPTR50HL RSCAN0.RMPTR50.UINT8[HL]
    5289 #define RSCAN0RMPTR50HH RSCAN0.RMPTR50.UINT8[HH]
    5290 #define RSCAN0RMDF050 RSCAN0.RMDF050.UINT32
    5291 #define RSCAN0RMDF050L RSCAN0.RMDF050.UINT16[L]
    5292 #define RSCAN0RMDF050LL RSCAN0.RMDF050.UINT8[LL]
    5293 #define RSCAN0RMDF050LH RSCAN0.RMDF050.UINT8[LH]
    5294 #define RSCAN0RMDF050H RSCAN0.RMDF050.UINT16[H]
    5295 #define RSCAN0RMDF050HL RSCAN0.RMDF050.UINT8[HL]
    5296 #define RSCAN0RMDF050HH RSCAN0.RMDF050.UINT8[HH]
    5297 #define RSCAN0RMDF150 RSCAN0.RMDF150.UINT32
    5298 #define RSCAN0RMDF150L RSCAN0.RMDF150.UINT16[L]
    5299 #define RSCAN0RMDF150LL RSCAN0.RMDF150.UINT8[LL]
    5300 #define RSCAN0RMDF150LH RSCAN0.RMDF150.UINT8[LH]
    5301 #define RSCAN0RMDF150H RSCAN0.RMDF150.UINT16[H]
    5302 #define RSCAN0RMDF150HL RSCAN0.RMDF150.UINT8[HL]
    5303 #define RSCAN0RMDF150HH RSCAN0.RMDF150.UINT8[HH]
    5304 #define RSCAN0RMID51 RSCAN0.RMID51.UINT32
    5305 #define RSCAN0RMID51L RSCAN0.RMID51.UINT16[L]
    5306 #define RSCAN0RMID51LL RSCAN0.RMID51.UINT8[LL]
    5307 #define RSCAN0RMID51LH RSCAN0.RMID51.UINT8[LH]
    5308 #define RSCAN0RMID51H RSCAN0.RMID51.UINT16[H]
    5309 #define RSCAN0RMID51HL RSCAN0.RMID51.UINT8[HL]
    5310 #define RSCAN0RMID51HH RSCAN0.RMID51.UINT8[HH]
    5311 #define RSCAN0RMPTR51 RSCAN0.RMPTR51.UINT32
    5312 #define RSCAN0RMPTR51L RSCAN0.RMPTR51.UINT16[L]
    5313 #define RSCAN0RMPTR51LL RSCAN0.RMPTR51.UINT8[LL]
    5314 #define RSCAN0RMPTR51LH RSCAN0.RMPTR51.UINT8[LH]
    5315 #define RSCAN0RMPTR51H RSCAN0.RMPTR51.UINT16[H]
    5316 #define RSCAN0RMPTR51HL RSCAN0.RMPTR51.UINT8[HL]
    5317 #define RSCAN0RMPTR51HH RSCAN0.RMPTR51.UINT8[HH]
    5318 #define RSCAN0RMDF051 RSCAN0.RMDF051.UINT32
    5319 #define RSCAN0RMDF051L RSCAN0.RMDF051.UINT16[L]
    5320 #define RSCAN0RMDF051LL RSCAN0.RMDF051.UINT8[LL]
    5321 #define RSCAN0RMDF051LH RSCAN0.RMDF051.UINT8[LH]
    5322 #define RSCAN0RMDF051H RSCAN0.RMDF051.UINT16[H]
    5323 #define RSCAN0RMDF051HL RSCAN0.RMDF051.UINT8[HL]
    5324 #define RSCAN0RMDF051HH RSCAN0.RMDF051.UINT8[HH]
    5325 #define RSCAN0RMDF151 RSCAN0.RMDF151.UINT32
    5326 #define RSCAN0RMDF151L RSCAN0.RMDF151.UINT16[L]
    5327 #define RSCAN0RMDF151LL RSCAN0.RMDF151.UINT8[LL]
    5328 #define RSCAN0RMDF151LH RSCAN0.RMDF151.UINT8[LH]
    5329 #define RSCAN0RMDF151H RSCAN0.RMDF151.UINT16[H]
    5330 #define RSCAN0RMDF151HL RSCAN0.RMDF151.UINT8[HL]
    5331 #define RSCAN0RMDF151HH RSCAN0.RMDF151.UINT8[HH]
    5332 #define RSCAN0RMID52 RSCAN0.RMID52.UINT32
    5333 #define RSCAN0RMID52L RSCAN0.RMID52.UINT16[L]
    5334 #define RSCAN0RMID52LL RSCAN0.RMID52.UINT8[LL]
    5335 #define RSCAN0RMID52LH RSCAN0.RMID52.UINT8[LH]
    5336 #define RSCAN0RMID52H RSCAN0.RMID52.UINT16[H]
    5337 #define RSCAN0RMID52HL RSCAN0.RMID52.UINT8[HL]
    5338 #define RSCAN0RMID52HH RSCAN0.RMID52.UINT8[HH]
    5339 #define RSCAN0RMPTR52 RSCAN0.RMPTR52.UINT32
    5340 #define RSCAN0RMPTR52L RSCAN0.RMPTR52.UINT16[L]
    5341 #define RSCAN0RMPTR52LL RSCAN0.RMPTR52.UINT8[LL]
    5342 #define RSCAN0RMPTR52LH RSCAN0.RMPTR52.UINT8[LH]
    5343 #define RSCAN0RMPTR52H RSCAN0.RMPTR52.UINT16[H]
    5344 #define RSCAN0RMPTR52HL RSCAN0.RMPTR52.UINT8[HL]
    5345 #define RSCAN0RMPTR52HH RSCAN0.RMPTR52.UINT8[HH]
    5346 #define RSCAN0RMDF052 RSCAN0.RMDF052.UINT32
    5347 #define RSCAN0RMDF052L RSCAN0.RMDF052.UINT16[L]
    5348 #define RSCAN0RMDF052LL RSCAN0.RMDF052.UINT8[LL]
    5349 #define RSCAN0RMDF052LH RSCAN0.RMDF052.UINT8[LH]
    5350 #define RSCAN0RMDF052H RSCAN0.RMDF052.UINT16[H]
    5351 #define RSCAN0RMDF052HL RSCAN0.RMDF052.UINT8[HL]
    5352 #define RSCAN0RMDF052HH RSCAN0.RMDF052.UINT8[HH]
    5353 #define RSCAN0RMDF152 RSCAN0.RMDF152.UINT32
    5354 #define RSCAN0RMDF152L RSCAN0.RMDF152.UINT16[L]
    5355 #define RSCAN0RMDF152LL RSCAN0.RMDF152.UINT8[LL]
    5356 #define RSCAN0RMDF152LH RSCAN0.RMDF152.UINT8[LH]
    5357 #define RSCAN0RMDF152H RSCAN0.RMDF152.UINT16[H]
    5358 #define RSCAN0RMDF152HL RSCAN0.RMDF152.UINT8[HL]
    5359 #define RSCAN0RMDF152HH RSCAN0.RMDF152.UINT8[HH]
    5360 #define RSCAN0RMID53 RSCAN0.RMID53.UINT32
    5361 #define RSCAN0RMID53L RSCAN0.RMID53.UINT16[L]
    5362 #define RSCAN0RMID53LL RSCAN0.RMID53.UINT8[LL]
    5363 #define RSCAN0RMID53LH RSCAN0.RMID53.UINT8[LH]
    5364 #define RSCAN0RMID53H RSCAN0.RMID53.UINT16[H]
    5365 #define RSCAN0RMID53HL RSCAN0.RMID53.UINT8[HL]
    5366 #define RSCAN0RMID53HH RSCAN0.RMID53.UINT8[HH]
    5367 #define RSCAN0RMPTR53 RSCAN0.RMPTR53.UINT32
    5368 #define RSCAN0RMPTR53L RSCAN0.RMPTR53.UINT16[L]
    5369 #define RSCAN0RMPTR53LL RSCAN0.RMPTR53.UINT8[LL]
    5370 #define RSCAN0RMPTR53LH RSCAN0.RMPTR53.UINT8[LH]
    5371 #define RSCAN0RMPTR53H RSCAN0.RMPTR53.UINT16[H]
    5372 #define RSCAN0RMPTR53HL RSCAN0.RMPTR53.UINT8[HL]
    5373 #define RSCAN0RMPTR53HH RSCAN0.RMPTR53.UINT8[HH]
    5374 #define RSCAN0RMDF053 RSCAN0.RMDF053.UINT32
    5375 #define RSCAN0RMDF053L RSCAN0.RMDF053.UINT16[L]
    5376 #define RSCAN0RMDF053LL RSCAN0.RMDF053.UINT8[LL]
    5377 #define RSCAN0RMDF053LH RSCAN0.RMDF053.UINT8[LH]
    5378 #define RSCAN0RMDF053H RSCAN0.RMDF053.UINT16[H]
    5379 #define RSCAN0RMDF053HL RSCAN0.RMDF053.UINT8[HL]
    5380 #define RSCAN0RMDF053HH RSCAN0.RMDF053.UINT8[HH]
    5381 #define RSCAN0RMDF153 RSCAN0.RMDF153.UINT32
    5382 #define RSCAN0RMDF153L RSCAN0.RMDF153.UINT16[L]
    5383 #define RSCAN0RMDF153LL RSCAN0.RMDF153.UINT8[LL]
    5384 #define RSCAN0RMDF153LH RSCAN0.RMDF153.UINT8[LH]
    5385 #define RSCAN0RMDF153H RSCAN0.RMDF153.UINT16[H]
    5386 #define RSCAN0RMDF153HL RSCAN0.RMDF153.UINT8[HL]
    5387 #define RSCAN0RMDF153HH RSCAN0.RMDF153.UINT8[HH]
    5388 #define RSCAN0RMID54 RSCAN0.RMID54.UINT32
    5389 #define RSCAN0RMID54L RSCAN0.RMID54.UINT16[L]
    5390 #define RSCAN0RMID54LL RSCAN0.RMID54.UINT8[LL]
    5391 #define RSCAN0RMID54LH RSCAN0.RMID54.UINT8[LH]
    5392 #define RSCAN0RMID54H RSCAN0.RMID54.UINT16[H]
    5393 #define RSCAN0RMID54HL RSCAN0.RMID54.UINT8[HL]
    5394 #define RSCAN0RMID54HH RSCAN0.RMID54.UINT8[HH]
    5395 #define RSCAN0RMPTR54 RSCAN0.RMPTR54.UINT32
    5396 #define RSCAN0RMPTR54L RSCAN0.RMPTR54.UINT16[L]
    5397 #define RSCAN0RMPTR54LL RSCAN0.RMPTR54.UINT8[LL]
    5398 #define RSCAN0RMPTR54LH RSCAN0.RMPTR54.UINT8[LH]
    5399 #define RSCAN0RMPTR54H RSCAN0.RMPTR54.UINT16[H]
    5400 #define RSCAN0RMPTR54HL RSCAN0.RMPTR54.UINT8[HL]
    5401 #define RSCAN0RMPTR54HH RSCAN0.RMPTR54.UINT8[HH]
    5402 #define RSCAN0RMDF054 RSCAN0.RMDF054.UINT32
    5403 #define RSCAN0RMDF054L RSCAN0.RMDF054.UINT16[L]
    5404 #define RSCAN0RMDF054LL RSCAN0.RMDF054.UINT8[LL]
    5405 #define RSCAN0RMDF054LH RSCAN0.RMDF054.UINT8[LH]
    5406 #define RSCAN0RMDF054H RSCAN0.RMDF054.UINT16[H]
    5407 #define RSCAN0RMDF054HL RSCAN0.RMDF054.UINT8[HL]
    5408 #define RSCAN0RMDF054HH RSCAN0.RMDF054.UINT8[HH]
    5409 #define RSCAN0RMDF154 RSCAN0.RMDF154.UINT32
    5410 #define RSCAN0RMDF154L RSCAN0.RMDF154.UINT16[L]
    5411 #define RSCAN0RMDF154LL RSCAN0.RMDF154.UINT8[LL]
    5412 #define RSCAN0RMDF154LH RSCAN0.RMDF154.UINT8[LH]
    5413 #define RSCAN0RMDF154H RSCAN0.RMDF154.UINT16[H]
    5414 #define RSCAN0RMDF154HL RSCAN0.RMDF154.UINT8[HL]
    5415 #define RSCAN0RMDF154HH RSCAN0.RMDF154.UINT8[HH]
    5416 #define RSCAN0RMID55 RSCAN0.RMID55.UINT32
    5417 #define RSCAN0RMID55L RSCAN0.RMID55.UINT16[L]
    5418 #define RSCAN0RMID55LL RSCAN0.RMID55.UINT8[LL]
    5419 #define RSCAN0RMID55LH RSCAN0.RMID55.UINT8[LH]
    5420 #define RSCAN0RMID55H RSCAN0.RMID55.UINT16[H]
    5421 #define RSCAN0RMID55HL RSCAN0.RMID55.UINT8[HL]
    5422 #define RSCAN0RMID55HH RSCAN0.RMID55.UINT8[HH]
    5423 #define RSCAN0RMPTR55 RSCAN0.RMPTR55.UINT32
    5424 #define RSCAN0RMPTR55L RSCAN0.RMPTR55.UINT16[L]
    5425 #define RSCAN0RMPTR55LL RSCAN0.RMPTR55.UINT8[LL]
    5426 #define RSCAN0RMPTR55LH RSCAN0.RMPTR55.UINT8[LH]
    5427 #define RSCAN0RMPTR55H RSCAN0.RMPTR55.UINT16[H]
    5428 #define RSCAN0RMPTR55HL RSCAN0.RMPTR55.UINT8[HL]
    5429 #define RSCAN0RMPTR55HH RSCAN0.RMPTR55.UINT8[HH]
    5430 #define RSCAN0RMDF055 RSCAN0.RMDF055.UINT32
    5431 #define RSCAN0RMDF055L RSCAN0.RMDF055.UINT16[L]
    5432 #define RSCAN0RMDF055LL RSCAN0.RMDF055.UINT8[LL]
    5433 #define RSCAN0RMDF055LH RSCAN0.RMDF055.UINT8[LH]
    5434 #define RSCAN0RMDF055H RSCAN0.RMDF055.UINT16[H]
    5435 #define RSCAN0RMDF055HL RSCAN0.RMDF055.UINT8[HL]
    5436 #define RSCAN0RMDF055HH RSCAN0.RMDF055.UINT8[HH]
    5437 #define RSCAN0RMDF155 RSCAN0.RMDF155.UINT32
    5438 #define RSCAN0RMDF155L RSCAN0.RMDF155.UINT16[L]
    5439 #define RSCAN0RMDF155LL RSCAN0.RMDF155.UINT8[LL]
    5440 #define RSCAN0RMDF155LH RSCAN0.RMDF155.UINT8[LH]
    5441 #define RSCAN0RMDF155H RSCAN0.RMDF155.UINT16[H]
    5442 #define RSCAN0RMDF155HL RSCAN0.RMDF155.UINT8[HL]
    5443 #define RSCAN0RMDF155HH RSCAN0.RMDF155.UINT8[HH]
    5444 #define RSCAN0RMID56 RSCAN0.RMID56.UINT32
    5445 #define RSCAN0RMID56L RSCAN0.RMID56.UINT16[L]
    5446 #define RSCAN0RMID56LL RSCAN0.RMID56.UINT8[LL]
    5447 #define RSCAN0RMID56LH RSCAN0.RMID56.UINT8[LH]
    5448 #define RSCAN0RMID56H RSCAN0.RMID56.UINT16[H]
    5449 #define RSCAN0RMID56HL RSCAN0.RMID56.UINT8[HL]
    5450 #define RSCAN0RMID56HH RSCAN0.RMID56.UINT8[HH]
    5451 #define RSCAN0RMPTR56 RSCAN0.RMPTR56.UINT32
    5452 #define RSCAN0RMPTR56L RSCAN0.RMPTR56.UINT16[L]
    5453 #define RSCAN0RMPTR56LL RSCAN0.RMPTR56.UINT8[LL]
    5454 #define RSCAN0RMPTR56LH RSCAN0.RMPTR56.UINT8[LH]
    5455 #define RSCAN0RMPTR56H RSCAN0.RMPTR56.UINT16[H]
    5456 #define RSCAN0RMPTR56HL RSCAN0.RMPTR56.UINT8[HL]
    5457 #define RSCAN0RMPTR56HH RSCAN0.RMPTR56.UINT8[HH]
    5458 #define RSCAN0RMDF056 RSCAN0.RMDF056.UINT32
    5459 #define RSCAN0RMDF056L RSCAN0.RMDF056.UINT16[L]
    5460 #define RSCAN0RMDF056LL RSCAN0.RMDF056.UINT8[LL]
    5461 #define RSCAN0RMDF056LH RSCAN0.RMDF056.UINT8[LH]
    5462 #define RSCAN0RMDF056H RSCAN0.RMDF056.UINT16[H]
    5463 #define RSCAN0RMDF056HL RSCAN0.RMDF056.UINT8[HL]
    5464 #define RSCAN0RMDF056HH RSCAN0.RMDF056.UINT8[HH]
    5465 #define RSCAN0RMDF156 RSCAN0.RMDF156.UINT32
    5466 #define RSCAN0RMDF156L RSCAN0.RMDF156.UINT16[L]
    5467 #define RSCAN0RMDF156LL RSCAN0.RMDF156.UINT8[LL]
    5468 #define RSCAN0RMDF156LH RSCAN0.RMDF156.UINT8[LH]
    5469 #define RSCAN0RMDF156H RSCAN0.RMDF156.UINT16[H]
    5470 #define RSCAN0RMDF156HL RSCAN0.RMDF156.UINT8[HL]
    5471 #define RSCAN0RMDF156HH RSCAN0.RMDF156.UINT8[HH]
    5472 #define RSCAN0RMID57 RSCAN0.RMID57.UINT32
    5473 #define RSCAN0RMID57L RSCAN0.RMID57.UINT16[L]
    5474 #define RSCAN0RMID57LL RSCAN0.RMID57.UINT8[LL]
    5475 #define RSCAN0RMID57LH RSCAN0.RMID57.UINT8[LH]
    5476 #define RSCAN0RMID57H RSCAN0.RMID57.UINT16[H]
    5477 #define RSCAN0RMID57HL RSCAN0.RMID57.UINT8[HL]
    5478 #define RSCAN0RMID57HH RSCAN0.RMID57.UINT8[HH]
    5479 #define RSCAN0RMPTR57 RSCAN0.RMPTR57.UINT32
    5480 #define RSCAN0RMPTR57L RSCAN0.RMPTR57.UINT16[L]
    5481 #define RSCAN0RMPTR57LL RSCAN0.RMPTR57.UINT8[LL]
    5482 #define RSCAN0RMPTR57LH RSCAN0.RMPTR57.UINT8[LH]
    5483 #define RSCAN0RMPTR57H RSCAN0.RMPTR57.UINT16[H]
    5484 #define RSCAN0RMPTR57HL RSCAN0.RMPTR57.UINT8[HL]
    5485 #define RSCAN0RMPTR57HH RSCAN0.RMPTR57.UINT8[HH]
    5486 #define RSCAN0RMDF057 RSCAN0.RMDF057.UINT32
    5487 #define RSCAN0RMDF057L RSCAN0.RMDF057.UINT16[L]
    5488 #define RSCAN0RMDF057LL RSCAN0.RMDF057.UINT8[LL]
    5489 #define RSCAN0RMDF057LH RSCAN0.RMDF057.UINT8[LH]
    5490 #define RSCAN0RMDF057H RSCAN0.RMDF057.UINT16[H]
    5491 #define RSCAN0RMDF057HL RSCAN0.RMDF057.UINT8[HL]
    5492 #define RSCAN0RMDF057HH RSCAN0.RMDF057.UINT8[HH]
    5493 #define RSCAN0RMDF157 RSCAN0.RMDF157.UINT32
    5494 #define RSCAN0RMDF157L RSCAN0.RMDF157.UINT16[L]
    5495 #define RSCAN0RMDF157LL RSCAN0.RMDF157.UINT8[LL]
    5496 #define RSCAN0RMDF157LH RSCAN0.RMDF157.UINT8[LH]
    5497 #define RSCAN0RMDF157H RSCAN0.RMDF157.UINT16[H]
    5498 #define RSCAN0RMDF157HL RSCAN0.RMDF157.UINT8[HL]
    5499 #define RSCAN0RMDF157HH RSCAN0.RMDF157.UINT8[HH]
    5500 #define RSCAN0RMID58 RSCAN0.RMID58.UINT32
    5501 #define RSCAN0RMID58L RSCAN0.RMID58.UINT16[L]
    5502 #define RSCAN0RMID58LL RSCAN0.RMID58.UINT8[LL]
    5503 #define RSCAN0RMID58LH RSCAN0.RMID58.UINT8[LH]
    5504 #define RSCAN0RMID58H RSCAN0.RMID58.UINT16[H]
    5505 #define RSCAN0RMID58HL RSCAN0.RMID58.UINT8[HL]
    5506 #define RSCAN0RMID58HH RSCAN0.RMID58.UINT8[HH]
    5507 #define RSCAN0RMPTR58 RSCAN0.RMPTR58.UINT32
    5508 #define RSCAN0RMPTR58L RSCAN0.RMPTR58.UINT16[L]
    5509 #define RSCAN0RMPTR58LL RSCAN0.RMPTR58.UINT8[LL]
    5510 #define RSCAN0RMPTR58LH RSCAN0.RMPTR58.UINT8[LH]
    5511 #define RSCAN0RMPTR58H RSCAN0.RMPTR58.UINT16[H]
    5512 #define RSCAN0RMPTR58HL RSCAN0.RMPTR58.UINT8[HL]
    5513 #define RSCAN0RMPTR58HH RSCAN0.RMPTR58.UINT8[HH]
    5514 #define RSCAN0RMDF058 RSCAN0.RMDF058.UINT32
    5515 #define RSCAN0RMDF058L RSCAN0.RMDF058.UINT16[L]
    5516 #define RSCAN0RMDF058LL RSCAN0.RMDF058.UINT8[LL]
    5517 #define RSCAN0RMDF058LH RSCAN0.RMDF058.UINT8[LH]
    5518 #define RSCAN0RMDF058H RSCAN0.RMDF058.UINT16[H]
    5519 #define RSCAN0RMDF058HL RSCAN0.RMDF058.UINT8[HL]
    5520 #define RSCAN0RMDF058HH RSCAN0.RMDF058.UINT8[HH]
    5521 #define RSCAN0RMDF158 RSCAN0.RMDF158.UINT32
    5522 #define RSCAN0RMDF158L RSCAN0.RMDF158.UINT16[L]
    5523 #define RSCAN0RMDF158LL RSCAN0.RMDF158.UINT8[LL]
    5524 #define RSCAN0RMDF158LH RSCAN0.RMDF158.UINT8[LH]
    5525 #define RSCAN0RMDF158H RSCAN0.RMDF158.UINT16[H]
    5526 #define RSCAN0RMDF158HL RSCAN0.RMDF158.UINT8[HL]
    5527 #define RSCAN0RMDF158HH RSCAN0.RMDF158.UINT8[HH]
    5528 #define RSCAN0RMID59 RSCAN0.RMID59.UINT32
    5529 #define RSCAN0RMID59L RSCAN0.RMID59.UINT16[L]
    5530 #define RSCAN0RMID59LL RSCAN0.RMID59.UINT8[LL]
    5531 #define RSCAN0RMID59LH RSCAN0.RMID59.UINT8[LH]
    5532 #define RSCAN0RMID59H RSCAN0.RMID59.UINT16[H]
    5533 #define RSCAN0RMID59HL RSCAN0.RMID59.UINT8[HL]
    5534 #define RSCAN0RMID59HH RSCAN0.RMID59.UINT8[HH]
    5535 #define RSCAN0RMPTR59 RSCAN0.RMPTR59.UINT32
    5536 #define RSCAN0RMPTR59L RSCAN0.RMPTR59.UINT16[L]
    5537 #define RSCAN0RMPTR59LL RSCAN0.RMPTR59.UINT8[LL]
    5538 #define RSCAN0RMPTR59LH RSCAN0.RMPTR59.UINT8[LH]
    5539 #define RSCAN0RMPTR59H RSCAN0.RMPTR59.UINT16[H]
    5540 #define RSCAN0RMPTR59HL RSCAN0.RMPTR59.UINT8[HL]
    5541 #define RSCAN0RMPTR59HH RSCAN0.RMPTR59.UINT8[HH]
    5542 #define RSCAN0RMDF059 RSCAN0.RMDF059.UINT32
    5543 #define RSCAN0RMDF059L RSCAN0.RMDF059.UINT16[L]
    5544 #define RSCAN0RMDF059LL RSCAN0.RMDF059.UINT8[LL]
    5545 #define RSCAN0RMDF059LH RSCAN0.RMDF059.UINT8[LH]
    5546 #define RSCAN0RMDF059H RSCAN0.RMDF059.UINT16[H]
    5547 #define RSCAN0RMDF059HL RSCAN0.RMDF059.UINT8[HL]
    5548 #define RSCAN0RMDF059HH RSCAN0.RMDF059.UINT8[HH]
    5549 #define RSCAN0RMDF159 RSCAN0.RMDF159.UINT32
    5550 #define RSCAN0RMDF159L RSCAN0.RMDF159.UINT16[L]
    5551 #define RSCAN0RMDF159LL RSCAN0.RMDF159.UINT8[LL]
    5552 #define RSCAN0RMDF159LH RSCAN0.RMDF159.UINT8[LH]
    5553 #define RSCAN0RMDF159H RSCAN0.RMDF159.UINT16[H]
    5554 #define RSCAN0RMDF159HL RSCAN0.RMDF159.UINT8[HL]
    5555 #define RSCAN0RMDF159HH RSCAN0.RMDF159.UINT8[HH]
    5556 #define RSCAN0RMID60 RSCAN0.RMID60.UINT32
    5557 #define RSCAN0RMID60L RSCAN0.RMID60.UINT16[L]
    5558 #define RSCAN0RMID60LL RSCAN0.RMID60.UINT8[LL]
    5559 #define RSCAN0RMID60LH RSCAN0.RMID60.UINT8[LH]
    5560 #define RSCAN0RMID60H RSCAN0.RMID60.UINT16[H]
    5561 #define RSCAN0RMID60HL RSCAN0.RMID60.UINT8[HL]
    5562 #define RSCAN0RMID60HH RSCAN0.RMID60.UINT8[HH]
    5563 #define RSCAN0RMPTR60 RSCAN0.RMPTR60.UINT32
    5564 #define RSCAN0RMPTR60L RSCAN0.RMPTR60.UINT16[L]
    5565 #define RSCAN0RMPTR60LL RSCAN0.RMPTR60.UINT8[LL]
    5566 #define RSCAN0RMPTR60LH RSCAN0.RMPTR60.UINT8[LH]
    5567 #define RSCAN0RMPTR60H RSCAN0.RMPTR60.UINT16[H]
    5568 #define RSCAN0RMPTR60HL RSCAN0.RMPTR60.UINT8[HL]
    5569 #define RSCAN0RMPTR60HH RSCAN0.RMPTR60.UINT8[HH]
    5570 #define RSCAN0RMDF060 RSCAN0.RMDF060.UINT32
    5571 #define RSCAN0RMDF060L RSCAN0.RMDF060.UINT16[L]
    5572 #define RSCAN0RMDF060LL RSCAN0.RMDF060.UINT8[LL]
    5573 #define RSCAN0RMDF060LH RSCAN0.RMDF060.UINT8[LH]
    5574 #define RSCAN0RMDF060H RSCAN0.RMDF060.UINT16[H]
    5575 #define RSCAN0RMDF060HL RSCAN0.RMDF060.UINT8[HL]
    5576 #define RSCAN0RMDF060HH RSCAN0.RMDF060.UINT8[HH]
    5577 #define RSCAN0RMDF160 RSCAN0.RMDF160.UINT32
    5578 #define RSCAN0RMDF160L RSCAN0.RMDF160.UINT16[L]
    5579 #define RSCAN0RMDF160LL RSCAN0.RMDF160.UINT8[LL]
    5580 #define RSCAN0RMDF160LH RSCAN0.RMDF160.UINT8[LH]
    5581 #define RSCAN0RMDF160H RSCAN0.RMDF160.UINT16[H]
    5582 #define RSCAN0RMDF160HL RSCAN0.RMDF160.UINT8[HL]
    5583 #define RSCAN0RMDF160HH RSCAN0.RMDF160.UINT8[HH]
    5584 #define RSCAN0RMID61 RSCAN0.RMID61.UINT32
    5585 #define RSCAN0RMID61L RSCAN0.RMID61.UINT16[L]
    5586 #define RSCAN0RMID61LL RSCAN0.RMID61.UINT8[LL]
    5587 #define RSCAN0RMID61LH RSCAN0.RMID61.UINT8[LH]
    5588 #define RSCAN0RMID61H RSCAN0.RMID61.UINT16[H]
    5589 #define RSCAN0RMID61HL RSCAN0.RMID61.UINT8[HL]
    5590 #define RSCAN0RMID61HH RSCAN0.RMID61.UINT8[HH]
    5591 #define RSCAN0RMPTR61 RSCAN0.RMPTR61.UINT32
    5592 #define RSCAN0RMPTR61L RSCAN0.RMPTR61.UINT16[L]
    5593 #define RSCAN0RMPTR61LL RSCAN0.RMPTR61.UINT8[LL]
    5594 #define RSCAN0RMPTR61LH RSCAN0.RMPTR61.UINT8[LH]
    5595 #define RSCAN0RMPTR61H RSCAN0.RMPTR61.UINT16[H]
    5596 #define RSCAN0RMPTR61HL RSCAN0.RMPTR61.UINT8[HL]
    5597 #define RSCAN0RMPTR61HH RSCAN0.RMPTR61.UINT8[HH]
    5598 #define RSCAN0RMDF061 RSCAN0.RMDF061.UINT32
    5599 #define RSCAN0RMDF061L RSCAN0.RMDF061.UINT16[L]
    5600 #define RSCAN0RMDF061LL RSCAN0.RMDF061.UINT8[LL]
    5601 #define RSCAN0RMDF061LH RSCAN0.RMDF061.UINT8[LH]
    5602 #define RSCAN0RMDF061H RSCAN0.RMDF061.UINT16[H]
    5603 #define RSCAN0RMDF061HL RSCAN0.RMDF061.UINT8[HL]
    5604 #define RSCAN0RMDF061HH RSCAN0.RMDF061.UINT8[HH]
    5605 #define RSCAN0RMDF161 RSCAN0.RMDF161.UINT32
    5606 #define RSCAN0RMDF161L RSCAN0.RMDF161.UINT16[L]
    5607 #define RSCAN0RMDF161LL RSCAN0.RMDF161.UINT8[LL]
    5608 #define RSCAN0RMDF161LH RSCAN0.RMDF161.UINT8[LH]
    5609 #define RSCAN0RMDF161H RSCAN0.RMDF161.UINT16[H]
    5610 #define RSCAN0RMDF161HL RSCAN0.RMDF161.UINT8[HL]
    5611 #define RSCAN0RMDF161HH RSCAN0.RMDF161.UINT8[HH]
    5612 #define RSCAN0RMID62 RSCAN0.RMID62.UINT32
    5613 #define RSCAN0RMID62L RSCAN0.RMID62.UINT16[L]
    5614 #define RSCAN0RMID62LL RSCAN0.RMID62.UINT8[LL]
    5615 #define RSCAN0RMID62LH RSCAN0.RMID62.UINT8[LH]
    5616 #define RSCAN0RMID62H RSCAN0.RMID62.UINT16[H]
    5617 #define RSCAN0RMID62HL RSCAN0.RMID62.UINT8[HL]
    5618 #define RSCAN0RMID62HH RSCAN0.RMID62.UINT8[HH]
    5619 #define RSCAN0RMPTR62 RSCAN0.RMPTR62.UINT32
    5620 #define RSCAN0RMPTR62L RSCAN0.RMPTR62.UINT16[L]
    5621 #define RSCAN0RMPTR62LL RSCAN0.RMPTR62.UINT8[LL]
    5622 #define RSCAN0RMPTR62LH RSCAN0.RMPTR62.UINT8[LH]
    5623 #define RSCAN0RMPTR62H RSCAN0.RMPTR62.UINT16[H]
    5624 #define RSCAN0RMPTR62HL RSCAN0.RMPTR62.UINT8[HL]
    5625 #define RSCAN0RMPTR62HH RSCAN0.RMPTR62.UINT8[HH]
    5626 #define RSCAN0RMDF062 RSCAN0.RMDF062.UINT32
    5627 #define RSCAN0RMDF062L RSCAN0.RMDF062.UINT16[L]
    5628 #define RSCAN0RMDF062LL RSCAN0.RMDF062.UINT8[LL]
    5629 #define RSCAN0RMDF062LH RSCAN0.RMDF062.UINT8[LH]
    5630 #define RSCAN0RMDF062H RSCAN0.RMDF062.UINT16[H]
    5631 #define RSCAN0RMDF062HL RSCAN0.RMDF062.UINT8[HL]
    5632 #define RSCAN0RMDF062HH RSCAN0.RMDF062.UINT8[HH]
    5633 #define RSCAN0RMDF162 RSCAN0.RMDF162.UINT32
    5634 #define RSCAN0RMDF162L RSCAN0.RMDF162.UINT16[L]
    5635 #define RSCAN0RMDF162LL RSCAN0.RMDF162.UINT8[LL]
    5636 #define RSCAN0RMDF162LH RSCAN0.RMDF162.UINT8[LH]
    5637 #define RSCAN0RMDF162H RSCAN0.RMDF162.UINT16[H]
    5638 #define RSCAN0RMDF162HL RSCAN0.RMDF162.UINT8[HL]
    5639 #define RSCAN0RMDF162HH RSCAN0.RMDF162.UINT8[HH]
    5640 #define RSCAN0RMID63 RSCAN0.RMID63.UINT32
    5641 #define RSCAN0RMID63L RSCAN0.RMID63.UINT16[L]
    5642 #define RSCAN0RMID63LL RSCAN0.RMID63.UINT8[LL]
    5643 #define RSCAN0RMID63LH RSCAN0.RMID63.UINT8[LH]
    5644 #define RSCAN0RMID63H RSCAN0.RMID63.UINT16[H]
    5645 #define RSCAN0RMID63HL RSCAN0.RMID63.UINT8[HL]
    5646 #define RSCAN0RMID63HH RSCAN0.RMID63.UINT8[HH]
    5647 #define RSCAN0RMPTR63 RSCAN0.RMPTR63.UINT32
    5648 #define RSCAN0RMPTR63L RSCAN0.RMPTR63.UINT16[L]
    5649 #define RSCAN0RMPTR63LL RSCAN0.RMPTR63.UINT8[LL]
    5650 #define RSCAN0RMPTR63LH RSCAN0.RMPTR63.UINT8[LH]
    5651 #define RSCAN0RMPTR63H RSCAN0.RMPTR63.UINT16[H]
    5652 #define RSCAN0RMPTR63HL RSCAN0.RMPTR63.UINT8[HL]
    5653 #define RSCAN0RMPTR63HH RSCAN0.RMPTR63.UINT8[HH]
    5654 #define RSCAN0RMDF063 RSCAN0.RMDF063.UINT32
    5655 #define RSCAN0RMDF063L RSCAN0.RMDF063.UINT16[L]
    5656 #define RSCAN0RMDF063LL RSCAN0.RMDF063.UINT8[LL]
    5657 #define RSCAN0RMDF063LH RSCAN0.RMDF063.UINT8[LH]
    5658 #define RSCAN0RMDF063H RSCAN0.RMDF063.UINT16[H]
    5659 #define RSCAN0RMDF063HL RSCAN0.RMDF063.UINT8[HL]
    5660 #define RSCAN0RMDF063HH RSCAN0.RMDF063.UINT8[HH]
    5661 #define RSCAN0RMDF163 RSCAN0.RMDF163.UINT32
    5662 #define RSCAN0RMDF163L RSCAN0.RMDF163.UINT16[L]
    5663 #define RSCAN0RMDF163LL RSCAN0.RMDF163.UINT8[LL]
    5664 #define RSCAN0RMDF163LH RSCAN0.RMDF163.UINT8[LH]
    5665 #define RSCAN0RMDF163H RSCAN0.RMDF163.UINT16[H]
    5666 #define RSCAN0RMDF163HL RSCAN0.RMDF163.UINT8[HL]
    5667 #define RSCAN0RMDF163HH RSCAN0.RMDF163.UINT8[HH]
    5668 #define RSCAN0RMID64 RSCAN0.RMID64.UINT32
    5669 #define RSCAN0RMID64L RSCAN0.RMID64.UINT16[L]
    5670 #define RSCAN0RMID64LL RSCAN0.RMID64.UINT8[LL]
    5671 #define RSCAN0RMID64LH RSCAN0.RMID64.UINT8[LH]
    5672 #define RSCAN0RMID64H RSCAN0.RMID64.UINT16[H]
    5673 #define RSCAN0RMID64HL RSCAN0.RMID64.UINT8[HL]
    5674 #define RSCAN0RMID64HH RSCAN0.RMID64.UINT8[HH]
    5675 #define RSCAN0RMPTR64 RSCAN0.RMPTR64.UINT32
    5676 #define RSCAN0RMPTR64L RSCAN0.RMPTR64.UINT16[L]
    5677 #define RSCAN0RMPTR64LL RSCAN0.RMPTR64.UINT8[LL]
    5678 #define RSCAN0RMPTR64LH RSCAN0.RMPTR64.UINT8[LH]
    5679 #define RSCAN0RMPTR64H RSCAN0.RMPTR64.UINT16[H]
    5680 #define RSCAN0RMPTR64HL RSCAN0.RMPTR64.UINT8[HL]
    5681 #define RSCAN0RMPTR64HH RSCAN0.RMPTR64.UINT8[HH]
    5682 #define RSCAN0RMDF064 RSCAN0.RMDF064.UINT32
    5683 #define RSCAN0RMDF064L RSCAN0.RMDF064.UINT16[L]
    5684 #define RSCAN0RMDF064LL RSCAN0.RMDF064.UINT8[LL]
    5685 #define RSCAN0RMDF064LH RSCAN0.RMDF064.UINT8[LH]
    5686 #define RSCAN0RMDF064H RSCAN0.RMDF064.UINT16[H]
    5687 #define RSCAN0RMDF064HL RSCAN0.RMDF064.UINT8[HL]
    5688 #define RSCAN0RMDF064HH RSCAN0.RMDF064.UINT8[HH]
    5689 #define RSCAN0RMDF164 RSCAN0.RMDF164.UINT32
    5690 #define RSCAN0RMDF164L RSCAN0.RMDF164.UINT16[L]
    5691 #define RSCAN0RMDF164LL RSCAN0.RMDF164.UINT8[LL]
    5692 #define RSCAN0RMDF164LH RSCAN0.RMDF164.UINT8[LH]
    5693 #define RSCAN0RMDF164H RSCAN0.RMDF164.UINT16[H]
    5694 #define RSCAN0RMDF164HL RSCAN0.RMDF164.UINT8[HL]
    5695 #define RSCAN0RMDF164HH RSCAN0.RMDF164.UINT8[HH]
    5696 #define RSCAN0RMID65 RSCAN0.RMID65.UINT32
    5697 #define RSCAN0RMID65L RSCAN0.RMID65.UINT16[L]
    5698 #define RSCAN0RMID65LL RSCAN0.RMID65.UINT8[LL]
    5699 #define RSCAN0RMID65LH RSCAN0.RMID65.UINT8[LH]
    5700 #define RSCAN0RMID65H RSCAN0.RMID65.UINT16[H]
    5701 #define RSCAN0RMID65HL RSCAN0.RMID65.UINT8[HL]
    5702 #define RSCAN0RMID65HH RSCAN0.RMID65.UINT8[HH]
    5703 #define RSCAN0RMPTR65 RSCAN0.RMPTR65.UINT32
    5704 #define RSCAN0RMPTR65L RSCAN0.RMPTR65.UINT16[L]
    5705 #define RSCAN0RMPTR65LL RSCAN0.RMPTR65.UINT8[LL]
    5706 #define RSCAN0RMPTR65LH RSCAN0.RMPTR65.UINT8[LH]
    5707 #define RSCAN0RMPTR65H RSCAN0.RMPTR65.UINT16[H]
    5708 #define RSCAN0RMPTR65HL RSCAN0.RMPTR65.UINT8[HL]
    5709 #define RSCAN0RMPTR65HH RSCAN0.RMPTR65.UINT8[HH]
    5710 #define RSCAN0RMDF065 RSCAN0.RMDF065.UINT32
    5711 #define RSCAN0RMDF065L RSCAN0.RMDF065.UINT16[L]
    5712 #define RSCAN0RMDF065LL RSCAN0.RMDF065.UINT8[LL]
    5713 #define RSCAN0RMDF065LH RSCAN0.RMDF065.UINT8[LH]
    5714 #define RSCAN0RMDF065H RSCAN0.RMDF065.UINT16[H]
    5715 #define RSCAN0RMDF065HL RSCAN0.RMDF065.UINT8[HL]
    5716 #define RSCAN0RMDF065HH RSCAN0.RMDF065.UINT8[HH]
    5717 #define RSCAN0RMDF165 RSCAN0.RMDF165.UINT32
    5718 #define RSCAN0RMDF165L RSCAN0.RMDF165.UINT16[L]
    5719 #define RSCAN0RMDF165LL RSCAN0.RMDF165.UINT8[LL]
    5720 #define RSCAN0RMDF165LH RSCAN0.RMDF165.UINT8[LH]
    5721 #define RSCAN0RMDF165H RSCAN0.RMDF165.UINT16[H]
    5722 #define RSCAN0RMDF165HL RSCAN0.RMDF165.UINT8[HL]
    5723 #define RSCAN0RMDF165HH RSCAN0.RMDF165.UINT8[HH]
    5724 #define RSCAN0RMID66 RSCAN0.RMID66.UINT32
    5725 #define RSCAN0RMID66L RSCAN0.RMID66.UINT16[L]
    5726 #define RSCAN0RMID66LL RSCAN0.RMID66.UINT8[LL]
    5727 #define RSCAN0RMID66LH RSCAN0.RMID66.UINT8[LH]
    5728 #define RSCAN0RMID66H RSCAN0.RMID66.UINT16[H]
    5729 #define RSCAN0RMID66HL RSCAN0.RMID66.UINT8[HL]
    5730 #define RSCAN0RMID66HH RSCAN0.RMID66.UINT8[HH]
    5731 #define RSCAN0RMPTR66 RSCAN0.RMPTR66.UINT32
    5732 #define RSCAN0RMPTR66L RSCAN0.RMPTR66.UINT16[L]
    5733 #define RSCAN0RMPTR66LL RSCAN0.RMPTR66.UINT8[LL]
    5734 #define RSCAN0RMPTR66LH RSCAN0.RMPTR66.UINT8[LH]
    5735 #define RSCAN0RMPTR66H RSCAN0.RMPTR66.UINT16[H]
    5736 #define RSCAN0RMPTR66HL RSCAN0.RMPTR66.UINT8[HL]
    5737 #define RSCAN0RMPTR66HH RSCAN0.RMPTR66.UINT8[HH]
    5738 #define RSCAN0RMDF066 RSCAN0.RMDF066.UINT32
    5739 #define RSCAN0RMDF066L RSCAN0.RMDF066.UINT16[L]
    5740 #define RSCAN0RMDF066LL RSCAN0.RMDF066.UINT8[LL]
    5741 #define RSCAN0RMDF066LH RSCAN0.RMDF066.UINT8[LH]
    5742 #define RSCAN0RMDF066H RSCAN0.RMDF066.UINT16[H]
    5743 #define RSCAN0RMDF066HL RSCAN0.RMDF066.UINT8[HL]
    5744 #define RSCAN0RMDF066HH RSCAN0.RMDF066.UINT8[HH]
    5745 #define RSCAN0RMDF166 RSCAN0.RMDF166.UINT32
    5746 #define RSCAN0RMDF166L RSCAN0.RMDF166.UINT16[L]
    5747 #define RSCAN0RMDF166LL RSCAN0.RMDF166.UINT8[LL]
    5748 #define RSCAN0RMDF166LH RSCAN0.RMDF166.UINT8[LH]
    5749 #define RSCAN0RMDF166H RSCAN0.RMDF166.UINT16[H]
    5750 #define RSCAN0RMDF166HL RSCAN0.RMDF166.UINT8[HL]
    5751 #define RSCAN0RMDF166HH RSCAN0.RMDF166.UINT8[HH]
    5752 #define RSCAN0RMID67 RSCAN0.RMID67.UINT32
    5753 #define RSCAN0RMID67L RSCAN0.RMID67.UINT16[L]
    5754 #define RSCAN0RMID67LL RSCAN0.RMID67.UINT8[LL]
    5755 #define RSCAN0RMID67LH RSCAN0.RMID67.UINT8[LH]
    5756 #define RSCAN0RMID67H RSCAN0.RMID67.UINT16[H]
    5757 #define RSCAN0RMID67HL RSCAN0.RMID67.UINT8[HL]
    5758 #define RSCAN0RMID67HH RSCAN0.RMID67.UINT8[HH]
    5759 #define RSCAN0RMPTR67 RSCAN0.RMPTR67.UINT32
    5760 #define RSCAN0RMPTR67L RSCAN0.RMPTR67.UINT16[L]
    5761 #define RSCAN0RMPTR67LL RSCAN0.RMPTR67.UINT8[LL]
    5762 #define RSCAN0RMPTR67LH RSCAN0.RMPTR67.UINT8[LH]
    5763 #define RSCAN0RMPTR67H RSCAN0.RMPTR67.UINT16[H]
    5764 #define RSCAN0RMPTR67HL RSCAN0.RMPTR67.UINT8[HL]
    5765 #define RSCAN0RMPTR67HH RSCAN0.RMPTR67.UINT8[HH]
    5766 #define RSCAN0RMDF067 RSCAN0.RMDF067.UINT32
    5767 #define RSCAN0RMDF067L RSCAN0.RMDF067.UINT16[L]
    5768 #define RSCAN0RMDF067LL RSCAN0.RMDF067.UINT8[LL]
    5769 #define RSCAN0RMDF067LH RSCAN0.RMDF067.UINT8[LH]
    5770 #define RSCAN0RMDF067H RSCAN0.RMDF067.UINT16[H]
    5771 #define RSCAN0RMDF067HL RSCAN0.RMDF067.UINT8[HL]
    5772 #define RSCAN0RMDF067HH RSCAN0.RMDF067.UINT8[HH]
    5773 #define RSCAN0RMDF167 RSCAN0.RMDF167.UINT32
    5774 #define RSCAN0RMDF167L RSCAN0.RMDF167.UINT16[L]
    5775 #define RSCAN0RMDF167LL RSCAN0.RMDF167.UINT8[LL]
    5776 #define RSCAN0RMDF167LH RSCAN0.RMDF167.UINT8[LH]
    5777 #define RSCAN0RMDF167H RSCAN0.RMDF167.UINT16[H]
    5778 #define RSCAN0RMDF167HL RSCAN0.RMDF167.UINT8[HL]
    5779 #define RSCAN0RMDF167HH RSCAN0.RMDF167.UINT8[HH]
    5780 #define RSCAN0RMID68 RSCAN0.RMID68.UINT32
    5781 #define RSCAN0RMID68L RSCAN0.RMID68.UINT16[L]
    5782 #define RSCAN0RMID68LL RSCAN0.RMID68.UINT8[LL]
    5783 #define RSCAN0RMID68LH RSCAN0.RMID68.UINT8[LH]
    5784 #define RSCAN0RMID68H RSCAN0.RMID68.UINT16[H]
    5785 #define RSCAN0RMID68HL RSCAN0.RMID68.UINT8[HL]
    5786 #define RSCAN0RMID68HH RSCAN0.RMID68.UINT8[HH]
    5787 #define RSCAN0RMPTR68 RSCAN0.RMPTR68.UINT32
    5788 #define RSCAN0RMPTR68L RSCAN0.RMPTR68.UINT16[L]
    5789 #define RSCAN0RMPTR68LL RSCAN0.RMPTR68.UINT8[LL]
    5790 #define RSCAN0RMPTR68LH RSCAN0.RMPTR68.UINT8[LH]
    5791 #define RSCAN0RMPTR68H RSCAN0.RMPTR68.UINT16[H]
    5792 #define RSCAN0RMPTR68HL RSCAN0.RMPTR68.UINT8[HL]
    5793 #define RSCAN0RMPTR68HH RSCAN0.RMPTR68.UINT8[HH]
    5794 #define RSCAN0RMDF068 RSCAN0.RMDF068.UINT32
    5795 #define RSCAN0RMDF068L RSCAN0.RMDF068.UINT16[L]
    5796 #define RSCAN0RMDF068LL RSCAN0.RMDF068.UINT8[LL]
    5797 #define RSCAN0RMDF068LH RSCAN0.RMDF068.UINT8[LH]
    5798 #define RSCAN0RMDF068H RSCAN0.RMDF068.UINT16[H]
    5799 #define RSCAN0RMDF068HL RSCAN0.RMDF068.UINT8[HL]
    5800 #define RSCAN0RMDF068HH RSCAN0.RMDF068.UINT8[HH]
    5801 #define RSCAN0RMDF168 RSCAN0.RMDF168.UINT32
    5802 #define RSCAN0RMDF168L RSCAN0.RMDF168.UINT16[L]
    5803 #define RSCAN0RMDF168LL RSCAN0.RMDF168.UINT8[LL]
    5804 #define RSCAN0RMDF168LH RSCAN0.RMDF168.UINT8[LH]
    5805 #define RSCAN0RMDF168H RSCAN0.RMDF168.UINT16[H]
    5806 #define RSCAN0RMDF168HL RSCAN0.RMDF168.UINT8[HL]
    5807 #define RSCAN0RMDF168HH RSCAN0.RMDF168.UINT8[HH]
    5808 #define RSCAN0RMID69 RSCAN0.RMID69.UINT32
    5809 #define RSCAN0RMID69L RSCAN0.RMID69.UINT16[L]
    5810 #define RSCAN0RMID69LL RSCAN0.RMID69.UINT8[LL]
    5811 #define RSCAN0RMID69LH RSCAN0.RMID69.UINT8[LH]
    5812 #define RSCAN0RMID69H RSCAN0.RMID69.UINT16[H]
    5813 #define RSCAN0RMID69HL RSCAN0.RMID69.UINT8[HL]
    5814 #define RSCAN0RMID69HH RSCAN0.RMID69.UINT8[HH]
    5815 #define RSCAN0RMPTR69 RSCAN0.RMPTR69.UINT32
    5816 #define RSCAN0RMPTR69L RSCAN0.RMPTR69.UINT16[L]
    5817 #define RSCAN0RMPTR69LL RSCAN0.RMPTR69.UINT8[LL]
    5818 #define RSCAN0RMPTR69LH RSCAN0.RMPTR69.UINT8[LH]
    5819 #define RSCAN0RMPTR69H RSCAN0.RMPTR69.UINT16[H]
    5820 #define RSCAN0RMPTR69HL RSCAN0.RMPTR69.UINT8[HL]
    5821 #define RSCAN0RMPTR69HH RSCAN0.RMPTR69.UINT8[HH]
    5822 #define RSCAN0RMDF069 RSCAN0.RMDF069.UINT32
    5823 #define RSCAN0RMDF069L RSCAN0.RMDF069.UINT16[L]
    5824 #define RSCAN0RMDF069LL RSCAN0.RMDF069.UINT8[LL]
    5825 #define RSCAN0RMDF069LH RSCAN0.RMDF069.UINT8[LH]
    5826 #define RSCAN0RMDF069H RSCAN0.RMDF069.UINT16[H]
    5827 #define RSCAN0RMDF069HL RSCAN0.RMDF069.UINT8[HL]
    5828 #define RSCAN0RMDF069HH RSCAN0.RMDF069.UINT8[HH]
    5829 #define RSCAN0RMDF169 RSCAN0.RMDF169.UINT32
    5830 #define RSCAN0RMDF169L RSCAN0.RMDF169.UINT16[L]
    5831 #define RSCAN0RMDF169LL RSCAN0.RMDF169.UINT8[LL]
    5832 #define RSCAN0RMDF169LH RSCAN0.RMDF169.UINT8[LH]
    5833 #define RSCAN0RMDF169H RSCAN0.RMDF169.UINT16[H]
    5834 #define RSCAN0RMDF169HL RSCAN0.RMDF169.UINT8[HL]
    5835 #define RSCAN0RMDF169HH RSCAN0.RMDF169.UINT8[HH]
    5836 #define RSCAN0RMID70 RSCAN0.RMID70.UINT32
    5837 #define RSCAN0RMID70L RSCAN0.RMID70.UINT16[L]
    5838 #define RSCAN0RMID70LL RSCAN0.RMID70.UINT8[LL]
    5839 #define RSCAN0RMID70LH RSCAN0.RMID70.UINT8[LH]
    5840 #define RSCAN0RMID70H RSCAN0.RMID70.UINT16[H]
    5841 #define RSCAN0RMID70HL RSCAN0.RMID70.UINT8[HL]
    5842 #define RSCAN0RMID70HH RSCAN0.RMID70.UINT8[HH]
    5843 #define RSCAN0RMPTR70 RSCAN0.RMPTR70.UINT32
    5844 #define RSCAN0RMPTR70L RSCAN0.RMPTR70.UINT16[L]
    5845 #define RSCAN0RMPTR70LL RSCAN0.RMPTR70.UINT8[LL]
    5846 #define RSCAN0RMPTR70LH RSCAN0.RMPTR70.UINT8[LH]
    5847 #define RSCAN0RMPTR70H RSCAN0.RMPTR70.UINT16[H]
    5848 #define RSCAN0RMPTR70HL RSCAN0.RMPTR70.UINT8[HL]
    5849 #define RSCAN0RMPTR70HH RSCAN0.RMPTR70.UINT8[HH]
    5850 #define RSCAN0RMDF070 RSCAN0.RMDF070.UINT32
    5851 #define RSCAN0RMDF070L RSCAN0.RMDF070.UINT16[L]
    5852 #define RSCAN0RMDF070LL RSCAN0.RMDF070.UINT8[LL]
    5853 #define RSCAN0RMDF070LH RSCAN0.RMDF070.UINT8[LH]
    5854 #define RSCAN0RMDF070H RSCAN0.RMDF070.UINT16[H]
    5855 #define RSCAN0RMDF070HL RSCAN0.RMDF070.UINT8[HL]
    5856 #define RSCAN0RMDF070HH RSCAN0.RMDF070.UINT8[HH]
    5857 #define RSCAN0RMDF170 RSCAN0.RMDF170.UINT32
    5858 #define RSCAN0RMDF170L RSCAN0.RMDF170.UINT16[L]
    5859 #define RSCAN0RMDF170LL RSCAN0.RMDF170.UINT8[LL]
    5860 #define RSCAN0RMDF170LH RSCAN0.RMDF170.UINT8[LH]
    5861 #define RSCAN0RMDF170H RSCAN0.RMDF170.UINT16[H]
    5862 #define RSCAN0RMDF170HL RSCAN0.RMDF170.UINT8[HL]
    5863 #define RSCAN0RMDF170HH RSCAN0.RMDF170.UINT8[HH]
    5864 #define RSCAN0RMID71 RSCAN0.RMID71.UINT32
    5865 #define RSCAN0RMID71L RSCAN0.RMID71.UINT16[L]
    5866 #define RSCAN0RMID71LL RSCAN0.RMID71.UINT8[LL]
    5867 #define RSCAN0RMID71LH RSCAN0.RMID71.UINT8[LH]
    5868 #define RSCAN0RMID71H RSCAN0.RMID71.UINT16[H]
    5869 #define RSCAN0RMID71HL RSCAN0.RMID71.UINT8[HL]
    5870 #define RSCAN0RMID71HH RSCAN0.RMID71.UINT8[HH]
    5871 #define RSCAN0RMPTR71 RSCAN0.RMPTR71.UINT32
    5872 #define RSCAN0RMPTR71L RSCAN0.RMPTR71.UINT16[L]
    5873 #define RSCAN0RMPTR71LL RSCAN0.RMPTR71.UINT8[LL]
    5874 #define RSCAN0RMPTR71LH RSCAN0.RMPTR71.UINT8[LH]
    5875 #define RSCAN0RMPTR71H RSCAN0.RMPTR71.UINT16[H]
    5876 #define RSCAN0RMPTR71HL RSCAN0.RMPTR71.UINT8[HL]
    5877 #define RSCAN0RMPTR71HH RSCAN0.RMPTR71.UINT8[HH]
    5878 #define RSCAN0RMDF071 RSCAN0.RMDF071.UINT32
    5879 #define RSCAN0RMDF071L RSCAN0.RMDF071.UINT16[L]
    5880 #define RSCAN0RMDF071LL RSCAN0.RMDF071.UINT8[LL]
    5881 #define RSCAN0RMDF071LH RSCAN0.RMDF071.UINT8[LH]
    5882 #define RSCAN0RMDF071H RSCAN0.RMDF071.UINT16[H]
    5883 #define RSCAN0RMDF071HL RSCAN0.RMDF071.UINT8[HL]
    5884 #define RSCAN0RMDF071HH RSCAN0.RMDF071.UINT8[HH]
    5885 #define RSCAN0RMDF171 RSCAN0.RMDF171.UINT32
    5886 #define RSCAN0RMDF171L RSCAN0.RMDF171.UINT16[L]
    5887 #define RSCAN0RMDF171LL RSCAN0.RMDF171.UINT8[LL]
    5888 #define RSCAN0RMDF171LH RSCAN0.RMDF171.UINT8[LH]
    5889 #define RSCAN0RMDF171H RSCAN0.RMDF171.UINT16[H]
    5890 #define RSCAN0RMDF171HL RSCAN0.RMDF171.UINT8[HL]
    5891 #define RSCAN0RMDF171HH RSCAN0.RMDF171.UINT8[HH]
    5892 #define RSCAN0RMID72 RSCAN0.RMID72.UINT32
    5893 #define RSCAN0RMID72L RSCAN0.RMID72.UINT16[L]
    5894 #define RSCAN0RMID72LL RSCAN0.RMID72.UINT8[LL]
    5895 #define RSCAN0RMID72LH RSCAN0.RMID72.UINT8[LH]
    5896 #define RSCAN0RMID72H RSCAN0.RMID72.UINT16[H]
    5897 #define RSCAN0RMID72HL RSCAN0.RMID72.UINT8[HL]
    5898 #define RSCAN0RMID72HH RSCAN0.RMID72.UINT8[HH]
    5899 #define RSCAN0RMPTR72 RSCAN0.RMPTR72.UINT32
    5900 #define RSCAN0RMPTR72L RSCAN0.RMPTR72.UINT16[L]
    5901 #define RSCAN0RMPTR72LL RSCAN0.RMPTR72.UINT8[LL]
    5902 #define RSCAN0RMPTR72LH RSCAN0.RMPTR72.UINT8[LH]
    5903 #define RSCAN0RMPTR72H RSCAN0.RMPTR72.UINT16[H]
    5904 #define RSCAN0RMPTR72HL RSCAN0.RMPTR72.UINT8[HL]
    5905 #define RSCAN0RMPTR72HH RSCAN0.RMPTR72.UINT8[HH]
    5906 #define RSCAN0RMDF072 RSCAN0.RMDF072.UINT32
    5907 #define RSCAN0RMDF072L RSCAN0.RMDF072.UINT16[L]
    5908 #define RSCAN0RMDF072LL RSCAN0.RMDF072.UINT8[LL]
    5909 #define RSCAN0RMDF072LH RSCAN0.RMDF072.UINT8[LH]
    5910 #define RSCAN0RMDF072H RSCAN0.RMDF072.UINT16[H]
    5911 #define RSCAN0RMDF072HL RSCAN0.RMDF072.UINT8[HL]
    5912 #define RSCAN0RMDF072HH RSCAN0.RMDF072.UINT8[HH]
    5913 #define RSCAN0RMDF172 RSCAN0.RMDF172.UINT32
    5914 #define RSCAN0RMDF172L RSCAN0.RMDF172.UINT16[L]
    5915 #define RSCAN0RMDF172LL RSCAN0.RMDF172.UINT8[LL]
    5916 #define RSCAN0RMDF172LH RSCAN0.RMDF172.UINT8[LH]
    5917 #define RSCAN0RMDF172H RSCAN0.RMDF172.UINT16[H]
    5918 #define RSCAN0RMDF172HL RSCAN0.RMDF172.UINT8[HL]
    5919 #define RSCAN0RMDF172HH RSCAN0.RMDF172.UINT8[HH]
    5920 #define RSCAN0RMID73 RSCAN0.RMID73.UINT32
    5921 #define RSCAN0RMID73L RSCAN0.RMID73.UINT16[L]
    5922 #define RSCAN0RMID73LL RSCAN0.RMID73.UINT8[LL]
    5923 #define RSCAN0RMID73LH RSCAN0.RMID73.UINT8[LH]
    5924 #define RSCAN0RMID73H RSCAN0.RMID73.UINT16[H]
    5925 #define RSCAN0RMID73HL RSCAN0.RMID73.UINT8[HL]
    5926 #define RSCAN0RMID73HH RSCAN0.RMID73.UINT8[HH]
    5927 #define RSCAN0RMPTR73 RSCAN0.RMPTR73.UINT32
    5928 #define RSCAN0RMPTR73L RSCAN0.RMPTR73.UINT16[L]
    5929 #define RSCAN0RMPTR73LL RSCAN0.RMPTR73.UINT8[LL]
    5930 #define RSCAN0RMPTR73LH RSCAN0.RMPTR73.UINT8[LH]
    5931 #define RSCAN0RMPTR73H RSCAN0.RMPTR73.UINT16[H]
    5932 #define RSCAN0RMPTR73HL RSCAN0.RMPTR73.UINT8[HL]
    5933 #define RSCAN0RMPTR73HH RSCAN0.RMPTR73.UINT8[HH]
    5934 #define RSCAN0RMDF073 RSCAN0.RMDF073.UINT32
    5935 #define RSCAN0RMDF073L RSCAN0.RMDF073.UINT16[L]
    5936 #define RSCAN0RMDF073LL RSCAN0.RMDF073.UINT8[LL]
    5937 #define RSCAN0RMDF073LH RSCAN0.RMDF073.UINT8[LH]
    5938 #define RSCAN0RMDF073H RSCAN0.RMDF073.UINT16[H]
    5939 #define RSCAN0RMDF073HL RSCAN0.RMDF073.UINT8[HL]
    5940 #define RSCAN0RMDF073HH RSCAN0.RMDF073.UINT8[HH]
    5941 #define RSCAN0RMDF173 RSCAN0.RMDF173.UINT32
    5942 #define RSCAN0RMDF173L RSCAN0.RMDF173.UINT16[L]
    5943 #define RSCAN0RMDF173LL RSCAN0.RMDF173.UINT8[LL]
    5944 #define RSCAN0RMDF173LH RSCAN0.RMDF173.UINT8[LH]
    5945 #define RSCAN0RMDF173H RSCAN0.RMDF173.UINT16[H]
    5946 #define RSCAN0RMDF173HL RSCAN0.RMDF173.UINT8[HL]
    5947 #define RSCAN0RMDF173HH RSCAN0.RMDF173.UINT8[HH]
    5948 #define RSCAN0RMID74 RSCAN0.RMID74.UINT32
    5949 #define RSCAN0RMID74L RSCAN0.RMID74.UINT16[L]
    5950 #define RSCAN0RMID74LL RSCAN0.RMID74.UINT8[LL]
    5951 #define RSCAN0RMID74LH RSCAN0.RMID74.UINT8[LH]
    5952 #define RSCAN0RMID74H RSCAN0.RMID74.UINT16[H]
    5953 #define RSCAN0RMID74HL RSCAN0.RMID74.UINT8[HL]
    5954 #define RSCAN0RMID74HH RSCAN0.RMID74.UINT8[HH]
    5955 #define RSCAN0RMPTR74 RSCAN0.RMPTR74.UINT32
    5956 #define RSCAN0RMPTR74L RSCAN0.RMPTR74.UINT16[L]
    5957 #define RSCAN0RMPTR74LL RSCAN0.RMPTR74.UINT8[LL]
    5958 #define RSCAN0RMPTR74LH RSCAN0.RMPTR74.UINT8[LH]
    5959 #define RSCAN0RMPTR74H RSCAN0.RMPTR74.UINT16[H]
    5960 #define RSCAN0RMPTR74HL RSCAN0.RMPTR74.UINT8[HL]
    5961 #define RSCAN0RMPTR74HH RSCAN0.RMPTR74.UINT8[HH]
    5962 #define RSCAN0RMDF074 RSCAN0.RMDF074.UINT32
    5963 #define RSCAN0RMDF074L RSCAN0.RMDF074.UINT16[L]
    5964 #define RSCAN0RMDF074LL RSCAN0.RMDF074.UINT8[LL]
    5965 #define RSCAN0RMDF074LH RSCAN0.RMDF074.UINT8[LH]
    5966 #define RSCAN0RMDF074H RSCAN0.RMDF074.UINT16[H]
    5967 #define RSCAN0RMDF074HL RSCAN0.RMDF074.UINT8[HL]
    5968 #define RSCAN0RMDF074HH RSCAN0.RMDF074.UINT8[HH]
    5969 #define RSCAN0RMDF174 RSCAN0.RMDF174.UINT32
    5970 #define RSCAN0RMDF174L RSCAN0.RMDF174.UINT16[L]
    5971 #define RSCAN0RMDF174LL RSCAN0.RMDF174.UINT8[LL]
    5972 #define RSCAN0RMDF174LH RSCAN0.RMDF174.UINT8[LH]
    5973 #define RSCAN0RMDF174H RSCAN0.RMDF174.UINT16[H]
    5974 #define RSCAN0RMDF174HL RSCAN0.RMDF174.UINT8[HL]
    5975 #define RSCAN0RMDF174HH RSCAN0.RMDF174.UINT8[HH]
    5976 #define RSCAN0RMID75 RSCAN0.RMID75.UINT32
    5977 #define RSCAN0RMID75L RSCAN0.RMID75.UINT16[L]
    5978 #define RSCAN0RMID75LL RSCAN0.RMID75.UINT8[LL]
    5979 #define RSCAN0RMID75LH RSCAN0.RMID75.UINT8[LH]
    5980 #define RSCAN0RMID75H RSCAN0.RMID75.UINT16[H]
    5981 #define RSCAN0RMID75HL RSCAN0.RMID75.UINT8[HL]
    5982 #define RSCAN0RMID75HH RSCAN0.RMID75.UINT8[HH]
    5983 #define RSCAN0RMPTR75 RSCAN0.RMPTR75.UINT32
    5984 #define RSCAN0RMPTR75L RSCAN0.RMPTR75.UINT16[L]
    5985 #define RSCAN0RMPTR75LL RSCAN0.RMPTR75.UINT8[LL]
    5986 #define RSCAN0RMPTR75LH RSCAN0.RMPTR75.UINT8[LH]
    5987 #define RSCAN0RMPTR75H RSCAN0.RMPTR75.UINT16[H]
    5988 #define RSCAN0RMPTR75HL RSCAN0.RMPTR75.UINT8[HL]
    5989 #define RSCAN0RMPTR75HH RSCAN0.RMPTR75.UINT8[HH]
    5990 #define RSCAN0RMDF075 RSCAN0.RMDF075.UINT32
    5991 #define RSCAN0RMDF075L RSCAN0.RMDF075.UINT16[L]
    5992 #define RSCAN0RMDF075LL RSCAN0.RMDF075.UINT8[LL]
    5993 #define RSCAN0RMDF075LH RSCAN0.RMDF075.UINT8[LH]
    5994 #define RSCAN0RMDF075H RSCAN0.RMDF075.UINT16[H]
    5995 #define RSCAN0RMDF075HL RSCAN0.RMDF075.UINT8[HL]
    5996 #define RSCAN0RMDF075HH RSCAN0.RMDF075.UINT8[HH]
    5997 #define RSCAN0RMDF175 RSCAN0.RMDF175.UINT32
    5998 #define RSCAN0RMDF175L RSCAN0.RMDF175.UINT16[L]
    5999 #define RSCAN0RMDF175LL RSCAN0.RMDF175.UINT8[LL]
    6000 #define RSCAN0RMDF175LH RSCAN0.RMDF175.UINT8[LH]
    6001 #define RSCAN0RMDF175H RSCAN0.RMDF175.UINT16[H]
    6002 #define RSCAN0RMDF175HL RSCAN0.RMDF175.UINT8[HL]
    6003 #define RSCAN0RMDF175HH RSCAN0.RMDF175.UINT8[HH]
    6004 #define RSCAN0RMID76 RSCAN0.RMID76.UINT32
    6005 #define RSCAN0RMID76L RSCAN0.RMID76.UINT16[L]
    6006 #define RSCAN0RMID76LL RSCAN0.RMID76.UINT8[LL]
    6007 #define RSCAN0RMID76LH RSCAN0.RMID76.UINT8[LH]
    6008 #define RSCAN0RMID76H RSCAN0.RMID76.UINT16[H]
    6009 #define RSCAN0RMID76HL RSCAN0.RMID76.UINT8[HL]
    6010 #define RSCAN0RMID76HH RSCAN0.RMID76.UINT8[HH]
    6011 #define RSCAN0RMPTR76 RSCAN0.RMPTR76.UINT32
    6012 #define RSCAN0RMPTR76L RSCAN0.RMPTR76.UINT16[L]
    6013 #define RSCAN0RMPTR76LL RSCAN0.RMPTR76.UINT8[LL]
    6014 #define RSCAN0RMPTR76LH RSCAN0.RMPTR76.UINT8[LH]
    6015 #define RSCAN0RMPTR76H RSCAN0.RMPTR76.UINT16[H]
    6016 #define RSCAN0RMPTR76HL RSCAN0.RMPTR76.UINT8[HL]
    6017 #define RSCAN0RMPTR76HH RSCAN0.RMPTR76.UINT8[HH]
    6018 #define RSCAN0RMDF076 RSCAN0.RMDF076.UINT32
    6019 #define RSCAN0RMDF076L RSCAN0.RMDF076.UINT16[L]
    6020 #define RSCAN0RMDF076LL RSCAN0.RMDF076.UINT8[LL]
    6021 #define RSCAN0RMDF076LH RSCAN0.RMDF076.UINT8[LH]
    6022 #define RSCAN0RMDF076H RSCAN0.RMDF076.UINT16[H]
    6023 #define RSCAN0RMDF076HL RSCAN0.RMDF076.UINT8[HL]
    6024 #define RSCAN0RMDF076HH RSCAN0.RMDF076.UINT8[HH]
    6025 #define RSCAN0RMDF176 RSCAN0.RMDF176.UINT32
    6026 #define RSCAN0RMDF176L RSCAN0.RMDF176.UINT16[L]
    6027 #define RSCAN0RMDF176LL RSCAN0.RMDF176.UINT8[LL]
    6028 #define RSCAN0RMDF176LH RSCAN0.RMDF176.UINT8[LH]
    6029 #define RSCAN0RMDF176H RSCAN0.RMDF176.UINT16[H]
    6030 #define RSCAN0RMDF176HL RSCAN0.RMDF176.UINT8[HL]
    6031 #define RSCAN0RMDF176HH RSCAN0.RMDF176.UINT8[HH]
    6032 #define RSCAN0RMID77 RSCAN0.RMID77.UINT32
    6033 #define RSCAN0RMID77L RSCAN0.RMID77.UINT16[L]
    6034 #define RSCAN0RMID77LL RSCAN0.RMID77.UINT8[LL]
    6035 #define RSCAN0RMID77LH RSCAN0.RMID77.UINT8[LH]
    6036 #define RSCAN0RMID77H RSCAN0.RMID77.UINT16[H]
    6037 #define RSCAN0RMID77HL RSCAN0.RMID77.UINT8[HL]
    6038 #define RSCAN0RMID77HH RSCAN0.RMID77.UINT8[HH]
    6039 #define RSCAN0RMPTR77 RSCAN0.RMPTR77.UINT32
    6040 #define RSCAN0RMPTR77L RSCAN0.RMPTR77.UINT16[L]
    6041 #define RSCAN0RMPTR77LL RSCAN0.RMPTR77.UINT8[LL]
    6042 #define RSCAN0RMPTR77LH RSCAN0.RMPTR77.UINT8[LH]
    6043 #define RSCAN0RMPTR77H RSCAN0.RMPTR77.UINT16[H]
    6044 #define RSCAN0RMPTR77HL RSCAN0.RMPTR77.UINT8[HL]
    6045 #define RSCAN0RMPTR77HH RSCAN0.RMPTR77.UINT8[HH]
    6046 #define RSCAN0RMDF077 RSCAN0.RMDF077.UINT32
    6047 #define RSCAN0RMDF077L RSCAN0.RMDF077.UINT16[L]
    6048 #define RSCAN0RMDF077LL RSCAN0.RMDF077.UINT8[LL]
    6049 #define RSCAN0RMDF077LH RSCAN0.RMDF077.UINT8[LH]
    6050 #define RSCAN0RMDF077H RSCAN0.RMDF077.UINT16[H]
    6051 #define RSCAN0RMDF077HL RSCAN0.RMDF077.UINT8[HL]
    6052 #define RSCAN0RMDF077HH RSCAN0.RMDF077.UINT8[HH]
    6053 #define RSCAN0RMDF177 RSCAN0.RMDF177.UINT32
    6054 #define RSCAN0RMDF177L RSCAN0.RMDF177.UINT16[L]
    6055 #define RSCAN0RMDF177LL RSCAN0.RMDF177.UINT8[LL]
    6056 #define RSCAN0RMDF177LH RSCAN0.RMDF177.UINT8[LH]
    6057 #define RSCAN0RMDF177H RSCAN0.RMDF177.UINT16[H]
    6058 #define RSCAN0RMDF177HL RSCAN0.RMDF177.UINT8[HL]
    6059 #define RSCAN0RMDF177HH RSCAN0.RMDF177.UINT8[HH]
    6060 #define RSCAN0RMID78 RSCAN0.RMID78.UINT32
    6061 #define RSCAN0RMID78L RSCAN0.RMID78.UINT16[L]
    6062 #define RSCAN0RMID78LL RSCAN0.RMID78.UINT8[LL]
    6063 #define RSCAN0RMID78LH RSCAN0.RMID78.UINT8[LH]
    6064 #define RSCAN0RMID78H RSCAN0.RMID78.UINT16[H]
    6065 #define RSCAN0RMID78HL RSCAN0.RMID78.UINT8[HL]
    6066 #define RSCAN0RMID78HH RSCAN0.RMID78.UINT8[HH]
    6067 #define RSCAN0RMPTR78 RSCAN0.RMPTR78.UINT32
    6068 #define RSCAN0RMPTR78L RSCAN0.RMPTR78.UINT16[L]
    6069 #define RSCAN0RMPTR78LL RSCAN0.RMPTR78.UINT8[LL]
    6070 #define RSCAN0RMPTR78LH RSCAN0.RMPTR78.UINT8[LH]
    6071 #define RSCAN0RMPTR78H RSCAN0.RMPTR78.UINT16[H]
    6072 #define RSCAN0RMPTR78HL RSCAN0.RMPTR78.UINT8[HL]
    6073 #define RSCAN0RMPTR78HH RSCAN0.RMPTR78.UINT8[HH]
    6074 #define RSCAN0RMDF078 RSCAN0.RMDF078.UINT32
    6075 #define RSCAN0RMDF078L RSCAN0.RMDF078.UINT16[L]
    6076 #define RSCAN0RMDF078LL RSCAN0.RMDF078.UINT8[LL]
    6077 #define RSCAN0RMDF078LH RSCAN0.RMDF078.UINT8[LH]
    6078 #define RSCAN0RMDF078H RSCAN0.RMDF078.UINT16[H]
    6079 #define RSCAN0RMDF078HL RSCAN0.RMDF078.UINT8[HL]
    6080 #define RSCAN0RMDF078HH RSCAN0.RMDF078.UINT8[HH]
    6081 #define RSCAN0RMDF178 RSCAN0.RMDF178.UINT32
    6082 #define RSCAN0RMDF178L RSCAN0.RMDF178.UINT16[L]
    6083 #define RSCAN0RMDF178LL RSCAN0.RMDF178.UINT8[LL]
    6084 #define RSCAN0RMDF178LH RSCAN0.RMDF178.UINT8[LH]
    6085 #define RSCAN0RMDF178H RSCAN0.RMDF178.UINT16[H]
    6086 #define RSCAN0RMDF178HL RSCAN0.RMDF178.UINT8[HL]
    6087 #define RSCAN0RMDF178HH RSCAN0.RMDF178.UINT8[HH]
    6088 #define RSCAN0RMID79 RSCAN0.RMID79.UINT32
    6089 #define RSCAN0RMID79L RSCAN0.RMID79.UINT16[L]
    6090 #define RSCAN0RMID79LL RSCAN0.RMID79.UINT8[LL]
    6091 #define RSCAN0RMID79LH RSCAN0.RMID79.UINT8[LH]
    6092 #define RSCAN0RMID79H RSCAN0.RMID79.UINT16[H]
    6093 #define RSCAN0RMID79HL RSCAN0.RMID79.UINT8[HL]
    6094 #define RSCAN0RMID79HH RSCAN0.RMID79.UINT8[HH]
    6095 #define RSCAN0RMPTR79 RSCAN0.RMPTR79.UINT32
    6096 #define RSCAN0RMPTR79L RSCAN0.RMPTR79.UINT16[L]
    6097 #define RSCAN0RMPTR79LL RSCAN0.RMPTR79.UINT8[LL]
    6098 #define RSCAN0RMPTR79LH RSCAN0.RMPTR79.UINT8[LH]
    6099 #define RSCAN0RMPTR79H RSCAN0.RMPTR79.UINT16[H]
    6100 #define RSCAN0RMPTR79HL RSCAN0.RMPTR79.UINT8[HL]
    6101 #define RSCAN0RMPTR79HH RSCAN0.RMPTR79.UINT8[HH]
    6102 #define RSCAN0RMDF079 RSCAN0.RMDF079.UINT32
    6103 #define RSCAN0RMDF079L RSCAN0.RMDF079.UINT16[L]
    6104 #define RSCAN0RMDF079LL RSCAN0.RMDF079.UINT8[LL]
    6105 #define RSCAN0RMDF079LH RSCAN0.RMDF079.UINT8[LH]
    6106 #define RSCAN0RMDF079H RSCAN0.RMDF079.UINT16[H]
    6107 #define RSCAN0RMDF079HL RSCAN0.RMDF079.UINT8[HL]
    6108 #define RSCAN0RMDF079HH RSCAN0.RMDF079.UINT8[HH]
    6109 #define RSCAN0RMDF179 RSCAN0.RMDF179.UINT32
    6110 #define RSCAN0RMDF179L RSCAN0.RMDF179.UINT16[L]
    6111 #define RSCAN0RMDF179LL RSCAN0.RMDF179.UINT8[LL]
    6112 #define RSCAN0RMDF179LH RSCAN0.RMDF179.UINT8[LH]
    6113 #define RSCAN0RMDF179H RSCAN0.RMDF179.UINT16[H]
    6114 #define RSCAN0RMDF179HL RSCAN0.RMDF179.UINT8[HL]
    6115 #define RSCAN0RMDF179HH RSCAN0.RMDF179.UINT8[HH]
    6116 #define RSCAN0RFID0 RSCAN0.RFID0.UINT32
    6117 #define RSCAN0RFID0L RSCAN0.RFID0.UINT16[L]
    6118 #define RSCAN0RFID0LL RSCAN0.RFID0.UINT8[LL]
    6119 #define RSCAN0RFID0LH RSCAN0.RFID0.UINT8[LH]
    6120 #define RSCAN0RFID0H RSCAN0.RFID0.UINT16[H]
    6121 #define RSCAN0RFID0HL RSCAN0.RFID0.UINT8[HL]
    6122 #define RSCAN0RFID0HH RSCAN0.RFID0.UINT8[HH]
    6123 #define RSCAN0RFPTR0 RSCAN0.RFPTR0.UINT32
    6124 #define RSCAN0RFPTR0L RSCAN0.RFPTR0.UINT16[L]
    6125 #define RSCAN0RFPTR0LL RSCAN0.RFPTR0.UINT8[LL]
    6126 #define RSCAN0RFPTR0LH RSCAN0.RFPTR0.UINT8[LH]
    6127 #define RSCAN0RFPTR0H RSCAN0.RFPTR0.UINT16[H]
    6128 #define RSCAN0RFPTR0HL RSCAN0.RFPTR0.UINT8[HL]
    6129 #define RSCAN0RFPTR0HH RSCAN0.RFPTR0.UINT8[HH]
    6130 #define RSCAN0RFDF00 RSCAN0.RFDF00.UINT32
    6131 #define RSCAN0RFDF00L RSCAN0.RFDF00.UINT16[L]
    6132 #define RSCAN0RFDF00LL RSCAN0.RFDF00.UINT8[LL]
    6133 #define RSCAN0RFDF00LH RSCAN0.RFDF00.UINT8[LH]
    6134 #define RSCAN0RFDF00H RSCAN0.RFDF00.UINT16[H]
    6135 #define RSCAN0RFDF00HL RSCAN0.RFDF00.UINT8[HL]
    6136 #define RSCAN0RFDF00HH RSCAN0.RFDF00.UINT8[HH]
    6137 #define RSCAN0RFDF10 RSCAN0.RFDF10.UINT32
    6138 #define RSCAN0RFDF10L RSCAN0.RFDF10.UINT16[L]
    6139 #define RSCAN0RFDF10LL RSCAN0.RFDF10.UINT8[LL]
    6140 #define RSCAN0RFDF10LH RSCAN0.RFDF10.UINT8[LH]
    6141 #define RSCAN0RFDF10H RSCAN0.RFDF10.UINT16[H]
    6142 #define RSCAN0RFDF10HL RSCAN0.RFDF10.UINT8[HL]
    6143 #define RSCAN0RFDF10HH RSCAN0.RFDF10.UINT8[HH]
    6144 #define RSCAN0RFID1 RSCAN0.RFID1.UINT32
    6145 #define RSCAN0RFID1L RSCAN0.RFID1.UINT16[L]
    6146 #define RSCAN0RFID1LL RSCAN0.RFID1.UINT8[LL]
    6147 #define RSCAN0RFID1LH RSCAN0.RFID1.UINT8[LH]
    6148 #define RSCAN0RFID1H RSCAN0.RFID1.UINT16[H]
    6149 #define RSCAN0RFID1HL RSCAN0.RFID1.UINT8[HL]
    6150 #define RSCAN0RFID1HH RSCAN0.RFID1.UINT8[HH]
    6151 #define RSCAN0RFPTR1 RSCAN0.RFPTR1.UINT32
    6152 #define RSCAN0RFPTR1L RSCAN0.RFPTR1.UINT16[L]
    6153 #define RSCAN0RFPTR1LL RSCAN0.RFPTR1.UINT8[LL]
    6154 #define RSCAN0RFPTR1LH RSCAN0.RFPTR1.UINT8[LH]
    6155 #define RSCAN0RFPTR1H RSCAN0.RFPTR1.UINT16[H]
    6156 #define RSCAN0RFPTR1HL RSCAN0.RFPTR1.UINT8[HL]
    6157 #define RSCAN0RFPTR1HH RSCAN0.RFPTR1.UINT8[HH]
    6158 #define RSCAN0RFDF01 RSCAN0.RFDF01.UINT32
    6159 #define RSCAN0RFDF01L RSCAN0.RFDF01.UINT16[L]
    6160 #define RSCAN0RFDF01LL RSCAN0.RFDF01.UINT8[LL]
    6161 #define RSCAN0RFDF01LH RSCAN0.RFDF01.UINT8[LH]
    6162 #define RSCAN0RFDF01H RSCAN0.RFDF01.UINT16[H]
    6163 #define RSCAN0RFDF01HL RSCAN0.RFDF01.UINT8[HL]
    6164 #define RSCAN0RFDF01HH RSCAN0.RFDF01.UINT8[HH]
    6165 #define RSCAN0RFDF11 RSCAN0.RFDF11.UINT32
    6166 #define RSCAN0RFDF11L RSCAN0.RFDF11.UINT16[L]
    6167 #define RSCAN0RFDF11LL RSCAN0.RFDF11.UINT8[LL]
    6168 #define RSCAN0RFDF11LH RSCAN0.RFDF11.UINT8[LH]
    6169 #define RSCAN0RFDF11H RSCAN0.RFDF11.UINT16[H]
    6170 #define RSCAN0RFDF11HL RSCAN0.RFDF11.UINT8[HL]
    6171 #define RSCAN0RFDF11HH RSCAN0.RFDF11.UINT8[HH]
    6172 #define RSCAN0RFID2 RSCAN0.RFID2.UINT32
    6173 #define RSCAN0RFID2L RSCAN0.RFID2.UINT16[L]
    6174 #define RSCAN0RFID2LL RSCAN0.RFID2.UINT8[LL]
    6175 #define RSCAN0RFID2LH RSCAN0.RFID2.UINT8[LH]
    6176 #define RSCAN0RFID2H RSCAN0.RFID2.UINT16[H]
    6177 #define RSCAN0RFID2HL RSCAN0.RFID2.UINT8[HL]
    6178 #define RSCAN0RFID2HH RSCAN0.RFID2.UINT8[HH]
    6179 #define RSCAN0RFPTR2 RSCAN0.RFPTR2.UINT32
    6180 #define RSCAN0RFPTR2L RSCAN0.RFPTR2.UINT16[L]
    6181 #define RSCAN0RFPTR2LL RSCAN0.RFPTR2.UINT8[LL]
    6182 #define RSCAN0RFPTR2LH RSCAN0.RFPTR2.UINT8[LH]
    6183 #define RSCAN0RFPTR2H RSCAN0.RFPTR2.UINT16[H]
    6184 #define RSCAN0RFPTR2HL RSCAN0.RFPTR2.UINT8[HL]
    6185 #define RSCAN0RFPTR2HH RSCAN0.RFPTR2.UINT8[HH]
    6186 #define RSCAN0RFDF02 RSCAN0.RFDF02.UINT32
    6187 #define RSCAN0RFDF02L RSCAN0.RFDF02.UINT16[L]
    6188 #define RSCAN0RFDF02LL RSCAN0.RFDF02.UINT8[LL]
    6189 #define RSCAN0RFDF02LH RSCAN0.RFDF02.UINT8[LH]
    6190 #define RSCAN0RFDF02H RSCAN0.RFDF02.UINT16[H]
    6191 #define RSCAN0RFDF02HL RSCAN0.RFDF02.UINT8[HL]
    6192 #define RSCAN0RFDF02HH RSCAN0.RFDF02.UINT8[HH]
    6193 #define RSCAN0RFDF12 RSCAN0.RFDF12.UINT32
    6194 #define RSCAN0RFDF12L RSCAN0.RFDF12.UINT16[L]
    6195 #define RSCAN0RFDF12LL RSCAN0.RFDF12.UINT8[LL]
    6196 #define RSCAN0RFDF12LH RSCAN0.RFDF12.UINT8[LH]
    6197 #define RSCAN0RFDF12H RSCAN0.RFDF12.UINT16[H]
    6198 #define RSCAN0RFDF12HL RSCAN0.RFDF12.UINT8[HL]
    6199 #define RSCAN0RFDF12HH RSCAN0.RFDF12.UINT8[HH]
    6200 #define RSCAN0RFID3 RSCAN0.RFID3.UINT32
    6201 #define RSCAN0RFID3L RSCAN0.RFID3.UINT16[L]
    6202 #define RSCAN0RFID3LL RSCAN0.RFID3.UINT8[LL]
    6203 #define RSCAN0RFID3LH RSCAN0.RFID3.UINT8[LH]
    6204 #define RSCAN0RFID3H RSCAN0.RFID3.UINT16[H]
    6205 #define RSCAN0RFID3HL RSCAN0.RFID3.UINT8[HL]
    6206 #define RSCAN0RFID3HH RSCAN0.RFID3.UINT8[HH]
    6207 #define RSCAN0RFPTR3 RSCAN0.RFPTR3.UINT32
    6208 #define RSCAN0RFPTR3L RSCAN0.RFPTR3.UINT16[L]
    6209 #define RSCAN0RFPTR3LL RSCAN0.RFPTR3.UINT8[LL]
    6210 #define RSCAN0RFPTR3LH RSCAN0.RFPTR3.UINT8[LH]
    6211 #define RSCAN0RFPTR3H RSCAN0.RFPTR3.UINT16[H]
    6212 #define RSCAN0RFPTR3HL RSCAN0.RFPTR3.UINT8[HL]
    6213 #define RSCAN0RFPTR3HH RSCAN0.RFPTR3.UINT8[HH]
    6214 #define RSCAN0RFDF03 RSCAN0.RFDF03.UINT32
    6215 #define RSCAN0RFDF03L RSCAN0.RFDF03.UINT16[L]
    6216 #define RSCAN0RFDF03LL RSCAN0.RFDF03.UINT8[LL]
    6217 #define RSCAN0RFDF03LH RSCAN0.RFDF03.UINT8[LH]
    6218 #define RSCAN0RFDF03H RSCAN0.RFDF03.UINT16[H]
    6219 #define RSCAN0RFDF03HL RSCAN0.RFDF03.UINT8[HL]
    6220 #define RSCAN0RFDF03HH RSCAN0.RFDF03.UINT8[HH]
    6221 #define RSCAN0RFDF13 RSCAN0.RFDF13.UINT32
    6222 #define RSCAN0RFDF13L RSCAN0.RFDF13.UINT16[L]
    6223 #define RSCAN0RFDF13LL RSCAN0.RFDF13.UINT8[LL]
    6224 #define RSCAN0RFDF13LH RSCAN0.RFDF13.UINT8[LH]
    6225 #define RSCAN0RFDF13H RSCAN0.RFDF13.UINT16[H]
    6226 #define RSCAN0RFDF13HL RSCAN0.RFDF13.UINT8[HL]
    6227 #define RSCAN0RFDF13HH RSCAN0.RFDF13.UINT8[HH]
    6228 #define RSCAN0RFID4 RSCAN0.RFID4.UINT32
    6229 #define RSCAN0RFID4L RSCAN0.RFID4.UINT16[L]
    6230 #define RSCAN0RFID4LL RSCAN0.RFID4.UINT8[LL]
    6231 #define RSCAN0RFID4LH RSCAN0.RFID4.UINT8[LH]
    6232 #define RSCAN0RFID4H RSCAN0.RFID4.UINT16[H]
    6233 #define RSCAN0RFID4HL RSCAN0.RFID4.UINT8[HL]
    6234 #define RSCAN0RFID4HH RSCAN0.RFID4.UINT8[HH]
    6235 #define RSCAN0RFPTR4 RSCAN0.RFPTR4.UINT32
    6236 #define RSCAN0RFPTR4L RSCAN0.RFPTR4.UINT16[L]
    6237 #define RSCAN0RFPTR4LL RSCAN0.RFPTR4.UINT8[LL]
    6238 #define RSCAN0RFPTR4LH RSCAN0.RFPTR4.UINT8[LH]
    6239 #define RSCAN0RFPTR4H RSCAN0.RFPTR4.UINT16[H]
    6240 #define RSCAN0RFPTR4HL RSCAN0.RFPTR4.UINT8[HL]
    6241 #define RSCAN0RFPTR4HH RSCAN0.RFPTR4.UINT8[HH]
    6242 #define RSCAN0RFDF04 RSCAN0.RFDF04.UINT32
    6243 #define RSCAN0RFDF04L RSCAN0.RFDF04.UINT16[L]
    6244 #define RSCAN0RFDF04LL RSCAN0.RFDF04.UINT8[LL]
    6245 #define RSCAN0RFDF04LH RSCAN0.RFDF04.UINT8[LH]
    6246 #define RSCAN0RFDF04H RSCAN0.RFDF04.UINT16[H]
    6247 #define RSCAN0RFDF04HL RSCAN0.RFDF04.UINT8[HL]
    6248 #define RSCAN0RFDF04HH RSCAN0.RFDF04.UINT8[HH]
    6249 #define RSCAN0RFDF14 RSCAN0.RFDF14.UINT32
    6250 #define RSCAN0RFDF14L RSCAN0.RFDF14.UINT16[L]
    6251 #define RSCAN0RFDF14LL RSCAN0.RFDF14.UINT8[LL]
    6252 #define RSCAN0RFDF14LH RSCAN0.RFDF14.UINT8[LH]
    6253 #define RSCAN0RFDF14H RSCAN0.RFDF14.UINT16[H]
    6254 #define RSCAN0RFDF14HL RSCAN0.RFDF14.UINT8[HL]
    6255 #define RSCAN0RFDF14HH RSCAN0.RFDF14.UINT8[HH]
    6256 #define RSCAN0RFID5 RSCAN0.RFID5.UINT32
    6257 #define RSCAN0RFID5L RSCAN0.RFID5.UINT16[L]
    6258 #define RSCAN0RFID5LL RSCAN0.RFID5.UINT8[LL]
    6259 #define RSCAN0RFID5LH RSCAN0.RFID5.UINT8[LH]
    6260 #define RSCAN0RFID5H RSCAN0.RFID5.UINT16[H]
    6261 #define RSCAN0RFID5HL RSCAN0.RFID5.UINT8[HL]
    6262 #define RSCAN0RFID5HH RSCAN0.RFID5.UINT8[HH]
    6263 #define RSCAN0RFPTR5 RSCAN0.RFPTR5.UINT32
    6264 #define RSCAN0RFPTR5L RSCAN0.RFPTR5.UINT16[L]
    6265 #define RSCAN0RFPTR5LL RSCAN0.RFPTR5.UINT8[LL]
    6266 #define RSCAN0RFPTR5LH RSCAN0.RFPTR5.UINT8[LH]
    6267 #define RSCAN0RFPTR5H RSCAN0.RFPTR5.UINT16[H]
    6268 #define RSCAN0RFPTR5HL RSCAN0.RFPTR5.UINT8[HL]
    6269 #define RSCAN0RFPTR5HH RSCAN0.RFPTR5.UINT8[HH]
    6270 #define RSCAN0RFDF05 RSCAN0.RFDF05.UINT32
    6271 #define RSCAN0RFDF05L RSCAN0.RFDF05.UINT16[L]
    6272 #define RSCAN0RFDF05LL RSCAN0.RFDF05.UINT8[LL]
    6273 #define RSCAN0RFDF05LH RSCAN0.RFDF05.UINT8[LH]
    6274 #define RSCAN0RFDF05H RSCAN0.RFDF05.UINT16[H]
    6275 #define RSCAN0RFDF05HL RSCAN0.RFDF05.UINT8[HL]
    6276 #define RSCAN0RFDF05HH RSCAN0.RFDF05.UINT8[HH]
    6277 #define RSCAN0RFDF15 RSCAN0.RFDF15.UINT32
    6278 #define RSCAN0RFDF15L RSCAN0.RFDF15.UINT16[L]
    6279 #define RSCAN0RFDF15LL RSCAN0.RFDF15.UINT8[LL]
    6280 #define RSCAN0RFDF15LH RSCAN0.RFDF15.UINT8[LH]
    6281 #define RSCAN0RFDF15H RSCAN0.RFDF15.UINT16[H]
    6282 #define RSCAN0RFDF15HL RSCAN0.RFDF15.UINT8[HL]
    6283 #define RSCAN0RFDF15HH RSCAN0.RFDF15.UINT8[HH]
    6284 #define RSCAN0RFID6 RSCAN0.RFID6.UINT32
    6285 #define RSCAN0RFID6L RSCAN0.RFID6.UINT16[L]
    6286 #define RSCAN0RFID6LL RSCAN0.RFID6.UINT8[LL]
    6287 #define RSCAN0RFID6LH RSCAN0.RFID6.UINT8[LH]
    6288 #define RSCAN0RFID6H RSCAN0.RFID6.UINT16[H]
    6289 #define RSCAN0RFID6HL RSCAN0.RFID6.UINT8[HL]
    6290 #define RSCAN0RFID6HH RSCAN0.RFID6.UINT8[HH]
    6291 #define RSCAN0RFPTR6 RSCAN0.RFPTR6.UINT32
    6292 #define RSCAN0RFPTR6L RSCAN0.RFPTR6.UINT16[L]
    6293 #define RSCAN0RFPTR6LL RSCAN0.RFPTR6.UINT8[LL]
    6294 #define RSCAN0RFPTR6LH RSCAN0.RFPTR6.UINT8[LH]
    6295 #define RSCAN0RFPTR6H RSCAN0.RFPTR6.UINT16[H]
    6296 #define RSCAN0RFPTR6HL RSCAN0.RFPTR6.UINT8[HL]
    6297 #define RSCAN0RFPTR6HH RSCAN0.RFPTR6.UINT8[HH]
    6298 #define RSCAN0RFDF06 RSCAN0.RFDF06.UINT32
    6299 #define RSCAN0RFDF06L RSCAN0.RFDF06.UINT16[L]
    6300 #define RSCAN0RFDF06LL RSCAN0.RFDF06.UINT8[LL]
    6301 #define RSCAN0RFDF06LH RSCAN0.RFDF06.UINT8[LH]
    6302 #define RSCAN0RFDF06H RSCAN0.RFDF06.UINT16[H]
    6303 #define RSCAN0RFDF06HL RSCAN0.RFDF06.UINT8[HL]
    6304 #define RSCAN0RFDF06HH RSCAN0.RFDF06.UINT8[HH]
    6305 #define RSCAN0RFDF16 RSCAN0.RFDF16.UINT32
    6306 #define RSCAN0RFDF16L RSCAN0.RFDF16.UINT16[L]
    6307 #define RSCAN0RFDF16LL RSCAN0.RFDF16.UINT8[LL]
    6308 #define RSCAN0RFDF16LH RSCAN0.RFDF16.UINT8[LH]
    6309 #define RSCAN0RFDF16H RSCAN0.RFDF16.UINT16[H]
    6310 #define RSCAN0RFDF16HL RSCAN0.RFDF16.UINT8[HL]
    6311 #define RSCAN0RFDF16HH RSCAN0.RFDF16.UINT8[HH]
    6312 #define RSCAN0RFID7 RSCAN0.RFID7.UINT32
    6313 #define RSCAN0RFID7L RSCAN0.RFID7.UINT16[L]
    6314 #define RSCAN0RFID7LL RSCAN0.RFID7.UINT8[LL]
    6315 #define RSCAN0RFID7LH RSCAN0.RFID7.UINT8[LH]
    6316 #define RSCAN0RFID7H RSCAN0.RFID7.UINT16[H]
    6317 #define RSCAN0RFID7HL RSCAN0.RFID7.UINT8[HL]
    6318 #define RSCAN0RFID7HH RSCAN0.RFID7.UINT8[HH]
    6319 #define RSCAN0RFPTR7 RSCAN0.RFPTR7.UINT32
    6320 #define RSCAN0RFPTR7L RSCAN0.RFPTR7.UINT16[L]
    6321 #define RSCAN0RFPTR7LL RSCAN0.RFPTR7.UINT8[LL]
    6322 #define RSCAN0RFPTR7LH RSCAN0.RFPTR7.UINT8[LH]
    6323 #define RSCAN0RFPTR7H RSCAN0.RFPTR7.UINT16[H]
    6324 #define RSCAN0RFPTR7HL RSCAN0.RFPTR7.UINT8[HL]
    6325 #define RSCAN0RFPTR7HH RSCAN0.RFPTR7.UINT8[HH]
    6326 #define RSCAN0RFDF07 RSCAN0.RFDF07.UINT32
    6327 #define RSCAN0RFDF07L RSCAN0.RFDF07.UINT16[L]
    6328 #define RSCAN0RFDF07LL RSCAN0.RFDF07.UINT8[LL]
    6329 #define RSCAN0RFDF07LH RSCAN0.RFDF07.UINT8[LH]
    6330 #define RSCAN0RFDF07H RSCAN0.RFDF07.UINT16[H]
    6331 #define RSCAN0RFDF07HL RSCAN0.RFDF07.UINT8[HL]
    6332 #define RSCAN0RFDF07HH RSCAN0.RFDF07.UINT8[HH]
    6333 #define RSCAN0RFDF17 RSCAN0.RFDF17.UINT32
    6334 #define RSCAN0RFDF17L RSCAN0.RFDF17.UINT16[L]
    6335 #define RSCAN0RFDF17LL RSCAN0.RFDF17.UINT8[LL]
    6336 #define RSCAN0RFDF17LH RSCAN0.RFDF17.UINT8[LH]
    6337 #define RSCAN0RFDF17H RSCAN0.RFDF17.UINT16[H]
    6338 #define RSCAN0RFDF17HL RSCAN0.RFDF17.UINT8[HL]
    6339 #define RSCAN0RFDF17HH RSCAN0.RFDF17.UINT8[HH]
    6340 #define RSCAN0CFID0 RSCAN0.CFID0.UINT32
    6341 #define RSCAN0CFID0L RSCAN0.CFID0.UINT16[L]
    6342 #define RSCAN0CFID0LL RSCAN0.CFID0.UINT8[LL]
    6343 #define RSCAN0CFID0LH RSCAN0.CFID0.UINT8[LH]
    6344 #define RSCAN0CFID0H RSCAN0.CFID0.UINT16[H]
    6345 #define RSCAN0CFID0HL RSCAN0.CFID0.UINT8[HL]
    6346 #define RSCAN0CFID0HH RSCAN0.CFID0.UINT8[HH]
    6347 #define RSCAN0CFPTR0 RSCAN0.CFPTR0.UINT32
    6348 #define RSCAN0CFPTR0L RSCAN0.CFPTR0.UINT16[L]
    6349 #define RSCAN0CFPTR0LL RSCAN0.CFPTR0.UINT8[LL]
    6350 #define RSCAN0CFPTR0LH RSCAN0.CFPTR0.UINT8[LH]
    6351 #define RSCAN0CFPTR0H RSCAN0.CFPTR0.UINT16[H]
    6352 #define RSCAN0CFPTR0HL RSCAN0.CFPTR0.UINT8[HL]
    6353 #define RSCAN0CFPTR0HH RSCAN0.CFPTR0.UINT8[HH]
    6354 #define RSCAN0CFDF00 RSCAN0.CFDF00.UINT32
    6355 #define RSCAN0CFDF00L RSCAN0.CFDF00.UINT16[L]
    6356 #define RSCAN0CFDF00LL RSCAN0.CFDF00.UINT8[LL]
    6357 #define RSCAN0CFDF00LH RSCAN0.CFDF00.UINT8[LH]
    6358 #define RSCAN0CFDF00H RSCAN0.CFDF00.UINT16[H]
    6359 #define RSCAN0CFDF00HL RSCAN0.CFDF00.UINT8[HL]
    6360 #define RSCAN0CFDF00HH RSCAN0.CFDF00.UINT8[HH]
    6361 #define RSCAN0CFDF10 RSCAN0.CFDF10.UINT32
    6362 #define RSCAN0CFDF10L RSCAN0.CFDF10.UINT16[L]
    6363 #define RSCAN0CFDF10LL RSCAN0.CFDF10.UINT8[LL]
    6364 #define RSCAN0CFDF10LH RSCAN0.CFDF10.UINT8[LH]
    6365 #define RSCAN0CFDF10H RSCAN0.CFDF10.UINT16[H]
    6366 #define RSCAN0CFDF10HL RSCAN0.CFDF10.UINT8[HL]
    6367 #define RSCAN0CFDF10HH RSCAN0.CFDF10.UINT8[HH]
    6368 #define RSCAN0CFID1 RSCAN0.CFID1.UINT32
    6369 #define RSCAN0CFID1L RSCAN0.CFID1.UINT16[L]
    6370 #define RSCAN0CFID1LL RSCAN0.CFID1.UINT8[LL]
    6371 #define RSCAN0CFID1LH RSCAN0.CFID1.UINT8[LH]
    6372 #define RSCAN0CFID1H RSCAN0.CFID1.UINT16[H]
    6373 #define RSCAN0CFID1HL RSCAN0.CFID1.UINT8[HL]
    6374 #define RSCAN0CFID1HH RSCAN0.CFID1.UINT8[HH]
    6375 #define RSCAN0CFPTR1 RSCAN0.CFPTR1.UINT32
    6376 #define RSCAN0CFPTR1L RSCAN0.CFPTR1.UINT16[L]
    6377 #define RSCAN0CFPTR1LL RSCAN0.CFPTR1.UINT8[LL]
    6378 #define RSCAN0CFPTR1LH RSCAN0.CFPTR1.UINT8[LH]
    6379 #define RSCAN0CFPTR1H RSCAN0.CFPTR1.UINT16[H]
    6380 #define RSCAN0CFPTR1HL RSCAN0.CFPTR1.UINT8[HL]
    6381 #define RSCAN0CFPTR1HH RSCAN0.CFPTR1.UINT8[HH]
    6382 #define RSCAN0CFDF01 RSCAN0.CFDF01.UINT32
    6383 #define RSCAN0CFDF01L RSCAN0.CFDF01.UINT16[L]
    6384 #define RSCAN0CFDF01LL RSCAN0.CFDF01.UINT8[LL]
    6385 #define RSCAN0CFDF01LH RSCAN0.CFDF01.UINT8[LH]
    6386 #define RSCAN0CFDF01H RSCAN0.CFDF01.UINT16[H]
    6387 #define RSCAN0CFDF01HL RSCAN0.CFDF01.UINT8[HL]
    6388 #define RSCAN0CFDF01HH RSCAN0.CFDF01.UINT8[HH]
    6389 #define RSCAN0CFDF11 RSCAN0.CFDF11.UINT32
    6390 #define RSCAN0CFDF11L RSCAN0.CFDF11.UINT16[L]
    6391 #define RSCAN0CFDF11LL RSCAN0.CFDF11.UINT8[LL]
    6392 #define RSCAN0CFDF11LH RSCAN0.CFDF11.UINT8[LH]
    6393 #define RSCAN0CFDF11H RSCAN0.CFDF11.UINT16[H]
    6394 #define RSCAN0CFDF11HL RSCAN0.CFDF11.UINT8[HL]
    6395 #define RSCAN0CFDF11HH RSCAN0.CFDF11.UINT8[HH]
    6396 #define RSCAN0CFID2 RSCAN0.CFID2.UINT32
    6397 #define RSCAN0CFID2L RSCAN0.CFID2.UINT16[L]
    6398 #define RSCAN0CFID2LL RSCAN0.CFID2.UINT8[LL]
    6399 #define RSCAN0CFID2LH RSCAN0.CFID2.UINT8[LH]
    6400 #define RSCAN0CFID2H RSCAN0.CFID2.UINT16[H]
    6401 #define RSCAN0CFID2HL RSCAN0.CFID2.UINT8[HL]
    6402 #define RSCAN0CFID2HH RSCAN0.CFID2.UINT8[HH]
    6403 #define RSCAN0CFPTR2 RSCAN0.CFPTR2.UINT32
    6404 #define RSCAN0CFPTR2L RSCAN0.CFPTR2.UINT16[L]
    6405 #define RSCAN0CFPTR2LL RSCAN0.CFPTR2.UINT8[LL]
    6406 #define RSCAN0CFPTR2LH RSCAN0.CFPTR2.UINT8[LH]
    6407 #define RSCAN0CFPTR2H RSCAN0.CFPTR2.UINT16[H]
    6408 #define RSCAN0CFPTR2HL RSCAN0.CFPTR2.UINT8[HL]
    6409 #define RSCAN0CFPTR2HH RSCAN0.CFPTR2.UINT8[HH]
    6410 #define RSCAN0CFDF02 RSCAN0.CFDF02.UINT32
    6411 #define RSCAN0CFDF02L RSCAN0.CFDF02.UINT16[L]
    6412 #define RSCAN0CFDF02LL RSCAN0.CFDF02.UINT8[LL]
    6413 #define RSCAN0CFDF02LH RSCAN0.CFDF02.UINT8[LH]
    6414 #define RSCAN0CFDF02H RSCAN0.CFDF02.UINT16[H]
    6415 #define RSCAN0CFDF02HL RSCAN0.CFDF02.UINT8[HL]
    6416 #define RSCAN0CFDF02HH RSCAN0.CFDF02.UINT8[HH]
    6417 #define RSCAN0CFDF12 RSCAN0.CFDF12.UINT32
    6418 #define RSCAN0CFDF12L RSCAN0.CFDF12.UINT16[L]
    6419 #define RSCAN0CFDF12LL RSCAN0.CFDF12.UINT8[LL]
    6420 #define RSCAN0CFDF12LH RSCAN0.CFDF12.UINT8[LH]
    6421 #define RSCAN0CFDF12H RSCAN0.CFDF12.UINT16[H]
    6422 #define RSCAN0CFDF12HL RSCAN0.CFDF12.UINT8[HL]
    6423 #define RSCAN0CFDF12HH RSCAN0.CFDF12.UINT8[HH]
    6424 #define RSCAN0CFID3 RSCAN0.CFID3.UINT32
    6425 #define RSCAN0CFID3L RSCAN0.CFID3.UINT16[L]
    6426 #define RSCAN0CFID3LL RSCAN0.CFID3.UINT8[LL]
    6427 #define RSCAN0CFID3LH RSCAN0.CFID3.UINT8[LH]
    6428 #define RSCAN0CFID3H RSCAN0.CFID3.UINT16[H]
    6429 #define RSCAN0CFID3HL RSCAN0.CFID3.UINT8[HL]
    6430 #define RSCAN0CFID3HH RSCAN0.CFID3.UINT8[HH]
    6431 #define RSCAN0CFPTR3 RSCAN0.CFPTR3.UINT32
    6432 #define RSCAN0CFPTR3L RSCAN0.CFPTR3.UINT16[L]
    6433 #define RSCAN0CFPTR3LL RSCAN0.CFPTR3.UINT8[LL]
    6434 #define RSCAN0CFPTR3LH RSCAN0.CFPTR3.UINT8[LH]
    6435 #define RSCAN0CFPTR3H RSCAN0.CFPTR3.UINT16[H]
    6436 #define RSCAN0CFPTR3HL RSCAN0.CFPTR3.UINT8[HL]
    6437 #define RSCAN0CFPTR3HH RSCAN0.CFPTR3.UINT8[HH]
    6438 #define RSCAN0CFDF03 RSCAN0.CFDF03.UINT32
    6439 #define RSCAN0CFDF03L RSCAN0.CFDF03.UINT16[L]
    6440 #define RSCAN0CFDF03LL RSCAN0.CFDF03.UINT8[LL]
    6441 #define RSCAN0CFDF03LH RSCAN0.CFDF03.UINT8[LH]
    6442 #define RSCAN0CFDF03H RSCAN0.CFDF03.UINT16[H]
    6443 #define RSCAN0CFDF03HL RSCAN0.CFDF03.UINT8[HL]
    6444 #define RSCAN0CFDF03HH RSCAN0.CFDF03.UINT8[HH]
    6445 #define RSCAN0CFDF13 RSCAN0.CFDF13.UINT32
    6446 #define RSCAN0CFDF13L RSCAN0.CFDF13.UINT16[L]
    6447 #define RSCAN0CFDF13LL RSCAN0.CFDF13.UINT8[LL]
    6448 #define RSCAN0CFDF13LH RSCAN0.CFDF13.UINT8[LH]
    6449 #define RSCAN0CFDF13H RSCAN0.CFDF13.UINT16[H]
    6450 #define RSCAN0CFDF13HL RSCAN0.CFDF13.UINT8[HL]
    6451 #define RSCAN0CFDF13HH RSCAN0.CFDF13.UINT8[HH]
    6452 #define RSCAN0CFID4 RSCAN0.CFID4.UINT32
    6453 #define RSCAN0CFID4L RSCAN0.CFID4.UINT16[L]
    6454 #define RSCAN0CFID4LL RSCAN0.CFID4.UINT8[LL]
    6455 #define RSCAN0CFID4LH RSCAN0.CFID4.UINT8[LH]
    6456 #define RSCAN0CFID4H RSCAN0.CFID4.UINT16[H]
    6457 #define RSCAN0CFID4HL RSCAN0.CFID4.UINT8[HL]
    6458 #define RSCAN0CFID4HH RSCAN0.CFID4.UINT8[HH]
    6459 #define RSCAN0CFPTR4 RSCAN0.CFPTR4.UINT32
    6460 #define RSCAN0CFPTR4L RSCAN0.CFPTR4.UINT16[L]
    6461 #define RSCAN0CFPTR4LL RSCAN0.CFPTR4.UINT8[LL]
    6462 #define RSCAN0CFPTR4LH RSCAN0.CFPTR4.UINT8[LH]
    6463 #define RSCAN0CFPTR4H RSCAN0.CFPTR4.UINT16[H]
    6464 #define RSCAN0CFPTR4HL RSCAN0.CFPTR4.UINT8[HL]
    6465 #define RSCAN0CFPTR4HH RSCAN0.CFPTR4.UINT8[HH]
    6466 #define RSCAN0CFDF04 RSCAN0.CFDF04.UINT32
    6467 #define RSCAN0CFDF04L RSCAN0.CFDF04.UINT16[L]
    6468 #define RSCAN0CFDF04LL RSCAN0.CFDF04.UINT8[LL]
    6469 #define RSCAN0CFDF04LH RSCAN0.CFDF04.UINT8[LH]
    6470 #define RSCAN0CFDF04H RSCAN0.CFDF04.UINT16[H]
    6471 #define RSCAN0CFDF04HL RSCAN0.CFDF04.UINT8[HL]
    6472 #define RSCAN0CFDF04HH RSCAN0.CFDF04.UINT8[HH]
    6473 #define RSCAN0CFDF14 RSCAN0.CFDF14.UINT32
    6474 #define RSCAN0CFDF14L RSCAN0.CFDF14.UINT16[L]
    6475 #define RSCAN0CFDF14LL RSCAN0.CFDF14.UINT8[LL]
    6476 #define RSCAN0CFDF14LH RSCAN0.CFDF14.UINT8[LH]
    6477 #define RSCAN0CFDF14H RSCAN0.CFDF14.UINT16[H]
    6478 #define RSCAN0CFDF14HL RSCAN0.CFDF14.UINT8[HL]
    6479 #define RSCAN0CFDF14HH RSCAN0.CFDF14.UINT8[HH]
    6480 #define RSCAN0CFID5 RSCAN0.CFID5.UINT32
    6481 #define RSCAN0CFID5L RSCAN0.CFID5.UINT16[L]
    6482 #define RSCAN0CFID5LL RSCAN0.CFID5.UINT8[LL]
    6483 #define RSCAN0CFID5LH RSCAN0.CFID5.UINT8[LH]
    6484 #define RSCAN0CFID5H RSCAN0.CFID5.UINT16[H]
    6485 #define RSCAN0CFID5HL RSCAN0.CFID5.UINT8[HL]
    6486 #define RSCAN0CFID5HH RSCAN0.CFID5.UINT8[HH]
    6487 #define RSCAN0CFPTR5 RSCAN0.CFPTR5.UINT32
    6488 #define RSCAN0CFPTR5L RSCAN0.CFPTR5.UINT16[L]
    6489 #define RSCAN0CFPTR5LL RSCAN0.CFPTR5.UINT8[LL]
    6490 #define RSCAN0CFPTR5LH RSCAN0.CFPTR5.UINT8[LH]
    6491 #define RSCAN0CFPTR5H RSCAN0.CFPTR5.UINT16[H]
    6492 #define RSCAN0CFPTR5HL RSCAN0.CFPTR5.UINT8[HL]
    6493 #define RSCAN0CFPTR5HH RSCAN0.CFPTR5.UINT8[HH]
    6494 #define RSCAN0CFDF05 RSCAN0.CFDF05.UINT32
    6495 #define RSCAN0CFDF05L RSCAN0.CFDF05.UINT16[L]
    6496 #define RSCAN0CFDF05LL RSCAN0.CFDF05.UINT8[LL]
    6497 #define RSCAN0CFDF05LH RSCAN0.CFDF05.UINT8[LH]
    6498 #define RSCAN0CFDF05H RSCAN0.CFDF05.UINT16[H]
    6499 #define RSCAN0CFDF05HL RSCAN0.CFDF05.UINT8[HL]
    6500 #define RSCAN0CFDF05HH RSCAN0.CFDF05.UINT8[HH]
    6501 #define RSCAN0CFDF15 RSCAN0.CFDF15.UINT32
    6502 #define RSCAN0CFDF15L RSCAN0.CFDF15.UINT16[L]
    6503 #define RSCAN0CFDF15LL RSCAN0.CFDF15.UINT8[LL]
    6504 #define RSCAN0CFDF15LH RSCAN0.CFDF15.UINT8[LH]
    6505 #define RSCAN0CFDF15H RSCAN0.CFDF15.UINT16[H]
    6506 #define RSCAN0CFDF15HL RSCAN0.CFDF15.UINT8[HL]
    6507 #define RSCAN0CFDF15HH RSCAN0.CFDF15.UINT8[HH]
    6508 #define RSCAN0CFID6 RSCAN0.CFID6.UINT32
    6509 #define RSCAN0CFID6L RSCAN0.CFID6.UINT16[L]
    6510 #define RSCAN0CFID6LL RSCAN0.CFID6.UINT8[LL]
    6511 #define RSCAN0CFID6LH RSCAN0.CFID6.UINT8[LH]
    6512 #define RSCAN0CFID6H RSCAN0.CFID6.UINT16[H]
    6513 #define RSCAN0CFID6HL RSCAN0.CFID6.UINT8[HL]
    6514 #define RSCAN0CFID6HH RSCAN0.CFID6.UINT8[HH]
    6515 #define RSCAN0CFPTR6 RSCAN0.CFPTR6.UINT32
    6516 #define RSCAN0CFPTR6L RSCAN0.CFPTR6.UINT16[L]
    6517 #define RSCAN0CFPTR6LL RSCAN0.CFPTR6.UINT8[LL]
    6518 #define RSCAN0CFPTR6LH RSCAN0.CFPTR6.UINT8[LH]
    6519 #define RSCAN0CFPTR6H RSCAN0.CFPTR6.UINT16[H]
    6520 #define RSCAN0CFPTR6HL RSCAN0.CFPTR6.UINT8[HL]
    6521 #define RSCAN0CFPTR6HH RSCAN0.CFPTR6.UINT8[HH]
    6522 #define RSCAN0CFDF06 RSCAN0.CFDF06.UINT32
    6523 #define RSCAN0CFDF06L RSCAN0.CFDF06.UINT16[L]
    6524 #define RSCAN0CFDF06LL RSCAN0.CFDF06.UINT8[LL]
    6525 #define RSCAN0CFDF06LH RSCAN0.CFDF06.UINT8[LH]
    6526 #define RSCAN0CFDF06H RSCAN0.CFDF06.UINT16[H]
    6527 #define RSCAN0CFDF06HL RSCAN0.CFDF06.UINT8[HL]
    6528 #define RSCAN0CFDF06HH RSCAN0.CFDF06.UINT8[HH]
    6529 #define RSCAN0CFDF16 RSCAN0.CFDF16.UINT32
    6530 #define RSCAN0CFDF16L RSCAN0.CFDF16.UINT16[L]
    6531 #define RSCAN0CFDF16LL RSCAN0.CFDF16.UINT8[LL]
    6532 #define RSCAN0CFDF16LH RSCAN0.CFDF16.UINT8[LH]
    6533 #define RSCAN0CFDF16H RSCAN0.CFDF16.UINT16[H]
    6534 #define RSCAN0CFDF16HL RSCAN0.CFDF16.UINT8[HL]
    6535 #define RSCAN0CFDF16HH RSCAN0.CFDF16.UINT8[HH]
    6536 #define RSCAN0CFID7 RSCAN0.CFID7.UINT32
    6537 #define RSCAN0CFID7L RSCAN0.CFID7.UINT16[L]
    6538 #define RSCAN0CFID7LL RSCAN0.CFID7.UINT8[LL]
    6539 #define RSCAN0CFID7LH RSCAN0.CFID7.UINT8[LH]
    6540 #define RSCAN0CFID7H RSCAN0.CFID7.UINT16[H]
    6541 #define RSCAN0CFID7HL RSCAN0.CFID7.UINT8[HL]
    6542 #define RSCAN0CFID7HH RSCAN0.CFID7.UINT8[HH]
    6543 #define RSCAN0CFPTR7 RSCAN0.CFPTR7.UINT32
    6544 #define RSCAN0CFPTR7L RSCAN0.CFPTR7.UINT16[L]
    6545 #define RSCAN0CFPTR7LL RSCAN0.CFPTR7.UINT8[LL]
    6546 #define RSCAN0CFPTR7LH RSCAN0.CFPTR7.UINT8[LH]
    6547 #define RSCAN0CFPTR7H RSCAN0.CFPTR7.UINT16[H]
    6548 #define RSCAN0CFPTR7HL RSCAN0.CFPTR7.UINT8[HL]
    6549 #define RSCAN0CFPTR7HH RSCAN0.CFPTR7.UINT8[HH]
    6550 #define RSCAN0CFDF07 RSCAN0.CFDF07.UINT32
    6551 #define RSCAN0CFDF07L RSCAN0.CFDF07.UINT16[L]
    6552 #define RSCAN0CFDF07LL RSCAN0.CFDF07.UINT8[LL]
    6553 #define RSCAN0CFDF07LH RSCAN0.CFDF07.UINT8[LH]
    6554 #define RSCAN0CFDF07H RSCAN0.CFDF07.UINT16[H]
    6555 #define RSCAN0CFDF07HL RSCAN0.CFDF07.UINT8[HL]
    6556 #define RSCAN0CFDF07HH RSCAN0.CFDF07.UINT8[HH]
    6557 #define RSCAN0CFDF17 RSCAN0.CFDF17.UINT32
    6558 #define RSCAN0CFDF17L RSCAN0.CFDF17.UINT16[L]
    6559 #define RSCAN0CFDF17LL RSCAN0.CFDF17.UINT8[LL]
    6560 #define RSCAN0CFDF17LH RSCAN0.CFDF17.UINT8[LH]
    6561 #define RSCAN0CFDF17H RSCAN0.CFDF17.UINT16[H]
    6562 #define RSCAN0CFDF17HL RSCAN0.CFDF17.UINT8[HL]
    6563 #define RSCAN0CFDF17HH RSCAN0.CFDF17.UINT8[HH]
    6564 #define RSCAN0CFID8 RSCAN0.CFID8.UINT32
    6565 #define RSCAN0CFID8L RSCAN0.CFID8.UINT16[L]
    6566 #define RSCAN0CFID8LL RSCAN0.CFID8.UINT8[LL]
    6567 #define RSCAN0CFID8LH RSCAN0.CFID8.UINT8[LH]
    6568 #define RSCAN0CFID8H RSCAN0.CFID8.UINT16[H]
    6569 #define RSCAN0CFID8HL RSCAN0.CFID8.UINT8[HL]
    6570 #define RSCAN0CFID8HH RSCAN0.CFID8.UINT8[HH]
    6571 #define RSCAN0CFPTR8 RSCAN0.CFPTR8.UINT32
    6572 #define RSCAN0CFPTR8L RSCAN0.CFPTR8.UINT16[L]
    6573 #define RSCAN0CFPTR8LL RSCAN0.CFPTR8.UINT8[LL]
    6574 #define RSCAN0CFPTR8LH RSCAN0.CFPTR8.UINT8[LH]
    6575 #define RSCAN0CFPTR8H RSCAN0.CFPTR8.UINT16[H]
    6576 #define RSCAN0CFPTR8HL RSCAN0.CFPTR8.UINT8[HL]
    6577 #define RSCAN0CFPTR8HH RSCAN0.CFPTR8.UINT8[HH]
    6578 #define RSCAN0CFDF08 RSCAN0.CFDF08.UINT32
    6579 #define RSCAN0CFDF08L RSCAN0.CFDF08.UINT16[L]
    6580 #define RSCAN0CFDF08LL RSCAN0.CFDF08.UINT8[LL]
    6581 #define RSCAN0CFDF08LH RSCAN0.CFDF08.UINT8[LH]
    6582 #define RSCAN0CFDF08H RSCAN0.CFDF08.UINT16[H]
    6583 #define RSCAN0CFDF08HL RSCAN0.CFDF08.UINT8[HL]
    6584 #define RSCAN0CFDF08HH RSCAN0.CFDF08.UINT8[HH]
    6585 #define RSCAN0CFDF18 RSCAN0.CFDF18.UINT32
    6586 #define RSCAN0CFDF18L RSCAN0.CFDF18.UINT16[L]
    6587 #define RSCAN0CFDF18LL RSCAN0.CFDF18.UINT8[LL]
    6588 #define RSCAN0CFDF18LH RSCAN0.CFDF18.UINT8[LH]
    6589 #define RSCAN0CFDF18H RSCAN0.CFDF18.UINT16[H]
    6590 #define RSCAN0CFDF18HL RSCAN0.CFDF18.UINT8[HL]
    6591 #define RSCAN0CFDF18HH RSCAN0.CFDF18.UINT8[HH]
    6592 #define RSCAN0CFID9 RSCAN0.CFID9.UINT32
    6593 #define RSCAN0CFID9L RSCAN0.CFID9.UINT16[L]
    6594 #define RSCAN0CFID9LL RSCAN0.CFID9.UINT8[LL]
    6595 #define RSCAN0CFID9LH RSCAN0.CFID9.UINT8[LH]
    6596 #define RSCAN0CFID9H RSCAN0.CFID9.UINT16[H]
    6597 #define RSCAN0CFID9HL RSCAN0.CFID9.UINT8[HL]
    6598 #define RSCAN0CFID9HH RSCAN0.CFID9.UINT8[HH]
    6599 #define RSCAN0CFPTR9 RSCAN0.CFPTR9.UINT32
    6600 #define RSCAN0CFPTR9L RSCAN0.CFPTR9.UINT16[L]
    6601 #define RSCAN0CFPTR9LL RSCAN0.CFPTR9.UINT8[LL]
    6602 #define RSCAN0CFPTR9LH RSCAN0.CFPTR9.UINT8[LH]
    6603 #define RSCAN0CFPTR9H RSCAN0.CFPTR9.UINT16[H]
    6604 #define RSCAN0CFPTR9HL RSCAN0.CFPTR9.UINT8[HL]
    6605 #define RSCAN0CFPTR9HH RSCAN0.CFPTR9.UINT8[HH]
    6606 #define RSCAN0CFDF09 RSCAN0.CFDF09.UINT32
    6607 #define RSCAN0CFDF09L RSCAN0.CFDF09.UINT16[L]
    6608 #define RSCAN0CFDF09LL RSCAN0.CFDF09.UINT8[LL]
    6609 #define RSCAN0CFDF09LH RSCAN0.CFDF09.UINT8[LH]
    6610 #define RSCAN0CFDF09H RSCAN0.CFDF09.UINT16[H]
    6611 #define RSCAN0CFDF09HL RSCAN0.CFDF09.UINT8[HL]
    6612 #define RSCAN0CFDF09HH RSCAN0.CFDF09.UINT8[HH]
    6613 #define RSCAN0CFDF19 RSCAN0.CFDF19.UINT32
    6614 #define RSCAN0CFDF19L RSCAN0.CFDF19.UINT16[L]
    6615 #define RSCAN0CFDF19LL RSCAN0.CFDF19.UINT8[LL]
    6616 #define RSCAN0CFDF19LH RSCAN0.CFDF19.UINT8[LH]
    6617 #define RSCAN0CFDF19H RSCAN0.CFDF19.UINT16[H]
    6618 #define RSCAN0CFDF19HL RSCAN0.CFDF19.UINT8[HL]
    6619 #define RSCAN0CFDF19HH RSCAN0.CFDF19.UINT8[HH]
    6620 #define RSCAN0CFID10 RSCAN0.CFID10.UINT32
    6621 #define RSCAN0CFID10L RSCAN0.CFID10.UINT16[L]
    6622 #define RSCAN0CFID10LL RSCAN0.CFID10.UINT8[LL]
    6623 #define RSCAN0CFID10LH RSCAN0.CFID10.UINT8[LH]
    6624 #define RSCAN0CFID10H RSCAN0.CFID10.UINT16[H]
    6625 #define RSCAN0CFID10HL RSCAN0.CFID10.UINT8[HL]
    6626 #define RSCAN0CFID10HH RSCAN0.CFID10.UINT8[HH]
    6627 #define RSCAN0CFPTR10 RSCAN0.CFPTR10.UINT32
    6628 #define RSCAN0CFPTR10L RSCAN0.CFPTR10.UINT16[L]
    6629 #define RSCAN0CFPTR10LL RSCAN0.CFPTR10.UINT8[LL]
    6630 #define RSCAN0CFPTR10LH RSCAN0.CFPTR10.UINT8[LH]
    6631 #define RSCAN0CFPTR10H RSCAN0.CFPTR10.UINT16[H]
    6632 #define RSCAN0CFPTR10HL RSCAN0.CFPTR10.UINT8[HL]
    6633 #define RSCAN0CFPTR10HH RSCAN0.CFPTR10.UINT8[HH]
    6634 #define RSCAN0CFDF010 RSCAN0.CFDF010.UINT32
    6635 #define RSCAN0CFDF010L RSCAN0.CFDF010.UINT16[L]
    6636 #define RSCAN0CFDF010LL RSCAN0.CFDF010.UINT8[LL]
    6637 #define RSCAN0CFDF010LH RSCAN0.CFDF010.UINT8[LH]
    6638 #define RSCAN0CFDF010H RSCAN0.CFDF010.UINT16[H]
    6639 #define RSCAN0CFDF010HL RSCAN0.CFDF010.UINT8[HL]
    6640 #define RSCAN0CFDF010HH RSCAN0.CFDF010.UINT8[HH]
    6641 #define RSCAN0CFDF110 RSCAN0.CFDF110.UINT32
    6642 #define RSCAN0CFDF110L RSCAN0.CFDF110.UINT16[L]
    6643 #define RSCAN0CFDF110LL RSCAN0.CFDF110.UINT8[LL]
    6644 #define RSCAN0CFDF110LH RSCAN0.CFDF110.UINT8[LH]
    6645 #define RSCAN0CFDF110H RSCAN0.CFDF110.UINT16[H]
    6646 #define RSCAN0CFDF110HL RSCAN0.CFDF110.UINT8[HL]
    6647 #define RSCAN0CFDF110HH RSCAN0.CFDF110.UINT8[HH]
    6648 #define RSCAN0CFID11 RSCAN0.CFID11.UINT32
    6649 #define RSCAN0CFID11L RSCAN0.CFID11.UINT16[L]
    6650 #define RSCAN0CFID11LL RSCAN0.CFID11.UINT8[LL]
    6651 #define RSCAN0CFID11LH RSCAN0.CFID11.UINT8[LH]
    6652 #define RSCAN0CFID11H RSCAN0.CFID11.UINT16[H]
    6653 #define RSCAN0CFID11HL RSCAN0.CFID11.UINT8[HL]
    6654 #define RSCAN0CFID11HH RSCAN0.CFID11.UINT8[HH]
    6655 #define RSCAN0CFPTR11 RSCAN0.CFPTR11.UINT32
    6656 #define RSCAN0CFPTR11L RSCAN0.CFPTR11.UINT16[L]
    6657 #define RSCAN0CFPTR11LL RSCAN0.CFPTR11.UINT8[LL]
    6658 #define RSCAN0CFPTR11LH RSCAN0.CFPTR11.UINT8[LH]
    6659 #define RSCAN0CFPTR11H RSCAN0.CFPTR11.UINT16[H]
    6660 #define RSCAN0CFPTR11HL RSCAN0.CFPTR11.UINT8[HL]
    6661 #define RSCAN0CFPTR11HH RSCAN0.CFPTR11.UINT8[HH]
    6662 #define RSCAN0CFDF011 RSCAN0.CFDF011.UINT32
    6663 #define RSCAN0CFDF011L RSCAN0.CFDF011.UINT16[L]
    6664 #define RSCAN0CFDF011LL RSCAN0.CFDF011.UINT8[LL]
    6665 #define RSCAN0CFDF011LH RSCAN0.CFDF011.UINT8[LH]
    6666 #define RSCAN0CFDF011H RSCAN0.CFDF011.UINT16[H]
    6667 #define RSCAN0CFDF011HL RSCAN0.CFDF011.UINT8[HL]
    6668 #define RSCAN0CFDF011HH RSCAN0.CFDF011.UINT8[HH]
    6669 #define RSCAN0CFDF111 RSCAN0.CFDF111.UINT32
    6670 #define RSCAN0CFDF111L RSCAN0.CFDF111.UINT16[L]
    6671 #define RSCAN0CFDF111LL RSCAN0.CFDF111.UINT8[LL]
    6672 #define RSCAN0CFDF111LH RSCAN0.CFDF111.UINT8[LH]
    6673 #define RSCAN0CFDF111H RSCAN0.CFDF111.UINT16[H]
    6674 #define RSCAN0CFDF111HL RSCAN0.CFDF111.UINT8[HL]
    6675 #define RSCAN0CFDF111HH RSCAN0.CFDF111.UINT8[HH]
    6676 #define RSCAN0CFID12 RSCAN0.CFID12.UINT32
    6677 #define RSCAN0CFID12L RSCAN0.CFID12.UINT16[L]
    6678 #define RSCAN0CFID12LL RSCAN0.CFID12.UINT8[LL]
    6679 #define RSCAN0CFID12LH RSCAN0.CFID12.UINT8[LH]
    6680 #define RSCAN0CFID12H RSCAN0.CFID12.UINT16[H]
    6681 #define RSCAN0CFID12HL RSCAN0.CFID12.UINT8[HL]
    6682 #define RSCAN0CFID12HH RSCAN0.CFID12.UINT8[HH]
    6683 #define RSCAN0CFPTR12 RSCAN0.CFPTR12.UINT32
    6684 #define RSCAN0CFPTR12L RSCAN0.CFPTR12.UINT16[L]
    6685 #define RSCAN0CFPTR12LL RSCAN0.CFPTR12.UINT8[LL]
    6686 #define RSCAN0CFPTR12LH RSCAN0.CFPTR12.UINT8[LH]
    6687 #define RSCAN0CFPTR12H RSCAN0.CFPTR12.UINT16[H]
    6688 #define RSCAN0CFPTR12HL RSCAN0.CFPTR12.UINT8[HL]
    6689 #define RSCAN0CFPTR12HH RSCAN0.CFPTR12.UINT8[HH]
    6690 #define RSCAN0CFDF012 RSCAN0.CFDF012.UINT32
    6691 #define RSCAN0CFDF012L RSCAN0.CFDF012.UINT16[L]
    6692 #define RSCAN0CFDF012LL RSCAN0.CFDF012.UINT8[LL]
    6693 #define RSCAN0CFDF012LH RSCAN0.CFDF012.UINT8[LH]
    6694 #define RSCAN0CFDF012H RSCAN0.CFDF012.UINT16[H]
    6695 #define RSCAN0CFDF012HL RSCAN0.CFDF012.UINT8[HL]
    6696 #define RSCAN0CFDF012HH RSCAN0.CFDF012.UINT8[HH]
    6697 #define RSCAN0CFDF112 RSCAN0.CFDF112.UINT32
    6698 #define RSCAN0CFDF112L RSCAN0.CFDF112.UINT16[L]
    6699 #define RSCAN0CFDF112LL RSCAN0.CFDF112.UINT8[LL]
    6700 #define RSCAN0CFDF112LH RSCAN0.CFDF112.UINT8[LH]
    6701 #define RSCAN0CFDF112H RSCAN0.CFDF112.UINT16[H]
    6702 #define RSCAN0CFDF112HL RSCAN0.CFDF112.UINT8[HL]
    6703 #define RSCAN0CFDF112HH RSCAN0.CFDF112.UINT8[HH]
    6704 #define RSCAN0CFID13 RSCAN0.CFID13.UINT32
    6705 #define RSCAN0CFID13L RSCAN0.CFID13.UINT16[L]
    6706 #define RSCAN0CFID13LL RSCAN0.CFID13.UINT8[LL]
    6707 #define RSCAN0CFID13LH RSCAN0.CFID13.UINT8[LH]
    6708 #define RSCAN0CFID13H RSCAN0.CFID13.UINT16[H]
    6709 #define RSCAN0CFID13HL RSCAN0.CFID13.UINT8[HL]
    6710 #define RSCAN0CFID13HH RSCAN0.CFID13.UINT8[HH]
    6711 #define RSCAN0CFPTR13 RSCAN0.CFPTR13.UINT32
    6712 #define RSCAN0CFPTR13L RSCAN0.CFPTR13.UINT16[L]
    6713 #define RSCAN0CFPTR13LL RSCAN0.CFPTR13.UINT8[LL]
    6714 #define RSCAN0CFPTR13LH RSCAN0.CFPTR13.UINT8[LH]
    6715 #define RSCAN0CFPTR13H RSCAN0.CFPTR13.UINT16[H]
    6716 #define RSCAN0CFPTR13HL RSCAN0.CFPTR13.UINT8[HL]
    6717 #define RSCAN0CFPTR13HH RSCAN0.CFPTR13.UINT8[HH]
    6718 #define RSCAN0CFDF013 RSCAN0.CFDF013.UINT32
    6719 #define RSCAN0CFDF013L RSCAN0.CFDF013.UINT16[L]
    6720 #define RSCAN0CFDF013LL RSCAN0.CFDF013.UINT8[LL]
    6721 #define RSCAN0CFDF013LH RSCAN0.CFDF013.UINT8[LH]
    6722 #define RSCAN0CFDF013H RSCAN0.CFDF013.UINT16[H]
    6723 #define RSCAN0CFDF013HL RSCAN0.CFDF013.UINT8[HL]
    6724 #define RSCAN0CFDF013HH RSCAN0.CFDF013.UINT8[HH]
    6725 #define RSCAN0CFDF113 RSCAN0.CFDF113.UINT32
    6726 #define RSCAN0CFDF113L RSCAN0.CFDF113.UINT16[L]
    6727 #define RSCAN0CFDF113LL RSCAN0.CFDF113.UINT8[LL]
    6728 #define RSCAN0CFDF113LH RSCAN0.CFDF113.UINT8[LH]
    6729 #define RSCAN0CFDF113H RSCAN0.CFDF113.UINT16[H]
    6730 #define RSCAN0CFDF113HL RSCAN0.CFDF113.UINT8[HL]
    6731 #define RSCAN0CFDF113HH RSCAN0.CFDF113.UINT8[HH]
    6732 #define RSCAN0CFID14 RSCAN0.CFID14.UINT32
    6733 #define RSCAN0CFID14L RSCAN0.CFID14.UINT16[L]
    6734 #define RSCAN0CFID14LL RSCAN0.CFID14.UINT8[LL]
    6735 #define RSCAN0CFID14LH RSCAN0.CFID14.UINT8[LH]
    6736 #define RSCAN0CFID14H RSCAN0.CFID14.UINT16[H]
    6737 #define RSCAN0CFID14HL RSCAN0.CFID14.UINT8[HL]
    6738 #define RSCAN0CFID14HH RSCAN0.CFID14.UINT8[HH]
    6739 #define RSCAN0CFPTR14 RSCAN0.CFPTR14.UINT32
    6740 #define RSCAN0CFPTR14L RSCAN0.CFPTR14.UINT16[L]
    6741 #define RSCAN0CFPTR14LL RSCAN0.CFPTR14.UINT8[LL]
    6742 #define RSCAN0CFPTR14LH RSCAN0.CFPTR14.UINT8[LH]
    6743 #define RSCAN0CFPTR14H RSCAN0.CFPTR14.UINT16[H]
    6744 #define RSCAN0CFPTR14HL RSCAN0.CFPTR14.UINT8[HL]
    6745 #define RSCAN0CFPTR14HH RSCAN0.CFPTR14.UINT8[HH]
    6746 #define RSCAN0CFDF014 RSCAN0.CFDF014.UINT32
    6747 #define RSCAN0CFDF014L RSCAN0.CFDF014.UINT16[L]
    6748 #define RSCAN0CFDF014LL RSCAN0.CFDF014.UINT8[LL]
    6749 #define RSCAN0CFDF014LH RSCAN0.CFDF014.UINT8[LH]
    6750 #define RSCAN0CFDF014H RSCAN0.CFDF014.UINT16[H]
    6751 #define RSCAN0CFDF014HL RSCAN0.CFDF014.UINT8[HL]
    6752 #define RSCAN0CFDF014HH RSCAN0.CFDF014.UINT8[HH]
    6753 #define RSCAN0CFDF114 RSCAN0.CFDF114.UINT32
    6754 #define RSCAN0CFDF114L RSCAN0.CFDF114.UINT16[L]
    6755 #define RSCAN0CFDF114LL RSCAN0.CFDF114.UINT8[LL]
    6756 #define RSCAN0CFDF114LH RSCAN0.CFDF114.UINT8[LH]
    6757 #define RSCAN0CFDF114H RSCAN0.CFDF114.UINT16[H]
    6758 #define RSCAN0CFDF114HL RSCAN0.CFDF114.UINT8[HL]
    6759 #define RSCAN0CFDF114HH RSCAN0.CFDF114.UINT8[HH]
    6760 #define RSCAN0TMID0 RSCAN0.TMID0.UINT32
    6761 #define RSCAN0TMID0L RSCAN0.TMID0.UINT16[L]
    6762 #define RSCAN0TMID0LL RSCAN0.TMID0.UINT8[LL]
    6763 #define RSCAN0TMID0LH RSCAN0.TMID0.UINT8[LH]
    6764 #define RSCAN0TMID0H RSCAN0.TMID0.UINT16[H]
    6765 #define RSCAN0TMID0HL RSCAN0.TMID0.UINT8[HL]
    6766 #define RSCAN0TMID0HH RSCAN0.TMID0.UINT8[HH]
    6767 #define RSCAN0TMPTR0 RSCAN0.TMPTR0.UINT32
    6768 #define RSCAN0TMPTR0L RSCAN0.TMPTR0.UINT16[L]
    6769 #define RSCAN0TMPTR0LL RSCAN0.TMPTR0.UINT8[LL]
    6770 #define RSCAN0TMPTR0LH RSCAN0.TMPTR0.UINT8[LH]
    6771 #define RSCAN0TMPTR0H RSCAN0.TMPTR0.UINT16[H]
    6772 #define RSCAN0TMPTR0HL RSCAN0.TMPTR0.UINT8[HL]
    6773 #define RSCAN0TMPTR0HH RSCAN0.TMPTR0.UINT8[HH]
    6774 #define RSCAN0TMDF00 RSCAN0.TMDF00.UINT32
    6775 #define RSCAN0TMDF00L RSCAN0.TMDF00.UINT16[L]
    6776 #define RSCAN0TMDF00LL RSCAN0.TMDF00.UINT8[LL]
    6777 #define RSCAN0TMDF00LH RSCAN0.TMDF00.UINT8[LH]
    6778 #define RSCAN0TMDF00H RSCAN0.TMDF00.UINT16[H]
    6779 #define RSCAN0TMDF00HL RSCAN0.TMDF00.UINT8[HL]
    6780 #define RSCAN0TMDF00HH RSCAN0.TMDF00.UINT8[HH]
    6781 #define RSCAN0TMDF10 RSCAN0.TMDF10.UINT32
    6782 #define RSCAN0TMDF10L RSCAN0.TMDF10.UINT16[L]
    6783 #define RSCAN0TMDF10LL RSCAN0.TMDF10.UINT8[LL]
    6784 #define RSCAN0TMDF10LH RSCAN0.TMDF10.UINT8[LH]
    6785 #define RSCAN0TMDF10H RSCAN0.TMDF10.UINT16[H]
    6786 #define RSCAN0TMDF10HL RSCAN0.TMDF10.UINT8[HL]
    6787 #define RSCAN0TMDF10HH RSCAN0.TMDF10.UINT8[HH]
    6788 #define RSCAN0TMID1 RSCAN0.TMID1.UINT32
    6789 #define RSCAN0TMID1L RSCAN0.TMID1.UINT16[L]
    6790 #define RSCAN0TMID1LL RSCAN0.TMID1.UINT8[LL]
    6791 #define RSCAN0TMID1LH RSCAN0.TMID1.UINT8[LH]
    6792 #define RSCAN0TMID1H RSCAN0.TMID1.UINT16[H]
    6793 #define RSCAN0TMID1HL RSCAN0.TMID1.UINT8[HL]
    6794 #define RSCAN0TMID1HH RSCAN0.TMID1.UINT8[HH]
    6795 #define RSCAN0TMPTR1 RSCAN0.TMPTR1.UINT32
    6796 #define RSCAN0TMPTR1L RSCAN0.TMPTR1.UINT16[L]
    6797 #define RSCAN0TMPTR1LL RSCAN0.TMPTR1.UINT8[LL]
    6798 #define RSCAN0TMPTR1LH RSCAN0.TMPTR1.UINT8[LH]
    6799 #define RSCAN0TMPTR1H RSCAN0.TMPTR1.UINT16[H]
    6800 #define RSCAN0TMPTR1HL RSCAN0.TMPTR1.UINT8[HL]
    6801 #define RSCAN0TMPTR1HH RSCAN0.TMPTR1.UINT8[HH]
    6802 #define RSCAN0TMDF01 RSCAN0.TMDF01.UINT32
    6803 #define RSCAN0TMDF01L RSCAN0.TMDF01.UINT16[L]
    6804 #define RSCAN0TMDF01LL RSCAN0.TMDF01.UINT8[LL]
    6805 #define RSCAN0TMDF01LH RSCAN0.TMDF01.UINT8[LH]
    6806 #define RSCAN0TMDF01H RSCAN0.TMDF01.UINT16[H]
    6807 #define RSCAN0TMDF01HL RSCAN0.TMDF01.UINT8[HL]
    6808 #define RSCAN0TMDF01HH RSCAN0.TMDF01.UINT8[HH]
    6809 #define RSCAN0TMDF11 RSCAN0.TMDF11.UINT32
    6810 #define RSCAN0TMDF11L RSCAN0.TMDF11.UINT16[L]
    6811 #define RSCAN0TMDF11LL RSCAN0.TMDF11.UINT8[LL]
    6812 #define RSCAN0TMDF11LH RSCAN0.TMDF11.UINT8[LH]
    6813 #define RSCAN0TMDF11H RSCAN0.TMDF11.UINT16[H]
    6814 #define RSCAN0TMDF11HL RSCAN0.TMDF11.UINT8[HL]
    6815 #define RSCAN0TMDF11HH RSCAN0.TMDF11.UINT8[HH]
    6816 #define RSCAN0TMID2 RSCAN0.TMID2.UINT32
    6817 #define RSCAN0TMID2L RSCAN0.TMID2.UINT16[L]
    6818 #define RSCAN0TMID2LL RSCAN0.TMID2.UINT8[LL]
    6819 #define RSCAN0TMID2LH RSCAN0.TMID2.UINT8[LH]
    6820 #define RSCAN0TMID2H RSCAN0.TMID2.UINT16[H]
    6821 #define RSCAN0TMID2HL RSCAN0.TMID2.UINT8[HL]
    6822 #define RSCAN0TMID2HH RSCAN0.TMID2.UINT8[HH]
    6823 #define RSCAN0TMPTR2 RSCAN0.TMPTR2.UINT32
    6824 #define RSCAN0TMPTR2L RSCAN0.TMPTR2.UINT16[L]
    6825 #define RSCAN0TMPTR2LL RSCAN0.TMPTR2.UINT8[LL]
    6826 #define RSCAN0TMPTR2LH RSCAN0.TMPTR2.UINT8[LH]
    6827 #define RSCAN0TMPTR2H RSCAN0.TMPTR2.UINT16[H]
    6828 #define RSCAN0TMPTR2HL RSCAN0.TMPTR2.UINT8[HL]
    6829 #define RSCAN0TMPTR2HH RSCAN0.TMPTR2.UINT8[HH]
    6830 #define RSCAN0TMDF02 RSCAN0.TMDF02.UINT32
    6831 #define RSCAN0TMDF02L RSCAN0.TMDF02.UINT16[L]
    6832 #define RSCAN0TMDF02LL RSCAN0.TMDF02.UINT8[LL]
    6833 #define RSCAN0TMDF02LH RSCAN0.TMDF02.UINT8[LH]
    6834 #define RSCAN0TMDF02H RSCAN0.TMDF02.UINT16[H]
    6835 #define RSCAN0TMDF02HL RSCAN0.TMDF02.UINT8[HL]
    6836 #define RSCAN0TMDF02HH RSCAN0.TMDF02.UINT8[HH]
    6837 #define RSCAN0TMDF12 RSCAN0.TMDF12.UINT32
    6838 #define RSCAN0TMDF12L RSCAN0.TMDF12.UINT16[L]
    6839 #define RSCAN0TMDF12LL RSCAN0.TMDF12.UINT8[LL]
    6840 #define RSCAN0TMDF12LH RSCAN0.TMDF12.UINT8[LH]
    6841 #define RSCAN0TMDF12H RSCAN0.TMDF12.UINT16[H]
    6842 #define RSCAN0TMDF12HL RSCAN0.TMDF12.UINT8[HL]
    6843 #define RSCAN0TMDF12HH RSCAN0.TMDF12.UINT8[HH]
    6844 #define RSCAN0TMID3 RSCAN0.TMID3.UINT32
    6845 #define RSCAN0TMID3L RSCAN0.TMID3.UINT16[L]
    6846 #define RSCAN0TMID3LL RSCAN0.TMID3.UINT8[LL]
    6847 #define RSCAN0TMID3LH RSCAN0.TMID3.UINT8[LH]
    6848 #define RSCAN0TMID3H RSCAN0.TMID3.UINT16[H]
    6849 #define RSCAN0TMID3HL RSCAN0.TMID3.UINT8[HL]
    6850 #define RSCAN0TMID3HH RSCAN0.TMID3.UINT8[HH]
    6851 #define RSCAN0TMPTR3 RSCAN0.TMPTR3.UINT32
    6852 #define RSCAN0TMPTR3L RSCAN0.TMPTR3.UINT16[L]
    6853 #define RSCAN0TMPTR3LL RSCAN0.TMPTR3.UINT8[LL]
    6854 #define RSCAN0TMPTR3LH RSCAN0.TMPTR3.UINT8[LH]
    6855 #define RSCAN0TMPTR3H RSCAN0.TMPTR3.UINT16[H]
    6856 #define RSCAN0TMPTR3HL RSCAN0.TMPTR3.UINT8[HL]
    6857 #define RSCAN0TMPTR3HH RSCAN0.TMPTR3.UINT8[HH]
    6858 #define RSCAN0TMDF03 RSCAN0.TMDF03.UINT32
    6859 #define RSCAN0TMDF03L RSCAN0.TMDF03.UINT16[L]
    6860 #define RSCAN0TMDF03LL RSCAN0.TMDF03.UINT8[LL]
    6861 #define RSCAN0TMDF03LH RSCAN0.TMDF03.UINT8[LH]
    6862 #define RSCAN0TMDF03H RSCAN0.TMDF03.UINT16[H]
    6863 #define RSCAN0TMDF03HL RSCAN0.TMDF03.UINT8[HL]
    6864 #define RSCAN0TMDF03HH RSCAN0.TMDF03.UINT8[HH]
    6865 #define RSCAN0TMDF13 RSCAN0.TMDF13.UINT32
    6866 #define RSCAN0TMDF13L RSCAN0.TMDF13.UINT16[L]
    6867 #define RSCAN0TMDF13LL RSCAN0.TMDF13.UINT8[LL]
    6868 #define RSCAN0TMDF13LH RSCAN0.TMDF13.UINT8[LH]
    6869 #define RSCAN0TMDF13H RSCAN0.TMDF13.UINT16[H]
    6870 #define RSCAN0TMDF13HL RSCAN0.TMDF13.UINT8[HL]
    6871 #define RSCAN0TMDF13HH RSCAN0.TMDF13.UINT8[HH]
    6872 #define RSCAN0TMID4 RSCAN0.TMID4.UINT32
    6873 #define RSCAN0TMID4L RSCAN0.TMID4.UINT16[L]
    6874 #define RSCAN0TMID4LL RSCAN0.TMID4.UINT8[LL]
    6875 #define RSCAN0TMID4LH RSCAN0.TMID4.UINT8[LH]
    6876 #define RSCAN0TMID4H RSCAN0.TMID4.UINT16[H]
    6877 #define RSCAN0TMID4HL RSCAN0.TMID4.UINT8[HL]
    6878 #define RSCAN0TMID4HH RSCAN0.TMID4.UINT8[HH]
    6879 #define RSCAN0TMPTR4 RSCAN0.TMPTR4.UINT32
    6880 #define RSCAN0TMPTR4L RSCAN0.TMPTR4.UINT16[L]
    6881 #define RSCAN0TMPTR4LL RSCAN0.TMPTR4.UINT8[LL]
    6882 #define RSCAN0TMPTR4LH RSCAN0.TMPTR4.UINT8[LH]
    6883 #define RSCAN0TMPTR4H RSCAN0.TMPTR4.UINT16[H]
    6884 #define RSCAN0TMPTR4HL RSCAN0.TMPTR4.UINT8[HL]
    6885 #define RSCAN0TMPTR4HH RSCAN0.TMPTR4.UINT8[HH]
    6886 #define RSCAN0TMDF04 RSCAN0.TMDF04.UINT32
    6887 #define RSCAN0TMDF04L RSCAN0.TMDF04.UINT16[L]
    6888 #define RSCAN0TMDF04LL RSCAN0.TMDF04.UINT8[LL]
    6889 #define RSCAN0TMDF04LH RSCAN0.TMDF04.UINT8[LH]
    6890 #define RSCAN0TMDF04H RSCAN0.TMDF04.UINT16[H]
    6891 #define RSCAN0TMDF04HL RSCAN0.TMDF04.UINT8[HL]
    6892 #define RSCAN0TMDF04HH RSCAN0.TMDF04.UINT8[HH]
    6893 #define RSCAN0TMDF14 RSCAN0.TMDF14.UINT32
    6894 #define RSCAN0TMDF14L RSCAN0.TMDF14.UINT16[L]
    6895 #define RSCAN0TMDF14LL RSCAN0.TMDF14.UINT8[LL]
    6896 #define RSCAN0TMDF14LH RSCAN0.TMDF14.UINT8[LH]
    6897 #define RSCAN0TMDF14H RSCAN0.TMDF14.UINT16[H]
    6898 #define RSCAN0TMDF14HL RSCAN0.TMDF14.UINT8[HL]
    6899 #define RSCAN0TMDF14HH RSCAN0.TMDF14.UINT8[HH]
    6900 #define RSCAN0TMID5 RSCAN0.TMID5.UINT32
    6901 #define RSCAN0TMID5L RSCAN0.TMID5.UINT16[L]
    6902 #define RSCAN0TMID5LL RSCAN0.TMID5.UINT8[LL]
    6903 #define RSCAN0TMID5LH RSCAN0.TMID5.UINT8[LH]
    6904 #define RSCAN0TMID5H RSCAN0.TMID5.UINT16[H]
    6905 #define RSCAN0TMID5HL RSCAN0.TMID5.UINT8[HL]
    6906 #define RSCAN0TMID5HH RSCAN0.TMID5.UINT8[HH]
    6907 #define RSCAN0TMPTR5 RSCAN0.TMPTR5.UINT32
    6908 #define RSCAN0TMPTR5L RSCAN0.TMPTR5.UINT16[L]
    6909 #define RSCAN0TMPTR5LL RSCAN0.TMPTR5.UINT8[LL]
    6910 #define RSCAN0TMPTR5LH RSCAN0.TMPTR5.UINT8[LH]
    6911 #define RSCAN0TMPTR5H RSCAN0.TMPTR5.UINT16[H]
    6912 #define RSCAN0TMPTR5HL RSCAN0.TMPTR5.UINT8[HL]
    6913 #define RSCAN0TMPTR5HH RSCAN0.TMPTR5.UINT8[HH]
    6914 #define RSCAN0TMDF05 RSCAN0.TMDF05.UINT32
    6915 #define RSCAN0TMDF05L RSCAN0.TMDF05.UINT16[L]
    6916 #define RSCAN0TMDF05LL RSCAN0.TMDF05.UINT8[LL]
    6917 #define RSCAN0TMDF05LH RSCAN0.TMDF05.UINT8[LH]
    6918 #define RSCAN0TMDF05H RSCAN0.TMDF05.UINT16[H]
    6919 #define RSCAN0TMDF05HL RSCAN0.TMDF05.UINT8[HL]
    6920 #define RSCAN0TMDF05HH RSCAN0.TMDF05.UINT8[HH]
    6921 #define RSCAN0TMDF15 RSCAN0.TMDF15.UINT32
    6922 #define RSCAN0TMDF15L RSCAN0.TMDF15.UINT16[L]
    6923 #define RSCAN0TMDF15LL RSCAN0.TMDF15.UINT8[LL]
    6924 #define RSCAN0TMDF15LH RSCAN0.TMDF15.UINT8[LH]
    6925 #define RSCAN0TMDF15H RSCAN0.TMDF15.UINT16[H]
    6926 #define RSCAN0TMDF15HL RSCAN0.TMDF15.UINT8[HL]
    6927 #define RSCAN0TMDF15HH RSCAN0.TMDF15.UINT8[HH]
    6928 #define RSCAN0TMID6 RSCAN0.TMID6.UINT32
    6929 #define RSCAN0TMID6L RSCAN0.TMID6.UINT16[L]
    6930 #define RSCAN0TMID6LL RSCAN0.TMID6.UINT8[LL]
    6931 #define RSCAN0TMID6LH RSCAN0.TMID6.UINT8[LH]
    6932 #define RSCAN0TMID6H RSCAN0.TMID6.UINT16[H]
    6933 #define RSCAN0TMID6HL RSCAN0.TMID6.UINT8[HL]
    6934 #define RSCAN0TMID6HH RSCAN0.TMID6.UINT8[HH]
    6935 #define RSCAN0TMPTR6 RSCAN0.TMPTR6.UINT32
    6936 #define RSCAN0TMPTR6L RSCAN0.TMPTR6.UINT16[L]
    6937 #define RSCAN0TMPTR6LL RSCAN0.TMPTR6.UINT8[LL]
    6938 #define RSCAN0TMPTR6LH RSCAN0.TMPTR6.UINT8[LH]
    6939 #define RSCAN0TMPTR6H RSCAN0.TMPTR6.UINT16[H]
    6940 #define RSCAN0TMPTR6HL RSCAN0.TMPTR6.UINT8[HL]
    6941 #define RSCAN0TMPTR6HH RSCAN0.TMPTR6.UINT8[HH]
    6942 #define RSCAN0TMDF06 RSCAN0.TMDF06.UINT32
    6943 #define RSCAN0TMDF06L RSCAN0.TMDF06.UINT16[L]
    6944 #define RSCAN0TMDF06LL RSCAN0.TMDF06.UINT8[LL]
    6945 #define RSCAN0TMDF06LH RSCAN0.TMDF06.UINT8[LH]
    6946 #define RSCAN0TMDF06H RSCAN0.TMDF06.UINT16[H]
    6947 #define RSCAN0TMDF06HL RSCAN0.TMDF06.UINT8[HL]
    6948 #define RSCAN0TMDF06HH RSCAN0.TMDF06.UINT8[HH]
    6949 #define RSCAN0TMDF16 RSCAN0.TMDF16.UINT32
    6950 #define RSCAN0TMDF16L RSCAN0.TMDF16.UINT16[L]
    6951 #define RSCAN0TMDF16LL RSCAN0.TMDF16.UINT8[LL]
    6952 #define RSCAN0TMDF16LH RSCAN0.TMDF16.UINT8[LH]
    6953 #define RSCAN0TMDF16H RSCAN0.TMDF16.UINT16[H]
    6954 #define RSCAN0TMDF16HL RSCAN0.TMDF16.UINT8[HL]
    6955 #define RSCAN0TMDF16HH RSCAN0.TMDF16.UINT8[HH]
    6956 #define RSCAN0TMID7 RSCAN0.TMID7.UINT32
    6957 #define RSCAN0TMID7L RSCAN0.TMID7.UINT16[L]
    6958 #define RSCAN0TMID7LL RSCAN0.TMID7.UINT8[LL]
    6959 #define RSCAN0TMID7LH RSCAN0.TMID7.UINT8[LH]
    6960 #define RSCAN0TMID7H RSCAN0.TMID7.UINT16[H]
    6961 #define RSCAN0TMID7HL RSCAN0.TMID7.UINT8[HL]
    6962 #define RSCAN0TMID7HH RSCAN0.TMID7.UINT8[HH]
    6963 #define RSCAN0TMPTR7 RSCAN0.TMPTR7.UINT32
    6964 #define RSCAN0TMPTR7L RSCAN0.TMPTR7.UINT16[L]
    6965 #define RSCAN0TMPTR7LL RSCAN0.TMPTR7.UINT8[LL]
    6966 #define RSCAN0TMPTR7LH RSCAN0.TMPTR7.UINT8[LH]
    6967 #define RSCAN0TMPTR7H RSCAN0.TMPTR7.UINT16[H]
    6968 #define RSCAN0TMPTR7HL RSCAN0.TMPTR7.UINT8[HL]
    6969 #define RSCAN0TMPTR7HH RSCAN0.TMPTR7.UINT8[HH]
    6970 #define RSCAN0TMDF07 RSCAN0.TMDF07.UINT32
    6971 #define RSCAN0TMDF07L RSCAN0.TMDF07.UINT16[L]
    6972 #define RSCAN0TMDF07LL RSCAN0.TMDF07.UINT8[LL]
    6973 #define RSCAN0TMDF07LH RSCAN0.TMDF07.UINT8[LH]
    6974 #define RSCAN0TMDF07H RSCAN0.TMDF07.UINT16[H]
    6975 #define RSCAN0TMDF07HL RSCAN0.TMDF07.UINT8[HL]
    6976 #define RSCAN0TMDF07HH RSCAN0.TMDF07.UINT8[HH]
    6977 #define RSCAN0TMDF17 RSCAN0.TMDF17.UINT32
    6978 #define RSCAN0TMDF17L RSCAN0.TMDF17.UINT16[L]
    6979 #define RSCAN0TMDF17LL RSCAN0.TMDF17.UINT8[LL]
    6980 #define RSCAN0TMDF17LH RSCAN0.TMDF17.UINT8[LH]
    6981 #define RSCAN0TMDF17H RSCAN0.TMDF17.UINT16[H]
    6982 #define RSCAN0TMDF17HL RSCAN0.TMDF17.UINT8[HL]
    6983 #define RSCAN0TMDF17HH RSCAN0.TMDF17.UINT8[HH]
    6984 #define RSCAN0TMID8 RSCAN0.TMID8.UINT32
    6985 #define RSCAN0TMID8L RSCAN0.TMID8.UINT16[L]
    6986 #define RSCAN0TMID8LL RSCAN0.TMID8.UINT8[LL]
    6987 #define RSCAN0TMID8LH RSCAN0.TMID8.UINT8[LH]
    6988 #define RSCAN0TMID8H RSCAN0.TMID8.UINT16[H]
    6989 #define RSCAN0TMID8HL RSCAN0.TMID8.UINT8[HL]
    6990 #define RSCAN0TMID8HH RSCAN0.TMID8.UINT8[HH]
    6991 #define RSCAN0TMPTR8 RSCAN0.TMPTR8.UINT32
    6992 #define RSCAN0TMPTR8L RSCAN0.TMPTR8.UINT16[L]
    6993 #define RSCAN0TMPTR8LL RSCAN0.TMPTR8.UINT8[LL]
    6994 #define RSCAN0TMPTR8LH RSCAN0.TMPTR8.UINT8[LH]
    6995 #define RSCAN0TMPTR8H RSCAN0.TMPTR8.UINT16[H]
    6996 #define RSCAN0TMPTR8HL RSCAN0.TMPTR8.UINT8[HL]
    6997 #define RSCAN0TMPTR8HH RSCAN0.TMPTR8.UINT8[HH]
    6998 #define RSCAN0TMDF08 RSCAN0.TMDF08.UINT32
    6999 #define RSCAN0TMDF08L RSCAN0.TMDF08.UINT16[L]
    7000 #define RSCAN0TMDF08LL RSCAN0.TMDF08.UINT8[LL]
    7001 #define RSCAN0TMDF08LH RSCAN0.TMDF08.UINT8[LH]
    7002 #define RSCAN0TMDF08H RSCAN0.TMDF08.UINT16[H]
    7003 #define RSCAN0TMDF08HL RSCAN0.TMDF08.UINT8[HL]
    7004 #define RSCAN0TMDF08HH RSCAN0.TMDF08.UINT8[HH]
    7005 #define RSCAN0TMDF18 RSCAN0.TMDF18.UINT32
    7006 #define RSCAN0TMDF18L RSCAN0.TMDF18.UINT16[L]
    7007 #define RSCAN0TMDF18LL RSCAN0.TMDF18.UINT8[LL]
    7008 #define RSCAN0TMDF18LH RSCAN0.TMDF18.UINT8[LH]
    7009 #define RSCAN0TMDF18H RSCAN0.TMDF18.UINT16[H]
    7010 #define RSCAN0TMDF18HL RSCAN0.TMDF18.UINT8[HL]
    7011 #define RSCAN0TMDF18HH RSCAN0.TMDF18.UINT8[HH]
    7012 #define RSCAN0TMID9 RSCAN0.TMID9.UINT32
    7013 #define RSCAN0TMID9L RSCAN0.TMID9.UINT16[L]
    7014 #define RSCAN0TMID9LL RSCAN0.TMID9.UINT8[LL]
    7015 #define RSCAN0TMID9LH RSCAN0.TMID9.UINT8[LH]
    7016 #define RSCAN0TMID9H RSCAN0.TMID9.UINT16[H]
    7017 #define RSCAN0TMID9HL RSCAN0.TMID9.UINT8[HL]
    7018 #define RSCAN0TMID9HH RSCAN0.TMID9.UINT8[HH]
    7019 #define RSCAN0TMPTR9 RSCAN0.TMPTR9.UINT32
    7020 #define RSCAN0TMPTR9L RSCAN0.TMPTR9.UINT16[L]
    7021 #define RSCAN0TMPTR9LL RSCAN0.TMPTR9.UINT8[LL]
    7022 #define RSCAN0TMPTR9LH RSCAN0.TMPTR9.UINT8[LH]
    7023 #define RSCAN0TMPTR9H RSCAN0.TMPTR9.UINT16[H]
    7024 #define RSCAN0TMPTR9HL RSCAN0.TMPTR9.UINT8[HL]
    7025 #define RSCAN0TMPTR9HH RSCAN0.TMPTR9.UINT8[HH]
    7026 #define RSCAN0TMDF09 RSCAN0.TMDF09.UINT32
    7027 #define RSCAN0TMDF09L RSCAN0.TMDF09.UINT16[L]
    7028 #define RSCAN0TMDF09LL RSCAN0.TMDF09.UINT8[LL]
    7029 #define RSCAN0TMDF09LH RSCAN0.TMDF09.UINT8[LH]
    7030 #define RSCAN0TMDF09H RSCAN0.TMDF09.UINT16[H]
    7031 #define RSCAN0TMDF09HL RSCAN0.TMDF09.UINT8[HL]
    7032 #define RSCAN0TMDF09HH RSCAN0.TMDF09.UINT8[HH]
    7033 #define RSCAN0TMDF19 RSCAN0.TMDF19.UINT32
    7034 #define RSCAN0TMDF19L RSCAN0.TMDF19.UINT16[L]
    7035 #define RSCAN0TMDF19LL RSCAN0.TMDF19.UINT8[LL]
    7036 #define RSCAN0TMDF19LH RSCAN0.TMDF19.UINT8[LH]
    7037 #define RSCAN0TMDF19H RSCAN0.TMDF19.UINT16[H]
    7038 #define RSCAN0TMDF19HL RSCAN0.TMDF19.UINT8[HL]
    7039 #define RSCAN0TMDF19HH RSCAN0.TMDF19.UINT8[HH]
    7040 #define RSCAN0TMID10 RSCAN0.TMID10.UINT32
    7041 #define RSCAN0TMID10L RSCAN0.TMID10.UINT16[L]
    7042 #define RSCAN0TMID10LL RSCAN0.TMID10.UINT8[LL]
    7043 #define RSCAN0TMID10LH RSCAN0.TMID10.UINT8[LH]
    7044 #define RSCAN0TMID10H RSCAN0.TMID10.UINT16[H]
    7045 #define RSCAN0TMID10HL RSCAN0.TMID10.UINT8[HL]
    7046 #define RSCAN0TMID10HH RSCAN0.TMID10.UINT8[HH]
    7047 #define RSCAN0TMPTR10 RSCAN0.TMPTR10.UINT32
    7048 #define RSCAN0TMPTR10L RSCAN0.TMPTR10.UINT16[L]
    7049 #define RSCAN0TMPTR10LL RSCAN0.TMPTR10.UINT8[LL]
    7050 #define RSCAN0TMPTR10LH RSCAN0.TMPTR10.UINT8[LH]
    7051 #define RSCAN0TMPTR10H RSCAN0.TMPTR10.UINT16[H]
    7052 #define RSCAN0TMPTR10HL RSCAN0.TMPTR10.UINT8[HL]
    7053 #define RSCAN0TMPTR10HH RSCAN0.TMPTR10.UINT8[HH]
    7054 #define RSCAN0TMDF010 RSCAN0.TMDF010.UINT32
    7055 #define RSCAN0TMDF010L RSCAN0.TMDF010.UINT16[L]
    7056 #define RSCAN0TMDF010LL RSCAN0.TMDF010.UINT8[LL]
    7057 #define RSCAN0TMDF010LH RSCAN0.TMDF010.UINT8[LH]
    7058 #define RSCAN0TMDF010H RSCAN0.TMDF010.UINT16[H]
    7059 #define RSCAN0TMDF010HL RSCAN0.TMDF010.UINT8[HL]
    7060 #define RSCAN0TMDF010HH RSCAN0.TMDF010.UINT8[HH]
    7061 #define RSCAN0TMDF110 RSCAN0.TMDF110.UINT32
    7062 #define RSCAN0TMDF110L RSCAN0.TMDF110.UINT16[L]
    7063 #define RSCAN0TMDF110LL RSCAN0.TMDF110.UINT8[LL]
    7064 #define RSCAN0TMDF110LH RSCAN0.TMDF110.UINT8[LH]
    7065 #define RSCAN0TMDF110H RSCAN0.TMDF110.UINT16[H]
    7066 #define RSCAN0TMDF110HL RSCAN0.TMDF110.UINT8[HL]
    7067 #define RSCAN0TMDF110HH RSCAN0.TMDF110.UINT8[HH]
    7068 #define RSCAN0TMID11 RSCAN0.TMID11.UINT32
    7069 #define RSCAN0TMID11L RSCAN0.TMID11.UINT16[L]
    7070 #define RSCAN0TMID11LL RSCAN0.TMID11.UINT8[LL]
    7071 #define RSCAN0TMID11LH RSCAN0.TMID11.UINT8[LH]
    7072 #define RSCAN0TMID11H RSCAN0.TMID11.UINT16[H]
    7073 #define RSCAN0TMID11HL RSCAN0.TMID11.UINT8[HL]
    7074 #define RSCAN0TMID11HH RSCAN0.TMID11.UINT8[HH]
    7075 #define RSCAN0TMPTR11 RSCAN0.TMPTR11.UINT32
    7076 #define RSCAN0TMPTR11L RSCAN0.TMPTR11.UINT16[L]
    7077 #define RSCAN0TMPTR11LL RSCAN0.TMPTR11.UINT8[LL]
    7078 #define RSCAN0TMPTR11LH RSCAN0.TMPTR11.UINT8[LH]
    7079 #define RSCAN0TMPTR11H RSCAN0.TMPTR11.UINT16[H]
    7080 #define RSCAN0TMPTR11HL RSCAN0.TMPTR11.UINT8[HL]
    7081 #define RSCAN0TMPTR11HH RSCAN0.TMPTR11.UINT8[HH]
    7082 #define RSCAN0TMDF011 RSCAN0.TMDF011.UINT32
    7083 #define RSCAN0TMDF011L RSCAN0.TMDF011.UINT16[L]
    7084 #define RSCAN0TMDF011LL RSCAN0.TMDF011.UINT8[LL]
    7085 #define RSCAN0TMDF011LH RSCAN0.TMDF011.UINT8[LH]
    7086 #define RSCAN0TMDF011H RSCAN0.TMDF011.UINT16[H]
    7087 #define RSCAN0TMDF011HL RSCAN0.TMDF011.UINT8[HL]
    7088 #define RSCAN0TMDF011HH RSCAN0.TMDF011.UINT8[HH]
    7089 #define RSCAN0TMDF111 RSCAN0.TMDF111.UINT32
    7090 #define RSCAN0TMDF111L RSCAN0.TMDF111.UINT16[L]
    7091 #define RSCAN0TMDF111LL RSCAN0.TMDF111.UINT8[LL]
    7092 #define RSCAN0TMDF111LH RSCAN0.TMDF111.UINT8[LH]
    7093 #define RSCAN0TMDF111H RSCAN0.TMDF111.UINT16[H]
    7094 #define RSCAN0TMDF111HL RSCAN0.TMDF111.UINT8[HL]
    7095 #define RSCAN0TMDF111HH RSCAN0.TMDF111.UINT8[HH]
    7096 #define RSCAN0TMID12 RSCAN0.TMID12.UINT32
    7097 #define RSCAN0TMID12L RSCAN0.TMID12.UINT16[L]
    7098 #define RSCAN0TMID12LL RSCAN0.TMID12.UINT8[LL]
    7099 #define RSCAN0TMID12LH RSCAN0.TMID12.UINT8[LH]
    7100 #define RSCAN0TMID12H RSCAN0.TMID12.UINT16[H]
    7101 #define RSCAN0TMID12HL RSCAN0.TMID12.UINT8[HL]
    7102 #define RSCAN0TMID12HH RSCAN0.TMID12.UINT8[HH]
    7103 #define RSCAN0TMPTR12 RSCAN0.TMPTR12.UINT32
    7104 #define RSCAN0TMPTR12L RSCAN0.TMPTR12.UINT16[L]
    7105 #define RSCAN0TMPTR12LL RSCAN0.TMPTR12.UINT8[LL]
    7106 #define RSCAN0TMPTR12LH RSCAN0.TMPTR12.UINT8[LH]
    7107 #define RSCAN0TMPTR12H RSCAN0.TMPTR12.UINT16[H]
    7108 #define RSCAN0TMPTR12HL RSCAN0.TMPTR12.UINT8[HL]
    7109 #define RSCAN0TMPTR12HH RSCAN0.TMPTR12.UINT8[HH]
    7110 #define RSCAN0TMDF012 RSCAN0.TMDF012.UINT32
    7111 #define RSCAN0TMDF012L RSCAN0.TMDF012.UINT16[L]
    7112 #define RSCAN0TMDF012LL RSCAN0.TMDF012.UINT8[LL]
    7113 #define RSCAN0TMDF012LH RSCAN0.TMDF012.UINT8[LH]
    7114 #define RSCAN0TMDF012H RSCAN0.TMDF012.UINT16[H]
    7115 #define RSCAN0TMDF012HL RSCAN0.TMDF012.UINT8[HL]
    7116 #define RSCAN0TMDF012HH RSCAN0.TMDF012.UINT8[HH]
    7117 #define RSCAN0TMDF112 RSCAN0.TMDF112.UINT32
    7118 #define RSCAN0TMDF112L RSCAN0.TMDF112.UINT16[L]
    7119 #define RSCAN0TMDF112LL RSCAN0.TMDF112.UINT8[LL]
    7120 #define RSCAN0TMDF112LH RSCAN0.TMDF112.UINT8[LH]
    7121 #define RSCAN0TMDF112H RSCAN0.TMDF112.UINT16[H]
    7122 #define RSCAN0TMDF112HL RSCAN0.TMDF112.UINT8[HL]
    7123 #define RSCAN0TMDF112HH RSCAN0.TMDF112.UINT8[HH]
    7124 #define RSCAN0TMID13 RSCAN0.TMID13.UINT32
    7125 #define RSCAN0TMID13L RSCAN0.TMID13.UINT16[L]
    7126 #define RSCAN0TMID13LL RSCAN0.TMID13.UINT8[LL]
    7127 #define RSCAN0TMID13LH RSCAN0.TMID13.UINT8[LH]
    7128 #define RSCAN0TMID13H RSCAN0.TMID13.UINT16[H]
    7129 #define RSCAN0TMID13HL RSCAN0.TMID13.UINT8[HL]
    7130 #define RSCAN0TMID13HH RSCAN0.TMID13.UINT8[HH]
    7131 #define RSCAN0TMPTR13 RSCAN0.TMPTR13.UINT32
    7132 #define RSCAN0TMPTR13L RSCAN0.TMPTR13.UINT16[L]
    7133 #define RSCAN0TMPTR13LL RSCAN0.TMPTR13.UINT8[LL]
    7134 #define RSCAN0TMPTR13LH RSCAN0.TMPTR13.UINT8[LH]
    7135 #define RSCAN0TMPTR13H RSCAN0.TMPTR13.UINT16[H]
    7136 #define RSCAN0TMPTR13HL RSCAN0.TMPTR13.UINT8[HL]
    7137 #define RSCAN0TMPTR13HH RSCAN0.TMPTR13.UINT8[HH]
    7138 #define RSCAN0TMDF013 RSCAN0.TMDF013.UINT32
    7139 #define RSCAN0TMDF013L RSCAN0.TMDF013.UINT16[L]
    7140 #define RSCAN0TMDF013LL RSCAN0.TMDF013.UINT8[LL]
    7141 #define RSCAN0TMDF013LH RSCAN0.TMDF013.UINT8[LH]
    7142 #define RSCAN0TMDF013H RSCAN0.TMDF013.UINT16[H]
    7143 #define RSCAN0TMDF013HL RSCAN0.TMDF013.UINT8[HL]
    7144 #define RSCAN0TMDF013HH RSCAN0.TMDF013.UINT8[HH]
    7145 #define RSCAN0TMDF113 RSCAN0.TMDF113.UINT32
    7146 #define RSCAN0TMDF113L RSCAN0.TMDF113.UINT16[L]
    7147 #define RSCAN0TMDF113LL RSCAN0.TMDF113.UINT8[LL]
    7148 #define RSCAN0TMDF113LH RSCAN0.TMDF113.UINT8[LH]
    7149 #define RSCAN0TMDF113H RSCAN0.TMDF113.UINT16[H]
    7150 #define RSCAN0TMDF113HL RSCAN0.TMDF113.UINT8[HL]
    7151 #define RSCAN0TMDF113HH RSCAN0.TMDF113.UINT8[HH]
    7152 #define RSCAN0TMID14 RSCAN0.TMID14.UINT32
    7153 #define RSCAN0TMID14L RSCAN0.TMID14.UINT16[L]
    7154 #define RSCAN0TMID14LL RSCAN0.TMID14.UINT8[LL]
    7155 #define RSCAN0TMID14LH RSCAN0.TMID14.UINT8[LH]
    7156 #define RSCAN0TMID14H RSCAN0.TMID14.UINT16[H]
    7157 #define RSCAN0TMID14HL RSCAN0.TMID14.UINT8[HL]
    7158 #define RSCAN0TMID14HH RSCAN0.TMID14.UINT8[HH]
    7159 #define RSCAN0TMPTR14 RSCAN0.TMPTR14.UINT32
    7160 #define RSCAN0TMPTR14L RSCAN0.TMPTR14.UINT16[L]
    7161 #define RSCAN0TMPTR14LL RSCAN0.TMPTR14.UINT8[LL]
    7162 #define RSCAN0TMPTR14LH RSCAN0.TMPTR14.UINT8[LH]
    7163 #define RSCAN0TMPTR14H RSCAN0.TMPTR14.UINT16[H]
    7164 #define RSCAN0TMPTR14HL RSCAN0.TMPTR14.UINT8[HL]
    7165 #define RSCAN0TMPTR14HH RSCAN0.TMPTR14.UINT8[HH]
    7166 #define RSCAN0TMDF014 RSCAN0.TMDF014.UINT32
    7167 #define RSCAN0TMDF014L RSCAN0.TMDF014.UINT16[L]
    7168 #define RSCAN0TMDF014LL RSCAN0.TMDF014.UINT8[LL]
    7169 #define RSCAN0TMDF014LH RSCAN0.TMDF014.UINT8[LH]
    7170 #define RSCAN0TMDF014H RSCAN0.TMDF014.UINT16[H]
    7171 #define RSCAN0TMDF014HL RSCAN0.TMDF014.UINT8[HL]
    7172 #define RSCAN0TMDF014HH RSCAN0.TMDF014.UINT8[HH]
    7173 #define RSCAN0TMDF114 RSCAN0.TMDF114.UINT32
    7174 #define RSCAN0TMDF114L RSCAN0.TMDF114.UINT16[L]
    7175 #define RSCAN0TMDF114LL RSCAN0.TMDF114.UINT8[LL]
    7176 #define RSCAN0TMDF114LH RSCAN0.TMDF114.UINT8[LH]
    7177 #define RSCAN0TMDF114H RSCAN0.TMDF114.UINT16[H]
    7178 #define RSCAN0TMDF114HL RSCAN0.TMDF114.UINT8[HL]
    7179 #define RSCAN0TMDF114HH RSCAN0.TMDF114.UINT8[HH]
    7180 #define RSCAN0TMID15 RSCAN0.TMID15.UINT32
    7181 #define RSCAN0TMID15L RSCAN0.TMID15.UINT16[L]
    7182 #define RSCAN0TMID15LL RSCAN0.TMID15.UINT8[LL]
    7183 #define RSCAN0TMID15LH RSCAN0.TMID15.UINT8[LH]
    7184 #define RSCAN0TMID15H RSCAN0.TMID15.UINT16[H]
    7185 #define RSCAN0TMID15HL RSCAN0.TMID15.UINT8[HL]
    7186 #define RSCAN0TMID15HH RSCAN0.TMID15.UINT8[HH]
    7187 #define RSCAN0TMPTR15 RSCAN0.TMPTR15.UINT32
    7188 #define RSCAN0TMPTR15L RSCAN0.TMPTR15.UINT16[L]
    7189 #define RSCAN0TMPTR15LL RSCAN0.TMPTR15.UINT8[LL]
    7190 #define RSCAN0TMPTR15LH RSCAN0.TMPTR15.UINT8[LH]
    7191 #define RSCAN0TMPTR15H RSCAN0.TMPTR15.UINT16[H]
    7192 #define RSCAN0TMPTR15HL RSCAN0.TMPTR15.UINT8[HL]
    7193 #define RSCAN0TMPTR15HH RSCAN0.TMPTR15.UINT8[HH]
    7194 #define RSCAN0TMDF015 RSCAN0.TMDF015.UINT32
    7195 #define RSCAN0TMDF015L RSCAN0.TMDF015.UINT16[L]
    7196 #define RSCAN0TMDF015LL RSCAN0.TMDF015.UINT8[LL]
    7197 #define RSCAN0TMDF015LH RSCAN0.TMDF015.UINT8[LH]
    7198 #define RSCAN0TMDF015H RSCAN0.TMDF015.UINT16[H]
    7199 #define RSCAN0TMDF015HL RSCAN0.TMDF015.UINT8[HL]
    7200 #define RSCAN0TMDF015HH RSCAN0.TMDF015.UINT8[HH]
    7201 #define RSCAN0TMDF115 RSCAN0.TMDF115.UINT32
    7202 #define RSCAN0TMDF115L RSCAN0.TMDF115.UINT16[L]
    7203 #define RSCAN0TMDF115LL RSCAN0.TMDF115.UINT8[LL]
    7204 #define RSCAN0TMDF115LH RSCAN0.TMDF115.UINT8[LH]
    7205 #define RSCAN0TMDF115H RSCAN0.TMDF115.UINT16[H]
    7206 #define RSCAN0TMDF115HL RSCAN0.TMDF115.UINT8[HL]
    7207 #define RSCAN0TMDF115HH RSCAN0.TMDF115.UINT8[HH]
    7208 #define RSCAN0TMID16 RSCAN0.TMID16.UINT32
    7209 #define RSCAN0TMID16L RSCAN0.TMID16.UINT16[L]
    7210 #define RSCAN0TMID16LL RSCAN0.TMID16.UINT8[LL]
    7211 #define RSCAN0TMID16LH RSCAN0.TMID16.UINT8[LH]
    7212 #define RSCAN0TMID16H RSCAN0.TMID16.UINT16[H]
    7213 #define RSCAN0TMID16HL RSCAN0.TMID16.UINT8[HL]
    7214 #define RSCAN0TMID16HH RSCAN0.TMID16.UINT8[HH]
    7215 #define RSCAN0TMPTR16 RSCAN0.TMPTR16.UINT32
    7216 #define RSCAN0TMPTR16L RSCAN0.TMPTR16.UINT16[L]
    7217 #define RSCAN0TMPTR16LL RSCAN0.TMPTR16.UINT8[LL]
    7218 #define RSCAN0TMPTR16LH RSCAN0.TMPTR16.UINT8[LH]
    7219 #define RSCAN0TMPTR16H RSCAN0.TMPTR16.UINT16[H]
    7220 #define RSCAN0TMPTR16HL RSCAN0.TMPTR16.UINT8[HL]
    7221 #define RSCAN0TMPTR16HH RSCAN0.TMPTR16.UINT8[HH]
    7222 #define RSCAN0TMDF016 RSCAN0.TMDF016.UINT32
    7223 #define RSCAN0TMDF016L RSCAN0.TMDF016.UINT16[L]
    7224 #define RSCAN0TMDF016LL RSCAN0.TMDF016.UINT8[LL]
    7225 #define RSCAN0TMDF016LH RSCAN0.TMDF016.UINT8[LH]
    7226 #define RSCAN0TMDF016H RSCAN0.TMDF016.UINT16[H]
    7227 #define RSCAN0TMDF016HL RSCAN0.TMDF016.UINT8[HL]
    7228 #define RSCAN0TMDF016HH RSCAN0.TMDF016.UINT8[HH]
    7229 #define RSCAN0TMDF116 RSCAN0.TMDF116.UINT32
    7230 #define RSCAN0TMDF116L RSCAN0.TMDF116.UINT16[L]
    7231 #define RSCAN0TMDF116LL RSCAN0.TMDF116.UINT8[LL]
    7232 #define RSCAN0TMDF116LH RSCAN0.TMDF116.UINT8[LH]
    7233 #define RSCAN0TMDF116H RSCAN0.TMDF116.UINT16[H]
    7234 #define RSCAN0TMDF116HL RSCAN0.TMDF116.UINT8[HL]
    7235 #define RSCAN0TMDF116HH RSCAN0.TMDF116.UINT8[HH]
    7236 #define RSCAN0TMID17 RSCAN0.TMID17.UINT32
    7237 #define RSCAN0TMID17L RSCAN0.TMID17.UINT16[L]
    7238 #define RSCAN0TMID17LL RSCAN0.TMID17.UINT8[LL]
    7239 #define RSCAN0TMID17LH RSCAN0.TMID17.UINT8[LH]
    7240 #define RSCAN0TMID17H RSCAN0.TMID17.UINT16[H]
    7241 #define RSCAN0TMID17HL RSCAN0.TMID17.UINT8[HL]
    7242 #define RSCAN0TMID17HH RSCAN0.TMID17.UINT8[HH]
    7243 #define RSCAN0TMPTR17 RSCAN0.TMPTR17.UINT32
    7244 #define RSCAN0TMPTR17L RSCAN0.TMPTR17.UINT16[L]
    7245 #define RSCAN0TMPTR17LL RSCAN0.TMPTR17.UINT8[LL]
    7246 #define RSCAN0TMPTR17LH RSCAN0.TMPTR17.UINT8[LH]
    7247 #define RSCAN0TMPTR17H RSCAN0.TMPTR17.UINT16[H]
    7248 #define RSCAN0TMPTR17HL RSCAN0.TMPTR17.UINT8[HL]
    7249 #define RSCAN0TMPTR17HH RSCAN0.TMPTR17.UINT8[HH]
    7250 #define RSCAN0TMDF017 RSCAN0.TMDF017.UINT32
    7251 #define RSCAN0TMDF017L RSCAN0.TMDF017.UINT16[L]
    7252 #define RSCAN0TMDF017LL RSCAN0.TMDF017.UINT8[LL]
    7253 #define RSCAN0TMDF017LH RSCAN0.TMDF017.UINT8[LH]
    7254 #define RSCAN0TMDF017H RSCAN0.TMDF017.UINT16[H]
    7255 #define RSCAN0TMDF017HL RSCAN0.TMDF017.UINT8[HL]
    7256 #define RSCAN0TMDF017HH RSCAN0.TMDF017.UINT8[HH]
    7257 #define RSCAN0TMDF117 RSCAN0.TMDF117.UINT32
    7258 #define RSCAN0TMDF117L RSCAN0.TMDF117.UINT16[L]
    7259 #define RSCAN0TMDF117LL RSCAN0.TMDF117.UINT8[LL]
    7260 #define RSCAN0TMDF117LH RSCAN0.TMDF117.UINT8[LH]
    7261 #define RSCAN0TMDF117H RSCAN0.TMDF117.UINT16[H]
    7262 #define RSCAN0TMDF117HL RSCAN0.TMDF117.UINT8[HL]
    7263 #define RSCAN0TMDF117HH RSCAN0.TMDF117.UINT8[HH]
    7264 #define RSCAN0TMID18 RSCAN0.TMID18.UINT32
    7265 #define RSCAN0TMID18L RSCAN0.TMID18.UINT16[L]
    7266 #define RSCAN0TMID18LL RSCAN0.TMID18.UINT8[LL]
    7267 #define RSCAN0TMID18LH RSCAN0.TMID18.UINT8[LH]
    7268 #define RSCAN0TMID18H RSCAN0.TMID18.UINT16[H]
    7269 #define RSCAN0TMID18HL RSCAN0.TMID18.UINT8[HL]
    7270 #define RSCAN0TMID18HH RSCAN0.TMID18.UINT8[HH]
    7271 #define RSCAN0TMPTR18 RSCAN0.TMPTR18.UINT32
    7272 #define RSCAN0TMPTR18L RSCAN0.TMPTR18.UINT16[L]
    7273 #define RSCAN0TMPTR18LL RSCAN0.TMPTR18.UINT8[LL]
    7274 #define RSCAN0TMPTR18LH RSCAN0.TMPTR18.UINT8[LH]
    7275 #define RSCAN0TMPTR18H RSCAN0.TMPTR18.UINT16[H]
    7276 #define RSCAN0TMPTR18HL RSCAN0.TMPTR18.UINT8[HL]
    7277 #define RSCAN0TMPTR18HH RSCAN0.TMPTR18.UINT8[HH]
    7278 #define RSCAN0TMDF018 RSCAN0.TMDF018.UINT32
    7279 #define RSCAN0TMDF018L RSCAN0.TMDF018.UINT16[L]
    7280 #define RSCAN0TMDF018LL RSCAN0.TMDF018.UINT8[LL]
    7281 #define RSCAN0TMDF018LH RSCAN0.TMDF018.UINT8[LH]
    7282 #define RSCAN0TMDF018H RSCAN0.TMDF018.UINT16[H]
    7283 #define RSCAN0TMDF018HL RSCAN0.TMDF018.UINT8[HL]
    7284 #define RSCAN0TMDF018HH RSCAN0.TMDF018.UINT8[HH]
    7285 #define RSCAN0TMDF118 RSCAN0.TMDF118.UINT32
    7286 #define RSCAN0TMDF118L RSCAN0.TMDF118.UINT16[L]
    7287 #define RSCAN0TMDF118LL RSCAN0.TMDF118.UINT8[LL]
    7288 #define RSCAN0TMDF118LH RSCAN0.TMDF118.UINT8[LH]
    7289 #define RSCAN0TMDF118H RSCAN0.TMDF118.UINT16[H]
    7290 #define RSCAN0TMDF118HL RSCAN0.TMDF118.UINT8[HL]
    7291 #define RSCAN0TMDF118HH RSCAN0.TMDF118.UINT8[HH]
    7292 #define RSCAN0TMID19 RSCAN0.TMID19.UINT32
    7293 #define RSCAN0TMID19L RSCAN0.TMID19.UINT16[L]
    7294 #define RSCAN0TMID19LL RSCAN0.TMID19.UINT8[LL]
    7295 #define RSCAN0TMID19LH RSCAN0.TMID19.UINT8[LH]
    7296 #define RSCAN0TMID19H RSCAN0.TMID19.UINT16[H]
    7297 #define RSCAN0TMID19HL RSCAN0.TMID19.UINT8[HL]
    7298 #define RSCAN0TMID19HH RSCAN0.TMID19.UINT8[HH]
    7299 #define RSCAN0TMPTR19 RSCAN0.TMPTR19.UINT32
    7300 #define RSCAN0TMPTR19L RSCAN0.TMPTR19.UINT16[L]
    7301 #define RSCAN0TMPTR19LL RSCAN0.TMPTR19.UINT8[LL]
    7302 #define RSCAN0TMPTR19LH RSCAN0.TMPTR19.UINT8[LH]
    7303 #define RSCAN0TMPTR19H RSCAN0.TMPTR19.UINT16[H]
    7304 #define RSCAN0TMPTR19HL RSCAN0.TMPTR19.UINT8[HL]
    7305 #define RSCAN0TMPTR19HH RSCAN0.TMPTR19.UINT8[HH]
    7306 #define RSCAN0TMDF019 RSCAN0.TMDF019.UINT32
    7307 #define RSCAN0TMDF019L RSCAN0.TMDF019.UINT16[L]
    7308 #define RSCAN0TMDF019LL RSCAN0.TMDF019.UINT8[LL]
    7309 #define RSCAN0TMDF019LH RSCAN0.TMDF019.UINT8[LH]
    7310 #define RSCAN0TMDF019H RSCAN0.TMDF019.UINT16[H]
    7311 #define RSCAN0TMDF019HL RSCAN0.TMDF019.UINT8[HL]
    7312 #define RSCAN0TMDF019HH RSCAN0.TMDF019.UINT8[HH]
    7313 #define RSCAN0TMDF119 RSCAN0.TMDF119.UINT32
    7314 #define RSCAN0TMDF119L RSCAN0.TMDF119.UINT16[L]
    7315 #define RSCAN0TMDF119LL RSCAN0.TMDF119.UINT8[LL]
    7316 #define RSCAN0TMDF119LH RSCAN0.TMDF119.UINT8[LH]
    7317 #define RSCAN0TMDF119H RSCAN0.TMDF119.UINT16[H]
    7318 #define RSCAN0TMDF119HL RSCAN0.TMDF119.UINT8[HL]
    7319 #define RSCAN0TMDF119HH RSCAN0.TMDF119.UINT8[HH]
    7320 #define RSCAN0TMID20 RSCAN0.TMID20.UINT32
    7321 #define RSCAN0TMID20L RSCAN0.TMID20.UINT16[L]
    7322 #define RSCAN0TMID20LL RSCAN0.TMID20.UINT8[LL]
    7323 #define RSCAN0TMID20LH RSCAN0.TMID20.UINT8[LH]
    7324 #define RSCAN0TMID20H RSCAN0.TMID20.UINT16[H]
    7325 #define RSCAN0TMID20HL RSCAN0.TMID20.UINT8[HL]
    7326 #define RSCAN0TMID20HH RSCAN0.TMID20.UINT8[HH]
    7327 #define RSCAN0TMPTR20 RSCAN0.TMPTR20.UINT32
    7328 #define RSCAN0TMPTR20L RSCAN0.TMPTR20.UINT16[L]
    7329 #define RSCAN0TMPTR20LL RSCAN0.TMPTR20.UINT8[LL]
    7330 #define RSCAN0TMPTR20LH RSCAN0.TMPTR20.UINT8[LH]
    7331 #define RSCAN0TMPTR20H RSCAN0.TMPTR20.UINT16[H]
    7332 #define RSCAN0TMPTR20HL RSCAN0.TMPTR20.UINT8[HL]
    7333 #define RSCAN0TMPTR20HH RSCAN0.TMPTR20.UINT8[HH]
    7334 #define RSCAN0TMDF020 RSCAN0.TMDF020.UINT32
    7335 #define RSCAN0TMDF020L RSCAN0.TMDF020.UINT16[L]
    7336 #define RSCAN0TMDF020LL RSCAN0.TMDF020.UINT8[LL]
    7337 #define RSCAN0TMDF020LH RSCAN0.TMDF020.UINT8[LH]
    7338 #define RSCAN0TMDF020H RSCAN0.TMDF020.UINT16[H]
    7339 #define RSCAN0TMDF020HL RSCAN0.TMDF020.UINT8[HL]
    7340 #define RSCAN0TMDF020HH RSCAN0.TMDF020.UINT8[HH]
    7341 #define RSCAN0TMDF120 RSCAN0.TMDF120.UINT32
    7342 #define RSCAN0TMDF120L RSCAN0.TMDF120.UINT16[L]
    7343 #define RSCAN0TMDF120LL RSCAN0.TMDF120.UINT8[LL]
    7344 #define RSCAN0TMDF120LH RSCAN0.TMDF120.UINT8[LH]
    7345 #define RSCAN0TMDF120H RSCAN0.TMDF120.UINT16[H]
    7346 #define RSCAN0TMDF120HL RSCAN0.TMDF120.UINT8[HL]
    7347 #define RSCAN0TMDF120HH RSCAN0.TMDF120.UINT8[HH]
    7348 #define RSCAN0TMID21 RSCAN0.TMID21.UINT32
    7349 #define RSCAN0TMID21L RSCAN0.TMID21.UINT16[L]
    7350 #define RSCAN0TMID21LL RSCAN0.TMID21.UINT8[LL]
    7351 #define RSCAN0TMID21LH RSCAN0.TMID21.UINT8[LH]
    7352 #define RSCAN0TMID21H RSCAN0.TMID21.UINT16[H]
    7353 #define RSCAN0TMID21HL RSCAN0.TMID21.UINT8[HL]
    7354 #define RSCAN0TMID21HH RSCAN0.TMID21.UINT8[HH]
    7355 #define RSCAN0TMPTR21 RSCAN0.TMPTR21.UINT32
    7356 #define RSCAN0TMPTR21L RSCAN0.TMPTR21.UINT16[L]
    7357 #define RSCAN0TMPTR21LL RSCAN0.TMPTR21.UINT8[LL]
    7358 #define RSCAN0TMPTR21LH RSCAN0.TMPTR21.UINT8[LH]
    7359 #define RSCAN0TMPTR21H RSCAN0.TMPTR21.UINT16[H]
    7360 #define RSCAN0TMPTR21HL RSCAN0.TMPTR21.UINT8[HL]
    7361 #define RSCAN0TMPTR21HH RSCAN0.TMPTR21.UINT8[HH]
    7362 #define RSCAN0TMDF021 RSCAN0.TMDF021.UINT32
    7363 #define RSCAN0TMDF021L RSCAN0.TMDF021.UINT16[L]
    7364 #define RSCAN0TMDF021LL RSCAN0.TMDF021.UINT8[LL]
    7365 #define RSCAN0TMDF021LH RSCAN0.TMDF021.UINT8[LH]
    7366 #define RSCAN0TMDF021H RSCAN0.TMDF021.UINT16[H]
    7367 #define RSCAN0TMDF021HL RSCAN0.TMDF021.UINT8[HL]
    7368 #define RSCAN0TMDF021HH RSCAN0.TMDF021.UINT8[HH]
    7369 #define RSCAN0TMDF121 RSCAN0.TMDF121.UINT32
    7370 #define RSCAN0TMDF121L RSCAN0.TMDF121.UINT16[L]
    7371 #define RSCAN0TMDF121LL RSCAN0.TMDF121.UINT8[LL]
    7372 #define RSCAN0TMDF121LH RSCAN0.TMDF121.UINT8[LH]
    7373 #define RSCAN0TMDF121H RSCAN0.TMDF121.UINT16[H]
    7374 #define RSCAN0TMDF121HL RSCAN0.TMDF121.UINT8[HL]
    7375 #define RSCAN0TMDF121HH RSCAN0.TMDF121.UINT8[HH]
    7376 #define RSCAN0TMID22 RSCAN0.TMID22.UINT32
    7377 #define RSCAN0TMID22L RSCAN0.TMID22.UINT16[L]
    7378 #define RSCAN0TMID22LL RSCAN0.TMID22.UINT8[LL]
    7379 #define RSCAN0TMID22LH RSCAN0.TMID22.UINT8[LH]
    7380 #define RSCAN0TMID22H RSCAN0.TMID22.UINT16[H]
    7381 #define RSCAN0TMID22HL RSCAN0.TMID22.UINT8[HL]
    7382 #define RSCAN0TMID22HH RSCAN0.TMID22.UINT8[HH]
    7383 #define RSCAN0TMPTR22 RSCAN0.TMPTR22.UINT32
    7384 #define RSCAN0TMPTR22L RSCAN0.TMPTR22.UINT16[L]
    7385 #define RSCAN0TMPTR22LL RSCAN0.TMPTR22.UINT8[LL]
    7386 #define RSCAN0TMPTR22LH RSCAN0.TMPTR22.UINT8[LH]
    7387 #define RSCAN0TMPTR22H RSCAN0.TMPTR22.UINT16[H]
    7388 #define RSCAN0TMPTR22HL RSCAN0.TMPTR22.UINT8[HL]
    7389 #define RSCAN0TMPTR22HH RSCAN0.TMPTR22.UINT8[HH]
    7390 #define RSCAN0TMDF022 RSCAN0.TMDF022.UINT32
    7391 #define RSCAN0TMDF022L RSCAN0.TMDF022.UINT16[L]
    7392 #define RSCAN0TMDF022LL RSCAN0.TMDF022.UINT8[LL]
    7393 #define RSCAN0TMDF022LH RSCAN0.TMDF022.UINT8[LH]
    7394 #define RSCAN0TMDF022H RSCAN0.TMDF022.UINT16[H]
    7395 #define RSCAN0TMDF022HL RSCAN0.TMDF022.UINT8[HL]
    7396 #define RSCAN0TMDF022HH RSCAN0.TMDF022.UINT8[HH]
    7397 #define RSCAN0TMDF122 RSCAN0.TMDF122.UINT32
    7398 #define RSCAN0TMDF122L RSCAN0.TMDF122.UINT16[L]
    7399 #define RSCAN0TMDF122LL RSCAN0.TMDF122.UINT8[LL]
    7400 #define RSCAN0TMDF122LH RSCAN0.TMDF122.UINT8[LH]
    7401 #define RSCAN0TMDF122H RSCAN0.TMDF122.UINT16[H]
    7402 #define RSCAN0TMDF122HL RSCAN0.TMDF122.UINT8[HL]
    7403 #define RSCAN0TMDF122HH RSCAN0.TMDF122.UINT8[HH]
    7404 #define RSCAN0TMID23 RSCAN0.TMID23.UINT32
    7405 #define RSCAN0TMID23L RSCAN0.TMID23.UINT16[L]
    7406 #define RSCAN0TMID23LL RSCAN0.TMID23.UINT8[LL]
    7407 #define RSCAN0TMID23LH RSCAN0.TMID23.UINT8[LH]
    7408 #define RSCAN0TMID23H RSCAN0.TMID23.UINT16[H]
    7409 #define RSCAN0TMID23HL RSCAN0.TMID23.UINT8[HL]
    7410 #define RSCAN0TMID23HH RSCAN0.TMID23.UINT8[HH]
    7411 #define RSCAN0TMPTR23 RSCAN0.TMPTR23.UINT32
    7412 #define RSCAN0TMPTR23L RSCAN0.TMPTR23.UINT16[L]
    7413 #define RSCAN0TMPTR23LL RSCAN0.TMPTR23.UINT8[LL]
    7414 #define RSCAN0TMPTR23LH RSCAN0.TMPTR23.UINT8[LH]
    7415 #define RSCAN0TMPTR23H RSCAN0.TMPTR23.UINT16[H]
    7416 #define RSCAN0TMPTR23HL RSCAN0.TMPTR23.UINT8[HL]
    7417 #define RSCAN0TMPTR23HH RSCAN0.TMPTR23.UINT8[HH]
    7418 #define RSCAN0TMDF023 RSCAN0.TMDF023.UINT32
    7419 #define RSCAN0TMDF023L RSCAN0.TMDF023.UINT16[L]
    7420 #define RSCAN0TMDF023LL RSCAN0.TMDF023.UINT8[LL]
    7421 #define RSCAN0TMDF023LH RSCAN0.TMDF023.UINT8[LH]
    7422 #define RSCAN0TMDF023H RSCAN0.TMDF023.UINT16[H]
    7423 #define RSCAN0TMDF023HL RSCAN0.TMDF023.UINT8[HL]
    7424 #define RSCAN0TMDF023HH RSCAN0.TMDF023.UINT8[HH]
    7425 #define RSCAN0TMDF123 RSCAN0.TMDF123.UINT32
    7426 #define RSCAN0TMDF123L RSCAN0.TMDF123.UINT16[L]
    7427 #define RSCAN0TMDF123LL RSCAN0.TMDF123.UINT8[LL]
    7428 #define RSCAN0TMDF123LH RSCAN0.TMDF123.UINT8[LH]
    7429 #define RSCAN0TMDF123H RSCAN0.TMDF123.UINT16[H]
    7430 #define RSCAN0TMDF123HL RSCAN0.TMDF123.UINT8[HL]
    7431 #define RSCAN0TMDF123HH RSCAN0.TMDF123.UINT8[HH]
    7432 #define RSCAN0TMID24 RSCAN0.TMID24.UINT32
    7433 #define RSCAN0TMID24L RSCAN0.TMID24.UINT16[L]
    7434 #define RSCAN0TMID24LL RSCAN0.TMID24.UINT8[LL]
    7435 #define RSCAN0TMID24LH RSCAN0.TMID24.UINT8[LH]
    7436 #define RSCAN0TMID24H RSCAN0.TMID24.UINT16[H]
    7437 #define RSCAN0TMID24HL RSCAN0.TMID24.UINT8[HL]
    7438 #define RSCAN0TMID24HH RSCAN0.TMID24.UINT8[HH]
    7439 #define RSCAN0TMPTR24 RSCAN0.TMPTR24.UINT32
    7440 #define RSCAN0TMPTR24L RSCAN0.TMPTR24.UINT16[L]
    7441 #define RSCAN0TMPTR24LL RSCAN0.TMPTR24.UINT8[LL]
    7442 #define RSCAN0TMPTR24LH RSCAN0.TMPTR24.UINT8[LH]
    7443 #define RSCAN0TMPTR24H RSCAN0.TMPTR24.UINT16[H]
    7444 #define RSCAN0TMPTR24HL RSCAN0.TMPTR24.UINT8[HL]
    7445 #define RSCAN0TMPTR24HH RSCAN0.TMPTR24.UINT8[HH]
    7446 #define RSCAN0TMDF024 RSCAN0.TMDF024.UINT32
    7447 #define RSCAN0TMDF024L RSCAN0.TMDF024.UINT16[L]
    7448 #define RSCAN0TMDF024LL RSCAN0.TMDF024.UINT8[LL]
    7449 #define RSCAN0TMDF024LH RSCAN0.TMDF024.UINT8[LH]
    7450 #define RSCAN0TMDF024H RSCAN0.TMDF024.UINT16[H]
    7451 #define RSCAN0TMDF024HL RSCAN0.TMDF024.UINT8[HL]
    7452 #define RSCAN0TMDF024HH RSCAN0.TMDF024.UINT8[HH]
    7453 #define RSCAN0TMDF124 RSCAN0.TMDF124.UINT32
    7454 #define RSCAN0TMDF124L RSCAN0.TMDF124.UINT16[L]
    7455 #define RSCAN0TMDF124LL RSCAN0.TMDF124.UINT8[LL]
    7456 #define RSCAN0TMDF124LH RSCAN0.TMDF124.UINT8[LH]
    7457 #define RSCAN0TMDF124H RSCAN0.TMDF124.UINT16[H]
    7458 #define RSCAN0TMDF124HL RSCAN0.TMDF124.UINT8[HL]
    7459 #define RSCAN0TMDF124HH RSCAN0.TMDF124.UINT8[HH]
    7460 #define RSCAN0TMID25 RSCAN0.TMID25.UINT32
    7461 #define RSCAN0TMID25L RSCAN0.TMID25.UINT16[L]
    7462 #define RSCAN0TMID25LL RSCAN0.TMID25.UINT8[LL]
    7463 #define RSCAN0TMID25LH RSCAN0.TMID25.UINT8[LH]
    7464 #define RSCAN0TMID25H RSCAN0.TMID25.UINT16[H]
    7465 #define RSCAN0TMID25HL RSCAN0.TMID25.UINT8[HL]
    7466 #define RSCAN0TMID25HH RSCAN0.TMID25.UINT8[HH]
    7467 #define RSCAN0TMPTR25 RSCAN0.TMPTR25.UINT32
    7468 #define RSCAN0TMPTR25L RSCAN0.TMPTR25.UINT16[L]
    7469 #define RSCAN0TMPTR25LL RSCAN0.TMPTR25.UINT8[LL]
    7470 #define RSCAN0TMPTR25LH RSCAN0.TMPTR25.UINT8[LH]
    7471 #define RSCAN0TMPTR25H RSCAN0.TMPTR25.UINT16[H]
    7472 #define RSCAN0TMPTR25HL RSCAN0.TMPTR25.UINT8[HL]
    7473 #define RSCAN0TMPTR25HH RSCAN0.TMPTR25.UINT8[HH]
    7474 #define RSCAN0TMDF025 RSCAN0.TMDF025.UINT32
    7475 #define RSCAN0TMDF025L RSCAN0.TMDF025.UINT16[L]
    7476 #define RSCAN0TMDF025LL RSCAN0.TMDF025.UINT8[LL]
    7477 #define RSCAN0TMDF025LH RSCAN0.TMDF025.UINT8[LH]
    7478 #define RSCAN0TMDF025H RSCAN0.TMDF025.UINT16[H]
    7479 #define RSCAN0TMDF025HL RSCAN0.TMDF025.UINT8[HL]
    7480 #define RSCAN0TMDF025HH RSCAN0.TMDF025.UINT8[HH]
    7481 #define RSCAN0TMDF125 RSCAN0.TMDF125.UINT32
    7482 #define RSCAN0TMDF125L RSCAN0.TMDF125.UINT16[L]
    7483 #define RSCAN0TMDF125LL RSCAN0.TMDF125.UINT8[LL]
    7484 #define RSCAN0TMDF125LH RSCAN0.TMDF125.UINT8[LH]
    7485 #define RSCAN0TMDF125H RSCAN0.TMDF125.UINT16[H]
    7486 #define RSCAN0TMDF125HL RSCAN0.TMDF125.UINT8[HL]
    7487 #define RSCAN0TMDF125HH RSCAN0.TMDF125.UINT8[HH]
    7488 #define RSCAN0TMID26 RSCAN0.TMID26.UINT32
    7489 #define RSCAN0TMID26L RSCAN0.TMID26.UINT16[L]
    7490 #define RSCAN0TMID26LL RSCAN0.TMID26.UINT8[LL]
    7491 #define RSCAN0TMID26LH RSCAN0.TMID26.UINT8[LH]
    7492 #define RSCAN0TMID26H RSCAN0.TMID26.UINT16[H]
    7493 #define RSCAN0TMID26HL RSCAN0.TMID26.UINT8[HL]
    7494 #define RSCAN0TMID26HH RSCAN0.TMID26.UINT8[HH]
    7495 #define RSCAN0TMPTR26 RSCAN0.TMPTR26.UINT32
    7496 #define RSCAN0TMPTR26L RSCAN0.TMPTR26.UINT16[L]
    7497 #define RSCAN0TMPTR26LL RSCAN0.TMPTR26.UINT8[LL]
    7498 #define RSCAN0TMPTR26LH RSCAN0.TMPTR26.UINT8[LH]
    7499 #define RSCAN0TMPTR26H RSCAN0.TMPTR26.UINT16[H]
    7500 #define RSCAN0TMPTR26HL RSCAN0.TMPTR26.UINT8[HL]
    7501 #define RSCAN0TMPTR26HH RSCAN0.TMPTR26.UINT8[HH]
    7502 #define RSCAN0TMDF026 RSCAN0.TMDF026.UINT32
    7503 #define RSCAN0TMDF026L RSCAN0.TMDF026.UINT16[L]
    7504 #define RSCAN0TMDF026LL RSCAN0.TMDF026.UINT8[LL]
    7505 #define RSCAN0TMDF026LH RSCAN0.TMDF026.UINT8[LH]
    7506 #define RSCAN0TMDF026H RSCAN0.TMDF026.UINT16[H]
    7507 #define RSCAN0TMDF026HL RSCAN0.TMDF026.UINT8[HL]
    7508 #define RSCAN0TMDF026HH RSCAN0.TMDF026.UINT8[HH]
    7509 #define RSCAN0TMDF126 RSCAN0.TMDF126.UINT32
    7510 #define RSCAN0TMDF126L RSCAN0.TMDF126.UINT16[L]
    7511 #define RSCAN0TMDF126LL RSCAN0.TMDF126.UINT8[LL]
    7512 #define RSCAN0TMDF126LH RSCAN0.TMDF126.UINT8[LH]
    7513 #define RSCAN0TMDF126H RSCAN0.TMDF126.UINT16[H]
    7514 #define RSCAN0TMDF126HL RSCAN0.TMDF126.UINT8[HL]
    7515 #define RSCAN0TMDF126HH RSCAN0.TMDF126.UINT8[HH]
    7516 #define RSCAN0TMID27 RSCAN0.TMID27.UINT32
    7517 #define RSCAN0TMID27L RSCAN0.TMID27.UINT16[L]
    7518 #define RSCAN0TMID27LL RSCAN0.TMID27.UINT8[LL]
    7519 #define RSCAN0TMID27LH RSCAN0.TMID27.UINT8[LH]
    7520 #define RSCAN0TMID27H RSCAN0.TMID27.UINT16[H]
    7521 #define RSCAN0TMID27HL RSCAN0.TMID27.UINT8[HL]
    7522 #define RSCAN0TMID27HH RSCAN0.TMID27.UINT8[HH]
    7523 #define RSCAN0TMPTR27 RSCAN0.TMPTR27.UINT32
    7524 #define RSCAN0TMPTR27L RSCAN0.TMPTR27.UINT16[L]
    7525 #define RSCAN0TMPTR27LL RSCAN0.TMPTR27.UINT8[LL]
    7526 #define RSCAN0TMPTR27LH RSCAN0.TMPTR27.UINT8[LH]
    7527 #define RSCAN0TMPTR27H RSCAN0.TMPTR27.UINT16[H]
    7528 #define RSCAN0TMPTR27HL RSCAN0.TMPTR27.UINT8[HL]
    7529 #define RSCAN0TMPTR27HH RSCAN0.TMPTR27.UINT8[HH]
    7530 #define RSCAN0TMDF027 RSCAN0.TMDF027.UINT32
    7531 #define RSCAN0TMDF027L RSCAN0.TMDF027.UINT16[L]
    7532 #define RSCAN0TMDF027LL RSCAN0.TMDF027.UINT8[LL]
    7533 #define RSCAN0TMDF027LH RSCAN0.TMDF027.UINT8[LH]
    7534 #define RSCAN0TMDF027H RSCAN0.TMDF027.UINT16[H]
    7535 #define RSCAN0TMDF027HL RSCAN0.TMDF027.UINT8[HL]
    7536 #define RSCAN0TMDF027HH RSCAN0.TMDF027.UINT8[HH]
    7537 #define RSCAN0TMDF127 RSCAN0.TMDF127.UINT32
    7538 #define RSCAN0TMDF127L RSCAN0.TMDF127.UINT16[L]
    7539 #define RSCAN0TMDF127LL RSCAN0.TMDF127.UINT8[LL]
    7540 #define RSCAN0TMDF127LH RSCAN0.TMDF127.UINT8[LH]
    7541 #define RSCAN0TMDF127H RSCAN0.TMDF127.UINT16[H]
    7542 #define RSCAN0TMDF127HL RSCAN0.TMDF127.UINT8[HL]
    7543 #define RSCAN0TMDF127HH RSCAN0.TMDF127.UINT8[HH]
    7544 #define RSCAN0TMID28 RSCAN0.TMID28.UINT32
    7545 #define RSCAN0TMID28L RSCAN0.TMID28.UINT16[L]
    7546 #define RSCAN0TMID28LL RSCAN0.TMID28.UINT8[LL]
    7547 #define RSCAN0TMID28LH RSCAN0.TMID28.UINT8[LH]
    7548 #define RSCAN0TMID28H RSCAN0.TMID28.UINT16[H]
    7549 #define RSCAN0TMID28HL RSCAN0.TMID28.UINT8[HL]
    7550 #define RSCAN0TMID28HH RSCAN0.TMID28.UINT8[HH]
    7551 #define RSCAN0TMPTR28 RSCAN0.TMPTR28.UINT32
    7552 #define RSCAN0TMPTR28L RSCAN0.TMPTR28.UINT16[L]
    7553 #define RSCAN0TMPTR28LL RSCAN0.TMPTR28.UINT8[LL]
    7554 #define RSCAN0TMPTR28LH RSCAN0.TMPTR28.UINT8[LH]
    7555 #define RSCAN0TMPTR28H RSCAN0.TMPTR28.UINT16[H]
    7556 #define RSCAN0TMPTR28HL RSCAN0.TMPTR28.UINT8[HL]
    7557 #define RSCAN0TMPTR28HH RSCAN0.TMPTR28.UINT8[HH]
    7558 #define RSCAN0TMDF028 RSCAN0.TMDF028.UINT32
    7559 #define RSCAN0TMDF028L RSCAN0.TMDF028.UINT16[L]
    7560 #define RSCAN0TMDF028LL RSCAN0.TMDF028.UINT8[LL]
    7561 #define RSCAN0TMDF028LH RSCAN0.TMDF028.UINT8[LH]
    7562 #define RSCAN0TMDF028H RSCAN0.TMDF028.UINT16[H]
    7563 #define RSCAN0TMDF028HL RSCAN0.TMDF028.UINT8[HL]
    7564 #define RSCAN0TMDF028HH RSCAN0.TMDF028.UINT8[HH]
    7565 #define RSCAN0TMDF128 RSCAN0.TMDF128.UINT32
    7566 #define RSCAN0TMDF128L RSCAN0.TMDF128.UINT16[L]
    7567 #define RSCAN0TMDF128LL RSCAN0.TMDF128.UINT8[LL]
    7568 #define RSCAN0TMDF128LH RSCAN0.TMDF128.UINT8[LH]
    7569 #define RSCAN0TMDF128H RSCAN0.TMDF128.UINT16[H]
    7570 #define RSCAN0TMDF128HL RSCAN0.TMDF128.UINT8[HL]
    7571 #define RSCAN0TMDF128HH RSCAN0.TMDF128.UINT8[HH]
    7572 #define RSCAN0TMID29 RSCAN0.TMID29.UINT32
    7573 #define RSCAN0TMID29L RSCAN0.TMID29.UINT16[L]
    7574 #define RSCAN0TMID29LL RSCAN0.TMID29.UINT8[LL]
    7575 #define RSCAN0TMID29LH RSCAN0.TMID29.UINT8[LH]
    7576 #define RSCAN0TMID29H RSCAN0.TMID29.UINT16[H]
    7577 #define RSCAN0TMID29HL RSCAN0.TMID29.UINT8[HL]
    7578 #define RSCAN0TMID29HH RSCAN0.TMID29.UINT8[HH]
    7579 #define RSCAN0TMPTR29 RSCAN0.TMPTR29.UINT32
    7580 #define RSCAN0TMPTR29L RSCAN0.TMPTR29.UINT16[L]
    7581 #define RSCAN0TMPTR29LL RSCAN0.TMPTR29.UINT8[LL]
    7582 #define RSCAN0TMPTR29LH RSCAN0.TMPTR29.UINT8[LH]
    7583 #define RSCAN0TMPTR29H RSCAN0.TMPTR29.UINT16[H]
    7584 #define RSCAN0TMPTR29HL RSCAN0.TMPTR29.UINT8[HL]
    7585 #define RSCAN0TMPTR29HH RSCAN0.TMPTR29.UINT8[HH]
    7586 #define RSCAN0TMDF029 RSCAN0.TMDF029.UINT32
    7587 #define RSCAN0TMDF029L RSCAN0.TMDF029.UINT16[L]
    7588 #define RSCAN0TMDF029LL RSCAN0.TMDF029.UINT8[LL]
    7589 #define RSCAN0TMDF029LH RSCAN0.TMDF029.UINT8[LH]
    7590 #define RSCAN0TMDF029H RSCAN0.TMDF029.UINT16[H]
    7591 #define RSCAN0TMDF029HL RSCAN0.TMDF029.UINT8[HL]
    7592 #define RSCAN0TMDF029HH RSCAN0.TMDF029.UINT8[HH]
    7593 #define RSCAN0TMDF129 RSCAN0.TMDF129.UINT32
    7594 #define RSCAN0TMDF129L RSCAN0.TMDF129.UINT16[L]
    7595 #define RSCAN0TMDF129LL RSCAN0.TMDF129.UINT8[LL]
    7596 #define RSCAN0TMDF129LH RSCAN0.TMDF129.UINT8[LH]
    7597 #define RSCAN0TMDF129H RSCAN0.TMDF129.UINT16[H]
    7598 #define RSCAN0TMDF129HL RSCAN0.TMDF129.UINT8[HL]
    7599 #define RSCAN0TMDF129HH RSCAN0.TMDF129.UINT8[HH]
    7600 #define RSCAN0TMID30 RSCAN0.TMID30.UINT32
    7601 #define RSCAN0TMID30L RSCAN0.TMID30.UINT16[L]
    7602 #define RSCAN0TMID30LL RSCAN0.TMID30.UINT8[LL]
    7603 #define RSCAN0TMID30LH RSCAN0.TMID30.UINT8[LH]
    7604 #define RSCAN0TMID30H RSCAN0.TMID30.UINT16[H]
    7605 #define RSCAN0TMID30HL RSCAN0.TMID30.UINT8[HL]
    7606 #define RSCAN0TMID30HH RSCAN0.TMID30.UINT8[HH]
    7607 #define RSCAN0TMPTR30 RSCAN0.TMPTR30.UINT32
    7608 #define RSCAN0TMPTR30L RSCAN0.TMPTR30.UINT16[L]
    7609 #define RSCAN0TMPTR30LL RSCAN0.TMPTR30.UINT8[LL]
    7610 #define RSCAN0TMPTR30LH RSCAN0.TMPTR30.UINT8[LH]
    7611 #define RSCAN0TMPTR30H RSCAN0.TMPTR30.UINT16[H]
    7612 #define RSCAN0TMPTR30HL RSCAN0.TMPTR30.UINT8[HL]
    7613 #define RSCAN0TMPTR30HH RSCAN0.TMPTR30.UINT8[HH]
    7614 #define RSCAN0TMDF030 RSCAN0.TMDF030.UINT32
    7615 #define RSCAN0TMDF030L RSCAN0.TMDF030.UINT16[L]
    7616 #define RSCAN0TMDF030LL RSCAN0.TMDF030.UINT8[LL]
    7617 #define RSCAN0TMDF030LH RSCAN0.TMDF030.UINT8[LH]
    7618 #define RSCAN0TMDF030H RSCAN0.TMDF030.UINT16[H]
    7619 #define RSCAN0TMDF030HL RSCAN0.TMDF030.UINT8[HL]
    7620 #define RSCAN0TMDF030HH RSCAN0.TMDF030.UINT8[HH]
    7621 #define RSCAN0TMDF130 RSCAN0.TMDF130.UINT32
    7622 #define RSCAN0TMDF130L RSCAN0.TMDF130.UINT16[L]
    7623 #define RSCAN0TMDF130LL RSCAN0.TMDF130.UINT8[LL]
    7624 #define RSCAN0TMDF130LH RSCAN0.TMDF130.UINT8[LH]
    7625 #define RSCAN0TMDF130H RSCAN0.TMDF130.UINT16[H]
    7626 #define RSCAN0TMDF130HL RSCAN0.TMDF130.UINT8[HL]
    7627 #define RSCAN0TMDF130HH RSCAN0.TMDF130.UINT8[HH]
    7628 #define RSCAN0TMID31 RSCAN0.TMID31.UINT32
    7629 #define RSCAN0TMID31L RSCAN0.TMID31.UINT16[L]
    7630 #define RSCAN0TMID31LL RSCAN0.TMID31.UINT8[LL]
    7631 #define RSCAN0TMID31LH RSCAN0.TMID31.UINT8[LH]
    7632 #define RSCAN0TMID31H RSCAN0.TMID31.UINT16[H]
    7633 #define RSCAN0TMID31HL RSCAN0.TMID31.UINT8[HL]
    7634 #define RSCAN0TMID31HH RSCAN0.TMID31.UINT8[HH]
    7635 #define RSCAN0TMPTR31 RSCAN0.TMPTR31.UINT32
    7636 #define RSCAN0TMPTR31L RSCAN0.TMPTR31.UINT16[L]
    7637 #define RSCAN0TMPTR31LL RSCAN0.TMPTR31.UINT8[LL]
    7638 #define RSCAN0TMPTR31LH RSCAN0.TMPTR31.UINT8[LH]
    7639 #define RSCAN0TMPTR31H RSCAN0.TMPTR31.UINT16[H]
    7640 #define RSCAN0TMPTR31HL RSCAN0.TMPTR31.UINT8[HL]
    7641 #define RSCAN0TMPTR31HH RSCAN0.TMPTR31.UINT8[HH]
    7642 #define RSCAN0TMDF031 RSCAN0.TMDF031.UINT32
    7643 #define RSCAN0TMDF031L RSCAN0.TMDF031.UINT16[L]
    7644 #define RSCAN0TMDF031LL RSCAN0.TMDF031.UINT8[LL]
    7645 #define RSCAN0TMDF031LH RSCAN0.TMDF031.UINT8[LH]
    7646 #define RSCAN0TMDF031H RSCAN0.TMDF031.UINT16[H]
    7647 #define RSCAN0TMDF031HL RSCAN0.TMDF031.UINT8[HL]
    7648 #define RSCAN0TMDF031HH RSCAN0.TMDF031.UINT8[HH]
    7649 #define RSCAN0TMDF131 RSCAN0.TMDF131.UINT32
    7650 #define RSCAN0TMDF131L RSCAN0.TMDF131.UINT16[L]
    7651 #define RSCAN0TMDF131LL RSCAN0.TMDF131.UINT8[LL]
    7652 #define RSCAN0TMDF131LH RSCAN0.TMDF131.UINT8[LH]
    7653 #define RSCAN0TMDF131H RSCAN0.TMDF131.UINT16[H]
    7654 #define RSCAN0TMDF131HL RSCAN0.TMDF131.UINT8[HL]
    7655 #define RSCAN0TMDF131HH RSCAN0.TMDF131.UINT8[HH]
    7656 #define RSCAN0TMID32 RSCAN0.TMID32.UINT32
    7657 #define RSCAN0TMID32L RSCAN0.TMID32.UINT16[L]
    7658 #define RSCAN0TMID32LL RSCAN0.TMID32.UINT8[LL]
    7659 #define RSCAN0TMID32LH RSCAN0.TMID32.UINT8[LH]
    7660 #define RSCAN0TMID32H RSCAN0.TMID32.UINT16[H]
    7661 #define RSCAN0TMID32HL RSCAN0.TMID32.UINT8[HL]
    7662 #define RSCAN0TMID32HH RSCAN0.TMID32.UINT8[HH]
    7663 #define RSCAN0TMPTR32 RSCAN0.TMPTR32.UINT32
    7664 #define RSCAN0TMPTR32L RSCAN0.TMPTR32.UINT16[L]
    7665 #define RSCAN0TMPTR32LL RSCAN0.TMPTR32.UINT8[LL]
    7666 #define RSCAN0TMPTR32LH RSCAN0.TMPTR32.UINT8[LH]
    7667 #define RSCAN0TMPTR32H RSCAN0.TMPTR32.UINT16[H]
    7668 #define RSCAN0TMPTR32HL RSCAN0.TMPTR32.UINT8[HL]
    7669 #define RSCAN0TMPTR32HH RSCAN0.TMPTR32.UINT8[HH]
    7670 #define RSCAN0TMDF032 RSCAN0.TMDF032.UINT32
    7671 #define RSCAN0TMDF032L RSCAN0.TMDF032.UINT16[L]
    7672 #define RSCAN0TMDF032LL RSCAN0.TMDF032.UINT8[LL]
    7673 #define RSCAN0TMDF032LH RSCAN0.TMDF032.UINT8[LH]
    7674 #define RSCAN0TMDF032H RSCAN0.TMDF032.UINT16[H]
    7675 #define RSCAN0TMDF032HL RSCAN0.TMDF032.UINT8[HL]
    7676 #define RSCAN0TMDF032HH RSCAN0.TMDF032.UINT8[HH]
    7677 #define RSCAN0TMDF132 RSCAN0.TMDF132.UINT32
    7678 #define RSCAN0TMDF132L RSCAN0.TMDF132.UINT16[L]
    7679 #define RSCAN0TMDF132LL RSCAN0.TMDF132.UINT8[LL]
    7680 #define RSCAN0TMDF132LH RSCAN0.TMDF132.UINT8[LH]
    7681 #define RSCAN0TMDF132H RSCAN0.TMDF132.UINT16[H]
    7682 #define RSCAN0TMDF132HL RSCAN0.TMDF132.UINT8[HL]
    7683 #define RSCAN0TMDF132HH RSCAN0.TMDF132.UINT8[HH]
    7684 #define RSCAN0TMID33 RSCAN0.TMID33.UINT32
    7685 #define RSCAN0TMID33L RSCAN0.TMID33.UINT16[L]
    7686 #define RSCAN0TMID33LL RSCAN0.TMID33.UINT8[LL]
    7687 #define RSCAN0TMID33LH RSCAN0.TMID33.UINT8[LH]
    7688 #define RSCAN0TMID33H RSCAN0.TMID33.UINT16[H]
    7689 #define RSCAN0TMID33HL RSCAN0.TMID33.UINT8[HL]
    7690 #define RSCAN0TMID33HH RSCAN0.TMID33.UINT8[HH]
    7691 #define RSCAN0TMPTR33 RSCAN0.TMPTR33.UINT32
    7692 #define RSCAN0TMPTR33L RSCAN0.TMPTR33.UINT16[L]
    7693 #define RSCAN0TMPTR33LL RSCAN0.TMPTR33.UINT8[LL]
    7694 #define RSCAN0TMPTR33LH RSCAN0.TMPTR33.UINT8[LH]
    7695 #define RSCAN0TMPTR33H RSCAN0.TMPTR33.UINT16[H]
    7696 #define RSCAN0TMPTR33HL RSCAN0.TMPTR33.UINT8[HL]
    7697 #define RSCAN0TMPTR33HH RSCAN0.TMPTR33.UINT8[HH]
    7698 #define RSCAN0TMDF033 RSCAN0.TMDF033.UINT32
    7699 #define RSCAN0TMDF033L RSCAN0.TMDF033.UINT16[L]
    7700 #define RSCAN0TMDF033LL RSCAN0.TMDF033.UINT8[LL]
    7701 #define RSCAN0TMDF033LH RSCAN0.TMDF033.UINT8[LH]
    7702 #define RSCAN0TMDF033H RSCAN0.TMDF033.UINT16[H]
    7703 #define RSCAN0TMDF033HL RSCAN0.TMDF033.UINT8[HL]
    7704 #define RSCAN0TMDF033HH RSCAN0.TMDF033.UINT8[HH]
    7705 #define RSCAN0TMDF133 RSCAN0.TMDF133.UINT32
    7706 #define RSCAN0TMDF133L RSCAN0.TMDF133.UINT16[L]
    7707 #define RSCAN0TMDF133LL RSCAN0.TMDF133.UINT8[LL]
    7708 #define RSCAN0TMDF133LH RSCAN0.TMDF133.UINT8[LH]
    7709 #define RSCAN0TMDF133H RSCAN0.TMDF133.UINT16[H]
    7710 #define RSCAN0TMDF133HL RSCAN0.TMDF133.UINT8[HL]
    7711 #define RSCAN0TMDF133HH RSCAN0.TMDF133.UINT8[HH]
    7712 #define RSCAN0TMID34 RSCAN0.TMID34.UINT32
    7713 #define RSCAN0TMID34L RSCAN0.TMID34.UINT16[L]
    7714 #define RSCAN0TMID34LL RSCAN0.TMID34.UINT8[LL]
    7715 #define RSCAN0TMID34LH RSCAN0.TMID34.UINT8[LH]
    7716 #define RSCAN0TMID34H RSCAN0.TMID34.UINT16[H]
    7717 #define RSCAN0TMID34HL RSCAN0.TMID34.UINT8[HL]
    7718 #define RSCAN0TMID34HH RSCAN0.TMID34.UINT8[HH]
    7719 #define RSCAN0TMPTR34 RSCAN0.TMPTR34.UINT32
    7720 #define RSCAN0TMPTR34L RSCAN0.TMPTR34.UINT16[L]
    7721 #define RSCAN0TMPTR34LL RSCAN0.TMPTR34.UINT8[LL]
    7722 #define RSCAN0TMPTR34LH RSCAN0.TMPTR34.UINT8[LH]
    7723 #define RSCAN0TMPTR34H RSCAN0.TMPTR34.UINT16[H]
    7724 #define RSCAN0TMPTR34HL RSCAN0.TMPTR34.UINT8[HL]
    7725 #define RSCAN0TMPTR34HH RSCAN0.TMPTR34.UINT8[HH]
    7726 #define RSCAN0TMDF034 RSCAN0.TMDF034.UINT32
    7727 #define RSCAN0TMDF034L RSCAN0.TMDF034.UINT16[L]
    7728 #define RSCAN0TMDF034LL RSCAN0.TMDF034.UINT8[LL]
    7729 #define RSCAN0TMDF034LH RSCAN0.TMDF034.UINT8[LH]
    7730 #define RSCAN0TMDF034H RSCAN0.TMDF034.UINT16[H]
    7731 #define RSCAN0TMDF034HL RSCAN0.TMDF034.UINT8[HL]
    7732 #define RSCAN0TMDF034HH RSCAN0.TMDF034.UINT8[HH]
    7733 #define RSCAN0TMDF134 RSCAN0.TMDF134.UINT32
    7734 #define RSCAN0TMDF134L RSCAN0.TMDF134.UINT16[L]
    7735 #define RSCAN0TMDF134LL RSCAN0.TMDF134.UINT8[LL]
    7736 #define RSCAN0TMDF134LH RSCAN0.TMDF134.UINT8[LH]
    7737 #define RSCAN0TMDF134H RSCAN0.TMDF134.UINT16[H]
    7738 #define RSCAN0TMDF134HL RSCAN0.TMDF134.UINT8[HL]
    7739 #define RSCAN0TMDF134HH RSCAN0.TMDF134.UINT8[HH]
    7740 #define RSCAN0TMID35 RSCAN0.TMID35.UINT32
    7741 #define RSCAN0TMID35L RSCAN0.TMID35.UINT16[L]
    7742 #define RSCAN0TMID35LL RSCAN0.TMID35.UINT8[LL]
    7743 #define RSCAN0TMID35LH RSCAN0.TMID35.UINT8[LH]
    7744 #define RSCAN0TMID35H RSCAN0.TMID35.UINT16[H]
    7745 #define RSCAN0TMID35HL RSCAN0.TMID35.UINT8[HL]
    7746 #define RSCAN0TMID35HH RSCAN0.TMID35.UINT8[HH]
    7747 #define RSCAN0TMPTR35 RSCAN0.TMPTR35.UINT32
    7748 #define RSCAN0TMPTR35L RSCAN0.TMPTR35.UINT16[L]
    7749 #define RSCAN0TMPTR35LL RSCAN0.TMPTR35.UINT8[LL]
    7750 #define RSCAN0TMPTR35LH RSCAN0.TMPTR35.UINT8[LH]
    7751 #define RSCAN0TMPTR35H RSCAN0.TMPTR35.UINT16[H]
    7752 #define RSCAN0TMPTR35HL RSCAN0.TMPTR35.UINT8[HL]
    7753 #define RSCAN0TMPTR35HH RSCAN0.TMPTR35.UINT8[HH]
    7754 #define RSCAN0TMDF035 RSCAN0.TMDF035.UINT32
    7755 #define RSCAN0TMDF035L RSCAN0.TMDF035.UINT16[L]
    7756 #define RSCAN0TMDF035LL RSCAN0.TMDF035.UINT8[LL]
    7757 #define RSCAN0TMDF035LH RSCAN0.TMDF035.UINT8[LH]
    7758 #define RSCAN0TMDF035H RSCAN0.TMDF035.UINT16[H]
    7759 #define RSCAN0TMDF035HL RSCAN0.TMDF035.UINT8[HL]
    7760 #define RSCAN0TMDF035HH RSCAN0.TMDF035.UINT8[HH]
    7761 #define RSCAN0TMDF135 RSCAN0.TMDF135.UINT32
    7762 #define RSCAN0TMDF135L RSCAN0.TMDF135.UINT16[L]
    7763 #define RSCAN0TMDF135LL RSCAN0.TMDF135.UINT8[LL]
    7764 #define RSCAN0TMDF135LH RSCAN0.TMDF135.UINT8[LH]
    7765 #define RSCAN0TMDF135H RSCAN0.TMDF135.UINT16[H]
    7766 #define RSCAN0TMDF135HL RSCAN0.TMDF135.UINT8[HL]
    7767 #define RSCAN0TMDF135HH RSCAN0.TMDF135.UINT8[HH]
    7768 #define RSCAN0TMID36 RSCAN0.TMID36.UINT32
    7769 #define RSCAN0TMID36L RSCAN0.TMID36.UINT16[L]
    7770 #define RSCAN0TMID36LL RSCAN0.TMID36.UINT8[LL]
    7771 #define RSCAN0TMID36LH RSCAN0.TMID36.UINT8[LH]
    7772 #define RSCAN0TMID36H RSCAN0.TMID36.UINT16[H]
    7773 #define RSCAN0TMID36HL RSCAN0.TMID36.UINT8[HL]
    7774 #define RSCAN0TMID36HH RSCAN0.TMID36.UINT8[HH]
    7775 #define RSCAN0TMPTR36 RSCAN0.TMPTR36.UINT32
    7776 #define RSCAN0TMPTR36L RSCAN0.TMPTR36.UINT16[L]
    7777 #define RSCAN0TMPTR36LL RSCAN0.TMPTR36.UINT8[LL]
    7778 #define RSCAN0TMPTR36LH RSCAN0.TMPTR36.UINT8[LH]
    7779 #define RSCAN0TMPTR36H RSCAN0.TMPTR36.UINT16[H]
    7780 #define RSCAN0TMPTR36HL RSCAN0.TMPTR36.UINT8[HL]
    7781 #define RSCAN0TMPTR36HH RSCAN0.TMPTR36.UINT8[HH]
    7782 #define RSCAN0TMDF036 RSCAN0.TMDF036.UINT32
    7783 #define RSCAN0TMDF036L RSCAN0.TMDF036.UINT16[L]
    7784 #define RSCAN0TMDF036LL RSCAN0.TMDF036.UINT8[LL]
    7785 #define RSCAN0TMDF036LH RSCAN0.TMDF036.UINT8[LH]
    7786 #define RSCAN0TMDF036H RSCAN0.TMDF036.UINT16[H]
    7787 #define RSCAN0TMDF036HL RSCAN0.TMDF036.UINT8[HL]
    7788 #define RSCAN0TMDF036HH RSCAN0.TMDF036.UINT8[HH]
    7789 #define RSCAN0TMDF136 RSCAN0.TMDF136.UINT32
    7790 #define RSCAN0TMDF136L RSCAN0.TMDF136.UINT16[L]
    7791 #define RSCAN0TMDF136LL RSCAN0.TMDF136.UINT8[LL]
    7792 #define RSCAN0TMDF136LH RSCAN0.TMDF136.UINT8[LH]
    7793 #define RSCAN0TMDF136H RSCAN0.TMDF136.UINT16[H]
    7794 #define RSCAN0TMDF136HL RSCAN0.TMDF136.UINT8[HL]
    7795 #define RSCAN0TMDF136HH RSCAN0.TMDF136.UINT8[HH]
    7796 #define RSCAN0TMID37 RSCAN0.TMID37.UINT32
    7797 #define RSCAN0TMID37L RSCAN0.TMID37.UINT16[L]
    7798 #define RSCAN0TMID37LL RSCAN0.TMID37.UINT8[LL]
    7799 #define RSCAN0TMID37LH RSCAN0.TMID37.UINT8[LH]
    7800 #define RSCAN0TMID37H RSCAN0.TMID37.UINT16[H]
    7801 #define RSCAN0TMID37HL RSCAN0.TMID37.UINT8[HL]
    7802 #define RSCAN0TMID37HH RSCAN0.TMID37.UINT8[HH]
    7803 #define RSCAN0TMPTR37 RSCAN0.TMPTR37.UINT32
    7804 #define RSCAN0TMPTR37L RSCAN0.TMPTR37.UINT16[L]
    7805 #define RSCAN0TMPTR37LL RSCAN0.TMPTR37.UINT8[LL]
    7806 #define RSCAN0TMPTR37LH RSCAN0.TMPTR37.UINT8[LH]
    7807 #define RSCAN0TMPTR37H RSCAN0.TMPTR37.UINT16[H]
    7808 #define RSCAN0TMPTR37HL RSCAN0.TMPTR37.UINT8[HL]
    7809 #define RSCAN0TMPTR37HH RSCAN0.TMPTR37.UINT8[HH]
    7810 #define RSCAN0TMDF037 RSCAN0.TMDF037.UINT32
    7811 #define RSCAN0TMDF037L RSCAN0.TMDF037.UINT16[L]
    7812 #define RSCAN0TMDF037LL RSCAN0.TMDF037.UINT8[LL]
    7813 #define RSCAN0TMDF037LH RSCAN0.TMDF037.UINT8[LH]
    7814 #define RSCAN0TMDF037H RSCAN0.TMDF037.UINT16[H]
    7815 #define RSCAN0TMDF037HL RSCAN0.TMDF037.UINT8[HL]
    7816 #define RSCAN0TMDF037HH RSCAN0.TMDF037.UINT8[HH]
    7817 #define RSCAN0TMDF137 RSCAN0.TMDF137.UINT32
    7818 #define RSCAN0TMDF137L RSCAN0.TMDF137.UINT16[L]
    7819 #define RSCAN0TMDF137LL RSCAN0.TMDF137.UINT8[LL]
    7820 #define RSCAN0TMDF137LH RSCAN0.TMDF137.UINT8[LH]
    7821 #define RSCAN0TMDF137H RSCAN0.TMDF137.UINT16[H]
    7822 #define RSCAN0TMDF137HL RSCAN0.TMDF137.UINT8[HL]
    7823 #define RSCAN0TMDF137HH RSCAN0.TMDF137.UINT8[HH]
    7824 #define RSCAN0TMID38 RSCAN0.TMID38.UINT32
    7825 #define RSCAN0TMID38L RSCAN0.TMID38.UINT16[L]
    7826 #define RSCAN0TMID38LL RSCAN0.TMID38.UINT8[LL]
    7827 #define RSCAN0TMID38LH RSCAN0.TMID38.UINT8[LH]
    7828 #define RSCAN0TMID38H RSCAN0.TMID38.UINT16[H]
    7829 #define RSCAN0TMID38HL RSCAN0.TMID38.UINT8[HL]
    7830 #define RSCAN0TMID38HH RSCAN0.TMID38.UINT8[HH]
    7831 #define RSCAN0TMPTR38 RSCAN0.TMPTR38.UINT32
    7832 #define RSCAN0TMPTR38L RSCAN0.TMPTR38.UINT16[L]
    7833 #define RSCAN0TMPTR38LL RSCAN0.TMPTR38.UINT8[LL]
    7834 #define RSCAN0TMPTR38LH RSCAN0.TMPTR38.UINT8[LH]
    7835 #define RSCAN0TMPTR38H RSCAN0.TMPTR38.UINT16[H]
    7836 #define RSCAN0TMPTR38HL RSCAN0.TMPTR38.UINT8[HL]
    7837 #define RSCAN0TMPTR38HH RSCAN0.TMPTR38.UINT8[HH]
    7838 #define RSCAN0TMDF038 RSCAN0.TMDF038.UINT32
    7839 #define RSCAN0TMDF038L RSCAN0.TMDF038.UINT16[L]
    7840 #define RSCAN0TMDF038LL RSCAN0.TMDF038.UINT8[LL]
    7841 #define RSCAN0TMDF038LH RSCAN0.TMDF038.UINT8[LH]
    7842 #define RSCAN0TMDF038H RSCAN0.TMDF038.UINT16[H]
    7843 #define RSCAN0TMDF038HL RSCAN0.TMDF038.UINT8[HL]
    7844 #define RSCAN0TMDF038HH RSCAN0.TMDF038.UINT8[HH]
    7845 #define RSCAN0TMDF138 RSCAN0.TMDF138.UINT32
    7846 #define RSCAN0TMDF138L RSCAN0.TMDF138.UINT16[L]
    7847 #define RSCAN0TMDF138LL RSCAN0.TMDF138.UINT8[LL]
    7848 #define RSCAN0TMDF138LH RSCAN0.TMDF138.UINT8[LH]
    7849 #define RSCAN0TMDF138H RSCAN0.TMDF138.UINT16[H]
    7850 #define RSCAN0TMDF138HL RSCAN0.TMDF138.UINT8[HL]
    7851 #define RSCAN0TMDF138HH RSCAN0.TMDF138.UINT8[HH]
    7852 #define RSCAN0TMID39 RSCAN0.TMID39.UINT32
    7853 #define RSCAN0TMID39L RSCAN0.TMID39.UINT16[L]
    7854 #define RSCAN0TMID39LL RSCAN0.TMID39.UINT8[LL]
    7855 #define RSCAN0TMID39LH RSCAN0.TMID39.UINT8[LH]
    7856 #define RSCAN0TMID39H RSCAN0.TMID39.UINT16[H]
    7857 #define RSCAN0TMID39HL RSCAN0.TMID39.UINT8[HL]
    7858 #define RSCAN0TMID39HH RSCAN0.TMID39.UINT8[HH]
    7859 #define RSCAN0TMPTR39 RSCAN0.TMPTR39.UINT32
    7860 #define RSCAN0TMPTR39L RSCAN0.TMPTR39.UINT16[L]
    7861 #define RSCAN0TMPTR39LL RSCAN0.TMPTR39.UINT8[LL]
    7862 #define RSCAN0TMPTR39LH RSCAN0.TMPTR39.UINT8[LH]
    7863 #define RSCAN0TMPTR39H RSCAN0.TMPTR39.UINT16[H]
    7864 #define RSCAN0TMPTR39HL RSCAN0.TMPTR39.UINT8[HL]
    7865 #define RSCAN0TMPTR39HH RSCAN0.TMPTR39.UINT8[HH]
    7866 #define RSCAN0TMDF039 RSCAN0.TMDF039.UINT32
    7867 #define RSCAN0TMDF039L RSCAN0.TMDF039.UINT16[L]
    7868 #define RSCAN0TMDF039LL RSCAN0.TMDF039.UINT8[LL]
    7869 #define RSCAN0TMDF039LH RSCAN0.TMDF039.UINT8[LH]
    7870 #define RSCAN0TMDF039H RSCAN0.TMDF039.UINT16[H]
    7871 #define RSCAN0TMDF039HL RSCAN0.TMDF039.UINT8[HL]
    7872 #define RSCAN0TMDF039HH RSCAN0.TMDF039.UINT8[HH]
    7873 #define RSCAN0TMDF139 RSCAN0.TMDF139.UINT32
    7874 #define RSCAN0TMDF139L RSCAN0.TMDF139.UINT16[L]
    7875 #define RSCAN0TMDF139LL RSCAN0.TMDF139.UINT8[LL]
    7876 #define RSCAN0TMDF139LH RSCAN0.TMDF139.UINT8[LH]
    7877 #define RSCAN0TMDF139H RSCAN0.TMDF139.UINT16[H]
    7878 #define RSCAN0TMDF139HL RSCAN0.TMDF139.UINT8[HL]
    7879 #define RSCAN0TMDF139HH RSCAN0.TMDF139.UINT8[HH]
    7880 #define RSCAN0TMID40 RSCAN0.TMID40.UINT32
    7881 #define RSCAN0TMID40L RSCAN0.TMID40.UINT16[L]
    7882 #define RSCAN0TMID40LL RSCAN0.TMID40.UINT8[LL]
    7883 #define RSCAN0TMID40LH RSCAN0.TMID40.UINT8[LH]
    7884 #define RSCAN0TMID40H RSCAN0.TMID40.UINT16[H]
    7885 #define RSCAN0TMID40HL RSCAN0.TMID40.UINT8[HL]
    7886 #define RSCAN0TMID40HH RSCAN0.TMID40.UINT8[HH]
    7887 #define RSCAN0TMPTR40 RSCAN0.TMPTR40.UINT32
    7888 #define RSCAN0TMPTR40L RSCAN0.TMPTR40.UINT16[L]
    7889 #define RSCAN0TMPTR40LL RSCAN0.TMPTR40.UINT8[LL]
    7890 #define RSCAN0TMPTR40LH RSCAN0.TMPTR40.UINT8[LH]
    7891 #define RSCAN0TMPTR40H RSCAN0.TMPTR40.UINT16[H]
    7892 #define RSCAN0TMPTR40HL RSCAN0.TMPTR40.UINT8[HL]
    7893 #define RSCAN0TMPTR40HH RSCAN0.TMPTR40.UINT8[HH]
    7894 #define RSCAN0TMDF040 RSCAN0.TMDF040.UINT32
    7895 #define RSCAN0TMDF040L RSCAN0.TMDF040.UINT16[L]
    7896 #define RSCAN0TMDF040LL RSCAN0.TMDF040.UINT8[LL]
    7897 #define RSCAN0TMDF040LH RSCAN0.TMDF040.UINT8[LH]
    7898 #define RSCAN0TMDF040H RSCAN0.TMDF040.UINT16[H]
    7899 #define RSCAN0TMDF040HL RSCAN0.TMDF040.UINT8[HL]
    7900 #define RSCAN0TMDF040HH RSCAN0.TMDF040.UINT8[HH]
    7901 #define RSCAN0TMDF140 RSCAN0.TMDF140.UINT32
    7902 #define RSCAN0TMDF140L RSCAN0.TMDF140.UINT16[L]
    7903 #define RSCAN0TMDF140LL RSCAN0.TMDF140.UINT8[LL]
    7904 #define RSCAN0TMDF140LH RSCAN0.TMDF140.UINT8[LH]
    7905 #define RSCAN0TMDF140H RSCAN0.TMDF140.UINT16[H]
    7906 #define RSCAN0TMDF140HL RSCAN0.TMDF140.UINT8[HL]
    7907 #define RSCAN0TMDF140HH RSCAN0.TMDF140.UINT8[HH]
    7908 #define RSCAN0TMID41 RSCAN0.TMID41.UINT32
    7909 #define RSCAN0TMID41L RSCAN0.TMID41.UINT16[L]
    7910 #define RSCAN0TMID41LL RSCAN0.TMID41.UINT8[LL]
    7911 #define RSCAN0TMID41LH RSCAN0.TMID41.UINT8[LH]
    7912 #define RSCAN0TMID41H RSCAN0.TMID41.UINT16[H]
    7913 #define RSCAN0TMID41HL RSCAN0.TMID41.UINT8[HL]
    7914 #define RSCAN0TMID41HH RSCAN0.TMID41.UINT8[HH]
    7915 #define RSCAN0TMPTR41 RSCAN0.TMPTR41.UINT32
    7916 #define RSCAN0TMPTR41L RSCAN0.TMPTR41.UINT16[L]
    7917 #define RSCAN0TMPTR41LL RSCAN0.TMPTR41.UINT8[LL]
    7918 #define RSCAN0TMPTR41LH RSCAN0.TMPTR41.UINT8[LH]
    7919 #define RSCAN0TMPTR41H RSCAN0.TMPTR41.UINT16[H]
    7920 #define RSCAN0TMPTR41HL RSCAN0.TMPTR41.UINT8[HL]
    7921 #define RSCAN0TMPTR41HH RSCAN0.TMPTR41.UINT8[HH]
    7922 #define RSCAN0TMDF041 RSCAN0.TMDF041.UINT32
    7923 #define RSCAN0TMDF041L RSCAN0.TMDF041.UINT16[L]
    7924 #define RSCAN0TMDF041LL RSCAN0.TMDF041.UINT8[LL]
    7925 #define RSCAN0TMDF041LH RSCAN0.TMDF041.UINT8[LH]
    7926 #define RSCAN0TMDF041H RSCAN0.TMDF041.UINT16[H]
    7927 #define RSCAN0TMDF041HL RSCAN0.TMDF041.UINT8[HL]
    7928 #define RSCAN0TMDF041HH RSCAN0.TMDF041.UINT8[HH]
    7929 #define RSCAN0TMDF141 RSCAN0.TMDF141.UINT32
    7930 #define RSCAN0TMDF141L RSCAN0.TMDF141.UINT16[L]
    7931 #define RSCAN0TMDF141LL RSCAN0.TMDF141.UINT8[LL]
    7932 #define RSCAN0TMDF141LH RSCAN0.TMDF141.UINT8[LH]
    7933 #define RSCAN0TMDF141H RSCAN0.TMDF141.UINT16[H]
    7934 #define RSCAN0TMDF141HL RSCAN0.TMDF141.UINT8[HL]
    7935 #define RSCAN0TMDF141HH RSCAN0.TMDF141.UINT8[HH]
    7936 #define RSCAN0TMID42 RSCAN0.TMID42.UINT32
    7937 #define RSCAN0TMID42L RSCAN0.TMID42.UINT16[L]
    7938 #define RSCAN0TMID42LL RSCAN0.TMID42.UINT8[LL]
    7939 #define RSCAN0TMID42LH RSCAN0.TMID42.UINT8[LH]
    7940 #define RSCAN0TMID42H RSCAN0.TMID42.UINT16[H]
    7941 #define RSCAN0TMID42HL RSCAN0.TMID42.UINT8[HL]
    7942 #define RSCAN0TMID42HH RSCAN0.TMID42.UINT8[HH]
    7943 #define RSCAN0TMPTR42 RSCAN0.TMPTR42.UINT32
    7944 #define RSCAN0TMPTR42L RSCAN0.TMPTR42.UINT16[L]
    7945 #define RSCAN0TMPTR42LL RSCAN0.TMPTR42.UINT8[LL]
    7946 #define RSCAN0TMPTR42LH RSCAN0.TMPTR42.UINT8[LH]
    7947 #define RSCAN0TMPTR42H RSCAN0.TMPTR42.UINT16[H]
    7948 #define RSCAN0TMPTR42HL RSCAN0.TMPTR42.UINT8[HL]
    7949 #define RSCAN0TMPTR42HH RSCAN0.TMPTR42.UINT8[HH]
    7950 #define RSCAN0TMDF042 RSCAN0.TMDF042.UINT32
    7951 #define RSCAN0TMDF042L RSCAN0.TMDF042.UINT16[L]
    7952 #define RSCAN0TMDF042LL RSCAN0.TMDF042.UINT8[LL]
    7953 #define RSCAN0TMDF042LH RSCAN0.TMDF042.UINT8[LH]
    7954 #define RSCAN0TMDF042H RSCAN0.TMDF042.UINT16[H]
    7955 #define RSCAN0TMDF042HL RSCAN0.TMDF042.UINT8[HL]
    7956 #define RSCAN0TMDF042HH RSCAN0.TMDF042.UINT8[HH]
    7957 #define RSCAN0TMDF142 RSCAN0.TMDF142.UINT32
    7958 #define RSCAN0TMDF142L RSCAN0.TMDF142.UINT16[L]
    7959 #define RSCAN0TMDF142LL RSCAN0.TMDF142.UINT8[LL]
    7960 #define RSCAN0TMDF142LH RSCAN0.TMDF142.UINT8[LH]
    7961 #define RSCAN0TMDF142H RSCAN0.TMDF142.UINT16[H]
    7962 #define RSCAN0TMDF142HL RSCAN0.TMDF142.UINT8[HL]
    7963 #define RSCAN0TMDF142HH RSCAN0.TMDF142.UINT8[HH]
    7964 #define RSCAN0TMID43 RSCAN0.TMID43.UINT32
    7965 #define RSCAN0TMID43L RSCAN0.TMID43.UINT16[L]
    7966 #define RSCAN0TMID43LL RSCAN0.TMID43.UINT8[LL]
    7967 #define RSCAN0TMID43LH RSCAN0.TMID43.UINT8[LH]
    7968 #define RSCAN0TMID43H RSCAN0.TMID43.UINT16[H]
    7969 #define RSCAN0TMID43HL RSCAN0.TMID43.UINT8[HL]
    7970 #define RSCAN0TMID43HH RSCAN0.TMID43.UINT8[HH]
    7971 #define RSCAN0TMPTR43 RSCAN0.TMPTR43.UINT32
    7972 #define RSCAN0TMPTR43L RSCAN0.TMPTR43.UINT16[L]
    7973 #define RSCAN0TMPTR43LL RSCAN0.TMPTR43.UINT8[LL]
    7974 #define RSCAN0TMPTR43LH RSCAN0.TMPTR43.UINT8[LH]
    7975 #define RSCAN0TMPTR43H RSCAN0.TMPTR43.UINT16[H]
    7976 #define RSCAN0TMPTR43HL RSCAN0.TMPTR43.UINT8[HL]
    7977 #define RSCAN0TMPTR43HH RSCAN0.TMPTR43.UINT8[HH]
    7978 #define RSCAN0TMDF043 RSCAN0.TMDF043.UINT32
    7979 #define RSCAN0TMDF043L RSCAN0.TMDF043.UINT16[L]
    7980 #define RSCAN0TMDF043LL RSCAN0.TMDF043.UINT8[LL]
    7981 #define RSCAN0TMDF043LH RSCAN0.TMDF043.UINT8[LH]
    7982 #define RSCAN0TMDF043H RSCAN0.TMDF043.UINT16[H]
    7983 #define RSCAN0TMDF043HL RSCAN0.TMDF043.UINT8[HL]
    7984 #define RSCAN0TMDF043HH RSCAN0.TMDF043.UINT8[HH]
    7985 #define RSCAN0TMDF143 RSCAN0.TMDF143.UINT32
    7986 #define RSCAN0TMDF143L RSCAN0.TMDF143.UINT16[L]
    7987 #define RSCAN0TMDF143LL RSCAN0.TMDF143.UINT8[LL]
    7988 #define RSCAN0TMDF143LH RSCAN0.TMDF143.UINT8[LH]
    7989 #define RSCAN0TMDF143H RSCAN0.TMDF143.UINT16[H]
    7990 #define RSCAN0TMDF143HL RSCAN0.TMDF143.UINT8[HL]
    7991 #define RSCAN0TMDF143HH RSCAN0.TMDF143.UINT8[HH]
    7992 #define RSCAN0TMID44 RSCAN0.TMID44.UINT32
    7993 #define RSCAN0TMID44L RSCAN0.TMID44.UINT16[L]
    7994 #define RSCAN0TMID44LL RSCAN0.TMID44.UINT8[LL]
    7995 #define RSCAN0TMID44LH RSCAN0.TMID44.UINT8[LH]
    7996 #define RSCAN0TMID44H RSCAN0.TMID44.UINT16[H]
    7997 #define RSCAN0TMID44HL RSCAN0.TMID44.UINT8[HL]
    7998 #define RSCAN0TMID44HH RSCAN0.TMID44.UINT8[HH]
    7999 #define RSCAN0TMPTR44 RSCAN0.TMPTR44.UINT32
    8000 #define RSCAN0TMPTR44L RSCAN0.TMPTR44.UINT16[L]
    8001 #define RSCAN0TMPTR44LL RSCAN0.TMPTR44.UINT8[LL]
    8002 #define RSCAN0TMPTR44LH RSCAN0.TMPTR44.UINT8[LH]
    8003 #define RSCAN0TMPTR44H RSCAN0.TMPTR44.UINT16[H]
    8004 #define RSCAN0TMPTR44HL RSCAN0.TMPTR44.UINT8[HL]
    8005 #define RSCAN0TMPTR44HH RSCAN0.TMPTR44.UINT8[HH]
    8006 #define RSCAN0TMDF044 RSCAN0.TMDF044.UINT32
    8007 #define RSCAN0TMDF044L RSCAN0.TMDF044.UINT16[L]
    8008 #define RSCAN0TMDF044LL RSCAN0.TMDF044.UINT8[LL]
    8009 #define RSCAN0TMDF044LH RSCAN0.TMDF044.UINT8[LH]
    8010 #define RSCAN0TMDF044H RSCAN0.TMDF044.UINT16[H]
    8011 #define RSCAN0TMDF044HL RSCAN0.TMDF044.UINT8[HL]
    8012 #define RSCAN0TMDF044HH RSCAN0.TMDF044.UINT8[HH]
    8013 #define RSCAN0TMDF144 RSCAN0.TMDF144.UINT32
    8014 #define RSCAN0TMDF144L RSCAN0.TMDF144.UINT16[L]
    8015 #define RSCAN0TMDF144LL RSCAN0.TMDF144.UINT8[LL]
    8016 #define RSCAN0TMDF144LH RSCAN0.TMDF144.UINT8[LH]
    8017 #define RSCAN0TMDF144H RSCAN0.TMDF144.UINT16[H]
    8018 #define RSCAN0TMDF144HL RSCAN0.TMDF144.UINT8[HL]
    8019 #define RSCAN0TMDF144HH RSCAN0.TMDF144.UINT8[HH]
    8020 #define RSCAN0TMID45 RSCAN0.TMID45.UINT32
    8021 #define RSCAN0TMID45L RSCAN0.TMID45.UINT16[L]
    8022 #define RSCAN0TMID45LL RSCAN0.TMID45.UINT8[LL]
    8023 #define RSCAN0TMID45LH RSCAN0.TMID45.UINT8[LH]
    8024 #define RSCAN0TMID45H RSCAN0.TMID45.UINT16[H]
    8025 #define RSCAN0TMID45HL RSCAN0.TMID45.UINT8[HL]
    8026 #define RSCAN0TMID45HH RSCAN0.TMID45.UINT8[HH]
    8027 #define RSCAN0TMPTR45 RSCAN0.TMPTR45.UINT32
    8028 #define RSCAN0TMPTR45L RSCAN0.TMPTR45.UINT16[L]
    8029 #define RSCAN0TMPTR45LL RSCAN0.TMPTR45.UINT8[LL]
    8030 #define RSCAN0TMPTR45LH RSCAN0.TMPTR45.UINT8[LH]
    8031 #define RSCAN0TMPTR45H RSCAN0.TMPTR45.UINT16[H]
    8032 #define RSCAN0TMPTR45HL RSCAN0.TMPTR45.UINT8[HL]
    8033 #define RSCAN0TMPTR45HH RSCAN0.TMPTR45.UINT8[HH]
    8034 #define RSCAN0TMDF045 RSCAN0.TMDF045.UINT32
    8035 #define RSCAN0TMDF045L RSCAN0.TMDF045.UINT16[L]
    8036 #define RSCAN0TMDF045LL RSCAN0.TMDF045.UINT8[LL]
    8037 #define RSCAN0TMDF045LH RSCAN0.TMDF045.UINT8[LH]
    8038 #define RSCAN0TMDF045H RSCAN0.TMDF045.UINT16[H]
    8039 #define RSCAN0TMDF045HL RSCAN0.TMDF045.UINT8[HL]
    8040 #define RSCAN0TMDF045HH RSCAN0.TMDF045.UINT8[HH]
    8041 #define RSCAN0TMDF145 RSCAN0.TMDF145.UINT32
    8042 #define RSCAN0TMDF145L RSCAN0.TMDF145.UINT16[L]
    8043 #define RSCAN0TMDF145LL RSCAN0.TMDF145.UINT8[LL]
    8044 #define RSCAN0TMDF145LH RSCAN0.TMDF145.UINT8[LH]
    8045 #define RSCAN0TMDF145H RSCAN0.TMDF145.UINT16[H]
    8046 #define RSCAN0TMDF145HL RSCAN0.TMDF145.UINT8[HL]
    8047 #define RSCAN0TMDF145HH RSCAN0.TMDF145.UINT8[HH]
    8048 #define RSCAN0TMID46 RSCAN0.TMID46.UINT32
    8049 #define RSCAN0TMID46L RSCAN0.TMID46.UINT16[L]
    8050 #define RSCAN0TMID46LL RSCAN0.TMID46.UINT8[LL]
    8051 #define RSCAN0TMID46LH RSCAN0.TMID46.UINT8[LH]
    8052 #define RSCAN0TMID46H RSCAN0.TMID46.UINT16[H]
    8053 #define RSCAN0TMID46HL RSCAN0.TMID46.UINT8[HL]
    8054 #define RSCAN0TMID46HH RSCAN0.TMID46.UINT8[HH]
    8055 #define RSCAN0TMPTR46 RSCAN0.TMPTR46.UINT32
    8056 #define RSCAN0TMPTR46L RSCAN0.TMPTR46.UINT16[L]
    8057 #define RSCAN0TMPTR46LL RSCAN0.TMPTR46.UINT8[LL]
    8058 #define RSCAN0TMPTR46LH RSCAN0.TMPTR46.UINT8[LH]
    8059 #define RSCAN0TMPTR46H RSCAN0.TMPTR46.UINT16[H]
    8060 #define RSCAN0TMPTR46HL RSCAN0.TMPTR46.UINT8[HL]
    8061 #define RSCAN0TMPTR46HH RSCAN0.TMPTR46.UINT8[HH]
    8062 #define RSCAN0TMDF046 RSCAN0.TMDF046.UINT32
    8063 #define RSCAN0TMDF046L RSCAN0.TMDF046.UINT16[L]
    8064 #define RSCAN0TMDF046LL RSCAN0.TMDF046.UINT8[LL]
    8065 #define RSCAN0TMDF046LH RSCAN0.TMDF046.UINT8[LH]
    8066 #define RSCAN0TMDF046H RSCAN0.TMDF046.UINT16[H]
    8067 #define RSCAN0TMDF046HL RSCAN0.TMDF046.UINT8[HL]
    8068 #define RSCAN0TMDF046HH RSCAN0.TMDF046.UINT8[HH]
    8069 #define RSCAN0TMDF146 RSCAN0.TMDF146.UINT32
    8070 #define RSCAN0TMDF146L RSCAN0.TMDF146.UINT16[L]
    8071 #define RSCAN0TMDF146LL RSCAN0.TMDF146.UINT8[LL]
    8072 #define RSCAN0TMDF146LH RSCAN0.TMDF146.UINT8[LH]
    8073 #define RSCAN0TMDF146H RSCAN0.TMDF146.UINT16[H]
    8074 #define RSCAN0TMDF146HL RSCAN0.TMDF146.UINT8[HL]
    8075 #define RSCAN0TMDF146HH RSCAN0.TMDF146.UINT8[HH]
    8076 #define RSCAN0TMID47 RSCAN0.TMID47.UINT32
    8077 #define RSCAN0TMID47L RSCAN0.TMID47.UINT16[L]
    8078 #define RSCAN0TMID47LL RSCAN0.TMID47.UINT8[LL]
    8079 #define RSCAN0TMID47LH RSCAN0.TMID47.UINT8[LH]
    8080 #define RSCAN0TMID47H RSCAN0.TMID47.UINT16[H]
    8081 #define RSCAN0TMID47HL RSCAN0.TMID47.UINT8[HL]
    8082 #define RSCAN0TMID47HH RSCAN0.TMID47.UINT8[HH]
    8083 #define RSCAN0TMPTR47 RSCAN0.TMPTR47.UINT32
    8084 #define RSCAN0TMPTR47L RSCAN0.TMPTR47.UINT16[L]
    8085 #define RSCAN0TMPTR47LL RSCAN0.TMPTR47.UINT8[LL]
    8086 #define RSCAN0TMPTR47LH RSCAN0.TMPTR47.UINT8[LH]
    8087 #define RSCAN0TMPTR47H RSCAN0.TMPTR47.UINT16[H]
    8088 #define RSCAN0TMPTR47HL RSCAN0.TMPTR47.UINT8[HL]
    8089 #define RSCAN0TMPTR47HH RSCAN0.TMPTR47.UINT8[HH]
    8090 #define RSCAN0TMDF047 RSCAN0.TMDF047.UINT32
    8091 #define RSCAN0TMDF047L RSCAN0.TMDF047.UINT16[L]
    8092 #define RSCAN0TMDF047LL RSCAN0.TMDF047.UINT8[LL]
    8093 #define RSCAN0TMDF047LH RSCAN0.TMDF047.UINT8[LH]
    8094 #define RSCAN0TMDF047H RSCAN0.TMDF047.UINT16[H]
    8095 #define RSCAN0TMDF047HL RSCAN0.TMDF047.UINT8[HL]
    8096 #define RSCAN0TMDF047HH RSCAN0.TMDF047.UINT8[HH]
    8097 #define RSCAN0TMDF147 RSCAN0.TMDF147.UINT32
    8098 #define RSCAN0TMDF147L RSCAN0.TMDF147.UINT16[L]
    8099 #define RSCAN0TMDF147LL RSCAN0.TMDF147.UINT8[LL]
    8100 #define RSCAN0TMDF147LH RSCAN0.TMDF147.UINT8[LH]
    8101 #define RSCAN0TMDF147H RSCAN0.TMDF147.UINT16[H]
    8102 #define RSCAN0TMDF147HL RSCAN0.TMDF147.UINT8[HL]
    8103 #define RSCAN0TMDF147HH RSCAN0.TMDF147.UINT8[HH]
    8104 #define RSCAN0TMID48 RSCAN0.TMID48.UINT32
    8105 #define RSCAN0TMID48L RSCAN0.TMID48.UINT16[L]
    8106 #define RSCAN0TMID48LL RSCAN0.TMID48.UINT8[LL]
    8107 #define RSCAN0TMID48LH RSCAN0.TMID48.UINT8[LH]
    8108 #define RSCAN0TMID48H RSCAN0.TMID48.UINT16[H]
    8109 #define RSCAN0TMID48HL RSCAN0.TMID48.UINT8[HL]
    8110 #define RSCAN0TMID48HH RSCAN0.TMID48.UINT8[HH]
    8111 #define RSCAN0TMPTR48 RSCAN0.TMPTR48.UINT32
    8112 #define RSCAN0TMPTR48L RSCAN0.TMPTR48.UINT16[L]
    8113 #define RSCAN0TMPTR48LL RSCAN0.TMPTR48.UINT8[LL]
    8114 #define RSCAN0TMPTR48LH RSCAN0.TMPTR48.UINT8[LH]
    8115 #define RSCAN0TMPTR48H RSCAN0.TMPTR48.UINT16[H]
    8116 #define RSCAN0TMPTR48HL RSCAN0.TMPTR48.UINT8[HL]
    8117 #define RSCAN0TMPTR48HH RSCAN0.TMPTR48.UINT8[HH]
    8118 #define RSCAN0TMDF048 RSCAN0.TMDF048.UINT32
    8119 #define RSCAN0TMDF048L RSCAN0.TMDF048.UINT16[L]
    8120 #define RSCAN0TMDF048LL RSCAN0.TMDF048.UINT8[LL]
    8121 #define RSCAN0TMDF048LH RSCAN0.TMDF048.UINT8[LH]
    8122 #define RSCAN0TMDF048H RSCAN0.TMDF048.UINT16[H]
    8123 #define RSCAN0TMDF048HL RSCAN0.TMDF048.UINT8[HL]
    8124 #define RSCAN0TMDF048HH RSCAN0.TMDF048.UINT8[HH]
    8125 #define RSCAN0TMDF148 RSCAN0.TMDF148.UINT32
    8126 #define RSCAN0TMDF148L RSCAN0.TMDF148.UINT16[L]
    8127 #define RSCAN0TMDF148LL RSCAN0.TMDF148.UINT8[LL]
    8128 #define RSCAN0TMDF148LH RSCAN0.TMDF148.UINT8[LH]
    8129 #define RSCAN0TMDF148H RSCAN0.TMDF148.UINT16[H]
    8130 #define RSCAN0TMDF148HL RSCAN0.TMDF148.UINT8[HL]
    8131 #define RSCAN0TMDF148HH RSCAN0.TMDF148.UINT8[HH]
    8132 #define RSCAN0TMID49 RSCAN0.TMID49.UINT32
    8133 #define RSCAN0TMID49L RSCAN0.TMID49.UINT16[L]
    8134 #define RSCAN0TMID49LL RSCAN0.TMID49.UINT8[LL]
    8135 #define RSCAN0TMID49LH RSCAN0.TMID49.UINT8[LH]
    8136 #define RSCAN0TMID49H RSCAN0.TMID49.UINT16[H]
    8137 #define RSCAN0TMID49HL RSCAN0.TMID49.UINT8[HL]
    8138 #define RSCAN0TMID49HH RSCAN0.TMID49.UINT8[HH]
    8139 #define RSCAN0TMPTR49 RSCAN0.TMPTR49.UINT32
    8140 #define RSCAN0TMPTR49L RSCAN0.TMPTR49.UINT16[L]
    8141 #define RSCAN0TMPTR49LL RSCAN0.TMPTR49.UINT8[LL]
    8142 #define RSCAN0TMPTR49LH RSCAN0.TMPTR49.UINT8[LH]
    8143 #define RSCAN0TMPTR49H RSCAN0.TMPTR49.UINT16[H]
    8144 #define RSCAN0TMPTR49HL RSCAN0.TMPTR49.UINT8[HL]
    8145 #define RSCAN0TMPTR49HH RSCAN0.TMPTR49.UINT8[HH]
    8146 #define RSCAN0TMDF049 RSCAN0.TMDF049.UINT32
    8147 #define RSCAN0TMDF049L RSCAN0.TMDF049.UINT16[L]
    8148 #define RSCAN0TMDF049LL RSCAN0.TMDF049.UINT8[LL]
    8149 #define RSCAN0TMDF049LH RSCAN0.TMDF049.UINT8[LH]
    8150 #define RSCAN0TMDF049H RSCAN0.TMDF049.UINT16[H]
    8151 #define RSCAN0TMDF049HL RSCAN0.TMDF049.UINT8[HL]
    8152 #define RSCAN0TMDF049HH RSCAN0.TMDF049.UINT8[HH]
    8153 #define RSCAN0TMDF149 RSCAN0.TMDF149.UINT32
    8154 #define RSCAN0TMDF149L RSCAN0.TMDF149.UINT16[L]
    8155 #define RSCAN0TMDF149LL RSCAN0.TMDF149.UINT8[LL]
    8156 #define RSCAN0TMDF149LH RSCAN0.TMDF149.UINT8[LH]
    8157 #define RSCAN0TMDF149H RSCAN0.TMDF149.UINT16[H]
    8158 #define RSCAN0TMDF149HL RSCAN0.TMDF149.UINT8[HL]
    8159 #define RSCAN0TMDF149HH RSCAN0.TMDF149.UINT8[HH]
    8160 #define RSCAN0TMID50 RSCAN0.TMID50.UINT32
    8161 #define RSCAN0TMID50L RSCAN0.TMID50.UINT16[L]
    8162 #define RSCAN0TMID50LL RSCAN0.TMID50.UINT8[LL]
    8163 #define RSCAN0TMID50LH RSCAN0.TMID50.UINT8[LH]
    8164 #define RSCAN0TMID50H RSCAN0.TMID50.UINT16[H]
    8165 #define RSCAN0TMID50HL RSCAN0.TMID50.UINT8[HL]
    8166 #define RSCAN0TMID50HH RSCAN0.TMID50.UINT8[HH]
    8167 #define RSCAN0TMPTR50 RSCAN0.TMPTR50.UINT32
    8168 #define RSCAN0TMPTR50L RSCAN0.TMPTR50.UINT16[L]
    8169 #define RSCAN0TMPTR50LL RSCAN0.TMPTR50.UINT8[LL]
    8170 #define RSCAN0TMPTR50LH RSCAN0.TMPTR50.UINT8[LH]
    8171 #define RSCAN0TMPTR50H RSCAN0.TMPTR50.UINT16[H]
    8172 #define RSCAN0TMPTR50HL RSCAN0.TMPTR50.UINT8[HL]
    8173 #define RSCAN0TMPTR50HH RSCAN0.TMPTR50.UINT8[HH]
    8174 #define RSCAN0TMDF050 RSCAN0.TMDF050.UINT32
    8175 #define RSCAN0TMDF050L RSCAN0.TMDF050.UINT16[L]
    8176 #define RSCAN0TMDF050LL RSCAN0.TMDF050.UINT8[LL]
    8177 #define RSCAN0TMDF050LH RSCAN0.TMDF050.UINT8[LH]
    8178 #define RSCAN0TMDF050H RSCAN0.TMDF050.UINT16[H]
    8179 #define RSCAN0TMDF050HL RSCAN0.TMDF050.UINT8[HL]
    8180 #define RSCAN0TMDF050HH RSCAN0.TMDF050.UINT8[HH]
    8181 #define RSCAN0TMDF150 RSCAN0.TMDF150.UINT32
    8182 #define RSCAN0TMDF150L RSCAN0.TMDF150.UINT16[L]
    8183 #define RSCAN0TMDF150LL RSCAN0.TMDF150.UINT8[LL]
    8184 #define RSCAN0TMDF150LH RSCAN0.TMDF150.UINT8[LH]
    8185 #define RSCAN0TMDF150H RSCAN0.TMDF150.UINT16[H]
    8186 #define RSCAN0TMDF150HL RSCAN0.TMDF150.UINT8[HL]
    8187 #define RSCAN0TMDF150HH RSCAN0.TMDF150.UINT8[HH]
    8188 #define RSCAN0TMID51 RSCAN0.TMID51.UINT32
    8189 #define RSCAN0TMID51L RSCAN0.TMID51.UINT16[L]
    8190 #define RSCAN0TMID51LL RSCAN0.TMID51.UINT8[LL]
    8191 #define RSCAN0TMID51LH RSCAN0.TMID51.UINT8[LH]
    8192 #define RSCAN0TMID51H RSCAN0.TMID51.UINT16[H]
    8193 #define RSCAN0TMID51HL RSCAN0.TMID51.UINT8[HL]
    8194 #define RSCAN0TMID51HH RSCAN0.TMID51.UINT8[HH]
    8195 #define RSCAN0TMPTR51 RSCAN0.TMPTR51.UINT32
    8196 #define RSCAN0TMPTR51L RSCAN0.TMPTR51.UINT16[L]
    8197 #define RSCAN0TMPTR51LL RSCAN0.TMPTR51.UINT8[LL]
    8198 #define RSCAN0TMPTR51LH RSCAN0.TMPTR51.UINT8[LH]
    8199 #define RSCAN0TMPTR51H RSCAN0.TMPTR51.UINT16[H]
    8200 #define RSCAN0TMPTR51HL RSCAN0.TMPTR51.UINT8[HL]
    8201 #define RSCAN0TMPTR51HH RSCAN0.TMPTR51.UINT8[HH]
    8202 #define RSCAN0TMDF051 RSCAN0.TMDF051.UINT32
    8203 #define RSCAN0TMDF051L RSCAN0.TMDF051.UINT16[L]
    8204 #define RSCAN0TMDF051LL RSCAN0.TMDF051.UINT8[LL]
    8205 #define RSCAN0TMDF051LH RSCAN0.TMDF051.UINT8[LH]
    8206 #define RSCAN0TMDF051H RSCAN0.TMDF051.UINT16[H]
    8207 #define RSCAN0TMDF051HL RSCAN0.TMDF051.UINT8[HL]
    8208 #define RSCAN0TMDF051HH RSCAN0.TMDF051.UINT8[HH]
    8209 #define RSCAN0TMDF151 RSCAN0.TMDF151.UINT32
    8210 #define RSCAN0TMDF151L RSCAN0.TMDF151.UINT16[L]
    8211 #define RSCAN0TMDF151LL RSCAN0.TMDF151.UINT8[LL]
    8212 #define RSCAN0TMDF151LH RSCAN0.TMDF151.UINT8[LH]
    8213 #define RSCAN0TMDF151H RSCAN0.TMDF151.UINT16[H]
    8214 #define RSCAN0TMDF151HL RSCAN0.TMDF151.UINT8[HL]
    8215 #define RSCAN0TMDF151HH RSCAN0.TMDF151.UINT8[HH]
    8216 #define RSCAN0TMID52 RSCAN0.TMID52.UINT32
    8217 #define RSCAN0TMID52L RSCAN0.TMID52.UINT16[L]
    8218 #define RSCAN0TMID52LL RSCAN0.TMID52.UINT8[LL]
    8219 #define RSCAN0TMID52LH RSCAN0.TMID52.UINT8[LH]
    8220 #define RSCAN0TMID52H RSCAN0.TMID52.UINT16[H]
    8221 #define RSCAN0TMID52HL RSCAN0.TMID52.UINT8[HL]
    8222 #define RSCAN0TMID52HH RSCAN0.TMID52.UINT8[HH]
    8223 #define RSCAN0TMPTR52 RSCAN0.TMPTR52.UINT32
    8224 #define RSCAN0TMPTR52L RSCAN0.TMPTR52.UINT16[L]
    8225 #define RSCAN0TMPTR52LL RSCAN0.TMPTR52.UINT8[LL]
    8226 #define RSCAN0TMPTR52LH RSCAN0.TMPTR52.UINT8[LH]
    8227 #define RSCAN0TMPTR52H RSCAN0.TMPTR52.UINT16[H]
    8228 #define RSCAN0TMPTR52HL RSCAN0.TMPTR52.UINT8[HL]
    8229 #define RSCAN0TMPTR52HH RSCAN0.TMPTR52.UINT8[HH]
    8230 #define RSCAN0TMDF052 RSCAN0.TMDF052.UINT32
    8231 #define RSCAN0TMDF052L RSCAN0.TMDF052.UINT16[L]
    8232 #define RSCAN0TMDF052LL RSCAN0.TMDF052.UINT8[LL]
    8233 #define RSCAN0TMDF052LH RSCAN0.TMDF052.UINT8[LH]
    8234 #define RSCAN0TMDF052H RSCAN0.TMDF052.UINT16[H]
    8235 #define RSCAN0TMDF052HL RSCAN0.TMDF052.UINT8[HL]
    8236 #define RSCAN0TMDF052HH RSCAN0.TMDF052.UINT8[HH]
    8237 #define RSCAN0TMDF152 RSCAN0.TMDF152.UINT32
    8238 #define RSCAN0TMDF152L RSCAN0.TMDF152.UINT16[L]
    8239 #define RSCAN0TMDF152LL RSCAN0.TMDF152.UINT8[LL]
    8240 #define RSCAN0TMDF152LH RSCAN0.TMDF152.UINT8[LH]
    8241 #define RSCAN0TMDF152H RSCAN0.TMDF152.UINT16[H]
    8242 #define RSCAN0TMDF152HL RSCAN0.TMDF152.UINT8[HL]
    8243 #define RSCAN0TMDF152HH RSCAN0.TMDF152.UINT8[HH]
    8244 #define RSCAN0TMID53 RSCAN0.TMID53.UINT32
    8245 #define RSCAN0TMID53L RSCAN0.TMID53.UINT16[L]
    8246 #define RSCAN0TMID53LL RSCAN0.TMID53.UINT8[LL]
    8247 #define RSCAN0TMID53LH RSCAN0.TMID53.UINT8[LH]
    8248 #define RSCAN0TMID53H RSCAN0.TMID53.UINT16[H]
    8249 #define RSCAN0TMID53HL RSCAN0.TMID53.UINT8[HL]
    8250 #define RSCAN0TMID53HH RSCAN0.TMID53.UINT8[HH]
    8251 #define RSCAN0TMPTR53 RSCAN0.TMPTR53.UINT32
    8252 #define RSCAN0TMPTR53L RSCAN0.TMPTR53.UINT16[L]
    8253 #define RSCAN0TMPTR53LL RSCAN0.TMPTR53.UINT8[LL]
    8254 #define RSCAN0TMPTR53LH RSCAN0.TMPTR53.UINT8[LH]
    8255 #define RSCAN0TMPTR53H RSCAN0.TMPTR53.UINT16[H]
    8256 #define RSCAN0TMPTR53HL RSCAN0.TMPTR53.UINT8[HL]
    8257 #define RSCAN0TMPTR53HH RSCAN0.TMPTR53.UINT8[HH]
    8258 #define RSCAN0TMDF053 RSCAN0.TMDF053.UINT32
    8259 #define RSCAN0TMDF053L RSCAN0.TMDF053.UINT16[L]
    8260 #define RSCAN0TMDF053LL RSCAN0.TMDF053.UINT8[LL]
    8261 #define RSCAN0TMDF053LH RSCAN0.TMDF053.UINT8[LH]
    8262 #define RSCAN0TMDF053H RSCAN0.TMDF053.UINT16[H]
    8263 #define RSCAN0TMDF053HL RSCAN0.TMDF053.UINT8[HL]
    8264 #define RSCAN0TMDF053HH RSCAN0.TMDF053.UINT8[HH]
    8265 #define RSCAN0TMDF153 RSCAN0.TMDF153.UINT32
    8266 #define RSCAN0TMDF153L RSCAN0.TMDF153.UINT16[L]
    8267 #define RSCAN0TMDF153LL RSCAN0.TMDF153.UINT8[LL]
    8268 #define RSCAN0TMDF153LH RSCAN0.TMDF153.UINT8[LH]
    8269 #define RSCAN0TMDF153H RSCAN0.TMDF153.UINT16[H]
    8270 #define RSCAN0TMDF153HL RSCAN0.TMDF153.UINT8[HL]
    8271 #define RSCAN0TMDF153HH RSCAN0.TMDF153.UINT8[HH]
    8272 #define RSCAN0TMID54 RSCAN0.TMID54.UINT32
    8273 #define RSCAN0TMID54L RSCAN0.TMID54.UINT16[L]
    8274 #define RSCAN0TMID54LL RSCAN0.TMID54.UINT8[LL]
    8275 #define RSCAN0TMID54LH RSCAN0.TMID54.UINT8[LH]
    8276 #define RSCAN0TMID54H RSCAN0.TMID54.UINT16[H]
    8277 #define RSCAN0TMID54HL RSCAN0.TMID54.UINT8[HL]
    8278 #define RSCAN0TMID54HH RSCAN0.TMID54.UINT8[HH]
    8279 #define RSCAN0TMPTR54 RSCAN0.TMPTR54.UINT32
    8280 #define RSCAN0TMPTR54L RSCAN0.TMPTR54.UINT16[L]
    8281 #define RSCAN0TMPTR54LL RSCAN0.TMPTR54.UINT8[LL]
    8282 #define RSCAN0TMPTR54LH RSCAN0.TMPTR54.UINT8[LH]
    8283 #define RSCAN0TMPTR54H RSCAN0.TMPTR54.UINT16[H]
    8284 #define RSCAN0TMPTR54HL RSCAN0.TMPTR54.UINT8[HL]
    8285 #define RSCAN0TMPTR54HH RSCAN0.TMPTR54.UINT8[HH]
    8286 #define RSCAN0TMDF054 RSCAN0.TMDF054.UINT32
    8287 #define RSCAN0TMDF054L RSCAN0.TMDF054.UINT16[L]
    8288 #define RSCAN0TMDF054LL RSCAN0.TMDF054.UINT8[LL]
    8289 #define RSCAN0TMDF054LH RSCAN0.TMDF054.UINT8[LH]
    8290 #define RSCAN0TMDF054H RSCAN0.TMDF054.UINT16[H]
    8291 #define RSCAN0TMDF054HL RSCAN0.TMDF054.UINT8[HL]
    8292 #define RSCAN0TMDF054HH RSCAN0.TMDF054.UINT8[HH]
    8293 #define RSCAN0TMDF154 RSCAN0.TMDF154.UINT32
    8294 #define RSCAN0TMDF154L RSCAN0.TMDF154.UINT16[L]
    8295 #define RSCAN0TMDF154LL RSCAN0.TMDF154.UINT8[LL]
    8296 #define RSCAN0TMDF154LH RSCAN0.TMDF154.UINT8[LH]
    8297 #define RSCAN0TMDF154H RSCAN0.TMDF154.UINT16[H]
    8298 #define RSCAN0TMDF154HL RSCAN0.TMDF154.UINT8[HL]
    8299 #define RSCAN0TMDF154HH RSCAN0.TMDF154.UINT8[HH]
    8300 #define RSCAN0TMID55 RSCAN0.TMID55.UINT32
    8301 #define RSCAN0TMID55L RSCAN0.TMID55.UINT16[L]
    8302 #define RSCAN0TMID55LL RSCAN0.TMID55.UINT8[LL]
    8303 #define RSCAN0TMID55LH RSCAN0.TMID55.UINT8[LH]
    8304 #define RSCAN0TMID55H RSCAN0.TMID55.UINT16[H]
    8305 #define RSCAN0TMID55HL RSCAN0.TMID55.UINT8[HL]
    8306 #define RSCAN0TMID55HH RSCAN0.TMID55.UINT8[HH]
    8307 #define RSCAN0TMPTR55 RSCAN0.TMPTR55.UINT32
    8308 #define RSCAN0TMPTR55L RSCAN0.TMPTR55.UINT16[L]
    8309 #define RSCAN0TMPTR55LL RSCAN0.TMPTR55.UINT8[LL]
    8310 #define RSCAN0TMPTR55LH RSCAN0.TMPTR55.UINT8[LH]
    8311 #define RSCAN0TMPTR55H RSCAN0.TMPTR55.UINT16[H]
    8312 #define RSCAN0TMPTR55HL RSCAN0.TMPTR55.UINT8[HL]
    8313 #define RSCAN0TMPTR55HH RSCAN0.TMPTR55.UINT8[HH]
    8314 #define RSCAN0TMDF055 RSCAN0.TMDF055.UINT32
    8315 #define RSCAN0TMDF055L RSCAN0.TMDF055.UINT16[L]
    8316 #define RSCAN0TMDF055LL RSCAN0.TMDF055.UINT8[LL]
    8317 #define RSCAN0TMDF055LH RSCAN0.TMDF055.UINT8[LH]
    8318 #define RSCAN0TMDF055H RSCAN0.TMDF055.UINT16[H]
    8319 #define RSCAN0TMDF055HL RSCAN0.TMDF055.UINT8[HL]
    8320 #define RSCAN0TMDF055HH RSCAN0.TMDF055.UINT8[HH]
    8321 #define RSCAN0TMDF155 RSCAN0.TMDF155.UINT32
    8322 #define RSCAN0TMDF155L RSCAN0.TMDF155.UINT16[L]
    8323 #define RSCAN0TMDF155LL RSCAN0.TMDF155.UINT8[LL]
    8324 #define RSCAN0TMDF155LH RSCAN0.TMDF155.UINT8[LH]
    8325 #define RSCAN0TMDF155H RSCAN0.TMDF155.UINT16[H]
    8326 #define RSCAN0TMDF155HL RSCAN0.TMDF155.UINT8[HL]
    8327 #define RSCAN0TMDF155HH RSCAN0.TMDF155.UINT8[HH]
    8328 #define RSCAN0TMID56 RSCAN0.TMID56.UINT32
    8329 #define RSCAN0TMID56L RSCAN0.TMID56.UINT16[L]
    8330 #define RSCAN0TMID56LL RSCAN0.TMID56.UINT8[LL]
    8331 #define RSCAN0TMID56LH RSCAN0.TMID56.UINT8[LH]
    8332 #define RSCAN0TMID56H RSCAN0.TMID56.UINT16[H]
    8333 #define RSCAN0TMID56HL RSCAN0.TMID56.UINT8[HL]
    8334 #define RSCAN0TMID56HH RSCAN0.TMID56.UINT8[HH]
    8335 #define RSCAN0TMPTR56 RSCAN0.TMPTR56.UINT32
    8336 #define RSCAN0TMPTR56L RSCAN0.TMPTR56.UINT16[L]
    8337 #define RSCAN0TMPTR56LL RSCAN0.TMPTR56.UINT8[LL]
    8338 #define RSCAN0TMPTR56LH RSCAN0.TMPTR56.UINT8[LH]
    8339 #define RSCAN0TMPTR56H RSCAN0.TMPTR56.UINT16[H]
    8340 #define RSCAN0TMPTR56HL RSCAN0.TMPTR56.UINT8[HL]
    8341 #define RSCAN0TMPTR56HH RSCAN0.TMPTR56.UINT8[HH]
    8342 #define RSCAN0TMDF056 RSCAN0.TMDF056.UINT32
    8343 #define RSCAN0TMDF056L RSCAN0.TMDF056.UINT16[L]
    8344 #define RSCAN0TMDF056LL RSCAN0.TMDF056.UINT8[LL]
    8345 #define RSCAN0TMDF056LH RSCAN0.TMDF056.UINT8[LH]
    8346 #define RSCAN0TMDF056H RSCAN0.TMDF056.UINT16[H]
    8347 #define RSCAN0TMDF056HL RSCAN0.TMDF056.UINT8[HL]
    8348 #define RSCAN0TMDF056HH RSCAN0.TMDF056.UINT8[HH]
    8349 #define RSCAN0TMDF156 RSCAN0.TMDF156.UINT32
    8350 #define RSCAN0TMDF156L RSCAN0.TMDF156.UINT16[L]
    8351 #define RSCAN0TMDF156LL RSCAN0.TMDF156.UINT8[LL]
    8352 #define RSCAN0TMDF156LH RSCAN0.TMDF156.UINT8[LH]
    8353 #define RSCAN0TMDF156H RSCAN0.TMDF156.UINT16[H]
    8354 #define RSCAN0TMDF156HL RSCAN0.TMDF156.UINT8[HL]
    8355 #define RSCAN0TMDF156HH RSCAN0.TMDF156.UINT8[HH]
    8356 #define RSCAN0TMID57 RSCAN0.TMID57.UINT32
    8357 #define RSCAN0TMID57L RSCAN0.TMID57.UINT16[L]
    8358 #define RSCAN0TMID57LL RSCAN0.TMID57.UINT8[LL]
    8359 #define RSCAN0TMID57LH RSCAN0.TMID57.UINT8[LH]
    8360 #define RSCAN0TMID57H RSCAN0.TMID57.UINT16[H]
    8361 #define RSCAN0TMID57HL RSCAN0.TMID57.UINT8[HL]
    8362 #define RSCAN0TMID57HH RSCAN0.TMID57.UINT8[HH]
    8363 #define RSCAN0TMPTR57 RSCAN0.TMPTR57.UINT32
    8364 #define RSCAN0TMPTR57L RSCAN0.TMPTR57.UINT16[L]
    8365 #define RSCAN0TMPTR57LL RSCAN0.TMPTR57.UINT8[LL]
    8366 #define RSCAN0TMPTR57LH RSCAN0.TMPTR57.UINT8[LH]
    8367 #define RSCAN0TMPTR57H RSCAN0.TMPTR57.UINT16[H]
    8368 #define RSCAN0TMPTR57HL RSCAN0.TMPTR57.UINT8[HL]
    8369 #define RSCAN0TMPTR57HH RSCAN0.TMPTR57.UINT8[HH]
    8370 #define RSCAN0TMDF057 RSCAN0.TMDF057.UINT32
    8371 #define RSCAN0TMDF057L RSCAN0.TMDF057.UINT16[L]
    8372 #define RSCAN0TMDF057LL RSCAN0.TMDF057.UINT8[LL]
    8373 #define RSCAN0TMDF057LH RSCAN0.TMDF057.UINT8[LH]
    8374 #define RSCAN0TMDF057H RSCAN0.TMDF057.UINT16[H]
    8375 #define RSCAN0TMDF057HL RSCAN0.TMDF057.UINT8[HL]
    8376 #define RSCAN0TMDF057HH RSCAN0.TMDF057.UINT8[HH]
    8377 #define RSCAN0TMDF157 RSCAN0.TMDF157.UINT32
    8378 #define RSCAN0TMDF157L RSCAN0.TMDF157.UINT16[L]
    8379 #define RSCAN0TMDF157LL RSCAN0.TMDF157.UINT8[LL]
    8380 #define RSCAN0TMDF157LH RSCAN0.TMDF157.UINT8[LH]
    8381 #define RSCAN0TMDF157H RSCAN0.TMDF157.UINT16[H]
    8382 #define RSCAN0TMDF157HL RSCAN0.TMDF157.UINT8[HL]
    8383 #define RSCAN0TMDF157HH RSCAN0.TMDF157.UINT8[HH]
    8384 #define RSCAN0TMID58 RSCAN0.TMID58.UINT32
    8385 #define RSCAN0TMID58L RSCAN0.TMID58.UINT16[L]
    8386 #define RSCAN0TMID58LL RSCAN0.TMID58.UINT8[LL]
    8387 #define RSCAN0TMID58LH RSCAN0.TMID58.UINT8[LH]
    8388 #define RSCAN0TMID58H RSCAN0.TMID58.UINT16[H]
    8389 #define RSCAN0TMID58HL RSCAN0.TMID58.UINT8[HL]
    8390 #define RSCAN0TMID58HH RSCAN0.TMID58.UINT8[HH]
    8391 #define RSCAN0TMPTR58 RSCAN0.TMPTR58.UINT32
    8392 #define RSCAN0TMPTR58L RSCAN0.TMPTR58.UINT16[L]
    8393 #define RSCAN0TMPTR58LL RSCAN0.TMPTR58.UINT8[LL]
    8394 #define RSCAN0TMPTR58LH RSCAN0.TMPTR58.UINT8[LH]
    8395 #define RSCAN0TMPTR58H RSCAN0.TMPTR58.UINT16[H]
    8396 #define RSCAN0TMPTR58HL RSCAN0.TMPTR58.UINT8[HL]
    8397 #define RSCAN0TMPTR58HH RSCAN0.TMPTR58.UINT8[HH]
    8398 #define RSCAN0TMDF058 RSCAN0.TMDF058.UINT32
    8399 #define RSCAN0TMDF058L RSCAN0.TMDF058.UINT16[L]
    8400 #define RSCAN0TMDF058LL RSCAN0.TMDF058.UINT8[LL]
    8401 #define RSCAN0TMDF058LH RSCAN0.TMDF058.UINT8[LH]
    8402 #define RSCAN0TMDF058H RSCAN0.TMDF058.UINT16[H]
    8403 #define RSCAN0TMDF058HL RSCAN0.TMDF058.UINT8[HL]
    8404 #define RSCAN0TMDF058HH RSCAN0.TMDF058.UINT8[HH]
    8405 #define RSCAN0TMDF158 RSCAN0.TMDF158.UINT32
    8406 #define RSCAN0TMDF158L RSCAN0.TMDF158.UINT16[L]
    8407 #define RSCAN0TMDF158LL RSCAN0.TMDF158.UINT8[LL]
    8408 #define RSCAN0TMDF158LH RSCAN0.TMDF158.UINT8[LH]
    8409 #define RSCAN0TMDF158H RSCAN0.TMDF158.UINT16[H]
    8410 #define RSCAN0TMDF158HL RSCAN0.TMDF158.UINT8[HL]
    8411 #define RSCAN0TMDF158HH RSCAN0.TMDF158.UINT8[HH]
    8412 #define RSCAN0TMID59 RSCAN0.TMID59.UINT32
    8413 #define RSCAN0TMID59L RSCAN0.TMID59.UINT16[L]
    8414 #define RSCAN0TMID59LL RSCAN0.TMID59.UINT8[LL]
    8415 #define RSCAN0TMID59LH RSCAN0.TMID59.UINT8[LH]
    8416 #define RSCAN0TMID59H RSCAN0.TMID59.UINT16[H]
    8417 #define RSCAN0TMID59HL RSCAN0.TMID59.UINT8[HL]
    8418 #define RSCAN0TMID59HH RSCAN0.TMID59.UINT8[HH]
    8419 #define RSCAN0TMPTR59 RSCAN0.TMPTR59.UINT32
    8420 #define RSCAN0TMPTR59L RSCAN0.TMPTR59.UINT16[L]
    8421 #define RSCAN0TMPTR59LL RSCAN0.TMPTR59.UINT8[LL]
    8422 #define RSCAN0TMPTR59LH RSCAN0.TMPTR59.UINT8[LH]
    8423 #define RSCAN0TMPTR59H RSCAN0.TMPTR59.UINT16[H]
    8424 #define RSCAN0TMPTR59HL RSCAN0.TMPTR59.UINT8[HL]
    8425 #define RSCAN0TMPTR59HH RSCAN0.TMPTR59.UINT8[HH]
    8426 #define RSCAN0TMDF059 RSCAN0.TMDF059.UINT32
    8427 #define RSCAN0TMDF059L RSCAN0.TMDF059.UINT16[L]
    8428 #define RSCAN0TMDF059LL RSCAN0.TMDF059.UINT8[LL]
    8429 #define RSCAN0TMDF059LH RSCAN0.TMDF059.UINT8[LH]
    8430 #define RSCAN0TMDF059H RSCAN0.TMDF059.UINT16[H]
    8431 #define RSCAN0TMDF059HL RSCAN0.TMDF059.UINT8[HL]
    8432 #define RSCAN0TMDF059HH RSCAN0.TMDF059.UINT8[HH]
    8433 #define RSCAN0TMDF159 RSCAN0.TMDF159.UINT32
    8434 #define RSCAN0TMDF159L RSCAN0.TMDF159.UINT16[L]
    8435 #define RSCAN0TMDF159LL RSCAN0.TMDF159.UINT8[LL]
    8436 #define RSCAN0TMDF159LH RSCAN0.TMDF159.UINT8[LH]
    8437 #define RSCAN0TMDF159H RSCAN0.TMDF159.UINT16[H]
    8438 #define RSCAN0TMDF159HL RSCAN0.TMDF159.UINT8[HL]
    8439 #define RSCAN0TMDF159HH RSCAN0.TMDF159.UINT8[HH]
    8440 #define RSCAN0TMID60 RSCAN0.TMID60.UINT32
    8441 #define RSCAN0TMID60L RSCAN0.TMID60.UINT16[L]
    8442 #define RSCAN0TMID60LL RSCAN0.TMID60.UINT8[LL]
    8443 #define RSCAN0TMID60LH RSCAN0.TMID60.UINT8[LH]
    8444 #define RSCAN0TMID60H RSCAN0.TMID60.UINT16[H]
    8445 #define RSCAN0TMID60HL RSCAN0.TMID60.UINT8[HL]
    8446 #define RSCAN0TMID60HH RSCAN0.TMID60.UINT8[HH]
    8447 #define RSCAN0TMPTR60 RSCAN0.TMPTR60.UINT32
    8448 #define RSCAN0TMPTR60L RSCAN0.TMPTR60.UINT16[L]
    8449 #define RSCAN0TMPTR60LL RSCAN0.TMPTR60.UINT8[LL]
    8450 #define RSCAN0TMPTR60LH RSCAN0.TMPTR60.UINT8[LH]
    8451 #define RSCAN0TMPTR60H RSCAN0.TMPTR60.UINT16[H]
    8452 #define RSCAN0TMPTR60HL RSCAN0.TMPTR60.UINT8[HL]
    8453 #define RSCAN0TMPTR60HH RSCAN0.TMPTR60.UINT8[HH]
    8454 #define RSCAN0TMDF060 RSCAN0.TMDF060.UINT32
    8455 #define RSCAN0TMDF060L RSCAN0.TMDF060.UINT16[L]
    8456 #define RSCAN0TMDF060LL RSCAN0.TMDF060.UINT8[LL]
    8457 #define RSCAN0TMDF060LH RSCAN0.TMDF060.UINT8[LH]
    8458 #define RSCAN0TMDF060H RSCAN0.TMDF060.UINT16[H]
    8459 #define RSCAN0TMDF060HL RSCAN0.TMDF060.UINT8[HL]
    8460 #define RSCAN0TMDF060HH RSCAN0.TMDF060.UINT8[HH]
    8461 #define RSCAN0TMDF160 RSCAN0.TMDF160.UINT32
    8462 #define RSCAN0TMDF160L RSCAN0.TMDF160.UINT16[L]
    8463 #define RSCAN0TMDF160LL RSCAN0.TMDF160.UINT8[LL]
    8464 #define RSCAN0TMDF160LH RSCAN0.TMDF160.UINT8[LH]
    8465 #define RSCAN0TMDF160H RSCAN0.TMDF160.UINT16[H]
    8466 #define RSCAN0TMDF160HL RSCAN0.TMDF160.UINT8[HL]
    8467 #define RSCAN0TMDF160HH RSCAN0.TMDF160.UINT8[HH]
    8468 #define RSCAN0TMID61 RSCAN0.TMID61.UINT32
    8469 #define RSCAN0TMID61L RSCAN0.TMID61.UINT16[L]
    8470 #define RSCAN0TMID61LL RSCAN0.TMID61.UINT8[LL]
    8471 #define RSCAN0TMID61LH RSCAN0.TMID61.UINT8[LH]
    8472 #define RSCAN0TMID61H RSCAN0.TMID61.UINT16[H]
    8473 #define RSCAN0TMID61HL RSCAN0.TMID61.UINT8[HL]
    8474 #define RSCAN0TMID61HH RSCAN0.TMID61.UINT8[HH]
    8475 #define RSCAN0TMPTR61 RSCAN0.TMPTR61.UINT32
    8476 #define RSCAN0TMPTR61L RSCAN0.TMPTR61.UINT16[L]
    8477 #define RSCAN0TMPTR61LL RSCAN0.TMPTR61.UINT8[LL]
    8478 #define RSCAN0TMPTR61LH RSCAN0.TMPTR61.UINT8[LH]
    8479 #define RSCAN0TMPTR61H RSCAN0.TMPTR61.UINT16[H]
    8480 #define RSCAN0TMPTR61HL RSCAN0.TMPTR61.UINT8[HL]
    8481 #define RSCAN0TMPTR61HH RSCAN0.TMPTR61.UINT8[HH]
    8482 #define RSCAN0TMDF061 RSCAN0.TMDF061.UINT32
    8483 #define RSCAN0TMDF061L RSCAN0.TMDF061.UINT16[L]
    8484 #define RSCAN0TMDF061LL RSCAN0.TMDF061.UINT8[LL]
    8485 #define RSCAN0TMDF061LH RSCAN0.TMDF061.UINT8[LH]
    8486 #define RSCAN0TMDF061H RSCAN0.TMDF061.UINT16[H]
    8487 #define RSCAN0TMDF061HL RSCAN0.TMDF061.UINT8[HL]
    8488 #define RSCAN0TMDF061HH RSCAN0.TMDF061.UINT8[HH]
    8489 #define RSCAN0TMDF161 RSCAN0.TMDF161.UINT32
    8490 #define RSCAN0TMDF161L RSCAN0.TMDF161.UINT16[L]
    8491 #define RSCAN0TMDF161LL RSCAN0.TMDF161.UINT8[LL]
    8492 #define RSCAN0TMDF161LH RSCAN0.TMDF161.UINT8[LH]
    8493 #define RSCAN0TMDF161H RSCAN0.TMDF161.UINT16[H]
    8494 #define RSCAN0TMDF161HL RSCAN0.TMDF161.UINT8[HL]
    8495 #define RSCAN0TMDF161HH RSCAN0.TMDF161.UINT8[HH]
    8496 #define RSCAN0TMID62 RSCAN0.TMID62.UINT32
    8497 #define RSCAN0TMID62L RSCAN0.TMID62.UINT16[L]
    8498 #define RSCAN0TMID62LL RSCAN0.TMID62.UINT8[LL]
    8499 #define RSCAN0TMID62LH RSCAN0.TMID62.UINT8[LH]
    8500 #define RSCAN0TMID62H RSCAN0.TMID62.UINT16[H]
    8501 #define RSCAN0TMID62HL RSCAN0.TMID62.UINT8[HL]
    8502 #define RSCAN0TMID62HH RSCAN0.TMID62.UINT8[HH]
    8503 #define RSCAN0TMPTR62 RSCAN0.TMPTR62.UINT32
    8504 #define RSCAN0TMPTR62L RSCAN0.TMPTR62.UINT16[L]
    8505 #define RSCAN0TMPTR62LL RSCAN0.TMPTR62.UINT8[LL]
    8506 #define RSCAN0TMPTR62LH RSCAN0.TMPTR62.UINT8[LH]
    8507 #define RSCAN0TMPTR62H RSCAN0.TMPTR62.UINT16[H]
    8508 #define RSCAN0TMPTR62HL RSCAN0.TMPTR62.UINT8[HL]
    8509 #define RSCAN0TMPTR62HH RSCAN0.TMPTR62.UINT8[HH]
    8510 #define RSCAN0TMDF062 RSCAN0.TMDF062.UINT32
    8511 #define RSCAN0TMDF062L RSCAN0.TMDF062.UINT16[L]
    8512 #define RSCAN0TMDF062LL RSCAN0.TMDF062.UINT8[LL]
    8513 #define RSCAN0TMDF062LH RSCAN0.TMDF062.UINT8[LH]
    8514 #define RSCAN0TMDF062H RSCAN0.TMDF062.UINT16[H]
    8515 #define RSCAN0TMDF062HL RSCAN0.TMDF062.UINT8[HL]
    8516 #define RSCAN0TMDF062HH RSCAN0.TMDF062.UINT8[HH]
    8517 #define RSCAN0TMDF162 RSCAN0.TMDF162.UINT32
    8518 #define RSCAN0TMDF162L RSCAN0.TMDF162.UINT16[L]
    8519 #define RSCAN0TMDF162LL RSCAN0.TMDF162.UINT8[LL]
    8520 #define RSCAN0TMDF162LH RSCAN0.TMDF162.UINT8[LH]
    8521 #define RSCAN0TMDF162H RSCAN0.TMDF162.UINT16[H]
    8522 #define RSCAN0TMDF162HL RSCAN0.TMDF162.UINT8[HL]
    8523 #define RSCAN0TMDF162HH RSCAN0.TMDF162.UINT8[HH]
    8524 #define RSCAN0TMID63 RSCAN0.TMID63.UINT32
    8525 #define RSCAN0TMID63L RSCAN0.TMID63.UINT16[L]
    8526 #define RSCAN0TMID63LL RSCAN0.TMID63.UINT8[LL]
    8527 #define RSCAN0TMID63LH RSCAN0.TMID63.UINT8[LH]
    8528 #define RSCAN0TMID63H RSCAN0.TMID63.UINT16[H]
    8529 #define RSCAN0TMID63HL RSCAN0.TMID63.UINT8[HL]
    8530 #define RSCAN0TMID63HH RSCAN0.TMID63.UINT8[HH]
    8531 #define RSCAN0TMPTR63 RSCAN0.TMPTR63.UINT32
    8532 #define RSCAN0TMPTR63L RSCAN0.TMPTR63.UINT16[L]
    8533 #define RSCAN0TMPTR63LL RSCAN0.TMPTR63.UINT8[LL]
    8534 #define RSCAN0TMPTR63LH RSCAN0.TMPTR63.UINT8[LH]
    8535 #define RSCAN0TMPTR63H RSCAN0.TMPTR63.UINT16[H]
    8536 #define RSCAN0TMPTR63HL RSCAN0.TMPTR63.UINT8[HL]
    8537 #define RSCAN0TMPTR63HH RSCAN0.TMPTR63.UINT8[HH]
    8538 #define RSCAN0TMDF063 RSCAN0.TMDF063.UINT32
    8539 #define RSCAN0TMDF063L RSCAN0.TMDF063.UINT16[L]
    8540 #define RSCAN0TMDF063LL RSCAN0.TMDF063.UINT8[LL]
    8541 #define RSCAN0TMDF063LH RSCAN0.TMDF063.UINT8[LH]
    8542 #define RSCAN0TMDF063H RSCAN0.TMDF063.UINT16[H]
    8543 #define RSCAN0TMDF063HL RSCAN0.TMDF063.UINT8[HL]
    8544 #define RSCAN0TMDF063HH RSCAN0.TMDF063.UINT8[HH]
    8545 #define RSCAN0TMDF163 RSCAN0.TMDF163.UINT32
    8546 #define RSCAN0TMDF163L RSCAN0.TMDF163.UINT16[L]
    8547 #define RSCAN0TMDF163LL RSCAN0.TMDF163.UINT8[LL]
    8548 #define RSCAN0TMDF163LH RSCAN0.TMDF163.UINT8[LH]
    8549 #define RSCAN0TMDF163H RSCAN0.TMDF163.UINT16[H]
    8550 #define RSCAN0TMDF163HL RSCAN0.TMDF163.UINT8[HL]
    8551 #define RSCAN0TMDF163HH RSCAN0.TMDF163.UINT8[HH]
    8552 #define RSCAN0TMID64 RSCAN0.TMID64.UINT32
    8553 #define RSCAN0TMID64L RSCAN0.TMID64.UINT16[L]
    8554 #define RSCAN0TMID64LL RSCAN0.TMID64.UINT8[LL]
    8555 #define RSCAN0TMID64LH RSCAN0.TMID64.UINT8[LH]
    8556 #define RSCAN0TMID64H RSCAN0.TMID64.UINT16[H]
    8557 #define RSCAN0TMID64HL RSCAN0.TMID64.UINT8[HL]
    8558 #define RSCAN0TMID64HH RSCAN0.TMID64.UINT8[HH]
    8559 #define RSCAN0TMPTR64 RSCAN0.TMPTR64.UINT32
    8560 #define RSCAN0TMPTR64L RSCAN0.TMPTR64.UINT16[L]
    8561 #define RSCAN0TMPTR64LL RSCAN0.TMPTR64.UINT8[LL]
    8562 #define RSCAN0TMPTR64LH RSCAN0.TMPTR64.UINT8[LH]
    8563 #define RSCAN0TMPTR64H RSCAN0.TMPTR64.UINT16[H]
    8564 #define RSCAN0TMPTR64HL RSCAN0.TMPTR64.UINT8[HL]
    8565 #define RSCAN0TMPTR64HH RSCAN0.TMPTR64.UINT8[HH]
    8566 #define RSCAN0TMDF064 RSCAN0.TMDF064.UINT32
    8567 #define RSCAN0TMDF064L RSCAN0.TMDF064.UINT16[L]
    8568 #define RSCAN0TMDF064LL RSCAN0.TMDF064.UINT8[LL]
    8569 #define RSCAN0TMDF064LH RSCAN0.TMDF064.UINT8[LH]
    8570 #define RSCAN0TMDF064H RSCAN0.TMDF064.UINT16[H]
    8571 #define RSCAN0TMDF064HL RSCAN0.TMDF064.UINT8[HL]
    8572 #define RSCAN0TMDF064HH RSCAN0.TMDF064.UINT8[HH]
    8573 #define RSCAN0TMDF164 RSCAN0.TMDF164.UINT32
    8574 #define RSCAN0TMDF164L RSCAN0.TMDF164.UINT16[L]
    8575 #define RSCAN0TMDF164LL RSCAN0.TMDF164.UINT8[LL]
    8576 #define RSCAN0TMDF164LH RSCAN0.TMDF164.UINT8[LH]
    8577 #define RSCAN0TMDF164H RSCAN0.TMDF164.UINT16[H]
    8578 #define RSCAN0TMDF164HL RSCAN0.TMDF164.UINT8[HL]
    8579 #define RSCAN0TMDF164HH RSCAN0.TMDF164.UINT8[HH]
    8580 #define RSCAN0TMID65 RSCAN0.TMID65.UINT32
    8581 #define RSCAN0TMID65L RSCAN0.TMID65.UINT16[L]
    8582 #define RSCAN0TMID65LL RSCAN0.TMID65.UINT8[LL]
    8583 #define RSCAN0TMID65LH RSCAN0.TMID65.UINT8[LH]
    8584 #define RSCAN0TMID65H RSCAN0.TMID65.UINT16[H]
    8585 #define RSCAN0TMID65HL RSCAN0.TMID65.UINT8[HL]
    8586 #define RSCAN0TMID65HH RSCAN0.TMID65.UINT8[HH]
    8587 #define RSCAN0TMPTR65 RSCAN0.TMPTR65.UINT32
    8588 #define RSCAN0TMPTR65L RSCAN0.TMPTR65.UINT16[L]
    8589 #define RSCAN0TMPTR65LL RSCAN0.TMPTR65.UINT8[LL]
    8590 #define RSCAN0TMPTR65LH RSCAN0.TMPTR65.UINT8[LH]
    8591 #define RSCAN0TMPTR65H RSCAN0.TMPTR65.UINT16[H]
    8592 #define RSCAN0TMPTR65HL RSCAN0.TMPTR65.UINT8[HL]
    8593 #define RSCAN0TMPTR65HH RSCAN0.TMPTR65.UINT8[HH]
    8594 #define RSCAN0TMDF065 RSCAN0.TMDF065.UINT32
    8595 #define RSCAN0TMDF065L RSCAN0.TMDF065.UINT16[L]
    8596 #define RSCAN0TMDF065LL RSCAN0.TMDF065.UINT8[LL]
    8597 #define RSCAN0TMDF065LH RSCAN0.TMDF065.UINT8[LH]
    8598 #define RSCAN0TMDF065H RSCAN0.TMDF065.UINT16[H]
    8599 #define RSCAN0TMDF065HL RSCAN0.TMDF065.UINT8[HL]
    8600 #define RSCAN0TMDF065HH RSCAN0.TMDF065.UINT8[HH]
    8601 #define RSCAN0TMDF165 RSCAN0.TMDF165.UINT32
    8602 #define RSCAN0TMDF165L RSCAN0.TMDF165.UINT16[L]
    8603 #define RSCAN0TMDF165LL RSCAN0.TMDF165.UINT8[LL]
    8604 #define RSCAN0TMDF165LH RSCAN0.TMDF165.UINT8[LH]
    8605 #define RSCAN0TMDF165H RSCAN0.TMDF165.UINT16[H]
    8606 #define RSCAN0TMDF165HL RSCAN0.TMDF165.UINT8[HL]
    8607 #define RSCAN0TMDF165HH RSCAN0.TMDF165.UINT8[HH]
    8608 #define RSCAN0TMID66 RSCAN0.TMID66.UINT32
    8609 #define RSCAN0TMID66L RSCAN0.TMID66.UINT16[L]
    8610 #define RSCAN0TMID66LL RSCAN0.TMID66.UINT8[LL]
    8611 #define RSCAN0TMID66LH RSCAN0.TMID66.UINT8[LH]
    8612 #define RSCAN0TMID66H RSCAN0.TMID66.UINT16[H]
    8613 #define RSCAN0TMID66HL RSCAN0.TMID66.UINT8[HL]
    8614 #define RSCAN0TMID66HH RSCAN0.TMID66.UINT8[HH]
    8615 #define RSCAN0TMPTR66 RSCAN0.TMPTR66.UINT32
    8616 #define RSCAN0TMPTR66L RSCAN0.TMPTR66.UINT16[L]
    8617 #define RSCAN0TMPTR66LL RSCAN0.TMPTR66.UINT8[LL]
    8618 #define RSCAN0TMPTR66LH RSCAN0.TMPTR66.UINT8[LH]
    8619 #define RSCAN0TMPTR66H RSCAN0.TMPTR66.UINT16[H]
    8620 #define RSCAN0TMPTR66HL RSCAN0.TMPTR66.UINT8[HL]
    8621 #define RSCAN0TMPTR66HH RSCAN0.TMPTR66.UINT8[HH]
    8622 #define RSCAN0TMDF066 RSCAN0.TMDF066.UINT32
    8623 #define RSCAN0TMDF066L RSCAN0.TMDF066.UINT16[L]
    8624 #define RSCAN0TMDF066LL RSCAN0.TMDF066.UINT8[LL]
    8625 #define RSCAN0TMDF066LH RSCAN0.TMDF066.UINT8[LH]
    8626 #define RSCAN0TMDF066H RSCAN0.TMDF066.UINT16[H]
    8627 #define RSCAN0TMDF066HL RSCAN0.TMDF066.UINT8[HL]
    8628 #define RSCAN0TMDF066HH RSCAN0.TMDF066.UINT8[HH]
    8629 #define RSCAN0TMDF166 RSCAN0.TMDF166.UINT32
    8630 #define RSCAN0TMDF166L RSCAN0.TMDF166.UINT16[L]
    8631 #define RSCAN0TMDF166LL RSCAN0.TMDF166.UINT8[LL]
    8632 #define RSCAN0TMDF166LH RSCAN0.TMDF166.UINT8[LH]
    8633 #define RSCAN0TMDF166H RSCAN0.TMDF166.UINT16[H]
    8634 #define RSCAN0TMDF166HL RSCAN0.TMDF166.UINT8[HL]
    8635 #define RSCAN0TMDF166HH RSCAN0.TMDF166.UINT8[HH]
    8636 #define RSCAN0TMID67 RSCAN0.TMID67.UINT32
    8637 #define RSCAN0TMID67L RSCAN0.TMID67.UINT16[L]
    8638 #define RSCAN0TMID67LL RSCAN0.TMID67.UINT8[LL]
    8639 #define RSCAN0TMID67LH RSCAN0.TMID67.UINT8[LH]
    8640 #define RSCAN0TMID67H RSCAN0.TMID67.UINT16[H]
    8641 #define RSCAN0TMID67HL RSCAN0.TMID67.UINT8[HL]
    8642 #define RSCAN0TMID67HH RSCAN0.TMID67.UINT8[HH]
    8643 #define RSCAN0TMPTR67 RSCAN0.TMPTR67.UINT32
    8644 #define RSCAN0TMPTR67L RSCAN0.TMPTR67.UINT16[L]
    8645 #define RSCAN0TMPTR67LL RSCAN0.TMPTR67.UINT8[LL]
    8646 #define RSCAN0TMPTR67LH RSCAN0.TMPTR67.UINT8[LH]
    8647 #define RSCAN0TMPTR67H RSCAN0.TMPTR67.UINT16[H]
    8648 #define RSCAN0TMPTR67HL RSCAN0.TMPTR67.UINT8[HL]
    8649 #define RSCAN0TMPTR67HH RSCAN0.TMPTR67.UINT8[HH]
    8650 #define RSCAN0TMDF067 RSCAN0.TMDF067.UINT32
    8651 #define RSCAN0TMDF067L RSCAN0.TMDF067.UINT16[L]
    8652 #define RSCAN0TMDF067LL RSCAN0.TMDF067.UINT8[LL]
    8653 #define RSCAN0TMDF067LH RSCAN0.TMDF067.UINT8[LH]
    8654 #define RSCAN0TMDF067H RSCAN0.TMDF067.UINT16[H]
    8655 #define RSCAN0TMDF067HL RSCAN0.TMDF067.UINT8[HL]
    8656 #define RSCAN0TMDF067HH RSCAN0.TMDF067.UINT8[HH]
    8657 #define RSCAN0TMDF167 RSCAN0.TMDF167.UINT32
    8658 #define RSCAN0TMDF167L RSCAN0.TMDF167.UINT16[L]
    8659 #define RSCAN0TMDF167LL RSCAN0.TMDF167.UINT8[LL]
    8660 #define RSCAN0TMDF167LH RSCAN0.TMDF167.UINT8[LH]
    8661 #define RSCAN0TMDF167H RSCAN0.TMDF167.UINT16[H]
    8662 #define RSCAN0TMDF167HL RSCAN0.TMDF167.UINT8[HL]
    8663 #define RSCAN0TMDF167HH RSCAN0.TMDF167.UINT8[HH]
    8664 #define RSCAN0TMID68 RSCAN0.TMID68.UINT32
    8665 #define RSCAN0TMID68L RSCAN0.TMID68.UINT16[L]
    8666 #define RSCAN0TMID68LL RSCAN0.TMID68.UINT8[LL]
    8667 #define RSCAN0TMID68LH RSCAN0.TMID68.UINT8[LH]
    8668 #define RSCAN0TMID68H RSCAN0.TMID68.UINT16[H]
    8669 #define RSCAN0TMID68HL RSCAN0.TMID68.UINT8[HL]
    8670 #define RSCAN0TMID68HH RSCAN0.TMID68.UINT8[HH]
    8671 #define RSCAN0TMPTR68 RSCAN0.TMPTR68.UINT32
    8672 #define RSCAN0TMPTR68L RSCAN0.TMPTR68.UINT16[L]
    8673 #define RSCAN0TMPTR68LL RSCAN0.TMPTR68.UINT8[LL]
    8674 #define RSCAN0TMPTR68LH RSCAN0.TMPTR68.UINT8[LH]
    8675 #define RSCAN0TMPTR68H RSCAN0.TMPTR68.UINT16[H]
    8676 #define RSCAN0TMPTR68HL RSCAN0.TMPTR68.UINT8[HL]
    8677 #define RSCAN0TMPTR68HH RSCAN0.TMPTR68.UINT8[HH]
    8678 #define RSCAN0TMDF068 RSCAN0.TMDF068.UINT32
    8679 #define RSCAN0TMDF068L RSCAN0.TMDF068.UINT16[L]
    8680 #define RSCAN0TMDF068LL RSCAN0.TMDF068.UINT8[LL]
    8681 #define RSCAN0TMDF068LH RSCAN0.TMDF068.UINT8[LH]
    8682 #define RSCAN0TMDF068H RSCAN0.TMDF068.UINT16[H]
    8683 #define RSCAN0TMDF068HL RSCAN0.TMDF068.UINT8[HL]
    8684 #define RSCAN0TMDF068HH RSCAN0.TMDF068.UINT8[HH]
    8685 #define RSCAN0TMDF168 RSCAN0.TMDF168.UINT32
    8686 #define RSCAN0TMDF168L RSCAN0.TMDF168.UINT16[L]
    8687 #define RSCAN0TMDF168LL RSCAN0.TMDF168.UINT8[LL]
    8688 #define RSCAN0TMDF168LH RSCAN0.TMDF168.UINT8[LH]
    8689 #define RSCAN0TMDF168H RSCAN0.TMDF168.UINT16[H]
    8690 #define RSCAN0TMDF168HL RSCAN0.TMDF168.UINT8[HL]
    8691 #define RSCAN0TMDF168HH RSCAN0.TMDF168.UINT8[HH]
    8692 #define RSCAN0TMID69 RSCAN0.TMID69.UINT32
    8693 #define RSCAN0TMID69L RSCAN0.TMID69.UINT16[L]
    8694 #define RSCAN0TMID69LL RSCAN0.TMID69.UINT8[LL]
    8695 #define RSCAN0TMID69LH RSCAN0.TMID69.UINT8[LH]
    8696 #define RSCAN0TMID69H RSCAN0.TMID69.UINT16[H]
    8697 #define RSCAN0TMID69HL RSCAN0.TMID69.UINT8[HL]
    8698 #define RSCAN0TMID69HH RSCAN0.TMID69.UINT8[HH]
    8699 #define RSCAN0TMPTR69 RSCAN0.TMPTR69.UINT32
    8700 #define RSCAN0TMPTR69L RSCAN0.TMPTR69.UINT16[L]
    8701 #define RSCAN0TMPTR69LL RSCAN0.TMPTR69.UINT8[LL]
    8702 #define RSCAN0TMPTR69LH RSCAN0.TMPTR69.UINT8[LH]
    8703 #define RSCAN0TMPTR69H RSCAN0.TMPTR69.UINT16[H]
    8704 #define RSCAN0TMPTR69HL RSCAN0.TMPTR69.UINT8[HL]
    8705 #define RSCAN0TMPTR69HH RSCAN0.TMPTR69.UINT8[HH]
    8706 #define RSCAN0TMDF069 RSCAN0.TMDF069.UINT32
    8707 #define RSCAN0TMDF069L RSCAN0.TMDF069.UINT16[L]
    8708 #define RSCAN0TMDF069LL RSCAN0.TMDF069.UINT8[LL]
    8709 #define RSCAN0TMDF069LH RSCAN0.TMDF069.UINT8[LH]
    8710 #define RSCAN0TMDF069H RSCAN0.TMDF069.UINT16[H]
    8711 #define RSCAN0TMDF069HL RSCAN0.TMDF069.UINT8[HL]
    8712 #define RSCAN0TMDF069HH RSCAN0.TMDF069.UINT8[HH]
    8713 #define RSCAN0TMDF169 RSCAN0.TMDF169.UINT32
    8714 #define RSCAN0TMDF169L RSCAN0.TMDF169.UINT16[L]
    8715 #define RSCAN0TMDF169LL RSCAN0.TMDF169.UINT8[LL]
    8716 #define RSCAN0TMDF169LH RSCAN0.TMDF169.UINT8[LH]
    8717 #define RSCAN0TMDF169H RSCAN0.TMDF169.UINT16[H]
    8718 #define RSCAN0TMDF169HL RSCAN0.TMDF169.UINT8[HL]
    8719 #define RSCAN0TMDF169HH RSCAN0.TMDF169.UINT8[HH]
    8720 #define RSCAN0TMID70 RSCAN0.TMID70.UINT32
    8721 #define RSCAN0TMID70L RSCAN0.TMID70.UINT16[L]
    8722 #define RSCAN0TMID70LL RSCAN0.TMID70.UINT8[LL]
    8723 #define RSCAN0TMID70LH RSCAN0.TMID70.UINT8[LH]
    8724 #define RSCAN0TMID70H RSCAN0.TMID70.UINT16[H]
    8725 #define RSCAN0TMID70HL RSCAN0.TMID70.UINT8[HL]
    8726 #define RSCAN0TMID70HH RSCAN0.TMID70.UINT8[HH]
    8727 #define RSCAN0TMPTR70 RSCAN0.TMPTR70.UINT32
    8728 #define RSCAN0TMPTR70L RSCAN0.TMPTR70.UINT16[L]
    8729 #define RSCAN0TMPTR70LL RSCAN0.TMPTR70.UINT8[LL]
    8730 #define RSCAN0TMPTR70LH RSCAN0.TMPTR70.UINT8[LH]
    8731 #define RSCAN0TMPTR70H RSCAN0.TMPTR70.UINT16[H]
    8732 #define RSCAN0TMPTR70HL RSCAN0.TMPTR70.UINT8[HL]
    8733 #define RSCAN0TMPTR70HH RSCAN0.TMPTR70.UINT8[HH]
    8734 #define RSCAN0TMDF070 RSCAN0.TMDF070.UINT32
    8735 #define RSCAN0TMDF070L RSCAN0.TMDF070.UINT16[L]
    8736 #define RSCAN0TMDF070LL RSCAN0.TMDF070.UINT8[LL]
    8737 #define RSCAN0TMDF070LH RSCAN0.TMDF070.UINT8[LH]
    8738 #define RSCAN0TMDF070H RSCAN0.TMDF070.UINT16[H]
    8739 #define RSCAN0TMDF070HL RSCAN0.TMDF070.UINT8[HL]
    8740 #define RSCAN0TMDF070HH RSCAN0.TMDF070.UINT8[HH]
    8741 #define RSCAN0TMDF170 RSCAN0.TMDF170.UINT32
    8742 #define RSCAN0TMDF170L RSCAN0.TMDF170.UINT16[L]
    8743 #define RSCAN0TMDF170LL RSCAN0.TMDF170.UINT8[LL]
    8744 #define RSCAN0TMDF170LH RSCAN0.TMDF170.UINT8[LH]
    8745 #define RSCAN0TMDF170H RSCAN0.TMDF170.UINT16[H]
    8746 #define RSCAN0TMDF170HL RSCAN0.TMDF170.UINT8[HL]
    8747 #define RSCAN0TMDF170HH RSCAN0.TMDF170.UINT8[HH]
    8748 #define RSCAN0TMID71 RSCAN0.TMID71.UINT32
    8749 #define RSCAN0TMID71L RSCAN0.TMID71.UINT16[L]
    8750 #define RSCAN0TMID71LL RSCAN0.TMID71.UINT8[LL]
    8751 #define RSCAN0TMID71LH RSCAN0.TMID71.UINT8[LH]
    8752 #define RSCAN0TMID71H RSCAN0.TMID71.UINT16[H]
    8753 #define RSCAN0TMID71HL RSCAN0.TMID71.UINT8[HL]
    8754 #define RSCAN0TMID71HH RSCAN0.TMID71.UINT8[HH]
    8755 #define RSCAN0TMPTR71 RSCAN0.TMPTR71.UINT32
    8756 #define RSCAN0TMPTR71L RSCAN0.TMPTR71.UINT16[L]
    8757 #define RSCAN0TMPTR71LL RSCAN0.TMPTR71.UINT8[LL]
    8758 #define RSCAN0TMPTR71LH RSCAN0.TMPTR71.UINT8[LH]
    8759 #define RSCAN0TMPTR71H RSCAN0.TMPTR71.UINT16[H]
    8760 #define RSCAN0TMPTR71HL RSCAN0.TMPTR71.UINT8[HL]
    8761 #define RSCAN0TMPTR71HH RSCAN0.TMPTR71.UINT8[HH]
    8762 #define RSCAN0TMDF071 RSCAN0.TMDF071.UINT32
    8763 #define RSCAN0TMDF071L RSCAN0.TMDF071.UINT16[L]
    8764 #define RSCAN0TMDF071LL RSCAN0.TMDF071.UINT8[LL]
    8765 #define RSCAN0TMDF071LH RSCAN0.TMDF071.UINT8[LH]
    8766 #define RSCAN0TMDF071H RSCAN0.TMDF071.UINT16[H]
    8767 #define RSCAN0TMDF071HL RSCAN0.TMDF071.UINT8[HL]
    8768 #define RSCAN0TMDF071HH RSCAN0.TMDF071.UINT8[HH]
    8769 #define RSCAN0TMDF171 RSCAN0.TMDF171.UINT32
    8770 #define RSCAN0TMDF171L RSCAN0.TMDF171.UINT16[L]
    8771 #define RSCAN0TMDF171LL RSCAN0.TMDF171.UINT8[LL]
    8772 #define RSCAN0TMDF171LH RSCAN0.TMDF171.UINT8[LH]
    8773 #define RSCAN0TMDF171H RSCAN0.TMDF171.UINT16[H]
    8774 #define RSCAN0TMDF171HL RSCAN0.TMDF171.UINT8[HL]
    8775 #define RSCAN0TMDF171HH RSCAN0.TMDF171.UINT8[HH]
    8776 #define RSCAN0TMID72 RSCAN0.TMID72.UINT32
    8777 #define RSCAN0TMID72L RSCAN0.TMID72.UINT16[L]
    8778 #define RSCAN0TMID72LL RSCAN0.TMID72.UINT8[LL]
    8779 #define RSCAN0TMID72LH RSCAN0.TMID72.UINT8[LH]
    8780 #define RSCAN0TMID72H RSCAN0.TMID72.UINT16[H]
    8781 #define RSCAN0TMID72HL RSCAN0.TMID72.UINT8[HL]
    8782 #define RSCAN0TMID72HH RSCAN0.TMID72.UINT8[HH]
    8783 #define RSCAN0TMPTR72 RSCAN0.TMPTR72.UINT32
    8784 #define RSCAN0TMPTR72L RSCAN0.TMPTR72.UINT16[L]
    8785 #define RSCAN0TMPTR72LL RSCAN0.TMPTR72.UINT8[LL]
    8786 #define RSCAN0TMPTR72LH RSCAN0.TMPTR72.UINT8[LH]
    8787 #define RSCAN0TMPTR72H RSCAN0.TMPTR72.UINT16[H]
    8788 #define RSCAN0TMPTR72HL RSCAN0.TMPTR72.UINT8[HL]
    8789 #define RSCAN0TMPTR72HH RSCAN0.TMPTR72.UINT8[HH]
    8790 #define RSCAN0TMDF072 RSCAN0.TMDF072.UINT32
    8791 #define RSCAN0TMDF072L RSCAN0.TMDF072.UINT16[L]
    8792 #define RSCAN0TMDF072LL RSCAN0.TMDF072.UINT8[LL]
    8793 #define RSCAN0TMDF072LH RSCAN0.TMDF072.UINT8[LH]
    8794 #define RSCAN0TMDF072H RSCAN0.TMDF072.UINT16[H]
    8795 #define RSCAN0TMDF072HL RSCAN0.TMDF072.UINT8[HL]
    8796 #define RSCAN0TMDF072HH RSCAN0.TMDF072.UINT8[HH]
    8797 #define RSCAN0TMDF172 RSCAN0.TMDF172.UINT32
    8798 #define RSCAN0TMDF172L RSCAN0.TMDF172.UINT16[L]
    8799 #define RSCAN0TMDF172LL RSCAN0.TMDF172.UINT8[LL]
    8800 #define RSCAN0TMDF172LH RSCAN0.TMDF172.UINT8[LH]
    8801 #define RSCAN0TMDF172H RSCAN0.TMDF172.UINT16[H]
    8802 #define RSCAN0TMDF172HL RSCAN0.TMDF172.UINT8[HL]
    8803 #define RSCAN0TMDF172HH RSCAN0.TMDF172.UINT8[HH]
    8804 #define RSCAN0TMID73 RSCAN0.TMID73.UINT32
    8805 #define RSCAN0TMID73L RSCAN0.TMID73.UINT16[L]
    8806 #define RSCAN0TMID73LL RSCAN0.TMID73.UINT8[LL]
    8807 #define RSCAN0TMID73LH RSCAN0.TMID73.UINT8[LH]
    8808 #define RSCAN0TMID73H RSCAN0.TMID73.UINT16[H]
    8809 #define RSCAN0TMID73HL RSCAN0.TMID73.UINT8[HL]
    8810 #define RSCAN0TMID73HH RSCAN0.TMID73.UINT8[HH]
    8811 #define RSCAN0TMPTR73 RSCAN0.TMPTR73.UINT32
    8812 #define RSCAN0TMPTR73L RSCAN0.TMPTR73.UINT16[L]
    8813 #define RSCAN0TMPTR73LL RSCAN0.TMPTR73.UINT8[LL]
    8814 #define RSCAN0TMPTR73LH RSCAN0.TMPTR73.UINT8[LH]
    8815 #define RSCAN0TMPTR73H RSCAN0.TMPTR73.UINT16[H]
    8816 #define RSCAN0TMPTR73HL RSCAN0.TMPTR73.UINT8[HL]
    8817 #define RSCAN0TMPTR73HH RSCAN0.TMPTR73.UINT8[HH]
    8818 #define RSCAN0TMDF073 RSCAN0.TMDF073.UINT32
    8819 #define RSCAN0TMDF073L RSCAN0.TMDF073.UINT16[L]
    8820 #define RSCAN0TMDF073LL RSCAN0.TMDF073.UINT8[LL]
    8821 #define RSCAN0TMDF073LH RSCAN0.TMDF073.UINT8[LH]
    8822 #define RSCAN0TMDF073H RSCAN0.TMDF073.UINT16[H]
    8823 #define RSCAN0TMDF073HL RSCAN0.TMDF073.UINT8[HL]
    8824 #define RSCAN0TMDF073HH RSCAN0.TMDF073.UINT8[HH]
    8825 #define RSCAN0TMDF173 RSCAN0.TMDF173.UINT32
    8826 #define RSCAN0TMDF173L RSCAN0.TMDF173.UINT16[L]
    8827 #define RSCAN0TMDF173LL RSCAN0.TMDF173.UINT8[LL]
    8828 #define RSCAN0TMDF173LH RSCAN0.TMDF173.UINT8[LH]
    8829 #define RSCAN0TMDF173H RSCAN0.TMDF173.UINT16[H]
    8830 #define RSCAN0TMDF173HL RSCAN0.TMDF173.UINT8[HL]
    8831 #define RSCAN0TMDF173HH RSCAN0.TMDF173.UINT8[HH]
    8832 #define RSCAN0TMID74 RSCAN0.TMID74.UINT32
    8833 #define RSCAN0TMID74L RSCAN0.TMID74.UINT16[L]
    8834 #define RSCAN0TMID74LL RSCAN0.TMID74.UINT8[LL]
    8835 #define RSCAN0TMID74LH RSCAN0.TMID74.UINT8[LH]
    8836 #define RSCAN0TMID74H RSCAN0.TMID74.UINT16[H]
    8837 #define RSCAN0TMID74HL RSCAN0.TMID74.UINT8[HL]
    8838 #define RSCAN0TMID74HH RSCAN0.TMID74.UINT8[HH]
    8839 #define RSCAN0TMPTR74 RSCAN0.TMPTR74.UINT32
    8840 #define RSCAN0TMPTR74L RSCAN0.TMPTR74.UINT16[L]
    8841 #define RSCAN0TMPTR74LL RSCAN0.TMPTR74.UINT8[LL]
    8842 #define RSCAN0TMPTR74LH RSCAN0.TMPTR74.UINT8[LH]
    8843 #define RSCAN0TMPTR74H RSCAN0.TMPTR74.UINT16[H]
    8844 #define RSCAN0TMPTR74HL RSCAN0.TMPTR74.UINT8[HL]
    8845 #define RSCAN0TMPTR74HH RSCAN0.TMPTR74.UINT8[HH]
    8846 #define RSCAN0TMDF074 RSCAN0.TMDF074.UINT32
    8847 #define RSCAN0TMDF074L RSCAN0.TMDF074.UINT16[L]
    8848 #define RSCAN0TMDF074LL RSCAN0.TMDF074.UINT8[LL]
    8849 #define RSCAN0TMDF074LH RSCAN0.TMDF074.UINT8[LH]
    8850 #define RSCAN0TMDF074H RSCAN0.TMDF074.UINT16[H]
    8851 #define RSCAN0TMDF074HL RSCAN0.TMDF074.UINT8[HL]
    8852 #define RSCAN0TMDF074HH RSCAN0.TMDF074.UINT8[HH]
    8853 #define RSCAN0TMDF174 RSCAN0.TMDF174.UINT32
    8854 #define RSCAN0TMDF174L RSCAN0.TMDF174.UINT16[L]
    8855 #define RSCAN0TMDF174LL RSCAN0.TMDF174.UINT8[LL]
    8856 #define RSCAN0TMDF174LH RSCAN0.TMDF174.UINT8[LH]
    8857 #define RSCAN0TMDF174H RSCAN0.TMDF174.UINT16[H]
    8858 #define RSCAN0TMDF174HL RSCAN0.TMDF174.UINT8[HL]
    8859 #define RSCAN0TMDF174HH RSCAN0.TMDF174.UINT8[HH]
    8860 #define RSCAN0TMID75 RSCAN0.TMID75.UINT32
    8861 #define RSCAN0TMID75L RSCAN0.TMID75.UINT16[L]
    8862 #define RSCAN0TMID75LL RSCAN0.TMID75.UINT8[LL]
    8863 #define RSCAN0TMID75LH RSCAN0.TMID75.UINT8[LH]
    8864 #define RSCAN0TMID75H RSCAN0.TMID75.UINT16[H]
    8865 #define RSCAN0TMID75HL RSCAN0.TMID75.UINT8[HL]
    8866 #define RSCAN0TMID75HH RSCAN0.TMID75.UINT8[HH]
    8867 #define RSCAN0TMPTR75 RSCAN0.TMPTR75.UINT32
    8868 #define RSCAN0TMPTR75L RSCAN0.TMPTR75.UINT16[L]
    8869 #define RSCAN0TMPTR75LL RSCAN0.TMPTR75.UINT8[LL]
    8870 #define RSCAN0TMPTR75LH RSCAN0.TMPTR75.UINT8[LH]
    8871 #define RSCAN0TMPTR75H RSCAN0.TMPTR75.UINT16[H]
    8872 #define RSCAN0TMPTR75HL RSCAN0.TMPTR75.UINT8[HL]
    8873 #define RSCAN0TMPTR75HH RSCAN0.TMPTR75.UINT8[HH]
    8874 #define RSCAN0TMDF075 RSCAN0.TMDF075.UINT32
    8875 #define RSCAN0TMDF075L RSCAN0.TMDF075.UINT16[L]
    8876 #define RSCAN0TMDF075LL RSCAN0.TMDF075.UINT8[LL]
    8877 #define RSCAN0TMDF075LH RSCAN0.TMDF075.UINT8[LH]
    8878 #define RSCAN0TMDF075H RSCAN0.TMDF075.UINT16[H]
    8879 #define RSCAN0TMDF075HL RSCAN0.TMDF075.UINT8[HL]
    8880 #define RSCAN0TMDF075HH RSCAN0.TMDF075.UINT8[HH]
    8881 #define RSCAN0TMDF175 RSCAN0.TMDF175.UINT32
    8882 #define RSCAN0TMDF175L RSCAN0.TMDF175.UINT16[L]
    8883 #define RSCAN0TMDF175LL RSCAN0.TMDF175.UINT8[LL]
    8884 #define RSCAN0TMDF175LH RSCAN0.TMDF175.UINT8[LH]
    8885 #define RSCAN0TMDF175H RSCAN0.TMDF175.UINT16[H]
    8886 #define RSCAN0TMDF175HL RSCAN0.TMDF175.UINT8[HL]
    8887 #define RSCAN0TMDF175HH RSCAN0.TMDF175.UINT8[HH]
    8888 #define RSCAN0TMID76 RSCAN0.TMID76.UINT32
    8889 #define RSCAN0TMID76L RSCAN0.TMID76.UINT16[L]
    8890 #define RSCAN0TMID76LL RSCAN0.TMID76.UINT8[LL]
    8891 #define RSCAN0TMID76LH RSCAN0.TMID76.UINT8[LH]
    8892 #define RSCAN0TMID76H RSCAN0.TMID76.UINT16[H]
    8893 #define RSCAN0TMID76HL RSCAN0.TMID76.UINT8[HL]
    8894 #define RSCAN0TMID76HH RSCAN0.TMID76.UINT8[HH]
    8895 #define RSCAN0TMPTR76 RSCAN0.TMPTR76.UINT32
    8896 #define RSCAN0TMPTR76L RSCAN0.TMPTR76.UINT16[L]
    8897 #define RSCAN0TMPTR76LL RSCAN0.TMPTR76.UINT8[LL]
    8898 #define RSCAN0TMPTR76LH RSCAN0.TMPTR76.UINT8[LH]
    8899 #define RSCAN0TMPTR76H RSCAN0.TMPTR76.UINT16[H]
    8900 #define RSCAN0TMPTR76HL RSCAN0.TMPTR76.UINT8[HL]
    8901 #define RSCAN0TMPTR76HH RSCAN0.TMPTR76.UINT8[HH]
    8902 #define RSCAN0TMDF076 RSCAN0.TMDF076.UINT32
    8903 #define RSCAN0TMDF076L RSCAN0.TMDF076.UINT16[L]
    8904 #define RSCAN0TMDF076LL RSCAN0.TMDF076.UINT8[LL]
    8905 #define RSCAN0TMDF076LH RSCAN0.TMDF076.UINT8[LH]
    8906 #define RSCAN0TMDF076H RSCAN0.TMDF076.UINT16[H]
    8907 #define RSCAN0TMDF076HL RSCAN0.TMDF076.UINT8[HL]
    8908 #define RSCAN0TMDF076HH RSCAN0.TMDF076.UINT8[HH]
    8909 #define RSCAN0TMDF176 RSCAN0.TMDF176.UINT32
    8910 #define RSCAN0TMDF176L RSCAN0.TMDF176.UINT16[L]
    8911 #define RSCAN0TMDF176LL RSCAN0.TMDF176.UINT8[LL]
    8912 #define RSCAN0TMDF176LH RSCAN0.TMDF176.UINT8[LH]
    8913 #define RSCAN0TMDF176H RSCAN0.TMDF176.UINT16[H]
    8914 #define RSCAN0TMDF176HL RSCAN0.TMDF176.UINT8[HL]
    8915 #define RSCAN0TMDF176HH RSCAN0.TMDF176.UINT8[HH]
    8916 #define RSCAN0TMID77 RSCAN0.TMID77.UINT32
    8917 #define RSCAN0TMID77L RSCAN0.TMID77.UINT16[L]
    8918 #define RSCAN0TMID77LL RSCAN0.TMID77.UINT8[LL]
    8919 #define RSCAN0TMID77LH RSCAN0.TMID77.UINT8[LH]
    8920 #define RSCAN0TMID77H RSCAN0.TMID77.UINT16[H]
    8921 #define RSCAN0TMID77HL RSCAN0.TMID77.UINT8[HL]
    8922 #define RSCAN0TMID77HH RSCAN0.TMID77.UINT8[HH]
    8923 #define RSCAN0TMPTR77 RSCAN0.TMPTR77.UINT32
    8924 #define RSCAN0TMPTR77L RSCAN0.TMPTR77.UINT16[L]
    8925 #define RSCAN0TMPTR77LL RSCAN0.TMPTR77.UINT8[LL]
    8926 #define RSCAN0TMPTR77LH RSCAN0.TMPTR77.UINT8[LH]
    8927 #define RSCAN0TMPTR77H RSCAN0.TMPTR77.UINT16[H]
    8928 #define RSCAN0TMPTR77HL RSCAN0.TMPTR77.UINT8[HL]
    8929 #define RSCAN0TMPTR77HH RSCAN0.TMPTR77.UINT8[HH]
    8930 #define RSCAN0TMDF077 RSCAN0.TMDF077.UINT32
    8931 #define RSCAN0TMDF077L RSCAN0.TMDF077.UINT16[L]
    8932 #define RSCAN0TMDF077LL RSCAN0.TMDF077.UINT8[LL]
    8933 #define RSCAN0TMDF077LH RSCAN0.TMDF077.UINT8[LH]
    8934 #define RSCAN0TMDF077H RSCAN0.TMDF077.UINT16[H]
    8935 #define RSCAN0TMDF077HL RSCAN0.TMDF077.UINT8[HL]
    8936 #define RSCAN0TMDF077HH RSCAN0.TMDF077.UINT8[HH]
    8937 #define RSCAN0TMDF177 RSCAN0.TMDF177.UINT32
    8938 #define RSCAN0TMDF177L RSCAN0.TMDF177.UINT16[L]
    8939 #define RSCAN0TMDF177LL RSCAN0.TMDF177.UINT8[LL]
    8940 #define RSCAN0TMDF177LH RSCAN0.TMDF177.UINT8[LH]
    8941 #define RSCAN0TMDF177H RSCAN0.TMDF177.UINT16[H]
    8942 #define RSCAN0TMDF177HL RSCAN0.TMDF177.UINT8[HL]
    8943 #define RSCAN0TMDF177HH RSCAN0.TMDF177.UINT8[HH]
    8944 #define RSCAN0TMID78 RSCAN0.TMID78.UINT32
    8945 #define RSCAN0TMID78L RSCAN0.TMID78.UINT16[L]
    8946 #define RSCAN0TMID78LL RSCAN0.TMID78.UINT8[LL]
    8947 #define RSCAN0TMID78LH RSCAN0.TMID78.UINT8[LH]
    8948 #define RSCAN0TMID78H RSCAN0.TMID78.UINT16[H]
    8949 #define RSCAN0TMID78HL RSCAN0.TMID78.UINT8[HL]
    8950 #define RSCAN0TMID78HH RSCAN0.TMID78.UINT8[HH]
    8951 #define RSCAN0TMPTR78 RSCAN0.TMPTR78.UINT32
    8952 #define RSCAN0TMPTR78L RSCAN0.TMPTR78.UINT16[L]
    8953 #define RSCAN0TMPTR78LL RSCAN0.TMPTR78.UINT8[LL]
    8954 #define RSCAN0TMPTR78LH RSCAN0.TMPTR78.UINT8[LH]
    8955 #define RSCAN0TMPTR78H RSCAN0.TMPTR78.UINT16[H]
    8956 #define RSCAN0TMPTR78HL RSCAN0.TMPTR78.UINT8[HL]
    8957 #define RSCAN0TMPTR78HH RSCAN0.TMPTR78.UINT8[HH]
    8958 #define RSCAN0TMDF078 RSCAN0.TMDF078.UINT32
    8959 #define RSCAN0TMDF078L RSCAN0.TMDF078.UINT16[L]
    8960 #define RSCAN0TMDF078LL RSCAN0.TMDF078.UINT8[LL]
    8961 #define RSCAN0TMDF078LH RSCAN0.TMDF078.UINT8[LH]
    8962 #define RSCAN0TMDF078H RSCAN0.TMDF078.UINT16[H]
    8963 #define RSCAN0TMDF078HL RSCAN0.TMDF078.UINT8[HL]
    8964 #define RSCAN0TMDF078HH RSCAN0.TMDF078.UINT8[HH]
    8965 #define RSCAN0TMDF178 RSCAN0.TMDF178.UINT32
    8966 #define RSCAN0TMDF178L RSCAN0.TMDF178.UINT16[L]
    8967 #define RSCAN0TMDF178LL RSCAN0.TMDF178.UINT8[LL]
    8968 #define RSCAN0TMDF178LH RSCAN0.TMDF178.UINT8[LH]
    8969 #define RSCAN0TMDF178H RSCAN0.TMDF178.UINT16[H]
    8970 #define RSCAN0TMDF178HL RSCAN0.TMDF178.UINT8[HL]
    8971 #define RSCAN0TMDF178HH RSCAN0.TMDF178.UINT8[HH]
    8972 #define RSCAN0TMID79 RSCAN0.TMID79.UINT32
    8973 #define RSCAN0TMID79L RSCAN0.TMID79.UINT16[L]
    8974 #define RSCAN0TMID79LL RSCAN0.TMID79.UINT8[LL]
    8975 #define RSCAN0TMID79LH RSCAN0.TMID79.UINT8[LH]
    8976 #define RSCAN0TMID79H RSCAN0.TMID79.UINT16[H]
    8977 #define RSCAN0TMID79HL RSCAN0.TMID79.UINT8[HL]
    8978 #define RSCAN0TMID79HH RSCAN0.TMID79.UINT8[HH]
    8979 #define RSCAN0TMPTR79 RSCAN0.TMPTR79.UINT32
    8980 #define RSCAN0TMPTR79L RSCAN0.TMPTR79.UINT16[L]
    8981 #define RSCAN0TMPTR79LL RSCAN0.TMPTR79.UINT8[LL]
    8982 #define RSCAN0TMPTR79LH RSCAN0.TMPTR79.UINT8[LH]
    8983 #define RSCAN0TMPTR79H RSCAN0.TMPTR79.UINT16[H]
    8984 #define RSCAN0TMPTR79HL RSCAN0.TMPTR79.UINT8[HL]
    8985 #define RSCAN0TMPTR79HH RSCAN0.TMPTR79.UINT8[HH]
    8986 #define RSCAN0TMDF079 RSCAN0.TMDF079.UINT32
    8987 #define RSCAN0TMDF079L RSCAN0.TMDF079.UINT16[L]
    8988 #define RSCAN0TMDF079LL RSCAN0.TMDF079.UINT8[LL]
    8989 #define RSCAN0TMDF079LH RSCAN0.TMDF079.UINT8[LH]
    8990 #define RSCAN0TMDF079H RSCAN0.TMDF079.UINT16[H]
    8991 #define RSCAN0TMDF079HL RSCAN0.TMDF079.UINT8[HL]
    8992 #define RSCAN0TMDF079HH RSCAN0.TMDF079.UINT8[HH]
    8993 #define RSCAN0TMDF179 RSCAN0.TMDF179.UINT32
    8994 #define RSCAN0TMDF179L RSCAN0.TMDF179.UINT16[L]
    8995 #define RSCAN0TMDF179LL RSCAN0.TMDF179.UINT8[LL]
    8996 #define RSCAN0TMDF179LH RSCAN0.TMDF179.UINT8[LH]
    8997 #define RSCAN0TMDF179H RSCAN0.TMDF179.UINT16[H]
    8998 #define RSCAN0TMDF179HL RSCAN0.TMDF179.UINT8[HL]
    8999 #define RSCAN0TMDF179HH RSCAN0.TMDF179.UINT8[HH]
    9000 #define RSCAN0THLACC0 RSCAN0.THLACC0.UINT32
    9001 #define RSCAN0THLACC0L RSCAN0.THLACC0.UINT16[L]
    9002 #define RSCAN0THLACC0LL RSCAN0.THLACC0.UINT8[LL]
    9003 #define RSCAN0THLACC0LH RSCAN0.THLACC0.UINT8[LH]
    9004 #define RSCAN0THLACC0H RSCAN0.THLACC0.UINT16[H]
    9005 #define RSCAN0THLACC0HL RSCAN0.THLACC0.UINT8[HL]
    9006 #define RSCAN0THLACC0HH RSCAN0.THLACC0.UINT8[HH]
    9007 #define RSCAN0THLACC1 RSCAN0.THLACC1.UINT32
    9008 #define RSCAN0THLACC1L RSCAN0.THLACC1.UINT16[L]
    9009 #define RSCAN0THLACC1LL RSCAN0.THLACC1.UINT8[LL]
    9010 #define RSCAN0THLACC1LH RSCAN0.THLACC1.UINT8[LH]
    9011 #define RSCAN0THLACC1H RSCAN0.THLACC1.UINT16[H]
    9012 #define RSCAN0THLACC1HL RSCAN0.THLACC1.UINT8[HL]
    9013 #define RSCAN0THLACC1HH RSCAN0.THLACC1.UINT8[HH]
    9014 #define RSCAN0THLACC2 RSCAN0.THLACC2.UINT32
    9015 #define RSCAN0THLACC2L RSCAN0.THLACC2.UINT16[L]
    9016 #define RSCAN0THLACC2LL RSCAN0.THLACC2.UINT8[LL]
    9017 #define RSCAN0THLACC2LH RSCAN0.THLACC2.UINT8[LH]
    9018 #define RSCAN0THLACC2H RSCAN0.THLACC2.UINT16[H]
    9019 #define RSCAN0THLACC2HL RSCAN0.THLACC2.UINT8[HL]
    9020 #define RSCAN0THLACC2HH RSCAN0.THLACC2.UINT8[HH]
    9021 #define RSCAN0THLACC3 RSCAN0.THLACC3.UINT32
    9022 #define RSCAN0THLACC3L RSCAN0.THLACC3.UINT16[L]
    9023 #define RSCAN0THLACC3LL RSCAN0.THLACC3.UINT8[LL]
    9024 #define RSCAN0THLACC3LH RSCAN0.THLACC3.UINT8[LH]
    9025 #define RSCAN0THLACC3H RSCAN0.THLACC3.UINT16[H]
    9026 #define RSCAN0THLACC3HL RSCAN0.THLACC3.UINT8[HL]
    9027 #define RSCAN0THLACC3HH RSCAN0.THLACC3.UINT8[HH]
    9028 #define RSCAN0THLACC4 RSCAN0.THLACC4.UINT32
    9029 #define RSCAN0THLACC4L RSCAN0.THLACC4.UINT16[L]
    9030 #define RSCAN0THLACC4LL RSCAN0.THLACC4.UINT8[LL]
    9031 #define RSCAN0THLACC4LH RSCAN0.THLACC4.UINT8[LH]
    9032 #define RSCAN0THLACC4H RSCAN0.THLACC4.UINT16[H]
    9033 #define RSCAN0THLACC4HL RSCAN0.THLACC4.UINT8[HL]
    9034 #define RSCAN0THLACC4HH RSCAN0.THLACC4.UINT8[HH]
     318/* End of channel array defines of RSCAN0 */
     319
     320
     321#define RSCAN0C0CFG (RSCAN0.C0CFG.UINT32)
     322#define RSCAN0C0CFGL (RSCAN0.C0CFG.UINT16[R_IO_L])
     323#define RSCAN0C0CFGLL (RSCAN0.C0CFG.UINT8[R_IO_LL])
     324#define RSCAN0C0CFGLH (RSCAN0.C0CFG.UINT8[R_IO_LH])
     325#define RSCAN0C0CFGH (RSCAN0.C0CFG.UINT16[R_IO_H])
     326#define RSCAN0C0CFGHL (RSCAN0.C0CFG.UINT8[R_IO_HL])
     327#define RSCAN0C0CFGHH (RSCAN0.C0CFG.UINT8[R_IO_HH])
     328#define RSCAN0C0CTR (RSCAN0.C0CTR.UINT32)
     329#define RSCAN0C0CTRL (RSCAN0.C0CTR.UINT16[R_IO_L])
     330#define RSCAN0C0CTRLL (RSCAN0.C0CTR.UINT8[R_IO_LL])
     331#define RSCAN0C0CTRLH (RSCAN0.C0CTR.UINT8[R_IO_LH])
     332#define RSCAN0C0CTRH (RSCAN0.C0CTR.UINT16[R_IO_H])
     333#define RSCAN0C0CTRHL (RSCAN0.C0CTR.UINT8[R_IO_HL])
     334#define RSCAN0C0CTRHH (RSCAN0.C0CTR.UINT8[R_IO_HH])
     335#define RSCAN0C0STS (RSCAN0.C0STS.UINT32)
     336#define RSCAN0C0STSL (RSCAN0.C0STS.UINT16[R_IO_L])
     337#define RSCAN0C0STSLL (RSCAN0.C0STS.UINT8[R_IO_LL])
     338#define RSCAN0C0STSLH (RSCAN0.C0STS.UINT8[R_IO_LH])
     339#define RSCAN0C0STSH (RSCAN0.C0STS.UINT16[R_IO_H])
     340#define RSCAN0C0STSHL (RSCAN0.C0STS.UINT8[R_IO_HL])
     341#define RSCAN0C0STSHH (RSCAN0.C0STS.UINT8[R_IO_HH])
     342#define RSCAN0C0ERFL (RSCAN0.C0ERFL.UINT32)
     343#define RSCAN0C0ERFLL (RSCAN0.C0ERFL.UINT16[R_IO_L])
     344#define RSCAN0C0ERFLLL (RSCAN0.C0ERFL.UINT8[R_IO_LL])
     345#define RSCAN0C0ERFLLH (RSCAN0.C0ERFL.UINT8[R_IO_LH])
     346#define RSCAN0C0ERFLH (RSCAN0.C0ERFL.UINT16[R_IO_H])
     347#define RSCAN0C0ERFLHL (RSCAN0.C0ERFL.UINT8[R_IO_HL])
     348#define RSCAN0C0ERFLHH (RSCAN0.C0ERFL.UINT8[R_IO_HH])
     349#define RSCAN0C1CFG (RSCAN0.C1CFG.UINT32)
     350#define RSCAN0C1CFGL (RSCAN0.C1CFG.UINT16[R_IO_L])
     351#define RSCAN0C1CFGLL (RSCAN0.C1CFG.UINT8[R_IO_LL])
     352#define RSCAN0C1CFGLH (RSCAN0.C1CFG.UINT8[R_IO_LH])
     353#define RSCAN0C1CFGH (RSCAN0.C1CFG.UINT16[R_IO_H])
     354#define RSCAN0C1CFGHL (RSCAN0.C1CFG.UINT8[R_IO_HL])
     355#define RSCAN0C1CFGHH (RSCAN0.C1CFG.UINT8[R_IO_HH])
     356#define RSCAN0C1CTR (RSCAN0.C1CTR.UINT32)
     357#define RSCAN0C1CTRL (RSCAN0.C1CTR.UINT16[R_IO_L])
     358#define RSCAN0C1CTRLL (RSCAN0.C1CTR.UINT8[R_IO_LL])
     359#define RSCAN0C1CTRLH (RSCAN0.C1CTR.UINT8[R_IO_LH])
     360#define RSCAN0C1CTRH (RSCAN0.C1CTR.UINT16[R_IO_H])
     361#define RSCAN0C1CTRHL (RSCAN0.C1CTR.UINT8[R_IO_HL])
     362#define RSCAN0C1CTRHH (RSCAN0.C1CTR.UINT8[R_IO_HH])
     363#define RSCAN0C1STS (RSCAN0.C1STS.UINT32)
     364#define RSCAN0C1STSL (RSCAN0.C1STS.UINT16[R_IO_L])
     365#define RSCAN0C1STSLL (RSCAN0.C1STS.UINT8[R_IO_LL])
     366#define RSCAN0C1STSLH (RSCAN0.C1STS.UINT8[R_IO_LH])
     367#define RSCAN0C1STSH (RSCAN0.C1STS.UINT16[R_IO_H])
     368#define RSCAN0C1STSHL (RSCAN0.C1STS.UINT8[R_IO_HL])
     369#define RSCAN0C1STSHH (RSCAN0.C1STS.UINT8[R_IO_HH])
     370#define RSCAN0C1ERFL (RSCAN0.C1ERFL.UINT32)
     371#define RSCAN0C1ERFLL (RSCAN0.C1ERFL.UINT16[R_IO_L])
     372#define RSCAN0C1ERFLLL (RSCAN0.C1ERFL.UINT8[R_IO_LL])
     373#define RSCAN0C1ERFLLH (RSCAN0.C1ERFL.UINT8[R_IO_LH])
     374#define RSCAN0C1ERFLH (RSCAN0.C1ERFL.UINT16[R_IO_H])
     375#define RSCAN0C1ERFLHL (RSCAN0.C1ERFL.UINT8[R_IO_HL])
     376#define RSCAN0C1ERFLHH (RSCAN0.C1ERFL.UINT8[R_IO_HH])
     377#define RSCAN0C2CFG (RSCAN0.C2CFG.UINT32)
     378#define RSCAN0C2CFGL (RSCAN0.C2CFG.UINT16[R_IO_L])
     379#define RSCAN0C2CFGLL (RSCAN0.C2CFG.UINT8[R_IO_LL])
     380#define RSCAN0C2CFGLH (RSCAN0.C2CFG.UINT8[R_IO_LH])
     381#define RSCAN0C2CFGH (RSCAN0.C2CFG.UINT16[R_IO_H])
     382#define RSCAN0C2CFGHL (RSCAN0.C2CFG.UINT8[R_IO_HL])
     383#define RSCAN0C2CFGHH (RSCAN0.C2CFG.UINT8[R_IO_HH])
     384#define RSCAN0C2CTR (RSCAN0.C2CTR.UINT32)
     385#define RSCAN0C2CTRL (RSCAN0.C2CTR.UINT16[R_IO_L])
     386#define RSCAN0C2CTRLL (RSCAN0.C2CTR.UINT8[R_IO_LL])
     387#define RSCAN0C2CTRLH (RSCAN0.C2CTR.UINT8[R_IO_LH])
     388#define RSCAN0C2CTRH (RSCAN0.C2CTR.UINT16[R_IO_H])
     389#define RSCAN0C2CTRHL (RSCAN0.C2CTR.UINT8[R_IO_HL])
     390#define RSCAN0C2CTRHH (RSCAN0.C2CTR.UINT8[R_IO_HH])
     391#define RSCAN0C2STS (RSCAN0.C2STS.UINT32)
     392#define RSCAN0C2STSL (RSCAN0.C2STS.UINT16[R_IO_L])
     393#define RSCAN0C2STSLL (RSCAN0.C2STS.UINT8[R_IO_LL])
     394#define RSCAN0C2STSLH (RSCAN0.C2STS.UINT8[R_IO_LH])
     395#define RSCAN0C2STSH (RSCAN0.C2STS.UINT16[R_IO_H])
     396#define RSCAN0C2STSHL (RSCAN0.C2STS.UINT8[R_IO_HL])
     397#define RSCAN0C2STSHH (RSCAN0.C2STS.UINT8[R_IO_HH])
     398#define RSCAN0C2ERFL (RSCAN0.C2ERFL.UINT32)
     399#define RSCAN0C2ERFLL (RSCAN0.C2ERFL.UINT16[R_IO_L])
     400#define RSCAN0C2ERFLLL (RSCAN0.C2ERFL.UINT8[R_IO_LL])
     401#define RSCAN0C2ERFLLH (RSCAN0.C2ERFL.UINT8[R_IO_LH])
     402#define RSCAN0C2ERFLH (RSCAN0.C2ERFL.UINT16[R_IO_H])
     403#define RSCAN0C2ERFLHL (RSCAN0.C2ERFL.UINT8[R_IO_HL])
     404#define RSCAN0C2ERFLHH (RSCAN0.C2ERFL.UINT8[R_IO_HH])
     405#define RSCAN0C3CFG (RSCAN0.C3CFG.UINT32)
     406#define RSCAN0C3CFGL (RSCAN0.C3CFG.UINT16[R_IO_L])
     407#define RSCAN0C3CFGLL (RSCAN0.C3CFG.UINT8[R_IO_LL])
     408#define RSCAN0C3CFGLH (RSCAN0.C3CFG.UINT8[R_IO_LH])
     409#define RSCAN0C3CFGH (RSCAN0.C3CFG.UINT16[R_IO_H])
     410#define RSCAN0C3CFGHL (RSCAN0.C3CFG.UINT8[R_IO_HL])
     411#define RSCAN0C3CFGHH (RSCAN0.C3CFG.UINT8[R_IO_HH])
     412#define RSCAN0C3CTR (RSCAN0.C3CTR.UINT32)
     413#define RSCAN0C3CTRL (RSCAN0.C3CTR.UINT16[R_IO_L])
     414#define RSCAN0C3CTRLL (RSCAN0.C3CTR.UINT8[R_IO_LL])
     415#define RSCAN0C3CTRLH (RSCAN0.C3CTR.UINT8[R_IO_LH])
     416#define RSCAN0C3CTRH (RSCAN0.C3CTR.UINT16[R_IO_H])
     417#define RSCAN0C3CTRHL (RSCAN0.C3CTR.UINT8[R_IO_HL])
     418#define RSCAN0C3CTRHH (RSCAN0.C3CTR.UINT8[R_IO_HH])
     419#define RSCAN0C3STS (RSCAN0.C3STS.UINT32)
     420#define RSCAN0C3STSL (RSCAN0.C3STS.UINT16[R_IO_L])
     421#define RSCAN0C3STSLL (RSCAN0.C3STS.UINT8[R_IO_LL])
     422#define RSCAN0C3STSLH (RSCAN0.C3STS.UINT8[R_IO_LH])
     423#define RSCAN0C3STSH (RSCAN0.C3STS.UINT16[R_IO_H])
     424#define RSCAN0C3STSHL (RSCAN0.C3STS.UINT8[R_IO_HL])
     425#define RSCAN0C3STSHH (RSCAN0.C3STS.UINT8[R_IO_HH])
     426#define RSCAN0C3ERFL (RSCAN0.C3ERFL.UINT32)
     427#define RSCAN0C3ERFLL (RSCAN0.C3ERFL.UINT16[R_IO_L])
     428#define RSCAN0C3ERFLLL (RSCAN0.C3ERFL.UINT8[R_IO_LL])
     429#define RSCAN0C3ERFLLH (RSCAN0.C3ERFL.UINT8[R_IO_LH])
     430#define RSCAN0C3ERFLH (RSCAN0.C3ERFL.UINT16[R_IO_H])
     431#define RSCAN0C3ERFLHL (RSCAN0.C3ERFL.UINT8[R_IO_HL])
     432#define RSCAN0C3ERFLHH (RSCAN0.C3ERFL.UINT8[R_IO_HH])
     433#define RSCAN0C4CFG (RSCAN0.C4CFG.UINT32)
     434#define RSCAN0C4CFGL (RSCAN0.C4CFG.UINT16[R_IO_L])
     435#define RSCAN0C4CFGLL (RSCAN0.C4CFG.UINT8[R_IO_LL])
     436#define RSCAN0C4CFGLH (RSCAN0.C4CFG.UINT8[R_IO_LH])
     437#define RSCAN0C4CFGH (RSCAN0.C4CFG.UINT16[R_IO_H])
     438#define RSCAN0C4CFGHL (RSCAN0.C4CFG.UINT8[R_IO_HL])
     439#define RSCAN0C4CFGHH (RSCAN0.C4CFG.UINT8[R_IO_HH])
     440#define RSCAN0C4CTR (RSCAN0.C4CTR.UINT32)
     441#define RSCAN0C4CTRL (RSCAN0.C4CTR.UINT16[R_IO_L])
     442#define RSCAN0C4CTRLL (RSCAN0.C4CTR.UINT8[R_IO_LL])
     443#define RSCAN0C4CTRLH (RSCAN0.C4CTR.UINT8[R_IO_LH])
     444#define RSCAN0C4CTRH (RSCAN0.C4CTR.UINT16[R_IO_H])
     445#define RSCAN0C4CTRHL (RSCAN0.C4CTR.UINT8[R_IO_HL])
     446#define RSCAN0C4CTRHH (RSCAN0.C4CTR.UINT8[R_IO_HH])
     447#define RSCAN0C4STS (RSCAN0.C4STS.UINT32)
     448#define RSCAN0C4STSL (RSCAN0.C4STS.UINT16[R_IO_L])
     449#define RSCAN0C4STSLL (RSCAN0.C4STS.UINT8[R_IO_LL])
     450#define RSCAN0C4STSLH (RSCAN0.C4STS.UINT8[R_IO_LH])
     451#define RSCAN0C4STSH (RSCAN0.C4STS.UINT16[R_IO_H])
     452#define RSCAN0C4STSHL (RSCAN0.C4STS.UINT8[R_IO_HL])
     453#define RSCAN0C4STSHH (RSCAN0.C4STS.UINT8[R_IO_HH])
     454#define RSCAN0C4ERFL (RSCAN0.C4ERFL.UINT32)
     455#define RSCAN0C4ERFLL (RSCAN0.C4ERFL.UINT16[R_IO_L])
     456#define RSCAN0C4ERFLLL (RSCAN0.C4ERFL.UINT8[R_IO_LL])
     457#define RSCAN0C4ERFLLH (RSCAN0.C4ERFL.UINT8[R_IO_LH])
     458#define RSCAN0C4ERFLH (RSCAN0.C4ERFL.UINT16[R_IO_H])
     459#define RSCAN0C4ERFLHL (RSCAN0.C4ERFL.UINT8[R_IO_HL])
     460#define RSCAN0C4ERFLHH (RSCAN0.C4ERFL.UINT8[R_IO_HH])
     461#define RSCAN0GCFG (RSCAN0.GCFG.UINT32)
     462#define RSCAN0GCFGL (RSCAN0.GCFG.UINT16[R_IO_L])
     463#define RSCAN0GCFGLL (RSCAN0.GCFG.UINT8[R_IO_LL])
     464#define RSCAN0GCFGLH (RSCAN0.GCFG.UINT8[R_IO_LH])
     465#define RSCAN0GCFGH (RSCAN0.GCFG.UINT16[R_IO_H])
     466#define RSCAN0GCFGHL (RSCAN0.GCFG.UINT8[R_IO_HL])
     467#define RSCAN0GCFGHH (RSCAN0.GCFG.UINT8[R_IO_HH])
     468#define RSCAN0GCTR (RSCAN0.GCTR.UINT32)
     469#define RSCAN0GCTRL (RSCAN0.GCTR.UINT16[R_IO_L])
     470#define RSCAN0GCTRLL (RSCAN0.GCTR.UINT8[R_IO_LL])
     471#define RSCAN0GCTRLH (RSCAN0.GCTR.UINT8[R_IO_LH])
     472#define RSCAN0GCTRH (RSCAN0.GCTR.UINT16[R_IO_H])
     473#define RSCAN0GCTRHL (RSCAN0.GCTR.UINT8[R_IO_HL])
     474#define RSCAN0GCTRHH (RSCAN0.GCTR.UINT8[R_IO_HH])
     475#define RSCAN0GSTS (RSCAN0.GSTS.UINT32)
     476#define RSCAN0GSTSL (RSCAN0.GSTS.UINT16[R_IO_L])
     477#define RSCAN0GSTSLL (RSCAN0.GSTS.UINT8[R_IO_LL])
     478#define RSCAN0GSTSLH (RSCAN0.GSTS.UINT8[R_IO_LH])
     479#define RSCAN0GSTSH (RSCAN0.GSTS.UINT16[R_IO_H])
     480#define RSCAN0GSTSHL (RSCAN0.GSTS.UINT8[R_IO_HL])
     481#define RSCAN0GSTSHH (RSCAN0.GSTS.UINT8[R_IO_HH])
     482#define RSCAN0GERFL (RSCAN0.GERFL.UINT32)
     483#define RSCAN0GERFLL (RSCAN0.GERFL.UINT16[R_IO_L])
     484#define RSCAN0GERFLLL (RSCAN0.GERFL.UINT8[R_IO_LL])
     485#define RSCAN0GERFLLH (RSCAN0.GERFL.UINT8[R_IO_LH])
     486#define RSCAN0GERFLH (RSCAN0.GERFL.UINT16[R_IO_H])
     487#define RSCAN0GERFLHL (RSCAN0.GERFL.UINT8[R_IO_HL])
     488#define RSCAN0GERFLHH (RSCAN0.GERFL.UINT8[R_IO_HH])
     489#define RSCAN0GTSC (RSCAN0.GTSC.UINT32)
     490#define RSCAN0GTSCL (RSCAN0.GTSC.UINT16[R_IO_L])
     491#define RSCAN0GTSCH (RSCAN0.GTSC.UINT16[R_IO_H])
     492#define RSCAN0GAFLECTR (RSCAN0.GAFLECTR.UINT32)
     493#define RSCAN0GAFLECTRL (RSCAN0.GAFLECTR.UINT16[R_IO_L])
     494#define RSCAN0GAFLECTRLL (RSCAN0.GAFLECTR.UINT8[R_IO_LL])
     495#define RSCAN0GAFLECTRLH (RSCAN0.GAFLECTR.UINT8[R_IO_LH])
     496#define RSCAN0GAFLECTRH (RSCAN0.GAFLECTR.UINT16[R_IO_H])
     497#define RSCAN0GAFLECTRHL (RSCAN0.GAFLECTR.UINT8[R_IO_HL])
     498#define RSCAN0GAFLECTRHH (RSCAN0.GAFLECTR.UINT8[R_IO_HH])
     499#define RSCAN0GAFLCFG0 (RSCAN0.GAFLCFG0.UINT32)
     500#define RSCAN0GAFLCFG0L (RSCAN0.GAFLCFG0.UINT16[R_IO_L])
     501#define RSCAN0GAFLCFG0LL (RSCAN0.GAFLCFG0.UINT8[R_IO_LL])
     502#define RSCAN0GAFLCFG0LH (RSCAN0.GAFLCFG0.UINT8[R_IO_LH])
     503#define RSCAN0GAFLCFG0H (RSCAN0.GAFLCFG0.UINT16[R_IO_H])
     504#define RSCAN0GAFLCFG0HL (RSCAN0.GAFLCFG0.UINT8[R_IO_HL])
     505#define RSCAN0GAFLCFG0HH (RSCAN0.GAFLCFG0.UINT8[R_IO_HH])
     506#define RSCAN0GAFLCFG1 (RSCAN0.GAFLCFG1.UINT32)
     507#define RSCAN0GAFLCFG1L (RSCAN0.GAFLCFG1.UINT16[R_IO_L])
     508#define RSCAN0GAFLCFG1LL (RSCAN0.GAFLCFG1.UINT8[R_IO_LL])
     509#define RSCAN0GAFLCFG1LH (RSCAN0.GAFLCFG1.UINT8[R_IO_LH])
     510#define RSCAN0GAFLCFG1H (RSCAN0.GAFLCFG1.UINT16[R_IO_H])
     511#define RSCAN0GAFLCFG1HL (RSCAN0.GAFLCFG1.UINT8[R_IO_HL])
     512#define RSCAN0GAFLCFG1HH (RSCAN0.GAFLCFG1.UINT8[R_IO_HH])
     513#define RSCAN0RMNB (RSCAN0.RMNB.UINT32)
     514#define RSCAN0RMNBL (RSCAN0.RMNB.UINT16[R_IO_L])
     515#define RSCAN0RMNBLL (RSCAN0.RMNB.UINT8[R_IO_LL])
     516#define RSCAN0RMNBLH (RSCAN0.RMNB.UINT8[R_IO_LH])
     517#define RSCAN0RMNBH (RSCAN0.RMNB.UINT16[R_IO_H])
     518#define RSCAN0RMNBHL (RSCAN0.RMNB.UINT8[R_IO_HL])
     519#define RSCAN0RMNBHH (RSCAN0.RMNB.UINT8[R_IO_HH])
     520#define RSCAN0RMND0 (RSCAN0.RMND0.UINT32)
     521#define RSCAN0RMND0L (RSCAN0.RMND0.UINT16[R_IO_L])
     522#define RSCAN0RMND0LL (RSCAN0.RMND0.UINT8[R_IO_LL])
     523#define RSCAN0RMND0LH (RSCAN0.RMND0.UINT8[R_IO_LH])
     524#define RSCAN0RMND0H (RSCAN0.RMND0.UINT16[R_IO_H])
     525#define RSCAN0RMND0HL (RSCAN0.RMND0.UINT8[R_IO_HL])
     526#define RSCAN0RMND0HH (RSCAN0.RMND0.UINT8[R_IO_HH])
     527#define RSCAN0RMND1 (RSCAN0.RMND1.UINT32)
     528#define RSCAN0RMND1L (RSCAN0.RMND1.UINT16[R_IO_L])
     529#define RSCAN0RMND1LL (RSCAN0.RMND1.UINT8[R_IO_LL])
     530#define RSCAN0RMND1LH (RSCAN0.RMND1.UINT8[R_IO_LH])
     531#define RSCAN0RMND1H (RSCAN0.RMND1.UINT16[R_IO_H])
     532#define RSCAN0RMND1HL (RSCAN0.RMND1.UINT8[R_IO_HL])
     533#define RSCAN0RMND1HH (RSCAN0.RMND1.UINT8[R_IO_HH])
     534#define RSCAN0RMND2 (RSCAN0.RMND2.UINT32)
     535#define RSCAN0RMND2L (RSCAN0.RMND2.UINT16[R_IO_L])
     536#define RSCAN0RMND2LL (RSCAN0.RMND2.UINT8[R_IO_LL])
     537#define RSCAN0RMND2LH (RSCAN0.RMND2.UINT8[R_IO_LH])
     538#define RSCAN0RMND2H (RSCAN0.RMND2.UINT16[R_IO_H])
     539#define RSCAN0RMND2HL (RSCAN0.RMND2.UINT8[R_IO_HL])
     540#define RSCAN0RMND2HH (RSCAN0.RMND2.UINT8[R_IO_HH])
     541#define RSCAN0RFCC0 (RSCAN0.RFCC0.UINT32)
     542#define RSCAN0RFCC0L (RSCAN0.RFCC0.UINT16[R_IO_L])
     543#define RSCAN0RFCC0LL (RSCAN0.RFCC0.UINT8[R_IO_LL])
     544#define RSCAN0RFCC0LH (RSCAN0.RFCC0.UINT8[R_IO_LH])
     545#define RSCAN0RFCC0H (RSCAN0.RFCC0.UINT16[R_IO_H])
     546#define RSCAN0RFCC0HL (RSCAN0.RFCC0.UINT8[R_IO_HL])
     547#define RSCAN0RFCC0HH (RSCAN0.RFCC0.UINT8[R_IO_HH])
     548#define RSCAN0RFCC1 (RSCAN0.RFCC1.UINT32)
     549#define RSCAN0RFCC1L (RSCAN0.RFCC1.UINT16[R_IO_L])
     550#define RSCAN0RFCC1LL (RSCAN0.RFCC1.UINT8[R_IO_LL])
     551#define RSCAN0RFCC1LH (RSCAN0.RFCC1.UINT8[R_IO_LH])
     552#define RSCAN0RFCC1H (RSCAN0.RFCC1.UINT16[R_IO_H])
     553#define RSCAN0RFCC1HL (RSCAN0.RFCC1.UINT8[R_IO_HL])
     554#define RSCAN0RFCC1HH (RSCAN0.RFCC1.UINT8[R_IO_HH])
     555#define RSCAN0RFCC2 (RSCAN0.RFCC2.UINT32)
     556#define RSCAN0RFCC2L (RSCAN0.RFCC2.UINT16[R_IO_L])
     557#define RSCAN0RFCC2LL (RSCAN0.RFCC2.UINT8[R_IO_LL])
     558#define RSCAN0RFCC2LH (RSCAN0.RFCC2.UINT8[R_IO_LH])
     559#define RSCAN0RFCC2H (RSCAN0.RFCC2.UINT16[R_IO_H])
     560#define RSCAN0RFCC2HL (RSCAN0.RFCC2.UINT8[R_IO_HL])
     561#define RSCAN0RFCC2HH (RSCAN0.RFCC2.UINT8[R_IO_HH])
     562#define RSCAN0RFCC3 (RSCAN0.RFCC3.UINT32)
     563#define RSCAN0RFCC3L (RSCAN0.RFCC3.UINT16[R_IO_L])
     564#define RSCAN0RFCC3LL (RSCAN0.RFCC3.UINT8[R_IO_LL])
     565#define RSCAN0RFCC3LH (RSCAN0.RFCC3.UINT8[R_IO_LH])
     566#define RSCAN0RFCC3H (RSCAN0.RFCC3.UINT16[R_IO_H])
     567#define RSCAN0RFCC3HL (RSCAN0.RFCC3.UINT8[R_IO_HL])
     568#define RSCAN0RFCC3HH (RSCAN0.RFCC3.UINT8[R_IO_HH])
     569#define RSCAN0RFCC4 (RSCAN0.RFCC4.UINT32)
     570#define RSCAN0RFCC4L (RSCAN0.RFCC4.UINT16[R_IO_L])
     571#define RSCAN0RFCC4LL (RSCAN0.RFCC4.UINT8[R_IO_LL])
     572#define RSCAN0RFCC4LH (RSCAN0.RFCC4.UINT8[R_IO_LH])
     573#define RSCAN0RFCC4H (RSCAN0.RFCC4.UINT16[R_IO_H])
     574#define RSCAN0RFCC4HL (RSCAN0.RFCC4.UINT8[R_IO_HL])
     575#define RSCAN0RFCC4HH (RSCAN0.RFCC4.UINT8[R_IO_HH])
     576#define RSCAN0RFCC5 (RSCAN0.RFCC5.UINT32)
     577#define RSCAN0RFCC5L (RSCAN0.RFCC5.UINT16[R_IO_L])
     578#define RSCAN0RFCC5LL (RSCAN0.RFCC5.UINT8[R_IO_LL])
     579#define RSCAN0RFCC5LH (RSCAN0.RFCC5.UINT8[R_IO_LH])
     580#define RSCAN0RFCC5H (RSCAN0.RFCC5.UINT16[R_IO_H])
     581#define RSCAN0RFCC5HL (RSCAN0.RFCC5.UINT8[R_IO_HL])
     582#define RSCAN0RFCC5HH (RSCAN0.RFCC5.UINT8[R_IO_HH])
     583#define RSCAN0RFCC6 (RSCAN0.RFCC6.UINT32)
     584#define RSCAN0RFCC6L (RSCAN0.RFCC6.UINT16[R_IO_L])
     585#define RSCAN0RFCC6LL (RSCAN0.RFCC6.UINT8[R_IO_LL])
     586#define RSCAN0RFCC6LH (RSCAN0.RFCC6.UINT8[R_IO_LH])
     587#define RSCAN0RFCC6H (RSCAN0.RFCC6.UINT16[R_IO_H])
     588#define RSCAN0RFCC6HL (RSCAN0.RFCC6.UINT8[R_IO_HL])
     589#define RSCAN0RFCC6HH (RSCAN0.RFCC6.UINT8[R_IO_HH])
     590#define RSCAN0RFCC7 (RSCAN0.RFCC7.UINT32)
     591#define RSCAN0RFCC7L (RSCAN0.RFCC7.UINT16[R_IO_L])
     592#define RSCAN0RFCC7LL (RSCAN0.RFCC7.UINT8[R_IO_LL])
     593#define RSCAN0RFCC7LH (RSCAN0.RFCC7.UINT8[R_IO_LH])
     594#define RSCAN0RFCC7H (RSCAN0.RFCC7.UINT16[R_IO_H])
     595#define RSCAN0RFCC7HL (RSCAN0.RFCC7.UINT8[R_IO_HL])
     596#define RSCAN0RFCC7HH (RSCAN0.RFCC7.UINT8[R_IO_HH])
     597#define RSCAN0RFSTS0 (RSCAN0.RFSTS0.UINT32)
     598#define RSCAN0RFSTS0L (RSCAN0.RFSTS0.UINT16[R_IO_L])
     599#define RSCAN0RFSTS0LL (RSCAN0.RFSTS0.UINT8[R_IO_LL])
     600#define RSCAN0RFSTS0LH (RSCAN0.RFSTS0.UINT8[R_IO_LH])
     601#define RSCAN0RFSTS0H (RSCAN0.RFSTS0.UINT16[R_IO_H])
     602#define RSCAN0RFSTS0HL (RSCAN0.RFSTS0.UINT8[R_IO_HL])
     603#define RSCAN0RFSTS0HH (RSCAN0.RFSTS0.UINT8[R_IO_HH])
     604#define RSCAN0RFSTS1 (RSCAN0.RFSTS1.UINT32)
     605#define RSCAN0RFSTS1L (RSCAN0.RFSTS1.UINT16[R_IO_L])
     606#define RSCAN0RFSTS1LL (RSCAN0.RFSTS1.UINT8[R_IO_LL])
     607#define RSCAN0RFSTS1LH (RSCAN0.RFSTS1.UINT8[R_IO_LH])
     608#define RSCAN0RFSTS1H (RSCAN0.RFSTS1.UINT16[R_IO_H])
     609#define RSCAN0RFSTS1HL (RSCAN0.RFSTS1.UINT8[R_IO_HL])
     610#define RSCAN0RFSTS1HH (RSCAN0.RFSTS1.UINT8[R_IO_HH])
     611#define RSCAN0RFSTS2 (RSCAN0.RFSTS2.UINT32)
     612#define RSCAN0RFSTS2L (RSCAN0.RFSTS2.UINT16[R_IO_L])
     613#define RSCAN0RFSTS2LL (RSCAN0.RFSTS2.UINT8[R_IO_LL])
     614#define RSCAN0RFSTS2LH (RSCAN0.RFSTS2.UINT8[R_IO_LH])
     615#define RSCAN0RFSTS2H (RSCAN0.RFSTS2.UINT16[R_IO_H])
     616#define RSCAN0RFSTS2HL (RSCAN0.RFSTS2.UINT8[R_IO_HL])
     617#define RSCAN0RFSTS2HH (RSCAN0.RFSTS2.UINT8[R_IO_HH])
     618#define RSCAN0RFSTS3 (RSCAN0.RFSTS3.UINT32)
     619#define RSCAN0RFSTS3L (RSCAN0.RFSTS3.UINT16[R_IO_L])
     620#define RSCAN0RFSTS3LL (RSCAN0.RFSTS3.UINT8[R_IO_LL])
     621#define RSCAN0RFSTS3LH (RSCAN0.RFSTS3.UINT8[R_IO_LH])
     622#define RSCAN0RFSTS3H (RSCAN0.RFSTS3.UINT16[R_IO_H])
     623#define RSCAN0RFSTS3HL (RSCAN0.RFSTS3.UINT8[R_IO_HL])
     624#define RSCAN0RFSTS3HH (RSCAN0.RFSTS3.UINT8[R_IO_HH])
     625#define RSCAN0RFSTS4 (RSCAN0.RFSTS4.UINT32)
     626#define RSCAN0RFSTS4L (RSCAN0.RFSTS4.UINT16[R_IO_L])
     627#define RSCAN0RFSTS4LL (RSCAN0.RFSTS4.UINT8[R_IO_LL])
     628#define RSCAN0RFSTS4LH (RSCAN0.RFSTS4.UINT8[R_IO_LH])
     629#define RSCAN0RFSTS4H (RSCAN0.RFSTS4.UINT16[R_IO_H])
     630#define RSCAN0RFSTS4HL (RSCAN0.RFSTS4.UINT8[R_IO_HL])
     631#define RSCAN0RFSTS4HH (RSCAN0.RFSTS4.UINT8[R_IO_HH])
     632#define RSCAN0RFSTS5 (RSCAN0.RFSTS5.UINT32)
     633#define RSCAN0RFSTS5L (RSCAN0.RFSTS5.UINT16[R_IO_L])
     634#define RSCAN0RFSTS5LL (RSCAN0.RFSTS5.UINT8[R_IO_LL])
     635#define RSCAN0RFSTS5LH (RSCAN0.RFSTS5.UINT8[R_IO_LH])
     636#define RSCAN0RFSTS5H (RSCAN0.RFSTS5.UINT16[R_IO_H])
     637#define RSCAN0RFSTS5HL (RSCAN0.RFSTS5.UINT8[R_IO_HL])
     638#define RSCAN0RFSTS5HH (RSCAN0.RFSTS5.UINT8[R_IO_HH])
     639#define RSCAN0RFSTS6 (RSCAN0.RFSTS6.UINT32)
     640#define RSCAN0RFSTS6L (RSCAN0.RFSTS6.UINT16[R_IO_L])
     641#define RSCAN0RFSTS6LL (RSCAN0.RFSTS6.UINT8[R_IO_LL])
     642#define RSCAN0RFSTS6LH (RSCAN0.RFSTS6.UINT8[R_IO_LH])
     643#define RSCAN0RFSTS6H (RSCAN0.RFSTS6.UINT16[R_IO_H])
     644#define RSCAN0RFSTS6HL (RSCAN0.RFSTS6.UINT8[R_IO_HL])
     645#define RSCAN0RFSTS6HH (RSCAN0.RFSTS6.UINT8[R_IO_HH])
     646#define RSCAN0RFSTS7 (RSCAN0.RFSTS7.UINT32)
     647#define RSCAN0RFSTS7L (RSCAN0.RFSTS7.UINT16[R_IO_L])
     648#define RSCAN0RFSTS7LL (RSCAN0.RFSTS7.UINT8[R_IO_LL])
     649#define RSCAN0RFSTS7LH (RSCAN0.RFSTS7.UINT8[R_IO_LH])
     650#define RSCAN0RFSTS7H (RSCAN0.RFSTS7.UINT16[R_IO_H])
     651#define RSCAN0RFSTS7HL (RSCAN0.RFSTS7.UINT8[R_IO_HL])
     652#define RSCAN0RFSTS7HH (RSCAN0.RFSTS7.UINT8[R_IO_HH])
     653#define RSCAN0RFPCTR0 (RSCAN0.RFPCTR0.UINT32)
     654#define RSCAN0RFPCTR0L (RSCAN0.RFPCTR0.UINT16[R_IO_L])
     655#define RSCAN0RFPCTR0LL (RSCAN0.RFPCTR0.UINT8[R_IO_LL])
     656#define RSCAN0RFPCTR0LH (RSCAN0.RFPCTR0.UINT8[R_IO_LH])
     657#define RSCAN0RFPCTR0H (RSCAN0.RFPCTR0.UINT16[R_IO_H])
     658#define RSCAN0RFPCTR0HL (RSCAN0.RFPCTR0.UINT8[R_IO_HL])
     659#define RSCAN0RFPCTR0HH (RSCAN0.RFPCTR0.UINT8[R_IO_HH])
     660#define RSCAN0RFPCTR1 (RSCAN0.RFPCTR1.UINT32)
     661#define RSCAN0RFPCTR1L (RSCAN0.RFPCTR1.UINT16[R_IO_L])
     662#define RSCAN0RFPCTR1LL (RSCAN0.RFPCTR1.UINT8[R_IO_LL])
     663#define RSCAN0RFPCTR1LH (RSCAN0.RFPCTR1.UINT8[R_IO_LH])
     664#define RSCAN0RFPCTR1H (RSCAN0.RFPCTR1.UINT16[R_IO_H])
     665#define RSCAN0RFPCTR1HL (RSCAN0.RFPCTR1.UINT8[R_IO_HL])
     666#define RSCAN0RFPCTR1HH (RSCAN0.RFPCTR1.UINT8[R_IO_HH])
     667#define RSCAN0RFPCTR2 (RSCAN0.RFPCTR2.UINT32)
     668#define RSCAN0RFPCTR2L (RSCAN0.RFPCTR2.UINT16[R_IO_L])
     669#define RSCAN0RFPCTR2LL (RSCAN0.RFPCTR2.UINT8[R_IO_LL])
     670#define RSCAN0RFPCTR2LH (RSCAN0.RFPCTR2.UINT8[R_IO_LH])
     671#define RSCAN0RFPCTR2H (RSCAN0.RFPCTR2.UINT16[R_IO_H])
     672#define RSCAN0RFPCTR2HL (RSCAN0.RFPCTR2.UINT8[R_IO_HL])
     673#define RSCAN0RFPCTR2HH (RSCAN0.RFPCTR2.UINT8[R_IO_HH])
     674#define RSCAN0RFPCTR3 (RSCAN0.RFPCTR3.UINT32)
     675#define RSCAN0RFPCTR3L (RSCAN0.RFPCTR3.UINT16[R_IO_L])
     676#define RSCAN0RFPCTR3LL (RSCAN0.RFPCTR3.UINT8[R_IO_LL])
     677#define RSCAN0RFPCTR3LH (RSCAN0.RFPCTR3.UINT8[R_IO_LH])
     678#define RSCAN0RFPCTR3H (RSCAN0.RFPCTR3.UINT16[R_IO_H])
     679#define RSCAN0RFPCTR3HL (RSCAN0.RFPCTR3.UINT8[R_IO_HL])
     680#define RSCAN0RFPCTR3HH (RSCAN0.RFPCTR3.UINT8[R_IO_HH])
     681#define RSCAN0RFPCTR4 (RSCAN0.RFPCTR4.UINT32)
     682#define RSCAN0RFPCTR4L (RSCAN0.RFPCTR4.UINT16[R_IO_L])
     683#define RSCAN0RFPCTR4LL (RSCAN0.RFPCTR4.UINT8[R_IO_LL])
     684#define RSCAN0RFPCTR4LH (RSCAN0.RFPCTR4.UINT8[R_IO_LH])
     685#define RSCAN0RFPCTR4H (RSCAN0.RFPCTR4.UINT16[R_IO_H])
     686#define RSCAN0RFPCTR4HL (RSCAN0.RFPCTR4.UINT8[R_IO_HL])
     687#define RSCAN0RFPCTR4HH (RSCAN0.RFPCTR4.UINT8[R_IO_HH])
     688#define RSCAN0RFPCTR5 (RSCAN0.RFPCTR5.UINT32)
     689#define RSCAN0RFPCTR5L (RSCAN0.RFPCTR5.UINT16[R_IO_L])
     690#define RSCAN0RFPCTR5LL (RSCAN0.RFPCTR5.UINT8[R_IO_LL])
     691#define RSCAN0RFPCTR5LH (RSCAN0.RFPCTR5.UINT8[R_IO_LH])
     692#define RSCAN0RFPCTR5H (RSCAN0.RFPCTR5.UINT16[R_IO_H])
     693#define RSCAN0RFPCTR5HL (RSCAN0.RFPCTR5.UINT8[R_IO_HL])
     694#define RSCAN0RFPCTR5HH (RSCAN0.RFPCTR5.UINT8[R_IO_HH])
     695#define RSCAN0RFPCTR6 (RSCAN0.RFPCTR6.UINT32)
     696#define RSCAN0RFPCTR6L (RSCAN0.RFPCTR6.UINT16[R_IO_L])
     697#define RSCAN0RFPCTR6LL (RSCAN0.RFPCTR6.UINT8[R_IO_LL])
     698#define RSCAN0RFPCTR6LH (RSCAN0.RFPCTR6.UINT8[R_IO_LH])
     699#define RSCAN0RFPCTR6H (RSCAN0.RFPCTR6.UINT16[R_IO_H])
     700#define RSCAN0RFPCTR6HL (RSCAN0.RFPCTR6.UINT8[R_IO_HL])
     701#define RSCAN0RFPCTR6HH (RSCAN0.RFPCTR6.UINT8[R_IO_HH])
     702#define RSCAN0RFPCTR7 (RSCAN0.RFPCTR7.UINT32)
     703#define RSCAN0RFPCTR7L (RSCAN0.RFPCTR7.UINT16[R_IO_L])
     704#define RSCAN0RFPCTR7LL (RSCAN0.RFPCTR7.UINT8[R_IO_LL])
     705#define RSCAN0RFPCTR7LH (RSCAN0.RFPCTR7.UINT8[R_IO_LH])
     706#define RSCAN0RFPCTR7H (RSCAN0.RFPCTR7.UINT16[R_IO_H])
     707#define RSCAN0RFPCTR7HL (RSCAN0.RFPCTR7.UINT8[R_IO_HL])
     708#define RSCAN0RFPCTR7HH (RSCAN0.RFPCTR7.UINT8[R_IO_HH])
     709#define RSCAN0CFCC0 (RSCAN0.CFCC0.UINT32)
     710#define RSCAN0CFCC0L (RSCAN0.CFCC0.UINT16[R_IO_L])
     711#define RSCAN0CFCC0LL (RSCAN0.CFCC0.UINT8[R_IO_LL])
     712#define RSCAN0CFCC0LH (RSCAN0.CFCC0.UINT8[R_IO_LH])
     713#define RSCAN0CFCC0H (RSCAN0.CFCC0.UINT16[R_IO_H])
     714#define RSCAN0CFCC0HL (RSCAN0.CFCC0.UINT8[R_IO_HL])
     715#define RSCAN0CFCC0HH (RSCAN0.CFCC0.UINT8[R_IO_HH])
     716#define RSCAN0CFCC1 (RSCAN0.CFCC1.UINT32)
     717#define RSCAN0CFCC1L (RSCAN0.CFCC1.UINT16[R_IO_L])
     718#define RSCAN0CFCC1LL (RSCAN0.CFCC1.UINT8[R_IO_LL])
     719#define RSCAN0CFCC1LH (RSCAN0.CFCC1.UINT8[R_IO_LH])
     720#define RSCAN0CFCC1H (RSCAN0.CFCC1.UINT16[R_IO_H])
     721#define RSCAN0CFCC1HL (RSCAN0.CFCC1.UINT8[R_IO_HL])
     722#define RSCAN0CFCC1HH (RSCAN0.CFCC1.UINT8[R_IO_HH])
     723#define RSCAN0CFCC2 (RSCAN0.CFCC2.UINT32)
     724#define RSCAN0CFCC2L (RSCAN0.CFCC2.UINT16[R_IO_L])
     725#define RSCAN0CFCC2LL (RSCAN0.CFCC2.UINT8[R_IO_LL])
     726#define RSCAN0CFCC2LH (RSCAN0.CFCC2.UINT8[R_IO_LH])
     727#define RSCAN0CFCC2H (RSCAN0.CFCC2.UINT16[R_IO_H])
     728#define RSCAN0CFCC2HL (RSCAN0.CFCC2.UINT8[R_IO_HL])
     729#define RSCAN0CFCC2HH (RSCAN0.CFCC2.UINT8[R_IO_HH])
     730#define RSCAN0CFCC3 (RSCAN0.CFCC3.UINT32)
     731#define RSCAN0CFCC3L (RSCAN0.CFCC3.UINT16[R_IO_L])
     732#define RSCAN0CFCC3LL (RSCAN0.CFCC3.UINT8[R_IO_LL])
     733#define RSCAN0CFCC3LH (RSCAN0.CFCC3.UINT8[R_IO_LH])
     734#define RSCAN0CFCC3H (RSCAN0.CFCC3.UINT16[R_IO_H])
     735#define RSCAN0CFCC3HL (RSCAN0.CFCC3.UINT8[R_IO_HL])
     736#define RSCAN0CFCC3HH (RSCAN0.CFCC3.UINT8[R_IO_HH])
     737#define RSCAN0CFCC4 (RSCAN0.CFCC4.UINT32)
     738#define RSCAN0CFCC4L (RSCAN0.CFCC4.UINT16[R_IO_L])
     739#define RSCAN0CFCC4LL (RSCAN0.CFCC4.UINT8[R_IO_LL])
     740#define RSCAN0CFCC4LH (RSCAN0.CFCC4.UINT8[R_IO_LH])
     741#define RSCAN0CFCC4H (RSCAN0.CFCC4.UINT16[R_IO_H])
     742#define RSCAN0CFCC4HL (RSCAN0.CFCC4.UINT8[R_IO_HL])
     743#define RSCAN0CFCC4HH (RSCAN0.CFCC4.UINT8[R_IO_HH])
     744#define RSCAN0CFCC5 (RSCAN0.CFCC5.UINT32)
     745#define RSCAN0CFCC5L (RSCAN0.CFCC5.UINT16[R_IO_L])
     746#define RSCAN0CFCC5LL (RSCAN0.CFCC5.UINT8[R_IO_LL])
     747#define RSCAN0CFCC5LH (RSCAN0.CFCC5.UINT8[R_IO_LH])
     748#define RSCAN0CFCC5H (RSCAN0.CFCC5.UINT16[R_IO_H])
     749#define RSCAN0CFCC5HL (RSCAN0.CFCC5.UINT8[R_IO_HL])
     750#define RSCAN0CFCC5HH (RSCAN0.CFCC5.UINT8[R_IO_HH])
     751#define RSCAN0CFCC6 (RSCAN0.CFCC6.UINT32)
     752#define RSCAN0CFCC6L (RSCAN0.CFCC6.UINT16[R_IO_L])
     753#define RSCAN0CFCC6LL (RSCAN0.CFCC6.UINT8[R_IO_LL])
     754#define RSCAN0CFCC6LH (RSCAN0.CFCC6.UINT8[R_IO_LH])
     755#define RSCAN0CFCC6H (RSCAN0.CFCC6.UINT16[R_IO_H])
     756#define RSCAN0CFCC6HL (RSCAN0.CFCC6.UINT8[R_IO_HL])
     757#define RSCAN0CFCC6HH (RSCAN0.CFCC6.UINT8[R_IO_HH])
     758#define RSCAN0CFCC7 (RSCAN0.CFCC7.UINT32)
     759#define RSCAN0CFCC7L (RSCAN0.CFCC7.UINT16[R_IO_L])
     760#define RSCAN0CFCC7LL (RSCAN0.CFCC7.UINT8[R_IO_LL])
     761#define RSCAN0CFCC7LH (RSCAN0.CFCC7.UINT8[R_IO_LH])
     762#define RSCAN0CFCC7H (RSCAN0.CFCC7.UINT16[R_IO_H])
     763#define RSCAN0CFCC7HL (RSCAN0.CFCC7.UINT8[R_IO_HL])
     764#define RSCAN0CFCC7HH (RSCAN0.CFCC7.UINT8[R_IO_HH])
     765#define RSCAN0CFCC8 (RSCAN0.CFCC8.UINT32)
     766#define RSCAN0CFCC8L (RSCAN0.CFCC8.UINT16[R_IO_L])
     767#define RSCAN0CFCC8LL (RSCAN0.CFCC8.UINT8[R_IO_LL])
     768#define RSCAN0CFCC8LH (RSCAN0.CFCC8.UINT8[R_IO_LH])
     769#define RSCAN0CFCC8H (RSCAN0.CFCC8.UINT16[R_IO_H])
     770#define RSCAN0CFCC8HL (RSCAN0.CFCC8.UINT8[R_IO_HL])
     771#define RSCAN0CFCC8HH (RSCAN0.CFCC8.UINT8[R_IO_HH])
     772#define RSCAN0CFCC9 (RSCAN0.CFCC9.UINT32)
     773#define RSCAN0CFCC9L (RSCAN0.CFCC9.UINT16[R_IO_L])
     774#define RSCAN0CFCC9LL (RSCAN0.CFCC9.UINT8[R_IO_LL])
     775#define RSCAN0CFCC9LH (RSCAN0.CFCC9.UINT8[R_IO_LH])
     776#define RSCAN0CFCC9H (RSCAN0.CFCC9.UINT16[R_IO_H])
     777#define RSCAN0CFCC9HL (RSCAN0.CFCC9.UINT8[R_IO_HL])
     778#define RSCAN0CFCC9HH (RSCAN0.CFCC9.UINT8[R_IO_HH])
     779#define RSCAN0CFCC10 (RSCAN0.CFCC10.UINT32)
     780#define RSCAN0CFCC10L (RSCAN0.CFCC10.UINT16[R_IO_L])
     781#define RSCAN0CFCC10LL (RSCAN0.CFCC10.UINT8[R_IO_LL])
     782#define RSCAN0CFCC10LH (RSCAN0.CFCC10.UINT8[R_IO_LH])
     783#define RSCAN0CFCC10H (RSCAN0.CFCC10.UINT16[R_IO_H])
     784#define RSCAN0CFCC10HL (RSCAN0.CFCC10.UINT8[R_IO_HL])
     785#define RSCAN0CFCC10HH (RSCAN0.CFCC10.UINT8[R_IO_HH])
     786#define RSCAN0CFCC11 (RSCAN0.CFCC11.UINT32)
     787#define RSCAN0CFCC11L (RSCAN0.CFCC11.UINT16[R_IO_L])
     788#define RSCAN0CFCC11LL (RSCAN0.CFCC11.UINT8[R_IO_LL])
     789#define RSCAN0CFCC11LH (RSCAN0.CFCC11.UINT8[R_IO_LH])
     790#define RSCAN0CFCC11H (RSCAN0.CFCC11.UINT16[R_IO_H])
     791#define RSCAN0CFCC11HL (RSCAN0.CFCC11.UINT8[R_IO_HL])
     792#define RSCAN0CFCC11HH (RSCAN0.CFCC11.UINT8[R_IO_HH])
     793#define RSCAN0CFCC12 (RSCAN0.CFCC12.UINT32)
     794#define RSCAN0CFCC12L (RSCAN0.CFCC12.UINT16[R_IO_L])
     795#define RSCAN0CFCC12LL (RSCAN0.CFCC12.UINT8[R_IO_LL])
     796#define RSCAN0CFCC12LH (RSCAN0.CFCC12.UINT8[R_IO_LH])
     797#define RSCAN0CFCC12H (RSCAN0.CFCC12.UINT16[R_IO_H])
     798#define RSCAN0CFCC12HL (RSCAN0.CFCC12.UINT8[R_IO_HL])
     799#define RSCAN0CFCC12HH (RSCAN0.CFCC12.UINT8[R_IO_HH])
     800#define RSCAN0CFCC13 (RSCAN0.CFCC13.UINT32)
     801#define RSCAN0CFCC13L (RSCAN0.CFCC13.UINT16[R_IO_L])
     802#define RSCAN0CFCC13LL (RSCAN0.CFCC13.UINT8[R_IO_LL])
     803#define RSCAN0CFCC13LH (RSCAN0.CFCC13.UINT8[R_IO_LH])
     804#define RSCAN0CFCC13H (RSCAN0.CFCC13.UINT16[R_IO_H])
     805#define RSCAN0CFCC13HL (RSCAN0.CFCC13.UINT8[R_IO_HL])
     806#define RSCAN0CFCC13HH (RSCAN0.CFCC13.UINT8[R_IO_HH])
     807#define RSCAN0CFCC14 (RSCAN0.CFCC14.UINT32)
     808#define RSCAN0CFCC14L (RSCAN0.CFCC14.UINT16[R_IO_L])
     809#define RSCAN0CFCC14LL (RSCAN0.CFCC14.UINT8[R_IO_LL])
     810#define RSCAN0CFCC14LH (RSCAN0.CFCC14.UINT8[R_IO_LH])
     811#define RSCAN0CFCC14H (RSCAN0.CFCC14.UINT16[R_IO_H])
     812#define RSCAN0CFCC14HL (RSCAN0.CFCC14.UINT8[R_IO_HL])
     813#define RSCAN0CFCC14HH (RSCAN0.CFCC14.UINT8[R_IO_HH])
     814#define RSCAN0CFSTS0 (RSCAN0.CFSTS0.UINT32)
     815#define RSCAN0CFSTS0L (RSCAN0.CFSTS0.UINT16[R_IO_L])
     816#define RSCAN0CFSTS0LL (RSCAN0.CFSTS0.UINT8[R_IO_LL])
     817#define RSCAN0CFSTS0LH (RSCAN0.CFSTS0.UINT8[R_IO_LH])
     818#define RSCAN0CFSTS0H (RSCAN0.CFSTS0.UINT16[R_IO_H])
     819#define RSCAN0CFSTS0HL (RSCAN0.CFSTS0.UINT8[R_IO_HL])
     820#define RSCAN0CFSTS0HH (RSCAN0.CFSTS0.UINT8[R_IO_HH])
     821#define RSCAN0CFSTS1 (RSCAN0.CFSTS1.UINT32)
     822#define RSCAN0CFSTS1L (RSCAN0.CFSTS1.UINT16[R_IO_L])
     823#define RSCAN0CFSTS1LL (RSCAN0.CFSTS1.UINT8[R_IO_LL])
     824#define RSCAN0CFSTS1LH (RSCAN0.CFSTS1.UINT8[R_IO_LH])
     825#define RSCAN0CFSTS1H (RSCAN0.CFSTS1.UINT16[R_IO_H])
     826#define RSCAN0CFSTS1HL (RSCAN0.CFSTS1.UINT8[R_IO_HL])
     827#define RSCAN0CFSTS1HH (RSCAN0.CFSTS1.UINT8[R_IO_HH])
     828#define RSCAN0CFSTS2 (RSCAN0.CFSTS2.UINT32)
     829#define RSCAN0CFSTS2L (RSCAN0.CFSTS2.UINT16[R_IO_L])
     830#define RSCAN0CFSTS2LL (RSCAN0.CFSTS2.UINT8[R_IO_LL])
     831#define RSCAN0CFSTS2LH (RSCAN0.CFSTS2.UINT8[R_IO_LH])
     832#define RSCAN0CFSTS2H (RSCAN0.CFSTS2.UINT16[R_IO_H])
     833#define RSCAN0CFSTS2HL (RSCAN0.CFSTS2.UINT8[R_IO_HL])
     834#define RSCAN0CFSTS2HH (RSCAN0.CFSTS2.UINT8[R_IO_HH])
     835#define RSCAN0CFSTS3 (RSCAN0.CFSTS3.UINT32)
     836#define RSCAN0CFSTS3L (RSCAN0.CFSTS3.UINT16[R_IO_L])
     837#define RSCAN0CFSTS3LL (RSCAN0.CFSTS3.UINT8[R_IO_LL])
     838#define RSCAN0CFSTS3LH (RSCAN0.CFSTS3.UINT8[R_IO_LH])
     839#define RSCAN0CFSTS3H (RSCAN0.CFSTS3.UINT16[R_IO_H])
     840#define RSCAN0CFSTS3HL (RSCAN0.CFSTS3.UINT8[R_IO_HL])
     841#define RSCAN0CFSTS3HH (RSCAN0.CFSTS3.UINT8[R_IO_HH])
     842#define RSCAN0CFSTS4 (RSCAN0.CFSTS4.UINT32)
     843#define RSCAN0CFSTS4L (RSCAN0.CFSTS4.UINT16[R_IO_L])
     844#define RSCAN0CFSTS4LL (RSCAN0.CFSTS4.UINT8[R_IO_LL])
     845#define RSCAN0CFSTS4LH (RSCAN0.CFSTS4.UINT8[R_IO_LH])
     846#define RSCAN0CFSTS4H (RSCAN0.CFSTS4.UINT16[R_IO_H])
     847#define RSCAN0CFSTS4HL (RSCAN0.CFSTS4.UINT8[R_IO_HL])
     848#define RSCAN0CFSTS4HH (RSCAN0.CFSTS4.UINT8[R_IO_HH])
     849#define RSCAN0CFSTS5 (RSCAN0.CFSTS5.UINT32)
     850#define RSCAN0CFSTS5L (RSCAN0.CFSTS5.UINT16[R_IO_L])
     851#define RSCAN0CFSTS5LL (RSCAN0.CFSTS5.UINT8[R_IO_LL])
     852#define RSCAN0CFSTS5LH (RSCAN0.CFSTS5.UINT8[R_IO_LH])
     853#define RSCAN0CFSTS5H (RSCAN0.CFSTS5.UINT16[R_IO_H])
     854#define RSCAN0CFSTS5HL (RSCAN0.CFSTS5.UINT8[R_IO_HL])
     855#define RSCAN0CFSTS5HH (RSCAN0.CFSTS5.UINT8[R_IO_HH])
     856#define RSCAN0CFSTS6 (RSCAN0.CFSTS6.UINT32)
     857#define RSCAN0CFSTS6L (RSCAN0.CFSTS6.UINT16[R_IO_L])
     858#define RSCAN0CFSTS6LL (RSCAN0.CFSTS6.UINT8[R_IO_LL])
     859#define RSCAN0CFSTS6LH (RSCAN0.CFSTS6.UINT8[R_IO_LH])
     860#define RSCAN0CFSTS6H (RSCAN0.CFSTS6.UINT16[R_IO_H])
     861#define RSCAN0CFSTS6HL (RSCAN0.CFSTS6.UINT8[R_IO_HL])
     862#define RSCAN0CFSTS6HH (RSCAN0.CFSTS6.UINT8[R_IO_HH])
     863#define RSCAN0CFSTS7 (RSCAN0.CFSTS7.UINT32)
     864#define RSCAN0CFSTS7L (RSCAN0.CFSTS7.UINT16[R_IO_L])
     865#define RSCAN0CFSTS7LL (RSCAN0.CFSTS7.UINT8[R_IO_LL])
     866#define RSCAN0CFSTS7LH (RSCAN0.CFSTS7.UINT8[R_IO_LH])
     867#define RSCAN0CFSTS7H (RSCAN0.CFSTS7.UINT16[R_IO_H])
     868#define RSCAN0CFSTS7HL (RSCAN0.CFSTS7.UINT8[R_IO_HL])
     869#define RSCAN0CFSTS7HH (RSCAN0.CFSTS7.UINT8[R_IO_HH])
     870#define RSCAN0CFSTS8 (RSCAN0.CFSTS8.UINT32)
     871#define RSCAN0CFSTS8L (RSCAN0.CFSTS8.UINT16[R_IO_L])
     872#define RSCAN0CFSTS8LL (RSCAN0.CFSTS8.UINT8[R_IO_LL])
     873#define RSCAN0CFSTS8LH (RSCAN0.CFSTS8.UINT8[R_IO_LH])
     874#define RSCAN0CFSTS8H (RSCAN0.CFSTS8.UINT16[R_IO_H])
     875#define RSCAN0CFSTS8HL (RSCAN0.CFSTS8.UINT8[R_IO_HL])
     876#define RSCAN0CFSTS8HH (RSCAN0.CFSTS8.UINT8[R_IO_HH])
     877#define RSCAN0CFSTS9 (RSCAN0.CFSTS9.UINT32)
     878#define RSCAN0CFSTS9L (RSCAN0.CFSTS9.UINT16[R_IO_L])
     879#define RSCAN0CFSTS9LL (RSCAN0.CFSTS9.UINT8[R_IO_LL])
     880#define RSCAN0CFSTS9LH (RSCAN0.CFSTS9.UINT8[R_IO_LH])
     881#define RSCAN0CFSTS9H (RSCAN0.CFSTS9.UINT16[R_IO_H])
     882#define RSCAN0CFSTS9HL (RSCAN0.CFSTS9.UINT8[R_IO_HL])
     883#define RSCAN0CFSTS9HH (RSCAN0.CFSTS9.UINT8[R_IO_HH])
     884#define RSCAN0CFSTS10 (RSCAN0.CFSTS10.UINT32)
     885#define RSCAN0CFSTS10L (RSCAN0.CFSTS10.UINT16[R_IO_L])
     886#define RSCAN0CFSTS10LL (RSCAN0.CFSTS10.UINT8[R_IO_LL])
     887#define RSCAN0CFSTS10LH (RSCAN0.CFSTS10.UINT8[R_IO_LH])
     888#define RSCAN0CFSTS10H (RSCAN0.CFSTS10.UINT16[R_IO_H])
     889#define RSCAN0CFSTS10HL (RSCAN0.CFSTS10.UINT8[R_IO_HL])
     890#define RSCAN0CFSTS10HH (RSCAN0.CFSTS10.UINT8[R_IO_HH])
     891#define RSCAN0CFSTS11 (RSCAN0.CFSTS11.UINT32)
     892#define RSCAN0CFSTS11L (RSCAN0.CFSTS11.UINT16[R_IO_L])
     893#define RSCAN0CFSTS11LL (RSCAN0.CFSTS11.UINT8[R_IO_LL])
     894#define RSCAN0CFSTS11LH (RSCAN0.CFSTS11.UINT8[R_IO_LH])
     895#define RSCAN0CFSTS11H (RSCAN0.CFSTS11.UINT16[R_IO_H])
     896#define RSCAN0CFSTS11HL (RSCAN0.CFSTS11.UINT8[R_IO_HL])
     897#define RSCAN0CFSTS11HH (RSCAN0.CFSTS11.UINT8[R_IO_HH])
     898#define RSCAN0CFSTS12 (RSCAN0.CFSTS12.UINT32)
     899#define RSCAN0CFSTS12L (RSCAN0.CFSTS12.UINT16[R_IO_L])
     900#define RSCAN0CFSTS12LL (RSCAN0.CFSTS12.UINT8[R_IO_LL])
     901#define RSCAN0CFSTS12LH (RSCAN0.CFSTS12.UINT8[R_IO_LH])
     902#define RSCAN0CFSTS12H (RSCAN0.CFSTS12.UINT16[R_IO_H])
     903#define RSCAN0CFSTS12HL (RSCAN0.CFSTS12.UINT8[R_IO_HL])
     904#define RSCAN0CFSTS12HH (RSCAN0.CFSTS12.UINT8[R_IO_HH])
     905#define RSCAN0CFSTS13 (RSCAN0.CFSTS13.UINT32)
     906#define RSCAN0CFSTS13L (RSCAN0.CFSTS13.UINT16[R_IO_L])
     907#define RSCAN0CFSTS13LL (RSCAN0.CFSTS13.UINT8[R_IO_LL])
     908#define RSCAN0CFSTS13LH (RSCAN0.CFSTS13.UINT8[R_IO_LH])
     909#define RSCAN0CFSTS13H (RSCAN0.CFSTS13.UINT16[R_IO_H])
     910#define RSCAN0CFSTS13HL (RSCAN0.CFSTS13.UINT8[R_IO_HL])
     911#define RSCAN0CFSTS13HH (RSCAN0.CFSTS13.UINT8[R_IO_HH])
     912#define RSCAN0CFSTS14 (RSCAN0.CFSTS14.UINT32)
     913#define RSCAN0CFSTS14L (RSCAN0.CFSTS14.UINT16[R_IO_L])
     914#define RSCAN0CFSTS14LL (RSCAN0.CFSTS14.UINT8[R_IO_LL])
     915#define RSCAN0CFSTS14LH (RSCAN0.CFSTS14.UINT8[R_IO_LH])
     916#define RSCAN0CFSTS14H (RSCAN0.CFSTS14.UINT16[R_IO_H])
     917#define RSCAN0CFSTS14HL (RSCAN0.CFSTS14.UINT8[R_IO_HL])
     918#define RSCAN0CFSTS14HH (RSCAN0.CFSTS14.UINT8[R_IO_HH])
     919#define RSCAN0CFPCTR0 (RSCAN0.CFPCTR0.UINT32)
     920#define RSCAN0CFPCTR0L (RSCAN0.CFPCTR0.UINT16[R_IO_L])
     921#define RSCAN0CFPCTR0LL (RSCAN0.CFPCTR0.UINT8[R_IO_LL])
     922#define RSCAN0CFPCTR0LH (RSCAN0.CFPCTR0.UINT8[R_IO_LH])
     923#define RSCAN0CFPCTR0H (RSCAN0.CFPCTR0.UINT16[R_IO_H])
     924#define RSCAN0CFPCTR0HL (RSCAN0.CFPCTR0.UINT8[R_IO_HL])
     925#define RSCAN0CFPCTR0HH (RSCAN0.CFPCTR0.UINT8[R_IO_HH])
     926#define RSCAN0CFPCTR1 (RSCAN0.CFPCTR1.UINT32)
     927#define RSCAN0CFPCTR1L (RSCAN0.CFPCTR1.UINT16[R_IO_L])
     928#define RSCAN0CFPCTR1LL (RSCAN0.CFPCTR1.UINT8[R_IO_LL])
     929#define RSCAN0CFPCTR1LH (RSCAN0.CFPCTR1.UINT8[R_IO_LH])
     930#define RSCAN0CFPCTR1H (RSCAN0.CFPCTR1.UINT16[R_IO_H])
     931#define RSCAN0CFPCTR1HL (RSCAN0.CFPCTR1.UINT8[R_IO_HL])
     932#define RSCAN0CFPCTR1HH (RSCAN0.CFPCTR1.UINT8[R_IO_HH])
     933#define RSCAN0CFPCTR2 (RSCAN0.CFPCTR2.UINT32)
     934#define RSCAN0CFPCTR2L (RSCAN0.CFPCTR2.UINT16[R_IO_L])
     935#define RSCAN0CFPCTR2LL (RSCAN0.CFPCTR2.UINT8[R_IO_LL])
     936#define RSCAN0CFPCTR2LH (RSCAN0.CFPCTR2.UINT8[R_IO_LH])
     937#define RSCAN0CFPCTR2H (RSCAN0.CFPCTR2.UINT16[R_IO_H])
     938#define RSCAN0CFPCTR2HL (RSCAN0.CFPCTR2.UINT8[R_IO_HL])
     939#define RSCAN0CFPCTR2HH (RSCAN0.CFPCTR2.UINT8[R_IO_HH])
     940#define RSCAN0CFPCTR3 (RSCAN0.CFPCTR3.UINT32)
     941#define RSCAN0CFPCTR3L (RSCAN0.CFPCTR3.UINT16[R_IO_L])
     942#define RSCAN0CFPCTR3LL (RSCAN0.CFPCTR3.UINT8[R_IO_LL])
     943#define RSCAN0CFPCTR3LH (RSCAN0.CFPCTR3.UINT8[R_IO_LH])
     944#define RSCAN0CFPCTR3H (RSCAN0.CFPCTR3.UINT16[R_IO_H])
     945#define RSCAN0CFPCTR3HL (RSCAN0.CFPCTR3.UINT8[R_IO_HL])
     946#define RSCAN0CFPCTR3HH (RSCAN0.CFPCTR3.UINT8[R_IO_HH])
     947#define RSCAN0CFPCTR4 (RSCAN0.CFPCTR4.UINT32)
     948#define RSCAN0CFPCTR4L (RSCAN0.CFPCTR4.UINT16[R_IO_L])
     949#define RSCAN0CFPCTR4LL (RSCAN0.CFPCTR4.UINT8[R_IO_LL])
     950#define RSCAN0CFPCTR4LH (RSCAN0.CFPCTR4.UINT8[R_IO_LH])
     951#define RSCAN0CFPCTR4H (RSCAN0.CFPCTR4.UINT16[R_IO_H])
     952#define RSCAN0CFPCTR4HL (RSCAN0.CFPCTR4.UINT8[R_IO_HL])
     953#define RSCAN0CFPCTR4HH (RSCAN0.CFPCTR4.UINT8[R_IO_HH])
     954#define RSCAN0CFPCTR5 (RSCAN0.CFPCTR5.UINT32)
     955#define RSCAN0CFPCTR5L (RSCAN0.CFPCTR5.UINT16[R_IO_L])
     956#define RSCAN0CFPCTR5LL (RSCAN0.CFPCTR5.UINT8[R_IO_LL])
     957#define RSCAN0CFPCTR5LH (RSCAN0.CFPCTR5.UINT8[R_IO_LH])
     958#define RSCAN0CFPCTR5H (RSCAN0.CFPCTR5.UINT16[R_IO_H])
     959#define RSCAN0CFPCTR5HL (RSCAN0.CFPCTR5.UINT8[R_IO_HL])
     960#define RSCAN0CFPCTR5HH (RSCAN0.CFPCTR5.UINT8[R_IO_HH])
     961#define RSCAN0CFPCTR6 (RSCAN0.CFPCTR6.UINT32)
     962#define RSCAN0CFPCTR6L (RSCAN0.CFPCTR6.UINT16[R_IO_L])
     963#define RSCAN0CFPCTR6LL (RSCAN0.CFPCTR6.UINT8[R_IO_LL])
     964#define RSCAN0CFPCTR6LH (RSCAN0.CFPCTR6.UINT8[R_IO_LH])
     965#define RSCAN0CFPCTR6H (RSCAN0.CFPCTR6.UINT16[R_IO_H])
     966#define RSCAN0CFPCTR6HL (RSCAN0.CFPCTR6.UINT8[R_IO_HL])
     967#define RSCAN0CFPCTR6HH (RSCAN0.CFPCTR6.UINT8[R_IO_HH])
     968#define RSCAN0CFPCTR7 (RSCAN0.CFPCTR7.UINT32)
     969#define RSCAN0CFPCTR7L (RSCAN0.CFPCTR7.UINT16[R_IO_L])
     970#define RSCAN0CFPCTR7LL (RSCAN0.CFPCTR7.UINT8[R_IO_LL])
     971#define RSCAN0CFPCTR7LH (RSCAN0.CFPCTR7.UINT8[R_IO_LH])
     972#define RSCAN0CFPCTR7H (RSCAN0.CFPCTR7.UINT16[R_IO_H])
     973#define RSCAN0CFPCTR7HL (RSCAN0.CFPCTR7.UINT8[R_IO_HL])
     974#define RSCAN0CFPCTR7HH (RSCAN0.CFPCTR7.UINT8[R_IO_HH])
     975#define RSCAN0CFPCTR8 (RSCAN0.CFPCTR8.UINT32)
     976#define RSCAN0CFPCTR8L (RSCAN0.CFPCTR8.UINT16[R_IO_L])
     977#define RSCAN0CFPCTR8LL (RSCAN0.CFPCTR8.UINT8[R_IO_LL])
     978#define RSCAN0CFPCTR8LH (RSCAN0.CFPCTR8.UINT8[R_IO_LH])
     979#define RSCAN0CFPCTR8H (RSCAN0.CFPCTR8.UINT16[R_IO_H])
     980#define RSCAN0CFPCTR8HL (RSCAN0.CFPCTR8.UINT8[R_IO_HL])
     981#define RSCAN0CFPCTR8HH (RSCAN0.CFPCTR8.UINT8[R_IO_HH])
     982#define RSCAN0CFPCTR9 (RSCAN0.CFPCTR9.UINT32)
     983#define RSCAN0CFPCTR9L (RSCAN0.CFPCTR9.UINT16[R_IO_L])
     984#define RSCAN0CFPCTR9LL (RSCAN0.CFPCTR9.UINT8[R_IO_LL])
     985#define RSCAN0CFPCTR9LH (RSCAN0.CFPCTR9.UINT8[R_IO_LH])
     986#define RSCAN0CFPCTR9H (RSCAN0.CFPCTR9.UINT16[R_IO_H])
     987#define RSCAN0CFPCTR9HL (RSCAN0.CFPCTR9.UINT8[R_IO_HL])
     988#define RSCAN0CFPCTR9HH (RSCAN0.CFPCTR9.UINT8[R_IO_HH])
     989#define RSCAN0CFPCTR10 (RSCAN0.CFPCTR10.UINT32)
     990#define RSCAN0CFPCTR10L (RSCAN0.CFPCTR10.UINT16[R_IO_L])
     991#define RSCAN0CFPCTR10LL (RSCAN0.CFPCTR10.UINT8[R_IO_LL])
     992#define RSCAN0CFPCTR10LH (RSCAN0.CFPCTR10.UINT8[R_IO_LH])
     993#define RSCAN0CFPCTR10H (RSCAN0.CFPCTR10.UINT16[R_IO_H])
     994#define RSCAN0CFPCTR10HL (RSCAN0.CFPCTR10.UINT8[R_IO_HL])
     995#define RSCAN0CFPCTR10HH (RSCAN0.CFPCTR10.UINT8[R_IO_HH])
     996#define RSCAN0CFPCTR11 (RSCAN0.CFPCTR11.UINT32)
     997#define RSCAN0CFPCTR11L (RSCAN0.CFPCTR11.UINT16[R_IO_L])
     998#define RSCAN0CFPCTR11LL (RSCAN0.CFPCTR11.UINT8[R_IO_LL])
     999#define RSCAN0CFPCTR11LH (RSCAN0.CFPCTR11.UINT8[R_IO_LH])
     1000#define RSCAN0CFPCTR11H (RSCAN0.CFPCTR11.UINT16[R_IO_H])
     1001#define RSCAN0CFPCTR11HL (RSCAN0.CFPCTR11.UINT8[R_IO_HL])
     1002#define RSCAN0CFPCTR11HH (RSCAN0.CFPCTR11.UINT8[R_IO_HH])
     1003#define RSCAN0CFPCTR12 (RSCAN0.CFPCTR12.UINT32)
     1004#define RSCAN0CFPCTR12L (RSCAN0.CFPCTR12.UINT16[R_IO_L])
     1005#define RSCAN0CFPCTR12LL (RSCAN0.CFPCTR12.UINT8[R_IO_LL])
     1006#define RSCAN0CFPCTR12LH (RSCAN0.CFPCTR12.UINT8[R_IO_LH])
     1007#define RSCAN0CFPCTR12H (RSCAN0.CFPCTR12.UINT16[R_IO_H])
     1008#define RSCAN0CFPCTR12HL (RSCAN0.CFPCTR12.UINT8[R_IO_HL])
     1009#define RSCAN0CFPCTR12HH (RSCAN0.CFPCTR12.UINT8[R_IO_HH])
     1010#define RSCAN0CFPCTR13 (RSCAN0.CFPCTR13.UINT32)
     1011#define RSCAN0CFPCTR13L (RSCAN0.CFPCTR13.UINT16[R_IO_L])
     1012#define RSCAN0CFPCTR13LL (RSCAN0.CFPCTR13.UINT8[R_IO_LL])
     1013#define RSCAN0CFPCTR13LH (RSCAN0.CFPCTR13.UINT8[R_IO_LH])
     1014#define RSCAN0CFPCTR13H (RSCAN0.CFPCTR13.UINT16[R_IO_H])
     1015#define RSCAN0CFPCTR13HL (RSCAN0.CFPCTR13.UINT8[R_IO_HL])
     1016#define RSCAN0CFPCTR13HH (RSCAN0.CFPCTR13.UINT8[R_IO_HH])
     1017#define RSCAN0CFPCTR14 (RSCAN0.CFPCTR14.UINT32)
     1018#define RSCAN0CFPCTR14L (RSCAN0.CFPCTR14.UINT16[R_IO_L])
     1019#define RSCAN0CFPCTR14LL (RSCAN0.CFPCTR14.UINT8[R_IO_LL])
     1020#define RSCAN0CFPCTR14LH (RSCAN0.CFPCTR14.UINT8[R_IO_LH])
     1021#define RSCAN0CFPCTR14H (RSCAN0.CFPCTR14.UINT16[R_IO_H])
     1022#define RSCAN0CFPCTR14HL (RSCAN0.CFPCTR14.UINT8[R_IO_HL])
     1023#define RSCAN0CFPCTR14HH (RSCAN0.CFPCTR14.UINT8[R_IO_HH])
     1024#define RSCAN0FESTS (RSCAN0.FESTS.UINT32)
     1025#define RSCAN0FESTSL (RSCAN0.FESTS.UINT16[R_IO_L])
     1026#define RSCAN0FESTSLL (RSCAN0.FESTS.UINT8[R_IO_LL])
     1027#define RSCAN0FESTSLH (RSCAN0.FESTS.UINT8[R_IO_LH])
     1028#define RSCAN0FESTSH (RSCAN0.FESTS.UINT16[R_IO_H])
     1029#define RSCAN0FESTSHL (RSCAN0.FESTS.UINT8[R_IO_HL])
     1030#define RSCAN0FESTSHH (RSCAN0.FESTS.UINT8[R_IO_HH])
     1031#define RSCAN0FFSTS (RSCAN0.FFSTS.UINT32)
     1032#define RSCAN0FFSTSL (RSCAN0.FFSTS.UINT16[R_IO_L])
     1033#define RSCAN0FFSTSLL (RSCAN0.FFSTS.UINT8[R_IO_LL])
     1034#define RSCAN0FFSTSLH (RSCAN0.FFSTS.UINT8[R_IO_LH])
     1035#define RSCAN0FFSTSH (RSCAN0.FFSTS.UINT16[R_IO_H])
     1036#define RSCAN0FFSTSHL (RSCAN0.FFSTS.UINT8[R_IO_HL])
     1037#define RSCAN0FFSTSHH (RSCAN0.FFSTS.UINT8[R_IO_HH])
     1038#define RSCAN0FMSTS (RSCAN0.FMSTS.UINT32)
     1039#define RSCAN0FMSTSL (RSCAN0.FMSTS.UINT16[R_IO_L])
     1040#define RSCAN0FMSTSLL (RSCAN0.FMSTS.UINT8[R_IO_LL])
     1041#define RSCAN0FMSTSLH (RSCAN0.FMSTS.UINT8[R_IO_LH])
     1042#define RSCAN0FMSTSH (RSCAN0.FMSTS.UINT16[R_IO_H])
     1043#define RSCAN0FMSTSHL (RSCAN0.FMSTS.UINT8[R_IO_HL])
     1044#define RSCAN0FMSTSHH (RSCAN0.FMSTS.UINT8[R_IO_HH])
     1045#define RSCAN0RFISTS (RSCAN0.RFISTS.UINT32)
     1046#define RSCAN0RFISTSL (RSCAN0.RFISTS.UINT16[R_IO_L])
     1047#define RSCAN0RFISTSLL (RSCAN0.RFISTS.UINT8[R_IO_LL])
     1048#define RSCAN0RFISTSLH (RSCAN0.RFISTS.UINT8[R_IO_LH])
     1049#define RSCAN0RFISTSH (RSCAN0.RFISTS.UINT16[R_IO_H])
     1050#define RSCAN0RFISTSHL (RSCAN0.RFISTS.UINT8[R_IO_HL])
     1051#define RSCAN0RFISTSHH (RSCAN0.RFISTS.UINT8[R_IO_HH])
     1052#define RSCAN0CFRISTS (RSCAN0.CFRISTS.UINT32)
     1053#define RSCAN0CFRISTSL (RSCAN0.CFRISTS.UINT16[R_IO_L])
     1054#define RSCAN0CFRISTSLL (RSCAN0.CFRISTS.UINT8[R_IO_LL])
     1055#define RSCAN0CFRISTSLH (RSCAN0.CFRISTS.UINT8[R_IO_LH])
     1056#define RSCAN0CFRISTSH (RSCAN0.CFRISTS.UINT16[R_IO_H])
     1057#define RSCAN0CFRISTSHL (RSCAN0.CFRISTS.UINT8[R_IO_HL])
     1058#define RSCAN0CFRISTSHH (RSCAN0.CFRISTS.UINT8[R_IO_HH])
     1059#define RSCAN0CFTISTS (RSCAN0.CFTISTS.UINT32)
     1060#define RSCAN0CFTISTSL (RSCAN0.CFTISTS.UINT16[R_IO_L])
     1061#define RSCAN0CFTISTSLL (RSCAN0.CFTISTS.UINT8[R_IO_LL])
     1062#define RSCAN0CFTISTSLH (RSCAN0.CFTISTS.UINT8[R_IO_LH])
     1063#define RSCAN0CFTISTSH (RSCAN0.CFTISTS.UINT16[R_IO_H])
     1064#define RSCAN0CFTISTSHL (RSCAN0.CFTISTS.UINT8[R_IO_HL])
     1065#define RSCAN0CFTISTSHH (RSCAN0.CFTISTS.UINT8[R_IO_HH])
     1066#define RSCAN0TMC0 (RSCAN0.TMC0)
     1067#define RSCAN0TMC1 (RSCAN0.TMC1)
     1068#define RSCAN0TMC2 (RSCAN0.TMC2)
     1069#define RSCAN0TMC3 (RSCAN0.TMC3)
     1070#define RSCAN0TMC4 (RSCAN0.TMC4)
     1071#define RSCAN0TMC5 (RSCAN0.TMC5)
     1072#define RSCAN0TMC6 (RSCAN0.TMC6)
     1073#define RSCAN0TMC7 (RSCAN0.TMC7)
     1074#define RSCAN0TMC8 (RSCAN0.TMC8)
     1075#define RSCAN0TMC9 (RSCAN0.TMC9)
     1076#define RSCAN0TMC10 (RSCAN0.TMC10)
     1077#define RSCAN0TMC11 (RSCAN0.TMC11)
     1078#define RSCAN0TMC12 (RSCAN0.TMC12)
     1079#define RSCAN0TMC13 (RSCAN0.TMC13)
     1080#define RSCAN0TMC14 (RSCAN0.TMC14)
     1081#define RSCAN0TMC15 (RSCAN0.TMC15)
     1082#define RSCAN0TMC16 (RSCAN0.TMC16)
     1083#define RSCAN0TMC17 (RSCAN0.TMC17)
     1084#define RSCAN0TMC18 (RSCAN0.TMC18)
     1085#define RSCAN0TMC19 (RSCAN0.TMC19)
     1086#define RSCAN0TMC20 (RSCAN0.TMC20)
     1087#define RSCAN0TMC21 (RSCAN0.TMC21)
     1088#define RSCAN0TMC22 (RSCAN0.TMC22)
     1089#define RSCAN0TMC23 (RSCAN0.TMC23)
     1090#define RSCAN0TMC24 (RSCAN0.TMC24)
     1091#define RSCAN0TMC25 (RSCAN0.TMC25)
     1092#define RSCAN0TMC26 (RSCAN0.TMC26)
     1093#define RSCAN0TMC27 (RSCAN0.TMC27)
     1094#define RSCAN0TMC28 (RSCAN0.TMC28)
     1095#define RSCAN0TMC29 (RSCAN0.TMC29)
     1096#define RSCAN0TMC30 (RSCAN0.TMC30)
     1097#define RSCAN0TMC31 (RSCAN0.TMC31)
     1098#define RSCAN0TMC32 (RSCAN0.TMC32)
     1099#define RSCAN0TMC33 (RSCAN0.TMC33)
     1100#define RSCAN0TMC34 (RSCAN0.TMC34)
     1101#define RSCAN0TMC35 (RSCAN0.TMC35)
     1102#define RSCAN0TMC36 (RSCAN0.TMC36)
     1103#define RSCAN0TMC37 (RSCAN0.TMC37)
     1104#define RSCAN0TMC38 (RSCAN0.TMC38)
     1105#define RSCAN0TMC39 (RSCAN0.TMC39)
     1106#define RSCAN0TMC40 (RSCAN0.TMC40)
     1107#define RSCAN0TMC41 (RSCAN0.TMC41)
     1108#define RSCAN0TMC42 (RSCAN0.TMC42)
     1109#define RSCAN0TMC43 (RSCAN0.TMC43)
     1110#define RSCAN0TMC44 (RSCAN0.TMC44)
     1111#define RSCAN0TMC45 (RSCAN0.TMC45)
     1112#define RSCAN0TMC46 (RSCAN0.TMC46)
     1113#define RSCAN0TMC47 (RSCAN0.TMC47)
     1114#define RSCAN0TMC48 (RSCAN0.TMC48)
     1115#define RSCAN0TMC49 (RSCAN0.TMC49)
     1116#define RSCAN0TMC50 (RSCAN0.TMC50)
     1117#define RSCAN0TMC51 (RSCAN0.TMC51)
     1118#define RSCAN0TMC52 (RSCAN0.TMC52)
     1119#define RSCAN0TMC53 (RSCAN0.TMC53)
     1120#define RSCAN0TMC54 (RSCAN0.TMC54)
     1121#define RSCAN0TMC55 (RSCAN0.TMC55)
     1122#define RSCAN0TMC56 (RSCAN0.TMC56)
     1123#define RSCAN0TMC57 (RSCAN0.TMC57)
     1124#define RSCAN0TMC58 (RSCAN0.TMC58)
     1125#define RSCAN0TMC59 (RSCAN0.TMC59)
     1126#define RSCAN0TMC60 (RSCAN0.TMC60)
     1127#define RSCAN0TMC61 (RSCAN0.TMC61)
     1128#define RSCAN0TMC62 (RSCAN0.TMC62)
     1129#define RSCAN0TMC63 (RSCAN0.TMC63)
     1130#define RSCAN0TMC64 (RSCAN0.TMC64)
     1131#define RSCAN0TMC65 (RSCAN0.TMC65)
     1132#define RSCAN0TMC66 (RSCAN0.TMC66)
     1133#define RSCAN0TMC67 (RSCAN0.TMC67)
     1134#define RSCAN0TMC68 (RSCAN0.TMC68)
     1135#define RSCAN0TMC69 (RSCAN0.TMC69)
     1136#define RSCAN0TMC70 (RSCAN0.TMC70)
     1137#define RSCAN0TMC71 (RSCAN0.TMC71)
     1138#define RSCAN0TMC72 (RSCAN0.TMC72)
     1139#define RSCAN0TMC73 (RSCAN0.TMC73)
     1140#define RSCAN0TMC74 (RSCAN0.TMC74)
     1141#define RSCAN0TMC75 (RSCAN0.TMC75)
     1142#define RSCAN0TMC76 (RSCAN0.TMC76)
     1143#define RSCAN0TMC77 (RSCAN0.TMC77)
     1144#define RSCAN0TMC78 (RSCAN0.TMC78)
     1145#define RSCAN0TMC79 (RSCAN0.TMC79)
     1146#define RSCAN0TMSTS0 (RSCAN0.TMSTS0)
     1147#define RSCAN0TMSTS1 (RSCAN0.TMSTS1)
     1148#define RSCAN0TMSTS2 (RSCAN0.TMSTS2)
     1149#define RSCAN0TMSTS3 (RSCAN0.TMSTS3)
     1150#define RSCAN0TMSTS4 (RSCAN0.TMSTS4)
     1151#define RSCAN0TMSTS5 (RSCAN0.TMSTS5)
     1152#define RSCAN0TMSTS6 (RSCAN0.TMSTS6)
     1153#define RSCAN0TMSTS7 (RSCAN0.TMSTS7)
     1154#define RSCAN0TMSTS8 (RSCAN0.TMSTS8)
     1155#define RSCAN0TMSTS9 (RSCAN0.TMSTS9)
     1156#define RSCAN0TMSTS10 (RSCAN0.TMSTS10)
     1157#define RSCAN0TMSTS11 (RSCAN0.TMSTS11)
     1158#define RSCAN0TMSTS12 (RSCAN0.TMSTS12)
     1159#define RSCAN0TMSTS13 (RSCAN0.TMSTS13)
     1160#define RSCAN0TMSTS14 (RSCAN0.TMSTS14)
     1161#define RSCAN0TMSTS15 (RSCAN0.TMSTS15)
     1162#define RSCAN0TMSTS16 (RSCAN0.TMSTS16)
     1163#define RSCAN0TMSTS17 (RSCAN0.TMSTS17)
     1164#define RSCAN0TMSTS18 (RSCAN0.TMSTS18)
     1165#define RSCAN0TMSTS19 (RSCAN0.TMSTS19)
     1166#define RSCAN0TMSTS20 (RSCAN0.TMSTS20)
     1167#define RSCAN0TMSTS21 (RSCAN0.TMSTS21)
     1168#define RSCAN0TMSTS22 (RSCAN0.TMSTS22)
     1169#define RSCAN0TMSTS23 (RSCAN0.TMSTS23)
     1170#define RSCAN0TMSTS24 (RSCAN0.TMSTS24)
     1171#define RSCAN0TMSTS25 (RSCAN0.TMSTS25)
     1172#define RSCAN0TMSTS26 (RSCAN0.TMSTS26)
     1173#define RSCAN0TMSTS27 (RSCAN0.TMSTS27)
     1174#define RSCAN0TMSTS28 (RSCAN0.TMSTS28)
     1175#define RSCAN0TMSTS29 (RSCAN0.TMSTS29)
     1176#define RSCAN0TMSTS30 (RSCAN0.TMSTS30)
     1177#define RSCAN0TMSTS31 (RSCAN0.TMSTS31)
     1178#define RSCAN0TMSTS32 (RSCAN0.TMSTS32)
     1179#define RSCAN0TMSTS33 (RSCAN0.TMSTS33)
     1180#define RSCAN0TMSTS34 (RSCAN0.TMSTS34)
     1181#define RSCAN0TMSTS35 (RSCAN0.TMSTS35)
     1182#define RSCAN0TMSTS36 (RSCAN0.TMSTS36)
     1183#define RSCAN0TMSTS37 (RSCAN0.TMSTS37)
     1184#define RSCAN0TMSTS38 (RSCAN0.TMSTS38)
     1185#define RSCAN0TMSTS39 (RSCAN0.TMSTS39)
     1186#define RSCAN0TMSTS40 (RSCAN0.TMSTS40)
     1187#define RSCAN0TMSTS41 (RSCAN0.TMSTS41)
     1188#define RSCAN0TMSTS42 (RSCAN0.TMSTS42)
     1189#define RSCAN0TMSTS43 (RSCAN0.TMSTS43)
     1190#define RSCAN0TMSTS44 (RSCAN0.TMSTS44)
     1191#define RSCAN0TMSTS45 (RSCAN0.TMSTS45)
     1192#define RSCAN0TMSTS46 (RSCAN0.TMSTS46)
     1193#define RSCAN0TMSTS47 (RSCAN0.TMSTS47)
     1194#define RSCAN0TMSTS48 (RSCAN0.TMSTS48)
     1195#define RSCAN0TMSTS49 (RSCAN0.TMSTS49)
     1196#define RSCAN0TMSTS50 (RSCAN0.TMSTS50)
     1197#define RSCAN0TMSTS51 (RSCAN0.TMSTS51)
     1198#define RSCAN0TMSTS52 (RSCAN0.TMSTS52)
     1199#define RSCAN0TMSTS53 (RSCAN0.TMSTS53)
     1200#define RSCAN0TMSTS54 (RSCAN0.TMSTS54)
     1201#define RSCAN0TMSTS55 (RSCAN0.TMSTS55)
     1202#define RSCAN0TMSTS56 (RSCAN0.TMSTS56)
     1203#define RSCAN0TMSTS57 (RSCAN0.TMSTS57)
     1204#define RSCAN0TMSTS58 (RSCAN0.TMSTS58)
     1205#define RSCAN0TMSTS59 (RSCAN0.TMSTS59)
     1206#define RSCAN0TMSTS60 (RSCAN0.TMSTS60)
     1207#define RSCAN0TMSTS61 (RSCAN0.TMSTS61)
     1208#define RSCAN0TMSTS62 (RSCAN0.TMSTS62)
     1209#define RSCAN0TMSTS63 (RSCAN0.TMSTS63)
     1210#define RSCAN0TMSTS64 (RSCAN0.TMSTS64)
     1211#define RSCAN0TMSTS65 (RSCAN0.TMSTS65)
     1212#define RSCAN0TMSTS66 (RSCAN0.TMSTS66)
     1213#define RSCAN0TMSTS67 (RSCAN0.TMSTS67)
     1214#define RSCAN0TMSTS68 (RSCAN0.TMSTS68)
     1215#define RSCAN0TMSTS69 (RSCAN0.TMSTS69)
     1216#define RSCAN0TMSTS70 (RSCAN0.TMSTS70)
     1217#define RSCAN0TMSTS71 (RSCAN0.TMSTS71)
     1218#define RSCAN0TMSTS72 (RSCAN0.TMSTS72)
     1219#define RSCAN0TMSTS73 (RSCAN0.TMSTS73)
     1220#define RSCAN0TMSTS74 (RSCAN0.TMSTS74)
     1221#define RSCAN0TMSTS75 (RSCAN0.TMSTS75)
     1222#define RSCAN0TMSTS76 (RSCAN0.TMSTS76)
     1223#define RSCAN0TMSTS77 (RSCAN0.TMSTS77)
     1224#define RSCAN0TMSTS78 (RSCAN0.TMSTS78)
     1225#define RSCAN0TMSTS79 (RSCAN0.TMSTS79)
     1226#define RSCAN0TMTRSTS0 (RSCAN0.TMTRSTS0.UINT32)
     1227#define RSCAN0TMTRSTS0L (RSCAN0.TMTRSTS0.UINT16[R_IO_L])
     1228#define RSCAN0TMTRSTS0LL (RSCAN0.TMTRSTS0.UINT8[R_IO_LL])
     1229#define RSCAN0TMTRSTS0LH (RSCAN0.TMTRSTS0.UINT8[R_IO_LH])
     1230#define RSCAN0TMTRSTS0H (RSCAN0.TMTRSTS0.UINT16[R_IO_H])
     1231#define RSCAN0TMTRSTS0HL (RSCAN0.TMTRSTS0.UINT8[R_IO_HL])
     1232#define RSCAN0TMTRSTS0HH (RSCAN0.TMTRSTS0.UINT8[R_IO_HH])
     1233#define RSCAN0TMTRSTS1 (RSCAN0.TMTRSTS1.UINT32)
     1234#define RSCAN0TMTRSTS1L (RSCAN0.TMTRSTS1.UINT16[R_IO_L])
     1235#define RSCAN0TMTRSTS1LL (RSCAN0.TMTRSTS1.UINT8[R_IO_LL])
     1236#define RSCAN0TMTRSTS1LH (RSCAN0.TMTRSTS1.UINT8[R_IO_LH])
     1237#define RSCAN0TMTRSTS1H (RSCAN0.TMTRSTS1.UINT16[R_IO_H])
     1238#define RSCAN0TMTRSTS1HL (RSCAN0.TMTRSTS1.UINT8[R_IO_HL])
     1239#define RSCAN0TMTRSTS1HH (RSCAN0.TMTRSTS1.UINT8[R_IO_HH])
     1240#define RSCAN0TMTRSTS2 (RSCAN0.TMTRSTS2.UINT32)
     1241#define RSCAN0TMTRSTS2L (RSCAN0.TMTRSTS2.UINT16[R_IO_L])
     1242#define RSCAN0TMTRSTS2LL (RSCAN0.TMTRSTS2.UINT8[R_IO_LL])
     1243#define RSCAN0TMTRSTS2LH (RSCAN0.TMTRSTS2.UINT8[R_IO_LH])
     1244#define RSCAN0TMTRSTS2H (RSCAN0.TMTRSTS2.UINT16[R_IO_H])
     1245#define RSCAN0TMTRSTS2HL (RSCAN0.TMTRSTS2.UINT8[R_IO_HL])
     1246#define RSCAN0TMTRSTS2HH (RSCAN0.TMTRSTS2.UINT8[R_IO_HH])
     1247#define RSCAN0TMTARSTS0 (RSCAN0.TMTARSTS0.UINT32)
     1248#define RSCAN0TMTARSTS0L (RSCAN0.TMTARSTS0.UINT16[R_IO_L])
     1249#define RSCAN0TMTARSTS0LL (RSCAN0.TMTARSTS0.UINT8[R_IO_LL])
     1250#define RSCAN0TMTARSTS0LH (RSCAN0.TMTARSTS0.UINT8[R_IO_LH])
     1251#define RSCAN0TMTARSTS0H (RSCAN0.TMTARSTS0.UINT16[R_IO_H])
     1252#define RSCAN0TMTARSTS0HL (RSCAN0.TMTARSTS0.UINT8[R_IO_HL])
     1253#define RSCAN0TMTARSTS0HH (RSCAN0.TMTARSTS0.UINT8[R_IO_HH])
     1254#define RSCAN0TMTARSTS1 (RSCAN0.TMTARSTS1.UINT32)
     1255#define RSCAN0TMTARSTS1L (RSCAN0.TMTARSTS1.UINT16[R_IO_L])
     1256#define RSCAN0TMTARSTS1LL (RSCAN0.TMTARSTS1.UINT8[R_IO_LL])
     1257#define RSCAN0TMTARSTS1LH (RSCAN0.TMTARSTS1.UINT8[R_IO_LH])
     1258#define RSCAN0TMTARSTS1H (RSCAN0.TMTARSTS1.UINT16[R_IO_H])
     1259#define RSCAN0TMTARSTS1HL (RSCAN0.TMTARSTS1.UINT8[R_IO_HL])
     1260#define RSCAN0TMTARSTS1HH (RSCAN0.TMTARSTS1.UINT8[R_IO_HH])
     1261#define RSCAN0TMTARSTS2 (RSCAN0.TMTARSTS2.UINT32)
     1262#define RSCAN0TMTARSTS2L (RSCAN0.TMTARSTS2.UINT16[R_IO_L])
     1263#define RSCAN0TMTARSTS2LL (RSCAN0.TMTARSTS2.UINT8[R_IO_LL])
     1264#define RSCAN0TMTARSTS2LH (RSCAN0.TMTARSTS2.UINT8[R_IO_LH])
     1265#define RSCAN0TMTARSTS2H (RSCAN0.TMTARSTS2.UINT16[R_IO_H])
     1266#define RSCAN0TMTARSTS2HL (RSCAN0.TMTARSTS2.UINT8[R_IO_HL])
     1267#define RSCAN0TMTARSTS2HH (RSCAN0.TMTARSTS2.UINT8[R_IO_HH])
     1268#define RSCAN0TMTCSTS0 (RSCAN0.TMTCSTS0.UINT32)
     1269#define RSCAN0TMTCSTS0L (RSCAN0.TMTCSTS0.UINT16[R_IO_L])
     1270#define RSCAN0TMTCSTS0LL (RSCAN0.TMTCSTS0.UINT8[R_IO_LL])
     1271#define RSCAN0TMTCSTS0LH (RSCAN0.TMTCSTS0.UINT8[R_IO_LH])
     1272#define RSCAN0TMTCSTS0H (RSCAN0.TMTCSTS0.UINT16[R_IO_H])
     1273#define RSCAN0TMTCSTS0HL (RSCAN0.TMTCSTS0.UINT8[R_IO_HL])
     1274#define RSCAN0TMTCSTS0HH (RSCAN0.TMTCSTS0.UINT8[R_IO_HH])
     1275#define RSCAN0TMTCSTS1 (RSCAN0.TMTCSTS1.UINT32)
     1276#define RSCAN0TMTCSTS1L (RSCAN0.TMTCSTS1.UINT16[R_IO_L])
     1277#define RSCAN0TMTCSTS1LL (RSCAN0.TMTCSTS1.UINT8[R_IO_LL])
     1278#define RSCAN0TMTCSTS1LH (RSCAN0.TMTCSTS1.UINT8[R_IO_LH])
     1279#define RSCAN0TMTCSTS1H (RSCAN0.TMTCSTS1.UINT16[R_IO_H])
     1280#define RSCAN0TMTCSTS1HL (RSCAN0.TMTCSTS1.UINT8[R_IO_HL])
     1281#define RSCAN0TMTCSTS1HH (RSCAN0.TMTCSTS1.UINT8[R_IO_HH])
     1282#define RSCAN0TMTCSTS2 (RSCAN0.TMTCSTS2.UINT32)
     1283#define RSCAN0TMTCSTS2L (RSCAN0.TMTCSTS2.UINT16[R_IO_L])
     1284#define RSCAN0TMTCSTS2LL (RSCAN0.TMTCSTS2.UINT8[R_IO_LL])
     1285#define RSCAN0TMTCSTS2LH (RSCAN0.TMTCSTS2.UINT8[R_IO_LH])
     1286#define RSCAN0TMTCSTS2H (RSCAN0.TMTCSTS2.UINT16[R_IO_H])
     1287#define RSCAN0TMTCSTS2HL (RSCAN0.TMTCSTS2.UINT8[R_IO_HL])
     1288#define RSCAN0TMTCSTS2HH (RSCAN0.TMTCSTS2.UINT8[R_IO_HH])
     1289#define RSCAN0TMTASTS0 (RSCAN0.TMTASTS0.UINT32)
     1290#define RSCAN0TMTASTS0L (RSCAN0.TMTASTS0.UINT16[R_IO_L])
     1291#define RSCAN0TMTASTS0LL (RSCAN0.TMTASTS0.UINT8[R_IO_LL])
     1292#define RSCAN0TMTASTS0LH (RSCAN0.TMTASTS0.UINT8[R_IO_LH])
     1293#define RSCAN0TMTASTS0H (RSCAN0.TMTASTS0.UINT16[R_IO_H])
     1294#define RSCAN0TMTASTS0HL (RSCAN0.TMTASTS0.UINT8[R_IO_HL])
     1295#define RSCAN0TMTASTS0HH (RSCAN0.TMTASTS0.UINT8[R_IO_HH])
     1296#define RSCAN0TMTASTS1 (RSCAN0.TMTASTS1.UINT32)
     1297#define RSCAN0TMTASTS1L (RSCAN0.TMTASTS1.UINT16[R_IO_L])
     1298#define RSCAN0TMTASTS1LL (RSCAN0.TMTASTS1.UINT8[R_IO_LL])
     1299#define RSCAN0TMTASTS1LH (RSCAN0.TMTASTS1.UINT8[R_IO_LH])
     1300#define RSCAN0TMTASTS1H (RSCAN0.TMTASTS1.UINT16[R_IO_H])
     1301#define RSCAN0TMTASTS1HL (RSCAN0.TMTASTS1.UINT8[R_IO_HL])
     1302#define RSCAN0TMTASTS1HH (RSCAN0.TMTASTS1.UINT8[R_IO_HH])
     1303#define RSCAN0TMTASTS2 (RSCAN0.TMTASTS2.UINT32)
     1304#define RSCAN0TMTASTS2L (RSCAN0.TMTASTS2.UINT16[R_IO_L])
     1305#define RSCAN0TMTASTS2LL (RSCAN0.TMTASTS2.UINT8[R_IO_LL])
     1306#define RSCAN0TMTASTS2LH (RSCAN0.TMTASTS2.UINT8[R_IO_LH])
     1307#define RSCAN0TMTASTS2H (RSCAN0.TMTASTS2.UINT16[R_IO_H])
     1308#define RSCAN0TMTASTS2HL (RSCAN0.TMTASTS2.UINT8[R_IO_HL])
     1309#define RSCAN0TMTASTS2HH (RSCAN0.TMTASTS2.UINT8[R_IO_HH])
     1310#define RSCAN0TMIEC0 (RSCAN0.TMIEC0.UINT32)
     1311#define RSCAN0TMIEC0L (RSCAN0.TMIEC0.UINT16[R_IO_L])
     1312#define RSCAN0TMIEC0LL (RSCAN0.TMIEC0.UINT8[R_IO_LL])
     1313#define RSCAN0TMIEC0LH (RSCAN0.TMIEC0.UINT8[R_IO_LH])
     1314#define RSCAN0TMIEC0H (RSCAN0.TMIEC0.UINT16[R_IO_H])
     1315#define RSCAN0TMIEC0HL (RSCAN0.TMIEC0.UINT8[R_IO_HL])
     1316#define RSCAN0TMIEC0HH (RSCAN0.TMIEC0.UINT8[R_IO_HH])
     1317#define RSCAN0TMIEC1 (RSCAN0.TMIEC1.UINT32)
     1318#define RSCAN0TMIEC1L (RSCAN0.TMIEC1.UINT16[R_IO_L])
     1319#define RSCAN0TMIEC1LL (RSCAN0.TMIEC1.UINT8[R_IO_LL])
     1320#define RSCAN0TMIEC1LH (RSCAN0.TMIEC1.UINT8[R_IO_LH])
     1321#define RSCAN0TMIEC1H (RSCAN0.TMIEC1.UINT16[R_IO_H])
     1322#define RSCAN0TMIEC1HL (RSCAN0.TMIEC1.UINT8[R_IO_HL])
     1323#define RSCAN0TMIEC1HH (RSCAN0.TMIEC1.UINT8[R_IO_HH])
     1324#define RSCAN0TMIEC2 (RSCAN0.TMIEC2.UINT32)
     1325#define RSCAN0TMIEC2L (RSCAN0.TMIEC2.UINT16[R_IO_L])
     1326#define RSCAN0TMIEC2LL (RSCAN0.TMIEC2.UINT8[R_IO_LL])
     1327#define RSCAN0TMIEC2LH (RSCAN0.TMIEC2.UINT8[R_IO_LH])
     1328#define RSCAN0TMIEC2H (RSCAN0.TMIEC2.UINT16[R_IO_H])
     1329#define RSCAN0TMIEC2HL (RSCAN0.TMIEC2.UINT8[R_IO_HL])
     1330#define RSCAN0TMIEC2HH (RSCAN0.TMIEC2.UINT8[R_IO_HH])
     1331#define RSCAN0TXQCC0 (RSCAN0.TXQCC0.UINT32)
     1332#define RSCAN0TXQCC0L (RSCAN0.TXQCC0.UINT16[R_IO_L])
     1333#define RSCAN0TXQCC0LL (RSCAN0.TXQCC0.UINT8[R_IO_LL])
     1334#define RSCAN0TXQCC0LH (RSCAN0.TXQCC0.UINT8[R_IO_LH])
     1335#define RSCAN0TXQCC0H (RSCAN0.TXQCC0.UINT16[R_IO_H])
     1336#define RSCAN0TXQCC0HL (RSCAN0.TXQCC0.UINT8[R_IO_HL])
     1337#define RSCAN0TXQCC0HH (RSCAN0.TXQCC0.UINT8[R_IO_HH])
     1338#define RSCAN0TXQCC1 (RSCAN0.TXQCC1.UINT32)
     1339#define RSCAN0TXQCC1L (RSCAN0.TXQCC1.UINT16[R_IO_L])
     1340#define RSCAN0TXQCC1LL (RSCAN0.TXQCC1.UINT8[R_IO_LL])
     1341#define RSCAN0TXQCC1LH (RSCAN0.TXQCC1.UINT8[R_IO_LH])
     1342#define RSCAN0TXQCC1H (RSCAN0.TXQCC1.UINT16[R_IO_H])
     1343#define RSCAN0TXQCC1HL (RSCAN0.TXQCC1.UINT8[R_IO_HL])
     1344#define RSCAN0TXQCC1HH (RSCAN0.TXQCC1.UINT8[R_IO_HH])
     1345#define RSCAN0TXQCC2 (RSCAN0.TXQCC2.UINT32)
     1346#define RSCAN0TXQCC2L (RSCAN0.TXQCC2.UINT16[R_IO_L])
     1347#define RSCAN0TXQCC2LL (RSCAN0.TXQCC2.UINT8[R_IO_LL])
     1348#define RSCAN0TXQCC2LH (RSCAN0.TXQCC2.UINT8[R_IO_LH])
     1349#define RSCAN0TXQCC2H (RSCAN0.TXQCC2.UINT16[R_IO_H])
     1350#define RSCAN0TXQCC2HL (RSCAN0.TXQCC2.UINT8[R_IO_HL])
     1351#define RSCAN0TXQCC2HH (RSCAN0.TXQCC2.UINT8[R_IO_HH])
     1352#define RSCAN0TXQCC3 (RSCAN0.TXQCC3.UINT32)
     1353#define RSCAN0TXQCC3L (RSCAN0.TXQCC3.UINT16[R_IO_L])
     1354#define RSCAN0TXQCC3LL (RSCAN0.TXQCC3.UINT8[R_IO_LL])
     1355#define RSCAN0TXQCC3LH (RSCAN0.TXQCC3.UINT8[R_IO_LH])
     1356#define RSCAN0TXQCC3H (RSCAN0.TXQCC3.UINT16[R_IO_H])
     1357#define RSCAN0TXQCC3HL (RSCAN0.TXQCC3.UINT8[R_IO_HL])
     1358#define RSCAN0TXQCC3HH (RSCAN0.TXQCC3.UINT8[R_IO_HH])
     1359#define RSCAN0TXQCC4 (RSCAN0.TXQCC4.UINT32)
     1360#define RSCAN0TXQCC4L (RSCAN0.TXQCC4.UINT16[R_IO_L])
     1361#define RSCAN0TXQCC4LL (RSCAN0.TXQCC4.UINT8[R_IO_LL])
     1362#define RSCAN0TXQCC4LH (RSCAN0.TXQCC4.UINT8[R_IO_LH])
     1363#define RSCAN0TXQCC4H (RSCAN0.TXQCC4.UINT16[R_IO_H])
     1364#define RSCAN0TXQCC4HL (RSCAN0.TXQCC4.UINT8[R_IO_HL])
     1365#define RSCAN0TXQCC4HH (RSCAN0.TXQCC4.UINT8[R_IO_HH])
     1366#define RSCAN0TXQSTS0 (RSCAN0.TXQSTS0.UINT32)
     1367#define RSCAN0TXQSTS0L (RSCAN0.TXQSTS0.UINT16[R_IO_L])
     1368#define RSCAN0TXQSTS0LL (RSCAN0.TXQSTS0.UINT8[R_IO_LL])
     1369#define RSCAN0TXQSTS0LH (RSCAN0.TXQSTS0.UINT8[R_IO_LH])
     1370#define RSCAN0TXQSTS0H (RSCAN0.TXQSTS0.UINT16[R_IO_H])
     1371#define RSCAN0TXQSTS0HL (RSCAN0.TXQSTS0.UINT8[R_IO_HL])
     1372#define RSCAN0TXQSTS0HH (RSCAN0.TXQSTS0.UINT8[R_IO_HH])
     1373#define RSCAN0TXQSTS1 (RSCAN0.TXQSTS1.UINT32)
     1374#define RSCAN0TXQSTS1L (RSCAN0.TXQSTS1.UINT16[R_IO_L])
     1375#define RSCAN0TXQSTS1LL (RSCAN0.TXQSTS1.UINT8[R_IO_LL])
     1376#define RSCAN0TXQSTS1LH (RSCAN0.TXQSTS1.UINT8[R_IO_LH])
     1377#define RSCAN0TXQSTS1H (RSCAN0.TXQSTS1.UINT16[R_IO_H])
     1378#define RSCAN0TXQSTS1HL (RSCAN0.TXQSTS1.UINT8[R_IO_HL])
     1379#define RSCAN0TXQSTS1HH (RSCAN0.TXQSTS1.UINT8[R_IO_HH])
     1380#define RSCAN0TXQSTS2 (RSCAN0.TXQSTS2.UINT32)
     1381#define RSCAN0TXQSTS2L (RSCAN0.TXQSTS2.UINT16[R_IO_L])
     1382#define RSCAN0TXQSTS2LL (RSCAN0.TXQSTS2.UINT8[R_IO_LL])
     1383#define RSCAN0TXQSTS2LH (RSCAN0.TXQSTS2.UINT8[R_IO_LH])
     1384#define RSCAN0TXQSTS2H (RSCAN0.TXQSTS2.UINT16[R_IO_H])
     1385#define RSCAN0TXQSTS2HL (RSCAN0.TXQSTS2.UINT8[R_IO_HL])
     1386#define RSCAN0TXQSTS2HH (RSCAN0.TXQSTS2.UINT8[R_IO_HH])
     1387#define RSCAN0TXQSTS3 (RSCAN0.TXQSTS3.UINT32)
     1388#define RSCAN0TXQSTS3L (RSCAN0.TXQSTS3.UINT16[R_IO_L])
     1389#define RSCAN0TXQSTS3LL (RSCAN0.TXQSTS3.UINT8[R_IO_LL])
     1390#define RSCAN0TXQSTS3LH (RSCAN0.TXQSTS3.UINT8[R_IO_LH])
     1391#define RSCAN0TXQSTS3H (RSCAN0.TXQSTS3.UINT16[R_IO_H])
     1392#define RSCAN0TXQSTS3HL (RSCAN0.TXQSTS3.UINT8[R_IO_HL])
     1393#define RSCAN0TXQSTS3HH (RSCAN0.TXQSTS3.UINT8[R_IO_HH])
     1394#define RSCAN0TXQSTS4 (RSCAN0.TXQSTS4.UINT32)
     1395#define RSCAN0TXQSTS4L (RSCAN0.TXQSTS4.UINT16[R_IO_L])
     1396#define RSCAN0TXQSTS4LL (RSCAN0.TXQSTS4.UINT8[R_IO_LL])
     1397#define RSCAN0TXQSTS4LH (RSCAN0.TXQSTS4.UINT8[R_IO_LH])
     1398#define RSCAN0TXQSTS4H (RSCAN0.TXQSTS4.UINT16[R_IO_H])
     1399#define RSCAN0TXQSTS4HL (RSCAN0.TXQSTS4.UINT8[R_IO_HL])
     1400#define RSCAN0TXQSTS4HH (RSCAN0.TXQSTS4.UINT8[R_IO_HH])
     1401#define RSCAN0TXQPCTR0 (RSCAN0.TXQPCTR0.UINT32)
     1402#define RSCAN0TXQPCTR0L (RSCAN0.TXQPCTR0.UINT16[R_IO_L])
     1403#define RSCAN0TXQPCTR0LL (RSCAN0.TXQPCTR0.UINT8[R_IO_LL])
     1404#define RSCAN0TXQPCTR0LH (RSCAN0.TXQPCTR0.UINT8[R_IO_LH])
     1405#define RSCAN0TXQPCTR0H (RSCAN0.TXQPCTR0.UINT16[R_IO_H])
     1406#define RSCAN0TXQPCTR0HL (RSCAN0.TXQPCTR0.UINT8[R_IO_HL])
     1407#define RSCAN0TXQPCTR0HH (RSCAN0.TXQPCTR0.UINT8[R_IO_HH])
     1408#define RSCAN0TXQPCTR1 (RSCAN0.TXQPCTR1.UINT32)
     1409#define RSCAN0TXQPCTR1L (RSCAN0.TXQPCTR1.UINT16[R_IO_L])
     1410#define RSCAN0TXQPCTR1LL (RSCAN0.TXQPCTR1.UINT8[R_IO_LL])
     1411#define RSCAN0TXQPCTR1LH (RSCAN0.TXQPCTR1.UINT8[R_IO_LH])
     1412#define RSCAN0TXQPCTR1H (RSCAN0.TXQPCTR1.UINT16[R_IO_H])
     1413#define RSCAN0TXQPCTR1HL (RSCAN0.TXQPCTR1.UINT8[R_IO_HL])
     1414#define RSCAN0TXQPCTR1HH (RSCAN0.TXQPCTR1.UINT8[R_IO_HH])
     1415#define RSCAN0TXQPCTR2 (RSCAN0.TXQPCTR2.UINT32)
     1416#define RSCAN0TXQPCTR2L (RSCAN0.TXQPCTR2.UINT16[R_IO_L])
     1417#define RSCAN0TXQPCTR2LL (RSCAN0.TXQPCTR2.UINT8[R_IO_LL])
     1418#define RSCAN0TXQPCTR2LH (RSCAN0.TXQPCTR2.UINT8[R_IO_LH])
     1419#define RSCAN0TXQPCTR2H (RSCAN0.TXQPCTR2.UINT16[R_IO_H])
     1420#define RSCAN0TXQPCTR2HL (RSCAN0.TXQPCTR2.UINT8[R_IO_HL])
     1421#define RSCAN0TXQPCTR2HH (RSCAN0.TXQPCTR2.UINT8[R_IO_HH])
     1422#define RSCAN0TXQPCTR3 (RSCAN0.TXQPCTR3.UINT32)
     1423#define RSCAN0TXQPCTR3L (RSCAN0.TXQPCTR3.UINT16[R_IO_L])
     1424#define RSCAN0TXQPCTR3LL (RSCAN0.TXQPCTR3.UINT8[R_IO_LL])
     1425#define RSCAN0TXQPCTR3LH (RSCAN0.TXQPCTR3.UINT8[R_IO_LH])
     1426#define RSCAN0TXQPCTR3H (RSCAN0.TXQPCTR3.UINT16[R_IO_H])
     1427#define RSCAN0TXQPCTR3HL (RSCAN0.TXQPCTR3.UINT8[R_IO_HL])
     1428#define RSCAN0TXQPCTR3HH (RSCAN0.TXQPCTR3.UINT8[R_IO_HH])
     1429#define RSCAN0TXQPCTR4 (RSCAN0.TXQPCTR4.UINT32)
     1430#define RSCAN0TXQPCTR4L (RSCAN0.TXQPCTR4.UINT16[R_IO_L])
     1431#define RSCAN0TXQPCTR4LL (RSCAN0.TXQPCTR4.UINT8[R_IO_LL])
     1432#define RSCAN0TXQPCTR4LH (RSCAN0.TXQPCTR4.UINT8[R_IO_LH])
     1433#define RSCAN0TXQPCTR4H (RSCAN0.TXQPCTR4.UINT16[R_IO_H])
     1434#define RSCAN0TXQPCTR4HL (RSCAN0.TXQPCTR4.UINT8[R_IO_HL])
     1435#define RSCAN0TXQPCTR4HH (RSCAN0.TXQPCTR4.UINT8[R_IO_HH])
     1436#define RSCAN0THLCC0 (RSCAN0.THLCC0.UINT32)
     1437#define RSCAN0THLCC0L (RSCAN0.THLCC0.UINT16[R_IO_L])
     1438#define RSCAN0THLCC0LL (RSCAN0.THLCC0.UINT8[R_IO_LL])
     1439#define RSCAN0THLCC0LH (RSCAN0.THLCC0.UINT8[R_IO_LH])
     1440#define RSCAN0THLCC0H (RSCAN0.THLCC0.UINT16[R_IO_H])
     1441#define RSCAN0THLCC0HL (RSCAN0.THLCC0.UINT8[R_IO_HL])
     1442#define RSCAN0THLCC0HH (RSCAN0.THLCC0.UINT8[R_IO_HH])
     1443#define RSCAN0THLCC1 (RSCAN0.THLCC1.UINT32)
     1444#define RSCAN0THLCC1L (RSCAN0.THLCC1.UINT16[R_IO_L])
     1445#define RSCAN0THLCC1LL (RSCAN0.THLCC1.UINT8[R_IO_LL])
     1446#define RSCAN0THLCC1LH (RSCAN0.THLCC1.UINT8[R_IO_LH])
     1447#define RSCAN0THLCC1H (RSCAN0.THLCC1.UINT16[R_IO_H])
     1448#define RSCAN0THLCC1HL (RSCAN0.THLCC1.UINT8[R_IO_HL])
     1449#define RSCAN0THLCC1HH (RSCAN0.THLCC1.UINT8[R_IO_HH])
     1450#define RSCAN0THLCC2 (RSCAN0.THLCC2.UINT32)
     1451#define RSCAN0THLCC2L (RSCAN0.THLCC2.UINT16[R_IO_L])
     1452#define RSCAN0THLCC2LL (RSCAN0.THLCC2.UINT8[R_IO_LL])
     1453#define RSCAN0THLCC2LH (RSCAN0.THLCC2.UINT8[R_IO_LH])
     1454#define RSCAN0THLCC2H (RSCAN0.THLCC2.UINT16[R_IO_H])
     1455#define RSCAN0THLCC2HL (RSCAN0.THLCC2.UINT8[R_IO_HL])
     1456#define RSCAN0THLCC2HH (RSCAN0.THLCC2.UINT8[R_IO_HH])
     1457#define RSCAN0THLCC3 (RSCAN0.THLCC3.UINT32)
     1458#define RSCAN0THLCC3L (RSCAN0.THLCC3.UINT16[R_IO_L])
     1459#define RSCAN0THLCC3LL (RSCAN0.THLCC3.UINT8[R_IO_LL])
     1460#define RSCAN0THLCC3LH (RSCAN0.THLCC3.UINT8[R_IO_LH])
     1461#define RSCAN0THLCC3H (RSCAN0.THLCC3.UINT16[R_IO_H])
     1462#define RSCAN0THLCC3HL (RSCAN0.THLCC3.UINT8[R_IO_HL])
     1463#define RSCAN0THLCC3HH (RSCAN0.THLCC3.UINT8[R_IO_HH])
     1464#define RSCAN0THLCC4 (RSCAN0.THLCC4.UINT32)
     1465#define RSCAN0THLCC4L (RSCAN0.THLCC4.UINT16[R_IO_L])
     1466#define RSCAN0THLCC4LL (RSCAN0.THLCC4.UINT8[R_IO_LL])
     1467#define RSCAN0THLCC4LH (RSCAN0.THLCC4.UINT8[R_IO_LH])
     1468#define RSCAN0THLCC4H (RSCAN0.THLCC4.UINT16[R_IO_H])
     1469#define RSCAN0THLCC4HL (RSCAN0.THLCC4.UINT8[R_IO_HL])
     1470#define RSCAN0THLCC4HH (RSCAN0.THLCC4.UINT8[R_IO_HH])
     1471#define RSCAN0THLSTS0 (RSCAN0.THLSTS0.UINT32)
     1472#define RSCAN0THLSTS0L (RSCAN0.THLSTS0.UINT16[R_IO_L])
     1473#define RSCAN0THLSTS0LL (RSCAN0.THLSTS0.UINT8[R_IO_LL])
     1474#define RSCAN0THLSTS0LH (RSCAN0.THLSTS0.UINT8[R_IO_LH])
     1475#define RSCAN0THLSTS0H (RSCAN0.THLSTS0.UINT16[R_IO_H])
     1476#define RSCAN0THLSTS0HL (RSCAN0.THLSTS0.UINT8[R_IO_HL])
     1477#define RSCAN0THLSTS0HH (RSCAN0.THLSTS0.UINT8[R_IO_HH])
     1478#define RSCAN0THLSTS1 (RSCAN0.THLSTS1.UINT32)
     1479#define RSCAN0THLSTS1L (RSCAN0.THLSTS1.UINT16[R_IO_L])
     1480#define RSCAN0THLSTS1LL (RSCAN0.THLSTS1.UINT8[R_IO_LL])
     1481#define RSCAN0THLSTS1LH (RSCAN0.THLSTS1.UINT8[R_IO_LH])
     1482#define RSCAN0THLSTS1H (RSCAN0.THLSTS1.UINT16[R_IO_H])
     1483#define RSCAN0THLSTS1HL (RSCAN0.THLSTS1.UINT8[R_IO_HL])
     1484#define RSCAN0THLSTS1HH (RSCAN0.THLSTS1.UINT8[R_IO_HH])
     1485#define RSCAN0THLSTS2 (RSCAN0.THLSTS2.UINT32)
     1486#define RSCAN0THLSTS2L (RSCAN0.THLSTS2.UINT16[R_IO_L])
     1487#define RSCAN0THLSTS2LL (RSCAN0.THLSTS2.UINT8[R_IO_LL])
     1488#define RSCAN0THLSTS2LH (RSCAN0.THLSTS2.UINT8[R_IO_LH])
     1489#define RSCAN0THLSTS2H (RSCAN0.THLSTS2.UINT16[R_IO_H])
     1490#define RSCAN0THLSTS2HL (RSCAN0.THLSTS2.UINT8[R_IO_HL])
     1491#define RSCAN0THLSTS2HH (RSCAN0.THLSTS2.UINT8[R_IO_HH])
     1492#define RSCAN0THLSTS3 (RSCAN0.THLSTS3.UINT32)
     1493#define RSCAN0THLSTS3L (RSCAN0.THLSTS3.UINT16[R_IO_L])
     1494#define RSCAN0THLSTS3LL (RSCAN0.THLSTS3.UINT8[R_IO_LL])
     1495#define RSCAN0THLSTS3LH (RSCAN0.THLSTS3.UINT8[R_IO_LH])
     1496#define RSCAN0THLSTS3H (RSCAN0.THLSTS3.UINT16[R_IO_H])
     1497#define RSCAN0THLSTS3HL (RSCAN0.THLSTS3.UINT8[R_IO_HL])
     1498#define RSCAN0THLSTS3HH (RSCAN0.THLSTS3.UINT8[R_IO_HH])
     1499#define RSCAN0THLSTS4 (RSCAN0.THLSTS4.UINT32)
     1500#define RSCAN0THLSTS4L (RSCAN0.THLSTS4.UINT16[R_IO_L])
     1501#define RSCAN0THLSTS4LL (RSCAN0.THLSTS4.UINT8[R_IO_LL])
     1502#define RSCAN0THLSTS4LH (RSCAN0.THLSTS4.UINT8[R_IO_LH])
     1503#define RSCAN0THLSTS4H (RSCAN0.THLSTS4.UINT16[R_IO_H])
     1504#define RSCAN0THLSTS4HL (RSCAN0.THLSTS4.UINT8[R_IO_HL])
     1505#define RSCAN0THLSTS4HH (RSCAN0.THLSTS4.UINT8[R_IO_HH])
     1506#define RSCAN0THLPCTR0 (RSCAN0.THLPCTR0.UINT32)
     1507#define RSCAN0THLPCTR0L (RSCAN0.THLPCTR0.UINT16[R_IO_L])
     1508#define RSCAN0THLPCTR0LL (RSCAN0.THLPCTR0.UINT8[R_IO_LL])
     1509#define RSCAN0THLPCTR0LH (RSCAN0.THLPCTR0.UINT8[R_IO_LH])
     1510#define RSCAN0THLPCTR0H (RSCAN0.THLPCTR0.UINT16[R_IO_H])
     1511#define RSCAN0THLPCTR0HL (RSCAN0.THLPCTR0.UINT8[R_IO_HL])
     1512#define RSCAN0THLPCTR0HH (RSCAN0.THLPCTR0.UINT8[R_IO_HH])
     1513#define RSCAN0THLPCTR1 (RSCAN0.THLPCTR1.UINT32)
     1514#define RSCAN0THLPCTR1L (RSCAN0.THLPCTR1.UINT16[R_IO_L])
     1515#define RSCAN0THLPCTR1LL (RSCAN0.THLPCTR1.UINT8[R_IO_LL])
     1516#define RSCAN0THLPCTR1LH (RSCAN0.THLPCTR1.UINT8[R_IO_LH])
     1517#define RSCAN0THLPCTR1H (RSCAN0.THLPCTR1.UINT16[R_IO_H])
     1518#define RSCAN0THLPCTR1HL (RSCAN0.THLPCTR1.UINT8[R_IO_HL])
     1519#define RSCAN0THLPCTR1HH (RSCAN0.THLPCTR1.UINT8[R_IO_HH])
     1520#define RSCAN0THLPCTR2 (RSCAN0.THLPCTR2.UINT32)
     1521#define RSCAN0THLPCTR2L (RSCAN0.THLPCTR2.UINT16[R_IO_L])
     1522#define RSCAN0THLPCTR2LL (RSCAN0.THLPCTR2.UINT8[R_IO_LL])
     1523#define RSCAN0THLPCTR2LH (RSCAN0.THLPCTR2.UINT8[R_IO_LH])
     1524#define RSCAN0THLPCTR2H (RSCAN0.THLPCTR2.UINT16[R_IO_H])
     1525#define RSCAN0THLPCTR2HL (RSCAN0.THLPCTR2.UINT8[R_IO_HL])
     1526#define RSCAN0THLPCTR2HH (RSCAN0.THLPCTR2.UINT8[R_IO_HH])
     1527#define RSCAN0THLPCTR3 (RSCAN0.THLPCTR3.UINT32)
     1528#define RSCAN0THLPCTR3L (RSCAN0.THLPCTR3.UINT16[R_IO_L])
     1529#define RSCAN0THLPCTR3LL (RSCAN0.THLPCTR3.UINT8[R_IO_LL])
     1530#define RSCAN0THLPCTR3LH (RSCAN0.THLPCTR3.UINT8[R_IO_LH])
     1531#define RSCAN0THLPCTR3H (RSCAN0.THLPCTR3.UINT16[R_IO_H])
     1532#define RSCAN0THLPCTR3HL (RSCAN0.THLPCTR3.UINT8[R_IO_HL])
     1533#define RSCAN0THLPCTR3HH (RSCAN0.THLPCTR3.UINT8[R_IO_HH])
     1534#define RSCAN0THLPCTR4 (RSCAN0.THLPCTR4.UINT32)
     1535#define RSCAN0THLPCTR4L (RSCAN0.THLPCTR4.UINT16[R_IO_L])
     1536#define RSCAN0THLPCTR4LL (RSCAN0.THLPCTR4.UINT8[R_IO_LL])
     1537#define RSCAN0THLPCTR4LH (RSCAN0.THLPCTR4.UINT8[R_IO_LH])
     1538#define RSCAN0THLPCTR4H (RSCAN0.THLPCTR4.UINT16[R_IO_H])
     1539#define RSCAN0THLPCTR4HL (RSCAN0.THLPCTR4.UINT8[R_IO_HL])
     1540#define RSCAN0THLPCTR4HH (RSCAN0.THLPCTR4.UINT8[R_IO_HH])
     1541#define RSCAN0GTINTSTS0 (RSCAN0.GTINTSTS0.UINT32)
     1542#define RSCAN0GTINTSTS0L (RSCAN0.GTINTSTS0.UINT16[R_IO_L])
     1543#define RSCAN0GTINTSTS0LL (RSCAN0.GTINTSTS0.UINT8[R_IO_LL])
     1544#define RSCAN0GTINTSTS0LH (RSCAN0.GTINTSTS0.UINT8[R_IO_LH])
     1545#define RSCAN0GTINTSTS0H (RSCAN0.GTINTSTS0.UINT16[R_IO_H])
     1546#define RSCAN0GTINTSTS0HL (RSCAN0.GTINTSTS0.UINT8[R_IO_HL])
     1547#define RSCAN0GTINTSTS0HH (RSCAN0.GTINTSTS0.UINT8[R_IO_HH])
     1548#define RSCAN0GTINTSTS1 (RSCAN0.GTINTSTS1.UINT32)
     1549#define RSCAN0GTINTSTS1L (RSCAN0.GTINTSTS1.UINT16[R_IO_L])
     1550#define RSCAN0GTINTSTS1LL (RSCAN0.GTINTSTS1.UINT8[R_IO_LL])
     1551#define RSCAN0GTINTSTS1LH (RSCAN0.GTINTSTS1.UINT8[R_IO_LH])
     1552#define RSCAN0GTINTSTS1H (RSCAN0.GTINTSTS1.UINT16[R_IO_H])
     1553#define RSCAN0GTINTSTS1HL (RSCAN0.GTINTSTS1.UINT8[R_IO_HL])
     1554#define RSCAN0GTINTSTS1HH (RSCAN0.GTINTSTS1.UINT8[R_IO_HH])
     1555#define RSCAN0GTSTCFG (RSCAN0.GTSTCFG.UINT32)
     1556#define RSCAN0GTSTCFGL (RSCAN0.GTSTCFG.UINT16[R_IO_L])
     1557#define RSCAN0GTSTCFGLL (RSCAN0.GTSTCFG.UINT8[R_IO_LL])
     1558#define RSCAN0GTSTCFGLH (RSCAN0.GTSTCFG.UINT8[R_IO_LH])
     1559#define RSCAN0GTSTCFGH (RSCAN0.GTSTCFG.UINT16[R_IO_H])
     1560#define RSCAN0GTSTCFGHL (RSCAN0.GTSTCFG.UINT8[R_IO_HL])
     1561#define RSCAN0GTSTCFGHH (RSCAN0.GTSTCFG.UINT8[R_IO_HH])
     1562#define RSCAN0GTSTCTR (RSCAN0.GTSTCTR.UINT32)
     1563#define RSCAN0GTSTCTRL (RSCAN0.GTSTCTR.UINT16[R_IO_L])
     1564#define RSCAN0GTSTCTRLL (RSCAN0.GTSTCTR.UINT8[R_IO_LL])
     1565#define RSCAN0GTSTCTRLH (RSCAN0.GTSTCTR.UINT8[R_IO_LH])
     1566#define RSCAN0GTSTCTRH (RSCAN0.GTSTCTR.UINT16[R_IO_H])
     1567#define RSCAN0GTSTCTRHL (RSCAN0.GTSTCTR.UINT8[R_IO_HL])
     1568#define RSCAN0GTSTCTRHH (RSCAN0.GTSTCTR.UINT8[R_IO_HH])
     1569#define RSCAN0GLOCKK (RSCAN0.GLOCKK.UINT32)
     1570#define RSCAN0GLOCKKL (RSCAN0.GLOCKK.UINT16[R_IO_L])
     1571#define RSCAN0GLOCKKH (RSCAN0.GLOCKK.UINT16[R_IO_H])
     1572#define RSCAN0GAFLID0 (RSCAN0.GAFLID0.UINT32)
     1573#define RSCAN0GAFLID0L (RSCAN0.GAFLID0.UINT16[R_IO_L])
     1574#define RSCAN0GAFLID0LL (RSCAN0.GAFLID0.UINT8[R_IO_LL])
     1575#define RSCAN0GAFLID0LH (RSCAN0.GAFLID0.UINT8[R_IO_LH])
     1576#define RSCAN0GAFLID0H (RSCAN0.GAFLID0.UINT16[R_IO_H])
     1577#define RSCAN0GAFLID0HL (RSCAN0.GAFLID0.UINT8[R_IO_HL])
     1578#define RSCAN0GAFLID0HH (RSCAN0.GAFLID0.UINT8[R_IO_HH])
     1579#define RSCAN0GAFLM0 (RSCAN0.GAFLM0.UINT32)
     1580#define RSCAN0GAFLM0L (RSCAN0.GAFLM0.UINT16[R_IO_L])
     1581#define RSCAN0GAFLM0LL (RSCAN0.GAFLM0.UINT8[R_IO_LL])
     1582#define RSCAN0GAFLM0LH (RSCAN0.GAFLM0.UINT8[R_IO_LH])
     1583#define RSCAN0GAFLM0H (RSCAN0.GAFLM0.UINT16[R_IO_H])
     1584#define RSCAN0GAFLM0HL (RSCAN0.GAFLM0.UINT8[R_IO_HL])
     1585#define RSCAN0GAFLM0HH (RSCAN0.GAFLM0.UINT8[R_IO_HH])
     1586#define RSCAN0GAFLP00 (RSCAN0.GAFLP00.UINT32)
     1587#define RSCAN0GAFLP00L (RSCAN0.GAFLP00.UINT16[R_IO_L])
     1588#define RSCAN0GAFLP00LL (RSCAN0.GAFLP00.UINT8[R_IO_LL])
     1589#define RSCAN0GAFLP00LH (RSCAN0.GAFLP00.UINT8[R_IO_LH])
     1590#define RSCAN0GAFLP00H (RSCAN0.GAFLP00.UINT16[R_IO_H])
     1591#define RSCAN0GAFLP00HL (RSCAN0.GAFLP00.UINT8[R_IO_HL])
     1592#define RSCAN0GAFLP00HH (RSCAN0.GAFLP00.UINT8[R_IO_HH])
     1593#define RSCAN0GAFLP10 (RSCAN0.GAFLP10.UINT32)
     1594#define RSCAN0GAFLP10L (RSCAN0.GAFLP10.UINT16[R_IO_L])
     1595#define RSCAN0GAFLP10LL (RSCAN0.GAFLP10.UINT8[R_IO_LL])
     1596#define RSCAN0GAFLP10LH (RSCAN0.GAFLP10.UINT8[R_IO_LH])
     1597#define RSCAN0GAFLP10H (RSCAN0.GAFLP10.UINT16[R_IO_H])
     1598#define RSCAN0GAFLP10HL (RSCAN0.GAFLP10.UINT8[R_IO_HL])
     1599#define RSCAN0GAFLP10HH (RSCAN0.GAFLP10.UINT8[R_IO_HH])
     1600#define RSCAN0GAFLID1 (RSCAN0.GAFLID1.UINT32)
     1601#define RSCAN0GAFLID1L (RSCAN0.GAFLID1.UINT16[R_IO_L])
     1602#define RSCAN0GAFLID1LL (RSCAN0.GAFLID1.UINT8[R_IO_LL])
     1603#define RSCAN0GAFLID1LH (RSCAN0.GAFLID1.UINT8[R_IO_LH])
     1604#define RSCAN0GAFLID1H (RSCAN0.GAFLID1.UINT16[R_IO_H])
     1605#define RSCAN0GAFLID1HL (RSCAN0.GAFLID1.UINT8[R_IO_HL])
     1606#define RSCAN0GAFLID1HH (RSCAN0.GAFLID1.UINT8[R_IO_HH])
     1607#define RSCAN0GAFLM1 (RSCAN0.GAFLM1.UINT32)
     1608#define RSCAN0GAFLM1L (RSCAN0.GAFLM1.UINT16[R_IO_L])
     1609#define RSCAN0GAFLM1LL (RSCAN0.GAFLM1.UINT8[R_IO_LL])
     1610#define RSCAN0GAFLM1LH (RSCAN0.GAFLM1.UINT8[R_IO_LH])
     1611#define RSCAN0GAFLM1H (RSCAN0.GAFLM1.UINT16[R_IO_H])
     1612#define RSCAN0GAFLM1HL (RSCAN0.GAFLM1.UINT8[R_IO_HL])
     1613#define RSCAN0GAFLM1HH (RSCAN0.GAFLM1.UINT8[R_IO_HH])
     1614#define RSCAN0GAFLP01 (RSCAN0.GAFLP01.UINT32)
     1615#define RSCAN0GAFLP01L (RSCAN0.GAFLP01.UINT16[R_IO_L])
     1616#define RSCAN0GAFLP01LL (RSCAN0.GAFLP01.UINT8[R_IO_LL])
     1617#define RSCAN0GAFLP01LH (RSCAN0.GAFLP01.UINT8[R_IO_LH])
     1618#define RSCAN0GAFLP01H (RSCAN0.GAFLP01.UINT16[R_IO_H])
     1619#define RSCAN0GAFLP01HL (RSCAN0.GAFLP01.UINT8[R_IO_HL])
     1620#define RSCAN0GAFLP01HH (RSCAN0.GAFLP01.UINT8[R_IO_HH])
     1621#define RSCAN0GAFLP11 (RSCAN0.GAFLP11.UINT32)
     1622#define RSCAN0GAFLP11L (RSCAN0.GAFLP11.UINT16[R_IO_L])
     1623#define RSCAN0GAFLP11LL (RSCAN0.GAFLP11.UINT8[R_IO_LL])
     1624#define RSCAN0GAFLP11LH (RSCAN0.GAFLP11.UINT8[R_IO_LH])
     1625#define RSCAN0GAFLP11H (RSCAN0.GAFLP11.UINT16[R_IO_H])
     1626#define RSCAN0GAFLP11HL (RSCAN0.GAFLP11.UINT8[R_IO_HL])
     1627#define RSCAN0GAFLP11HH (RSCAN0.GAFLP11.UINT8[R_IO_HH])
     1628#define RSCAN0GAFLID2 (RSCAN0.GAFLID2.UINT32)
     1629#define RSCAN0GAFLID2L (RSCAN0.GAFLID2.UINT16[R_IO_L])
     1630#define RSCAN0GAFLID2LL (RSCAN0.GAFLID2.UINT8[R_IO_LL])
     1631#define RSCAN0GAFLID2LH (RSCAN0.GAFLID2.UINT8[R_IO_LH])
     1632#define RSCAN0GAFLID2H (RSCAN0.GAFLID2.UINT16[R_IO_H])
     1633#define RSCAN0GAFLID2HL (RSCAN0.GAFLID2.UINT8[R_IO_HL])
     1634#define RSCAN0GAFLID2HH (RSCAN0.GAFLID2.UINT8[R_IO_HH])
     1635#define RSCAN0GAFLM2 (RSCAN0.GAFLM2.UINT32)
     1636#define RSCAN0GAFLM2L (RSCAN0.GAFLM2.UINT16[R_IO_L])
     1637#define RSCAN0GAFLM2LL (RSCAN0.GAFLM2.UINT8[R_IO_LL])
     1638#define RSCAN0GAFLM2LH (RSCAN0.GAFLM2.UINT8[R_IO_LH])
     1639#define RSCAN0GAFLM2H (RSCAN0.GAFLM2.UINT16[R_IO_H])
     1640#define RSCAN0GAFLM2HL (RSCAN0.GAFLM2.UINT8[R_IO_HL])
     1641#define RSCAN0GAFLM2HH (RSCAN0.GAFLM2.UINT8[R_IO_HH])
     1642#define RSCAN0GAFLP02 (RSCAN0.GAFLP02.UINT32)
     1643#define RSCAN0GAFLP02L (RSCAN0.GAFLP02.UINT16[R_IO_L])
     1644#define RSCAN0GAFLP02LL (RSCAN0.GAFLP02.UINT8[R_IO_LL])
     1645#define RSCAN0GAFLP02LH (RSCAN0.GAFLP02.UINT8[R_IO_LH])
     1646#define RSCAN0GAFLP02H (RSCAN0.GAFLP02.UINT16[R_IO_H])
     1647#define RSCAN0GAFLP02HL (RSCAN0.GAFLP02.UINT8[R_IO_HL])
     1648#define RSCAN0GAFLP02HH (RSCAN0.GAFLP02.UINT8[R_IO_HH])
     1649#define RSCAN0GAFLP12 (RSCAN0.GAFLP12.UINT32)
     1650#define RSCAN0GAFLP12L (RSCAN0.GAFLP12.UINT16[R_IO_L])
     1651#define RSCAN0GAFLP12LL (RSCAN0.GAFLP12.UINT8[R_IO_LL])
     1652#define RSCAN0GAFLP12LH (RSCAN0.GAFLP12.UINT8[R_IO_LH])
     1653#define RSCAN0GAFLP12H (RSCAN0.GAFLP12.UINT16[R_IO_H])
     1654#define RSCAN0GAFLP12HL (RSCAN0.GAFLP12.UINT8[R_IO_HL])
     1655#define RSCAN0GAFLP12HH (RSCAN0.GAFLP12.UINT8[R_IO_HH])
     1656#define RSCAN0GAFLID3 (RSCAN0.GAFLID3.UINT32)
     1657#define RSCAN0GAFLID3L (RSCAN0.GAFLID3.UINT16[R_IO_L])
     1658#define RSCAN0GAFLID3LL (RSCAN0.GAFLID3.UINT8[R_IO_LL])
     1659#define RSCAN0GAFLID3LH (RSCAN0.GAFLID3.UINT8[R_IO_LH])
     1660#define RSCAN0GAFLID3H (RSCAN0.GAFLID3.UINT16[R_IO_H])
     1661#define RSCAN0GAFLID3HL (RSCAN0.GAFLID3.UINT8[R_IO_HL])
     1662#define RSCAN0GAFLID3HH (RSCAN0.GAFLID3.UINT8[R_IO_HH])
     1663#define RSCAN0GAFLM3 (RSCAN0.GAFLM3.UINT32)
     1664#define RSCAN0GAFLM3L (RSCAN0.GAFLM3.UINT16[R_IO_L])
     1665#define RSCAN0GAFLM3LL (RSCAN0.GAFLM3.UINT8[R_IO_LL])
     1666#define RSCAN0GAFLM3LH (RSCAN0.GAFLM3.UINT8[R_IO_LH])
     1667#define RSCAN0GAFLM3H (RSCAN0.GAFLM3.UINT16[R_IO_H])
     1668#define RSCAN0GAFLM3HL (RSCAN0.GAFLM3.UINT8[R_IO_HL])
     1669#define RSCAN0GAFLM3HH (RSCAN0.GAFLM3.UINT8[R_IO_HH])
     1670#define RSCAN0GAFLP03 (RSCAN0.GAFLP03.UINT32)
     1671#define RSCAN0GAFLP03L (RSCAN0.GAFLP03.UINT16[R_IO_L])
     1672#define RSCAN0GAFLP03LL (RSCAN0.GAFLP03.UINT8[R_IO_LL])
     1673#define RSCAN0GAFLP03LH (RSCAN0.GAFLP03.UINT8[R_IO_LH])
     1674#define RSCAN0GAFLP03H (RSCAN0.GAFLP03.UINT16[R_IO_H])
     1675#define RSCAN0GAFLP03HL (RSCAN0.GAFLP03.UINT8[R_IO_HL])
     1676#define RSCAN0GAFLP03HH (RSCAN0.GAFLP03.UINT8[R_IO_HH])
     1677#define RSCAN0GAFLP13 (RSCAN0.GAFLP13.UINT32)
     1678#define RSCAN0GAFLP13L (RSCAN0.GAFLP13.UINT16[R_IO_L])
     1679#define RSCAN0GAFLP13LL (RSCAN0.GAFLP13.UINT8[R_IO_LL])
     1680#define RSCAN0GAFLP13LH (RSCAN0.GAFLP13.UINT8[R_IO_LH])
     1681#define RSCAN0GAFLP13H (RSCAN0.GAFLP13.UINT16[R_IO_H])
     1682#define RSCAN0GAFLP13HL (RSCAN0.GAFLP13.UINT8[R_IO_HL])
     1683#define RSCAN0GAFLP13HH (RSCAN0.GAFLP13.UINT8[R_IO_HH])
     1684#define RSCAN0GAFLID4 (RSCAN0.GAFLID4.UINT32)
     1685#define RSCAN0GAFLID4L (RSCAN0.GAFLID4.UINT16[R_IO_L])
     1686#define RSCAN0GAFLID4LL (RSCAN0.GAFLID4.UINT8[R_IO_LL])
     1687#define RSCAN0GAFLID4LH (RSCAN0.GAFLID4.UINT8[R_IO_LH])
     1688#define RSCAN0GAFLID4H (RSCAN0.GAFLID4.UINT16[R_IO_H])
     1689#define RSCAN0GAFLID4HL (RSCAN0.GAFLID4.UINT8[R_IO_HL])
     1690#define RSCAN0GAFLID4HH (RSCAN0.GAFLID4.UINT8[R_IO_HH])
     1691#define RSCAN0GAFLM4 (RSCAN0.GAFLM4.UINT32)
     1692#define RSCAN0GAFLM4L (RSCAN0.GAFLM4.UINT16[R_IO_L])
     1693#define RSCAN0GAFLM4LL (RSCAN0.GAFLM4.UINT8[R_IO_LL])
     1694#define RSCAN0GAFLM4LH (RSCAN0.GAFLM4.UINT8[R_IO_LH])
     1695#define RSCAN0GAFLM4H (RSCAN0.GAFLM4.UINT16[R_IO_H])
     1696#define RSCAN0GAFLM4HL (RSCAN0.GAFLM4.UINT8[R_IO_HL])
     1697#define RSCAN0GAFLM4HH (RSCAN0.GAFLM4.UINT8[R_IO_HH])
     1698#define RSCAN0GAFLP04 (RSCAN0.GAFLP04.UINT32)
     1699#define RSCAN0GAFLP04L (RSCAN0.GAFLP04.UINT16[R_IO_L])
     1700#define RSCAN0GAFLP04LL (RSCAN0.GAFLP04.UINT8[R_IO_LL])
     1701#define RSCAN0GAFLP04LH (RSCAN0.GAFLP04.UINT8[R_IO_LH])
     1702#define RSCAN0GAFLP04H (RSCAN0.GAFLP04.UINT16[R_IO_H])
     1703#define RSCAN0GAFLP04HL (RSCAN0.GAFLP04.UINT8[R_IO_HL])
     1704#define RSCAN0GAFLP04HH (RSCAN0.GAFLP04.UINT8[R_IO_HH])
     1705#define RSCAN0GAFLP14 (RSCAN0.GAFLP14.UINT32)
     1706#define RSCAN0GAFLP14L (RSCAN0.GAFLP14.UINT16[R_IO_L])
     1707#define RSCAN0GAFLP14LL (RSCAN0.GAFLP14.UINT8[R_IO_LL])
     1708#define RSCAN0GAFLP14LH (RSCAN0.GAFLP14.UINT8[R_IO_LH])
     1709#define RSCAN0GAFLP14H (RSCAN0.GAFLP14.UINT16[R_IO_H])
     1710#define RSCAN0GAFLP14HL (RSCAN0.GAFLP14.UINT8[R_IO_HL])
     1711#define RSCAN0GAFLP14HH (RSCAN0.GAFLP14.UINT8[R_IO_HH])
     1712#define RSCAN0GAFLID5 (RSCAN0.GAFLID5.UINT32)
     1713#define RSCAN0GAFLID5L (RSCAN0.GAFLID5.UINT16[R_IO_L])
     1714#define RSCAN0GAFLID5LL (RSCAN0.GAFLID5.UINT8[R_IO_LL])
     1715#define RSCAN0GAFLID5LH (RSCAN0.GAFLID5.UINT8[R_IO_LH])
     1716#define RSCAN0GAFLID5H (RSCAN0.GAFLID5.UINT16[R_IO_H])
     1717#define RSCAN0GAFLID5HL (RSCAN0.GAFLID5.UINT8[R_IO_HL])
     1718#define RSCAN0GAFLID5HH (RSCAN0.GAFLID5.UINT8[R_IO_HH])
     1719#define RSCAN0GAFLM5 (RSCAN0.GAFLM5.UINT32)
     1720#define RSCAN0GAFLM5L (RSCAN0.GAFLM5.UINT16[R_IO_L])
     1721#define RSCAN0GAFLM5LL (RSCAN0.GAFLM5.UINT8[R_IO_LL])
     1722#define RSCAN0GAFLM5LH (RSCAN0.GAFLM5.UINT8[R_IO_LH])
     1723#define RSCAN0GAFLM5H (RSCAN0.GAFLM5.UINT16[R_IO_H])
     1724#define RSCAN0GAFLM5HL (RSCAN0.GAFLM5.UINT8[R_IO_HL])
     1725#define RSCAN0GAFLM5HH (RSCAN0.GAFLM5.UINT8[R_IO_HH])
     1726#define RSCAN0GAFLP05 (RSCAN0.GAFLP05.UINT32)
     1727#define RSCAN0GAFLP05L (RSCAN0.GAFLP05.UINT16[R_IO_L])
     1728#define RSCAN0GAFLP05LL (RSCAN0.GAFLP05.UINT8[R_IO_LL])
     1729#define RSCAN0GAFLP05LH (RSCAN0.GAFLP05.UINT8[R_IO_LH])
     1730#define RSCAN0GAFLP05H (RSCAN0.GAFLP05.UINT16[R_IO_H])
     1731#define RSCAN0GAFLP05HL (RSCAN0.GAFLP05.UINT8[R_IO_HL])
     1732#define RSCAN0GAFLP05HH (RSCAN0.GAFLP05.UINT8[R_IO_HH])
     1733#define RSCAN0GAFLP15 (RSCAN0.GAFLP15.UINT32)
     1734#define RSCAN0GAFLP15L (RSCAN0.GAFLP15.UINT16[R_IO_L])
     1735#define RSCAN0GAFLP15LL (RSCAN0.GAFLP15.UINT8[R_IO_LL])
     1736#define RSCAN0GAFLP15LH (RSCAN0.GAFLP15.UINT8[R_IO_LH])
     1737#define RSCAN0GAFLP15H (RSCAN0.GAFLP15.UINT16[R_IO_H])
     1738#define RSCAN0GAFLP15HL (RSCAN0.GAFLP15.UINT8[R_IO_HL])
     1739#define RSCAN0GAFLP15HH (RSCAN0.GAFLP15.UINT8[R_IO_HH])
     1740#define RSCAN0GAFLID6 (RSCAN0.GAFLID6.UINT32)
     1741#define RSCAN0GAFLID6L (RSCAN0.GAFLID6.UINT16[R_IO_L])
     1742#define RSCAN0GAFLID6LL (RSCAN0.GAFLID6.UINT8[R_IO_LL])
     1743#define RSCAN0GAFLID6LH (RSCAN0.GAFLID6.UINT8[R_IO_LH])
     1744#define RSCAN0GAFLID6H (RSCAN0.GAFLID6.UINT16[R_IO_H])
     1745#define RSCAN0GAFLID6HL (RSCAN0.GAFLID6.UINT8[R_IO_HL])
     1746#define RSCAN0GAFLID6HH (RSCAN0.GAFLID6.UINT8[R_IO_HH])
     1747#define RSCAN0GAFLM6 (RSCAN0.GAFLM6.UINT32)
     1748#define RSCAN0GAFLM6L (RSCAN0.GAFLM6.UINT16[R_IO_L])
     1749#define RSCAN0GAFLM6LL (RSCAN0.GAFLM6.UINT8[R_IO_LL])
     1750#define RSCAN0GAFLM6LH (RSCAN0.GAFLM6.UINT8[R_IO_LH])
     1751#define RSCAN0GAFLM6H (RSCAN0.GAFLM6.UINT16[R_IO_H])
     1752#define RSCAN0GAFLM6HL (RSCAN0.GAFLM6.UINT8[R_IO_HL])
     1753#define RSCAN0GAFLM6HH (RSCAN0.GAFLM6.UINT8[R_IO_HH])
     1754#define RSCAN0GAFLP06 (RSCAN0.GAFLP06.UINT32)
     1755#define RSCAN0GAFLP06L (RSCAN0.GAFLP06.UINT16[R_IO_L])
     1756#define RSCAN0GAFLP06LL (RSCAN0.GAFLP06.UINT8[R_IO_LL])
     1757#define RSCAN0GAFLP06LH (RSCAN0.GAFLP06.UINT8[R_IO_LH])
     1758#define RSCAN0GAFLP06H (RSCAN0.GAFLP06.UINT16[R_IO_H])
     1759#define RSCAN0GAFLP06HL (RSCAN0.GAFLP06.UINT8[R_IO_HL])
     1760#define RSCAN0GAFLP06HH (RSCAN0.GAFLP06.UINT8[R_IO_HH])
     1761#define RSCAN0GAFLP16 (RSCAN0.GAFLP16.UINT32)
     1762#define RSCAN0GAFLP16L (RSCAN0.GAFLP16.UINT16[R_IO_L])
     1763#define RSCAN0GAFLP16LL (RSCAN0.GAFLP16.UINT8[R_IO_LL])
     1764#define RSCAN0GAFLP16LH (RSCAN0.GAFLP16.UINT8[R_IO_LH])
     1765#define RSCAN0GAFLP16H (RSCAN0.GAFLP16.UINT16[R_IO_H])
     1766#define RSCAN0GAFLP16HL (RSCAN0.GAFLP16.UINT8[R_IO_HL])
     1767#define RSCAN0GAFLP16HH (RSCAN0.GAFLP16.UINT8[R_IO_HH])
     1768#define RSCAN0GAFLID7 (RSCAN0.GAFLID7.UINT32)
     1769#define RSCAN0GAFLID7L (RSCAN0.GAFLID7.UINT16[R_IO_L])
     1770#define RSCAN0GAFLID7LL (RSCAN0.GAFLID7.UINT8[R_IO_LL])
     1771#define RSCAN0GAFLID7LH (RSCAN0.GAFLID7.UINT8[R_IO_LH])
     1772#define RSCAN0GAFLID7H (RSCAN0.GAFLID7.UINT16[R_IO_H])
     1773#define RSCAN0GAFLID7HL (RSCAN0.GAFLID7.UINT8[R_IO_HL])
     1774#define RSCAN0GAFLID7HH (RSCAN0.GAFLID7.UINT8[R_IO_HH])
     1775#define RSCAN0GAFLM7 (RSCAN0.GAFLM7.UINT32)
     1776#define RSCAN0GAFLM7L (RSCAN0.GAFLM7.UINT16[R_IO_L])
     1777#define RSCAN0GAFLM7LL (RSCAN0.GAFLM7.UINT8[R_IO_LL])
     1778#define RSCAN0GAFLM7LH (RSCAN0.GAFLM7.UINT8[R_IO_LH])
     1779#define RSCAN0GAFLM7H (RSCAN0.GAFLM7.UINT16[R_IO_H])
     1780#define RSCAN0GAFLM7HL (RSCAN0.GAFLM7.UINT8[R_IO_HL])
     1781#define RSCAN0GAFLM7HH (RSCAN0.GAFLM7.UINT8[R_IO_HH])
     1782#define RSCAN0GAFLP07 (RSCAN0.GAFLP07.UINT32)
     1783#define RSCAN0GAFLP07L (RSCAN0.GAFLP07.UINT16[R_IO_L])
     1784#define RSCAN0GAFLP07LL (RSCAN0.GAFLP07.UINT8[R_IO_LL])
     1785#define RSCAN0GAFLP07LH (RSCAN0.GAFLP07.UINT8[R_IO_LH])
     1786#define RSCAN0GAFLP07H (RSCAN0.GAFLP07.UINT16[R_IO_H])
     1787#define RSCAN0GAFLP07HL (RSCAN0.GAFLP07.UINT8[R_IO_HL])
     1788#define RSCAN0GAFLP07HH (RSCAN0.GAFLP07.UINT8[R_IO_HH])
     1789#define RSCAN0GAFLP17 (RSCAN0.GAFLP17.UINT32)
     1790#define RSCAN0GAFLP17L (RSCAN0.GAFLP17.UINT16[R_IO_L])
     1791#define RSCAN0GAFLP17LL (RSCAN0.GAFLP17.UINT8[R_IO_LL])
     1792#define RSCAN0GAFLP17LH (RSCAN0.GAFLP17.UINT8[R_IO_LH])
     1793#define RSCAN0GAFLP17H (RSCAN0.GAFLP17.UINT16[R_IO_H])
     1794#define RSCAN0GAFLP17HL (RSCAN0.GAFLP17.UINT8[R_IO_HL])
     1795#define RSCAN0GAFLP17HH (RSCAN0.GAFLP17.UINT8[R_IO_HH])
     1796#define RSCAN0GAFLID8 (RSCAN0.GAFLID8.UINT32)
     1797#define RSCAN0GAFLID8L (RSCAN0.GAFLID8.UINT16[R_IO_L])
     1798#define RSCAN0GAFLID8LL (RSCAN0.GAFLID8.UINT8[R_IO_LL])
     1799#define RSCAN0GAFLID8LH (RSCAN0.GAFLID8.UINT8[R_IO_LH])
     1800#define RSCAN0GAFLID8H (RSCAN0.GAFLID8.UINT16[R_IO_H])
     1801#define RSCAN0GAFLID8HL (RSCAN0.GAFLID8.UINT8[R_IO_HL])
     1802#define RSCAN0GAFLID8HH (RSCAN0.GAFLID8.UINT8[R_IO_HH])
     1803#define RSCAN0GAFLM8 (RSCAN0.GAFLM8.UINT32)
     1804#define RSCAN0GAFLM8L (RSCAN0.GAFLM8.UINT16[R_IO_L])
     1805#define RSCAN0GAFLM8LL (RSCAN0.GAFLM8.UINT8[R_IO_LL])
     1806#define RSCAN0GAFLM8LH (RSCAN0.GAFLM8.UINT8[R_IO_LH])
     1807#define RSCAN0GAFLM8H (RSCAN0.GAFLM8.UINT16[R_IO_H])
     1808#define RSCAN0GAFLM8HL (RSCAN0.GAFLM8.UINT8[R_IO_HL])
     1809#define RSCAN0GAFLM8HH (RSCAN0.GAFLM8.UINT8[R_IO_HH])
     1810#define RSCAN0GAFLP08 (RSCAN0.GAFLP08.UINT32)
     1811#define RSCAN0GAFLP08L (RSCAN0.GAFLP08.UINT16[R_IO_L])
     1812#define RSCAN0GAFLP08LL (RSCAN0.GAFLP08.UINT8[R_IO_LL])
     1813#define RSCAN0GAFLP08LH (RSCAN0.GAFLP08.UINT8[R_IO_LH])
     1814#define RSCAN0GAFLP08H (RSCAN0.GAFLP08.UINT16[R_IO_H])
     1815#define RSCAN0GAFLP08HL (RSCAN0.GAFLP08.UINT8[R_IO_HL])
     1816#define RSCAN0GAFLP08HH (RSCAN0.GAFLP08.UINT8[R_IO_HH])
     1817#define RSCAN0GAFLP18 (RSCAN0.GAFLP18.UINT32)
     1818#define RSCAN0GAFLP18L (RSCAN0.GAFLP18.UINT16[R_IO_L])
     1819#define RSCAN0GAFLP18LL (RSCAN0.GAFLP18.UINT8[R_IO_LL])
     1820#define RSCAN0GAFLP18LH (RSCAN0.GAFLP18.UINT8[R_IO_LH])
     1821#define RSCAN0GAFLP18H (RSCAN0.GAFLP18.UINT16[R_IO_H])
     1822#define RSCAN0GAFLP18HL (RSCAN0.GAFLP18.UINT8[R_IO_HL])
     1823#define RSCAN0GAFLP18HH (RSCAN0.GAFLP18.UINT8[R_IO_HH])
     1824#define RSCAN0GAFLID9 (RSCAN0.GAFLID9.UINT32)
     1825#define RSCAN0GAFLID9L (RSCAN0.GAFLID9.UINT16[R_IO_L])
     1826#define RSCAN0GAFLID9LL (RSCAN0.GAFLID9.UINT8[R_IO_LL])
     1827#define RSCAN0GAFLID9LH (RSCAN0.GAFLID9.UINT8[R_IO_LH])
     1828#define RSCAN0GAFLID9H (RSCAN0.GAFLID9.UINT16[R_IO_H])
     1829#define RSCAN0GAFLID9HL (RSCAN0.GAFLID9.UINT8[R_IO_HL])
     1830#define RSCAN0GAFLID9HH (RSCAN0.GAFLID9.UINT8[R_IO_HH])
     1831#define RSCAN0GAFLM9 (RSCAN0.GAFLM9.UINT32)
     1832#define RSCAN0GAFLM9L (RSCAN0.GAFLM9.UINT16[R_IO_L])
     1833#define RSCAN0GAFLM9LL (RSCAN0.GAFLM9.UINT8[R_IO_LL])
     1834#define RSCAN0GAFLM9LH (RSCAN0.GAFLM9.UINT8[R_IO_LH])
     1835#define RSCAN0GAFLM9H (RSCAN0.GAFLM9.UINT16[R_IO_H])
     1836#define RSCAN0GAFLM9HL (RSCAN0.GAFLM9.UINT8[R_IO_HL])
     1837#define RSCAN0GAFLM9HH (RSCAN0.GAFLM9.UINT8[R_IO_HH])
     1838#define RSCAN0GAFLP09 (RSCAN0.GAFLP09.UINT32)
     1839#define RSCAN0GAFLP09L (RSCAN0.GAFLP09.UINT16[R_IO_L])
     1840#define RSCAN0GAFLP09LL (RSCAN0.GAFLP09.UINT8[R_IO_LL])
     1841#define RSCAN0GAFLP09LH (RSCAN0.GAFLP09.UINT8[R_IO_LH])
     1842#define RSCAN0GAFLP09H (RSCAN0.GAFLP09.UINT16[R_IO_H])
     1843#define RSCAN0GAFLP09HL (RSCAN0.GAFLP09.UINT8[R_IO_HL])
     1844#define RSCAN0GAFLP09HH (RSCAN0.GAFLP09.UINT8[R_IO_HH])
     1845#define RSCAN0GAFLP19 (RSCAN0.GAFLP19.UINT32)
     1846#define RSCAN0GAFLP19L (RSCAN0.GAFLP19.UINT16[R_IO_L])
     1847#define RSCAN0GAFLP19LL (RSCAN0.GAFLP19.UINT8[R_IO_LL])
     1848#define RSCAN0GAFLP19LH (RSCAN0.GAFLP19.UINT8[R_IO_LH])
     1849#define RSCAN0GAFLP19H (RSCAN0.GAFLP19.UINT16[R_IO_H])
     1850#define RSCAN0GAFLP19HL (RSCAN0.GAFLP19.UINT8[R_IO_HL])
     1851#define RSCAN0GAFLP19HH (RSCAN0.GAFLP19.UINT8[R_IO_HH])
     1852#define RSCAN0GAFLID10 (RSCAN0.GAFLID10.UINT32)
     1853#define RSCAN0GAFLID10L (RSCAN0.GAFLID10.UINT16[R_IO_L])
     1854#define RSCAN0GAFLID10LL (RSCAN0.GAFLID10.UINT8[R_IO_LL])
     1855#define RSCAN0GAFLID10LH (RSCAN0.GAFLID10.UINT8[R_IO_LH])
     1856#define RSCAN0GAFLID10H (RSCAN0.GAFLID10.UINT16[R_IO_H])
     1857#define RSCAN0GAFLID10HL (RSCAN0.GAFLID10.UINT8[R_IO_HL])
     1858#define RSCAN0GAFLID10HH (RSCAN0.GAFLID10.UINT8[R_IO_HH])
     1859#define RSCAN0GAFLM10 (RSCAN0.GAFLM10.UINT32)
     1860#define RSCAN0GAFLM10L (RSCAN0.GAFLM10.UINT16[R_IO_L])
     1861#define RSCAN0GAFLM10LL (RSCAN0.GAFLM10.UINT8[R_IO_LL])
     1862#define RSCAN0GAFLM10LH (RSCAN0.GAFLM10.UINT8[R_IO_LH])
     1863#define RSCAN0GAFLM10H (RSCAN0.GAFLM10.UINT16[R_IO_H])
     1864#define RSCAN0GAFLM10HL (RSCAN0.GAFLM10.UINT8[R_IO_HL])
     1865#define RSCAN0GAFLM10HH (RSCAN0.GAFLM10.UINT8[R_IO_HH])
     1866#define RSCAN0GAFLP010 (RSCAN0.GAFLP010.UINT32)
     1867#define RSCAN0GAFLP010L (RSCAN0.GAFLP010.UINT16[R_IO_L])
     1868#define RSCAN0GAFLP010LL (RSCAN0.GAFLP010.UINT8[R_IO_LL])
     1869#define RSCAN0GAFLP010LH (RSCAN0.GAFLP010.UINT8[R_IO_LH])
     1870#define RSCAN0GAFLP010H (RSCAN0.GAFLP010.UINT16[R_IO_H])
     1871#define RSCAN0GAFLP010HL (RSCAN0.GAFLP010.UINT8[R_IO_HL])
     1872#define RSCAN0GAFLP010HH (RSCAN0.GAFLP010.UINT8[R_IO_HH])
     1873#define RSCAN0GAFLP110 (RSCAN0.GAFLP110.UINT32)
     1874#define RSCAN0GAFLP110L (RSCAN0.GAFLP110.UINT16[R_IO_L])
     1875#define RSCAN0GAFLP110LL (RSCAN0.GAFLP110.UINT8[R_IO_LL])
     1876#define RSCAN0GAFLP110LH (RSCAN0.GAFLP110.UINT8[R_IO_LH])
     1877#define RSCAN0GAFLP110H (RSCAN0.GAFLP110.UINT16[R_IO_H])
     1878#define RSCAN0GAFLP110HL (RSCAN0.GAFLP110.UINT8[R_IO_HL])
     1879#define RSCAN0GAFLP110HH (RSCAN0.GAFLP110.UINT8[R_IO_HH])
     1880#define RSCAN0GAFLID11 (RSCAN0.GAFLID11.UINT32)
     1881#define RSCAN0GAFLID11L (RSCAN0.GAFLID11.UINT16[R_IO_L])
     1882#define RSCAN0GAFLID11LL (RSCAN0.GAFLID11.UINT8[R_IO_LL])
     1883#define RSCAN0GAFLID11LH (RSCAN0.GAFLID11.UINT8[R_IO_LH])
     1884#define RSCAN0GAFLID11H (RSCAN0.GAFLID11.UINT16[R_IO_H])
     1885#define RSCAN0GAFLID11HL (RSCAN0.GAFLID11.UINT8[R_IO_HL])
     1886#define RSCAN0GAFLID11HH (RSCAN0.GAFLID11.UINT8[R_IO_HH])
     1887#define RSCAN0GAFLM11 (RSCAN0.GAFLM11.UINT32)
     1888#define RSCAN0GAFLM11L (RSCAN0.GAFLM11.UINT16[R_IO_L])
     1889#define RSCAN0GAFLM11LL (RSCAN0.GAFLM11.UINT8[R_IO_LL])
     1890#define RSCAN0GAFLM11LH (RSCAN0.GAFLM11.UINT8[R_IO_LH])
     1891#define RSCAN0GAFLM11H (RSCAN0.GAFLM11.UINT16[R_IO_H])
     1892#define RSCAN0GAFLM11HL (RSCAN0.GAFLM11.UINT8[R_IO_HL])
     1893#define RSCAN0GAFLM11HH (RSCAN0.GAFLM11.UINT8[R_IO_HH])
     1894#define RSCAN0GAFLP011 (RSCAN0.GAFLP011.UINT32)
     1895#define RSCAN0GAFLP011L (RSCAN0.GAFLP011.UINT16[R_IO_L])
     1896#define RSCAN0GAFLP011LL (RSCAN0.GAFLP011.UINT8[R_IO_LL])
     1897#define RSCAN0GAFLP011LH (RSCAN0.GAFLP011.UINT8[R_IO_LH])
     1898#define RSCAN0GAFLP011H (RSCAN0.GAFLP011.UINT16[R_IO_H])
     1899#define RSCAN0GAFLP011HL (RSCAN0.GAFLP011.UINT8[R_IO_HL])
     1900#define RSCAN0GAFLP011HH (RSCAN0.GAFLP011.UINT8[R_IO_HH])
     1901#define RSCAN0GAFLP111 (RSCAN0.GAFLP111.UINT32)
     1902#define RSCAN0GAFLP111L (RSCAN0.GAFLP111.UINT16[R_IO_L])
     1903#define RSCAN0GAFLP111LL (RSCAN0.GAFLP111.UINT8[R_IO_LL])
     1904#define RSCAN0GAFLP111LH (RSCAN0.GAFLP111.UINT8[R_IO_LH])
     1905#define RSCAN0GAFLP111H (RSCAN0.GAFLP111.UINT16[R_IO_H])
     1906#define RSCAN0GAFLP111HL (RSCAN0.GAFLP111.UINT8[R_IO_HL])
     1907#define RSCAN0GAFLP111HH (RSCAN0.GAFLP111.UINT8[R_IO_HH])
     1908#define RSCAN0GAFLID12 (RSCAN0.GAFLID12.UINT32)
     1909#define RSCAN0GAFLID12L (RSCAN0.GAFLID12.UINT16[R_IO_L])
     1910#define RSCAN0GAFLID12LL (RSCAN0.GAFLID12.UINT8[R_IO_LL])
     1911#define RSCAN0GAFLID12LH (RSCAN0.GAFLID12.UINT8[R_IO_LH])
     1912#define RSCAN0GAFLID12H (RSCAN0.GAFLID12.UINT16[R_IO_H])
     1913#define RSCAN0GAFLID12HL (RSCAN0.GAFLID12.UINT8[R_IO_HL])
     1914#define RSCAN0GAFLID12HH (RSCAN0.GAFLID12.UINT8[R_IO_HH])
     1915#define RSCAN0GAFLM12 (RSCAN0.GAFLM12.UINT32)
     1916#define RSCAN0GAFLM12L (RSCAN0.GAFLM12.UINT16[R_IO_L])
     1917#define RSCAN0GAFLM12LL (RSCAN0.GAFLM12.UINT8[R_IO_LL])
     1918#define RSCAN0GAFLM12LH (RSCAN0.GAFLM12.UINT8[R_IO_LH])
     1919#define RSCAN0GAFLM12H (RSCAN0.GAFLM12.UINT16[R_IO_H])
     1920#define RSCAN0GAFLM12HL (RSCAN0.GAFLM12.UINT8[R_IO_HL])
     1921#define RSCAN0GAFLM12HH (RSCAN0.GAFLM12.UINT8[R_IO_HH])
     1922#define RSCAN0GAFLP012 (RSCAN0.GAFLP012.UINT32)
     1923#define RSCAN0GAFLP012L (RSCAN0.GAFLP012.UINT16[R_IO_L])
     1924#define RSCAN0GAFLP012LL (RSCAN0.GAFLP012.UINT8[R_IO_LL])
     1925#define RSCAN0GAFLP012LH (RSCAN0.GAFLP012.UINT8[R_IO_LH])
     1926#define RSCAN0GAFLP012H (RSCAN0.GAFLP012.UINT16[R_IO_H])
     1927#define RSCAN0GAFLP012HL (RSCAN0.GAFLP012.UINT8[R_IO_HL])
     1928#define RSCAN0GAFLP012HH (RSCAN0.GAFLP012.UINT8[R_IO_HH])
     1929#define RSCAN0GAFLP112 (RSCAN0.GAFLP112.UINT32)
     1930#define RSCAN0GAFLP112L (RSCAN0.GAFLP112.UINT16[R_IO_L])
     1931#define RSCAN0GAFLP112LL (RSCAN0.GAFLP112.UINT8[R_IO_LL])
     1932#define RSCAN0GAFLP112LH (RSCAN0.GAFLP112.UINT8[R_IO_LH])
     1933#define RSCAN0GAFLP112H (RSCAN0.GAFLP112.UINT16[R_IO_H])
     1934#define RSCAN0GAFLP112HL (RSCAN0.GAFLP112.UINT8[R_IO_HL])
     1935#define RSCAN0GAFLP112HH (RSCAN0.GAFLP112.UINT8[R_IO_HH])
     1936#define RSCAN0GAFLID13 (RSCAN0.GAFLID13.UINT32)
     1937#define RSCAN0GAFLID13L (RSCAN0.GAFLID13.UINT16[R_IO_L])
     1938#define RSCAN0GAFLID13LL (RSCAN0.GAFLID13.UINT8[R_IO_LL])
     1939#define RSCAN0GAFLID13LH (RSCAN0.GAFLID13.UINT8[R_IO_LH])
     1940#define RSCAN0GAFLID13H (RSCAN0.GAFLID13.UINT16[R_IO_H])
     1941#define RSCAN0GAFLID13HL (RSCAN0.GAFLID13.UINT8[R_IO_HL])
     1942#define RSCAN0GAFLID13HH (RSCAN0.GAFLID13.UINT8[R_IO_HH])
     1943#define RSCAN0GAFLM13 (RSCAN0.GAFLM13.UINT32)
     1944#define RSCAN0GAFLM13L (RSCAN0.GAFLM13.UINT16[R_IO_L])
     1945#define RSCAN0GAFLM13LL (RSCAN0.GAFLM13.UINT8[R_IO_LL])
     1946#define RSCAN0GAFLM13LH (RSCAN0.GAFLM13.UINT8[R_IO_LH])
     1947#define RSCAN0GAFLM13H (RSCAN0.GAFLM13.UINT16[R_IO_H])
     1948#define RSCAN0GAFLM13HL (RSCAN0.GAFLM13.UINT8[R_IO_HL])
     1949#define RSCAN0GAFLM13HH (RSCAN0.GAFLM13.UINT8[R_IO_HH])
     1950#define RSCAN0GAFLP013 (RSCAN0.GAFLP013.UINT32)
     1951#define RSCAN0GAFLP013L (RSCAN0.GAFLP013.UINT16[R_IO_L])
     1952#define RSCAN0GAFLP013LL (RSCAN0.GAFLP013.UINT8[R_IO_LL])
     1953#define RSCAN0GAFLP013LH (RSCAN0.GAFLP013.UINT8[R_IO_LH])
     1954#define RSCAN0GAFLP013H (RSCAN0.GAFLP013.UINT16[R_IO_H])
     1955#define RSCAN0GAFLP013HL (RSCAN0.GAFLP013.UINT8[R_IO_HL])
     1956#define RSCAN0GAFLP013HH (RSCAN0.GAFLP013.UINT8[R_IO_HH])
     1957#define RSCAN0GAFLP113 (RSCAN0.GAFLP113.UINT32)
     1958#define RSCAN0GAFLP113L (RSCAN0.GAFLP113.UINT16[R_IO_L])
     1959#define RSCAN0GAFLP113LL (RSCAN0.GAFLP113.UINT8[R_IO_LL])
     1960#define RSCAN0GAFLP113LH (RSCAN0.GAFLP113.UINT8[R_IO_LH])
     1961#define RSCAN0GAFLP113H (RSCAN0.GAFLP113.UINT16[R_IO_H])
     1962#define RSCAN0GAFLP113HL (RSCAN0.GAFLP113.UINT8[R_IO_HL])
     1963#define RSCAN0GAFLP113HH (RSCAN0.GAFLP113.UINT8[R_IO_HH])
     1964#define RSCAN0GAFLID14 (RSCAN0.GAFLID14.UINT32)
     1965#define RSCAN0GAFLID14L (RSCAN0.GAFLID14.UINT16[R_IO_L])
     1966#define RSCAN0GAFLID14LL (RSCAN0.GAFLID14.UINT8[R_IO_LL])
     1967#define RSCAN0GAFLID14LH (RSCAN0.GAFLID14.UINT8[R_IO_LH])
     1968#define RSCAN0GAFLID14H (RSCAN0.GAFLID14.UINT16[R_IO_H])
     1969#define RSCAN0GAFLID14HL (RSCAN0.GAFLID14.UINT8[R_IO_HL])
     1970#define RSCAN0GAFLID14HH (RSCAN0.GAFLID14.UINT8[R_IO_HH])
     1971#define RSCAN0GAFLM14 (RSCAN0.GAFLM14.UINT32)
     1972#define RSCAN0GAFLM14L (RSCAN0.GAFLM14.UINT16[R_IO_L])
     1973#define RSCAN0GAFLM14LL (RSCAN0.GAFLM14.UINT8[R_IO_LL])
     1974#define RSCAN0GAFLM14LH (RSCAN0.GAFLM14.UINT8[R_IO_LH])
     1975#define RSCAN0GAFLM14H (RSCAN0.GAFLM14.UINT16[R_IO_H])
     1976#define RSCAN0GAFLM14HL (RSCAN0.GAFLM14.UINT8[R_IO_HL])
     1977#define RSCAN0GAFLM14HH (RSCAN0.GAFLM14.UINT8[R_IO_HH])
     1978#define RSCAN0GAFLP014 (RSCAN0.GAFLP014.UINT32)
     1979#define RSCAN0GAFLP014L (RSCAN0.GAFLP014.UINT16[R_IO_L])
     1980#define RSCAN0GAFLP014LL (RSCAN0.GAFLP014.UINT8[R_IO_LL])
     1981#define RSCAN0GAFLP014LH (RSCAN0.GAFLP014.UINT8[R_IO_LH])
     1982#define RSCAN0GAFLP014H (RSCAN0.GAFLP014.UINT16[R_IO_H])
     1983#define RSCAN0GAFLP014HL (RSCAN0.GAFLP014.UINT8[R_IO_HL])
     1984#define RSCAN0GAFLP014HH (RSCAN0.GAFLP014.UINT8[R_IO_HH])
     1985#define RSCAN0GAFLP114 (RSCAN0.GAFLP114.UINT32)
     1986#define RSCAN0GAFLP114L (RSCAN0.GAFLP114.UINT16[R_IO_L])
     1987#define RSCAN0GAFLP114LL (RSCAN0.GAFLP114.UINT8[R_IO_LL])
     1988#define RSCAN0GAFLP114LH (RSCAN0.GAFLP114.UINT8[R_IO_LH])
     1989#define RSCAN0GAFLP114H (RSCAN0.GAFLP114.UINT16[R_IO_H])
     1990#define RSCAN0GAFLP114HL (RSCAN0.GAFLP114.UINT8[R_IO_HL])
     1991#define RSCAN0GAFLP114HH (RSCAN0.GAFLP114.UINT8[R_IO_HH])
     1992#define RSCAN0GAFLID15 (RSCAN0.GAFLID15.UINT32)
     1993#define RSCAN0GAFLID15L (RSCAN0.GAFLID15.UINT16[R_IO_L])
     1994#define RSCAN0GAFLID15LL (RSCAN0.GAFLID15.UINT8[R_IO_LL])
     1995#define RSCAN0GAFLID15LH (RSCAN0.GAFLID15.UINT8[R_IO_LH])
     1996#define RSCAN0GAFLID15H (RSCAN0.GAFLID15.UINT16[R_IO_H])
     1997#define RSCAN0GAFLID15HL (RSCAN0.GAFLID15.UINT8[R_IO_HL])
     1998#define RSCAN0GAFLID15HH (RSCAN0.GAFLID15.UINT8[R_IO_HH])
     1999#define RSCAN0GAFLM15 (RSCAN0.GAFLM15.UINT32)
     2000#define RSCAN0GAFLM15L (RSCAN0.GAFLM15.UINT16[R_IO_L])
     2001#define RSCAN0GAFLM15LL (RSCAN0.GAFLM15.UINT8[R_IO_LL])
     2002#define RSCAN0GAFLM15LH (RSCAN0.GAFLM15.UINT8[R_IO_LH])
     2003#define RSCAN0GAFLM15H (RSCAN0.GAFLM15.UINT16[R_IO_H])
     2004#define RSCAN0GAFLM15HL (RSCAN0.GAFLM15.UINT8[R_IO_HL])
     2005#define RSCAN0GAFLM15HH (RSCAN0.GAFLM15.UINT8[R_IO_HH])
     2006#define RSCAN0GAFLP015 (RSCAN0.GAFLP015.UINT32)
     2007#define RSCAN0GAFLP015L (RSCAN0.GAFLP015.UINT16[R_IO_L])
     2008#define RSCAN0GAFLP015LL (RSCAN0.GAFLP015.UINT8[R_IO_LL])
     2009#define RSCAN0GAFLP015LH (RSCAN0.GAFLP015.UINT8[R_IO_LH])
     2010#define RSCAN0GAFLP015H (RSCAN0.GAFLP015.UINT16[R_IO_H])
     2011#define RSCAN0GAFLP015HL (RSCAN0.GAFLP015.UINT8[R_IO_HL])
     2012#define RSCAN0GAFLP015HH (RSCAN0.GAFLP015.UINT8[R_IO_HH])
     2013#define RSCAN0GAFLP115 (RSCAN0.GAFLP115.UINT32)
     2014#define RSCAN0GAFLP115L (RSCAN0.GAFLP115.UINT16[R_IO_L])
     2015#define RSCAN0GAFLP115LL (RSCAN0.GAFLP115.UINT8[R_IO_LL])
     2016#define RSCAN0GAFLP115LH (RSCAN0.GAFLP115.UINT8[R_IO_LH])
     2017#define RSCAN0GAFLP115H (RSCAN0.GAFLP115.UINT16[R_IO_H])
     2018#define RSCAN0GAFLP115HL (RSCAN0.GAFLP115.UINT8[R_IO_HL])
     2019#define RSCAN0GAFLP115HH (RSCAN0.GAFLP115.UINT8[R_IO_HH])
     2020#define RSCAN0RMID0 (RSCAN0.RMID0.UINT32)
     2021#define RSCAN0RMID0L (RSCAN0.RMID0.UINT16[R_IO_L])
     2022#define RSCAN0RMID0LL (RSCAN0.RMID0.UINT8[R_IO_LL])
     2023#define RSCAN0RMID0LH (RSCAN0.RMID0.UINT8[R_IO_LH])
     2024#define RSCAN0RMID0H (RSCAN0.RMID0.UINT16[R_IO_H])
     2025#define RSCAN0RMID0HL (RSCAN0.RMID0.UINT8[R_IO_HL])
     2026#define RSCAN0RMID0HH (RSCAN0.RMID0.UINT8[R_IO_HH])
     2027#define RSCAN0RMPTR0 (RSCAN0.RMPTR0.UINT32)
     2028#define RSCAN0RMPTR0L (RSCAN0.RMPTR0.UINT16[R_IO_L])
     2029#define RSCAN0RMPTR0LL (RSCAN0.RMPTR0.UINT8[R_IO_LL])
     2030#define RSCAN0RMPTR0LH (RSCAN0.RMPTR0.UINT8[R_IO_LH])
     2031#define RSCAN0RMPTR0H (RSCAN0.RMPTR0.UINT16[R_IO_H])
     2032#define RSCAN0RMPTR0HL (RSCAN0.RMPTR0.UINT8[R_IO_HL])
     2033#define RSCAN0RMPTR0HH (RSCAN0.RMPTR0.UINT8[R_IO_HH])
     2034#define RSCAN0RMDF00 (RSCAN0.RMDF00.UINT32)
     2035#define RSCAN0RMDF00L (RSCAN0.RMDF00.UINT16[R_IO_L])
     2036#define RSCAN0RMDF00LL (RSCAN0.RMDF00.UINT8[R_IO_LL])
     2037#define RSCAN0RMDF00LH (RSCAN0.RMDF00.UINT8[R_IO_LH])
     2038#define RSCAN0RMDF00H (RSCAN0.RMDF00.UINT16[R_IO_H])
     2039#define RSCAN0RMDF00HL (RSCAN0.RMDF00.UINT8[R_IO_HL])
     2040#define RSCAN0RMDF00HH (RSCAN0.RMDF00.UINT8[R_IO_HH])
     2041#define RSCAN0RMDF10 (RSCAN0.RMDF10.UINT32)
     2042#define RSCAN0RMDF10L (RSCAN0.RMDF10.UINT16[R_IO_L])
     2043#define RSCAN0RMDF10LL (RSCAN0.RMDF10.UINT8[R_IO_LL])
     2044#define RSCAN0RMDF10LH (RSCAN0.RMDF10.UINT8[R_IO_LH])
     2045#define RSCAN0RMDF10H (RSCAN0.RMDF10.UINT16[R_IO_H])
     2046#define RSCAN0RMDF10HL (RSCAN0.RMDF10.UINT8[R_IO_HL])
     2047#define RSCAN0RMDF10HH (RSCAN0.RMDF10.UINT8[R_IO_HH])
     2048#define RSCAN0RMID1 (RSCAN0.RMID1.UINT32)
     2049#define RSCAN0RMID1L (RSCAN0.RMID1.UINT16[R_IO_L])
     2050#define RSCAN0RMID1LL (RSCAN0.RMID1.UINT8[R_IO_LL])
     2051#define RSCAN0RMID1LH (RSCAN0.RMID1.UINT8[R_IO_LH])
     2052#define RSCAN0RMID1H (RSCAN0.RMID1.UINT16[R_IO_H])
     2053#define RSCAN0RMID1HL (RSCAN0.RMID1.UINT8[R_IO_HL])
     2054#define RSCAN0RMID1HH (RSCAN0.RMID1.UINT8[R_IO_HH])
     2055#define RSCAN0RMPTR1 (RSCAN0.RMPTR1.UINT32)
     2056#define RSCAN0RMPTR1L (RSCAN0.RMPTR1.UINT16[R_IO_L])
     2057#define RSCAN0RMPTR1LL (RSCAN0.RMPTR1.UINT8[R_IO_LL])
     2058#define RSCAN0RMPTR1LH (RSCAN0.RMPTR1.UINT8[R_IO_LH])
     2059#define RSCAN0RMPTR1H (RSCAN0.RMPTR1.UINT16[R_IO_H])
     2060#define RSCAN0RMPTR1HL (RSCAN0.RMPTR1.UINT8[R_IO_HL])
     2061#define RSCAN0RMPTR1HH (RSCAN0.RMPTR1.UINT8[R_IO_HH])
     2062#define RSCAN0RMDF01 (RSCAN0.RMDF01.UINT32)
     2063#define RSCAN0RMDF01L (RSCAN0.RMDF01.UINT16[R_IO_L])
     2064#define RSCAN0RMDF01LL (RSCAN0.RMDF01.UINT8[R_IO_LL])
     2065#define RSCAN0RMDF01LH (RSCAN0.RMDF01.UINT8[R_IO_LH])
     2066#define RSCAN0RMDF01H (RSCAN0.RMDF01.UINT16[R_IO_H])
     2067#define RSCAN0RMDF01HL (RSCAN0.RMDF01.UINT8[R_IO_HL])
     2068#define RSCAN0RMDF01HH (RSCAN0.RMDF01.UINT8[R_IO_HH])
     2069#define RSCAN0RMDF11 (RSCAN0.RMDF11.UINT32)
     2070#define RSCAN0RMDF11L (RSCAN0.RMDF11.UINT16[R_IO_L])
     2071#define RSCAN0RMDF11LL (RSCAN0.RMDF11.UINT8[R_IO_LL])
     2072#define RSCAN0RMDF11LH (RSCAN0.RMDF11.UINT8[R_IO_LH])
     2073#define RSCAN0RMDF11H (RSCAN0.RMDF11.UINT16[R_IO_H])
     2074#define RSCAN0RMDF11HL (RSCAN0.RMDF11.UINT8[R_IO_HL])
     2075#define RSCAN0RMDF11HH (RSCAN0.RMDF11.UINT8[R_IO_HH])
     2076#define RSCAN0RMID2 (RSCAN0.RMID2.UINT32)
     2077#define RSCAN0RMID2L (RSCAN0.RMID2.UINT16[R_IO_L])
     2078#define RSCAN0RMID2LL (RSCAN0.RMID2.UINT8[R_IO_LL])
     2079#define RSCAN0RMID2LH (RSCAN0.RMID2.UINT8[R_IO_LH])
     2080#define RSCAN0RMID2H (RSCAN0.RMID2.UINT16[R_IO_H])
     2081#define RSCAN0RMID2HL (RSCAN0.RMID2.UINT8[R_IO_HL])
     2082#define RSCAN0RMID2HH (RSCAN0.RMID2.UINT8[R_IO_HH])
     2083#define RSCAN0RMPTR2 (RSCAN0.RMPTR2.UINT32)
     2084#define RSCAN0RMPTR2L (RSCAN0.RMPTR2.UINT16[R_IO_L])
     2085#define RSCAN0RMPTR2LL (RSCAN0.RMPTR2.UINT8[R_IO_LL])
     2086#define RSCAN0RMPTR2LH (RSCAN0.RMPTR2.UINT8[R_IO_LH])
     2087#define RSCAN0RMPTR2H (RSCAN0.RMPTR2.UINT16[R_IO_H])
     2088#define RSCAN0RMPTR2HL (RSCAN0.RMPTR2.UINT8[R_IO_HL])
     2089#define RSCAN0RMPTR2HH (RSCAN0.RMPTR2.UINT8[R_IO_HH])
     2090#define RSCAN0RMDF02 (RSCAN0.RMDF02.UINT32)
     2091#define RSCAN0RMDF02L (RSCAN0.RMDF02.UINT16[R_IO_L])
     2092#define RSCAN0RMDF02LL (RSCAN0.RMDF02.UINT8[R_IO_LL])
     2093#define RSCAN0RMDF02LH (RSCAN0.RMDF02.UINT8[R_IO_LH])
     2094#define RSCAN0RMDF02H (RSCAN0.RMDF02.UINT16[R_IO_H])
     2095#define RSCAN0RMDF02HL (RSCAN0.RMDF02.UINT8[R_IO_HL])
     2096#define RSCAN0RMDF02HH (RSCAN0.RMDF02.UINT8[R_IO_HH])
     2097#define RSCAN0RMDF12 (RSCAN0.RMDF12.UINT32)
     2098#define RSCAN0RMDF12L (RSCAN0.RMDF12.UINT16[R_IO_L])
     2099#define RSCAN0RMDF12LL (RSCAN0.RMDF12.UINT8[R_IO_LL])
     2100#define RSCAN0RMDF12LH (RSCAN0.RMDF12.UINT8[R_IO_LH])
     2101#define RSCAN0RMDF12H (RSCAN0.RMDF12.UINT16[R_IO_H])
     2102#define RSCAN0RMDF12HL (RSCAN0.RMDF12.UINT8[R_IO_HL])
     2103#define RSCAN0RMDF12HH (RSCAN0.RMDF12.UINT8[R_IO_HH])
     2104#define RSCAN0RMID3 (RSCAN0.RMID3.UINT32)
     2105#define RSCAN0RMID3L (RSCAN0.RMID3.UINT16[R_IO_L])
     2106#define RSCAN0RMID3LL (RSCAN0.RMID3.UINT8[R_IO_LL])
     2107#define RSCAN0RMID3LH (RSCAN0.RMID3.UINT8[R_IO_LH])
     2108#define RSCAN0RMID3H (RSCAN0.RMID3.UINT16[R_IO_H])
     2109#define RSCAN0RMID3HL (RSCAN0.RMID3.UINT8[R_IO_HL])
     2110#define RSCAN0RMID3HH (RSCAN0.RMID3.UINT8[R_IO_HH])
     2111#define RSCAN0RMPTR3 (RSCAN0.RMPTR3.UINT32)
     2112#define RSCAN0RMPTR3L (RSCAN0.RMPTR3.UINT16[R_IO_L])
     2113#define RSCAN0RMPTR3LL (RSCAN0.RMPTR3.UINT8[R_IO_LL])
     2114#define RSCAN0RMPTR3LH (RSCAN0.RMPTR3.UINT8[R_IO_LH])
     2115#define RSCAN0RMPTR3H (RSCAN0.RMPTR3.UINT16[R_IO_H])
     2116#define RSCAN0RMPTR3HL (RSCAN0.RMPTR3.UINT8[R_IO_HL])
     2117#define RSCAN0RMPTR3HH (RSCAN0.RMPTR3.UINT8[R_IO_HH])
     2118#define RSCAN0RMDF03 (RSCAN0.RMDF03.UINT32)
     2119#define RSCAN0RMDF03L (RSCAN0.RMDF03.UINT16[R_IO_L])
     2120#define RSCAN0RMDF03LL (RSCAN0.RMDF03.UINT8[R_IO_LL])
     2121#define RSCAN0RMDF03LH (RSCAN0.RMDF03.UINT8[R_IO_LH])
     2122#define RSCAN0RMDF03H (RSCAN0.RMDF03.UINT16[R_IO_H])
     2123#define RSCAN0RMDF03HL (RSCAN0.RMDF03.UINT8[R_IO_HL])
     2124#define RSCAN0RMDF03HH (RSCAN0.RMDF03.UINT8[R_IO_HH])
     2125#define RSCAN0RMDF13 (RSCAN0.RMDF13.UINT32)
     2126#define RSCAN0RMDF13L (RSCAN0.RMDF13.UINT16[R_IO_L])
     2127#define RSCAN0RMDF13LL (RSCAN0.RMDF13.UINT8[R_IO_LL])
     2128#define RSCAN0RMDF13LH (RSCAN0.RMDF13.UINT8[R_IO_LH])
     2129#define RSCAN0RMDF13H (RSCAN0.RMDF13.UINT16[R_IO_H])
     2130#define RSCAN0RMDF13HL (RSCAN0.RMDF13.UINT8[R_IO_HL])
     2131#define RSCAN0RMDF13HH (RSCAN0.RMDF13.UINT8[R_IO_HH])
     2132#define RSCAN0RMID4 (RSCAN0.RMID4.UINT32)
     2133#define RSCAN0RMID4L (RSCAN0.RMID4.UINT16[R_IO_L])
     2134#define RSCAN0RMID4LL (RSCAN0.RMID4.UINT8[R_IO_LL])
     2135#define RSCAN0RMID4LH (RSCAN0.RMID4.UINT8[R_IO_LH])
     2136#define RSCAN0RMID4H (RSCAN0.RMID4.UINT16[R_IO_H])
     2137#define RSCAN0RMID4HL (RSCAN0.RMID4.UINT8[R_IO_HL])
     2138#define RSCAN0RMID4HH (RSCAN0.RMID4.UINT8[R_IO_HH])
     2139#define RSCAN0RMPTR4 (RSCAN0.RMPTR4.UINT32)
     2140#define RSCAN0RMPTR4L (RSCAN0.RMPTR4.UINT16[R_IO_L])
     2141#define RSCAN0RMPTR4LL (RSCAN0.RMPTR4.UINT8[R_IO_LL])
     2142#define RSCAN0RMPTR4LH (RSCAN0.RMPTR4.UINT8[R_IO_LH])
     2143#define RSCAN0RMPTR4H (RSCAN0.RMPTR4.UINT16[R_IO_H])
     2144#define RSCAN0RMPTR4HL (RSCAN0.RMPTR4.UINT8[R_IO_HL])
     2145#define RSCAN0RMPTR4HH (RSCAN0.RMPTR4.UINT8[R_IO_HH])
     2146#define RSCAN0RMDF04 (RSCAN0.RMDF04.UINT32)
     2147#define RSCAN0RMDF04L (RSCAN0.RMDF04.UINT16[R_IO_L])
     2148#define RSCAN0RMDF04LL (RSCAN0.RMDF04.UINT8[R_IO_LL])
     2149#define RSCAN0RMDF04LH (RSCAN0.RMDF04.UINT8[R_IO_LH])
     2150#define RSCAN0RMDF04H (RSCAN0.RMDF04.UINT16[R_IO_H])
     2151#define RSCAN0RMDF04HL (RSCAN0.RMDF04.UINT8[R_IO_HL])
     2152#define RSCAN0RMDF04HH (RSCAN0.RMDF04.UINT8[R_IO_HH])
     2153#define RSCAN0RMDF14 (RSCAN0.RMDF14.UINT32)
     2154#define RSCAN0RMDF14L (RSCAN0.RMDF14.UINT16[R_IO_L])
     2155#define RSCAN0RMDF14LL (RSCAN0.RMDF14.UINT8[R_IO_LL])
     2156#define RSCAN0RMDF14LH (RSCAN0.RMDF14.UINT8[R_IO_LH])
     2157#define RSCAN0RMDF14H (RSCAN0.RMDF14.UINT16[R_IO_H])
     2158#define RSCAN0RMDF14HL (RSCAN0.RMDF14.UINT8[R_IO_HL])
     2159#define RSCAN0RMDF14HH (RSCAN0.RMDF14.UINT8[R_IO_HH])
     2160#define RSCAN0RMID5 (RSCAN0.RMID5.UINT32)
     2161#define RSCAN0RMID5L (RSCAN0.RMID5.UINT16[R_IO_L])
     2162#define RSCAN0RMID5LL (RSCAN0.RMID5.UINT8[R_IO_LL])
     2163#define RSCAN0RMID5LH (RSCAN0.RMID5.UINT8[R_IO_LH])
     2164#define RSCAN0RMID5H (RSCAN0.RMID5.UINT16[R_IO_H])
     2165#define RSCAN0RMID5HL (RSCAN0.RMID5.UINT8[R_IO_HL])
     2166#define RSCAN0RMID5HH (RSCAN0.RMID5.UINT8[R_IO_HH])
     2167#define RSCAN0RMPTR5 (RSCAN0.RMPTR5.UINT32)
     2168#define RSCAN0RMPTR5L (RSCAN0.RMPTR5.UINT16[R_IO_L])
     2169#define RSCAN0RMPTR5LL (RSCAN0.RMPTR5.UINT8[R_IO_LL])
     2170#define RSCAN0RMPTR5LH (RSCAN0.RMPTR5.UINT8[R_IO_LH])
     2171#define RSCAN0RMPTR5H (RSCAN0.RMPTR5.UINT16[R_IO_H])
     2172#define RSCAN0RMPTR5HL (RSCAN0.RMPTR5.UINT8[R_IO_HL])
     2173#define RSCAN0RMPTR5HH (RSCAN0.RMPTR5.UINT8[R_IO_HH])
     2174#define RSCAN0RMDF05 (RSCAN0.RMDF05.UINT32)
     2175#define RSCAN0RMDF05L (RSCAN0.RMDF05.UINT16[R_IO_L])
     2176#define RSCAN0RMDF05LL (RSCAN0.RMDF05.UINT8[R_IO_LL])
     2177#define RSCAN0RMDF05LH (RSCAN0.RMDF05.UINT8[R_IO_LH])
     2178#define RSCAN0RMDF05H (RSCAN0.RMDF05.UINT16[R_IO_H])
     2179#define RSCAN0RMDF05HL (RSCAN0.RMDF05.UINT8[R_IO_HL])
     2180#define RSCAN0RMDF05HH (RSCAN0.RMDF05.UINT8[R_IO_HH])
     2181#define RSCAN0RMDF15 (RSCAN0.RMDF15.UINT32)
     2182#define RSCAN0RMDF15L (RSCAN0.RMDF15.UINT16[R_IO_L])
     2183#define RSCAN0RMDF15LL (RSCAN0.RMDF15.UINT8[R_IO_LL])
     2184#define RSCAN0RMDF15LH (RSCAN0.RMDF15.UINT8[R_IO_LH])
     2185#define RSCAN0RMDF15H (RSCAN0.RMDF15.UINT16[R_IO_H])
     2186#define RSCAN0RMDF15HL (RSCAN0.RMDF15.UINT8[R_IO_HL])
     2187#define RSCAN0RMDF15HH (RSCAN0.RMDF15.UINT8[R_IO_HH])
     2188#define RSCAN0RMID6 (RSCAN0.RMID6.UINT32)
     2189#define RSCAN0RMID6L (RSCAN0.RMID6.UINT16[R_IO_L])
     2190#define RSCAN0RMID6LL (RSCAN0.RMID6.UINT8[R_IO_LL])
     2191#define RSCAN0RMID6LH (RSCAN0.RMID6.UINT8[R_IO_LH])
     2192#define RSCAN0RMID6H (RSCAN0.RMID6.UINT16[R_IO_H])
     2193#define RSCAN0RMID6HL (RSCAN0.RMID6.UINT8[R_IO_HL])
     2194#define RSCAN0RMID6HH (RSCAN0.RMID6.UINT8[R_IO_HH])
     2195#define RSCAN0RMPTR6 (RSCAN0.RMPTR6.UINT32)
     2196#define RSCAN0RMPTR6L (RSCAN0.RMPTR6.UINT16[R_IO_L])
     2197#define RSCAN0RMPTR6LL (RSCAN0.RMPTR6.UINT8[R_IO_LL])
     2198#define RSCAN0RMPTR6LH (RSCAN0.RMPTR6.UINT8[R_IO_LH])
     2199#define RSCAN0RMPTR6H (RSCAN0.RMPTR6.UINT16[R_IO_H])
     2200#define RSCAN0RMPTR6HL (RSCAN0.RMPTR6.UINT8[R_IO_HL])
     2201#define RSCAN0RMPTR6HH (RSCAN0.RMPTR6.UINT8[R_IO_HH])
     2202#define RSCAN0RMDF06 (RSCAN0.RMDF06.UINT32)
     2203#define RSCAN0RMDF06L (RSCAN0.RMDF06.UINT16[R_IO_L])
     2204#define RSCAN0RMDF06LL (RSCAN0.RMDF06.UINT8[R_IO_LL])
     2205#define RSCAN0RMDF06LH (RSCAN0.RMDF06.UINT8[R_IO_LH])
     2206#define RSCAN0RMDF06H (RSCAN0.RMDF06.UINT16[R_IO_H])
     2207#define RSCAN0RMDF06HL (RSCAN0.RMDF06.UINT8[R_IO_HL])
     2208#define RSCAN0RMDF06HH (RSCAN0.RMDF06.UINT8[R_IO_HH])
     2209#define RSCAN0RMDF16 (RSCAN0.RMDF16.UINT32)
     2210#define RSCAN0RMDF16L (RSCAN0.RMDF16.UINT16[R_IO_L])
     2211#define RSCAN0RMDF16LL (RSCAN0.RMDF16.UINT8[R_IO_LL])
     2212#define RSCAN0RMDF16LH (RSCAN0.RMDF16.UINT8[R_IO_LH])
     2213#define RSCAN0RMDF16H (RSCAN0.RMDF16.UINT16[R_IO_H])
     2214#define RSCAN0RMDF16HL (RSCAN0.RMDF16.UINT8[R_IO_HL])
     2215#define RSCAN0RMDF16HH (RSCAN0.RMDF16.UINT8[R_IO_HH])
     2216#define RSCAN0RMID7 (RSCAN0.RMID7.UINT32)
     2217#define RSCAN0RMID7L (RSCAN0.RMID7.UINT16[R_IO_L])
     2218#define RSCAN0RMID7LL (RSCAN0.RMID7.UINT8[R_IO_LL])
     2219#define RSCAN0RMID7LH (RSCAN0.RMID7.UINT8[R_IO_LH])
     2220#define RSCAN0RMID7H (RSCAN0.RMID7.UINT16[R_IO_H])
     2221#define RSCAN0RMID7HL (RSCAN0.RMID7.UINT8[R_IO_HL])
     2222#define RSCAN0RMID7HH (RSCAN0.RMID7.UINT8[R_IO_HH])
     2223#define RSCAN0RMPTR7 (RSCAN0.RMPTR7.UINT32)
     2224#define RSCAN0RMPTR7L (RSCAN0.RMPTR7.UINT16[R_IO_L])
     2225#define RSCAN0RMPTR7LL (RSCAN0.RMPTR7.UINT8[R_IO_LL])
     2226#define RSCAN0RMPTR7LH (RSCAN0.RMPTR7.UINT8[R_IO_LH])
     2227#define RSCAN0RMPTR7H (RSCAN0.RMPTR7.UINT16[R_IO_H])
     2228#define RSCAN0RMPTR7HL (RSCAN0.RMPTR7.UINT8[R_IO_HL])
     2229#define RSCAN0RMPTR7HH (RSCAN0.RMPTR7.UINT8[R_IO_HH])
     2230#define RSCAN0RMDF07 (RSCAN0.RMDF07.UINT32)
     2231#define RSCAN0RMDF07L (RSCAN0.RMDF07.UINT16[R_IO_L])
     2232#define RSCAN0RMDF07LL (RSCAN0.RMDF07.UINT8[R_IO_LL])
     2233#define RSCAN0RMDF07LH (RSCAN0.RMDF07.UINT8[R_IO_LH])
     2234#define RSCAN0RMDF07H (RSCAN0.RMDF07.UINT16[R_IO_H])
     2235#define RSCAN0RMDF07HL (RSCAN0.RMDF07.UINT8[R_IO_HL])
     2236#define RSCAN0RMDF07HH (RSCAN0.RMDF07.UINT8[R_IO_HH])
     2237#define RSCAN0RMDF17 (RSCAN0.RMDF17.UINT32)
     2238#define RSCAN0RMDF17L (RSCAN0.RMDF17.UINT16[R_IO_L])
     2239#define RSCAN0RMDF17LL (RSCAN0.RMDF17.UINT8[R_IO_LL])
     2240#define RSCAN0RMDF17LH (RSCAN0.RMDF17.UINT8[R_IO_LH])
     2241#define RSCAN0RMDF17H (RSCAN0.RMDF17.UINT16[R_IO_H])
     2242#define RSCAN0RMDF17HL (RSCAN0.RMDF17.UINT8[R_IO_HL])
     2243#define RSCAN0RMDF17HH (RSCAN0.RMDF17.UINT8[R_IO_HH])
     2244#define RSCAN0RMID8 (RSCAN0.RMID8.UINT32)
     2245#define RSCAN0RMID8L (RSCAN0.RMID8.UINT16[R_IO_L])
     2246#define RSCAN0RMID8LL (RSCAN0.RMID8.UINT8[R_IO_LL])
     2247#define RSCAN0RMID8LH (RSCAN0.RMID8.UINT8[R_IO_LH])
     2248#define RSCAN0RMID8H (RSCAN0.RMID8.UINT16[R_IO_H])
     2249#define RSCAN0RMID8HL (RSCAN0.RMID8.UINT8[R_IO_HL])
     2250#define RSCAN0RMID8HH (RSCAN0.RMID8.UINT8[R_IO_HH])
     2251#define RSCAN0RMPTR8 (RSCAN0.RMPTR8.UINT32)
     2252#define RSCAN0RMPTR8L (RSCAN0.RMPTR8.UINT16[R_IO_L])
     2253#define RSCAN0RMPTR8LL (RSCAN0.RMPTR8.UINT8[R_IO_LL])
     2254#define RSCAN0RMPTR8LH (RSCAN0.RMPTR8.UINT8[R_IO_LH])
     2255#define RSCAN0RMPTR8H (RSCAN0.RMPTR8.UINT16[R_IO_H])
     2256#define RSCAN0RMPTR8HL (RSCAN0.RMPTR8.UINT8[R_IO_HL])
     2257#define RSCAN0RMPTR8HH (RSCAN0.RMPTR8.UINT8[R_IO_HH])
     2258#define RSCAN0RMDF08 (RSCAN0.RMDF08.UINT32)
     2259#define RSCAN0RMDF08L (RSCAN0.RMDF08.UINT16[R_IO_L])
     2260#define RSCAN0RMDF08LL (RSCAN0.RMDF08.UINT8[R_IO_LL])
     2261#define RSCAN0RMDF08LH (RSCAN0.RMDF08.UINT8[R_IO_LH])
     2262#define RSCAN0RMDF08H (RSCAN0.RMDF08.UINT16[R_IO_H])
     2263#define RSCAN0RMDF08HL (RSCAN0.RMDF08.UINT8[R_IO_HL])
     2264#define RSCAN0RMDF08HH (RSCAN0.RMDF08.UINT8[R_IO_HH])
     2265#define RSCAN0RMDF18 (RSCAN0.RMDF18.UINT32)
     2266#define RSCAN0RMDF18L (RSCAN0.RMDF18.UINT16[R_IO_L])
     2267#define RSCAN0RMDF18LL (RSCAN0.RMDF18.UINT8[R_IO_LL])
     2268#define RSCAN0RMDF18LH (RSCAN0.RMDF18.UINT8[R_IO_LH])
     2269#define RSCAN0RMDF18H (RSCAN0.RMDF18.UINT16[R_IO_H])
     2270#define RSCAN0RMDF18HL (RSCAN0.RMDF18.UINT8[R_IO_HL])
     2271#define RSCAN0RMDF18HH (RSCAN0.RMDF18.UINT8[R_IO_HH])
     2272#define RSCAN0RMID9 (RSCAN0.RMID9.UINT32)
     2273#define RSCAN0RMID9L (RSCAN0.RMID9.UINT16[R_IO_L])
     2274#define RSCAN0RMID9LL (RSCAN0.RMID9.UINT8[R_IO_LL])
     2275#define RSCAN0RMID9LH (RSCAN0.RMID9.UINT8[R_IO_LH])
     2276#define RSCAN0RMID9H (RSCAN0.RMID9.UINT16[R_IO_H])
     2277#define RSCAN0RMID9HL (RSCAN0.RMID9.UINT8[R_IO_HL])
     2278#define RSCAN0RMID9HH (RSCAN0.RMID9.UINT8[R_IO_HH])
     2279#define RSCAN0RMPTR9 (RSCAN0.RMPTR9.UINT32)
     2280#define RSCAN0RMPTR9L (RSCAN0.RMPTR9.UINT16[R_IO_L])
     2281#define RSCAN0RMPTR9LL (RSCAN0.RMPTR9.UINT8[R_IO_LL])
     2282#define RSCAN0RMPTR9LH (RSCAN0.RMPTR9.UINT8[R_IO_LH])
     2283#define RSCAN0RMPTR9H (RSCAN0.RMPTR9.UINT16[R_IO_H])
     2284#define RSCAN0RMPTR9HL (RSCAN0.RMPTR9.UINT8[R_IO_HL])
     2285#define RSCAN0RMPTR9HH (RSCAN0.RMPTR9.UINT8[R_IO_HH])
     2286#define RSCAN0RMDF09 (RSCAN0.RMDF09.UINT32)
     2287#define RSCAN0RMDF09L (RSCAN0.RMDF09.UINT16[R_IO_L])
     2288#define RSCAN0RMDF09LL (RSCAN0.RMDF09.UINT8[R_IO_LL])
     2289#define RSCAN0RMDF09LH (RSCAN0.RMDF09.UINT8[R_IO_LH])
     2290#define RSCAN0RMDF09H (RSCAN0.RMDF09.UINT16[R_IO_H])
     2291#define RSCAN0RMDF09HL (RSCAN0.RMDF09.UINT8[R_IO_HL])
     2292#define RSCAN0RMDF09HH (RSCAN0.RMDF09.UINT8[R_IO_HH])
     2293#define RSCAN0RMDF19 (RSCAN0.RMDF19.UINT32)
     2294#define RSCAN0RMDF19L (RSCAN0.RMDF19.UINT16[R_IO_L])
     2295#define RSCAN0RMDF19LL (RSCAN0.RMDF19.UINT8[R_IO_LL])
     2296#define RSCAN0RMDF19LH (RSCAN0.RMDF19.UINT8[R_IO_LH])
     2297#define RSCAN0RMDF19H (RSCAN0.RMDF19.UINT16[R_IO_H])
     2298#define RSCAN0RMDF19HL (RSCAN0.RMDF19.UINT8[R_IO_HL])
     2299#define RSCAN0RMDF19HH (RSCAN0.RMDF19.UINT8[R_IO_HH])
     2300#define RSCAN0RMID10 (RSCAN0.RMID10.UINT32)
     2301#define RSCAN0RMID10L (RSCAN0.RMID10.UINT16[R_IO_L])
     2302#define RSCAN0RMID10LL (RSCAN0.RMID10.UINT8[R_IO_LL])
     2303#define RSCAN0RMID10LH (RSCAN0.RMID10.UINT8[R_IO_LH])
     2304#define RSCAN0RMID10H (RSCAN0.RMID10.UINT16[R_IO_H])
     2305#define RSCAN0RMID10HL (RSCAN0.RMID10.UINT8[R_IO_HL])
     2306#define RSCAN0RMID10HH (RSCAN0.RMID10.UINT8[R_IO_HH])
     2307#define RSCAN0RMPTR10 (RSCAN0.RMPTR10.UINT32)
     2308#define RSCAN0RMPTR10L (RSCAN0.RMPTR10.UINT16[R_IO_L])
     2309#define RSCAN0RMPTR10LL (RSCAN0.RMPTR10.UINT8[R_IO_LL])
     2310#define RSCAN0RMPTR10LH (RSCAN0.RMPTR10.UINT8[R_IO_LH])
     2311#define RSCAN0RMPTR10H (RSCAN0.RMPTR10.UINT16[R_IO_H])
     2312#define RSCAN0RMPTR10HL (RSCAN0.RMPTR10.UINT8[R_IO_HL])
     2313#define RSCAN0RMPTR10HH (RSCAN0.RMPTR10.UINT8[R_IO_HH])
     2314#define RSCAN0RMDF010 (RSCAN0.RMDF010.UINT32)
     2315#define RSCAN0RMDF010L (RSCAN0.RMDF010.UINT16[R_IO_L])
     2316#define RSCAN0RMDF010LL (RSCAN0.RMDF010.UINT8[R_IO_LL])
     2317#define RSCAN0RMDF010LH (RSCAN0.RMDF010.UINT8[R_IO_LH])
     2318#define RSCAN0RMDF010H (RSCAN0.RMDF010.UINT16[R_IO_H])
     2319#define RSCAN0RMDF010HL (RSCAN0.RMDF010.UINT8[R_IO_HL])
     2320#define RSCAN0RMDF010HH (RSCAN0.RMDF010.UINT8[R_IO_HH])
     2321#define RSCAN0RMDF110 (RSCAN0.RMDF110.UINT32)
     2322#define RSCAN0RMDF110L (RSCAN0.RMDF110.UINT16[R_IO_L])
     2323#define RSCAN0RMDF110LL (RSCAN0.RMDF110.UINT8[R_IO_LL])
     2324#define RSCAN0RMDF110LH (RSCAN0.RMDF110.UINT8[R_IO_LH])
     2325#define RSCAN0RMDF110H (RSCAN0.RMDF110.UINT16[R_IO_H])
     2326#define RSCAN0RMDF110HL (RSCAN0.RMDF110.UINT8[R_IO_HL])
     2327#define RSCAN0RMDF110HH (RSCAN0.RMDF110.UINT8[R_IO_HH])
     2328#define RSCAN0RMID11 (RSCAN0.RMID11.UINT32)
     2329#define RSCAN0RMID11L (RSCAN0.RMID11.UINT16[R_IO_L])
     2330#define RSCAN0RMID11LL (RSCAN0.RMID11.UINT8[R_IO_LL])
     2331#define RSCAN0RMID11LH (RSCAN0.RMID11.UINT8[R_IO_LH])
     2332#define RSCAN0RMID11H (RSCAN0.RMID11.UINT16[R_IO_H])
     2333#define RSCAN0RMID11HL (RSCAN0.RMID11.UINT8[R_IO_HL])
     2334#define RSCAN0RMID11HH (RSCAN0.RMID11.UINT8[R_IO_HH])
     2335#define RSCAN0RMPTR11 (RSCAN0.RMPTR11.UINT32)
     2336#define RSCAN0RMPTR11L (RSCAN0.RMPTR11.UINT16[R_IO_L])
     2337#define RSCAN0RMPTR11LL (RSCAN0.RMPTR11.UINT8[R_IO_LL])
     2338#define RSCAN0RMPTR11LH (RSCAN0.RMPTR11.UINT8[R_IO_LH])
     2339#define RSCAN0RMPTR11H (RSCAN0.RMPTR11.UINT16[R_IO_H])
     2340#define RSCAN0RMPTR11HL (RSCAN0.RMPTR11.UINT8[R_IO_HL])
     2341#define RSCAN0RMPTR11HH (RSCAN0.RMPTR11.UINT8[R_IO_HH])
     2342#define RSCAN0RMDF011 (RSCAN0.RMDF011.UINT32)
     2343#define RSCAN0RMDF011L (RSCAN0.RMDF011.UINT16[R_IO_L])
     2344#define RSCAN0RMDF011LL (RSCAN0.RMDF011.UINT8[R_IO_LL])
     2345#define RSCAN0RMDF011LH (RSCAN0.RMDF011.UINT8[R_IO_LH])
     2346#define RSCAN0RMDF011H (RSCAN0.RMDF011.UINT16[R_IO_H])
     2347#define RSCAN0RMDF011HL (RSCAN0.RMDF011.UINT8[R_IO_HL])
     2348#define RSCAN0RMDF011HH (RSCAN0.RMDF011.UINT8[R_IO_HH])
     2349#define RSCAN0RMDF111 (RSCAN0.RMDF111.UINT32)
     2350#define RSCAN0RMDF111L (RSCAN0.RMDF111.UINT16[R_IO_L])
     2351#define RSCAN0RMDF111LL (RSCAN0.RMDF111.UINT8[R_IO_LL])
     2352#define RSCAN0RMDF111LH (RSCAN0.RMDF111.UINT8[R_IO_LH])
     2353#define RSCAN0RMDF111H (RSCAN0.RMDF111.UINT16[R_IO_H])
     2354#define RSCAN0RMDF111HL (RSCAN0.RMDF111.UINT8[R_IO_HL])
     2355#define RSCAN0RMDF111HH (RSCAN0.RMDF111.UINT8[R_IO_HH])
     2356#define RSCAN0RMID12 (RSCAN0.RMID12.UINT32)
     2357#define RSCAN0RMID12L (RSCAN0.RMID12.UINT16[R_IO_L])
     2358#define RSCAN0RMID12LL (RSCAN0.RMID12.UINT8[R_IO_LL])
     2359#define RSCAN0RMID12LH (RSCAN0.RMID12.UINT8[R_IO_LH])
     2360#define RSCAN0RMID12H (RSCAN0.RMID12.UINT16[R_IO_H])
     2361#define RSCAN0RMID12HL (RSCAN0.RMID12.UINT8[R_IO_HL])
     2362#define RSCAN0RMID12HH (RSCAN0.RMID12.UINT8[R_IO_HH])
     2363#define RSCAN0RMPTR12 (RSCAN0.RMPTR12.UINT32)
     2364#define RSCAN0RMPTR12L (RSCAN0.RMPTR12.UINT16[R_IO_L])
     2365#define RSCAN0RMPTR12LL (RSCAN0.RMPTR12.UINT8[R_IO_LL])
     2366#define RSCAN0RMPTR12LH (RSCAN0.RMPTR12.UINT8[R_IO_LH])
     2367#define RSCAN0RMPTR12H (RSCAN0.RMPTR12.UINT16[R_IO_H])
     2368#define RSCAN0RMPTR12HL (RSCAN0.RMPTR12.UINT8[R_IO_HL])
     2369#define RSCAN0RMPTR12HH (RSCAN0.RMPTR12.UINT8[R_IO_HH])
     2370#define RSCAN0RMDF012 (RSCAN0.RMDF012.UINT32)
     2371#define RSCAN0RMDF012L (RSCAN0.RMDF012.UINT16[R_IO_L])
     2372#define RSCAN0RMDF012LL (RSCAN0.RMDF012.UINT8[R_IO_LL])
     2373#define RSCAN0RMDF012LH (RSCAN0.RMDF012.UINT8[R_IO_LH])
     2374#define RSCAN0RMDF012H (RSCAN0.RMDF012.UINT16[R_IO_H])
     2375#define RSCAN0RMDF012HL (RSCAN0.RMDF012.UINT8[R_IO_HL])
     2376#define RSCAN0RMDF012HH (RSCAN0.RMDF012.UINT8[R_IO_HH])
     2377#define RSCAN0RMDF112 (RSCAN0.RMDF112.UINT32)
     2378#define RSCAN0RMDF112L (RSCAN0.RMDF112.UINT16[R_IO_L])
     2379#define RSCAN0RMDF112LL (RSCAN0.RMDF112.UINT8[R_IO_LL])
     2380#define RSCAN0RMDF112LH (RSCAN0.RMDF112.UINT8[R_IO_LH])
     2381#define RSCAN0RMDF112H (RSCAN0.RMDF112.UINT16[R_IO_H])
     2382#define RSCAN0RMDF112HL (RSCAN0.RMDF112.UINT8[R_IO_HL])
     2383#define RSCAN0RMDF112HH (RSCAN0.RMDF112.UINT8[R_IO_HH])
     2384#define RSCAN0RMID13 (RSCAN0.RMID13.UINT32)
     2385#define RSCAN0RMID13L (RSCAN0.RMID13.UINT16[R_IO_L])
     2386#define RSCAN0RMID13LL (RSCAN0.RMID13.UINT8[R_IO_LL])
     2387#define RSCAN0RMID13LH (RSCAN0.RMID13.UINT8[R_IO_LH])
     2388#define RSCAN0RMID13H (RSCAN0.RMID13.UINT16[R_IO_H])
     2389#define RSCAN0RMID13HL (RSCAN0.RMID13.UINT8[R_IO_HL])
     2390#define RSCAN0RMID13HH (RSCAN0.RMID13.UINT8[R_IO_HH])
     2391#define RSCAN0RMPTR13 (RSCAN0.RMPTR13.UINT32)
     2392#define RSCAN0RMPTR13L (RSCAN0.RMPTR13.UINT16[R_IO_L])
     2393#define RSCAN0RMPTR13LL (RSCAN0.RMPTR13.UINT8[R_IO_LL])
     2394#define RSCAN0RMPTR13LH (RSCAN0.RMPTR13.UINT8[R_IO_LH])
     2395#define RSCAN0RMPTR13H (RSCAN0.RMPTR13.UINT16[R_IO_H])
     2396#define RSCAN0RMPTR13HL (RSCAN0.RMPTR13.UINT8[R_IO_HL])
     2397#define RSCAN0RMPTR13HH (RSCAN0.RMPTR13.UINT8[R_IO_HH])
     2398#define RSCAN0RMDF013 (RSCAN0.RMDF013.UINT32)
     2399#define RSCAN0RMDF013L (RSCAN0.RMDF013.UINT16[R_IO_L])
     2400#define RSCAN0RMDF013LL (RSCAN0.RMDF013.UINT8[R_IO_LL])
     2401#define RSCAN0RMDF013LH (RSCAN0.RMDF013.UINT8[R_IO_LH])
     2402#define RSCAN0RMDF013H (RSCAN0.RMDF013.UINT16[R_IO_H])
     2403#define RSCAN0RMDF013HL (RSCAN0.RMDF013.UINT8[R_IO_HL])
     2404#define RSCAN0RMDF013HH (RSCAN0.RMDF013.UINT8[R_IO_HH])
     2405#define RSCAN0RMDF113 (RSCAN0.RMDF113.UINT32)
     2406#define RSCAN0RMDF113L (RSCAN0.RMDF113.UINT16[R_IO_L])
     2407#define RSCAN0RMDF113LL (RSCAN0.RMDF113.UINT8[R_IO_LL])
     2408#define RSCAN0RMDF113LH (RSCAN0.RMDF113.UINT8[R_IO_LH])
     2409#define RSCAN0RMDF113H (RSCAN0.RMDF113.UINT16[R_IO_H])
     2410#define RSCAN0RMDF113HL (RSCAN0.RMDF113.UINT8[R_IO_HL])
     2411#define RSCAN0RMDF113HH (RSCAN0.RMDF113.UINT8[R_IO_HH])
     2412#define RSCAN0RMID14 (RSCAN0.RMID14.UINT32)
     2413#define RSCAN0RMID14L (RSCAN0.RMID14.UINT16[R_IO_L])
     2414#define RSCAN0RMID14LL (RSCAN0.RMID14.UINT8[R_IO_LL])
     2415#define RSCAN0RMID14LH (RSCAN0.RMID14.UINT8[R_IO_LH])
     2416#define RSCAN0RMID14H (RSCAN0.RMID14.UINT16[R_IO_H])
     2417#define RSCAN0RMID14HL (RSCAN0.RMID14.UINT8[R_IO_HL])
     2418#define RSCAN0RMID14HH (RSCAN0.RMID14.UINT8[R_IO_HH])
     2419#define RSCAN0RMPTR14 (RSCAN0.RMPTR14.UINT32)
     2420#define RSCAN0RMPTR14L (RSCAN0.RMPTR14.UINT16[R_IO_L])
     2421#define RSCAN0RMPTR14LL (RSCAN0.RMPTR14.UINT8[R_IO_LL])
     2422#define RSCAN0RMPTR14LH (RSCAN0.RMPTR14.UINT8[R_IO_LH])
     2423#define RSCAN0RMPTR14H (RSCAN0.RMPTR14.UINT16[R_IO_H])
     2424#define RSCAN0RMPTR14HL (RSCAN0.RMPTR14.UINT8[R_IO_HL])
     2425#define RSCAN0RMPTR14HH (RSCAN0.RMPTR14.UINT8[R_IO_HH])
     2426#define RSCAN0RMDF014 (RSCAN0.RMDF014.UINT32)
     2427#define RSCAN0RMDF014L (RSCAN0.RMDF014.UINT16[R_IO_L])
     2428#define RSCAN0RMDF014LL (RSCAN0.RMDF014.UINT8[R_IO_LL])
     2429#define RSCAN0RMDF014LH (RSCAN0.RMDF014.UINT8[R_IO_LH])
     2430#define RSCAN0RMDF014H (RSCAN0.RMDF014.UINT16[R_IO_H])
     2431#define RSCAN0RMDF014HL (RSCAN0.RMDF014.UINT8[R_IO_HL])
     2432#define RSCAN0RMDF014HH (RSCAN0.RMDF014.UINT8[R_IO_HH])
     2433#define RSCAN0RMDF114 (RSCAN0.RMDF114.UINT32)
     2434#define RSCAN0RMDF114L (RSCAN0.RMDF114.UINT16[R_IO_L])
     2435#define RSCAN0RMDF114LL (RSCAN0.RMDF114.UINT8[R_IO_LL])
     2436#define RSCAN0RMDF114LH (RSCAN0.RMDF114.UINT8[R_IO_LH])
     2437#define RSCAN0RMDF114H (RSCAN0.RMDF114.UINT16[R_IO_H])
     2438#define RSCAN0RMDF114HL (RSCAN0.RMDF114.UINT8[R_IO_HL])
     2439#define RSCAN0RMDF114HH (RSCAN0.RMDF114.UINT8[R_IO_HH])
     2440#define RSCAN0RMID15 (RSCAN0.RMID15.UINT32)
     2441#define RSCAN0RMID15L (RSCAN0.RMID15.UINT16[R_IO_L])
     2442#define RSCAN0RMID15LL (RSCAN0.RMID15.UINT8[R_IO_LL])
     2443#define RSCAN0RMID15LH (RSCAN0.RMID15.UINT8[R_IO_LH])
     2444#define RSCAN0RMID15H (RSCAN0.RMID15.UINT16[R_IO_H])
     2445#define RSCAN0RMID15HL (RSCAN0.RMID15.UINT8[R_IO_HL])
     2446#define RSCAN0RMID15HH (RSCAN0.RMID15.UINT8[R_IO_HH])
     2447#define RSCAN0RMPTR15 (RSCAN0.RMPTR15.UINT32)
     2448#define RSCAN0RMPTR15L (RSCAN0.RMPTR15.UINT16[R_IO_L])
     2449#define RSCAN0RMPTR15LL (RSCAN0.RMPTR15.UINT8[R_IO_LL])
     2450#define RSCAN0RMPTR15LH (RSCAN0.RMPTR15.UINT8[R_IO_LH])
     2451#define RSCAN0RMPTR15H (RSCAN0.RMPTR15.UINT16[R_IO_H])
     2452#define RSCAN0RMPTR15HL (RSCAN0.RMPTR15.UINT8[R_IO_HL])
     2453#define RSCAN0RMPTR15HH (RSCAN0.RMPTR15.UINT8[R_IO_HH])
     2454#define RSCAN0RMDF015 (RSCAN0.RMDF015.UINT32)
     2455#define RSCAN0RMDF015L (RSCAN0.RMDF015.UINT16[R_IO_L])
     2456#define RSCAN0RMDF015LL (RSCAN0.RMDF015.UINT8[R_IO_LL])
     2457#define RSCAN0RMDF015LH (RSCAN0.RMDF015.UINT8[R_IO_LH])
     2458#define RSCAN0RMDF015H (RSCAN0.RMDF015.UINT16[R_IO_H])
     2459#define RSCAN0RMDF015HL (RSCAN0.RMDF015.UINT8[R_IO_HL])
     2460#define RSCAN0RMDF015HH (RSCAN0.RMDF015.UINT8[R_IO_HH])
     2461#define RSCAN0RMDF115 (RSCAN0.RMDF115.UINT32)
     2462#define RSCAN0RMDF115L (RSCAN0.RMDF115.UINT16[R_IO_L])
     2463#define RSCAN0RMDF115LL (RSCAN0.RMDF115.UINT8[R_IO_LL])
     2464#define RSCAN0RMDF115LH (RSCAN0.RMDF115.UINT8[R_IO_LH])
     2465#define RSCAN0RMDF115H (RSCAN0.RMDF115.UINT16[R_IO_H])
     2466#define RSCAN0RMDF115HL (RSCAN0.RMDF115.UINT8[R_IO_HL])
     2467#define RSCAN0RMDF115HH (RSCAN0.RMDF115.UINT8[R_IO_HH])
     2468#define RSCAN0RMID16 (RSCAN0.RMID16.UINT32)
     2469#define RSCAN0RMID16L (RSCAN0.RMID16.UINT16[R_IO_L])
     2470#define RSCAN0RMID16LL (RSCAN0.RMID16.UINT8[R_IO_LL])
     2471#define RSCAN0RMID16LH (RSCAN0.RMID16.UINT8[R_IO_LH])
     2472#define RSCAN0RMID16H (RSCAN0.RMID16.UINT16[R_IO_H])
     2473#define RSCAN0RMID16HL (RSCAN0.RMID16.UINT8[R_IO_HL])
     2474#define RSCAN0RMID16HH (RSCAN0.RMID16.UINT8[R_IO_HH])
     2475#define RSCAN0RMPTR16 (RSCAN0.RMPTR16.UINT32)
     2476#define RSCAN0RMPTR16L (RSCAN0.RMPTR16.UINT16[R_IO_L])
     2477#define RSCAN0RMPTR16LL (RSCAN0.RMPTR16.UINT8[R_IO_LL])
     2478#define RSCAN0RMPTR16LH (RSCAN0.RMPTR16.UINT8[R_IO_LH])
     2479#define RSCAN0RMPTR16H (RSCAN0.RMPTR16.UINT16[R_IO_H])
     2480#define RSCAN0RMPTR16HL (RSCAN0.RMPTR16.UINT8[R_IO_HL])
     2481#define RSCAN0RMPTR16HH (RSCAN0.RMPTR16.UINT8[R_IO_HH])
     2482#define RSCAN0RMDF016 (RSCAN0.RMDF016.UINT32)
     2483#define RSCAN0RMDF016L (RSCAN0.RMDF016.UINT16[R_IO_L])
     2484#define RSCAN0RMDF016LL (RSCAN0.RMDF016.UINT8[R_IO_LL])
     2485#define RSCAN0RMDF016LH (RSCAN0.RMDF016.UINT8[R_IO_LH])
     2486#define RSCAN0RMDF016H (RSCAN0.RMDF016.UINT16[R_IO_H])
     2487#define RSCAN0RMDF016HL (RSCAN0.RMDF016.UINT8[R_IO_HL])
     2488#define RSCAN0RMDF016HH (RSCAN0.RMDF016.UINT8[R_IO_HH])
     2489#define RSCAN0RMDF116 (RSCAN0.RMDF116.UINT32)
     2490#define RSCAN0RMDF116L (RSCAN0.RMDF116.UINT16[R_IO_L])
     2491#define RSCAN0RMDF116LL (RSCAN0.RMDF116.UINT8[R_IO_LL])
     2492#define RSCAN0RMDF116LH (RSCAN0.RMDF116.UINT8[R_IO_LH])
     2493#define RSCAN0RMDF116H (RSCAN0.RMDF116.UINT16[R_IO_H])
     2494#define RSCAN0RMDF116HL (RSCAN0.RMDF116.UINT8[R_IO_HL])
     2495#define RSCAN0RMDF116HH (RSCAN0.RMDF116.UINT8[R_IO_HH])
     2496#define RSCAN0RMID17 (RSCAN0.RMID17.UINT32)
     2497#define RSCAN0RMID17L (RSCAN0.RMID17.UINT16[R_IO_L])
     2498#define RSCAN0RMID17LL (RSCAN0.RMID17.UINT8[R_IO_LL])
     2499#define RSCAN0RMID17LH (RSCAN0.RMID17.UINT8[R_IO_LH])
     2500#define RSCAN0RMID17H (RSCAN0.RMID17.UINT16[R_IO_H])
     2501#define RSCAN0RMID17HL (RSCAN0.RMID17.UINT8[R_IO_HL])
     2502#define RSCAN0RMID17HH (RSCAN0.RMID17.UINT8[R_IO_HH])
     2503#define RSCAN0RMPTR17 (RSCAN0.RMPTR17.UINT32)
     2504#define RSCAN0RMPTR17L (RSCAN0.RMPTR17.UINT16[R_IO_L])
     2505#define RSCAN0RMPTR17LL (RSCAN0.RMPTR17.UINT8[R_IO_LL])
     2506#define RSCAN0RMPTR17LH (RSCAN0.RMPTR17.UINT8[R_IO_LH])
     2507#define RSCAN0RMPTR17H (RSCAN0.RMPTR17.UINT16[R_IO_H])
     2508#define RSCAN0RMPTR17HL (RSCAN0.RMPTR17.UINT8[R_IO_HL])
     2509#define RSCAN0RMPTR17HH (RSCAN0.RMPTR17.UINT8[R_IO_HH])
     2510#define RSCAN0RMDF017 (RSCAN0.RMDF017.UINT32)
     2511#define RSCAN0RMDF017L (RSCAN0.RMDF017.UINT16[R_IO_L])
     2512#define RSCAN0RMDF017LL (RSCAN0.RMDF017.UINT8[R_IO_LL])
     2513#define RSCAN0RMDF017LH (RSCAN0.RMDF017.UINT8[R_IO_LH])
     2514#define RSCAN0RMDF017H (RSCAN0.RMDF017.UINT16[R_IO_H])
     2515#define RSCAN0RMDF017HL (RSCAN0.RMDF017.UINT8[R_IO_HL])
     2516#define RSCAN0RMDF017HH (RSCAN0.RMDF017.UINT8[R_IO_HH])
     2517#define RSCAN0RMDF117 (RSCAN0.RMDF117.UINT32)
     2518#define RSCAN0RMDF117L (RSCAN0.RMDF117.UINT16[R_IO_L])
     2519#define RSCAN0RMDF117LL (RSCAN0.RMDF117.UINT8[R_IO_LL])
     2520#define RSCAN0RMDF117LH (RSCAN0.RMDF117.UINT8[R_IO_LH])
     2521#define RSCAN0RMDF117H (RSCAN0.RMDF117.UINT16[R_IO_H])
     2522#define RSCAN0RMDF117HL (RSCAN0.RMDF117.UINT8[R_IO_HL])
     2523#define RSCAN0RMDF117HH (RSCAN0.RMDF117.UINT8[R_IO_HH])
     2524#define RSCAN0RMID18 (RSCAN0.RMID18.UINT32)
     2525#define RSCAN0RMID18L (RSCAN0.RMID18.UINT16[R_IO_L])
     2526#define RSCAN0RMID18LL (RSCAN0.RMID18.UINT8[R_IO_LL])
     2527#define RSCAN0RMID18LH (RSCAN0.RMID18.UINT8[R_IO_LH])
     2528#define RSCAN0RMID18H (RSCAN0.RMID18.UINT16[R_IO_H])
     2529#define RSCAN0RMID18HL (RSCAN0.RMID18.UINT8[R_IO_HL])
     2530#define RSCAN0RMID18HH (RSCAN0.RMID18.UINT8[R_IO_HH])
     2531#define RSCAN0RMPTR18 (RSCAN0.RMPTR18.UINT32)
     2532#define RSCAN0RMPTR18L (RSCAN0.RMPTR18.UINT16[R_IO_L])
     2533#define RSCAN0RMPTR18LL (RSCAN0.RMPTR18.UINT8[R_IO_LL])
     2534#define RSCAN0RMPTR18LH (RSCAN0.RMPTR18.UINT8[R_IO_LH])
     2535#define RSCAN0RMPTR18H (RSCAN0.RMPTR18.UINT16[R_IO_H])
     2536#define RSCAN0RMPTR18HL (RSCAN0.RMPTR18.UINT8[R_IO_HL])
     2537#define RSCAN0RMPTR18HH (RSCAN0.RMPTR18.UINT8[R_IO_HH])
     2538#define RSCAN0RMDF018 (RSCAN0.RMDF018.UINT32)
     2539#define RSCAN0RMDF018L (RSCAN0.RMDF018.UINT16[R_IO_L])
     2540#define RSCAN0RMDF018LL (RSCAN0.RMDF018.UINT8[R_IO_LL])
     2541#define RSCAN0RMDF018LH (RSCAN0.RMDF018.UINT8[R_IO_LH])
     2542#define RSCAN0RMDF018H (RSCAN0.RMDF018.UINT16[R_IO_H])
     2543#define RSCAN0RMDF018HL (RSCAN0.RMDF018.UINT8[R_IO_HL])
     2544#define RSCAN0RMDF018HH (RSCAN0.RMDF018.UINT8[R_IO_HH])
     2545#define RSCAN0RMDF118 (RSCAN0.RMDF118.UINT32)
     2546#define RSCAN0RMDF118L (RSCAN0.RMDF118.UINT16[R_IO_L])
     2547#define RSCAN0RMDF118LL (RSCAN0.RMDF118.UINT8[R_IO_LL])
     2548#define RSCAN0RMDF118LH (RSCAN0.RMDF118.UINT8[R_IO_LH])
     2549#define RSCAN0RMDF118H (RSCAN0.RMDF118.UINT16[R_IO_H])
     2550#define RSCAN0RMDF118HL (RSCAN0.RMDF118.UINT8[R_IO_HL])
     2551#define RSCAN0RMDF118HH (RSCAN0.RMDF118.UINT8[R_IO_HH])
     2552#define RSCAN0RMID19 (RSCAN0.RMID19.UINT32)
     2553#define RSCAN0RMID19L (RSCAN0.RMID19.UINT16[R_IO_L])
     2554#define RSCAN0RMID19LL (RSCAN0.RMID19.UINT8[R_IO_LL])
     2555#define RSCAN0RMID19LH (RSCAN0.RMID19.UINT8[R_IO_LH])
     2556#define RSCAN0RMID19H (RSCAN0.RMID19.UINT16[R_IO_H])
     2557#define RSCAN0RMID19HL (RSCAN0.RMID19.UINT8[R_IO_HL])
     2558#define RSCAN0RMID19HH (RSCAN0.RMID19.UINT8[R_IO_HH])
     2559#define RSCAN0RMPTR19 (RSCAN0.RMPTR19.UINT32)
     2560#define RSCAN0RMPTR19L (RSCAN0.RMPTR19.UINT16[R_IO_L])
     2561#define RSCAN0RMPTR19LL (RSCAN0.RMPTR19.UINT8[R_IO_LL])
     2562#define RSCAN0RMPTR19LH (RSCAN0.RMPTR19.UINT8[R_IO_LH])
     2563#define RSCAN0RMPTR19H (RSCAN0.RMPTR19.UINT16[R_IO_H])
     2564#define RSCAN0RMPTR19HL (RSCAN0.RMPTR19.UINT8[R_IO_HL])
     2565#define RSCAN0RMPTR19HH (RSCAN0.RMPTR19.UINT8[R_IO_HH])
     2566#define RSCAN0RMDF019 (RSCAN0.RMDF019.UINT32)
     2567#define RSCAN0RMDF019L (RSCAN0.RMDF019.UINT16[R_IO_L])
     2568#define RSCAN0RMDF019LL (RSCAN0.RMDF019.UINT8[R_IO_LL])
     2569#define RSCAN0RMDF019LH (RSCAN0.RMDF019.UINT8[R_IO_LH])
     2570#define RSCAN0RMDF019H (RSCAN0.RMDF019.UINT16[R_IO_H])
     2571#define RSCAN0RMDF019HL (RSCAN0.RMDF019.UINT8[R_IO_HL])
     2572#define RSCAN0RMDF019HH (RSCAN0.RMDF019.UINT8[R_IO_HH])
     2573#define RSCAN0RMDF119 (RSCAN0.RMDF119.UINT32)
     2574#define RSCAN0RMDF119L (RSCAN0.RMDF119.UINT16[R_IO_L])
     2575#define RSCAN0RMDF119LL (RSCAN0.RMDF119.UINT8[R_IO_LL])
     2576#define RSCAN0RMDF119LH (RSCAN0.RMDF119.UINT8[R_IO_LH])
     2577#define RSCAN0RMDF119H (RSCAN0.RMDF119.UINT16[R_IO_H])
     2578#define RSCAN0RMDF119HL (RSCAN0.RMDF119.UINT8[R_IO_HL])
     2579#define RSCAN0RMDF119HH (RSCAN0.RMDF119.UINT8[R_IO_HH])
     2580#define RSCAN0RMID20 (RSCAN0.RMID20.UINT32)
     2581#define RSCAN0RMID20L (RSCAN0.RMID20.UINT16[R_IO_L])
     2582#define RSCAN0RMID20LL (RSCAN0.RMID20.UINT8[R_IO_LL])
     2583#define RSCAN0RMID20LH (RSCAN0.RMID20.UINT8[R_IO_LH])
     2584#define RSCAN0RMID20H (RSCAN0.RMID20.UINT16[R_IO_H])
     2585#define RSCAN0RMID20HL (RSCAN0.RMID20.UINT8[R_IO_HL])
     2586#define RSCAN0RMID20HH (RSCAN0.RMID20.UINT8[R_IO_HH])
     2587#define RSCAN0RMPTR20 (RSCAN0.RMPTR20.UINT32)
     2588#define RSCAN0RMPTR20L (RSCAN0.RMPTR20.UINT16[R_IO_L])
     2589#define RSCAN0RMPTR20LL (RSCAN0.RMPTR20.UINT8[R_IO_LL])
     2590#define RSCAN0RMPTR20LH (RSCAN0.RMPTR20.UINT8[R_IO_LH])
     2591#define RSCAN0RMPTR20H (RSCAN0.RMPTR20.UINT16[R_IO_H])
     2592#define RSCAN0RMPTR20HL (RSCAN0.RMPTR20.UINT8[R_IO_HL])
     2593#define RSCAN0RMPTR20HH (RSCAN0.RMPTR20.UINT8[R_IO_HH])
     2594#define RSCAN0RMDF020 (RSCAN0.RMDF020.UINT32)
     2595#define RSCAN0RMDF020L (RSCAN0.RMDF020.UINT16[R_IO_L])
     2596#define RSCAN0RMDF020LL (RSCAN0.RMDF020.UINT8[R_IO_LL])
     2597#define RSCAN0RMDF020LH (RSCAN0.RMDF020.UINT8[R_IO_LH])
     2598#define RSCAN0RMDF020H (RSCAN0.RMDF020.UINT16[R_IO_H])
     2599#define RSCAN0RMDF020HL (RSCAN0.RMDF020.UINT8[R_IO_HL])
     2600#define RSCAN0RMDF020HH (RSCAN0.RMDF020.UINT8[R_IO_HH])
     2601#define RSCAN0RMDF120 (RSCAN0.RMDF120.UINT32)
     2602#define RSCAN0RMDF120L (RSCAN0.RMDF120.UINT16[R_IO_L])
     2603#define RSCAN0RMDF120LL (RSCAN0.RMDF120.UINT8[R_IO_LL])
     2604#define RSCAN0RMDF120LH (RSCAN0.RMDF120.UINT8[R_IO_LH])
     2605#define RSCAN0RMDF120H (RSCAN0.RMDF120.UINT16[R_IO_H])
     2606#define RSCAN0RMDF120HL (RSCAN0.RMDF120.UINT8[R_IO_HL])
     2607#define RSCAN0RMDF120HH (RSCAN0.RMDF120.UINT8[R_IO_HH])
     2608#define RSCAN0RMID21 (RSCAN0.RMID21.UINT32)
     2609#define RSCAN0RMID21L (RSCAN0.RMID21.UINT16[R_IO_L])
     2610#define RSCAN0RMID21LL (RSCAN0.RMID21.UINT8[R_IO_LL])
     2611#define RSCAN0RMID21LH (RSCAN0.RMID21.UINT8[R_IO_LH])
     2612#define RSCAN0RMID21H (RSCAN0.RMID21.UINT16[R_IO_H])
     2613#define RSCAN0RMID21HL (RSCAN0.RMID21.UINT8[R_IO_HL])
     2614#define RSCAN0RMID21HH (RSCAN0.RMID21.UINT8[R_IO_HH])
     2615#define RSCAN0RMPTR21 (RSCAN0.RMPTR21.UINT32)
     2616#define RSCAN0RMPTR21L (RSCAN0.RMPTR21.UINT16[R_IO_L])
     2617#define RSCAN0RMPTR21LL (RSCAN0.RMPTR21.UINT8[R_IO_LL])
     2618#define RSCAN0RMPTR21LH (RSCAN0.RMPTR21.UINT8[R_IO_LH])
     2619#define RSCAN0RMPTR21H (RSCAN0.RMPTR21.UINT16[R_IO_H])
     2620#define RSCAN0RMPTR21HL (RSCAN0.RMPTR21.UINT8[R_IO_HL])
     2621#define RSCAN0RMPTR21HH (RSCAN0.RMPTR21.UINT8[R_IO_HH])
     2622#define RSCAN0RMDF021 (RSCAN0.RMDF021.UINT32)
     2623#define RSCAN0RMDF021L (RSCAN0.RMDF021.UINT16[R_IO_L])
     2624#define RSCAN0RMDF021LL (RSCAN0.RMDF021.UINT8[R_IO_LL])
     2625#define RSCAN0RMDF021LH (RSCAN0.RMDF021.UINT8[R_IO_LH])
     2626#define RSCAN0RMDF021H (RSCAN0.RMDF021.UINT16[R_IO_H])
     2627#define RSCAN0RMDF021HL (RSCAN0.RMDF021.UINT8[R_IO_HL])
     2628#define RSCAN0RMDF021HH (RSCAN0.RMDF021.UINT8[R_IO_HH])
     2629#define RSCAN0RMDF121 (RSCAN0.RMDF121.UINT32)
     2630#define RSCAN0RMDF121L (RSCAN0.RMDF121.UINT16[R_IO_L])
     2631#define RSCAN0RMDF121LL (RSCAN0.RMDF121.UINT8[R_IO_LL])
     2632#define RSCAN0RMDF121LH (RSCAN0.RMDF121.UINT8[R_IO_LH])
     2633#define RSCAN0RMDF121H (RSCAN0.RMDF121.UINT16[R_IO_H])
     2634#define RSCAN0RMDF121HL (RSCAN0.RMDF121.UINT8[R_IO_HL])
     2635#define RSCAN0RMDF121HH (RSCAN0.RMDF121.UINT8[R_IO_HH])
     2636#define RSCAN0RMID22 (RSCAN0.RMID22.UINT32)
     2637#define RSCAN0RMID22L (RSCAN0.RMID22.UINT16[R_IO_L])
     2638#define RSCAN0RMID22LL (RSCAN0.RMID22.UINT8[R_IO_LL])
     2639#define RSCAN0RMID22LH (RSCAN0.RMID22.UINT8[R_IO_LH])
     2640#define RSCAN0RMID22H (RSCAN0.RMID22.UINT16[R_IO_H])
     2641#define RSCAN0RMID22HL (RSCAN0.RMID22.UINT8[R_IO_HL])
     2642#define RSCAN0RMID22HH (RSCAN0.RMID22.UINT8[R_IO_HH])
     2643#define RSCAN0RMPTR22 (RSCAN0.RMPTR22.UINT32)
     2644#define RSCAN0RMPTR22L (RSCAN0.RMPTR22.UINT16[R_IO_L])
     2645#define RSCAN0RMPTR22LL (RSCAN0.RMPTR22.UINT8[R_IO_LL])
     2646#define RSCAN0RMPTR22LH (RSCAN0.RMPTR22.UINT8[R_IO_LH])
     2647#define RSCAN0RMPTR22H (RSCAN0.RMPTR22.UINT16[R_IO_H])
     2648#define RSCAN0RMPTR22HL (RSCAN0.RMPTR22.UINT8[R_IO_HL])
     2649#define RSCAN0RMPTR22HH (RSCAN0.RMPTR22.UINT8[R_IO_HH])
     2650#define RSCAN0RMDF022 (RSCAN0.RMDF022.UINT32)
     2651#define RSCAN0RMDF022L (RSCAN0.RMDF022.UINT16[R_IO_L])
     2652#define RSCAN0RMDF022LL (RSCAN0.RMDF022.UINT8[R_IO_LL])
     2653#define RSCAN0RMDF022LH (RSCAN0.RMDF022.UINT8[R_IO_LH])
     2654#define RSCAN0RMDF022H (RSCAN0.RMDF022.UINT16[R_IO_H])
     2655#define RSCAN0RMDF022HL (RSCAN0.RMDF022.UINT8[R_IO_HL])
     2656#define RSCAN0RMDF022HH (RSCAN0.RMDF022.UINT8[R_IO_HH])
     2657#define RSCAN0RMDF122 (RSCAN0.RMDF122.UINT32)
     2658#define RSCAN0RMDF122L (RSCAN0.RMDF122.UINT16[R_IO_L])
     2659#define RSCAN0RMDF122LL (RSCAN0.RMDF122.UINT8[R_IO_LL])
     2660#define RSCAN0RMDF122LH (RSCAN0.RMDF122.UINT8[R_IO_LH])
     2661#define RSCAN0RMDF122H (RSCAN0.RMDF122.UINT16[R_IO_H])
     2662#define RSCAN0RMDF122HL (RSCAN0.RMDF122.UINT8[R_IO_HL])
     2663#define RSCAN0RMDF122HH (RSCAN0.RMDF122.UINT8[R_IO_HH])
     2664#define RSCAN0RMID23 (RSCAN0.RMID23.UINT32)
     2665#define RSCAN0RMID23L (RSCAN0.RMID23.UINT16[R_IO_L])
     2666#define RSCAN0RMID23LL (RSCAN0.RMID23.UINT8[R_IO_LL])
     2667#define RSCAN0RMID23LH (RSCAN0.RMID23.UINT8[R_IO_LH])
     2668#define RSCAN0RMID23H (RSCAN0.RMID23.UINT16[R_IO_H])
     2669#define RSCAN0RMID23HL (RSCAN0.RMID23.UINT8[R_IO_HL])
     2670#define RSCAN0RMID23HH (RSCAN0.RMID23.UINT8[R_IO_HH])
     2671#define RSCAN0RMPTR23 (RSCAN0.RMPTR23.UINT32)
     2672#define RSCAN0RMPTR23L (RSCAN0.RMPTR23.UINT16[R_IO_L])
     2673#define RSCAN0RMPTR23LL (RSCAN0.RMPTR23.UINT8[R_IO_LL])
     2674#define RSCAN0RMPTR23LH (RSCAN0.RMPTR23.UINT8[R_IO_LH])
     2675#define RSCAN0RMPTR23H (RSCAN0.RMPTR23.UINT16[R_IO_H])
     2676#define RSCAN0RMPTR23HL (RSCAN0.RMPTR23.UINT8[R_IO_HL])
     2677#define RSCAN0RMPTR23HH (RSCAN0.RMPTR23.UINT8[R_IO_HH])
     2678#define RSCAN0RMDF023 (RSCAN0.RMDF023.UINT32)
     2679#define RSCAN0RMDF023L (RSCAN0.RMDF023.UINT16[R_IO_L])
     2680#define RSCAN0RMDF023LL (RSCAN0.RMDF023.UINT8[R_IO_LL])
     2681#define RSCAN0RMDF023LH (RSCAN0.RMDF023.UINT8[R_IO_LH])
     2682#define RSCAN0RMDF023H (RSCAN0.RMDF023.UINT16[R_IO_H])
     2683#define RSCAN0RMDF023HL (RSCAN0.RMDF023.UINT8[R_IO_HL])
     2684#define RSCAN0RMDF023HH (RSCAN0.RMDF023.UINT8[R_IO_HH])
     2685#define RSCAN0RMDF123 (RSCAN0.RMDF123.UINT32)
     2686#define RSCAN0RMDF123L (RSCAN0.RMDF123.UINT16[R_IO_L])
     2687#define RSCAN0RMDF123LL (RSCAN0.RMDF123.UINT8[R_IO_LL])
     2688#define RSCAN0RMDF123LH (RSCAN0.RMDF123.UINT8[R_IO_LH])
     2689#define RSCAN0RMDF123H (RSCAN0.RMDF123.UINT16[R_IO_H])
     2690#define RSCAN0RMDF123HL (RSCAN0.RMDF123.UINT8[R_IO_HL])
     2691#define RSCAN0RMDF123HH (RSCAN0.RMDF123.UINT8[R_IO_HH])
     2692#define RSCAN0RMID24 (RSCAN0.RMID24.UINT32)
     2693#define RSCAN0RMID24L (RSCAN0.RMID24.UINT16[R_IO_L])
     2694#define RSCAN0RMID24LL (RSCAN0.RMID24.UINT8[R_IO_LL])
     2695#define RSCAN0RMID24LH (RSCAN0.RMID24.UINT8[R_IO_LH])
     2696#define RSCAN0RMID24H (RSCAN0.RMID24.UINT16[R_IO_H])
     2697#define RSCAN0RMID24HL (RSCAN0.RMID24.UINT8[R_IO_HL])
     2698#define RSCAN0RMID24HH (RSCAN0.RMID24.UINT8[R_IO_HH])
     2699#define RSCAN0RMPTR24 (RSCAN0.RMPTR24.UINT32)
     2700#define RSCAN0RMPTR24L (RSCAN0.RMPTR24.UINT16[R_IO_L])
     2701#define RSCAN0RMPTR24LL (RSCAN0.RMPTR24.UINT8[R_IO_LL])
     2702#define RSCAN0RMPTR24LH (RSCAN0.RMPTR24.UINT8[R_IO_LH])
     2703#define RSCAN0RMPTR24H (RSCAN0.RMPTR24.UINT16[R_IO_H])
     2704#define RSCAN0RMPTR24HL (RSCAN0.RMPTR24.UINT8[R_IO_HL])
     2705#define RSCAN0RMPTR24HH (RSCAN0.RMPTR24.UINT8[R_IO_HH])
     2706#define RSCAN0RMDF024 (RSCAN0.RMDF024.UINT32)
     2707#define RSCAN0RMDF024L (RSCAN0.RMDF024.UINT16[R_IO_L])
     2708#define RSCAN0RMDF024LL (RSCAN0.RMDF024.UINT8[R_IO_LL])
     2709#define RSCAN0RMDF024LH (RSCAN0.RMDF024.UINT8[R_IO_LH])
     2710#define RSCAN0RMDF024H (RSCAN0.RMDF024.UINT16[R_IO_H])
     2711#define RSCAN0RMDF024HL (RSCAN0.RMDF024.UINT8[R_IO_HL])
     2712#define RSCAN0RMDF024HH (RSCAN0.RMDF024.UINT8[R_IO_HH])
     2713#define RSCAN0RMDF124 (RSCAN0.RMDF124.UINT32)
     2714#define RSCAN0RMDF124L (RSCAN0.RMDF124.UINT16[R_IO_L])
     2715#define RSCAN0RMDF124LL (RSCAN0.RMDF124.UINT8[R_IO_LL])
     2716#define RSCAN0RMDF124LH (RSCAN0.RMDF124.UINT8[R_IO_LH])
     2717#define RSCAN0RMDF124H (RSCAN0.RMDF124.UINT16[R_IO_H])
     2718#define RSCAN0RMDF124HL (RSCAN0.RMDF124.UINT8[R_IO_HL])
     2719#define RSCAN0RMDF124HH (RSCAN0.RMDF124.UINT8[R_IO_HH])
     2720#define RSCAN0RMID25 (RSCAN0.RMID25.UINT32)
     2721#define RSCAN0RMID25L (RSCAN0.RMID25.UINT16[R_IO_L])
     2722#define RSCAN0RMID25LL (RSCAN0.RMID25.UINT8[R_IO_LL])
     2723#define RSCAN0RMID25LH (RSCAN0.RMID25.UINT8[R_IO_LH])
     2724#define RSCAN0RMID25H (RSCAN0.RMID25.UINT16[R_IO_H])
     2725#define RSCAN0RMID25HL (RSCAN0.RMID25.UINT8[R_IO_HL])
     2726#define RSCAN0RMID25HH (RSCAN0.RMID25.UINT8[R_IO_HH])
     2727#define RSCAN0RMPTR25 (RSCAN0.RMPTR25.UINT32)
     2728#define RSCAN0RMPTR25L (RSCAN0.RMPTR25.UINT16[R_IO_L])
     2729#define RSCAN0RMPTR25LL (RSCAN0.RMPTR25.UINT8[R_IO_LL])
     2730#define RSCAN0RMPTR25LH (RSCAN0.RMPTR25.UINT8[R_IO_LH])
     2731#define RSCAN0RMPTR25H (RSCAN0.RMPTR25.UINT16[R_IO_H])
     2732#define RSCAN0RMPTR25HL (RSCAN0.RMPTR25.UINT8[R_IO_HL])
     2733#define RSCAN0RMPTR25HH (RSCAN0.RMPTR25.UINT8[R_IO_HH])
     2734#define RSCAN0RMDF025 (RSCAN0.RMDF025.UINT32)
     2735#define RSCAN0RMDF025L (RSCAN0.RMDF025.UINT16[R_IO_L])
     2736#define RSCAN0RMDF025LL (RSCAN0.RMDF025.UINT8[R_IO_LL])
     2737#define RSCAN0RMDF025LH (RSCAN0.RMDF025.UINT8[R_IO_LH])
     2738#define RSCAN0RMDF025H (RSCAN0.RMDF025.UINT16[R_IO_H])
     2739#define RSCAN0RMDF025HL (RSCAN0.RMDF025.UINT8[R_IO_HL])
     2740#define RSCAN0RMDF025HH (RSCAN0.RMDF025.UINT8[R_IO_HH])
     2741#define RSCAN0RMDF125 (RSCAN0.RMDF125.UINT32)
     2742#define RSCAN0RMDF125L (RSCAN0.RMDF125.UINT16[R_IO_L])
     2743#define RSCAN0RMDF125LL (RSCAN0.RMDF125.UINT8[R_IO_LL])
     2744#define RSCAN0RMDF125LH (RSCAN0.RMDF125.UINT8[R_IO_LH])
     2745#define RSCAN0RMDF125H (RSCAN0.RMDF125.UINT16[R_IO_H])
     2746#define RSCAN0RMDF125HL (RSCAN0.RMDF125.UINT8[R_IO_HL])
     2747#define RSCAN0RMDF125HH (RSCAN0.RMDF125.UINT8[R_IO_HH])
     2748#define RSCAN0RMID26 (RSCAN0.RMID26.UINT32)
     2749#define RSCAN0RMID26L (RSCAN0.RMID26.UINT16[R_IO_L])
     2750#define RSCAN0RMID26LL (RSCAN0.RMID26.UINT8[R_IO_LL])
     2751#define RSCAN0RMID26LH (RSCAN0.RMID26.UINT8[R_IO_LH])
     2752#define RSCAN0RMID26H (RSCAN0.RMID26.UINT16[R_IO_H])
     2753#define RSCAN0RMID26HL (RSCAN0.RMID26.UINT8[R_IO_HL])
     2754#define RSCAN0RMID26HH (RSCAN0.RMID26.UINT8[R_IO_HH])
     2755#define RSCAN0RMPTR26 (RSCAN0.RMPTR26.UINT32)
     2756#define RSCAN0RMPTR26L (RSCAN0.RMPTR26.UINT16[R_IO_L])
     2757#define RSCAN0RMPTR26LL (RSCAN0.RMPTR26.UINT8[R_IO_LL])
     2758#define RSCAN0RMPTR26LH (RSCAN0.RMPTR26.UINT8[R_IO_LH])
     2759#define RSCAN0RMPTR26H (RSCAN0.RMPTR26.UINT16[R_IO_H])
     2760#define RSCAN0RMPTR26HL (RSCAN0.RMPTR26.UINT8[R_IO_HL])
     2761#define RSCAN0RMPTR26HH (RSCAN0.RMPTR26.UINT8[R_IO_HH])
     2762#define RSCAN0RMDF026 (RSCAN0.RMDF026.UINT32)
     2763#define RSCAN0RMDF026L (RSCAN0.RMDF026.UINT16[R_IO_L])
     2764#define RSCAN0RMDF026LL (RSCAN0.RMDF026.UINT8[R_IO_LL])
     2765#define RSCAN0RMDF026LH (RSCAN0.RMDF026.UINT8[R_IO_LH])
     2766#define RSCAN0RMDF026H (RSCAN0.RMDF026.UINT16[R_IO_H])
     2767#define RSCAN0RMDF026HL (RSCAN0.RMDF026.UINT8[R_IO_HL])
     2768#define RSCAN0RMDF026HH (RSCAN0.RMDF026.UINT8[R_IO_HH])
     2769#define RSCAN0RMDF126 (RSCAN0.RMDF126.UINT32)
     2770#define RSCAN0RMDF126L (RSCAN0.RMDF126.UINT16[R_IO_L])
     2771#define RSCAN0RMDF126LL (RSCAN0.RMDF126.UINT8[R_IO_LL])
     2772#define RSCAN0RMDF126LH (RSCAN0.RMDF126.UINT8[R_IO_LH])
     2773#define RSCAN0RMDF126H (RSCAN0.RMDF126.UINT16[R_IO_H])
     2774#define RSCAN0RMDF126HL (RSCAN0.RMDF126.UINT8[R_IO_HL])
     2775#define RSCAN0RMDF126HH (RSCAN0.RMDF126.UINT8[R_IO_HH])
     2776#define RSCAN0RMID27 (RSCAN0.RMID27.UINT32)
     2777#define RSCAN0RMID27L (RSCAN0.RMID27.UINT16[R_IO_L])
     2778#define RSCAN0RMID27LL (RSCAN0.RMID27.UINT8[R_IO_LL])
     2779#define RSCAN0RMID27LH (RSCAN0.RMID27.UINT8[R_IO_LH])
     2780#define RSCAN0RMID27H (RSCAN0.RMID27.UINT16[R_IO_H])
     2781#define RSCAN0RMID27HL (RSCAN0.RMID27.UINT8[R_IO_HL])
     2782#define RSCAN0RMID27HH (RSCAN0.RMID27.UINT8[R_IO_HH])
     2783#define RSCAN0RMPTR27 (RSCAN0.RMPTR27.UINT32)
     2784#define RSCAN0RMPTR27L (RSCAN0.RMPTR27.UINT16[R_IO_L])
     2785#define RSCAN0RMPTR27LL (RSCAN0.RMPTR27.UINT8[R_IO_LL])
     2786#define RSCAN0RMPTR27LH (RSCAN0.RMPTR27.UINT8[R_IO_LH])
     2787#define RSCAN0RMPTR27H (RSCAN0.RMPTR27.UINT16[R_IO_H])
     2788#define RSCAN0RMPTR27HL (RSCAN0.RMPTR27.UINT8[R_IO_HL])
     2789#define RSCAN0RMPTR27HH (RSCAN0.RMPTR27.UINT8[R_IO_HH])
     2790#define RSCAN0RMDF027 (RSCAN0.RMDF027.UINT32)
     2791#define RSCAN0RMDF027L (RSCAN0.RMDF027.UINT16[R_IO_L])
     2792#define RSCAN0RMDF027LL (RSCAN0.RMDF027.UINT8[R_IO_LL])
     2793#define RSCAN0RMDF027LH (RSCAN0.RMDF027.UINT8[R_IO_LH])
     2794#define RSCAN0RMDF027H (RSCAN0.RMDF027.UINT16[R_IO_H])
     2795#define RSCAN0RMDF027HL (RSCAN0.RMDF027.UINT8[R_IO_HL])
     2796#define RSCAN0RMDF027HH (RSCAN0.RMDF027.UINT8[R_IO_HH])
     2797#define RSCAN0RMDF127 (RSCAN0.RMDF127.UINT32)
     2798#define RSCAN0RMDF127L (RSCAN0.RMDF127.UINT16[R_IO_L])
     2799#define RSCAN0RMDF127LL (RSCAN0.RMDF127.UINT8[R_IO_LL])
     2800#define RSCAN0RMDF127LH (RSCAN0.RMDF127.UINT8[R_IO_LH])
     2801#define RSCAN0RMDF127H (RSCAN0.RMDF127.UINT16[R_IO_H])
     2802#define RSCAN0RMDF127HL (RSCAN0.RMDF127.UINT8[R_IO_HL])
     2803#define RSCAN0RMDF127HH (RSCAN0.RMDF127.UINT8[R_IO_HH])
     2804#define RSCAN0RMID28 (RSCAN0.RMID28.UINT32)
     2805#define RSCAN0RMID28L (RSCAN0.RMID28.UINT16[R_IO_L])
     2806#define RSCAN0RMID28LL (RSCAN0.RMID28.UINT8[R_IO_LL])
     2807#define RSCAN0RMID28LH (RSCAN0.RMID28.UINT8[R_IO_LH])
     2808#define RSCAN0RMID28H (RSCAN0.RMID28.UINT16[R_IO_H])
     2809#define RSCAN0RMID28HL (RSCAN0.RMID28.UINT8[R_IO_HL])
     2810#define RSCAN0RMID28HH (RSCAN0.RMID28.UINT8[R_IO_HH])
     2811#define RSCAN0RMPTR28 (RSCAN0.RMPTR28.UINT32)
     2812#define RSCAN0RMPTR28L (RSCAN0.RMPTR28.UINT16[R_IO_L])
     2813#define RSCAN0RMPTR28LL (RSCAN0.RMPTR28.UINT8[R_IO_LL])
     2814#define RSCAN0RMPTR28LH (RSCAN0.RMPTR28.UINT8[R_IO_LH])
     2815#define RSCAN0RMPTR28H (RSCAN0.RMPTR28.UINT16[R_IO_H])
     2816#define RSCAN0RMPTR28HL (RSCAN0.RMPTR28.UINT8[R_IO_HL])
     2817#define RSCAN0RMPTR28HH (RSCAN0.RMPTR28.UINT8[R_IO_HH])
     2818#define RSCAN0RMDF028 (RSCAN0.RMDF028.UINT32)
     2819#define RSCAN0RMDF028L (RSCAN0.RMDF028.UINT16[R_IO_L])
     2820#define RSCAN0RMDF028LL (RSCAN0.RMDF028.UINT8[R_IO_LL])
     2821#define RSCAN0RMDF028LH (RSCAN0.RMDF028.UINT8[R_IO_LH])
     2822#define RSCAN0RMDF028H (RSCAN0.RMDF028.UINT16[R_IO_H])
     2823#define RSCAN0RMDF028HL (RSCAN0.RMDF028.UINT8[R_IO_HL])
     2824#define RSCAN0RMDF028HH (RSCAN0.RMDF028.UINT8[R_IO_HH])
     2825#define RSCAN0RMDF128 (RSCAN0.RMDF128.UINT32)
     2826#define RSCAN0RMDF128L (RSCAN0.RMDF128.UINT16[R_IO_L])
     2827#define RSCAN0RMDF128LL (RSCAN0.RMDF128.UINT8[R_IO_LL])
     2828#define RSCAN0RMDF128LH (RSCAN0.RMDF128.UINT8[R_IO_LH])
     2829#define RSCAN0RMDF128H (RSCAN0.RMDF128.UINT16[R_IO_H])
     2830#define RSCAN0RMDF128HL (RSCAN0.RMDF128.UINT8[R_IO_HL])
     2831#define RSCAN0RMDF128HH (RSCAN0.RMDF128.UINT8[R_IO_HH])
     2832#define RSCAN0RMID29 (RSCAN0.RMID29.UINT32)
     2833#define RSCAN0RMID29L (RSCAN0.RMID29.UINT16[R_IO_L])
     2834#define RSCAN0RMID29LL (RSCAN0.RMID29.UINT8[R_IO_LL])
     2835#define RSCAN0RMID29LH (RSCAN0.RMID29.UINT8[R_IO_LH])
     2836#define RSCAN0RMID29H (RSCAN0.RMID29.UINT16[R_IO_H])
     2837#define RSCAN0RMID29HL (RSCAN0.RMID29.UINT8[R_IO_HL])
     2838#define RSCAN0RMID29HH (RSCAN0.RMID29.UINT8[R_IO_HH])
     2839#define RSCAN0RMPTR29 (RSCAN0.RMPTR29.UINT32)
     2840#define RSCAN0RMPTR29L (RSCAN0.RMPTR29.UINT16[R_IO_L])
     2841#define RSCAN0RMPTR29LL (RSCAN0.RMPTR29.UINT8[R_IO_LL])
     2842#define RSCAN0RMPTR29LH (RSCAN0.RMPTR29.UINT8[R_IO_LH])
     2843#define RSCAN0RMPTR29H (RSCAN0.RMPTR29.UINT16[R_IO_H])
     2844#define RSCAN0RMPTR29HL (RSCAN0.RMPTR29.UINT8[R_IO_HL])
     2845#define RSCAN0RMPTR29HH (RSCAN0.RMPTR29.UINT8[R_IO_HH])
     2846#define RSCAN0RMDF029 (RSCAN0.RMDF029.UINT32)
     2847#define RSCAN0RMDF029L (RSCAN0.RMDF029.UINT16[R_IO_L])
     2848#define RSCAN0RMDF029LL (RSCAN0.RMDF029.UINT8[R_IO_LL])
     2849#define RSCAN0RMDF029LH (RSCAN0.RMDF029.UINT8[R_IO_LH])
     2850#define RSCAN0RMDF029H (RSCAN0.RMDF029.UINT16[R_IO_H])
     2851#define RSCAN0RMDF029HL (RSCAN0.RMDF029.UINT8[R_IO_HL])
     2852#define RSCAN0RMDF029HH (RSCAN0.RMDF029.UINT8[R_IO_HH])
     2853#define RSCAN0RMDF129 (RSCAN0.RMDF129.UINT32)
     2854#define RSCAN0RMDF129L (RSCAN0.RMDF129.UINT16[R_IO_L])
     2855#define RSCAN0RMDF129LL (RSCAN0.RMDF129.UINT8[R_IO_LL])
     2856#define RSCAN0RMDF129LH (RSCAN0.RMDF129.UINT8[R_IO_LH])
     2857#define RSCAN0RMDF129H (RSCAN0.RMDF129.UINT16[R_IO_H])
     2858#define RSCAN0RMDF129HL (RSCAN0.RMDF129.UINT8[R_IO_HL])
     2859#define RSCAN0RMDF129HH (RSCAN0.RMDF129.UINT8[R_IO_HH])
     2860#define RSCAN0RMID30 (RSCAN0.RMID30.UINT32)
     2861#define RSCAN0RMID30L (RSCAN0.RMID30.UINT16[R_IO_L])
     2862#define RSCAN0RMID30LL (RSCAN0.RMID30.UINT8[R_IO_LL])
     2863#define RSCAN0RMID30LH (RSCAN0.RMID30.UINT8[R_IO_LH])
     2864#define RSCAN0RMID30H (RSCAN0.RMID30.UINT16[R_IO_H])
     2865#define RSCAN0RMID30HL (RSCAN0.RMID30.UINT8[R_IO_HL])
     2866#define RSCAN0RMID30HH (RSCAN0.RMID30.UINT8[R_IO_HH])
     2867#define RSCAN0RMPTR30 (RSCAN0.RMPTR30.UINT32)
     2868#define RSCAN0RMPTR30L (RSCAN0.RMPTR30.UINT16[R_IO_L])
     2869#define RSCAN0RMPTR30LL (RSCAN0.RMPTR30.UINT8[R_IO_LL])
     2870#define RSCAN0RMPTR30LH (RSCAN0.RMPTR30.UINT8[R_IO_LH])
     2871#define RSCAN0RMPTR30H (RSCAN0.RMPTR30.UINT16[R_IO_H])
     2872#define RSCAN0RMPTR30HL (RSCAN0.RMPTR30.UINT8[R_IO_HL])
     2873#define RSCAN0RMPTR30HH (RSCAN0.RMPTR30.UINT8[R_IO_HH])
     2874#define RSCAN0RMDF030 (RSCAN0.RMDF030.UINT32)
     2875#define RSCAN0RMDF030L (RSCAN0.RMDF030.UINT16[R_IO_L])
     2876#define RSCAN0RMDF030LL (RSCAN0.RMDF030.UINT8[R_IO_LL])
     2877#define RSCAN0RMDF030LH (RSCAN0.RMDF030.UINT8[R_IO_LH])
     2878#define RSCAN0RMDF030H (RSCAN0.RMDF030.UINT16[R_IO_H])
     2879#define RSCAN0RMDF030HL (RSCAN0.RMDF030.UINT8[R_IO_HL])
     2880#define RSCAN0RMDF030HH (RSCAN0.RMDF030.UINT8[R_IO_HH])
     2881#define RSCAN0RMDF130 (RSCAN0.RMDF130.UINT32)
     2882#define RSCAN0RMDF130L (RSCAN0.RMDF130.UINT16[R_IO_L])
     2883#define RSCAN0RMDF130LL (RSCAN0.RMDF130.UINT8[R_IO_LL])
     2884#define RSCAN0RMDF130LH (RSCAN0.RMDF130.UINT8[R_IO_LH])
     2885#define RSCAN0RMDF130H (RSCAN0.RMDF130.UINT16[R_IO_H])
     2886#define RSCAN0RMDF130HL (RSCAN0.RMDF130.UINT8[R_IO_HL])
     2887#define RSCAN0RMDF130HH (RSCAN0.RMDF130.UINT8[R_IO_HH])
     2888#define RSCAN0RMID31 (RSCAN0.RMID31.UINT32)
     2889#define RSCAN0RMID31L (RSCAN0.RMID31.UINT16[R_IO_L])
     2890#define RSCAN0RMID31LL (RSCAN0.RMID31.UINT8[R_IO_LL])
     2891#define RSCAN0RMID31LH (RSCAN0.RMID31.UINT8[R_IO_LH])
     2892#define RSCAN0RMID31H (RSCAN0.RMID31.UINT16[R_IO_H])
     2893#define RSCAN0RMID31HL (RSCAN0.RMID31.UINT8[R_IO_HL])
     2894#define RSCAN0RMID31HH (RSCAN0.RMID31.UINT8[R_IO_HH])
     2895#define RSCAN0RMPTR31 (RSCAN0.RMPTR31.UINT32)
     2896#define RSCAN0RMPTR31L (RSCAN0.RMPTR31.UINT16[R_IO_L])
     2897#define RSCAN0RMPTR31LL (RSCAN0.RMPTR31.UINT8[R_IO_LL])
     2898#define RSCAN0RMPTR31LH (RSCAN0.RMPTR31.UINT8[R_IO_LH])
     2899#define RSCAN0RMPTR31H (RSCAN0.RMPTR31.UINT16[R_IO_H])
     2900#define RSCAN0RMPTR31HL (RSCAN0.RMPTR31.UINT8[R_IO_HL])
     2901#define RSCAN0RMPTR31HH (RSCAN0.RMPTR31.UINT8[R_IO_HH])
     2902#define RSCAN0RMDF031 (RSCAN0.RMDF031.UINT32)
     2903#define RSCAN0RMDF031L (RSCAN0.RMDF031.UINT16[R_IO_L])
     2904#define RSCAN0RMDF031LL (RSCAN0.RMDF031.UINT8[R_IO_LL])
     2905#define RSCAN0RMDF031LH (RSCAN0.RMDF031.UINT8[R_IO_LH])
     2906#define RSCAN0RMDF031H (RSCAN0.RMDF031.UINT16[R_IO_H])
     2907#define RSCAN0RMDF031HL (RSCAN0.RMDF031.UINT8[R_IO_HL])
     2908#define RSCAN0RMDF031HH (RSCAN0.RMDF031.UINT8[R_IO_HH])
     2909#define RSCAN0RMDF131 (RSCAN0.RMDF131.UINT32)
     2910#define RSCAN0RMDF131L (RSCAN0.RMDF131.UINT16[R_IO_L])
     2911#define RSCAN0RMDF131LL (RSCAN0.RMDF131.UINT8[R_IO_LL])
     2912#define RSCAN0RMDF131LH (RSCAN0.RMDF131.UINT8[R_IO_LH])
     2913#define RSCAN0RMDF131H (RSCAN0.RMDF131.UINT16[R_IO_H])
     2914#define RSCAN0RMDF131HL (RSCAN0.RMDF131.UINT8[R_IO_HL])
     2915#define RSCAN0RMDF131HH (RSCAN0.RMDF131.UINT8[R_IO_HH])
     2916#define RSCAN0RMID32 (RSCAN0.RMID32.UINT32)
     2917#define RSCAN0RMID32L (RSCAN0.RMID32.UINT16[R_IO_L])
     2918#define RSCAN0RMID32LL (RSCAN0.RMID32.UINT8[R_IO_LL])
     2919#define RSCAN0RMID32LH (RSCAN0.RMID32.UINT8[R_IO_LH])
     2920#define RSCAN0RMID32H (RSCAN0.RMID32.UINT16[R_IO_H])
     2921#define RSCAN0RMID32HL (RSCAN0.RMID32.UINT8[R_IO_HL])
     2922#define RSCAN0RMID32HH (RSCAN0.RMID32.UINT8[R_IO_HH])
     2923#define RSCAN0RMPTR32 (RSCAN0.RMPTR32.UINT32)
     2924#define RSCAN0RMPTR32L (RSCAN0.RMPTR32.UINT16[R_IO_L])
     2925#define RSCAN0RMPTR32LL (RSCAN0.RMPTR32.UINT8[R_IO_LL])
     2926#define RSCAN0RMPTR32LH (RSCAN0.RMPTR32.UINT8[R_IO_LH])
     2927#define RSCAN0RMPTR32H (RSCAN0.RMPTR32.UINT16[R_IO_H])
     2928#define RSCAN0RMPTR32HL (RSCAN0.RMPTR32.UINT8[R_IO_HL])
     2929#define RSCAN0RMPTR32HH (RSCAN0.RMPTR32.UINT8[R_IO_HH])
     2930#define RSCAN0RMDF032 (RSCAN0.RMDF032.UINT32)
     2931#define RSCAN0RMDF032L (RSCAN0.RMDF032.UINT16[R_IO_L])
     2932#define RSCAN0RMDF032LL (RSCAN0.RMDF032.UINT8[R_IO_LL])
     2933#define RSCAN0RMDF032LH (RSCAN0.RMDF032.UINT8[R_IO_LH])
     2934#define RSCAN0RMDF032H (RSCAN0.RMDF032.UINT16[R_IO_H])
     2935#define RSCAN0RMDF032HL (RSCAN0.RMDF032.UINT8[R_IO_HL])
     2936#define RSCAN0RMDF032HH (RSCAN0.RMDF032.UINT8[R_IO_HH])
     2937#define RSCAN0RMDF132 (RSCAN0.RMDF132.UINT32)
     2938#define RSCAN0RMDF132L (RSCAN0.RMDF132.UINT16[R_IO_L])
     2939#define RSCAN0RMDF132LL (RSCAN0.RMDF132.UINT8[R_IO_LL])
     2940#define RSCAN0RMDF132LH (RSCAN0.RMDF132.UINT8[R_IO_LH])
     2941#define RSCAN0RMDF132H (RSCAN0.RMDF132.UINT16[R_IO_H])
     2942#define RSCAN0RMDF132HL (RSCAN0.RMDF132.UINT8[R_IO_HL])
     2943#define RSCAN0RMDF132HH (RSCAN0.RMDF132.UINT8[R_IO_HH])
     2944#define RSCAN0RMID33 (RSCAN0.RMID33.UINT32)
     2945#define RSCAN0RMID33L (RSCAN0.RMID33.UINT16[R_IO_L])
     2946#define RSCAN0RMID33LL (RSCAN0.RMID33.UINT8[R_IO_LL])
     2947#define RSCAN0RMID33LH (RSCAN0.RMID33.UINT8[R_IO_LH])
     2948#define RSCAN0RMID33H (RSCAN0.RMID33.UINT16[R_IO_H])
     2949#define RSCAN0RMID33HL (RSCAN0.RMID33.UINT8[R_IO_HL])
     2950#define RSCAN0RMID33HH (RSCAN0.RMID33.UINT8[R_IO_HH])
     2951#define RSCAN0RMPTR33 (RSCAN0.RMPTR33.UINT32)
     2952#define RSCAN0RMPTR33L (RSCAN0.RMPTR33.UINT16[R_IO_L])
     2953#define RSCAN0RMPTR33LL (RSCAN0.RMPTR33.UINT8[R_IO_LL])
     2954#define RSCAN0RMPTR33LH (RSCAN0.RMPTR33.UINT8[R_IO_LH])
     2955#define RSCAN0RMPTR33H (RSCAN0.RMPTR33.UINT16[R_IO_H])
     2956#define RSCAN0RMPTR33HL (RSCAN0.RMPTR33.UINT8[R_IO_HL])
     2957#define RSCAN0RMPTR33HH (RSCAN0.RMPTR33.UINT8[R_IO_HH])
     2958#define RSCAN0RMDF033 (RSCAN0.RMDF033.UINT32)
     2959#define RSCAN0RMDF033L (RSCAN0.RMDF033.UINT16[R_IO_L])
     2960#define RSCAN0RMDF033LL (RSCAN0.RMDF033.UINT8[R_IO_LL])
     2961#define RSCAN0RMDF033LH (RSCAN0.RMDF033.UINT8[R_IO_LH])
     2962#define RSCAN0RMDF033H (RSCAN0.RMDF033.UINT16[R_IO_H])
     2963#define RSCAN0RMDF033HL (RSCAN0.RMDF033.UINT8[R_IO_HL])
     2964#define RSCAN0RMDF033HH (RSCAN0.RMDF033.UINT8[R_IO_HH])
     2965#define RSCAN0RMDF133 (RSCAN0.RMDF133.UINT32)
     2966#define RSCAN0RMDF133L (RSCAN0.RMDF133.UINT16[R_IO_L])
     2967#define RSCAN0RMDF133LL (RSCAN0.RMDF133.UINT8[R_IO_LL])
     2968#define RSCAN0RMDF133LH (RSCAN0.RMDF133.UINT8[R_IO_LH])
     2969#define RSCAN0RMDF133H (RSCAN0.RMDF133.UINT16[R_IO_H])
     2970#define RSCAN0RMDF133HL (RSCAN0.RMDF133.UINT8[R_IO_HL])
     2971#define RSCAN0RMDF133HH (RSCAN0.RMDF133.UINT8[R_IO_HH])
     2972#define RSCAN0RMID34 (RSCAN0.RMID34.UINT32)
     2973#define RSCAN0RMID34L (RSCAN0.RMID34.UINT16[R_IO_L])
     2974#define RSCAN0RMID34LL (RSCAN0.RMID34.UINT8[R_IO_LL])
     2975#define RSCAN0RMID34LH (RSCAN0.RMID34.UINT8[R_IO_LH])
     2976#define RSCAN0RMID34H (RSCAN0.RMID34.UINT16[R_IO_H])
     2977#define RSCAN0RMID34HL (RSCAN0.RMID34.UINT8[R_IO_HL])
     2978#define RSCAN0RMID34HH (RSCAN0.RMID34.UINT8[R_IO_HH])
     2979#define RSCAN0RMPTR34 (RSCAN0.RMPTR34.UINT32)
     2980#define RSCAN0RMPTR34L (RSCAN0.RMPTR34.UINT16[R_IO_L])
     2981#define RSCAN0RMPTR34LL (RSCAN0.RMPTR34.UINT8[R_IO_LL])
     2982#define RSCAN0RMPTR34LH (RSCAN0.RMPTR34.UINT8[R_IO_LH])
     2983#define RSCAN0RMPTR34H (RSCAN0.RMPTR34.UINT16[R_IO_H])
     2984#define RSCAN0RMPTR34HL (RSCAN0.RMPTR34.UINT8[R_IO_HL])
     2985#define RSCAN0RMPTR34HH (RSCAN0.RMPTR34.UINT8[R_IO_HH])
     2986#define RSCAN0RMDF034 (RSCAN0.RMDF034.UINT32)
     2987#define RSCAN0RMDF034L (RSCAN0.RMDF034.UINT16[R_IO_L])
     2988#define RSCAN0RMDF034LL (RSCAN0.RMDF034.UINT8[R_IO_LL])
     2989#define RSCAN0RMDF034LH (RSCAN0.RMDF034.UINT8[R_IO_LH])
     2990#define RSCAN0RMDF034H (RSCAN0.RMDF034.UINT16[R_IO_H])
     2991#define RSCAN0RMDF034HL (RSCAN0.RMDF034.UINT8[R_IO_HL])
     2992#define RSCAN0RMDF034HH (RSCAN0.RMDF034.UINT8[R_IO_HH])
     2993#define RSCAN0RMDF134 (RSCAN0.RMDF134.UINT32)
     2994#define RSCAN0RMDF134L (RSCAN0.RMDF134.UINT16[R_IO_L])
     2995#define RSCAN0RMDF134LL (RSCAN0.RMDF134.UINT8[R_IO_LL])
     2996#define RSCAN0RMDF134LH (RSCAN0.RMDF134.UINT8[R_IO_LH])
     2997#define RSCAN0RMDF134H (RSCAN0.RMDF134.UINT16[R_IO_H])
     2998#define RSCAN0RMDF134HL (RSCAN0.RMDF134.UINT8[R_IO_HL])
     2999#define RSCAN0RMDF134HH (RSCAN0.RMDF134.UINT8[R_IO_HH])
     3000#define RSCAN0RMID35 (RSCAN0.RMID35.UINT32)
     3001#define RSCAN0RMID35L (RSCAN0.RMID35.UINT16[R_IO_L])
     3002#define RSCAN0RMID35LL (RSCAN0.RMID35.UINT8[R_IO_LL])
     3003#define RSCAN0RMID35LH (RSCAN0.RMID35.UINT8[R_IO_LH])
     3004#define RSCAN0RMID35H (RSCAN0.RMID35.UINT16[R_IO_H])
     3005#define RSCAN0RMID35HL (RSCAN0.RMID35.UINT8[R_IO_HL])
     3006#define RSCAN0RMID35HH (RSCAN0.RMID35.UINT8[R_IO_HH])
     3007#define RSCAN0RMPTR35 (RSCAN0.RMPTR35.UINT32)
     3008#define RSCAN0RMPTR35L (RSCAN0.RMPTR35.UINT16[R_IO_L])
     3009#define RSCAN0RMPTR35LL (RSCAN0.RMPTR35.UINT8[R_IO_LL])
     3010#define RSCAN0RMPTR35LH (RSCAN0.RMPTR35.UINT8[R_IO_LH])
     3011#define RSCAN0RMPTR35H (RSCAN0.RMPTR35.UINT16[R_IO_H])
     3012#define RSCAN0RMPTR35HL (RSCAN0.RMPTR35.UINT8[R_IO_HL])
     3013#define RSCAN0RMPTR35HH (RSCAN0.RMPTR35.UINT8[R_IO_HH])
     3014#define RSCAN0RMDF035 (RSCAN0.RMDF035.UINT32)
     3015#define RSCAN0RMDF035L (RSCAN0.RMDF035.UINT16[R_IO_L])
     3016#define RSCAN0RMDF035LL (RSCAN0.RMDF035.UINT8[R_IO_LL])
     3017#define RSCAN0RMDF035LH (RSCAN0.RMDF035.UINT8[R_IO_LH])
     3018#define RSCAN0RMDF035H (RSCAN0.RMDF035.UINT16[R_IO_H])
     3019#define RSCAN0RMDF035HL (RSCAN0.RMDF035.UINT8[R_IO_HL])
     3020#define RSCAN0RMDF035HH (RSCAN0.RMDF035.UINT8[R_IO_HH])
     3021#define RSCAN0RMDF135 (RSCAN0.RMDF135.UINT32)
     3022#define RSCAN0RMDF135L (RSCAN0.RMDF135.UINT16[R_IO_L])
     3023#define RSCAN0RMDF135LL (RSCAN0.RMDF135.UINT8[R_IO_LL])
     3024#define RSCAN0RMDF135LH (RSCAN0.RMDF135.UINT8[R_IO_LH])
     3025#define RSCAN0RMDF135H (RSCAN0.RMDF135.UINT16[R_IO_H])
     3026#define RSCAN0RMDF135HL (RSCAN0.RMDF135.UINT8[R_IO_HL])
     3027#define RSCAN0RMDF135HH (RSCAN0.RMDF135.UINT8[R_IO_HH])
     3028#define RSCAN0RMID36 (RSCAN0.RMID36.UINT32)
     3029#define RSCAN0RMID36L (RSCAN0.RMID36.UINT16[R_IO_L])
     3030#define RSCAN0RMID36LL (RSCAN0.RMID36.UINT8[R_IO_LL])
     3031#define RSCAN0RMID36LH (RSCAN0.RMID36.UINT8[R_IO_LH])
     3032#define RSCAN0RMID36H (RSCAN0.RMID36.UINT16[R_IO_H])
     3033#define RSCAN0RMID36HL (RSCAN0.RMID36.UINT8[R_IO_HL])
     3034#define RSCAN0RMID36HH (RSCAN0.RMID36.UINT8[R_IO_HH])
     3035#define RSCAN0RMPTR36 (RSCAN0.RMPTR36.UINT32)
     3036#define RSCAN0RMPTR36L (RSCAN0.RMPTR36.UINT16[R_IO_L])
     3037#define RSCAN0RMPTR36LL (RSCAN0.RMPTR36.UINT8[R_IO_LL])
     3038#define RSCAN0RMPTR36LH (RSCAN0.RMPTR36.UINT8[R_IO_LH])
     3039#define RSCAN0RMPTR36H (RSCAN0.RMPTR36.UINT16[R_IO_H])
     3040#define RSCAN0RMPTR36HL (RSCAN0.RMPTR36.UINT8[R_IO_HL])
     3041#define RSCAN0RMPTR36HH (RSCAN0.RMPTR36.UINT8[R_IO_HH])
     3042#define RSCAN0RMDF036 (RSCAN0.RMDF036.UINT32)
     3043#define RSCAN0RMDF036L (RSCAN0.RMDF036.UINT16[R_IO_L])
     3044#define RSCAN0RMDF036LL (RSCAN0.RMDF036.UINT8[R_IO_LL])
     3045#define RSCAN0RMDF036LH (RSCAN0.RMDF036.UINT8[R_IO_LH])
     3046#define RSCAN0RMDF036H (RSCAN0.RMDF036.UINT16[R_IO_H])
     3047#define RSCAN0RMDF036HL (RSCAN0.RMDF036.UINT8[R_IO_HL])
     3048#define RSCAN0RMDF036HH (RSCAN0.RMDF036.UINT8[R_IO_HH])
     3049#define RSCAN0RMDF136 (RSCAN0.RMDF136.UINT32)
     3050#define RSCAN0RMDF136L (RSCAN0.RMDF136.UINT16[R_IO_L])
     3051#define RSCAN0RMDF136LL (RSCAN0.RMDF136.UINT8[R_IO_LL])
     3052#define RSCAN0RMDF136LH (RSCAN0.RMDF136.UINT8[R_IO_LH])
     3053#define RSCAN0RMDF136H (RSCAN0.RMDF136.UINT16[R_IO_H])
     3054#define RSCAN0RMDF136HL (RSCAN0.RMDF136.UINT8[R_IO_HL])
     3055#define RSCAN0RMDF136HH (RSCAN0.RMDF136.UINT8[R_IO_HH])
     3056#define RSCAN0RMID37 (RSCAN0.RMID37.UINT32)
     3057#define RSCAN0RMID37L (RSCAN0.RMID37.UINT16[R_IO_L])
     3058#define RSCAN0RMID37LL (RSCAN0.RMID37.UINT8[R_IO_LL])
     3059#define RSCAN0RMID37LH (RSCAN0.RMID37.UINT8[R_IO_LH])
     3060#define RSCAN0RMID37H (RSCAN0.RMID37.UINT16[R_IO_H])
     3061#define RSCAN0RMID37HL (RSCAN0.RMID37.UINT8[R_IO_HL])
     3062#define RSCAN0RMID37HH (RSCAN0.RMID37.UINT8[R_IO_HH])
     3063#define RSCAN0RMPTR37 (RSCAN0.RMPTR37.UINT32)
     3064#define RSCAN0RMPTR37L (RSCAN0.RMPTR37.UINT16[R_IO_L])
     3065#define RSCAN0RMPTR37LL (RSCAN0.RMPTR37.UINT8[R_IO_LL])
     3066#define RSCAN0RMPTR37LH (RSCAN0.RMPTR37.UINT8[R_IO_LH])
     3067#define RSCAN0RMPTR37H (RSCAN0.RMPTR37.UINT16[R_IO_H])
     3068#define RSCAN0RMPTR37HL (RSCAN0.RMPTR37.UINT8[R_IO_HL])
     3069#define RSCAN0RMPTR37HH (RSCAN0.RMPTR37.UINT8[R_IO_HH])
     3070#define RSCAN0RMDF037 (RSCAN0.RMDF037.UINT32)
     3071#define RSCAN0RMDF037L (RSCAN0.RMDF037.UINT16[R_IO_L])
     3072#define RSCAN0RMDF037LL (RSCAN0.RMDF037.UINT8[R_IO_LL])
     3073#define RSCAN0RMDF037LH (RSCAN0.RMDF037.UINT8[R_IO_LH])
     3074#define RSCAN0RMDF037H (RSCAN0.RMDF037.UINT16[R_IO_H])
     3075#define RSCAN0RMDF037HL (RSCAN0.RMDF037.UINT8[R_IO_HL])
     3076#define RSCAN0RMDF037HH (RSCAN0.RMDF037.UINT8[R_IO_HH])
     3077#define RSCAN0RMDF137 (RSCAN0.RMDF137.UINT32)
     3078#define RSCAN0RMDF137L (RSCAN0.RMDF137.UINT16[R_IO_L])
     3079#define RSCAN0RMDF137LL (RSCAN0.RMDF137.UINT8[R_IO_LL])
     3080#define RSCAN0RMDF137LH (RSCAN0.RMDF137.UINT8[R_IO_LH])
     3081#define RSCAN0RMDF137H (RSCAN0.RMDF137.UINT16[R_IO_H])
     3082#define RSCAN0RMDF137HL (RSCAN0.RMDF137.UINT8[R_IO_HL])
     3083#define RSCAN0RMDF137HH (RSCAN0.RMDF137.UINT8[R_IO_HH])
     3084#define RSCAN0RMID38 (RSCAN0.RMID38.UINT32)
     3085#define RSCAN0RMID38L (RSCAN0.RMID38.UINT16[R_IO_L])
     3086#define RSCAN0RMID38LL (RSCAN0.RMID38.UINT8[R_IO_LL])
     3087#define RSCAN0RMID38LH (RSCAN0.RMID38.UINT8[R_IO_LH])
     3088#define RSCAN0RMID38H (RSCAN0.RMID38.UINT16[R_IO_H])
     3089#define RSCAN0RMID38HL (RSCAN0.RMID38.UINT8[R_IO_HL])
     3090#define RSCAN0RMID38HH (RSCAN0.RMID38.UINT8[R_IO_HH])
     3091#define RSCAN0RMPTR38 (RSCAN0.RMPTR38.UINT32)
     3092#define RSCAN0RMPTR38L (RSCAN0.RMPTR38.UINT16[R_IO_L])
     3093#define RSCAN0RMPTR38LL (RSCAN0.RMPTR38.UINT8[R_IO_LL])
     3094#define RSCAN0RMPTR38LH (RSCAN0.RMPTR38.UINT8[R_IO_LH])
     3095#define RSCAN0RMPTR38H (RSCAN0.RMPTR38.UINT16[R_IO_H])
     3096#define RSCAN0RMPTR38HL (RSCAN0.RMPTR38.UINT8[R_IO_HL])
     3097#define RSCAN0RMPTR38HH (RSCAN0.RMPTR38.UINT8[R_IO_HH])
     3098#define RSCAN0RMDF038 (RSCAN0.RMDF038.UINT32)
     3099#define RSCAN0RMDF038L (RSCAN0.RMDF038.UINT16[R_IO_L])
     3100#define RSCAN0RMDF038LL (RSCAN0.RMDF038.UINT8[R_IO_LL])
     3101#define RSCAN0RMDF038LH (RSCAN0.RMDF038.UINT8[R_IO_LH])
     3102#define RSCAN0RMDF038H (RSCAN0.RMDF038.UINT16[R_IO_H])
     3103#define RSCAN0RMDF038HL (RSCAN0.RMDF038.UINT8[R_IO_HL])
     3104#define RSCAN0RMDF038HH (RSCAN0.RMDF038.UINT8[R_IO_HH])
     3105#define RSCAN0RMDF138 (RSCAN0.RMDF138.UINT32)
     3106#define RSCAN0RMDF138L (RSCAN0.RMDF138.UINT16[R_IO_L])
     3107#define RSCAN0RMDF138LL (RSCAN0.RMDF138.UINT8[R_IO_LL])
     3108#define RSCAN0RMDF138LH (RSCAN0.RMDF138.UINT8[R_IO_LH])
     3109#define RSCAN0RMDF138H (RSCAN0.RMDF138.UINT16[R_IO_H])
     3110#define RSCAN0RMDF138HL (RSCAN0.RMDF138.UINT8[R_IO_HL])
     3111#define RSCAN0RMDF138HH (RSCAN0.RMDF138.UINT8[R_IO_HH])
     3112#define RSCAN0RMID39 (RSCAN0.RMID39.UINT32)
     3113#define RSCAN0RMID39L (RSCAN0.RMID39.UINT16[R_IO_L])
     3114#define RSCAN0RMID39LL (RSCAN0.RMID39.UINT8[R_IO_LL])
     3115#define RSCAN0RMID39LH (RSCAN0.RMID39.UINT8[R_IO_LH])
     3116#define RSCAN0RMID39H (RSCAN0.RMID39.UINT16[R_IO_H])
     3117#define RSCAN0RMID39HL (RSCAN0.RMID39.UINT8[R_IO_HL])
     3118#define RSCAN0RMID39HH (RSCAN0.RMID39.UINT8[R_IO_HH])
     3119#define RSCAN0RMPTR39 (RSCAN0.RMPTR39.UINT32)
     3120#define RSCAN0RMPTR39L (RSCAN0.RMPTR39.UINT16[R_IO_L])
     3121#define RSCAN0RMPTR39LL (RSCAN0.RMPTR39.UINT8[R_IO_LL])
     3122#define RSCAN0RMPTR39LH (RSCAN0.RMPTR39.UINT8[R_IO_LH])
     3123#define RSCAN0RMPTR39H (RSCAN0.RMPTR39.UINT16[R_IO_H])
     3124#define RSCAN0RMPTR39HL (RSCAN0.RMPTR39.UINT8[R_IO_HL])
     3125#define RSCAN0RMPTR39HH (RSCAN0.RMPTR39.UINT8[R_IO_HH])
     3126#define RSCAN0RMDF039 (RSCAN0.RMDF039.UINT32)
     3127#define RSCAN0RMDF039L (RSCAN0.RMDF039.UINT16[R_IO_L])
     3128#define RSCAN0RMDF039LL (RSCAN0.RMDF039.UINT8[R_IO_LL])
     3129#define RSCAN0RMDF039LH (RSCAN0.RMDF039.UINT8[R_IO_LH])
     3130#define RSCAN0RMDF039H (RSCAN0.RMDF039.UINT16[R_IO_H])
     3131#define RSCAN0RMDF039HL (RSCAN0.RMDF039.UINT8[R_IO_HL])
     3132#define RSCAN0RMDF039HH (RSCAN0.RMDF039.UINT8[R_IO_HH])
     3133#define RSCAN0RMDF139 (RSCAN0.RMDF139.UINT32)
     3134#define RSCAN0RMDF139L (RSCAN0.RMDF139.UINT16[R_IO_L])
     3135#define RSCAN0RMDF139LL (RSCAN0.RMDF139.UINT8[R_IO_LL])
     3136#define RSCAN0RMDF139LH (RSCAN0.RMDF139.UINT8[R_IO_LH])
     3137#define RSCAN0RMDF139H (RSCAN0.RMDF139.UINT16[R_IO_H])
     3138#define RSCAN0RMDF139HL (RSCAN0.RMDF139.UINT8[R_IO_HL])
     3139#define RSCAN0RMDF139HH (RSCAN0.RMDF139.UINT8[R_IO_HH])
     3140#define RSCAN0RMID40 (RSCAN0.RMID40.UINT32)
     3141#define RSCAN0RMID40L (RSCAN0.RMID40.UINT16[R_IO_L])
     3142#define RSCAN0RMID40LL (RSCAN0.RMID40.UINT8[R_IO_LL])
     3143#define RSCAN0RMID40LH (RSCAN0.RMID40.UINT8[R_IO_LH])
     3144#define RSCAN0RMID40H (RSCAN0.RMID40.UINT16[R_IO_H])
     3145#define RSCAN0RMID40HL (RSCAN0.RMID40.UINT8[R_IO_HL])
     3146#define RSCAN0RMID40HH (RSCAN0.RMID40.UINT8[R_IO_HH])
     3147#define RSCAN0RMPTR40 (RSCAN0.RMPTR40.UINT32)
     3148#define RSCAN0RMPTR40L (RSCAN0.RMPTR40.UINT16[R_IO_L])
     3149#define RSCAN0RMPTR40LL (RSCAN0.RMPTR40.UINT8[R_IO_LL])
     3150#define RSCAN0RMPTR40LH (RSCAN0.RMPTR40.UINT8[R_IO_LH])
     3151#define RSCAN0RMPTR40H (RSCAN0.RMPTR40.UINT16[R_IO_H])
     3152#define RSCAN0RMPTR40HL (RSCAN0.RMPTR40.UINT8[R_IO_HL])
     3153#define RSCAN0RMPTR40HH (RSCAN0.RMPTR40.UINT8[R_IO_HH])
     3154#define RSCAN0RMDF040 (RSCAN0.RMDF040.UINT32)
     3155#define RSCAN0RMDF040L (RSCAN0.RMDF040.UINT16[R_IO_L])
     3156#define RSCAN0RMDF040LL (RSCAN0.RMDF040.UINT8[R_IO_LL])
     3157#define RSCAN0RMDF040LH (RSCAN0.RMDF040.UINT8[R_IO_LH])
     3158#define RSCAN0RMDF040H (RSCAN0.RMDF040.UINT16[R_IO_H])
     3159#define RSCAN0RMDF040HL (RSCAN0.RMDF040.UINT8[R_IO_HL])
     3160#define RSCAN0RMDF040HH (RSCAN0.RMDF040.UINT8[R_IO_HH])
     3161#define RSCAN0RMDF140 (RSCAN0.RMDF140.UINT32)
     3162#define RSCAN0RMDF140L (RSCAN0.RMDF140.UINT16[R_IO_L])
     3163#define RSCAN0RMDF140LL (RSCAN0.RMDF140.UINT8[R_IO_LL])
     3164#define RSCAN0RMDF140LH (RSCAN0.RMDF140.UINT8[R_IO_LH])
     3165#define RSCAN0RMDF140H (RSCAN0.RMDF140.UINT16[R_IO_H])
     3166#define RSCAN0RMDF140HL (RSCAN0.RMDF140.UINT8[R_IO_HL])
     3167#define RSCAN0RMDF140HH (RSCAN0.RMDF140.UINT8[R_IO_HH])
     3168#define RSCAN0RMID41 (RSCAN0.RMID41.UINT32)
     3169#define RSCAN0RMID41L (RSCAN0.RMID41.UINT16[R_IO_L])
     3170#define RSCAN0RMID41LL (RSCAN0.RMID41.UINT8[R_IO_LL])
     3171#define RSCAN0RMID41LH (RSCAN0.RMID41.UINT8[R_IO_LH])
     3172#define RSCAN0RMID41H (RSCAN0.RMID41.UINT16[R_IO_H])
     3173#define RSCAN0RMID41HL (RSCAN0.RMID41.UINT8[R_IO_HL])
     3174#define RSCAN0RMID41HH (RSCAN0.RMID41.UINT8[R_IO_HH])
     3175#define RSCAN0RMPTR41 (RSCAN0.RMPTR41.UINT32)
     3176#define RSCAN0RMPTR41L (RSCAN0.RMPTR41.UINT16[R_IO_L])
     3177#define RSCAN0RMPTR41LL (RSCAN0.RMPTR41.UINT8[R_IO_LL])
     3178#define RSCAN0RMPTR41LH (RSCAN0.RMPTR41.UINT8[R_IO_LH])
     3179#define RSCAN0RMPTR41H (RSCAN0.RMPTR41.UINT16[R_IO_H])
     3180#define RSCAN0RMPTR41HL (RSCAN0.RMPTR41.UINT8[R_IO_HL])
     3181#define RSCAN0RMPTR41HH (RSCAN0.RMPTR41.UINT8[R_IO_HH])
     3182#define RSCAN0RMDF041 (RSCAN0.RMDF041.UINT32)
     3183#define RSCAN0RMDF041L (RSCAN0.RMDF041.UINT16[R_IO_L])
     3184#define RSCAN0RMDF041LL (RSCAN0.RMDF041.UINT8[R_IO_LL])
     3185#define RSCAN0RMDF041LH (RSCAN0.RMDF041.UINT8[R_IO_LH])
     3186#define RSCAN0RMDF041H (RSCAN0.RMDF041.UINT16[R_IO_H])
     3187#define RSCAN0RMDF041HL (RSCAN0.RMDF041.UINT8[R_IO_HL])
     3188#define RSCAN0RMDF041HH (RSCAN0.RMDF041.UINT8[R_IO_HH])
     3189#define RSCAN0RMDF141 (RSCAN0.RMDF141.UINT32)
     3190#define RSCAN0RMDF141L (RSCAN0.RMDF141.UINT16[R_IO_L])
     3191#define RSCAN0RMDF141LL (RSCAN0.RMDF141.UINT8[R_IO_LL])
     3192#define RSCAN0RMDF141LH (RSCAN0.RMDF141.UINT8[R_IO_LH])
     3193#define RSCAN0RMDF141H (RSCAN0.RMDF141.UINT16[R_IO_H])
     3194#define RSCAN0RMDF141HL (RSCAN0.RMDF141.UINT8[R_IO_HL])
     3195#define RSCAN0RMDF141HH (RSCAN0.RMDF141.UINT8[R_IO_HH])
     3196#define RSCAN0RMID42 (RSCAN0.RMID42.UINT32)
     3197#define RSCAN0RMID42L (RSCAN0.RMID42.UINT16[R_IO_L])
     3198#define RSCAN0RMID42LL (RSCAN0.RMID42.UINT8[R_IO_LL])
     3199#define RSCAN0RMID42LH (RSCAN0.RMID42.UINT8[R_IO_LH])
     3200#define RSCAN0RMID42H (RSCAN0.RMID42.UINT16[R_IO_H])
     3201#define RSCAN0RMID42HL (RSCAN0.RMID42.UINT8[R_IO_HL])
     3202#define RSCAN0RMID42HH (RSCAN0.RMID42.UINT8[R_IO_HH])
     3203#define RSCAN0RMPTR42 (RSCAN0.RMPTR42.UINT32)
     3204#define RSCAN0RMPTR42L (RSCAN0.RMPTR42.UINT16[R_IO_L])
     3205#define RSCAN0RMPTR42LL (RSCAN0.RMPTR42.UINT8[R_IO_LL])
     3206#define RSCAN0RMPTR42LH (RSCAN0.RMPTR42.UINT8[R_IO_LH])
     3207#define RSCAN0RMPTR42H (RSCAN0.RMPTR42.UINT16[R_IO_H])
     3208#define RSCAN0RMPTR42HL (RSCAN0.RMPTR42.UINT8[R_IO_HL])
     3209#define RSCAN0RMPTR42HH (RSCAN0.RMPTR42.UINT8[R_IO_HH])
     3210#define RSCAN0RMDF042 (RSCAN0.RMDF042.UINT32)
     3211#define RSCAN0RMDF042L (RSCAN0.RMDF042.UINT16[R_IO_L])
     3212#define RSCAN0RMDF042LL (RSCAN0.RMDF042.UINT8[R_IO_LL])
     3213#define RSCAN0RMDF042LH (RSCAN0.RMDF042.UINT8[R_IO_LH])
     3214#define RSCAN0RMDF042H (RSCAN0.RMDF042.UINT16[R_IO_H])
     3215#define RSCAN0RMDF042HL (RSCAN0.RMDF042.UINT8[R_IO_HL])
     3216#define RSCAN0RMDF042HH (RSCAN0.RMDF042.UINT8[R_IO_HH])
     3217#define RSCAN0RMDF142 (RSCAN0.RMDF142.UINT32)
     3218#define RSCAN0RMDF142L (RSCAN0.RMDF142.UINT16[R_IO_L])
     3219#define RSCAN0RMDF142LL (RSCAN0.RMDF142.UINT8[R_IO_LL])
     3220#define RSCAN0RMDF142LH (RSCAN0.RMDF142.UINT8[R_IO_LH])
     3221#define RSCAN0RMDF142H (RSCAN0.RMDF142.UINT16[R_IO_H])
     3222#define RSCAN0RMDF142HL (RSCAN0.RMDF142.UINT8[R_IO_HL])
     3223#define RSCAN0RMDF142HH (RSCAN0.RMDF142.UINT8[R_IO_HH])
     3224#define RSCAN0RMID43 (RSCAN0.RMID43.UINT32)
     3225#define RSCAN0RMID43L (RSCAN0.RMID43.UINT16[R_IO_L])
     3226#define RSCAN0RMID43LL (RSCAN0.RMID43.UINT8[R_IO_LL])
     3227#define RSCAN0RMID43LH (RSCAN0.RMID43.UINT8[R_IO_LH])
     3228#define RSCAN0RMID43H (RSCAN0.RMID43.UINT16[R_IO_H])
     3229#define RSCAN0RMID43HL (RSCAN0.RMID43.UINT8[R_IO_HL])
     3230#define RSCAN0RMID43HH (RSCAN0.RMID43.UINT8[R_IO_HH])
     3231#define RSCAN0RMPTR43 (RSCAN0.RMPTR43.UINT32)
     3232#define RSCAN0RMPTR43L (RSCAN0.RMPTR43.UINT16[R_IO_L])
     3233#define RSCAN0RMPTR43LL (RSCAN0.RMPTR43.UINT8[R_IO_LL])
     3234#define RSCAN0RMPTR43LH (RSCAN0.RMPTR43.UINT8[R_IO_LH])
     3235#define RSCAN0RMPTR43H (RSCAN0.RMPTR43.UINT16[R_IO_H])
     3236#define RSCAN0RMPTR43HL (RSCAN0.RMPTR43.UINT8[R_IO_HL])
     3237#define RSCAN0RMPTR43HH (RSCAN0.RMPTR43.UINT8[R_IO_HH])
     3238#define RSCAN0RMDF043 (RSCAN0.RMDF043.UINT32)
     3239#define RSCAN0RMDF043L (RSCAN0.RMDF043.UINT16[R_IO_L])
     3240#define RSCAN0RMDF043LL (RSCAN0.RMDF043.UINT8[R_IO_LL])
     3241#define RSCAN0RMDF043LH (RSCAN0.RMDF043.UINT8[R_IO_LH])
     3242#define RSCAN0RMDF043H (RSCAN0.RMDF043.UINT16[R_IO_H])
     3243#define RSCAN0RMDF043HL (RSCAN0.RMDF043.UINT8[R_IO_HL])
     3244#define RSCAN0RMDF043HH (RSCAN0.RMDF043.UINT8[R_IO_HH])
     3245#define RSCAN0RMDF143 (RSCAN0.RMDF143.UINT32)
     3246#define RSCAN0RMDF143L (RSCAN0.RMDF143.UINT16[R_IO_L])
     3247#define RSCAN0RMDF143LL (RSCAN0.RMDF143.UINT8[R_IO_LL])
     3248#define RSCAN0RMDF143LH (RSCAN0.RMDF143.UINT8[R_IO_LH])
     3249#define RSCAN0RMDF143H (RSCAN0.RMDF143.UINT16[R_IO_H])
     3250#define RSCAN0RMDF143HL (RSCAN0.RMDF143.UINT8[R_IO_HL])
     3251#define RSCAN0RMDF143HH (RSCAN0.RMDF143.UINT8[R_IO_HH])
     3252#define RSCAN0RMID44 (RSCAN0.RMID44.UINT32)
     3253#define RSCAN0RMID44L (RSCAN0.RMID44.UINT16[R_IO_L])
     3254#define RSCAN0RMID44LL (RSCAN0.RMID44.UINT8[R_IO_LL])
     3255#define RSCAN0RMID44LH (RSCAN0.RMID44.UINT8[R_IO_LH])
     3256#define RSCAN0RMID44H (RSCAN0.RMID44.UINT16[R_IO_H])
     3257#define RSCAN0RMID44HL (RSCAN0.RMID44.UINT8[R_IO_HL])
     3258#define RSCAN0RMID44HH (RSCAN0.RMID44.UINT8[R_IO_HH])
     3259#define RSCAN0RMPTR44 (RSCAN0.RMPTR44.UINT32)
     3260#define RSCAN0RMPTR44L (RSCAN0.RMPTR44.UINT16[R_IO_L])
     3261#define RSCAN0RMPTR44LL (RSCAN0.RMPTR44.UINT8[R_IO_LL])
     3262#define RSCAN0RMPTR44LH (RSCAN0.RMPTR44.UINT8[R_IO_LH])
     3263#define RSCAN0RMPTR44H (RSCAN0.RMPTR44.UINT16[R_IO_H])
     3264#define RSCAN0RMPTR44HL (RSCAN0.RMPTR44.UINT8[R_IO_HL])
     3265#define RSCAN0RMPTR44HH (RSCAN0.RMPTR44.UINT8[R_IO_HH])
     3266#define RSCAN0RMDF044 (RSCAN0.RMDF044.UINT32)
     3267#define RSCAN0RMDF044L (RSCAN0.RMDF044.UINT16[R_IO_L])
     3268#define RSCAN0RMDF044LL (RSCAN0.RMDF044.UINT8[R_IO_LL])
     3269#define RSCAN0RMDF044LH (RSCAN0.RMDF044.UINT8[R_IO_LH])
     3270#define RSCAN0RMDF044H (RSCAN0.RMDF044.UINT16[R_IO_H])
     3271#define RSCAN0RMDF044HL (RSCAN0.RMDF044.UINT8[R_IO_HL])
     3272#define RSCAN0RMDF044HH (RSCAN0.RMDF044.UINT8[R_IO_HH])
     3273#define RSCAN0RMDF144 (RSCAN0.RMDF144.UINT32)
     3274#define RSCAN0RMDF144L (RSCAN0.RMDF144.UINT16[R_IO_L])
     3275#define RSCAN0RMDF144LL (RSCAN0.RMDF144.UINT8[R_IO_LL])
     3276#define RSCAN0RMDF144LH (RSCAN0.RMDF144.UINT8[R_IO_LH])
     3277#define RSCAN0RMDF144H (RSCAN0.RMDF144.UINT16[R_IO_H])
     3278#define RSCAN0RMDF144HL (RSCAN0.RMDF144.UINT8[R_IO_HL])
     3279#define RSCAN0RMDF144HH (RSCAN0.RMDF144.UINT8[R_IO_HH])
     3280#define RSCAN0RMID45 (RSCAN0.RMID45.UINT32)
     3281#define RSCAN0RMID45L (RSCAN0.RMID45.UINT16[R_IO_L])
     3282#define RSCAN0RMID45LL (RSCAN0.RMID45.UINT8[R_IO_LL])
     3283#define RSCAN0RMID45LH (RSCAN0.RMID45.UINT8[R_IO_LH])
     3284#define RSCAN0RMID45H (RSCAN0.RMID45.UINT16[R_IO_H])
     3285#define RSCAN0RMID45HL (RSCAN0.RMID45.UINT8[R_IO_HL])
     3286#define RSCAN0RMID45HH (RSCAN0.RMID45.UINT8[R_IO_HH])
     3287#define RSCAN0RMPTR45 (RSCAN0.RMPTR45.UINT32)
     3288#define RSCAN0RMPTR45L (RSCAN0.RMPTR45.UINT16[R_IO_L])
     3289#define RSCAN0RMPTR45LL (RSCAN0.RMPTR45.UINT8[R_IO_LL])
     3290#define RSCAN0RMPTR45LH (RSCAN0.RMPTR45.UINT8[R_IO_LH])
     3291#define RSCAN0RMPTR45H (RSCAN0.RMPTR45.UINT16[R_IO_H])
     3292#define RSCAN0RMPTR45HL (RSCAN0.RMPTR45.UINT8[R_IO_HL])
     3293#define RSCAN0RMPTR45HH (RSCAN0.RMPTR45.UINT8[R_IO_HH])
     3294#define RSCAN0RMDF045 (RSCAN0.RMDF045.UINT32)
     3295#define RSCAN0RMDF045L (RSCAN0.RMDF045.UINT16[R_IO_L])
     3296#define RSCAN0RMDF045LL (RSCAN0.RMDF045.UINT8[R_IO_LL])
     3297#define RSCAN0RMDF045LH (RSCAN0.RMDF045.UINT8[R_IO_LH])
     3298#define RSCAN0RMDF045H (RSCAN0.RMDF045.UINT16[R_IO_H])
     3299#define RSCAN0RMDF045HL (RSCAN0.RMDF045.UINT8[R_IO_HL])
     3300#define RSCAN0RMDF045HH (RSCAN0.RMDF045.UINT8[R_IO_HH])
     3301#define RSCAN0RMDF145 (RSCAN0.RMDF145.UINT32)
     3302#define RSCAN0RMDF145L (RSCAN0.RMDF145.UINT16[R_IO_L])
     3303#define RSCAN0RMDF145LL (RSCAN0.RMDF145.UINT8[R_IO_LL])
     3304#define RSCAN0RMDF145LH (RSCAN0.RMDF145.UINT8[R_IO_LH])
     3305#define RSCAN0RMDF145H (RSCAN0.RMDF145.UINT16[R_IO_H])
     3306#define RSCAN0RMDF145HL (RSCAN0.RMDF145.UINT8[R_IO_HL])
     3307#define RSCAN0RMDF145HH (RSCAN0.RMDF145.UINT8[R_IO_HH])
     3308#define RSCAN0RMID46 (RSCAN0.RMID46.UINT32)
     3309#define RSCAN0RMID46L (RSCAN0.RMID46.UINT16[R_IO_L])
     3310#define RSCAN0RMID46LL (RSCAN0.RMID46.UINT8[R_IO_LL])
     3311#define RSCAN0RMID46LH (RSCAN0.RMID46.UINT8[R_IO_LH])
     3312#define RSCAN0RMID46H (RSCAN0.RMID46.UINT16[R_IO_H])
     3313#define RSCAN0RMID46HL (RSCAN0.RMID46.UINT8[R_IO_HL])
     3314#define RSCAN0RMID46HH (RSCAN0.RMID46.UINT8[R_IO_HH])
     3315#define RSCAN0RMPTR46 (RSCAN0.RMPTR46.UINT32)
     3316#define RSCAN0RMPTR46L (RSCAN0.RMPTR46.UINT16[R_IO_L])
     3317#define RSCAN0RMPTR46LL (RSCAN0.RMPTR46.UINT8[R_IO_LL])
     3318#define RSCAN0RMPTR46LH (RSCAN0.RMPTR46.UINT8[R_IO_LH])
     3319#define RSCAN0RMPTR46H (RSCAN0.RMPTR46.UINT16[R_IO_H])
     3320#define RSCAN0RMPTR46HL (RSCAN0.RMPTR46.UINT8[R_IO_HL])
     3321#define RSCAN0RMPTR46HH (RSCAN0.RMPTR46.UINT8[R_IO_HH])
     3322#define RSCAN0RMDF046 (RSCAN0.RMDF046.UINT32)
     3323#define RSCAN0RMDF046L (RSCAN0.RMDF046.UINT16[R_IO_L])
     3324#define RSCAN0RMDF046LL (RSCAN0.RMDF046.UINT8[R_IO_LL])
     3325#define RSCAN0RMDF046LH (RSCAN0.RMDF046.UINT8[R_IO_LH])
     3326#define RSCAN0RMDF046H (RSCAN0.RMDF046.UINT16[R_IO_H])
     3327#define RSCAN0RMDF046HL (RSCAN0.RMDF046.UINT8[R_IO_HL])
     3328#define RSCAN0RMDF046HH (RSCAN0.RMDF046.UINT8[R_IO_HH])
     3329#define RSCAN0RMDF146 (RSCAN0.RMDF146.UINT32)
     3330#define RSCAN0RMDF146L (RSCAN0.RMDF146.UINT16[R_IO_L])
     3331#define RSCAN0RMDF146LL (RSCAN0.RMDF146.UINT8[R_IO_LL])
     3332#define RSCAN0RMDF146LH (RSCAN0.RMDF146.UINT8[R_IO_LH])
     3333#define RSCAN0RMDF146H (RSCAN0.RMDF146.UINT16[R_IO_H])
     3334#define RSCAN0RMDF146HL (RSCAN0.RMDF146.UINT8[R_IO_HL])
     3335#define RSCAN0RMDF146HH (RSCAN0.RMDF146.UINT8[R_IO_HH])
     3336#define RSCAN0RMID47 (RSCAN0.RMID47.UINT32)
     3337#define RSCAN0RMID47L (RSCAN0.RMID47.UINT16[R_IO_L])
     3338#define RSCAN0RMID47LL (RSCAN0.RMID47.UINT8[R_IO_LL])
     3339#define RSCAN0RMID47LH (RSCAN0.RMID47.UINT8[R_IO_LH])
     3340#define RSCAN0RMID47H (RSCAN0.RMID47.UINT16[R_IO_H])
     3341#define RSCAN0RMID47HL (RSCAN0.RMID47.UINT8[R_IO_HL])
     3342#define RSCAN0RMID47HH (RSCAN0.RMID47.UINT8[R_IO_HH])
     3343#define RSCAN0RMPTR47 (RSCAN0.RMPTR47.UINT32)
     3344#define RSCAN0RMPTR47L (RSCAN0.RMPTR47.UINT16[R_IO_L])
     3345#define RSCAN0RMPTR47LL (RSCAN0.RMPTR47.UINT8[R_IO_LL])
     3346#define RSCAN0RMPTR47LH (RSCAN0.RMPTR47.UINT8[R_IO_LH])
     3347#define RSCAN0RMPTR47H (RSCAN0.RMPTR47.UINT16[R_IO_H])
     3348#define RSCAN0RMPTR47HL (RSCAN0.RMPTR47.UINT8[R_IO_HL])
     3349#define RSCAN0RMPTR47HH (RSCAN0.RMPTR47.UINT8[R_IO_HH])
     3350#define RSCAN0RMDF047 (RSCAN0.RMDF047.UINT32)
     3351#define RSCAN0RMDF047L (RSCAN0.RMDF047.UINT16[R_IO_L])
     3352#define RSCAN0RMDF047LL (RSCAN0.RMDF047.UINT8[R_IO_LL])
     3353#define RSCAN0RMDF047LH (RSCAN0.RMDF047.UINT8[R_IO_LH])
     3354#define RSCAN0RMDF047H (RSCAN0.RMDF047.UINT16[R_IO_H])
     3355#define RSCAN0RMDF047HL (RSCAN0.RMDF047.UINT8[R_IO_HL])
     3356#define RSCAN0RMDF047HH (RSCAN0.RMDF047.UINT8[R_IO_HH])
     3357#define RSCAN0RMDF147 (RSCAN0.RMDF147.UINT32)
     3358#define RSCAN0RMDF147L (RSCAN0.RMDF147.UINT16[R_IO_L])
     3359#define RSCAN0RMDF147LL (RSCAN0.RMDF147.UINT8[R_IO_LL])
     3360#define RSCAN0RMDF147LH (RSCAN0.RMDF147.UINT8[R_IO_LH])
     3361#define RSCAN0RMDF147H (RSCAN0.RMDF147.UINT16[R_IO_H])
     3362#define RSCAN0RMDF147HL (RSCAN0.RMDF147.UINT8[R_IO_HL])
     3363#define RSCAN0RMDF147HH (RSCAN0.RMDF147.UINT8[R_IO_HH])
     3364#define RSCAN0RMID48 (RSCAN0.RMID48.UINT32)
     3365#define RSCAN0RMID48L (RSCAN0.RMID48.UINT16[R_IO_L])
     3366#define RSCAN0RMID48LL (RSCAN0.RMID48.UINT8[R_IO_LL])
     3367#define RSCAN0RMID48LH (RSCAN0.RMID48.UINT8[R_IO_LH])
     3368#define RSCAN0RMID48H (RSCAN0.RMID48.UINT16[R_IO_H])
     3369#define RSCAN0RMID48HL (RSCAN0.RMID48.UINT8[R_IO_HL])
     3370#define RSCAN0RMID48HH (RSCAN0.RMID48.UINT8[R_IO_HH])
     3371#define RSCAN0RMPTR48 (RSCAN0.RMPTR48.UINT32)
     3372#define RSCAN0RMPTR48L (RSCAN0.RMPTR48.UINT16[R_IO_L])
     3373#define RSCAN0RMPTR48LL (RSCAN0.RMPTR48.UINT8[R_IO_LL])
     3374#define RSCAN0RMPTR48LH (RSCAN0.RMPTR48.UINT8[R_IO_LH])
     3375#define RSCAN0RMPTR48H (RSCAN0.RMPTR48.UINT16[R_IO_H])
     3376#define RSCAN0RMPTR48HL (RSCAN0.RMPTR48.UINT8[R_IO_HL])
     3377#define RSCAN0RMPTR48HH (RSCAN0.RMPTR48.UINT8[R_IO_HH])
     3378#define RSCAN0RMDF048 (RSCAN0.RMDF048.UINT32)
     3379#define RSCAN0RMDF048L (RSCAN0.RMDF048.UINT16[R_IO_L])
     3380#define RSCAN0RMDF048LL (RSCAN0.RMDF048.UINT8[R_IO_LL])
     3381#define RSCAN0RMDF048LH (RSCAN0.RMDF048.UINT8[R_IO_LH])
     3382#define RSCAN0RMDF048H (RSCAN0.RMDF048.UINT16[R_IO_H])
     3383#define RSCAN0RMDF048HL (RSCAN0.RMDF048.UINT8[R_IO_HL])
     3384#define RSCAN0RMDF048HH (RSCAN0.RMDF048.UINT8[R_IO_HH])
     3385#define RSCAN0RMDF148 (RSCAN0.RMDF148.UINT32)
     3386#define RSCAN0RMDF148L (RSCAN0.RMDF148.UINT16[R_IO_L])
     3387#define RSCAN0RMDF148LL (RSCAN0.RMDF148.UINT8[R_IO_LL])
     3388#define RSCAN0RMDF148LH (RSCAN0.RMDF148.UINT8[R_IO_LH])
     3389#define RSCAN0RMDF148H (RSCAN0.RMDF148.UINT16[R_IO_H])
     3390#define RSCAN0RMDF148HL (RSCAN0.RMDF148.UINT8[R_IO_HL])
     3391#define RSCAN0RMDF148HH (RSCAN0.RMDF148.UINT8[R_IO_HH])
     3392#define RSCAN0RMID49 (RSCAN0.RMID49.UINT32)
     3393#define RSCAN0RMID49L (RSCAN0.RMID49.UINT16[R_IO_L])
     3394#define RSCAN0RMID49LL (RSCAN0.RMID49.UINT8[R_IO_LL])
     3395#define RSCAN0RMID49LH (RSCAN0.RMID49.UINT8[R_IO_LH])
     3396#define RSCAN0RMID49H (RSCAN0.RMID49.UINT16[R_IO_H])
     3397#define RSCAN0RMID49HL (RSCAN0.RMID49.UINT8[R_IO_HL])
     3398#define RSCAN0RMID49HH (RSCAN0.RMID49.UINT8[R_IO_HH])
     3399#define RSCAN0RMPTR49 (RSCAN0.RMPTR49.UINT32)
     3400#define RSCAN0RMPTR49L (RSCAN0.RMPTR49.UINT16[R_IO_L])
     3401#define RSCAN0RMPTR49LL (RSCAN0.RMPTR49.UINT8[R_IO_LL])
     3402#define RSCAN0RMPTR49LH (RSCAN0.RMPTR49.UINT8[R_IO_LH])
     3403#define RSCAN0RMPTR49H (RSCAN0.RMPTR49.UINT16[R_IO_H])
     3404#define RSCAN0RMPTR49HL (RSCAN0.RMPTR49.UINT8[R_IO_HL])
     3405#define RSCAN0RMPTR49HH (RSCAN0.RMPTR49.UINT8[R_IO_HH])
     3406#define RSCAN0RMDF049 (RSCAN0.RMDF049.UINT32)
     3407#define RSCAN0RMDF049L (RSCAN0.RMDF049.UINT16[R_IO_L])
     3408#define RSCAN0RMDF049LL (RSCAN0.RMDF049.UINT8[R_IO_LL])
     3409#define RSCAN0RMDF049LH (RSCAN0.RMDF049.UINT8[R_IO_LH])
     3410#define RSCAN0RMDF049H (RSCAN0.RMDF049.UINT16[R_IO_H])
     3411#define RSCAN0RMDF049HL (RSCAN0.RMDF049.UINT8[R_IO_HL])
     3412#define RSCAN0RMDF049HH (RSCAN0.RMDF049.UINT8[R_IO_HH])
     3413#define RSCAN0RMDF149 (RSCAN0.RMDF149.UINT32)
     3414#define RSCAN0RMDF149L (RSCAN0.RMDF149.UINT16[R_IO_L])
     3415#define RSCAN0RMDF149LL (RSCAN0.RMDF149.UINT8[R_IO_LL])
     3416#define RSCAN0RMDF149LH (RSCAN0.RMDF149.UINT8[R_IO_LH])
     3417#define RSCAN0RMDF149H (RSCAN0.RMDF149.UINT16[R_IO_H])
     3418#define RSCAN0RMDF149HL (RSCAN0.RMDF149.UINT8[R_IO_HL])
     3419#define RSCAN0RMDF149HH (RSCAN0.RMDF149.UINT8[R_IO_HH])
     3420#define RSCAN0RMID50 (RSCAN0.RMID50.UINT32)
     3421#define RSCAN0RMID50L (RSCAN0.RMID50.UINT16[R_IO_L])
     3422#define RSCAN0RMID50LL (RSCAN0.RMID50.UINT8[R_IO_LL])
     3423#define RSCAN0RMID50LH (RSCAN0.RMID50.UINT8[R_IO_LH])
     3424#define RSCAN0RMID50H (RSCAN0.RMID50.UINT16[R_IO_H])
     3425#define RSCAN0RMID50HL (RSCAN0.RMID50.UINT8[R_IO_HL])
     3426#define RSCAN0RMID50HH (RSCAN0.RMID50.UINT8[R_IO_HH])
     3427#define RSCAN0RMPTR50 (RSCAN0.RMPTR50.UINT32)
     3428#define RSCAN0RMPTR50L (RSCAN0.RMPTR50.UINT16[R_IO_L])
     3429#define RSCAN0RMPTR50LL (RSCAN0.RMPTR50.UINT8[R_IO_LL])
     3430#define RSCAN0RMPTR50LH (RSCAN0.RMPTR50.UINT8[R_IO_LH])
     3431#define RSCAN0RMPTR50H (RSCAN0.RMPTR50.UINT16[R_IO_H])
     3432#define RSCAN0RMPTR50HL (RSCAN0.RMPTR50.UINT8[R_IO_HL])
     3433#define RSCAN0RMPTR50HH (RSCAN0.RMPTR50.UINT8[R_IO_HH])
     3434#define RSCAN0RMDF050 (RSCAN0.RMDF050.UINT32)
     3435#define RSCAN0RMDF050L (RSCAN0.RMDF050.UINT16[R_IO_L])
     3436#define RSCAN0RMDF050LL (RSCAN0.RMDF050.UINT8[R_IO_LL])
     3437#define RSCAN0RMDF050LH (RSCAN0.RMDF050.UINT8[R_IO_LH])
     3438#define RSCAN0RMDF050H (RSCAN0.RMDF050.UINT16[R_IO_H])
     3439#define RSCAN0RMDF050HL (RSCAN0.RMDF050.UINT8[R_IO_HL])
     3440#define RSCAN0RMDF050HH (RSCAN0.RMDF050.UINT8[R_IO_HH])
     3441#define RSCAN0RMDF150 (RSCAN0.RMDF150.UINT32)
     3442#define RSCAN0RMDF150L (RSCAN0.RMDF150.UINT16[R_IO_L])
     3443#define RSCAN0RMDF150LL (RSCAN0.RMDF150.UINT8[R_IO_LL])
     3444#define RSCAN0RMDF150LH (RSCAN0.RMDF150.UINT8[R_IO_LH])
     3445#define RSCAN0RMDF150H (RSCAN0.RMDF150.UINT16[R_IO_H])
     3446#define RSCAN0RMDF150HL (RSCAN0.RMDF150.UINT8[R_IO_HL])
     3447#define RSCAN0RMDF150HH (RSCAN0.RMDF150.UINT8[R_IO_HH])
     3448#define RSCAN0RMID51 (RSCAN0.RMID51.UINT32)
     3449#define RSCAN0RMID51L (RSCAN0.RMID51.UINT16[R_IO_L])
     3450#define RSCAN0RMID51LL (RSCAN0.RMID51.UINT8[R_IO_LL])
     3451#define RSCAN0RMID51LH (RSCAN0.RMID51.UINT8[R_IO_LH])
     3452#define RSCAN0RMID51H (RSCAN0.RMID51.UINT16[R_IO_H])
     3453#define RSCAN0RMID51HL (RSCAN0.RMID51.UINT8[R_IO_HL])
     3454#define RSCAN0RMID51HH (RSCAN0.RMID51.UINT8[R_IO_HH])
     3455#define RSCAN0RMPTR51 (RSCAN0.RMPTR51.UINT32)
     3456#define RSCAN0RMPTR51L (RSCAN0.RMPTR51.UINT16[R_IO_L])
     3457#define RSCAN0RMPTR51LL (RSCAN0.RMPTR51.UINT8[R_IO_LL])
     3458#define RSCAN0RMPTR51LH (RSCAN0.RMPTR51.UINT8[R_IO_LH])
     3459#define RSCAN0RMPTR51H (RSCAN0.RMPTR51.UINT16[R_IO_H])
     3460#define RSCAN0RMPTR51HL (RSCAN0.RMPTR51.UINT8[R_IO_HL])
     3461#define RSCAN0RMPTR51HH (RSCAN0.RMPTR51.UINT8[R_IO_HH])
     3462#define RSCAN0RMDF051 (RSCAN0.RMDF051.UINT32)
     3463#define RSCAN0RMDF051L (RSCAN0.RMDF051.UINT16[R_IO_L])
     3464#define RSCAN0RMDF051LL (RSCAN0.RMDF051.UINT8[R_IO_LL])
     3465#define RSCAN0RMDF051LH (RSCAN0.RMDF051.UINT8[R_IO_LH])
     3466#define RSCAN0RMDF051H (RSCAN0.RMDF051.UINT16[R_IO_H])
     3467#define RSCAN0RMDF051HL (RSCAN0.RMDF051.UINT8[R_IO_HL])
     3468#define RSCAN0RMDF051HH (RSCAN0.RMDF051.UINT8[R_IO_HH])
     3469#define RSCAN0RMDF151 (RSCAN0.RMDF151.UINT32)
     3470#define RSCAN0RMDF151L (RSCAN0.RMDF151.UINT16[R_IO_L])
     3471#define RSCAN0RMDF151LL (RSCAN0.RMDF151.UINT8[R_IO_LL])
     3472#define RSCAN0RMDF151LH (RSCAN0.RMDF151.UINT8[R_IO_LH])
     3473#define RSCAN0RMDF151H (RSCAN0.RMDF151.UINT16[R_IO_H])
     3474#define RSCAN0RMDF151HL (RSCAN0.RMDF151.UINT8[R_IO_HL])
     3475#define RSCAN0RMDF151HH (RSCAN0.RMDF151.UINT8[R_IO_HH])
     3476#define RSCAN0RMID52 (RSCAN0.RMID52.UINT32)
     3477#define RSCAN0RMID52L (RSCAN0.RMID52.UINT16[R_IO_L])
     3478#define RSCAN0RMID52LL (RSCAN0.RMID52.UINT8[R_IO_LL])
     3479#define RSCAN0RMID52LH (RSCAN0.RMID52.UINT8[R_IO_LH])
     3480#define RSCAN0RMID52H (RSCAN0.RMID52.UINT16[R_IO_H])
     3481#define RSCAN0RMID52HL (RSCAN0.RMID52.UINT8[R_IO_HL])
     3482#define RSCAN0RMID52HH (RSCAN0.RMID52.UINT8[R_IO_HH])
     3483#define RSCAN0RMPTR52 (RSCAN0.RMPTR52.UINT32)
     3484#define RSCAN0RMPTR52L (RSCAN0.RMPTR52.UINT16[R_IO_L])
     3485#define RSCAN0RMPTR52LL (RSCAN0.RMPTR52.UINT8[R_IO_LL])
     3486#define RSCAN0RMPTR52LH (RSCAN0.RMPTR52.UINT8[R_IO_LH])
     3487#define RSCAN0RMPTR52H (RSCAN0.RMPTR52.UINT16[R_IO_H])
     3488#define RSCAN0RMPTR52HL (RSCAN0.RMPTR52.UINT8[R_IO_HL])
     3489#define RSCAN0RMPTR52HH (RSCAN0.RMPTR52.UINT8[R_IO_HH])
     3490#define RSCAN0RMDF052 (RSCAN0.RMDF052.UINT32)
     3491#define RSCAN0RMDF052L (RSCAN0.RMDF052.UINT16[R_IO_L])
     3492#define RSCAN0RMDF052LL (RSCAN0.RMDF052.UINT8[R_IO_LL])
     3493#define RSCAN0RMDF052LH (RSCAN0.RMDF052.UINT8[R_IO_LH])
     3494#define RSCAN0RMDF052H (RSCAN0.RMDF052.UINT16[R_IO_H])
     3495#define RSCAN0RMDF052HL (RSCAN0.RMDF052.UINT8[R_IO_HL])
     3496#define RSCAN0RMDF052HH (RSCAN0.RMDF052.UINT8[R_IO_HH])
     3497#define RSCAN0RMDF152 (RSCAN0.RMDF152.UINT32)
     3498#define RSCAN0RMDF152L (RSCAN0.RMDF152.UINT16[R_IO_L])
     3499#define RSCAN0RMDF152LL (RSCAN0.RMDF152.UINT8[R_IO_LL])
     3500#define RSCAN0RMDF152LH (RSCAN0.RMDF152.UINT8[R_IO_LH])
     3501#define RSCAN0RMDF152H (RSCAN0.RMDF152.UINT16[R_IO_H])
     3502#define RSCAN0RMDF152HL (RSCAN0.RMDF152.UINT8[R_IO_HL])
     3503#define RSCAN0RMDF152HH (RSCAN0.RMDF152.UINT8[R_IO_HH])
     3504#define RSCAN0RMID53 (RSCAN0.RMID53.UINT32)
     3505#define RSCAN0RMID53L (RSCAN0.RMID53.UINT16[R_IO_L])
     3506#define RSCAN0RMID53LL (RSCAN0.RMID53.UINT8[R_IO_LL])
     3507#define RSCAN0RMID53LH (RSCAN0.RMID53.UINT8[R_IO_LH])
     3508#define RSCAN0RMID53H (RSCAN0.RMID53.UINT16[R_IO_H])
     3509#define RSCAN0RMID53HL (RSCAN0.RMID53.UINT8[R_IO_HL])
     3510#define RSCAN0RMID53HH (RSCAN0.RMID53.UINT8[R_IO_HH])
     3511#define RSCAN0RMPTR53 (RSCAN0.RMPTR53.UINT32)
     3512#define RSCAN0RMPTR53L (RSCAN0.RMPTR53.UINT16[R_IO_L])
     3513#define RSCAN0RMPTR53LL (RSCAN0.RMPTR53.UINT8[R_IO_LL])
     3514#define RSCAN0RMPTR53LH (RSCAN0.RMPTR53.UINT8[R_IO_LH])
     3515#define RSCAN0RMPTR53H (RSCAN0.RMPTR53.UINT16[R_IO_H])
     3516#define RSCAN0RMPTR53HL (RSCAN0.RMPTR53.UINT8[R_IO_HL])
     3517#define RSCAN0RMPTR53HH (RSCAN0.RMPTR53.UINT8[R_IO_HH])
     3518#define RSCAN0RMDF053 (RSCAN0.RMDF053.UINT32)
     3519#define RSCAN0RMDF053L (RSCAN0.RMDF053.UINT16[R_IO_L])
     3520#define RSCAN0RMDF053LL (RSCAN0.RMDF053.UINT8[R_IO_LL])
     3521#define RSCAN0RMDF053LH (RSCAN0.RMDF053.UINT8[R_IO_LH])
     3522#define RSCAN0RMDF053H (RSCAN0.RMDF053.UINT16[R_IO_H])
     3523#define RSCAN0RMDF053HL (RSCAN0.RMDF053.UINT8[R_IO_HL])
     3524#define RSCAN0RMDF053HH (RSCAN0.RMDF053.UINT8[R_IO_HH])
     3525#define RSCAN0RMDF153 (RSCAN0.RMDF153.UINT32)
     3526#define RSCAN0RMDF153L (RSCAN0.RMDF153.UINT16[R_IO_L])
     3527#define RSCAN0RMDF153LL (RSCAN0.RMDF153.UINT8[R_IO_LL])
     3528#define RSCAN0RMDF153LH (RSCAN0.RMDF153.UINT8[R_IO_LH])
     3529#define RSCAN0RMDF153H (RSCAN0.RMDF153.UINT16[R_IO_H])
     3530#define RSCAN0RMDF153HL (RSCAN0.RMDF153.UINT8[R_IO_HL])
     3531#define RSCAN0RMDF153HH (RSCAN0.RMDF153.UINT8[R_IO_HH])
     3532#define RSCAN0RMID54 (RSCAN0.RMID54.UINT32)
     3533#define RSCAN0RMID54L (RSCAN0.RMID54.UINT16[R_IO_L])
     3534#define RSCAN0RMID54LL (RSCAN0.RMID54.UINT8[R_IO_LL])
     3535#define RSCAN0RMID54LH (RSCAN0.RMID54.UINT8[R_IO_LH])
     3536#define RSCAN0RMID54H (RSCAN0.RMID54.UINT16[R_IO_H])
     3537#define RSCAN0RMID54HL (RSCAN0.RMID54.UINT8[R_IO_HL])
     3538#define RSCAN0RMID54HH (RSCAN0.RMID54.UINT8[R_IO_HH])
     3539#define RSCAN0RMPTR54 (RSCAN0.RMPTR54.UINT32)
     3540#define RSCAN0RMPTR54L (RSCAN0.RMPTR54.UINT16[R_IO_L])
     3541#define RSCAN0RMPTR54LL (RSCAN0.RMPTR54.UINT8[R_IO_LL])
     3542#define RSCAN0RMPTR54LH (RSCAN0.RMPTR54.UINT8[R_IO_LH])
     3543#define RSCAN0RMPTR54H (RSCAN0.RMPTR54.UINT16[R_IO_H])
     3544#define RSCAN0RMPTR54HL (RSCAN0.RMPTR54.UINT8[R_IO_HL])
     3545#define RSCAN0RMPTR54HH (RSCAN0.RMPTR54.UINT8[R_IO_HH])
     3546#define RSCAN0RMDF054 (RSCAN0.RMDF054.UINT32)
     3547#define RSCAN0RMDF054L (RSCAN0.RMDF054.UINT16[R_IO_L])
     3548#define RSCAN0RMDF054LL (RSCAN0.RMDF054.UINT8[R_IO_LL])
     3549#define RSCAN0RMDF054LH (RSCAN0.RMDF054.UINT8[R_IO_LH])
     3550#define RSCAN0RMDF054H (RSCAN0.RMDF054.UINT16[R_IO_H])
     3551#define RSCAN0RMDF054HL (RSCAN0.RMDF054.UINT8[R_IO_HL])
     3552#define RSCAN0RMDF054HH (RSCAN0.RMDF054.UINT8[R_IO_HH])
     3553#define RSCAN0RMDF154 (RSCAN0.RMDF154.UINT32)
     3554#define RSCAN0RMDF154L (RSCAN0.RMDF154.UINT16[R_IO_L])
     3555#define RSCAN0RMDF154LL (RSCAN0.RMDF154.UINT8[R_IO_LL])
     3556#define RSCAN0RMDF154LH (RSCAN0.RMDF154.UINT8[R_IO_LH])
     3557#define RSCAN0RMDF154H (RSCAN0.RMDF154.UINT16[R_IO_H])
     3558#define RSCAN0RMDF154HL (RSCAN0.RMDF154.UINT8[R_IO_HL])
     3559#define RSCAN0RMDF154HH (RSCAN0.RMDF154.UINT8[R_IO_HH])
     3560#define RSCAN0RMID55 (RSCAN0.RMID55.UINT32)
     3561#define RSCAN0RMID55L (RSCAN0.RMID55.UINT16[R_IO_L])
     3562#define RSCAN0RMID55LL (RSCAN0.RMID55.UINT8[R_IO_LL])
     3563#define RSCAN0RMID55LH (RSCAN0.RMID55.UINT8[R_IO_LH])
     3564#define RSCAN0RMID55H (RSCAN0.RMID55.UINT16[R_IO_H])
     3565#define RSCAN0RMID55HL (RSCAN0.RMID55.UINT8[R_IO_HL])
     3566#define RSCAN0RMID55HH (RSCAN0.RMID55.UINT8[R_IO_HH])
     3567#define RSCAN0RMPTR55 (RSCAN0.RMPTR55.UINT32)
     3568#define RSCAN0RMPTR55L (RSCAN0.RMPTR55.UINT16[R_IO_L])
     3569#define RSCAN0RMPTR55LL (RSCAN0.RMPTR55.UINT8[R_IO_LL])
     3570#define RSCAN0RMPTR55LH (RSCAN0.RMPTR55.UINT8[R_IO_LH])
     3571#define RSCAN0RMPTR55H (RSCAN0.RMPTR55.UINT16[R_IO_H])
     3572#define RSCAN0RMPTR55HL (RSCAN0.RMPTR55.UINT8[R_IO_HL])
     3573#define RSCAN0RMPTR55HH (RSCAN0.RMPTR55.UINT8[R_IO_HH])
     3574#define RSCAN0RMDF055 (RSCAN0.RMDF055.UINT32)
     3575#define RSCAN0RMDF055L (RSCAN0.RMDF055.UINT16[R_IO_L])
     3576#define RSCAN0RMDF055LL (RSCAN0.RMDF055.UINT8[R_IO_LL])
     3577#define RSCAN0RMDF055LH (RSCAN0.RMDF055.UINT8[R_IO_LH])
     3578#define RSCAN0RMDF055H (RSCAN0.RMDF055.UINT16[R_IO_H])
     3579#define RSCAN0RMDF055HL (RSCAN0.RMDF055.UINT8[R_IO_HL])
     3580#define RSCAN0RMDF055HH (RSCAN0.RMDF055.UINT8[R_IO_HH])
     3581#define RSCAN0RMDF155 (RSCAN0.RMDF155.UINT32)
     3582#define RSCAN0RMDF155L (RSCAN0.RMDF155.UINT16[R_IO_L])
     3583#define RSCAN0RMDF155LL (RSCAN0.RMDF155.UINT8[R_IO_LL])
     3584#define RSCAN0RMDF155LH (RSCAN0.RMDF155.UINT8[R_IO_LH])
     3585#define RSCAN0RMDF155H (RSCAN0.RMDF155.UINT16[R_IO_H])
     3586#define RSCAN0RMDF155HL (RSCAN0.RMDF155.UINT8[R_IO_HL])
     3587#define RSCAN0RMDF155HH (RSCAN0.RMDF155.UINT8[R_IO_HH])
     3588#define RSCAN0RMID56 (RSCAN0.RMID56.UINT32)
     3589#define RSCAN0RMID56L (RSCAN0.RMID56.UINT16[R_IO_L])
     3590#define RSCAN0RMID56LL (RSCAN0.RMID56.UINT8[R_IO_LL])
     3591#define RSCAN0RMID56LH (RSCAN0.RMID56.UINT8[R_IO_LH])
     3592#define RSCAN0RMID56H (RSCAN0.RMID56.UINT16[R_IO_H])
     3593#define RSCAN0RMID56HL (RSCAN0.RMID56.UINT8[R_IO_HL])
     3594#define RSCAN0RMID56HH (RSCAN0.RMID56.UINT8[R_IO_HH])
     3595#define RSCAN0RMPTR56 (RSCAN0.RMPTR56.UINT32)
     3596#define RSCAN0RMPTR56L (RSCAN0.RMPTR56.UINT16[R_IO_L])
     3597#define RSCAN0RMPTR56LL (RSCAN0.RMPTR56.UINT8[R_IO_LL])
     3598#define RSCAN0RMPTR56LH (RSCAN0.RMPTR56.UINT8[R_IO_LH])
     3599#define RSCAN0RMPTR56H (RSCAN0.RMPTR56.UINT16[R_IO_H])
     3600#define RSCAN0RMPTR56HL (RSCAN0.RMPTR56.UINT8[R_IO_HL])
     3601#define RSCAN0RMPTR56HH (RSCAN0.RMPTR56.UINT8[R_IO_HH])
     3602#define RSCAN0RMDF056 (RSCAN0.RMDF056.UINT32)
     3603#define RSCAN0RMDF056L (RSCAN0.RMDF056.UINT16[R_IO_L])
     3604#define RSCAN0RMDF056LL (RSCAN0.RMDF056.UINT8[R_IO_LL])
     3605#define RSCAN0RMDF056LH (RSCAN0.RMDF056.UINT8[R_IO_LH])
     3606#define RSCAN0RMDF056H (RSCAN0.RMDF056.UINT16[R_IO_H])
     3607#define RSCAN0RMDF056HL (RSCAN0.RMDF056.UINT8[R_IO_HL])
     3608#define RSCAN0RMDF056HH (RSCAN0.RMDF056.UINT8[R_IO_HH])
     3609#define RSCAN0RMDF156 (RSCAN0.RMDF156.UINT32)
     3610#define RSCAN0RMDF156L (RSCAN0.RMDF156.UINT16[R_IO_L])
     3611#define RSCAN0RMDF156LL (RSCAN0.RMDF156.UINT8[R_IO_LL])
     3612#define RSCAN0RMDF156LH (RSCAN0.RMDF156.UINT8[R_IO_LH])
     3613#define RSCAN0RMDF156H (RSCAN0.RMDF156.UINT16[R_IO_H])
     3614#define RSCAN0RMDF156HL (RSCAN0.RMDF156.UINT8[R_IO_HL])
     3615#define RSCAN0RMDF156HH (RSCAN0.RMDF156.UINT8[R_IO_HH])
     3616#define RSCAN0RMID57 (RSCAN0.RMID57.UINT32)
     3617#define RSCAN0RMID57L (RSCAN0.RMID57.UINT16[R_IO_L])
     3618#define RSCAN0RMID57LL (RSCAN0.RMID57.UINT8[R_IO_LL])
     3619#define RSCAN0RMID57LH (RSCAN0.RMID57.UINT8[R_IO_LH])
     3620#define RSCAN0RMID57H (RSCAN0.RMID57.UINT16[R_IO_H])
     3621#define RSCAN0RMID57HL (RSCAN0.RMID57.UINT8[R_IO_HL])
     3622#define RSCAN0RMID57HH (RSCAN0.RMID57.UINT8[R_IO_HH])
     3623#define RSCAN0RMPTR57 (RSCAN0.RMPTR57.UINT32)
     3624#define RSCAN0RMPTR57L (RSCAN0.RMPTR57.UINT16[R_IO_L])
     3625#define RSCAN0RMPTR57LL (RSCAN0.RMPTR57.UINT8[R_IO_LL])
     3626#define RSCAN0RMPTR57LH (RSCAN0.RMPTR57.UINT8[R_IO_LH])
     3627#define RSCAN0RMPTR57H (RSCAN0.RMPTR57.UINT16[R_IO_H])
     3628#define RSCAN0RMPTR57HL (RSCAN0.RMPTR57.UINT8[R_IO_HL])
     3629#define RSCAN0RMPTR57HH (RSCAN0.RMPTR57.UINT8[R_IO_HH])
     3630#define RSCAN0RMDF057 (RSCAN0.RMDF057.UINT32)
     3631#define RSCAN0RMDF057L (RSCAN0.RMDF057.UINT16[R_IO_L])
     3632#define RSCAN0RMDF057LL (RSCAN0.RMDF057.UINT8[R_IO_LL])
     3633#define RSCAN0RMDF057LH (RSCAN0.RMDF057.UINT8[R_IO_LH])
     3634#define RSCAN0RMDF057H (RSCAN0.RMDF057.UINT16[R_IO_H])
     3635#define RSCAN0RMDF057HL (RSCAN0.RMDF057.UINT8[R_IO_HL])
     3636#define RSCAN0RMDF057HH (RSCAN0.RMDF057.UINT8[R_IO_HH])
     3637#define RSCAN0RMDF157 (RSCAN0.RMDF157.UINT32)
     3638#define RSCAN0RMDF157L (RSCAN0.RMDF157.UINT16[R_IO_L])
     3639#define RSCAN0RMDF157LL (RSCAN0.RMDF157.UINT8[R_IO_LL])
     3640#define RSCAN0RMDF157LH (RSCAN0.RMDF157.UINT8[R_IO_LH])
     3641#define RSCAN0RMDF157H (RSCAN0.RMDF157.UINT16[R_IO_H])
     3642#define RSCAN0RMDF157HL (RSCAN0.RMDF157.UINT8[R_IO_HL])
     3643#define RSCAN0RMDF157HH (RSCAN0.RMDF157.UINT8[R_IO_HH])
     3644#define RSCAN0RMID58 (RSCAN0.RMID58.UINT32)
     3645#define RSCAN0RMID58L (RSCAN0.RMID58.UINT16[R_IO_L])
     3646#define RSCAN0RMID58LL (RSCAN0.RMID58.UINT8[R_IO_LL])
     3647#define RSCAN0RMID58LH (RSCAN0.RMID58.UINT8[R_IO_LH])
     3648#define RSCAN0RMID58H (RSCAN0.RMID58.UINT16[R_IO_H])
     3649#define RSCAN0RMID58HL (RSCAN0.RMID58.UINT8[R_IO_HL])
     3650#define RSCAN0RMID58HH (RSCAN0.RMID58.UINT8[R_IO_HH])
     3651#define RSCAN0RMPTR58 (RSCAN0.RMPTR58.UINT32)
     3652#define RSCAN0RMPTR58L (RSCAN0.RMPTR58.UINT16[R_IO_L])
     3653#define RSCAN0RMPTR58LL (RSCAN0.RMPTR58.UINT8[R_IO_LL])
     3654#define RSCAN0RMPTR58LH (RSCAN0.RMPTR58.UINT8[R_IO_LH])
     3655#define RSCAN0RMPTR58H (RSCAN0.RMPTR58.UINT16[R_IO_H])
     3656#define RSCAN0RMPTR58HL (RSCAN0.RMPTR58.UINT8[R_IO_HL])
     3657#define RSCAN0RMPTR58HH (RSCAN0.RMPTR58.UINT8[R_IO_HH])
     3658#define RSCAN0RMDF058 (RSCAN0.RMDF058.UINT32)
     3659#define RSCAN0RMDF058L (RSCAN0.RMDF058.UINT16[R_IO_L])
     3660#define RSCAN0RMDF058LL (RSCAN0.RMDF058.UINT8[R_IO_LL])
     3661#define RSCAN0RMDF058LH (RSCAN0.RMDF058.UINT8[R_IO_LH])
     3662#define RSCAN0RMDF058H (RSCAN0.RMDF058.UINT16[R_IO_H])
     3663#define RSCAN0RMDF058HL (RSCAN0.RMDF058.UINT8[R_IO_HL])
     3664#define RSCAN0RMDF058HH (RSCAN0.RMDF058.UINT8[R_IO_HH])
     3665#define RSCAN0RMDF158 (RSCAN0.RMDF158.UINT32)
     3666#define RSCAN0RMDF158L (RSCAN0.RMDF158.UINT16[R_IO_L])
     3667#define RSCAN0RMDF158LL (RSCAN0.RMDF158.UINT8[R_IO_LL])
     3668#define RSCAN0RMDF158LH (RSCAN0.RMDF158.UINT8[R_IO_LH])
     3669#define RSCAN0RMDF158H (RSCAN0.RMDF158.UINT16[R_IO_H])
     3670#define RSCAN0RMDF158HL (RSCAN0.RMDF158.UINT8[R_IO_HL])
     3671#define RSCAN0RMDF158HH (RSCAN0.RMDF158.UINT8[R_IO_HH])
     3672#define RSCAN0RMID59 (RSCAN0.RMID59.UINT32)
     3673#define RSCAN0RMID59L (RSCAN0.RMID59.UINT16[R_IO_L])
     3674#define RSCAN0RMID59LL (RSCAN0.RMID59.UINT8[R_IO_LL])
     3675#define RSCAN0RMID59LH (RSCAN0.RMID59.UINT8[R_IO_LH])
     3676#define RSCAN0RMID59H (RSCAN0.RMID59.UINT16[R_IO_H])
     3677#define RSCAN0RMID59HL (RSCAN0.RMID59.UINT8[R_IO_HL])
     3678#define RSCAN0RMID59HH (RSCAN0.RMID59.UINT8[R_IO_HH])
     3679#define RSCAN0RMPTR59 (RSCAN0.RMPTR59.UINT32)
     3680#define RSCAN0RMPTR59L (RSCAN0.RMPTR59.UINT16[R_IO_L])
     3681#define RSCAN0RMPTR59LL (RSCAN0.RMPTR59.UINT8[R_IO_LL])
     3682#define RSCAN0RMPTR59LH (RSCAN0.RMPTR59.UINT8[R_IO_LH])
     3683#define RSCAN0RMPTR59H (RSCAN0.RMPTR59.UINT16[R_IO_H])
     3684#define RSCAN0RMPTR59HL (RSCAN0.RMPTR59.UINT8[R_IO_HL])
     3685#define RSCAN0RMPTR59HH (RSCAN0.RMPTR59.UINT8[R_IO_HH])
     3686#define RSCAN0RMDF059 (RSCAN0.RMDF059.UINT32)
     3687#define RSCAN0RMDF059L (RSCAN0.RMDF059.UINT16[R_IO_L])
     3688#define RSCAN0RMDF059LL (RSCAN0.RMDF059.UINT8[R_IO_LL])
     3689#define RSCAN0RMDF059LH (RSCAN0.RMDF059.UINT8[R_IO_LH])
     3690#define RSCAN0RMDF059H (RSCAN0.RMDF059.UINT16[R_IO_H])
     3691#define RSCAN0RMDF059HL (RSCAN0.RMDF059.UINT8[R_IO_HL])
     3692#define RSCAN0RMDF059HH (RSCAN0.RMDF059.UINT8[R_IO_HH])
     3693#define RSCAN0RMDF159 (RSCAN0.RMDF159.UINT32)
     3694#define RSCAN0RMDF159L (RSCAN0.RMDF159.UINT16[R_IO_L])
     3695#define RSCAN0RMDF159LL (RSCAN0.RMDF159.UINT8[R_IO_LL])
     3696#define RSCAN0RMDF159LH (RSCAN0.RMDF159.UINT8[R_IO_LH])
     3697#define RSCAN0RMDF159H (RSCAN0.RMDF159.UINT16[R_IO_H])
     3698#define RSCAN0RMDF159HL (RSCAN0.RMDF159.UINT8[R_IO_HL])
     3699#define RSCAN0RMDF159HH (RSCAN0.RMDF159.UINT8[R_IO_HH])
     3700#define RSCAN0RMID60 (RSCAN0.RMID60.UINT32)
     3701#define RSCAN0RMID60L (RSCAN0.RMID60.UINT16[R_IO_L])
     3702#define RSCAN0RMID60LL (RSCAN0.RMID60.UINT8[R_IO_LL])
     3703#define RSCAN0RMID60LH (RSCAN0.RMID60.UINT8[R_IO_LH])
     3704#define RSCAN0RMID60H (RSCAN0.RMID60.UINT16[R_IO_H])
     3705#define RSCAN0RMID60HL (RSCAN0.RMID60.UINT8[R_IO_HL])
     3706#define RSCAN0RMID60HH (RSCAN0.RMID60.UINT8[R_IO_HH])
     3707#define RSCAN0RMPTR60 (RSCAN0.RMPTR60.UINT32)
     3708#define RSCAN0RMPTR60L (RSCAN0.RMPTR60.UINT16[R_IO_L])
     3709#define RSCAN0RMPTR60LL (RSCAN0.RMPTR60.UINT8[R_IO_LL])
     3710#define RSCAN0RMPTR60LH (RSCAN0.RMPTR60.UINT8[R_IO_LH])
     3711#define RSCAN0RMPTR60H (RSCAN0.RMPTR60.UINT16[R_IO_H])
     3712#define RSCAN0RMPTR60HL (RSCAN0.RMPTR60.UINT8[R_IO_HL])
     3713#define RSCAN0RMPTR60HH (RSCAN0.RMPTR60.UINT8[R_IO_HH])
     3714#define RSCAN0RMDF060 (RSCAN0.RMDF060.UINT32)
     3715#define RSCAN0RMDF060L (RSCAN0.RMDF060.UINT16[R_IO_L])
     3716#define RSCAN0RMDF060LL (RSCAN0.RMDF060.UINT8[R_IO_LL])
     3717#define RSCAN0RMDF060LH (RSCAN0.RMDF060.UINT8[R_IO_LH])
     3718#define RSCAN0RMDF060H (RSCAN0.RMDF060.UINT16[R_IO_H])
     3719#define RSCAN0RMDF060HL (RSCAN0.RMDF060.UINT8[R_IO_HL])
     3720#define RSCAN0RMDF060HH (RSCAN0.RMDF060.UINT8[R_IO_HH])
     3721#define RSCAN0RMDF160 (RSCAN0.RMDF160.UINT32)
     3722#define RSCAN0RMDF160L (RSCAN0.RMDF160.UINT16[R_IO_L])
     3723#define RSCAN0RMDF160LL (RSCAN0.RMDF160.UINT8[R_IO_LL])
     3724#define RSCAN0RMDF160LH (RSCAN0.RMDF160.UINT8[R_IO_LH])
     3725#define RSCAN0RMDF160H (RSCAN0.RMDF160.UINT16[R_IO_H])
     3726#define RSCAN0RMDF160HL (RSCAN0.RMDF160.UINT8[R_IO_HL])
     3727#define RSCAN0RMDF160HH (RSCAN0.RMDF160.UINT8[R_IO_HH])
     3728#define RSCAN0RMID61 (RSCAN0.RMID61.UINT32)
     3729#define RSCAN0RMID61L (RSCAN0.RMID61.UINT16[R_IO_L])
     3730#define RSCAN0RMID61LL (RSCAN0.RMID61.UINT8[R_IO_LL])
     3731#define RSCAN0RMID61LH (RSCAN0.RMID61.UINT8[R_IO_LH])
     3732#define RSCAN0RMID61H (RSCAN0.RMID61.UINT16[R_IO_H])
     3733#define RSCAN0RMID61HL (RSCAN0.RMID61.UINT8[R_IO_HL])
     3734#define RSCAN0RMID61HH (RSCAN0.RMID61.UINT8[R_IO_HH])
     3735#define RSCAN0RMPTR61 (RSCAN0.RMPTR61.UINT32)
     3736#define RSCAN0RMPTR61L (RSCAN0.RMPTR61.UINT16[R_IO_L])
     3737#define RSCAN0RMPTR61LL (RSCAN0.RMPTR61.UINT8[R_IO_LL])
     3738#define RSCAN0RMPTR61LH (RSCAN0.RMPTR61.UINT8[R_IO_LH])
     3739#define RSCAN0RMPTR61H (RSCAN0.RMPTR61.UINT16[R_IO_H])
     3740#define RSCAN0RMPTR61HL (RSCAN0.RMPTR61.UINT8[R_IO_HL])
     3741#define RSCAN0RMPTR61HH (RSCAN0.RMPTR61.UINT8[R_IO_HH])
     3742#define RSCAN0RMDF061 (RSCAN0.RMDF061.UINT32)
     3743#define RSCAN0RMDF061L (RSCAN0.RMDF061.UINT16[R_IO_L])
     3744#define RSCAN0RMDF061LL (RSCAN0.RMDF061.UINT8[R_IO_LL])
     3745#define RSCAN0RMDF061LH (RSCAN0.RMDF061.UINT8[R_IO_LH])
     3746#define RSCAN0RMDF061H (RSCAN0.RMDF061.UINT16[R_IO_H])
     3747#define RSCAN0RMDF061HL (RSCAN0.RMDF061.UINT8[R_IO_HL])
     3748#define RSCAN0RMDF061HH (RSCAN0.RMDF061.UINT8[R_IO_HH])
     3749#define RSCAN0RMDF161 (RSCAN0.RMDF161.UINT32)
     3750#define RSCAN0RMDF161L (RSCAN0.RMDF161.UINT16[R_IO_L])
     3751#define RSCAN0RMDF161LL (RSCAN0.RMDF161.UINT8[R_IO_LL])
     3752#define RSCAN0RMDF161LH (RSCAN0.RMDF161.UINT8[R_IO_LH])
     3753#define RSCAN0RMDF161H (RSCAN0.RMDF161.UINT16[R_IO_H])
     3754#define RSCAN0RMDF161HL (RSCAN0.RMDF161.UINT8[R_IO_HL])
     3755#define RSCAN0RMDF161HH (RSCAN0.RMDF161.UINT8[R_IO_HH])
     3756#define RSCAN0RMID62 (RSCAN0.RMID62.UINT32)
     3757#define RSCAN0RMID62L (RSCAN0.RMID62.UINT16[R_IO_L])
     3758#define RSCAN0RMID62LL (RSCAN0.RMID62.UINT8[R_IO_LL])
     3759#define RSCAN0RMID62LH (RSCAN0.RMID62.UINT8[R_IO_LH])
     3760#define RSCAN0RMID62H (RSCAN0.RMID62.UINT16[R_IO_H])
     3761#define RSCAN0RMID62HL (RSCAN0.RMID62.UINT8[R_IO_HL])
     3762#define RSCAN0RMID62HH (RSCAN0.RMID62.UINT8[R_IO_HH])
     3763#define RSCAN0RMPTR62 (RSCAN0.RMPTR62.UINT32)
     3764#define RSCAN0RMPTR62L (RSCAN0.RMPTR62.UINT16[R_IO_L])
     3765#define RSCAN0RMPTR62LL (RSCAN0.RMPTR62.UINT8[R_IO_LL])
     3766#define RSCAN0RMPTR62LH (RSCAN0.RMPTR62.UINT8[R_IO_LH])
     3767#define RSCAN0RMPTR62H (RSCAN0.RMPTR62.UINT16[R_IO_H])
     3768#define RSCAN0RMPTR62HL (RSCAN0.RMPTR62.UINT8[R_IO_HL])
     3769#define RSCAN0RMPTR62HH (RSCAN0.RMPTR62.UINT8[R_IO_HH])
     3770#define RSCAN0RMDF062 (RSCAN0.RMDF062.UINT32)
     3771#define RSCAN0RMDF062L (RSCAN0.RMDF062.UINT16[R_IO_L])
     3772#define RSCAN0RMDF062LL (RSCAN0.RMDF062.UINT8[R_IO_LL])
     3773#define RSCAN0RMDF062LH (RSCAN0.RMDF062.UINT8[R_IO_LH])
     3774#define RSCAN0RMDF062H (RSCAN0.RMDF062.UINT16[R_IO_H])
     3775#define RSCAN0RMDF062HL (RSCAN0.RMDF062.UINT8[R_IO_HL])
     3776#define RSCAN0RMDF062HH (RSCAN0.RMDF062.UINT8[R_IO_HH])
     3777#define RSCAN0RMDF162 (RSCAN0.RMDF162.UINT32)
     3778#define RSCAN0RMDF162L (RSCAN0.RMDF162.UINT16[R_IO_L])
     3779#define RSCAN0RMDF162LL (RSCAN0.RMDF162.UINT8[R_IO_LL])
     3780#define RSCAN0RMDF162LH (RSCAN0.RMDF162.UINT8[R_IO_LH])
     3781#define RSCAN0RMDF162H (RSCAN0.RMDF162.UINT16[R_IO_H])
     3782#define RSCAN0RMDF162HL (RSCAN0.RMDF162.UINT8[R_IO_HL])
     3783#define RSCAN0RMDF162HH (RSCAN0.RMDF162.UINT8[R_IO_HH])
     3784#define RSCAN0RMID63 (RSCAN0.RMID63.UINT32)
     3785#define RSCAN0RMID63L (RSCAN0.RMID63.UINT16[R_IO_L])
     3786#define RSCAN0RMID63LL (RSCAN0.RMID63.UINT8[R_IO_LL])
     3787#define RSCAN0RMID63LH (RSCAN0.RMID63.UINT8[R_IO_LH])
     3788#define RSCAN0RMID63H (RSCAN0.RMID63.UINT16[R_IO_H])
     3789#define RSCAN0RMID63HL (RSCAN0.RMID63.UINT8[R_IO_HL])
     3790#define RSCAN0RMID63HH (RSCAN0.RMID63.UINT8[R_IO_HH])
     3791#define RSCAN0RMPTR63 (RSCAN0.RMPTR63.UINT32)
     3792#define RSCAN0RMPTR63L (RSCAN0.RMPTR63.UINT16[R_IO_L])
     3793#define RSCAN0RMPTR63LL (RSCAN0.RMPTR63.UINT8[R_IO_LL])
     3794#define RSCAN0RMPTR63LH (RSCAN0.RMPTR63.UINT8[R_IO_LH])
     3795#define RSCAN0RMPTR63H (RSCAN0.RMPTR63.UINT16[R_IO_H])
     3796#define RSCAN0RMPTR63HL (RSCAN0.RMPTR63.UINT8[R_IO_HL])
     3797#define RSCAN0RMPTR63HH (RSCAN0.RMPTR63.UINT8[R_IO_HH])
     3798#define RSCAN0RMDF063 (RSCAN0.RMDF063.UINT32)
     3799#define RSCAN0RMDF063L (RSCAN0.RMDF063.UINT16[R_IO_L])
     3800#define RSCAN0RMDF063LL (RSCAN0.RMDF063.UINT8[R_IO_LL])
     3801#define RSCAN0RMDF063LH (RSCAN0.RMDF063.UINT8[R_IO_LH])
     3802#define RSCAN0RMDF063H (RSCAN0.RMDF063.UINT16[R_IO_H])
     3803#define RSCAN0RMDF063HL (RSCAN0.RMDF063.UINT8[R_IO_HL])
     3804#define RSCAN0RMDF063HH (RSCAN0.RMDF063.UINT8[R_IO_HH])
     3805#define RSCAN0RMDF163 (RSCAN0.RMDF163.UINT32)
     3806#define RSCAN0RMDF163L (RSCAN0.RMDF163.UINT16[R_IO_L])
     3807#define RSCAN0RMDF163LL (RSCAN0.RMDF163.UINT8[R_IO_LL])
     3808#define RSCAN0RMDF163LH (RSCAN0.RMDF163.UINT8[R_IO_LH])
     3809#define RSCAN0RMDF163H (RSCAN0.RMDF163.UINT16[R_IO_H])
     3810#define RSCAN0RMDF163HL (RSCAN0.RMDF163.UINT8[R_IO_HL])
     3811#define RSCAN0RMDF163HH (RSCAN0.RMDF163.UINT8[R_IO_HH])
     3812#define RSCAN0RMID64 (RSCAN0.RMID64.UINT32)
     3813#define RSCAN0RMID64L (RSCAN0.RMID64.UINT16[R_IO_L])
     3814#define RSCAN0RMID64LL (RSCAN0.RMID64.UINT8[R_IO_LL])
     3815#define RSCAN0RMID64LH (RSCAN0.RMID64.UINT8[R_IO_LH])
     3816#define RSCAN0RMID64H (RSCAN0.RMID64.UINT16[R_IO_H])
     3817#define RSCAN0RMID64HL (RSCAN0.RMID64.UINT8[R_IO_HL])
     3818#define RSCAN0RMID64HH (RSCAN0.RMID64.UINT8[R_IO_HH])
     3819#define RSCAN0RMPTR64 (RSCAN0.RMPTR64.UINT32)
     3820#define RSCAN0RMPTR64L (RSCAN0.RMPTR64.UINT16[R_IO_L])
     3821#define RSCAN0RMPTR64LL (RSCAN0.RMPTR64.UINT8[R_IO_LL])
     3822#define RSCAN0RMPTR64LH (RSCAN0.RMPTR64.UINT8[R_IO_LH])
     3823#define RSCAN0RMPTR64H (RSCAN0.RMPTR64.UINT16[R_IO_H])
     3824#define RSCAN0RMPTR64HL (RSCAN0.RMPTR64.UINT8[R_IO_HL])
     3825#define RSCAN0RMPTR64HH (RSCAN0.RMPTR64.UINT8[R_IO_HH])
     3826#define RSCAN0RMDF064 (RSCAN0.RMDF064.UINT32)
     3827#define RSCAN0RMDF064L (RSCAN0.RMDF064.UINT16[R_IO_L])
     3828#define RSCAN0RMDF064LL (RSCAN0.RMDF064.UINT8[R_IO_LL])
     3829#define RSCAN0RMDF064LH (RSCAN0.RMDF064.UINT8[R_IO_LH])
     3830#define RSCAN0RMDF064H (RSCAN0.RMDF064.UINT16[R_IO_H])
     3831#define RSCAN0RMDF064HL (RSCAN0.RMDF064.UINT8[R_IO_HL])
     3832#define RSCAN0RMDF064HH (RSCAN0.RMDF064.UINT8[R_IO_HH])
     3833#define RSCAN0RMDF164 (RSCAN0.RMDF164.UINT32)
     3834#define RSCAN0RMDF164L (RSCAN0.RMDF164.UINT16[R_IO_L])
     3835#define RSCAN0RMDF164LL (RSCAN0.RMDF164.UINT8[R_IO_LL])
     3836#define RSCAN0RMDF164LH (RSCAN0.RMDF164.UINT8[R_IO_LH])
     3837#define RSCAN0RMDF164H (RSCAN0.RMDF164.UINT16[R_IO_H])
     3838#define RSCAN0RMDF164HL (RSCAN0.RMDF164.UINT8[R_IO_HL])
     3839#define RSCAN0RMDF164HH (RSCAN0.RMDF164.UINT8[R_IO_HH])
     3840#define RSCAN0RMID65 (RSCAN0.RMID65.UINT32)
     3841#define RSCAN0RMID65L (RSCAN0.RMID65.UINT16[R_IO_L])
     3842#define RSCAN0RMID65LL (RSCAN0.RMID65.UINT8[R_IO_LL])
     3843#define RSCAN0RMID65LH (RSCAN0.RMID65.UINT8[R_IO_LH])
     3844#define RSCAN0RMID65H (RSCAN0.RMID65.UINT16[R_IO_H])
     3845#define RSCAN0RMID65HL (RSCAN0.RMID65.UINT8[R_IO_HL])
     3846#define RSCAN0RMID65HH (RSCAN0.RMID65.UINT8[R_IO_HH])
     3847#define RSCAN0RMPTR65 (RSCAN0.RMPTR65.UINT32)
     3848#define RSCAN0RMPTR65L (RSCAN0.RMPTR65.UINT16[R_IO_L])
     3849#define RSCAN0RMPTR65LL (RSCAN0.RMPTR65.UINT8[R_IO_LL])
     3850#define RSCAN0RMPTR65LH (RSCAN0.RMPTR65.UINT8[R_IO_LH])
     3851#define RSCAN0RMPTR65H (RSCAN0.RMPTR65.UINT16[R_IO_H])
     3852#define RSCAN0RMPTR65HL (RSCAN0.RMPTR65.UINT8[R_IO_HL])
     3853#define RSCAN0RMPTR65HH (RSCAN0.RMPTR65.UINT8[R_IO_HH])
     3854#define RSCAN0RMDF065 (RSCAN0.RMDF065.UINT32)
     3855#define RSCAN0RMDF065L (RSCAN0.RMDF065.UINT16[R_IO_L])
     3856#define RSCAN0RMDF065LL (RSCAN0.RMDF065.UINT8[R_IO_LL])
     3857#define RSCAN0RMDF065LH (RSCAN0.RMDF065.UINT8[R_IO_LH])
     3858#define RSCAN0RMDF065H (RSCAN0.RMDF065.UINT16[R_IO_H])
     3859#define RSCAN0RMDF065HL (RSCAN0.RMDF065.UINT8[R_IO_HL])
     3860#define RSCAN0RMDF065HH (RSCAN0.RMDF065.UINT8[R_IO_HH])
     3861#define RSCAN0RMDF165 (RSCAN0.RMDF165.UINT32)
     3862#define RSCAN0RMDF165L (RSCAN0.RMDF165.UINT16[R_IO_L])
     3863#define RSCAN0RMDF165LL (RSCAN0.RMDF165.UINT8[R_IO_LL])
     3864#define RSCAN0RMDF165LH (RSCAN0.RMDF165.UINT8[R_IO_LH])
     3865#define RSCAN0RMDF165H (RSCAN0.RMDF165.UINT16[R_IO_H])
     3866#define RSCAN0RMDF165HL (RSCAN0.RMDF165.UINT8[R_IO_HL])
     3867#define RSCAN0RMDF165HH (RSCAN0.RMDF165.UINT8[R_IO_HH])
     3868#define RSCAN0RMID66 (RSCAN0.RMID66.UINT32)
     3869#define RSCAN0RMID66L (RSCAN0.RMID66.UINT16[R_IO_L])
     3870#define RSCAN0RMID66LL (RSCAN0.RMID66.UINT8[R_IO_LL])
     3871#define RSCAN0RMID66LH (RSCAN0.RMID66.UINT8[R_IO_LH])
     3872#define RSCAN0RMID66H (RSCAN0.RMID66.UINT16[R_IO_H])
     3873#define RSCAN0RMID66HL (RSCAN0.RMID66.UINT8[R_IO_HL])
     3874#define RSCAN0RMID66HH (RSCAN0.RMID66.UINT8[R_IO_HH])
     3875#define RSCAN0RMPTR66 (RSCAN0.RMPTR66.UINT32)
     3876#define RSCAN0RMPTR66L (RSCAN0.RMPTR66.UINT16[R_IO_L])
     3877#define RSCAN0RMPTR66LL (RSCAN0.RMPTR66.UINT8[R_IO_LL])
     3878#define RSCAN0RMPTR66LH (RSCAN0.RMPTR66.UINT8[R_IO_LH])
     3879#define RSCAN0RMPTR66H (RSCAN0.RMPTR66.UINT16[R_IO_H])
     3880#define RSCAN0RMPTR66HL (RSCAN0.RMPTR66.UINT8[R_IO_HL])
     3881#define RSCAN0RMPTR66HH (RSCAN0.RMPTR66.UINT8[R_IO_HH])
     3882#define RSCAN0RMDF066 (RSCAN0.RMDF066.UINT32)
     3883#define RSCAN0RMDF066L (RSCAN0.RMDF066.UINT16[R_IO_L])
     3884#define RSCAN0RMDF066LL (RSCAN0.RMDF066.UINT8[R_IO_LL])
     3885#define RSCAN0RMDF066LH (RSCAN0.RMDF066.UINT8[R_IO_LH])
     3886#define RSCAN0RMDF066H (RSCAN0.RMDF066.UINT16[R_IO_H])
     3887#define RSCAN0RMDF066HL (RSCAN0.RMDF066.UINT8[R_IO_HL])
     3888#define RSCAN0RMDF066HH (RSCAN0.RMDF066.UINT8[R_IO_HH])
     3889#define RSCAN0RMDF166 (RSCAN0.RMDF166.UINT32)
     3890#define RSCAN0RMDF166L (RSCAN0.RMDF166.UINT16[R_IO_L])
     3891#define RSCAN0RMDF166LL (RSCAN0.RMDF166.UINT8[R_IO_LL])
     3892#define RSCAN0RMDF166LH (RSCAN0.RMDF166.UINT8[R_IO_LH])
     3893#define RSCAN0RMDF166H (RSCAN0.RMDF166.UINT16[R_IO_H])
     3894#define RSCAN0RMDF166HL (RSCAN0.RMDF166.UINT8[R_IO_HL])
     3895#define RSCAN0RMDF166HH (RSCAN0.RMDF166.UINT8[R_IO_HH])
     3896#define RSCAN0RMID67 (RSCAN0.RMID67.UINT32)
     3897#define RSCAN0RMID67L (RSCAN0.RMID67.UINT16[R_IO_L])
     3898#define RSCAN0RMID67LL (RSCAN0.RMID67.UINT8[R_IO_LL])
     3899#define RSCAN0RMID67LH (RSCAN0.RMID67.UINT8[R_IO_LH])
     3900#define RSCAN0RMID67H (RSCAN0.RMID67.UINT16[R_IO_H])
     3901#define RSCAN0RMID67HL (RSCAN0.RMID67.UINT8[R_IO_HL])
     3902#define RSCAN0RMID67HH (RSCAN0.RMID67.UINT8[R_IO_HH])
     3903#define RSCAN0RMPTR67 (RSCAN0.RMPTR67.UINT32)
     3904#define RSCAN0RMPTR67L (RSCAN0.RMPTR67.UINT16[R_IO_L])
     3905#define RSCAN0RMPTR67LL (RSCAN0.RMPTR67.UINT8[R_IO_LL])
     3906#define RSCAN0RMPTR67LH (RSCAN0.RMPTR67.UINT8[R_IO_LH])
     3907#define RSCAN0RMPTR67H (RSCAN0.RMPTR67.UINT16[R_IO_H])
     3908#define RSCAN0RMPTR67HL (RSCAN0.RMPTR67.UINT8[R_IO_HL])
     3909#define RSCAN0RMPTR67HH (RSCAN0.RMPTR67.UINT8[R_IO_HH])
     3910#define RSCAN0RMDF067 (RSCAN0.RMDF067.UINT32)
     3911#define RSCAN0RMDF067L (RSCAN0.RMDF067.UINT16[R_IO_L])
     3912#define RSCAN0RMDF067LL (RSCAN0.RMDF067.UINT8[R_IO_LL])
     3913#define RSCAN0RMDF067LH (RSCAN0.RMDF067.UINT8[R_IO_LH])
     3914#define RSCAN0RMDF067H (RSCAN0.RMDF067.UINT16[R_IO_H])
     3915#define RSCAN0RMDF067HL (RSCAN0.RMDF067.UINT8[R_IO_HL])
     3916#define RSCAN0RMDF067HH (RSCAN0.RMDF067.UINT8[R_IO_HH])
     3917#define RSCAN0RMDF167 (RSCAN0.RMDF167.UINT32)
     3918#define RSCAN0RMDF167L (RSCAN0.RMDF167.UINT16[R_IO_L])
     3919#define RSCAN0RMDF167LL (RSCAN0.RMDF167.UINT8[R_IO_LL])
     3920#define RSCAN0RMDF167LH (RSCAN0.RMDF167.UINT8[R_IO_LH])
     3921#define RSCAN0RMDF167H (RSCAN0.RMDF167.UINT16[R_IO_H])
     3922#define RSCAN0RMDF167HL (RSCAN0.RMDF167.UINT8[R_IO_HL])
     3923#define RSCAN0RMDF167HH (RSCAN0.RMDF167.UINT8[R_IO_HH])
     3924#define RSCAN0RMID68 (RSCAN0.RMID68.UINT32)
     3925#define RSCAN0RMID68L (RSCAN0.RMID68.UINT16[R_IO_L])
     3926#define RSCAN0RMID68LL (RSCAN0.RMID68.UINT8[R_IO_LL])
     3927#define RSCAN0RMID68LH (RSCAN0.RMID68.UINT8[R_IO_LH])
     3928#define RSCAN0RMID68H (RSCAN0.RMID68.UINT16[R_IO_H])
     3929#define RSCAN0RMID68HL (RSCAN0.RMID68.UINT8[R_IO_HL])
     3930#define RSCAN0RMID68HH (RSCAN0.RMID68.UINT8[R_IO_HH])
     3931#define RSCAN0RMPTR68 (RSCAN0.RMPTR68.UINT32)
     3932#define RSCAN0RMPTR68L (RSCAN0.RMPTR68.UINT16[R_IO_L])
     3933#define RSCAN0RMPTR68LL (RSCAN0.RMPTR68.UINT8[R_IO_LL])
     3934#define RSCAN0RMPTR68LH (RSCAN0.RMPTR68.UINT8[R_IO_LH])
     3935#define RSCAN0RMPTR68H (RSCAN0.RMPTR68.UINT16[R_IO_H])
     3936#define RSCAN0RMPTR68HL (RSCAN0.RMPTR68.UINT8[R_IO_HL])
     3937#define RSCAN0RMPTR68HH (RSCAN0.RMPTR68.UINT8[R_IO_HH])
     3938#define RSCAN0RMDF068 (RSCAN0.RMDF068.UINT32)
     3939#define RSCAN0RMDF068L (RSCAN0.RMDF068.UINT16[R_IO_L])
     3940#define RSCAN0RMDF068LL (RSCAN0.RMDF068.UINT8[R_IO_LL])
     3941#define RSCAN0RMDF068LH (RSCAN0.RMDF068.UINT8[R_IO_LH])
     3942#define RSCAN0RMDF068H (RSCAN0.RMDF068.UINT16[R_IO_H])
     3943#define RSCAN0RMDF068HL (RSCAN0.RMDF068.UINT8[R_IO_HL])
     3944#define RSCAN0RMDF068HH (RSCAN0.RMDF068.UINT8[R_IO_HH])
     3945#define RSCAN0RMDF168 (RSCAN0.RMDF168.UINT32)
     3946#define RSCAN0RMDF168L (RSCAN0.RMDF168.UINT16[R_IO_L])
     3947#define RSCAN0RMDF168LL (RSCAN0.RMDF168.UINT8[R_IO_LL])
     3948#define RSCAN0RMDF168LH (RSCAN0.RMDF168.UINT8[R_IO_LH])
     3949#define RSCAN0RMDF168H (RSCAN0.RMDF168.UINT16[R_IO_H])
     3950#define RSCAN0RMDF168HL (RSCAN0.RMDF168.UINT8[R_IO_HL])
     3951#define RSCAN0RMDF168HH (RSCAN0.RMDF168.UINT8[R_IO_HH])
     3952#define RSCAN0RMID69 (RSCAN0.RMID69.UINT32)
     3953#define RSCAN0RMID69L (RSCAN0.RMID69.UINT16[R_IO_L])
     3954#define RSCAN0RMID69LL (RSCAN0.RMID69.UINT8[R_IO_LL])
     3955#define RSCAN0RMID69LH (RSCAN0.RMID69.UINT8[R_IO_LH])
     3956#define RSCAN0RMID69H (RSCAN0.RMID69.UINT16[R_IO_H])
     3957#define RSCAN0RMID69HL (RSCAN0.RMID69.UINT8[R_IO_HL])
     3958#define RSCAN0RMID69HH (RSCAN0.RMID69.UINT8[R_IO_HH])
     3959#define RSCAN0RMPTR69 (RSCAN0.RMPTR69.UINT32)
     3960#define RSCAN0RMPTR69L (RSCAN0.RMPTR69.UINT16[R_IO_L])
     3961#define RSCAN0RMPTR69LL (RSCAN0.RMPTR69.UINT8[R_IO_LL])
     3962#define RSCAN0RMPTR69LH (RSCAN0.RMPTR69.UINT8[R_IO_LH])
     3963#define RSCAN0RMPTR69H (RSCAN0.RMPTR69.UINT16[R_IO_H])
     3964#define RSCAN0RMPTR69HL (RSCAN0.RMPTR69.UINT8[R_IO_HL])
     3965#define RSCAN0RMPTR69HH (RSCAN0.RMPTR69.UINT8[R_IO_HH])
     3966#define RSCAN0RMDF069 (RSCAN0.RMDF069.UINT32)
     3967#define RSCAN0RMDF069L (RSCAN0.RMDF069.UINT16[R_IO_L])
     3968#define RSCAN0RMDF069LL (RSCAN0.RMDF069.UINT8[R_IO_LL])
     3969#define RSCAN0RMDF069LH (RSCAN0.RMDF069.UINT8[R_IO_LH])
     3970#define RSCAN0RMDF069H (RSCAN0.RMDF069.UINT16[R_IO_H])
     3971#define RSCAN0RMDF069HL (RSCAN0.RMDF069.UINT8[R_IO_HL])
     3972#define RSCAN0RMDF069HH (RSCAN0.RMDF069.UINT8[R_IO_HH])
     3973#define RSCAN0RMDF169 (RSCAN0.RMDF169.UINT32)
     3974#define RSCAN0RMDF169L (RSCAN0.RMDF169.UINT16[R_IO_L])
     3975#define RSCAN0RMDF169LL (RSCAN0.RMDF169.UINT8[R_IO_LL])
     3976#define RSCAN0RMDF169LH (RSCAN0.RMDF169.UINT8[R_IO_LH])
     3977#define RSCAN0RMDF169H (RSCAN0.RMDF169.UINT16[R_IO_H])
     3978#define RSCAN0RMDF169HL (RSCAN0.RMDF169.UINT8[R_IO_HL])
     3979#define RSCAN0RMDF169HH (RSCAN0.RMDF169.UINT8[R_IO_HH])
     3980#define RSCAN0RMID70 (RSCAN0.RMID70.UINT32)
     3981#define RSCAN0RMID70L (RSCAN0.RMID70.UINT16[R_IO_L])
     3982#define RSCAN0RMID70LL (RSCAN0.RMID70.UINT8[R_IO_LL])
     3983#define RSCAN0RMID70LH (RSCAN0.RMID70.UINT8[R_IO_LH])
     3984#define RSCAN0RMID70H (RSCAN0.RMID70.UINT16[R_IO_H])
     3985#define RSCAN0RMID70HL (RSCAN0.RMID70.UINT8[R_IO_HL])
     3986#define RSCAN0RMID70HH (RSCAN0.RMID70.UINT8[R_IO_HH])
     3987#define RSCAN0RMPTR70 (RSCAN0.RMPTR70.UINT32)
     3988#define RSCAN0RMPTR70L (RSCAN0.RMPTR70.UINT16[R_IO_L])
     3989#define RSCAN0RMPTR70LL (RSCAN0.RMPTR70.UINT8[R_IO_LL])
     3990#define RSCAN0RMPTR70LH (RSCAN0.RMPTR70.UINT8[R_IO_LH])
     3991#define RSCAN0RMPTR70H (RSCAN0.RMPTR70.UINT16[R_IO_H])
     3992#define RSCAN0RMPTR70HL (RSCAN0.RMPTR70.UINT8[R_IO_HL])
     3993#define RSCAN0RMPTR70HH (RSCAN0.RMPTR70.UINT8[R_IO_HH])
     3994#define RSCAN0RMDF070 (RSCAN0.RMDF070.UINT32)
     3995#define RSCAN0RMDF070L (RSCAN0.RMDF070.UINT16[R_IO_L])
     3996#define RSCAN0RMDF070LL (RSCAN0.RMDF070.UINT8[R_IO_LL])
     3997#define RSCAN0RMDF070LH (RSCAN0.RMDF070.UINT8[R_IO_LH])
     3998#define RSCAN0RMDF070H (RSCAN0.RMDF070.UINT16[R_IO_H])
     3999#define RSCAN0RMDF070HL (RSCAN0.RMDF070.UINT8[R_IO_HL])
     4000#define RSCAN0RMDF070HH (RSCAN0.RMDF070.UINT8[R_IO_HH])
     4001#define RSCAN0RMDF170 (RSCAN0.RMDF170.UINT32)
     4002#define RSCAN0RMDF170L (RSCAN0.RMDF170.UINT16[R_IO_L])
     4003#define RSCAN0RMDF170LL (RSCAN0.RMDF170.UINT8[R_IO_LL])
     4004#define RSCAN0RMDF170LH (RSCAN0.RMDF170.UINT8[R_IO_LH])
     4005#define RSCAN0RMDF170H (RSCAN0.RMDF170.UINT16[R_IO_H])
     4006#define RSCAN0RMDF170HL (RSCAN0.RMDF170.UINT8[R_IO_HL])
     4007#define RSCAN0RMDF170HH (RSCAN0.RMDF170.UINT8[R_IO_HH])
     4008#define RSCAN0RMID71 (RSCAN0.RMID71.UINT32)
     4009#define RSCAN0RMID71L (RSCAN0.RMID71.UINT16[R_IO_L])
     4010#define RSCAN0RMID71LL (RSCAN0.RMID71.UINT8[R_IO_LL])
     4011#define RSCAN0RMID71LH (RSCAN0.RMID71.UINT8[R_IO_LH])
     4012#define RSCAN0RMID71H (RSCAN0.RMID71.UINT16[R_IO_H])
     4013#define RSCAN0RMID71HL (RSCAN0.RMID71.UINT8[R_IO_HL])
     4014#define RSCAN0RMID71HH (RSCAN0.RMID71.UINT8[R_IO_HH])
     4015#define RSCAN0RMPTR71 (RSCAN0.RMPTR71.UINT32)
     4016#define RSCAN0RMPTR71L (RSCAN0.RMPTR71.UINT16[R_IO_L])
     4017#define RSCAN0RMPTR71LL (RSCAN0.RMPTR71.UINT8[R_IO_LL])
     4018#define RSCAN0RMPTR71LH (RSCAN0.RMPTR71.UINT8[R_IO_LH])
     4019#define RSCAN0RMPTR71H (RSCAN0.RMPTR71.UINT16[R_IO_H])
     4020#define RSCAN0RMPTR71HL (RSCAN0.RMPTR71.UINT8[R_IO_HL])
     4021#define RSCAN0RMPTR71HH (RSCAN0.RMPTR71.UINT8[R_IO_HH])
     4022#define RSCAN0RMDF071 (RSCAN0.RMDF071.UINT32)
     4023#define RSCAN0RMDF071L (RSCAN0.RMDF071.UINT16[R_IO_L])
     4024#define RSCAN0RMDF071LL (RSCAN0.RMDF071.UINT8[R_IO_LL])
     4025#define RSCAN0RMDF071LH (RSCAN0.RMDF071.UINT8[R_IO_LH])
     4026#define RSCAN0RMDF071H (RSCAN0.RMDF071.UINT16[R_IO_H])
     4027#define RSCAN0RMDF071HL (RSCAN0.RMDF071.UINT8[R_IO_HL])
     4028#define RSCAN0RMDF071HH (RSCAN0.RMDF071.UINT8[R_IO_HH])
     4029#define RSCAN0RMDF171 (RSCAN0.RMDF171.UINT32)
     4030#define RSCAN0RMDF171L (RSCAN0.RMDF171.UINT16[R_IO_L])
     4031#define RSCAN0RMDF171LL (RSCAN0.RMDF171.UINT8[R_IO_LL])
     4032#define RSCAN0RMDF171LH (RSCAN0.RMDF171.UINT8[R_IO_LH])
     4033#define RSCAN0RMDF171H (RSCAN0.RMDF171.UINT16[R_IO_H])
     4034#define RSCAN0RMDF171HL (RSCAN0.RMDF171.UINT8[R_IO_HL])
     4035#define RSCAN0RMDF171HH (RSCAN0.RMDF171.UINT8[R_IO_HH])
     4036#define RSCAN0RMID72 (RSCAN0.RMID72.UINT32)
     4037#define RSCAN0RMID72L (RSCAN0.RMID72.UINT16[R_IO_L])
     4038#define RSCAN0RMID72LL (RSCAN0.RMID72.UINT8[R_IO_LL])
     4039#define RSCAN0RMID72LH (RSCAN0.RMID72.UINT8[R_IO_LH])
     4040#define RSCAN0RMID72H (RSCAN0.RMID72.UINT16[R_IO_H])
     4041#define RSCAN0RMID72HL (RSCAN0.RMID72.UINT8[R_IO_HL])
     4042#define RSCAN0RMID72HH (RSCAN0.RMID72.UINT8[R_IO_HH])
     4043#define RSCAN0RMPTR72 (RSCAN0.RMPTR72.UINT32)
     4044#define RSCAN0RMPTR72L (RSCAN0.RMPTR72.UINT16[R_IO_L])
     4045#define RSCAN0RMPTR72LL (RSCAN0.RMPTR72.UINT8[R_IO_LL])
     4046#define RSCAN0RMPTR72LH (RSCAN0.RMPTR72.UINT8[R_IO_LH])
     4047#define RSCAN0RMPTR72H (RSCAN0.RMPTR72.UINT16[R_IO_H])
     4048#define RSCAN0RMPTR72HL (RSCAN0.RMPTR72.UINT8[R_IO_HL])
     4049#define RSCAN0RMPTR72HH (RSCAN0.RMPTR72.UINT8[R_IO_HH])
     4050#define RSCAN0RMDF072 (RSCAN0.RMDF072.UINT32)
     4051#define RSCAN0RMDF072L (RSCAN0.RMDF072.UINT16[R_IO_L])
     4052#define RSCAN0RMDF072LL (RSCAN0.RMDF072.UINT8[R_IO_LL])
     4053#define RSCAN0RMDF072LH (RSCAN0.RMDF072.UINT8[R_IO_LH])
     4054#define RSCAN0RMDF072H (RSCAN0.RMDF072.UINT16[R_IO_H])
     4055#define RSCAN0RMDF072HL (RSCAN0.RMDF072.UINT8[R_IO_HL])
     4056#define RSCAN0RMDF072HH (RSCAN0.RMDF072.UINT8[R_IO_HH])
     4057#define RSCAN0RMDF172 (RSCAN0.RMDF172.UINT32)
     4058#define RSCAN0RMDF172L (RSCAN0.RMDF172.UINT16[R_IO_L])
     4059#define RSCAN0RMDF172LL (RSCAN0.RMDF172.UINT8[R_IO_LL])
     4060#define RSCAN0RMDF172LH (RSCAN0.RMDF172.UINT8[R_IO_LH])
     4061#define RSCAN0RMDF172H (RSCAN0.RMDF172.UINT16[R_IO_H])
     4062#define RSCAN0RMDF172HL (RSCAN0.RMDF172.UINT8[R_IO_HL])
     4063#define RSCAN0RMDF172HH (RSCAN0.RMDF172.UINT8[R_IO_HH])
     4064#define RSCAN0RMID73 (RSCAN0.RMID73.UINT32)
     4065#define RSCAN0RMID73L (RSCAN0.RMID73.UINT16[R_IO_L])
     4066#define RSCAN0RMID73LL (RSCAN0.RMID73.UINT8[R_IO_LL])
     4067#define RSCAN0RMID73LH (RSCAN0.RMID73.UINT8[R_IO_LH])
     4068#define RSCAN0RMID73H (RSCAN0.RMID73.UINT16[R_IO_H])
     4069#define RSCAN0RMID73HL (RSCAN0.RMID73.UINT8[R_IO_HL])
     4070#define RSCAN0RMID73HH (RSCAN0.RMID73.UINT8[R_IO_HH])
     4071#define RSCAN0RMPTR73 (RSCAN0.RMPTR73.UINT32)
     4072#define RSCAN0RMPTR73L (RSCAN0.RMPTR73.UINT16[R_IO_L])
     4073#define RSCAN0RMPTR73LL (RSCAN0.RMPTR73.UINT8[R_IO_LL])
     4074#define RSCAN0RMPTR73LH (RSCAN0.RMPTR73.UINT8[R_IO_LH])
     4075#define RSCAN0RMPTR73H (RSCAN0.RMPTR73.UINT16[R_IO_H])
     4076#define RSCAN0RMPTR73HL (RSCAN0.RMPTR73.UINT8[R_IO_HL])
     4077#define RSCAN0RMPTR73HH (RSCAN0.RMPTR73.UINT8[R_IO_HH])
     4078#define RSCAN0RMDF073 (RSCAN0.RMDF073.UINT32)
     4079#define RSCAN0RMDF073L (RSCAN0.RMDF073.UINT16[R_IO_L])
     4080#define RSCAN0RMDF073LL (RSCAN0.RMDF073.UINT8[R_IO_LL])
     4081#define RSCAN0RMDF073LH (RSCAN0.RMDF073.UINT8[R_IO_LH])
     4082#define RSCAN0RMDF073H (RSCAN0.RMDF073.UINT16[R_IO_H])
     4083#define RSCAN0RMDF073HL (RSCAN0.RMDF073.UINT8[R_IO_HL])
     4084#define RSCAN0RMDF073HH (RSCAN0.RMDF073.UINT8[R_IO_HH])
     4085#define RSCAN0RMDF173 (RSCAN0.RMDF173.UINT32)
     4086#define RSCAN0RMDF173L (RSCAN0.RMDF173.UINT16[R_IO_L])
     4087#define RSCAN0RMDF173LL (RSCAN0.RMDF173.UINT8[R_IO_LL])
     4088#define RSCAN0RMDF173LH (RSCAN0.RMDF173.UINT8[R_IO_LH])
     4089#define RSCAN0RMDF173H (RSCAN0.RMDF173.UINT16[R_IO_H])
     4090#define RSCAN0RMDF173HL (RSCAN0.RMDF173.UINT8[R_IO_HL])
     4091#define RSCAN0RMDF173HH (RSCAN0.RMDF173.UINT8[R_IO_HH])
     4092#define RSCAN0RMID74 (RSCAN0.RMID74.UINT32)
     4093#define RSCAN0RMID74L (RSCAN0.RMID74.UINT16[R_IO_L])
     4094#define RSCAN0RMID74LL (RSCAN0.RMID74.UINT8[R_IO_LL])
     4095#define RSCAN0RMID74LH (RSCAN0.RMID74.UINT8[R_IO_LH])
     4096#define RSCAN0RMID74H (RSCAN0.RMID74.UINT16[R_IO_H])
     4097#define RSCAN0RMID74HL (RSCAN0.RMID74.UINT8[R_IO_HL])
     4098#define RSCAN0RMID74HH (RSCAN0.RMID74.UINT8[R_IO_HH])
     4099#define RSCAN0RMPTR74 (RSCAN0.RMPTR74.UINT32)
     4100#define RSCAN0RMPTR74L (RSCAN0.RMPTR74.UINT16[R_IO_L])
     4101#define RSCAN0RMPTR74LL (RSCAN0.RMPTR74.UINT8[R_IO_LL])
     4102#define RSCAN0RMPTR74LH (RSCAN0.RMPTR74.UINT8[R_IO_LH])
     4103#define RSCAN0RMPTR74H (RSCAN0.RMPTR74.UINT16[R_IO_H])
     4104#define RSCAN0RMPTR74HL (RSCAN0.RMPTR74.UINT8[R_IO_HL])
     4105#define RSCAN0RMPTR74HH (RSCAN0.RMPTR74.UINT8[R_IO_HH])
     4106#define RSCAN0RMDF074 (RSCAN0.RMDF074.UINT32)
     4107#define RSCAN0RMDF074L (RSCAN0.RMDF074.UINT16[R_IO_L])
     4108#define RSCAN0RMDF074LL (RSCAN0.RMDF074.UINT8[R_IO_LL])
     4109#define RSCAN0RMDF074LH (RSCAN0.RMDF074.UINT8[R_IO_LH])
     4110#define RSCAN0RMDF074H (RSCAN0.RMDF074.UINT16[R_IO_H])
     4111#define RSCAN0RMDF074HL (RSCAN0.RMDF074.UINT8[R_IO_HL])
     4112#define RSCAN0RMDF074HH (RSCAN0.RMDF074.UINT8[R_IO_HH])
     4113#define RSCAN0RMDF174 (RSCAN0.RMDF174.UINT32)
     4114#define RSCAN0RMDF174L (RSCAN0.RMDF174.UINT16[R_IO_L])
     4115#define RSCAN0RMDF174LL (RSCAN0.RMDF174.UINT8[R_IO_LL])
     4116#define RSCAN0RMDF174LH (RSCAN0.RMDF174.UINT8[R_IO_LH])
     4117#define RSCAN0RMDF174H (RSCAN0.RMDF174.UINT16[R_IO_H])
     4118#define RSCAN0RMDF174HL (RSCAN0.RMDF174.UINT8[R_IO_HL])
     4119#define RSCAN0RMDF174HH (RSCAN0.RMDF174.UINT8[R_IO_HH])
     4120#define RSCAN0RMID75 (RSCAN0.RMID75.UINT32)
     4121#define RSCAN0RMID75L (RSCAN0.RMID75.UINT16[R_IO_L])
     4122#define RSCAN0RMID75LL (RSCAN0.RMID75.UINT8[R_IO_LL])
     4123#define RSCAN0RMID75LH (RSCAN0.RMID75.UINT8[R_IO_LH])
     4124#define RSCAN0RMID75H (RSCAN0.RMID75.UINT16[R_IO_H])
     4125#define RSCAN0RMID75HL (RSCAN0.RMID75.UINT8[R_IO_HL])
     4126#define RSCAN0RMID75HH (RSCAN0.RMID75.UINT8[R_IO_HH])
     4127#define RSCAN0RMPTR75 (RSCAN0.RMPTR75.UINT32)
     4128#define RSCAN0RMPTR75L (RSCAN0.RMPTR75.UINT16[R_IO_L])
     4129#define RSCAN0RMPTR75LL (RSCAN0.RMPTR75.UINT8[R_IO_LL])
     4130#define RSCAN0RMPTR75LH (RSCAN0.RMPTR75.UINT8[R_IO_LH])
     4131#define RSCAN0RMPTR75H (RSCAN0.RMPTR75.UINT16[R_IO_H])
     4132#define RSCAN0RMPTR75HL (RSCAN0.RMPTR75.UINT8[R_IO_HL])
     4133#define RSCAN0RMPTR75HH (RSCAN0.RMPTR75.UINT8[R_IO_HH])
     4134#define RSCAN0RMDF075 (RSCAN0.RMDF075.UINT32)
     4135#define RSCAN0RMDF075L (RSCAN0.RMDF075.UINT16[R_IO_L])
     4136#define RSCAN0RMDF075LL (RSCAN0.RMDF075.UINT8[R_IO_LL])
     4137#define RSCAN0RMDF075LH (RSCAN0.RMDF075.UINT8[R_IO_LH])
     4138#define RSCAN0RMDF075H (RSCAN0.RMDF075.UINT16[R_IO_H])
     4139#define RSCAN0RMDF075HL (RSCAN0.RMDF075.UINT8[R_IO_HL])
     4140#define RSCAN0RMDF075HH (RSCAN0.RMDF075.UINT8[R_IO_HH])
     4141#define RSCAN0RMDF175 (RSCAN0.RMDF175.UINT32)
     4142#define RSCAN0RMDF175L (RSCAN0.RMDF175.UINT16[R_IO_L])
     4143#define RSCAN0RMDF175LL (RSCAN0.RMDF175.UINT8[R_IO_LL])
     4144#define RSCAN0RMDF175LH (RSCAN0.RMDF175.UINT8[R_IO_LH])
     4145#define RSCAN0RMDF175H (RSCAN0.RMDF175.UINT16[R_IO_H])
     4146#define RSCAN0RMDF175HL (RSCAN0.RMDF175.UINT8[R_IO_HL])
     4147#define RSCAN0RMDF175HH (RSCAN0.RMDF175.UINT8[R_IO_HH])
     4148#define RSCAN0RMID76 (RSCAN0.RMID76.UINT32)
     4149#define RSCAN0RMID76L (RSCAN0.RMID76.UINT16[R_IO_L])
     4150#define RSCAN0RMID76LL (RSCAN0.RMID76.UINT8[R_IO_LL])
     4151#define RSCAN0RMID76LH (RSCAN0.RMID76.UINT8[R_IO_LH])
     4152#define RSCAN0RMID76H (RSCAN0.RMID76.UINT16[R_IO_H])
     4153#define RSCAN0RMID76HL (RSCAN0.RMID76.UINT8[R_IO_HL])
     4154#define RSCAN0RMID76HH (RSCAN0.RMID76.UINT8[R_IO_HH])
     4155#define RSCAN0RMPTR76 (RSCAN0.RMPTR76.UINT32)
     4156#define RSCAN0RMPTR76L (RSCAN0.RMPTR76.UINT16[R_IO_L])
     4157#define RSCAN0RMPTR76LL (RSCAN0.RMPTR76.UINT8[R_IO_LL])
     4158#define RSCAN0RMPTR76LH (RSCAN0.RMPTR76.UINT8[R_IO_LH])
     4159#define RSCAN0RMPTR76H (RSCAN0.RMPTR76.UINT16[R_IO_H])
     4160#define RSCAN0RMPTR76HL (RSCAN0.RMPTR76.UINT8[R_IO_HL])
     4161#define RSCAN0RMPTR76HH (RSCAN0.RMPTR76.UINT8[R_IO_HH])
     4162#define RSCAN0RMDF076 (RSCAN0.RMDF076.UINT32)
     4163#define RSCAN0RMDF076L (RSCAN0.RMDF076.UINT16[R_IO_L])
     4164#define RSCAN0RMDF076LL (RSCAN0.RMDF076.UINT8[R_IO_LL])
     4165#define RSCAN0RMDF076LH (RSCAN0.RMDF076.UINT8[R_IO_LH])
     4166#define RSCAN0RMDF076H (RSCAN0.RMDF076.UINT16[R_IO_H])
     4167#define RSCAN0RMDF076HL (RSCAN0.RMDF076.UINT8[R_IO_HL])
     4168#define RSCAN0RMDF076HH (RSCAN0.RMDF076.UINT8[R_IO_HH])
     4169#define RSCAN0RMDF176 (RSCAN0.RMDF176.UINT32)
     4170#define RSCAN0RMDF176L (RSCAN0.RMDF176.UINT16[R_IO_L])
     4171#define RSCAN0RMDF176LL (RSCAN0.RMDF176.UINT8[R_IO_LL])
     4172#define RSCAN0RMDF176LH (RSCAN0.RMDF176.UINT8[R_IO_LH])
     4173#define RSCAN0RMDF176H (RSCAN0.RMDF176.UINT16[R_IO_H])
     4174#define RSCAN0RMDF176HL (RSCAN0.RMDF176.UINT8[R_IO_HL])
     4175#define RSCAN0RMDF176HH (RSCAN0.RMDF176.UINT8[R_IO_HH])
     4176#define RSCAN0RMID77 (RSCAN0.RMID77.UINT32)
     4177#define RSCAN0RMID77L (RSCAN0.RMID77.UINT16[R_IO_L])
     4178#define RSCAN0RMID77LL (RSCAN0.RMID77.UINT8[R_IO_LL])
     4179#define RSCAN0RMID77LH (RSCAN0.RMID77.UINT8[R_IO_LH])
     4180#define RSCAN0RMID77H (RSCAN0.RMID77.UINT16[R_IO_H])
     4181#define RSCAN0RMID77HL (RSCAN0.RMID77.UINT8[R_IO_HL])
     4182#define RSCAN0RMID77HH (RSCAN0.RMID77.UINT8[R_IO_HH])
     4183#define RSCAN0RMPTR77 (RSCAN0.RMPTR77.UINT32)
     4184#define RSCAN0RMPTR77L (RSCAN0.RMPTR77.UINT16[R_IO_L])
     4185#define RSCAN0RMPTR77LL (RSCAN0.RMPTR77.UINT8[R_IO_LL])
     4186#define RSCAN0RMPTR77LH (RSCAN0.RMPTR77.UINT8[R_IO_LH])
     4187#define RSCAN0RMPTR77H (RSCAN0.RMPTR77.UINT16[R_IO_H])
     4188#define RSCAN0RMPTR77HL (RSCAN0.RMPTR77.UINT8[R_IO_HL])
     4189#define RSCAN0RMPTR77HH (RSCAN0.RMPTR77.UINT8[R_IO_HH])
     4190#define RSCAN0RMDF077 (RSCAN0.RMDF077.UINT32)
     4191#define RSCAN0RMDF077L (RSCAN0.RMDF077.UINT16[R_IO_L])
     4192#define RSCAN0RMDF077LL (RSCAN0.RMDF077.UINT8[R_IO_LL])
     4193#define RSCAN0RMDF077LH (RSCAN0.RMDF077.UINT8[R_IO_LH])
     4194#define RSCAN0RMDF077H (RSCAN0.RMDF077.UINT16[R_IO_H])
     4195#define RSCAN0RMDF077HL (RSCAN0.RMDF077.UINT8[R_IO_HL])
     4196#define RSCAN0RMDF077HH (RSCAN0.RMDF077.UINT8[R_IO_HH])
     4197#define RSCAN0RMDF177 (RSCAN0.RMDF177.UINT32)
     4198#define RSCAN0RMDF177L (RSCAN0.RMDF177.UINT16[R_IO_L])
     4199#define RSCAN0RMDF177LL (RSCAN0.RMDF177.UINT8[R_IO_LL])
     4200#define RSCAN0RMDF177LH (RSCAN0.RMDF177.UINT8[R_IO_LH])
     4201#define RSCAN0RMDF177H (RSCAN0.RMDF177.UINT16[R_IO_H])
     4202#define RSCAN0RMDF177HL (RSCAN0.RMDF177.UINT8[R_IO_HL])
     4203#define RSCAN0RMDF177HH (RSCAN0.RMDF177.UINT8[R_IO_HH])
     4204#define RSCAN0RMID78 (RSCAN0.RMID78.UINT32)
     4205#define RSCAN0RMID78L (RSCAN0.RMID78.UINT16[R_IO_L])
     4206#define RSCAN0RMID78LL (RSCAN0.RMID78.UINT8[R_IO_LL])
     4207#define RSCAN0RMID78LH (RSCAN0.RMID78.UINT8[R_IO_LH])
     4208#define RSCAN0RMID78H (RSCAN0.RMID78.UINT16[R_IO_H])
     4209#define RSCAN0RMID78HL (RSCAN0.RMID78.UINT8[R_IO_HL])
     4210#define RSCAN0RMID78HH (RSCAN0.RMID78.UINT8[R_IO_HH])
     4211#define RSCAN0RMPTR78 (RSCAN0.RMPTR78.UINT32)
     4212#define RSCAN0RMPTR78L (RSCAN0.RMPTR78.UINT16[R_IO_L])
     4213#define RSCAN0RMPTR78LL (RSCAN0.RMPTR78.UINT8[R_IO_LL])
     4214#define RSCAN0RMPTR78LH (RSCAN0.RMPTR78.UINT8[R_IO_LH])
     4215#define RSCAN0RMPTR78H (RSCAN0.RMPTR78.UINT16[R_IO_H])
     4216#define RSCAN0RMPTR78HL (RSCAN0.RMPTR78.UINT8[R_IO_HL])
     4217#define RSCAN0RMPTR78HH (RSCAN0.RMPTR78.UINT8[R_IO_HH])
     4218#define RSCAN0RMDF078 (RSCAN0.RMDF078.UINT32)
     4219#define RSCAN0RMDF078L (RSCAN0.RMDF078.UINT16[R_IO_L])
     4220#define RSCAN0RMDF078LL (RSCAN0.RMDF078.UINT8[R_IO_LL])
     4221#define RSCAN0RMDF078LH (RSCAN0.RMDF078.UINT8[R_IO_LH])
     4222#define RSCAN0RMDF078H (RSCAN0.RMDF078.UINT16[R_IO_H])
     4223#define RSCAN0RMDF078HL (RSCAN0.RMDF078.UINT8[R_IO_HL])
     4224#define RSCAN0RMDF078HH (RSCAN0.RMDF078.UINT8[R_IO_HH])
     4225#define RSCAN0RMDF178 (RSCAN0.RMDF178.UINT32)
     4226#define RSCAN0RMDF178L (RSCAN0.RMDF178.UINT16[R_IO_L])
     4227#define RSCAN0RMDF178LL (RSCAN0.RMDF178.UINT8[R_IO_LL])
     4228#define RSCAN0RMDF178LH (RSCAN0.RMDF178.UINT8[R_IO_LH])
     4229#define RSCAN0RMDF178H (RSCAN0.RMDF178.UINT16[R_IO_H])
     4230#define RSCAN0RMDF178HL (RSCAN0.RMDF178.UINT8[R_IO_HL])
     4231#define RSCAN0RMDF178HH (RSCAN0.RMDF178.UINT8[R_IO_HH])
     4232#define RSCAN0RMID79 (RSCAN0.RMID79.UINT32)
     4233#define RSCAN0RMID79L (RSCAN0.RMID79.UINT16[R_IO_L])
     4234#define RSCAN0RMID79LL (RSCAN0.RMID79.UINT8[R_IO_LL])
     4235#define RSCAN0RMID79LH (RSCAN0.RMID79.UINT8[R_IO_LH])
     4236#define RSCAN0RMID79H (RSCAN0.RMID79.UINT16[R_IO_H])
     4237#define RSCAN0RMID79HL (RSCAN0.RMID79.UINT8[R_IO_HL])
     4238#define RSCAN0RMID79HH (RSCAN0.RMID79.UINT8[R_IO_HH])
     4239#define RSCAN0RMPTR79 (RSCAN0.RMPTR79.UINT32)
     4240#define RSCAN0RMPTR79L (RSCAN0.RMPTR79.UINT16[R_IO_L])
     4241#define RSCAN0RMPTR79LL (RSCAN0.RMPTR79.UINT8[R_IO_LL])
     4242#define RSCAN0RMPTR79LH (RSCAN0.RMPTR79.UINT8[R_IO_LH])
     4243#define RSCAN0RMPTR79H (RSCAN0.RMPTR79.UINT16[R_IO_H])
     4244#define RSCAN0RMPTR79HL (RSCAN0.RMPTR79.UINT8[R_IO_HL])
     4245#define RSCAN0RMPTR79HH (RSCAN0.RMPTR79.UINT8[R_IO_HH])
     4246#define RSCAN0RMDF079 (RSCAN0.RMDF079.UINT32)
     4247#define RSCAN0RMDF079L (RSCAN0.RMDF079.UINT16[R_IO_L])
     4248#define RSCAN0RMDF079LL (RSCAN0.RMDF079.UINT8[R_IO_LL])
     4249#define RSCAN0RMDF079LH (RSCAN0.RMDF079.UINT8[R_IO_LH])
     4250#define RSCAN0RMDF079H (RSCAN0.RMDF079.UINT16[R_IO_H])
     4251#define RSCAN0RMDF079HL (RSCAN0.RMDF079.UINT8[R_IO_HL])
     4252#define RSCAN0RMDF079HH (RSCAN0.RMDF079.UINT8[R_IO_HH])
     4253#define RSCAN0RMDF179 (RSCAN0.RMDF179.UINT32)
     4254#define RSCAN0RMDF179L (RSCAN0.RMDF179.UINT16[R_IO_L])
     4255#define RSCAN0RMDF179LL (RSCAN0.RMDF179.UINT8[R_IO_LL])
     4256#define RSCAN0RMDF179LH (RSCAN0.RMDF179.UINT8[R_IO_LH])
     4257#define RSCAN0RMDF179H (RSCAN0.RMDF179.UINT16[R_IO_H])
     4258#define RSCAN0RMDF179HL (RSCAN0.RMDF179.UINT8[R_IO_HL])
     4259#define RSCAN0RMDF179HH (RSCAN0.RMDF179.UINT8[R_IO_HH])
     4260#define RSCAN0RFID0 (RSCAN0.RFID0.UINT32)
     4261#define RSCAN0RFID0L (RSCAN0.RFID0.UINT16[R_IO_L])
     4262#define RSCAN0RFID0LL (RSCAN0.RFID0.UINT8[R_IO_LL])
     4263#define RSCAN0RFID0LH (RSCAN0.RFID0.UINT8[R_IO_LH])
     4264#define RSCAN0RFID0H (RSCAN0.RFID0.UINT16[R_IO_H])
     4265#define RSCAN0RFID0HL (RSCAN0.RFID0.UINT8[R_IO_HL])
     4266#define RSCAN0RFID0HH (RSCAN0.RFID0.UINT8[R_IO_HH])
     4267#define RSCAN0RFPTR0 (RSCAN0.RFPTR0.UINT32)
     4268#define RSCAN0RFPTR0L (RSCAN0.RFPTR0.UINT16[R_IO_L])
     4269#define RSCAN0RFPTR0LL (RSCAN0.RFPTR0.UINT8[R_IO_LL])
     4270#define RSCAN0RFPTR0LH (RSCAN0.RFPTR0.UINT8[R_IO_LH])
     4271#define RSCAN0RFPTR0H (RSCAN0.RFPTR0.UINT16[R_IO_H])
     4272#define RSCAN0RFPTR0HL (RSCAN0.RFPTR0.UINT8[R_IO_HL])
     4273#define RSCAN0RFPTR0HH (RSCAN0.RFPTR0.UINT8[R_IO_HH])
     4274#define RSCAN0RFDF00 (RSCAN0.RFDF00.UINT32)
     4275#define RSCAN0RFDF00L (RSCAN0.RFDF00.UINT16[R_IO_L])
     4276#define RSCAN0RFDF00LL (RSCAN0.RFDF00.UINT8[R_IO_LL])
     4277#define RSCAN0RFDF00LH (RSCAN0.RFDF00.UINT8[R_IO_LH])
     4278#define RSCAN0RFDF00H (RSCAN0.RFDF00.UINT16[R_IO_H])
     4279#define RSCAN0RFDF00HL (RSCAN0.RFDF00.UINT8[R_IO_HL])
     4280#define RSCAN0RFDF00HH (RSCAN0.RFDF00.UINT8[R_IO_HH])
     4281#define RSCAN0RFDF10 (RSCAN0.RFDF10.UINT32)
     4282#define RSCAN0RFDF10L (RSCAN0.RFDF10.UINT16[R_IO_L])
     4283#define RSCAN0RFDF10LL (RSCAN0.RFDF10.UINT8[R_IO_LL])
     4284#define RSCAN0RFDF10LH (RSCAN0.RFDF10.UINT8[R_IO_LH])
     4285#define RSCAN0RFDF10H (RSCAN0.RFDF10.UINT16[R_IO_H])
     4286#define RSCAN0RFDF10HL (RSCAN0.RFDF10.UINT8[R_IO_HL])
     4287#define RSCAN0RFDF10HH (RSCAN0.RFDF10.UINT8[R_IO_HH])
     4288#define RSCAN0RFID1 (RSCAN0.RFID1.UINT32)
     4289#define RSCAN0RFID1L (RSCAN0.RFID1.UINT16[R_IO_L])
     4290#define RSCAN0RFID1LL (RSCAN0.RFID1.UINT8[R_IO_LL])
     4291#define RSCAN0RFID1LH (RSCAN0.RFID1.UINT8[R_IO_LH])
     4292#define RSCAN0RFID1H (RSCAN0.RFID1.UINT16[R_IO_H])
     4293#define RSCAN0RFID1HL (RSCAN0.RFID1.UINT8[R_IO_HL])
     4294#define RSCAN0RFID1HH (RSCAN0.RFID1.UINT8[R_IO_HH])
     4295#define RSCAN0RFPTR1 (RSCAN0.RFPTR1.UINT32)
     4296#define RSCAN0RFPTR1L (RSCAN0.RFPTR1.UINT16[R_IO_L])
     4297#define RSCAN0RFPTR1LL (RSCAN0.RFPTR1.UINT8[R_IO_LL])
     4298#define RSCAN0RFPTR1LH (RSCAN0.RFPTR1.UINT8[R_IO_LH])
     4299#define RSCAN0RFPTR1H (RSCAN0.RFPTR1.UINT16[R_IO_H])
     4300#define RSCAN0RFPTR1HL (RSCAN0.RFPTR1.UINT8[R_IO_HL])
     4301#define RSCAN0RFPTR1HH (RSCAN0.RFPTR1.UINT8[R_IO_HH])
     4302#define RSCAN0RFDF01 (RSCAN0.RFDF01.UINT32)
     4303#define RSCAN0RFDF01L (RSCAN0.RFDF01.UINT16[R_IO_L])
     4304#define RSCAN0RFDF01LL (RSCAN0.RFDF01.UINT8[R_IO_LL])
     4305#define RSCAN0RFDF01LH (RSCAN0.RFDF01.UINT8[R_IO_LH])
     4306#define RSCAN0RFDF01H (RSCAN0.RFDF01.UINT16[R_IO_H])
     4307#define RSCAN0RFDF01HL (RSCAN0.RFDF01.UINT8[R_IO_HL])
     4308#define RSCAN0RFDF01HH (RSCAN0.RFDF01.UINT8[R_IO_HH])
     4309#define RSCAN0RFDF11 (RSCAN0.RFDF11.UINT32)
     4310#define RSCAN0RFDF11L (RSCAN0.RFDF11.UINT16[R_IO_L])
     4311#define RSCAN0RFDF11LL (RSCAN0.RFDF11.UINT8[R_IO_LL])
     4312#define RSCAN0RFDF11LH (RSCAN0.RFDF11.UINT8[R_IO_LH])
     4313#define RSCAN0RFDF11H (RSCAN0.RFDF11.UINT16[R_IO_H])
     4314#define RSCAN0RFDF11HL (RSCAN0.RFDF11.UINT8[R_IO_HL])
     4315#define RSCAN0RFDF11HH (RSCAN0.RFDF11.UINT8[R_IO_HH])
     4316#define RSCAN0RFID2 (RSCAN0.RFID2.UINT32)
     4317#define RSCAN0RFID2L (RSCAN0.RFID2.UINT16[R_IO_L])
     4318#define RSCAN0RFID2LL (RSCAN0.RFID2.UINT8[R_IO_LL])
     4319#define RSCAN0RFID2LH (RSCAN0.RFID2.UINT8[R_IO_LH])
     4320#define RSCAN0RFID2H (RSCAN0.RFID2.UINT16[R_IO_H])
     4321#define RSCAN0RFID2HL (RSCAN0.RFID2.UINT8[R_IO_HL])
     4322#define RSCAN0RFID2HH (RSCAN0.RFID2.UINT8[R_IO_HH])
     4323#define RSCAN0RFPTR2 (RSCAN0.RFPTR2.UINT32)
     4324#define RSCAN0RFPTR2L (RSCAN0.RFPTR2.UINT16[R_IO_L])
     4325#define RSCAN0RFPTR2LL (RSCAN0.RFPTR2.UINT8[R_IO_LL])
     4326#define RSCAN0RFPTR2LH (RSCAN0.RFPTR2.UINT8[R_IO_LH])
     4327#define RSCAN0RFPTR2H (RSCAN0.RFPTR2.UINT16[R_IO_H])
     4328#define RSCAN0RFPTR2HL (RSCAN0.RFPTR2.UINT8[R_IO_HL])
     4329#define RSCAN0RFPTR2HH (RSCAN0.RFPTR2.UINT8[R_IO_HH])
     4330#define RSCAN0RFDF02 (RSCAN0.RFDF02.UINT32)
     4331#define RSCAN0RFDF02L (RSCAN0.RFDF02.UINT16[R_IO_L])
     4332#define RSCAN0RFDF02LL (RSCAN0.RFDF02.UINT8[R_IO_LL])
     4333#define RSCAN0RFDF02LH (RSCAN0.RFDF02.UINT8[R_IO_LH])
     4334#define RSCAN0RFDF02H (RSCAN0.RFDF02.UINT16[R_IO_H])
     4335#define RSCAN0RFDF02HL (RSCAN0.RFDF02.UINT8[R_IO_HL])
     4336#define RSCAN0RFDF02HH (RSCAN0.RFDF02.UINT8[R_IO_HH])
     4337#define RSCAN0RFDF12 (RSCAN0.RFDF12.UINT32)
     4338#define RSCAN0RFDF12L (RSCAN0.RFDF12.UINT16[R_IO_L])
     4339#define RSCAN0RFDF12LL (RSCAN0.RFDF12.UINT8[R_IO_LL])
     4340#define RSCAN0RFDF12LH (RSCAN0.RFDF12.UINT8[R_IO_LH])
     4341#define RSCAN0RFDF12H (RSCAN0.RFDF12.UINT16[R_IO_H])
     4342#define RSCAN0RFDF12HL (RSCAN0.RFDF12.UINT8[R_IO_HL])
     4343#define RSCAN0RFDF12HH (RSCAN0.RFDF12.UINT8[R_IO_HH])
     4344#define RSCAN0RFID3 (RSCAN0.RFID3.UINT32)
     4345#define RSCAN0RFID3L (RSCAN0.RFID3.UINT16[R_IO_L])
     4346#define RSCAN0RFID3LL (RSCAN0.RFID3.UINT8[R_IO_LL])
     4347#define RSCAN0RFID3LH (RSCAN0.RFID3.UINT8[R_IO_LH])
     4348#define RSCAN0RFID3H (RSCAN0.RFID3.UINT16[R_IO_H])
     4349#define RSCAN0RFID3HL (RSCAN0.RFID3.UINT8[R_IO_HL])
     4350#define RSCAN0RFID3HH (RSCAN0.RFID3.UINT8[R_IO_HH])
     4351#define RSCAN0RFPTR3 (RSCAN0.RFPTR3.UINT32)
     4352#define RSCAN0RFPTR3L (RSCAN0.RFPTR3.UINT16[R_IO_L])
     4353#define RSCAN0RFPTR3LL (RSCAN0.RFPTR3.UINT8[R_IO_LL])
     4354#define RSCAN0RFPTR3LH (RSCAN0.RFPTR3.UINT8[R_IO_LH])
     4355#define RSCAN0RFPTR3H (RSCAN0.RFPTR3.UINT16[R_IO_H])
     4356#define RSCAN0RFPTR3HL (RSCAN0.RFPTR3.UINT8[R_IO_HL])
     4357#define RSCAN0RFPTR3HH (RSCAN0.RFPTR3.UINT8[R_IO_HH])
     4358#define RSCAN0RFDF03 (RSCAN0.RFDF03.UINT32)
     4359#define RSCAN0RFDF03L (RSCAN0.RFDF03.UINT16[R_IO_L])
     4360#define RSCAN0RFDF03LL (RSCAN0.RFDF03.UINT8[R_IO_LL])
     4361#define RSCAN0RFDF03LH (RSCAN0.RFDF03.UINT8[R_IO_LH])
     4362#define RSCAN0RFDF03H (RSCAN0.RFDF03.UINT16[R_IO_H])
     4363#define RSCAN0RFDF03HL (RSCAN0.RFDF03.UINT8[R_IO_HL])
     4364#define RSCAN0RFDF03HH (RSCAN0.RFDF03.UINT8[R_IO_HH])
     4365#define RSCAN0RFDF13 (RSCAN0.RFDF13.UINT32)
     4366#define RSCAN0RFDF13L (RSCAN0.RFDF13.UINT16[R_IO_L])
     4367#define RSCAN0RFDF13LL (RSCAN0.RFDF13.UINT8[R_IO_LL])
     4368#define RSCAN0RFDF13LH (RSCAN0.RFDF13.UINT8[R_IO_LH])
     4369#define RSCAN0RFDF13H (RSCAN0.RFDF13.UINT16[R_IO_H])
     4370#define RSCAN0RFDF13HL (RSCAN0.RFDF13.UINT8[R_IO_HL])
     4371#define RSCAN0RFDF13HH (RSCAN0.RFDF13.UINT8[R_IO_HH])
     4372#define RSCAN0RFID4 (RSCAN0.RFID4.UINT32)
     4373#define RSCAN0RFID4L (RSCAN0.RFID4.UINT16[R_IO_L])
     4374#define RSCAN0RFID4LL (RSCAN0.RFID4.UINT8[R_IO_LL])
     4375#define RSCAN0RFID4LH (RSCAN0.RFID4.UINT8[R_IO_LH])
     4376#define RSCAN0RFID4H (RSCAN0.RFID4.UINT16[R_IO_H])
     4377#define RSCAN0RFID4HL (RSCAN0.RFID4.UINT8[R_IO_HL])
     4378#define RSCAN0RFID4HH (RSCAN0.RFID4.UINT8[R_IO_HH])
     4379#define RSCAN0RFPTR4 (RSCAN0.RFPTR4.UINT32)
     4380#define RSCAN0RFPTR4L (RSCAN0.RFPTR4.UINT16[R_IO_L])
     4381#define RSCAN0RFPTR4LL (RSCAN0.RFPTR4.UINT8[R_IO_LL])
     4382#define RSCAN0RFPTR4LH (RSCAN0.RFPTR4.UINT8[R_IO_LH])
     4383#define RSCAN0RFPTR4H (RSCAN0.RFPTR4.UINT16[R_IO_H])
     4384#define RSCAN0RFPTR4HL (RSCAN0.RFPTR4.UINT8[R_IO_HL])
     4385#define RSCAN0RFPTR4HH (RSCAN0.RFPTR4.UINT8[R_IO_HH])
     4386#define RSCAN0RFDF04 (RSCAN0.RFDF04.UINT32)
     4387#define RSCAN0RFDF04L (RSCAN0.RFDF04.UINT16[R_IO_L])
     4388#define RSCAN0RFDF04LL (RSCAN0.RFDF04.UINT8[R_IO_LL])
     4389#define RSCAN0RFDF04LH (RSCAN0.RFDF04.UINT8[R_IO_LH])
     4390#define RSCAN0RFDF04H (RSCAN0.RFDF04.UINT16[R_IO_H])
     4391#define RSCAN0RFDF04HL (RSCAN0.RFDF04.UINT8[R_IO_HL])
     4392#define RSCAN0RFDF04HH (RSCAN0.RFDF04.UINT8[R_IO_HH])
     4393#define RSCAN0RFDF14 (RSCAN0.RFDF14.UINT32)
     4394#define RSCAN0RFDF14L (RSCAN0.RFDF14.UINT16[R_IO_L])
     4395#define RSCAN0RFDF14LL (RSCAN0.RFDF14.UINT8[R_IO_LL])
     4396#define RSCAN0RFDF14LH (RSCAN0.RFDF14.UINT8[R_IO_LH])
     4397#define RSCAN0RFDF14H (RSCAN0.RFDF14.UINT16[R_IO_H])
     4398#define RSCAN0RFDF14HL (RSCAN0.RFDF14.UINT8[R_IO_HL])
     4399#define RSCAN0RFDF14HH (RSCAN0.RFDF14.UINT8[R_IO_HH])
     4400#define RSCAN0RFID5 (RSCAN0.RFID5.UINT32)
     4401#define RSCAN0RFID5L (RSCAN0.RFID5.UINT16[R_IO_L])
     4402#define RSCAN0RFID5LL (RSCAN0.RFID5.UINT8[R_IO_LL])
     4403#define RSCAN0RFID5LH (RSCAN0.RFID5.UINT8[R_IO_LH])
     4404#define RSCAN0RFID5H (RSCAN0.RFID5.UINT16[R_IO_H])
     4405#define RSCAN0RFID5HL (RSCAN0.RFID5.UINT8[R_IO_HL])
     4406#define RSCAN0RFID5HH (RSCAN0.RFID5.UINT8[R_IO_HH])
     4407#define RSCAN0RFPTR5 (RSCAN0.RFPTR5.UINT32)
     4408#define RSCAN0RFPTR5L (RSCAN0.RFPTR5.UINT16[R_IO_L])
     4409#define RSCAN0RFPTR5LL (RSCAN0.RFPTR5.UINT8[R_IO_LL])
     4410#define RSCAN0RFPTR5LH (RSCAN0.RFPTR5.UINT8[R_IO_LH])
     4411#define RSCAN0RFPTR5H (RSCAN0.RFPTR5.UINT16[R_IO_H])
     4412#define RSCAN0RFPTR5HL (RSCAN0.RFPTR5.UINT8[R_IO_HL])
     4413#define RSCAN0RFPTR5HH (RSCAN0.RFPTR5.UINT8[R_IO_HH])
     4414#define RSCAN0RFDF05 (RSCAN0.RFDF05.UINT32)
     4415#define RSCAN0RFDF05L (RSCAN0.RFDF05.UINT16[R_IO_L])
     4416#define RSCAN0RFDF05LL (RSCAN0.RFDF05.UINT8[R_IO_LL])
     4417#define RSCAN0RFDF05LH (RSCAN0.RFDF05.UINT8[R_IO_LH])
     4418#define RSCAN0RFDF05H (RSCAN0.RFDF05.UINT16[R_IO_H])
     4419#define RSCAN0RFDF05HL (RSCAN0.RFDF05.UINT8[R_IO_HL])
     4420#define RSCAN0RFDF05HH (RSCAN0.RFDF05.UINT8[R_IO_HH])
     4421#define RSCAN0RFDF15 (RSCAN0.RFDF15.UINT32)
     4422#define RSCAN0RFDF15L (RSCAN0.RFDF15.UINT16[R_IO_L])
     4423#define RSCAN0RFDF15LL (RSCAN0.RFDF15.UINT8[R_IO_LL])
     4424#define RSCAN0RFDF15LH (RSCAN0.RFDF15.UINT8[R_IO_LH])
     4425#define RSCAN0RFDF15H (RSCAN0.RFDF15.UINT16[R_IO_H])
     4426#define RSCAN0RFDF15HL (RSCAN0.RFDF15.UINT8[R_IO_HL])
     4427#define RSCAN0RFDF15HH (RSCAN0.RFDF15.UINT8[R_IO_HH])
     4428#define RSCAN0RFID6 (RSCAN0.RFID6.UINT32)
     4429#define RSCAN0RFID6L (RSCAN0.RFID6.UINT16[R_IO_L])
     4430#define RSCAN0RFID6LL (RSCAN0.RFID6.UINT8[R_IO_LL])
     4431#define RSCAN0RFID6LH (RSCAN0.RFID6.UINT8[R_IO_LH])
     4432#define RSCAN0RFID6H (RSCAN0.RFID6.UINT16[R_IO_H])
     4433#define RSCAN0RFID6HL (RSCAN0.RFID6.UINT8[R_IO_HL])
     4434#define RSCAN0RFID6HH (RSCAN0.RFID6.UINT8[R_IO_HH])
     4435#define RSCAN0RFPTR6 (RSCAN0.RFPTR6.UINT32)
     4436#define RSCAN0RFPTR6L (RSCAN0.RFPTR6.UINT16[R_IO_L])
     4437#define RSCAN0RFPTR6LL (RSCAN0.RFPTR6.UINT8[R_IO_LL])
     4438#define RSCAN0RFPTR6LH (RSCAN0.RFPTR6.UINT8[R_IO_LH])
     4439#define RSCAN0RFPTR6H (RSCAN0.RFPTR6.UINT16[R_IO_H])
     4440#define RSCAN0RFPTR6HL (RSCAN0.RFPTR6.UINT8[R_IO_HL])
     4441#define RSCAN0RFPTR6HH (RSCAN0.RFPTR6.UINT8[R_IO_HH])
     4442#define RSCAN0RFDF06 (RSCAN0.RFDF06.UINT32)
     4443#define RSCAN0RFDF06L (RSCAN0.RFDF06.UINT16[R_IO_L])
     4444#define RSCAN0RFDF06LL (RSCAN0.RFDF06.UINT8[R_IO_LL])
     4445#define RSCAN0RFDF06LH (RSCAN0.RFDF06.UINT8[R_IO_LH])
     4446#define RSCAN0RFDF06H (RSCAN0.RFDF06.UINT16[R_IO_H])
     4447#define RSCAN0RFDF06HL (RSCAN0.RFDF06.UINT8[R_IO_HL])
     4448#define RSCAN0RFDF06HH (RSCAN0.RFDF06.UINT8[R_IO_HH])
     4449#define RSCAN0RFDF16 (RSCAN0.RFDF16.UINT32)
     4450#define RSCAN0RFDF16L (RSCAN0.RFDF16.UINT16[R_IO_L])
     4451#define RSCAN0RFDF16LL (RSCAN0.RFDF16.UINT8[R_IO_LL])
     4452#define RSCAN0RFDF16LH (RSCAN0.RFDF16.UINT8[R_IO_LH])
     4453#define RSCAN0RFDF16H (RSCAN0.RFDF16.UINT16[R_IO_H])
     4454#define RSCAN0RFDF16HL (RSCAN0.RFDF16.UINT8[R_IO_HL])
     4455#define RSCAN0RFDF16HH (RSCAN0.RFDF16.UINT8[R_IO_HH])
     4456#define RSCAN0RFID7 (RSCAN0.RFID7.UINT32)
     4457#define RSCAN0RFID7L (RSCAN0.RFID7.UINT16[R_IO_L])
     4458#define RSCAN0RFID7LL (RSCAN0.RFID7.UINT8[R_IO_LL])
     4459#define RSCAN0RFID7LH (RSCAN0.RFID7.UINT8[R_IO_LH])
     4460#define RSCAN0RFID7H (RSCAN0.RFID7.UINT16[R_IO_H])
     4461#define RSCAN0RFID7HL (RSCAN0.RFID7.UINT8[R_IO_HL])
     4462#define RSCAN0RFID7HH (RSCAN0.RFID7.UINT8[R_IO_HH])
     4463#define RSCAN0RFPTR7 (RSCAN0.RFPTR7.UINT32)
     4464#define RSCAN0RFPTR7L (RSCAN0.RFPTR7.UINT16[R_IO_L])
     4465#define RSCAN0RFPTR7LL (RSCAN0.RFPTR7.UINT8[R_IO_LL])
     4466#define RSCAN0RFPTR7LH (RSCAN0.RFPTR7.UINT8[R_IO_LH])
     4467#define RSCAN0RFPTR7H (RSCAN0.RFPTR7.UINT16[R_IO_H])
     4468#define RSCAN0RFPTR7HL (RSCAN0.RFPTR7.UINT8[R_IO_HL])
     4469#define RSCAN0RFPTR7HH (RSCAN0.RFPTR7.UINT8[R_IO_HH])
     4470#define RSCAN0RFDF07 (RSCAN0.RFDF07.UINT32)
     4471#define RSCAN0RFDF07L (RSCAN0.RFDF07.UINT16[R_IO_L])
     4472#define RSCAN0RFDF07LL (RSCAN0.RFDF07.UINT8[R_IO_LL])
     4473#define RSCAN0RFDF07LH (RSCAN0.RFDF07.UINT8[R_IO_LH])
     4474#define RSCAN0RFDF07H (RSCAN0.RFDF07.UINT16[R_IO_H])
     4475#define RSCAN0RFDF07HL (RSCAN0.RFDF07.UINT8[R_IO_HL])
     4476#define RSCAN0RFDF07HH (RSCAN0.RFDF07.UINT8[R_IO_HH])
     4477#define RSCAN0RFDF17 (RSCAN0.RFDF17.UINT32)
     4478#define RSCAN0RFDF17L (RSCAN0.RFDF17.UINT16[R_IO_L])
     4479#define RSCAN0RFDF17LL (RSCAN0.RFDF17.UINT8[R_IO_LL])
     4480#define RSCAN0RFDF17LH (RSCAN0.RFDF17.UINT8[R_IO_LH])
     4481#define RSCAN0RFDF17H (RSCAN0.RFDF17.UINT16[R_IO_H])
     4482#define RSCAN0RFDF17HL (RSCAN0.RFDF17.UINT8[R_IO_HL])
     4483#define RSCAN0RFDF17HH (RSCAN0.RFDF17.UINT8[R_IO_HH])
     4484#define RSCAN0CFID0 (RSCAN0.CFID0.UINT32)
     4485#define RSCAN0CFID0L (RSCAN0.CFID0.UINT16[R_IO_L])
     4486#define RSCAN0CFID0LL (RSCAN0.CFID0.UINT8[R_IO_LL])
     4487#define RSCAN0CFID0LH (RSCAN0.CFID0.UINT8[R_IO_LH])
     4488#define RSCAN0CFID0H (RSCAN0.CFID0.UINT16[R_IO_H])
     4489#define RSCAN0CFID0HL (RSCAN0.CFID0.UINT8[R_IO_HL])
     4490#define RSCAN0CFID0HH (RSCAN0.CFID0.UINT8[R_IO_HH])
     4491#define RSCAN0CFPTR0 (RSCAN0.CFPTR0.UINT32)
     4492#define RSCAN0CFPTR0L (RSCAN0.CFPTR0.UINT16[R_IO_L])
     4493#define RSCAN0CFPTR0LL (RSCAN0.CFPTR0.UINT8[R_IO_LL])
     4494#define RSCAN0CFPTR0LH (RSCAN0.CFPTR0.UINT8[R_IO_LH])
     4495#define RSCAN0CFPTR0H (RSCAN0.CFPTR0.UINT16[R_IO_H])
     4496#define RSCAN0CFPTR0HL (RSCAN0.CFPTR0.UINT8[R_IO_HL])
     4497#define RSCAN0CFPTR0HH (RSCAN0.CFPTR0.UINT8[R_IO_HH])
     4498#define RSCAN0CFDF00 (RSCAN0.CFDF00.UINT32)
     4499#define RSCAN0CFDF00L (RSCAN0.CFDF00.UINT16[R_IO_L])
     4500#define RSCAN0CFDF00LL (RSCAN0.CFDF00.UINT8[R_IO_LL])
     4501#define RSCAN0CFDF00LH (RSCAN0.CFDF00.UINT8[R_IO_LH])
     4502#define RSCAN0CFDF00H (RSCAN0.CFDF00.UINT16[R_IO_H])
     4503#define RSCAN0CFDF00HL (RSCAN0.CFDF00.UINT8[R_IO_HL])
     4504#define RSCAN0CFDF00HH (RSCAN0.CFDF00.UINT8[R_IO_HH])
     4505#define RSCAN0CFDF10 (RSCAN0.CFDF10.UINT32)
     4506#define RSCAN0CFDF10L (RSCAN0.CFDF10.UINT16[R_IO_L])
     4507#define RSCAN0CFDF10LL (RSCAN0.CFDF10.UINT8[R_IO_LL])
     4508#define RSCAN0CFDF10LH (RSCAN0.CFDF10.UINT8[R_IO_LH])
     4509#define RSCAN0CFDF10H (RSCAN0.CFDF10.UINT16[R_IO_H])
     4510#define RSCAN0CFDF10HL (RSCAN0.CFDF10.UINT8[R_IO_HL])
     4511#define RSCAN0CFDF10HH (RSCAN0.CFDF10.UINT8[R_IO_HH])
     4512#define RSCAN0CFID1 (RSCAN0.CFID1.UINT32)
     4513#define RSCAN0CFID1L (RSCAN0.CFID1.UINT16[R_IO_L])
     4514#define RSCAN0CFID1LL (RSCAN0.CFID1.UINT8[R_IO_LL])
     4515#define RSCAN0CFID1LH (RSCAN0.CFID1.UINT8[R_IO_LH])
     4516#define RSCAN0CFID1H (RSCAN0.CFID1.UINT16[R_IO_H])
     4517#define RSCAN0CFID1HL (RSCAN0.CFID1.UINT8[R_IO_HL])
     4518#define RSCAN0CFID1HH (RSCAN0.CFID1.UINT8[R_IO_HH])
     4519#define RSCAN0CFPTR1 (RSCAN0.CFPTR1.UINT32)
     4520#define RSCAN0CFPTR1L (RSCAN0.CFPTR1.UINT16[R_IO_L])
     4521#define RSCAN0CFPTR1LL (RSCAN0.CFPTR1.UINT8[R_IO_LL])
     4522#define RSCAN0CFPTR1LH (RSCAN0.CFPTR1.UINT8[R_IO_LH])
     4523#define RSCAN0CFPTR1H (RSCAN0.CFPTR1.UINT16[R_IO_H])
     4524#define RSCAN0CFPTR1HL (RSCAN0.CFPTR1.UINT8[R_IO_HL])
     4525#define RSCAN0CFPTR1HH (RSCAN0.CFPTR1.UINT8[R_IO_HH])
     4526#define RSCAN0CFDF01 (RSCAN0.CFDF01.UINT32)
     4527#define RSCAN0CFDF01L (RSCAN0.CFDF01.UINT16[R_IO_L])
     4528#define RSCAN0CFDF01LL (RSCAN0.CFDF01.UINT8[R_IO_LL])
     4529#define RSCAN0CFDF01LH (RSCAN0.CFDF01.UINT8[R_IO_LH])
     4530#define RSCAN0CFDF01H (RSCAN0.CFDF01.UINT16[R_IO_H])
     4531#define RSCAN0CFDF01HL (RSCAN0.CFDF01.UINT8[R_IO_HL])
     4532#define RSCAN0CFDF01HH (RSCAN0.CFDF01.UINT8[R_IO_HH])
     4533#define RSCAN0CFDF11 (RSCAN0.CFDF11.UINT32)
     4534#define RSCAN0CFDF11L (RSCAN0.CFDF11.UINT16[R_IO_L])
     4535#define RSCAN0CFDF11LL (RSCAN0.CFDF11.UINT8[R_IO_LL])
     4536#define RSCAN0CFDF11LH (RSCAN0.CFDF11.UINT8[R_IO_LH])
     4537#define RSCAN0CFDF11H (RSCAN0.CFDF11.UINT16[R_IO_H])
     4538#define RSCAN0CFDF11HL (RSCAN0.CFDF11.UINT8[R_IO_HL])
     4539#define RSCAN0CFDF11HH (RSCAN0.CFDF11.UINT8[R_IO_HH])
     4540#define RSCAN0CFID2 (RSCAN0.CFID2.UINT32)
     4541#define RSCAN0CFID2L (RSCAN0.CFID2.UINT16[R_IO_L])
     4542#define RSCAN0CFID2LL (RSCAN0.CFID2.UINT8[R_IO_LL])
     4543#define RSCAN0CFID2LH (RSCAN0.CFID2.UINT8[R_IO_LH])
     4544#define RSCAN0CFID2H (RSCAN0.CFID2.UINT16[R_IO_H])
     4545#define RSCAN0CFID2HL (RSCAN0.CFID2.UINT8[R_IO_HL])
     4546#define RSCAN0CFID2HH (RSCAN0.CFID2.UINT8[R_IO_HH])
     4547#define RSCAN0CFPTR2 (RSCAN0.CFPTR2.UINT32)
     4548#define RSCAN0CFPTR2L (RSCAN0.CFPTR2.UINT16[R_IO_L])
     4549#define RSCAN0CFPTR2LL (RSCAN0.CFPTR2.UINT8[R_IO_LL])
     4550#define RSCAN0CFPTR2LH (RSCAN0.CFPTR2.UINT8[R_IO_LH])
     4551#define RSCAN0CFPTR2H (RSCAN0.CFPTR2.UINT16[R_IO_H])
     4552#define RSCAN0CFPTR2HL (RSCAN0.CFPTR2.UINT8[R_IO_HL])
     4553#define RSCAN0CFPTR2HH (RSCAN0.CFPTR2.UINT8[R_IO_HH])
     4554#define RSCAN0CFDF02 (RSCAN0.CFDF02.UINT32)
     4555#define RSCAN0CFDF02L (RSCAN0.CFDF02.UINT16[R_IO_L])
     4556#define RSCAN0CFDF02LL (RSCAN0.CFDF02.UINT8[R_IO_LL])
     4557#define RSCAN0CFDF02LH (RSCAN0.CFDF02.UINT8[R_IO_LH])
     4558#define RSCAN0CFDF02H (RSCAN0.CFDF02.UINT16[R_IO_H])
     4559#define RSCAN0CFDF02HL (RSCAN0.CFDF02.UINT8[R_IO_HL])
     4560#define RSCAN0CFDF02HH (RSCAN0.CFDF02.UINT8[R_IO_HH])
     4561#define RSCAN0CFDF12 (RSCAN0.CFDF12.UINT32)
     4562#define RSCAN0CFDF12L (RSCAN0.CFDF12.UINT16[R_IO_L])
     4563#define RSCAN0CFDF12LL (RSCAN0.CFDF12.UINT8[R_IO_LL])
     4564#define RSCAN0CFDF12LH (RSCAN0.CFDF12.UINT8[R_IO_LH])
     4565#define RSCAN0CFDF12H (RSCAN0.CFDF12.UINT16[R_IO_H])
     4566#define RSCAN0CFDF12HL (RSCAN0.CFDF12.UINT8[R_IO_HL])
     4567#define RSCAN0CFDF12HH (RSCAN0.CFDF12.UINT8[R_IO_HH])
     4568#define RSCAN0CFID3 (RSCAN0.CFID3.UINT32)
     4569#define RSCAN0CFID3L (RSCAN0.CFID3.UINT16[R_IO_L])
     4570#define RSCAN0CFID3LL (RSCAN0.CFID3.UINT8[R_IO_LL])
     4571#define RSCAN0CFID3LH (RSCAN0.CFID3.UINT8[R_IO_LH])
     4572#define RSCAN0CFID3H (RSCAN0.CFID3.UINT16[R_IO_H])
     4573#define RSCAN0CFID3HL (RSCAN0.CFID3.UINT8[R_IO_HL])
     4574#define RSCAN0CFID3HH (RSCAN0.CFID3.UINT8[R_IO_HH])
     4575#define RSCAN0CFPTR3 (RSCAN0.CFPTR3.UINT32)
     4576#define RSCAN0CFPTR3L (RSCAN0.CFPTR3.UINT16[R_IO_L])
     4577#define RSCAN0CFPTR3LL (RSCAN0.CFPTR3.UINT8[R_IO_LL])
     4578#define RSCAN0CFPTR3LH (RSCAN0.CFPTR3.UINT8[R_IO_LH])
     4579#define RSCAN0CFPTR3H (RSCAN0.CFPTR3.UINT16[R_IO_H])
     4580#define RSCAN0CFPTR3HL (RSCAN0.CFPTR3.UINT8[R_IO_HL])
     4581#define RSCAN0CFPTR3HH (RSCAN0.CFPTR3.UINT8[R_IO_HH])
     4582#define RSCAN0CFDF03 (RSCAN0.CFDF03.UINT32)
     4583#define RSCAN0CFDF03L (RSCAN0.CFDF03.UINT16[R_IO_L])
     4584#define RSCAN0CFDF03LL (RSCAN0.CFDF03.UINT8[R_IO_LL])
     4585#define RSCAN0CFDF03LH (RSCAN0.CFDF03.UINT8[R_IO_LH])
     4586#define RSCAN0CFDF03H (RSCAN0.CFDF03.UINT16[R_IO_H])
     4587#define RSCAN0CFDF03HL (RSCAN0.CFDF03.UINT8[R_IO_HL])
     4588#define RSCAN0CFDF03HH (RSCAN0.CFDF03.UINT8[R_IO_HH])
     4589#define RSCAN0CFDF13 (RSCAN0.CFDF13.UINT32)
     4590#define RSCAN0CFDF13L (RSCAN0.CFDF13.UINT16[R_IO_L])
     4591#define RSCAN0CFDF13LL (RSCAN0.CFDF13.UINT8[R_IO_LL])
     4592#define RSCAN0CFDF13LH (RSCAN0.CFDF13.UINT8[R_IO_LH])
     4593#define RSCAN0CFDF13H (RSCAN0.CFDF13.UINT16[R_IO_H])
     4594#define RSCAN0CFDF13HL (RSCAN0.CFDF13.UINT8[R_IO_HL])
     4595#define RSCAN0CFDF13HH (RSCAN0.CFDF13.UINT8[R_IO_HH])
     4596#define RSCAN0CFID4 (RSCAN0.CFID4.UINT32)
     4597#define RSCAN0CFID4L (RSCAN0.CFID4.UINT16[R_IO_L])
     4598#define RSCAN0CFID4LL (RSCAN0.CFID4.UINT8[R_IO_LL])
     4599#define RSCAN0CFID4LH (RSCAN0.CFID4.UINT8[R_IO_LH])
     4600#define RSCAN0CFID4H (RSCAN0.CFID4.UINT16[R_IO_H])
     4601#define RSCAN0CFID4HL (RSCAN0.CFID4.UINT8[R_IO_HL])
     4602#define RSCAN0CFID4HH (RSCAN0.CFID4.UINT8[R_IO_HH])
     4603#define RSCAN0CFPTR4 (RSCAN0.CFPTR4.UINT32)
     4604#define RSCAN0CFPTR4L (RSCAN0.CFPTR4.UINT16[R_IO_L])
     4605#define RSCAN0CFPTR4LL (RSCAN0.CFPTR4.UINT8[R_IO_LL])
     4606#define RSCAN0CFPTR4LH (RSCAN0.CFPTR4.UINT8[R_IO_LH])
     4607#define RSCAN0CFPTR4H (RSCAN0.CFPTR4.UINT16[R_IO_H])
     4608#define RSCAN0CFPTR4HL (RSCAN0.CFPTR4.UINT8[R_IO_HL])
     4609#define RSCAN0CFPTR4HH (RSCAN0.CFPTR4.UINT8[R_IO_HH])
     4610#define RSCAN0CFDF04 (RSCAN0.CFDF04.UINT32)
     4611#define RSCAN0CFDF04L (RSCAN0.CFDF04.UINT16[R_IO_L])
     4612#define RSCAN0CFDF04LL (RSCAN0.CFDF04.UINT8[R_IO_LL])
     4613#define RSCAN0CFDF04LH (RSCAN0.CFDF04.UINT8[R_IO_LH])
     4614#define RSCAN0CFDF04H (RSCAN0.CFDF04.UINT16[R_IO_H])
     4615#define RSCAN0CFDF04HL (RSCAN0.CFDF04.UINT8[R_IO_HL])
     4616#define RSCAN0CFDF04HH (RSCAN0.CFDF04.UINT8[R_IO_HH])
     4617#define RSCAN0CFDF14 (RSCAN0.CFDF14.UINT32)
     4618#define RSCAN0CFDF14L (RSCAN0.CFDF14.UINT16[R_IO_L])
     4619#define RSCAN0CFDF14LL (RSCAN0.CFDF14.UINT8[R_IO_LL])
     4620#define RSCAN0CFDF14LH (RSCAN0.CFDF14.UINT8[R_IO_LH])
     4621#define RSCAN0CFDF14H (RSCAN0.CFDF14.UINT16[R_IO_H])
     4622#define RSCAN0CFDF14HL (RSCAN0.CFDF14.UINT8[R_IO_HL])
     4623#define RSCAN0CFDF14HH (RSCAN0.CFDF14.UINT8[R_IO_HH])
     4624#define RSCAN0CFID5 (RSCAN0.CFID5.UINT32)
     4625#define RSCAN0CFID5L (RSCAN0.CFID5.UINT16[R_IO_L])
     4626#define RSCAN0CFID5LL (RSCAN0.CFID5.UINT8[R_IO_LL])
     4627#define RSCAN0CFID5LH (RSCAN0.CFID5.UINT8[R_IO_LH])
     4628#define RSCAN0CFID5H (RSCAN0.CFID5.UINT16[R_IO_H])
     4629#define RSCAN0CFID5HL (RSCAN0.CFID5.UINT8[R_IO_HL])
     4630#define RSCAN0CFID5HH (RSCAN0.CFID5.UINT8[R_IO_HH])
     4631#define RSCAN0CFPTR5 (RSCAN0.CFPTR5.UINT32)
     4632#define RSCAN0CFPTR5L (RSCAN0.CFPTR5.UINT16[R_IO_L])
     4633#define RSCAN0CFPTR5LL (RSCAN0.CFPTR5.UINT8[R_IO_LL])
     4634#define RSCAN0CFPTR5LH (RSCAN0.CFPTR5.UINT8[R_IO_LH])
     4635#define RSCAN0CFPTR5H (RSCAN0.CFPTR5.UINT16[R_IO_H])
     4636#define RSCAN0CFPTR5HL (RSCAN0.CFPTR5.UINT8[R_IO_HL])
     4637#define RSCAN0CFPTR5HH (RSCAN0.CFPTR5.UINT8[R_IO_HH])
     4638#define RSCAN0CFDF05 (RSCAN0.CFDF05.UINT32)
     4639#define RSCAN0CFDF05L (RSCAN0.CFDF05.UINT16[R_IO_L])
     4640#define RSCAN0CFDF05LL (RSCAN0.CFDF05.UINT8[R_IO_LL])
     4641#define RSCAN0CFDF05LH (RSCAN0.CFDF05.UINT8[R_IO_LH])
     4642#define RSCAN0CFDF05H (RSCAN0.CFDF05.UINT16[R_IO_H])
     4643#define RSCAN0CFDF05HL (RSCAN0.CFDF05.UINT8[R_IO_HL])
     4644#define RSCAN0CFDF05HH (RSCAN0.CFDF05.UINT8[R_IO_HH])
     4645#define RSCAN0CFDF15 (RSCAN0.CFDF15.UINT32)
     4646#define RSCAN0CFDF15L (RSCAN0.CFDF15.UINT16[R_IO_L])
     4647#define RSCAN0CFDF15LL (RSCAN0.CFDF15.UINT8[R_IO_LL])
     4648#define RSCAN0CFDF15LH (RSCAN0.CFDF15.UINT8[R_IO_LH])
     4649#define RSCAN0CFDF15H (RSCAN0.CFDF15.UINT16[R_IO_H])
     4650#define RSCAN0CFDF15HL (RSCAN0.CFDF15.UINT8[R_IO_HL])
     4651#define RSCAN0CFDF15HH (RSCAN0.CFDF15.UINT8[R_IO_HH])
     4652#define RSCAN0CFID6 (RSCAN0.CFID6.UINT32)
     4653#define RSCAN0CFID6L (RSCAN0.CFID6.UINT16[R_IO_L])
     4654#define RSCAN0CFID6LL (RSCAN0.CFID6.UINT8[R_IO_LL])
     4655#define RSCAN0CFID6LH (RSCAN0.CFID6.UINT8[R_IO_LH])
     4656#define RSCAN0CFID6H (RSCAN0.CFID6.UINT16[R_IO_H])
     4657#define RSCAN0CFID6HL (RSCAN0.CFID6.UINT8[R_IO_HL])
     4658#define RSCAN0CFID6HH (RSCAN0.CFID6.UINT8[R_IO_HH])
     4659#define RSCAN0CFPTR6 (RSCAN0.CFPTR6.UINT32)
     4660#define RSCAN0CFPTR6L (RSCAN0.CFPTR6.UINT16[R_IO_L])
     4661#define RSCAN0CFPTR6LL (RSCAN0.CFPTR6.UINT8[R_IO_LL])
     4662#define RSCAN0CFPTR6LH (RSCAN0.CFPTR6.UINT8[R_IO_LH])
     4663#define RSCAN0CFPTR6H (RSCAN0.CFPTR6.UINT16[R_IO_H])
     4664#define RSCAN0CFPTR6HL (RSCAN0.CFPTR6.UINT8[R_IO_HL])
     4665#define RSCAN0CFPTR6HH (RSCAN0.CFPTR6.UINT8[R_IO_HH])
     4666#define RSCAN0CFDF06 (RSCAN0.CFDF06.UINT32)
     4667#define RSCAN0CFDF06L (RSCAN0.CFDF06.UINT16[R_IO_L])
     4668#define RSCAN0CFDF06LL (RSCAN0.CFDF06.UINT8[R_IO_LL])
     4669#define RSCAN0CFDF06LH (RSCAN0.CFDF06.UINT8[R_IO_LH])
     4670#define RSCAN0CFDF06H (RSCAN0.CFDF06.UINT16[R_IO_H])
     4671#define RSCAN0CFDF06HL (RSCAN0.CFDF06.UINT8[R_IO_HL])
     4672#define RSCAN0CFDF06HH (RSCAN0.CFDF06.UINT8[R_IO_HH])
     4673#define RSCAN0CFDF16 (RSCAN0.CFDF16.UINT32)
     4674#define RSCAN0CFDF16L (RSCAN0.CFDF16.UINT16[R_IO_L])
     4675#define RSCAN0CFDF16LL (RSCAN0.CFDF16.UINT8[R_IO_LL])
     4676#define RSCAN0CFDF16LH (RSCAN0.CFDF16.UINT8[R_IO_LH])
     4677#define RSCAN0CFDF16H (RSCAN0.CFDF16.UINT16[R_IO_H])
     4678#define RSCAN0CFDF16HL (RSCAN0.CFDF16.UINT8[R_IO_HL])
     4679#define RSCAN0CFDF16HH (RSCAN0.CFDF16.UINT8[R_IO_HH])
     4680#define RSCAN0CFID7 (RSCAN0.CFID7.UINT32)
     4681#define RSCAN0CFID7L (RSCAN0.CFID7.UINT16[R_IO_L])
     4682#define RSCAN0CFID7LL (RSCAN0.CFID7.UINT8[R_IO_LL])
     4683#define RSCAN0CFID7LH (RSCAN0.CFID7.UINT8[R_IO_LH])
     4684#define RSCAN0CFID7H (RSCAN0.CFID7.UINT16[R_IO_H])
     4685#define RSCAN0CFID7HL (RSCAN0.CFID7.UINT8[R_IO_HL])
     4686#define RSCAN0CFID7HH (RSCAN0.CFID7.UINT8[R_IO_HH])
     4687#define RSCAN0CFPTR7 (RSCAN0.CFPTR7.UINT32)
     4688#define RSCAN0CFPTR7L (RSCAN0.CFPTR7.UINT16[R_IO_L])
     4689#define RSCAN0CFPTR7LL (RSCAN0.CFPTR7.UINT8[R_IO_LL])
     4690#define RSCAN0CFPTR7LH (RSCAN0.CFPTR7.UINT8[R_IO_LH])
     4691#define RSCAN0CFPTR7H (RSCAN0.CFPTR7.UINT16[R_IO_H])
     4692#define RSCAN0CFPTR7HL (RSCAN0.CFPTR7.UINT8[R_IO_HL])
     4693#define RSCAN0CFPTR7HH (RSCAN0.CFPTR7.UINT8[R_IO_HH])
     4694#define RSCAN0CFDF07 (RSCAN0.CFDF07.UINT32)
     4695#define RSCAN0CFDF07L (RSCAN0.CFDF07.UINT16[R_IO_L])
     4696#define RSCAN0CFDF07LL (RSCAN0.CFDF07.UINT8[R_IO_LL])
     4697#define RSCAN0CFDF07LH (RSCAN0.CFDF07.UINT8[R_IO_LH])
     4698#define RSCAN0CFDF07H (RSCAN0.CFDF07.UINT16[R_IO_H])
     4699#define RSCAN0CFDF07HL (RSCAN0.CFDF07.UINT8[R_IO_HL])
     4700#define RSCAN0CFDF07HH (RSCAN0.CFDF07.UINT8[R_IO_HH])
     4701#define RSCAN0CFDF17 (RSCAN0.CFDF17.UINT32)
     4702#define RSCAN0CFDF17L (RSCAN0.CFDF17.UINT16[R_IO_L])
     4703#define RSCAN0CFDF17LL (RSCAN0.CFDF17.UINT8[R_IO_LL])
     4704#define RSCAN0CFDF17LH (RSCAN0.CFDF17.UINT8[R_IO_LH])
     4705#define RSCAN0CFDF17H (RSCAN0.CFDF17.UINT16[R_IO_H])
     4706#define RSCAN0CFDF17HL (RSCAN0.CFDF17.UINT8[R_IO_HL])
     4707#define RSCAN0CFDF17HH (RSCAN0.CFDF17.UINT8[R_IO_HH])
     4708#define RSCAN0CFID8 (RSCAN0.CFID8.UINT32)
     4709#define RSCAN0CFID8L (RSCAN0.CFID8.UINT16[R_IO_L])
     4710#define RSCAN0CFID8LL (RSCAN0.CFID8.UINT8[R_IO_LL])
     4711#define RSCAN0CFID8LH (RSCAN0.CFID8.UINT8[R_IO_LH])
     4712#define RSCAN0CFID8H (RSCAN0.CFID8.UINT16[R_IO_H])
     4713#define RSCAN0CFID8HL (RSCAN0.CFID8.UINT8[R_IO_HL])
     4714#define RSCAN0CFID8HH (RSCAN0.CFID8.UINT8[R_IO_HH])
     4715#define RSCAN0CFPTR8 (RSCAN0.CFPTR8.UINT32)
     4716#define RSCAN0CFPTR8L (RSCAN0.CFPTR8.UINT16[R_IO_L])
     4717#define RSCAN0CFPTR8LL (RSCAN0.CFPTR8.UINT8[R_IO_LL])
     4718#define RSCAN0CFPTR8LH (RSCAN0.CFPTR8.UINT8[R_IO_LH])
     4719#define RSCAN0CFPTR8H (RSCAN0.CFPTR8.UINT16[R_IO_H])
     4720#define RSCAN0CFPTR8HL (RSCAN0.CFPTR8.UINT8[R_IO_HL])
     4721#define RSCAN0CFPTR8HH (RSCAN0.CFPTR8.UINT8[R_IO_HH])
     4722#define RSCAN0CFDF08 (RSCAN0.CFDF08.UINT32)
     4723#define RSCAN0CFDF08L (RSCAN0.CFDF08.UINT16[R_IO_L])
     4724#define RSCAN0CFDF08LL (RSCAN0.CFDF08.UINT8[R_IO_LL])
     4725#define RSCAN0CFDF08LH (RSCAN0.CFDF08.UINT8[R_IO_LH])
     4726#define RSCAN0CFDF08H (RSCAN0.CFDF08.UINT16[R_IO_H])
     4727#define RSCAN0CFDF08HL (RSCAN0.CFDF08.UINT8[R_IO_HL])
     4728#define RSCAN0CFDF08HH (RSCAN0.CFDF08.UINT8[R_IO_HH])
     4729#define RSCAN0CFDF18 (RSCAN0.CFDF18.UINT32)
     4730#define RSCAN0CFDF18L (RSCAN0.CFDF18.UINT16[R_IO_L])
     4731#define RSCAN0CFDF18LL (RSCAN0.CFDF18.UINT8[R_IO_LL])
     4732#define RSCAN0CFDF18LH (RSCAN0.CFDF18.UINT8[R_IO_LH])
     4733#define RSCAN0CFDF18H (RSCAN0.CFDF18.UINT16[R_IO_H])
     4734#define RSCAN0CFDF18HL (RSCAN0.CFDF18.UINT8[R_IO_HL])
     4735#define RSCAN0CFDF18HH (RSCAN0.CFDF18.UINT8[R_IO_HH])
     4736#define RSCAN0CFID9 (RSCAN0.CFID9.UINT32)
     4737#define RSCAN0CFID9L (RSCAN0.CFID9.UINT16[R_IO_L])
     4738#define RSCAN0CFID9LL (RSCAN0.CFID9.UINT8[R_IO_LL])
     4739#define RSCAN0CFID9LH (RSCAN0.CFID9.UINT8[R_IO_LH])
     4740#define RSCAN0CFID9H (RSCAN0.CFID9.UINT16[R_IO_H])
     4741#define RSCAN0CFID9HL (RSCAN0.CFID9.UINT8[R_IO_HL])
     4742#define RSCAN0CFID9HH (RSCAN0.CFID9.UINT8[R_IO_HH])
     4743#define RSCAN0CFPTR9 (RSCAN0.CFPTR9.UINT32)
     4744#define RSCAN0CFPTR9L (RSCAN0.CFPTR9.UINT16[R_IO_L])
     4745#define RSCAN0CFPTR9LL (RSCAN0.CFPTR9.UINT8[R_IO_LL])
     4746#define RSCAN0CFPTR9LH (RSCAN0.CFPTR9.UINT8[R_IO_LH])
     4747#define RSCAN0CFPTR9H (RSCAN0.CFPTR9.UINT16[R_IO_H])
     4748#define RSCAN0CFPTR9HL (RSCAN0.CFPTR9.UINT8[R_IO_HL])
     4749#define RSCAN0CFPTR9HH (RSCAN0.CFPTR9.UINT8[R_IO_HH])
     4750#define RSCAN0CFDF09 (RSCAN0.CFDF09.UINT32)
     4751#define RSCAN0CFDF09L (RSCAN0.CFDF09.UINT16[R_IO_L])
     4752#define RSCAN0CFDF09LL (RSCAN0.CFDF09.UINT8[R_IO_LL])
     4753#define RSCAN0CFDF09LH (RSCAN0.CFDF09.UINT8[R_IO_LH])
     4754#define RSCAN0CFDF09H (RSCAN0.CFDF09.UINT16[R_IO_H])
     4755#define RSCAN0CFDF09HL (RSCAN0.CFDF09.UINT8[R_IO_HL])
     4756#define RSCAN0CFDF09HH (RSCAN0.CFDF09.UINT8[R_IO_HH])
     4757#define RSCAN0CFDF19 (RSCAN0.CFDF19.UINT32)
     4758#define RSCAN0CFDF19L (RSCAN0.CFDF19.UINT16[R_IO_L])
     4759#define RSCAN0CFDF19LL (RSCAN0.CFDF19.UINT8[R_IO_LL])
     4760#define RSCAN0CFDF19LH (RSCAN0.CFDF19.UINT8[R_IO_LH])
     4761#define RSCAN0CFDF19H (RSCAN0.CFDF19.UINT16[R_IO_H])
     4762#define RSCAN0CFDF19HL (RSCAN0.CFDF19.UINT8[R_IO_HL])
     4763#define RSCAN0CFDF19HH (RSCAN0.CFDF19.UINT8[R_IO_HH])
     4764#define RSCAN0CFID10 (RSCAN0.CFID10.UINT32)
     4765#define RSCAN0CFID10L (RSCAN0.CFID10.UINT16[R_IO_L])
     4766#define RSCAN0CFID10LL (RSCAN0.CFID10.UINT8[R_IO_LL])
     4767#define RSCAN0CFID10LH (RSCAN0.CFID10.UINT8[R_IO_LH])
     4768#define RSCAN0CFID10H (RSCAN0.CFID10.UINT16[R_IO_H])
     4769#define RSCAN0CFID10HL (RSCAN0.CFID10.UINT8[R_IO_HL])
     4770#define RSCAN0CFID10HH (RSCAN0.CFID10.UINT8[R_IO_HH])
     4771#define RSCAN0CFPTR10 (RSCAN0.CFPTR10.UINT32)
     4772#define RSCAN0CFPTR10L (RSCAN0.CFPTR10.UINT16[R_IO_L])
     4773#define RSCAN0CFPTR10LL (RSCAN0.CFPTR10.UINT8[R_IO_LL])
     4774#define RSCAN0CFPTR10LH (RSCAN0.CFPTR10.UINT8[R_IO_LH])
     4775#define RSCAN0CFPTR10H (RSCAN0.CFPTR10.UINT16[R_IO_H])
     4776#define RSCAN0CFPTR10HL (RSCAN0.CFPTR10.UINT8[R_IO_HL])
     4777#define RSCAN0CFPTR10HH (RSCAN0.CFPTR10.UINT8[R_IO_HH])
     4778#define RSCAN0CFDF010 (RSCAN0.CFDF010.UINT32)
     4779#define RSCAN0CFDF010L (RSCAN0.CFDF010.UINT16[R_IO_L])
     4780#define RSCAN0CFDF010LL (RSCAN0.CFDF010.UINT8[R_IO_LL])
     4781#define RSCAN0CFDF010LH (RSCAN0.CFDF010.UINT8[R_IO_LH])
     4782#define RSCAN0CFDF010H (RSCAN0.CFDF010.UINT16[R_IO_H])
     4783#define RSCAN0CFDF010HL (RSCAN0.CFDF010.UINT8[R_IO_HL])
     4784#define RSCAN0CFDF010HH (RSCAN0.CFDF010.UINT8[R_IO_HH])
     4785#define RSCAN0CFDF110 (RSCAN0.CFDF110.UINT32)
     4786#define RSCAN0CFDF110L (RSCAN0.CFDF110.UINT16[R_IO_L])
     4787#define RSCAN0CFDF110LL (RSCAN0.CFDF110.UINT8[R_IO_LL])
     4788#define RSCAN0CFDF110LH (RSCAN0.CFDF110.UINT8[R_IO_LH])
     4789#define RSCAN0CFDF110H (RSCAN0.CFDF110.UINT16[R_IO_H])
     4790#define RSCAN0CFDF110HL (RSCAN0.CFDF110.UINT8[R_IO_HL])
     4791#define RSCAN0CFDF110HH (RSCAN0.CFDF110.UINT8[R_IO_HH])
     4792#define RSCAN0CFID11 (RSCAN0.CFID11.UINT32)
     4793#define RSCAN0CFID11L (RSCAN0.CFID11.UINT16[R_IO_L])
     4794#define RSCAN0CFID11LL (RSCAN0.CFID11.UINT8[R_IO_LL])
     4795#define RSCAN0CFID11LH (RSCAN0.CFID11.UINT8[R_IO_LH])
     4796#define RSCAN0CFID11H (RSCAN0.CFID11.UINT16[R_IO_H])
     4797#define RSCAN0CFID11HL (RSCAN0.CFID11.UINT8[R_IO_HL])
     4798#define RSCAN0CFID11HH (RSCAN0.CFID11.UINT8[R_IO_HH])
     4799#define RSCAN0CFPTR11 (RSCAN0.CFPTR11.UINT32)
     4800#define RSCAN0CFPTR11L (RSCAN0.CFPTR11.UINT16[R_IO_L])
     4801#define RSCAN0CFPTR11LL (RSCAN0.CFPTR11.UINT8[R_IO_LL])
     4802#define RSCAN0CFPTR11LH (RSCAN0.CFPTR11.UINT8[R_IO_LH])
     4803#define RSCAN0CFPTR11H (RSCAN0.CFPTR11.UINT16[R_IO_H])
     4804#define RSCAN0CFPTR11HL (RSCAN0.CFPTR11.UINT8[R_IO_HL])
     4805#define RSCAN0CFPTR11HH (RSCAN0.CFPTR11.UINT8[R_IO_HH])
     4806#define RSCAN0CFDF011 (RSCAN0.CFDF011.UINT32)
     4807#define RSCAN0CFDF011L (RSCAN0.CFDF011.UINT16[R_IO_L])
     4808#define RSCAN0CFDF011LL (RSCAN0.CFDF011.UINT8[R_IO_LL])
     4809#define RSCAN0CFDF011LH (RSCAN0.CFDF011.UINT8[R_IO_LH])
     4810#define RSCAN0CFDF011H (RSCAN0.CFDF011.UINT16[R_IO_H])
     4811#define RSCAN0CFDF011HL (RSCAN0.CFDF011.UINT8[R_IO_HL])
     4812#define RSCAN0CFDF011HH (RSCAN0.CFDF011.UINT8[R_IO_HH])
     4813#define RSCAN0CFDF111 (RSCAN0.CFDF111.UINT32)
     4814#define RSCAN0CFDF111L (RSCAN0.CFDF111.UINT16[R_IO_L])
     4815#define RSCAN0CFDF111LL (RSCAN0.CFDF111.UINT8[R_IO_LL])
     4816#define RSCAN0CFDF111LH (RSCAN0.CFDF111.UINT8[R_IO_LH])
     4817#define RSCAN0CFDF111H (RSCAN0.CFDF111.UINT16[R_IO_H])
     4818#define RSCAN0CFDF111HL (RSCAN0.CFDF111.UINT8[R_IO_HL])
     4819#define RSCAN0CFDF111HH (RSCAN0.CFDF111.UINT8[R_IO_HH])
     4820#define RSCAN0CFID12 (RSCAN0.CFID12.UINT32)
     4821#define RSCAN0CFID12L (RSCAN0.CFID12.UINT16[R_IO_L])
     4822#define RSCAN0CFID12LL (RSCAN0.CFID12.UINT8[R_IO_LL])
     4823#define RSCAN0CFID12LH (RSCAN0.CFID12.UINT8[R_IO_LH])
     4824#define RSCAN0CFID12H (RSCAN0.CFID12.UINT16[R_IO_H])
     4825#define RSCAN0CFID12HL (RSCAN0.CFID12.UINT8[R_IO_HL])
     4826#define RSCAN0CFID12HH (RSCAN0.CFID12.UINT8[R_IO_HH])
     4827#define RSCAN0CFPTR12 (RSCAN0.CFPTR12.UINT32)
     4828#define RSCAN0CFPTR12L (RSCAN0.CFPTR12.UINT16[R_IO_L])
     4829#define RSCAN0CFPTR12LL (RSCAN0.CFPTR12.UINT8[R_IO_LL])
     4830#define RSCAN0CFPTR12LH (RSCAN0.CFPTR12.UINT8[R_IO_LH])
     4831#define RSCAN0CFPTR12H (RSCAN0.CFPTR12.UINT16[R_IO_H])
     4832#define RSCAN0CFPTR12HL (RSCAN0.CFPTR12.UINT8[R_IO_HL])
     4833#define RSCAN0CFPTR12HH (RSCAN0.CFPTR12.UINT8[R_IO_HH])
     4834#define RSCAN0CFDF012 (RSCAN0.CFDF012.UINT32)
     4835#define RSCAN0CFDF012L (RSCAN0.CFDF012.UINT16[R_IO_L])
     4836#define RSCAN0CFDF012LL (RSCAN0.CFDF012.UINT8[R_IO_LL])
     4837#define RSCAN0CFDF012LH (RSCAN0.CFDF012.UINT8[R_IO_LH])
     4838#define RSCAN0CFDF012H (RSCAN0.CFDF012.UINT16[R_IO_H])
     4839#define RSCAN0CFDF012HL (RSCAN0.CFDF012.UINT8[R_IO_HL])
     4840#define RSCAN0CFDF012HH (RSCAN0.CFDF012.UINT8[R_IO_HH])
     4841#define RSCAN0CFDF112 (RSCAN0.CFDF112.UINT32)
     4842#define RSCAN0CFDF112L (RSCAN0.CFDF112.UINT16[R_IO_L])
     4843#define RSCAN0CFDF112LL (RSCAN0.CFDF112.UINT8[R_IO_LL])
     4844#define RSCAN0CFDF112LH (RSCAN0.CFDF112.UINT8[R_IO_LH])
     4845#define RSCAN0CFDF112H (RSCAN0.CFDF112.UINT16[R_IO_H])
     4846#define RSCAN0CFDF112HL (RSCAN0.CFDF112.UINT8[R_IO_HL])
     4847#define RSCAN0CFDF112HH (RSCAN0.CFDF112.UINT8[R_IO_HH])
     4848#define RSCAN0CFID13 (RSCAN0.CFID13.UINT32)
     4849#define RSCAN0CFID13L (RSCAN0.CFID13.UINT16[R_IO_L])
     4850#define RSCAN0CFID13LL (RSCAN0.CFID13.UINT8[R_IO_LL])
     4851#define RSCAN0CFID13LH (RSCAN0.CFID13.UINT8[R_IO_LH])
     4852#define RSCAN0CFID13H (RSCAN0.CFID13.UINT16[R_IO_H])
     4853#define RSCAN0CFID13HL (RSCAN0.CFID13.UINT8[R_IO_HL])
     4854#define RSCAN0CFID13HH (RSCAN0.CFID13.UINT8[R_IO_HH])
     4855#define RSCAN0CFPTR13 (RSCAN0.CFPTR13.UINT32)
     4856#define RSCAN0CFPTR13L (RSCAN0.CFPTR13.UINT16[R_IO_L])
     4857#define RSCAN0CFPTR13LL (RSCAN0.CFPTR13.UINT8[R_IO_LL])
     4858#define RSCAN0CFPTR13LH (RSCAN0.CFPTR13.UINT8[R_IO_LH])
     4859#define RSCAN0CFPTR13H (RSCAN0.CFPTR13.UINT16[R_IO_H])
     4860#define RSCAN0CFPTR13HL (RSCAN0.CFPTR13.UINT8[R_IO_HL])
     4861#define RSCAN0CFPTR13HH (RSCAN0.CFPTR13.UINT8[R_IO_HH])
     4862#define RSCAN0CFDF013 (RSCAN0.CFDF013.UINT32)
     4863#define RSCAN0CFDF013L (RSCAN0.CFDF013.UINT16[R_IO_L])
     4864#define RSCAN0CFDF013LL (RSCAN0.CFDF013.UINT8[R_IO_LL])
     4865#define RSCAN0CFDF013LH (RSCAN0.CFDF013.UINT8[R_IO_LH])
     4866#define RSCAN0CFDF013H (RSCAN0.CFDF013.UINT16[R_IO_H])
     4867#define RSCAN0CFDF013HL (RSCAN0.CFDF013.UINT8[R_IO_HL])
     4868#define RSCAN0CFDF013HH (RSCAN0.CFDF013.UINT8[R_IO_HH])
     4869#define RSCAN0CFDF113 (RSCAN0.CFDF113.UINT32)
     4870#define RSCAN0CFDF113L (RSCAN0.CFDF113.UINT16[R_IO_L])
     4871#define RSCAN0CFDF113LL (RSCAN0.CFDF113.UINT8[R_IO_LL])
     4872#define RSCAN0CFDF113LH (RSCAN0.CFDF113.UINT8[R_IO_LH])
     4873#define RSCAN0CFDF113H (RSCAN0.CFDF113.UINT16[R_IO_H])
     4874#define RSCAN0CFDF113HL (RSCAN0.CFDF113.UINT8[R_IO_HL])
     4875#define RSCAN0CFDF113HH (RSCAN0.CFDF113.UINT8[R_IO_HH])
     4876#define RSCAN0CFID14 (RSCAN0.CFID14.UINT32)
     4877#define RSCAN0CFID14L (RSCAN0.CFID14.UINT16[R_IO_L])
     4878#define RSCAN0CFID14LL (RSCAN0.CFID14.UINT8[R_IO_LL])
     4879#define RSCAN0CFID14LH (RSCAN0.CFID14.UINT8[R_IO_LH])
     4880#define RSCAN0CFID14H (RSCAN0.CFID14.UINT16[R_IO_H])
     4881#define RSCAN0CFID14HL (RSCAN0.CFID14.UINT8[R_IO_HL])
     4882#define RSCAN0CFID14HH (RSCAN0.CFID14.UINT8[R_IO_HH])
     4883#define RSCAN0CFPTR14 (RSCAN0.CFPTR14.UINT32)
     4884#define RSCAN0CFPTR14L (RSCAN0.CFPTR14.UINT16[R_IO_L])
     4885#define RSCAN0CFPTR14LL (RSCAN0.CFPTR14.UINT8[R_IO_LL])
     4886#define RSCAN0CFPTR14LH (RSCAN0.CFPTR14.UINT8[R_IO_LH])
     4887#define RSCAN0CFPTR14H (RSCAN0.CFPTR14.UINT16[R_IO_H])
     4888#define RSCAN0CFPTR14HL (RSCAN0.CFPTR14.UINT8[R_IO_HL])
     4889#define RSCAN0CFPTR14HH (RSCAN0.CFPTR14.UINT8[R_IO_HH])
     4890#define RSCAN0CFDF014 (RSCAN0.CFDF014.UINT32)
     4891#define RSCAN0CFDF014L (RSCAN0.CFDF014.UINT16[R_IO_L])
     4892#define RSCAN0CFDF014LL (RSCAN0.CFDF014.UINT8[R_IO_LL])
     4893#define RSCAN0CFDF014LH (RSCAN0.CFDF014.UINT8[R_IO_LH])
     4894#define RSCAN0CFDF014H (RSCAN0.CFDF014.UINT16[R_IO_H])
     4895#define RSCAN0CFDF014HL (RSCAN0.CFDF014.UINT8[R_IO_HL])
     4896#define RSCAN0CFDF014HH (RSCAN0.CFDF014.UINT8[R_IO_HH])
     4897#define RSCAN0CFDF114 (RSCAN0.CFDF114.UINT32)
     4898#define RSCAN0CFDF114L (RSCAN0.CFDF114.UINT16[R_IO_L])
     4899#define RSCAN0CFDF114LL (RSCAN0.CFDF114.UINT8[R_IO_LL])
     4900#define RSCAN0CFDF114LH (RSCAN0.CFDF114.UINT8[R_IO_LH])
     4901#define RSCAN0CFDF114H (RSCAN0.CFDF114.UINT16[R_IO_H])
     4902#define RSCAN0CFDF114HL (RSCAN0.CFDF114.UINT8[R_IO_HL])
     4903#define RSCAN0CFDF114HH (RSCAN0.CFDF114.UINT8[R_IO_HH])
     4904#define RSCAN0TMID0 (RSCAN0.TMID0.UINT32)
     4905#define RSCAN0TMID0L (RSCAN0.TMID0.UINT16[R_IO_L])
     4906#define RSCAN0TMID0LL (RSCAN0.TMID0.UINT8[R_IO_LL])
     4907#define RSCAN0TMID0LH (RSCAN0.TMID0.UINT8[R_IO_LH])
     4908#define RSCAN0TMID0H (RSCAN0.TMID0.UINT16[R_IO_H])
     4909#define RSCAN0TMID0HL (RSCAN0.TMID0.UINT8[R_IO_HL])
     4910#define RSCAN0TMID0HH (RSCAN0.TMID0.UINT8[R_IO_HH])
     4911#define RSCAN0TMPTR0 (RSCAN0.TMPTR0.UINT32)
     4912#define RSCAN0TMPTR0L (RSCAN0.TMPTR0.UINT16[R_IO_L])
     4913#define RSCAN0TMPTR0LL (RSCAN0.TMPTR0.UINT8[R_IO_LL])
     4914#define RSCAN0TMPTR0LH (RSCAN0.TMPTR0.UINT8[R_IO_LH])
     4915#define RSCAN0TMPTR0H (RSCAN0.TMPTR0.UINT16[R_IO_H])
     4916#define RSCAN0TMPTR0HL (RSCAN0.TMPTR0.UINT8[R_IO_HL])
     4917#define RSCAN0TMPTR0HH (RSCAN0.TMPTR0.UINT8[R_IO_HH])
     4918#define RSCAN0TMDF00 (RSCAN0.TMDF00.UINT32)
     4919#define RSCAN0TMDF00L (RSCAN0.TMDF00.UINT16[R_IO_L])
     4920#define RSCAN0TMDF00LL (RSCAN0.TMDF00.UINT8[R_IO_LL])
     4921#define RSCAN0TMDF00LH (RSCAN0.TMDF00.UINT8[R_IO_LH])
     4922#define RSCAN0TMDF00H (RSCAN0.TMDF00.UINT16[R_IO_H])
     4923#define RSCAN0TMDF00HL (RSCAN0.TMDF00.UINT8[R_IO_HL])
     4924#define RSCAN0TMDF00HH (RSCAN0.TMDF00.UINT8[R_IO_HH])
     4925#define RSCAN0TMDF10 (RSCAN0.TMDF10.UINT32)
     4926#define RSCAN0TMDF10L (RSCAN0.TMDF10.UINT16[R_IO_L])
     4927#define RSCAN0TMDF10LL (RSCAN0.TMDF10.UINT8[R_IO_LL])
     4928#define RSCAN0TMDF10LH (RSCAN0.TMDF10.UINT8[R_IO_LH])
     4929#define RSCAN0TMDF10H (RSCAN0.TMDF10.UINT16[R_IO_H])
     4930#define RSCAN0TMDF10HL (RSCAN0.TMDF10.UINT8[R_IO_HL])
     4931#define RSCAN0TMDF10HH (RSCAN0.TMDF10.UINT8[R_IO_HH])
     4932#define RSCAN0TMID1 (RSCAN0.TMID1.UINT32)
     4933#define RSCAN0TMID1L (RSCAN0.TMID1.UINT16[R_IO_L])
     4934#define RSCAN0TMID1LL (RSCAN0.TMID1.UINT8[R_IO_LL])
     4935#define RSCAN0TMID1LH (RSCAN0.TMID1.UINT8[R_IO_LH])
     4936#define RSCAN0TMID1H (RSCAN0.TMID1.UINT16[R_IO_H])
     4937#define RSCAN0TMID1HL (RSCAN0.TMID1.UINT8[R_IO_HL])
     4938#define RSCAN0TMID1HH (RSCAN0.TMID1.UINT8[R_IO_HH])
     4939#define RSCAN0TMPTR1 (RSCAN0.TMPTR1.UINT32)
     4940#define RSCAN0TMPTR1L (RSCAN0.TMPTR1.UINT16[R_IO_L])
     4941#define RSCAN0TMPTR1LL (RSCAN0.TMPTR1.UINT8[R_IO_LL])
     4942#define RSCAN0TMPTR1LH (RSCAN0.TMPTR1.UINT8[R_IO_LH])
     4943#define RSCAN0TMPTR1H (RSCAN0.TMPTR1.UINT16[R_IO_H])
     4944#define RSCAN0TMPTR1HL (RSCAN0.TMPTR1.UINT8[R_IO_HL])
     4945#define RSCAN0TMPTR1HH (RSCAN0.TMPTR1.UINT8[R_IO_HH])
     4946#define RSCAN0TMDF01 (RSCAN0.TMDF01.UINT32)
     4947#define RSCAN0TMDF01L (RSCAN0.TMDF01.UINT16[R_IO_L])
     4948#define RSCAN0TMDF01LL (RSCAN0.TMDF01.UINT8[R_IO_LL])
     4949#define RSCAN0TMDF01LH (RSCAN0.TMDF01.UINT8[R_IO_LH])
     4950#define RSCAN0TMDF01H (RSCAN0.TMDF01.UINT16[R_IO_H])
     4951#define RSCAN0TMDF01HL (RSCAN0.TMDF01.UINT8[R_IO_HL])
     4952#define RSCAN0TMDF01HH (RSCAN0.TMDF01.UINT8[R_IO_HH])
     4953#define RSCAN0TMDF11 (RSCAN0.TMDF11.UINT32)
     4954#define RSCAN0TMDF11L (RSCAN0.TMDF11.UINT16[R_IO_L])
     4955#define RSCAN0TMDF11LL (RSCAN0.TMDF11.UINT8[R_IO_LL])
     4956#define RSCAN0TMDF11LH (RSCAN0.TMDF11.UINT8[R_IO_LH])
     4957#define RSCAN0TMDF11H (RSCAN0.TMDF11.UINT16[R_IO_H])
     4958#define RSCAN0TMDF11HL (RSCAN0.TMDF11.UINT8[R_IO_HL])
     4959#define RSCAN0TMDF11HH (RSCAN0.TMDF11.UINT8[R_IO_HH])
     4960#define RSCAN0TMID2 (RSCAN0.TMID2.UINT32)
     4961#define RSCAN0TMID2L (RSCAN0.TMID2.UINT16[R_IO_L])
     4962#define RSCAN0TMID2LL (RSCAN0.TMID2.UINT8[R_IO_LL])
     4963#define RSCAN0TMID2LH (RSCAN0.TMID2.UINT8[R_IO_LH])
     4964#define RSCAN0TMID2H (RSCAN0.TMID2.UINT16[R_IO_H])
     4965#define RSCAN0TMID2HL (RSCAN0.TMID2.UINT8[R_IO_HL])
     4966#define RSCAN0TMID2HH (RSCAN0.TMID2.UINT8[R_IO_HH])
     4967#define RSCAN0TMPTR2 (RSCAN0.TMPTR2.UINT32)
     4968#define RSCAN0TMPTR2L (RSCAN0.TMPTR2.UINT16[R_IO_L])
     4969#define RSCAN0TMPTR2LL (RSCAN0.TMPTR2.UINT8[R_IO_LL])
     4970#define RSCAN0TMPTR2LH (RSCAN0.TMPTR2.UINT8[R_IO_LH])
     4971#define RSCAN0TMPTR2H (RSCAN0.TMPTR2.UINT16[R_IO_H])
     4972#define RSCAN0TMPTR2HL (RSCAN0.TMPTR2.UINT8[R_IO_HL])
     4973#define RSCAN0TMPTR2HH (RSCAN0.TMPTR2.UINT8[R_IO_HH])
     4974#define RSCAN0TMDF02 (RSCAN0.TMDF02.UINT32)
     4975#define RSCAN0TMDF02L (RSCAN0.TMDF02.UINT16[R_IO_L])
     4976#define RSCAN0TMDF02LL (RSCAN0.TMDF02.UINT8[R_IO_LL])
     4977#define RSCAN0TMDF02LH (RSCAN0.TMDF02.UINT8[R_IO_LH])
     4978#define RSCAN0TMDF02H (RSCAN0.TMDF02.UINT16[R_IO_H])
     4979#define RSCAN0TMDF02HL (RSCAN0.TMDF02.UINT8[R_IO_HL])
     4980#define RSCAN0TMDF02HH (RSCAN0.TMDF02.UINT8[R_IO_HH])
     4981#define RSCAN0TMDF12 (RSCAN0.TMDF12.UINT32)
     4982#define RSCAN0TMDF12L (RSCAN0.TMDF12.UINT16[R_IO_L])
     4983#define RSCAN0TMDF12LL (RSCAN0.TMDF12.UINT8[R_IO_LL])
     4984#define RSCAN0TMDF12LH (RSCAN0.TMDF12.UINT8[R_IO_LH])
     4985#define RSCAN0TMDF12H (RSCAN0.TMDF12.UINT16[R_IO_H])
     4986#define RSCAN0TMDF12HL (RSCAN0.TMDF12.UINT8[R_IO_HL])
     4987#define RSCAN0TMDF12HH (RSCAN0.TMDF12.UINT8[R_IO_HH])
     4988#define RSCAN0TMID3 (RSCAN0.TMID3.UINT32)
     4989#define RSCAN0TMID3L (RSCAN0.TMID3.UINT16[R_IO_L])
     4990#define RSCAN0TMID3LL (RSCAN0.TMID3.UINT8[R_IO_LL])
     4991#define RSCAN0TMID3LH (RSCAN0.TMID3.UINT8[R_IO_LH])
     4992#define RSCAN0TMID3H (RSCAN0.TMID3.UINT16[R_IO_H])
     4993#define RSCAN0TMID3HL (RSCAN0.TMID3.UINT8[R_IO_HL])
     4994#define RSCAN0TMID3HH (RSCAN0.TMID3.UINT8[R_IO_HH])
     4995#define RSCAN0TMPTR3 (RSCAN0.TMPTR3.UINT32)
     4996#define RSCAN0TMPTR3L (RSCAN0.TMPTR3.UINT16[R_IO_L])
     4997#define RSCAN0TMPTR3LL (RSCAN0.TMPTR3.UINT8[R_IO_LL])
     4998#define RSCAN0TMPTR3LH (RSCAN0.TMPTR3.UINT8[R_IO_LH])
     4999#define RSCAN0TMPTR3H (RSCAN0.TMPTR3.UINT16[R_IO_H])
     5000#define RSCAN0TMPTR3HL (RSCAN0.TMPTR3.UINT8[R_IO_HL])
     5001#define RSCAN0TMPTR3HH (RSCAN0.TMPTR3.UINT8[R_IO_HH])
     5002#define RSCAN0TMDF03 (RSCAN0.TMDF03.UINT32)
     5003#define RSCAN0TMDF03L (RSCAN0.TMDF03.UINT16[R_IO_L])
     5004#define RSCAN0TMDF03LL (RSCAN0.TMDF03.UINT8[R_IO_LL])
     5005#define RSCAN0TMDF03LH (RSCAN0.TMDF03.UINT8[R_IO_LH])
     5006#define RSCAN0TMDF03H (RSCAN0.TMDF03.UINT16[R_IO_H])
     5007#define RSCAN0TMDF03HL (RSCAN0.TMDF03.UINT8[R_IO_HL])
     5008#define RSCAN0TMDF03HH (RSCAN0.TMDF03.UINT8[R_IO_HH])
     5009#define RSCAN0TMDF13 (RSCAN0.TMDF13.UINT32)
     5010#define RSCAN0TMDF13L (RSCAN0.TMDF13.UINT16[R_IO_L])
     5011#define RSCAN0TMDF13LL (RSCAN0.TMDF13.UINT8[R_IO_LL])
     5012#define RSCAN0TMDF13LH (RSCAN0.TMDF13.UINT8[R_IO_LH])
     5013#define RSCAN0TMDF13H (RSCAN0.TMDF13.UINT16[R_IO_H])
     5014#define RSCAN0TMDF13HL (RSCAN0.TMDF13.UINT8[R_IO_HL])
     5015#define RSCAN0TMDF13HH (RSCAN0.TMDF13.UINT8[R_IO_HH])
     5016#define RSCAN0TMID4 (RSCAN0.TMID4.UINT32)
     5017#define RSCAN0TMID4L (RSCAN0.TMID4.UINT16[R_IO_L])
     5018#define RSCAN0TMID4LL (RSCAN0.TMID4.UINT8[R_IO_LL])
     5019#define RSCAN0TMID4LH (RSCAN0.TMID4.UINT8[R_IO_LH])
     5020#define RSCAN0TMID4H (RSCAN0.TMID4.UINT16[R_IO_H])
     5021#define RSCAN0TMID4HL (RSCAN0.TMID4.UINT8[R_IO_HL])
     5022#define RSCAN0TMID4HH (RSCAN0.TMID4.UINT8[R_IO_HH])
     5023#define RSCAN0TMPTR4 (RSCAN0.TMPTR4.UINT32)
     5024#define RSCAN0TMPTR4L (RSCAN0.TMPTR4.UINT16[R_IO_L])
     5025#define RSCAN0TMPTR4LL (RSCAN0.TMPTR4.UINT8[R_IO_LL])
     5026#define RSCAN0TMPTR4LH (RSCAN0.TMPTR4.UINT8[R_IO_LH])
     5027#define RSCAN0TMPTR4H (RSCAN0.TMPTR4.UINT16[R_IO_H])
     5028#define RSCAN0TMPTR4HL (RSCAN0.TMPTR4.UINT8[R_IO_HL])
     5029#define RSCAN0TMPTR4HH (RSCAN0.TMPTR4.UINT8[R_IO_HH])
     5030#define RSCAN0TMDF04 (RSCAN0.TMDF04.UINT32)
     5031#define RSCAN0TMDF04L (RSCAN0.TMDF04.UINT16[R_IO_L])
     5032#define RSCAN0TMDF04LL (RSCAN0.TMDF04.UINT8[R_IO_LL])
     5033#define RSCAN0TMDF04LH (RSCAN0.TMDF04.UINT8[R_IO_LH])
     5034#define RSCAN0TMDF04H (RSCAN0.TMDF04.UINT16[R_IO_H])
     5035#define RSCAN0TMDF04HL (RSCAN0.TMDF04.UINT8[R_IO_HL])
     5036#define RSCAN0TMDF04HH (RSCAN0.TMDF04.UINT8[R_IO_HH])
     5037#define RSCAN0TMDF14 (RSCAN0.TMDF14.UINT32)
     5038#define RSCAN0TMDF14L (RSCAN0.TMDF14.UINT16[R_IO_L])
     5039#define RSCAN0TMDF14LL (RSCAN0.TMDF14.UINT8[R_IO_LL])
     5040#define RSCAN0TMDF14LH (RSCAN0.TMDF14.UINT8[R_IO_LH])
     5041#define RSCAN0TMDF14H (RSCAN0.TMDF14.UINT16[R_IO_H])
     5042#define RSCAN0TMDF14HL (RSCAN0.TMDF14.UINT8[R_IO_HL])
     5043#define RSCAN0TMDF14HH (RSCAN0.TMDF14.UINT8[R_IO_HH])
     5044#define RSCAN0TMID5 (RSCAN0.TMID5.UINT32)
     5045#define RSCAN0TMID5L (RSCAN0.TMID5.UINT16[R_IO_L])
     5046#define RSCAN0TMID5LL (RSCAN0.TMID5.UINT8[R_IO_LL])
     5047#define RSCAN0TMID5LH (RSCAN0.TMID5.UINT8[R_IO_LH])
     5048#define RSCAN0TMID5H (RSCAN0.TMID5.UINT16[R_IO_H])
     5049#define RSCAN0TMID5HL (RSCAN0.TMID5.UINT8[R_IO_HL])
     5050#define RSCAN0TMID5HH (RSCAN0.TMID5.UINT8[R_IO_HH])
     5051#define RSCAN0TMPTR5 (RSCAN0.TMPTR5.UINT32)
     5052#define RSCAN0TMPTR5L (RSCAN0.TMPTR5.UINT16[R_IO_L])
     5053#define RSCAN0TMPTR5LL (RSCAN0.TMPTR5.UINT8[R_IO_LL])
     5054#define RSCAN0TMPTR5LH (RSCAN0.TMPTR5.UINT8[R_IO_LH])
     5055#define RSCAN0TMPTR5H (RSCAN0.TMPTR5.UINT16[R_IO_H])
     5056#define RSCAN0TMPTR5HL (RSCAN0.TMPTR5.UINT8[R_IO_HL])
     5057#define RSCAN0TMPTR5HH (RSCAN0.TMPTR5.UINT8[R_IO_HH])
     5058#define RSCAN0TMDF05 (RSCAN0.TMDF05.UINT32)
     5059#define RSCAN0TMDF05L (RSCAN0.TMDF05.UINT16[R_IO_L])
     5060#define RSCAN0TMDF05LL (RSCAN0.TMDF05.UINT8[R_IO_LL])
     5061#define RSCAN0TMDF05LH (RSCAN0.TMDF05.UINT8[R_IO_LH])
     5062#define RSCAN0TMDF05H (RSCAN0.TMDF05.UINT16[R_IO_H])
     5063#define RSCAN0TMDF05HL (RSCAN0.TMDF05.UINT8[R_IO_HL])
     5064#define RSCAN0TMDF05HH (RSCAN0.TMDF05.UINT8[R_IO_HH])
     5065#define RSCAN0TMDF15 (RSCAN0.TMDF15.UINT32)
     5066#define RSCAN0TMDF15L (RSCAN0.TMDF15.UINT16[R_IO_L])
     5067#define RSCAN0TMDF15LL (RSCAN0.TMDF15.UINT8[R_IO_LL])
     5068#define RSCAN0TMDF15LH (RSCAN0.TMDF15.UINT8[R_IO_LH])
     5069#define RSCAN0TMDF15H (RSCAN0.TMDF15.UINT16[R_IO_H])
     5070#define RSCAN0TMDF15HL (RSCAN0.TMDF15.UINT8[R_IO_HL])
     5071#define RSCAN0TMDF15HH (RSCAN0.TMDF15.UINT8[R_IO_HH])
     5072#define RSCAN0TMID6 (RSCAN0.TMID6.UINT32)
     5073#define RSCAN0TMID6L (RSCAN0.TMID6.UINT16[R_IO_L])
     5074#define RSCAN0TMID6LL (RSCAN0.TMID6.UINT8[R_IO_LL])
     5075#define RSCAN0TMID6LH (RSCAN0.TMID6.UINT8[R_IO_LH])
     5076#define RSCAN0TMID6H (RSCAN0.TMID6.UINT16[R_IO_H])
     5077#define RSCAN0TMID6HL (RSCAN0.TMID6.UINT8[R_IO_HL])
     5078#define RSCAN0TMID6HH (RSCAN0.TMID6.UINT8[R_IO_HH])
     5079#define RSCAN0TMPTR6 (RSCAN0.TMPTR6.UINT32)
     5080#define RSCAN0TMPTR6L (RSCAN0.TMPTR6.UINT16[R_IO_L])
     5081#define RSCAN0TMPTR6LL (RSCAN0.TMPTR6.UINT8[R_IO_LL])
     5082#define RSCAN0TMPTR6LH (RSCAN0.TMPTR6.UINT8[R_IO_LH])
     5083#define RSCAN0TMPTR6H (RSCAN0.TMPTR6.UINT16[R_IO_H])
     5084#define RSCAN0TMPTR6HL (RSCAN0.TMPTR6.UINT8[R_IO_HL])
     5085#define RSCAN0TMPTR6HH (RSCAN0.TMPTR6.UINT8[R_IO_HH])
     5086#define RSCAN0TMDF06 (RSCAN0.TMDF06.UINT32)
     5087#define RSCAN0TMDF06L (RSCAN0.TMDF06.UINT16[R_IO_L])
     5088#define RSCAN0TMDF06LL (RSCAN0.TMDF06.UINT8[R_IO_LL])
     5089#define RSCAN0TMDF06LH (RSCAN0.TMDF06.UINT8[R_IO_LH])
     5090#define RSCAN0TMDF06H (RSCAN0.TMDF06.UINT16[R_IO_H])
     5091#define RSCAN0TMDF06HL (RSCAN0.TMDF06.UINT8[R_IO_HL])
     5092#define RSCAN0TMDF06HH (RSCAN0.TMDF06.UINT8[R_IO_HH])
     5093#define RSCAN0TMDF16 (RSCAN0.TMDF16.UINT32)
     5094#define RSCAN0TMDF16L (RSCAN0.TMDF16.UINT16[R_IO_L])
     5095#define RSCAN0TMDF16LL (RSCAN0.TMDF16.UINT8[R_IO_LL])
     5096#define RSCAN0TMDF16LH (RSCAN0.TMDF16.UINT8[R_IO_LH])
     5097#define RSCAN0TMDF16H (RSCAN0.TMDF16.UINT16[R_IO_H])
     5098#define RSCAN0TMDF16HL (RSCAN0.TMDF16.UINT8[R_IO_HL])
     5099#define RSCAN0TMDF16HH (RSCAN0.TMDF16.UINT8[R_IO_HH])
     5100#define RSCAN0TMID7 (RSCAN0.TMID7.UINT32)
     5101#define RSCAN0TMID7L (RSCAN0.TMID7.UINT16[R_IO_L])
     5102#define RSCAN0TMID7LL (RSCAN0.TMID7.UINT8[R_IO_LL])
     5103#define RSCAN0TMID7LH (RSCAN0.TMID7.UINT8[R_IO_LH])
     5104#define RSCAN0TMID7H (RSCAN0.TMID7.UINT16[R_IO_H])
     5105#define RSCAN0TMID7HL (RSCAN0.TMID7.UINT8[R_IO_HL])
     5106#define RSCAN0TMID7HH (RSCAN0.TMID7.UINT8[R_IO_HH])
     5107#define RSCAN0TMPTR7 (RSCAN0.TMPTR7.UINT32)
     5108#define RSCAN0TMPTR7L (RSCAN0.TMPTR7.UINT16[R_IO_L])
     5109#define RSCAN0TMPTR7LL (RSCAN0.TMPTR7.UINT8[R_IO_LL])
     5110#define RSCAN0TMPTR7LH (RSCAN0.TMPTR7.UINT8[R_IO_LH])
     5111#define RSCAN0TMPTR7H (RSCAN0.TMPTR7.UINT16[R_IO_H])
     5112#define RSCAN0TMPTR7HL (RSCAN0.TMPTR7.UINT8[R_IO_HL])
     5113#define RSCAN0TMPTR7HH (RSCAN0.TMPTR7.UINT8[R_IO_HH])
     5114#define RSCAN0TMDF07 (RSCAN0.TMDF07.UINT32)
     5115#define RSCAN0TMDF07L (RSCAN0.TMDF07.UINT16[R_IO_L])
     5116#define RSCAN0TMDF07LL (RSCAN0.TMDF07.UINT8[R_IO_LL])
     5117#define RSCAN0TMDF07LH (RSCAN0.TMDF07.UINT8[R_IO_LH])
     5118#define RSCAN0TMDF07H (RSCAN0.TMDF07.UINT16[R_IO_H])
     5119#define RSCAN0TMDF07HL (RSCAN0.TMDF07.UINT8[R_IO_HL])
     5120#define RSCAN0TMDF07HH (RSCAN0.TMDF07.UINT8[R_IO_HH])
     5121#define RSCAN0TMDF17 (RSCAN0.TMDF17.UINT32)
     5122#define RSCAN0TMDF17L (RSCAN0.TMDF17.UINT16[R_IO_L])
     5123#define RSCAN0TMDF17LL (RSCAN0.TMDF17.UINT8[R_IO_LL])
     5124#define RSCAN0TMDF17LH (RSCAN0.TMDF17.UINT8[R_IO_LH])
     5125#define RSCAN0TMDF17H (RSCAN0.TMDF17.UINT16[R_IO_H])
     5126#define RSCAN0TMDF17HL (RSCAN0.TMDF17.UINT8[R_IO_HL])
     5127#define RSCAN0TMDF17HH (RSCAN0.TMDF17.UINT8[R_IO_HH])
     5128#define RSCAN0TMID8 (RSCAN0.TMID8.UINT32)
     5129#define RSCAN0TMID8L (RSCAN0.TMID8.UINT16[R_IO_L])
     5130#define RSCAN0TMID8LL (RSCAN0.TMID8.UINT8[R_IO_LL])
     5131#define RSCAN0TMID8LH (RSCAN0.TMID8.UINT8[R_IO_LH])
     5132#define RSCAN0TMID8H (RSCAN0.TMID8.UINT16[R_IO_H])
     5133#define RSCAN0TMID8HL (RSCAN0.TMID8.UINT8[R_IO_HL])
     5134#define RSCAN0TMID8HH (RSCAN0.TMID8.UINT8[R_IO_HH])
     5135#define RSCAN0TMPTR8 (RSCAN0.TMPTR8.UINT32)
     5136#define RSCAN0TMPTR8L (RSCAN0.TMPTR8.UINT16[R_IO_L])
     5137#define RSCAN0TMPTR8LL (RSCAN0.TMPTR8.UINT8[R_IO_LL])
     5138#define RSCAN0TMPTR8LH (RSCAN0.TMPTR8.UINT8[R_IO_LH])
     5139#define RSCAN0TMPTR8H (RSCAN0.TMPTR8.UINT16[R_IO_H])
     5140#define RSCAN0TMPTR8HL (RSCAN0.TMPTR8.UINT8[R_IO_HL])
     5141#define RSCAN0TMPTR8HH (RSCAN0.TMPTR8.UINT8[R_IO_HH])
     5142#define RSCAN0TMDF08 (RSCAN0.TMDF08.UINT32)
     5143#define RSCAN0TMDF08L (RSCAN0.TMDF08.UINT16[R_IO_L])
     5144#define RSCAN0TMDF08LL (RSCAN0.TMDF08.UINT8[R_IO_LL])
     5145#define RSCAN0TMDF08LH (RSCAN0.TMDF08.UINT8[R_IO_LH])
     5146#define RSCAN0TMDF08H (RSCAN0.TMDF08.UINT16[R_IO_H])
     5147#define RSCAN0TMDF08HL (RSCAN0.TMDF08.UINT8[R_IO_HL])
     5148#define RSCAN0TMDF08HH (RSCAN0.TMDF08.UINT8[R_IO_HH])
     5149#define RSCAN0TMDF18 (RSCAN0.TMDF18.UINT32)
     5150#define RSCAN0TMDF18L (RSCAN0.TMDF18.UINT16[R_IO_L])
     5151#define RSCAN0TMDF18LL (RSCAN0.TMDF18.UINT8[R_IO_LL])
     5152#define RSCAN0TMDF18LH (RSCAN0.TMDF18.UINT8[R_IO_LH])
     5153#define RSCAN0TMDF18H (RSCAN0.TMDF18.UINT16[R_IO_H])
     5154#define RSCAN0TMDF18HL (RSCAN0.TMDF18.UINT8[R_IO_HL])
     5155#define RSCAN0TMDF18HH (RSCAN0.TMDF18.UINT8[R_IO_HH])
     5156#define RSCAN0TMID9 (RSCAN0.TMID9.UINT32)
     5157#define RSCAN0TMID9L (RSCAN0.TMID9.UINT16[R_IO_L])
     5158#define RSCAN0TMID9LL (RSCAN0.TMID9.UINT8[R_IO_LL])
     5159#define RSCAN0TMID9LH (RSCAN0.TMID9.UINT8[R_IO_LH])
     5160#define RSCAN0TMID9H (RSCAN0.TMID9.UINT16[R_IO_H])
     5161#define RSCAN0TMID9HL (RSCAN0.TMID9.UINT8[R_IO_HL])
     5162#define RSCAN0TMID9HH (RSCAN0.TMID9.UINT8[R_IO_HH])
     5163#define RSCAN0TMPTR9 (RSCAN0.TMPTR9.UINT32)
     5164#define RSCAN0TMPTR9L (RSCAN0.TMPTR9.UINT16[R_IO_L])
     5165#define RSCAN0TMPTR9LL (RSCAN0.TMPTR9.UINT8[R_IO_LL])
     5166#define RSCAN0TMPTR9LH (RSCAN0.TMPTR9.UINT8[R_IO_LH])
     5167#define RSCAN0TMPTR9H (RSCAN0.TMPTR9.UINT16[R_IO_H])
     5168#define RSCAN0TMPTR9HL (RSCAN0.TMPTR9.UINT8[R_IO_HL])
     5169#define RSCAN0TMPTR9HH (RSCAN0.TMPTR9.UINT8[R_IO_HH])
     5170#define RSCAN0TMDF09 (RSCAN0.TMDF09.UINT32)
     5171#define RSCAN0TMDF09L (RSCAN0.TMDF09.UINT16[R_IO_L])
     5172#define RSCAN0TMDF09LL (RSCAN0.TMDF09.UINT8[R_IO_LL])
     5173#define RSCAN0TMDF09LH (RSCAN0.TMDF09.UINT8[R_IO_LH])
     5174#define RSCAN0TMDF09H (RSCAN0.TMDF09.UINT16[R_IO_H])
     5175#define RSCAN0TMDF09HL (RSCAN0.TMDF09.UINT8[R_IO_HL])
     5176#define RSCAN0TMDF09HH (RSCAN0.TMDF09.UINT8[R_IO_HH])
     5177#define RSCAN0TMDF19 (RSCAN0.TMDF19.UINT32)
     5178#define RSCAN0TMDF19L (RSCAN0.TMDF19.UINT16[R_IO_L])
     5179#define RSCAN0TMDF19LL (RSCAN0.TMDF19.UINT8[R_IO_LL])
     5180#define RSCAN0TMDF19LH (RSCAN0.TMDF19.UINT8[R_IO_LH])
     5181#define RSCAN0TMDF19H (RSCAN0.TMDF19.UINT16[R_IO_H])
     5182#define RSCAN0TMDF19HL (RSCAN0.TMDF19.UINT8[R_IO_HL])
     5183#define RSCAN0TMDF19HH (RSCAN0.TMDF19.UINT8[R_IO_HH])
     5184#define RSCAN0TMID10 (RSCAN0.TMID10.UINT32)
     5185#define RSCAN0TMID10L (RSCAN0.TMID10.UINT16[R_IO_L])
     5186#define RSCAN0TMID10LL (RSCAN0.TMID10.UINT8[R_IO_LL])
     5187#define RSCAN0TMID10LH (RSCAN0.TMID10.UINT8[R_IO_LH])
     5188#define RSCAN0TMID10H (RSCAN0.TMID10.UINT16[R_IO_H])
     5189#define RSCAN0TMID10HL (RSCAN0.TMID10.UINT8[R_IO_HL])
     5190#define RSCAN0TMID10HH (RSCAN0.TMID10.UINT8[R_IO_HH])
     5191#define RSCAN0TMPTR10 (RSCAN0.TMPTR10.UINT32)
     5192#define RSCAN0TMPTR10L (RSCAN0.TMPTR10.UINT16[R_IO_L])
     5193#define RSCAN0TMPTR10LL (RSCAN0.TMPTR10.UINT8[R_IO_LL])
     5194#define RSCAN0TMPTR10LH (RSCAN0.TMPTR10.UINT8[R_IO_LH])
     5195#define RSCAN0TMPTR10H (RSCAN0.TMPTR10.UINT16[R_IO_H])
     5196#define RSCAN0TMPTR10HL (RSCAN0.TMPTR10.UINT8[R_IO_HL])
     5197#define RSCAN0TMPTR10HH (RSCAN0.TMPTR10.UINT8[R_IO_HH])
     5198#define RSCAN0TMDF010 (RSCAN0.TMDF010.UINT32)
     5199#define RSCAN0TMDF010L (RSCAN0.TMDF010.UINT16[R_IO_L])
     5200#define RSCAN0TMDF010LL (RSCAN0.TMDF010.UINT8[R_IO_LL])
     5201#define RSCAN0TMDF010LH (RSCAN0.TMDF010.UINT8[R_IO_LH])
     5202#define RSCAN0TMDF010H (RSCAN0.TMDF010.UINT16[R_IO_H])
     5203#define RSCAN0TMDF010HL (RSCAN0.TMDF010.UINT8[R_IO_HL])
     5204#define RSCAN0TMDF010HH (RSCAN0.TMDF010.UINT8[R_IO_HH])
     5205#define RSCAN0TMDF110 (RSCAN0.TMDF110.UINT32)
     5206#define RSCAN0TMDF110L (RSCAN0.TMDF110.UINT16[R_IO_L])
     5207#define RSCAN0TMDF110LL (RSCAN0.TMDF110.UINT8[R_IO_LL])
     5208#define RSCAN0TMDF110LH (RSCAN0.TMDF110.UINT8[R_IO_LH])
     5209#define RSCAN0TMDF110H (RSCAN0.TMDF110.UINT16[R_IO_H])
     5210#define RSCAN0TMDF110HL (RSCAN0.TMDF110.UINT8[R_IO_HL])
     5211#define RSCAN0TMDF110HH (RSCAN0.TMDF110.UINT8[R_IO_HH])
     5212#define RSCAN0TMID11 (RSCAN0.TMID11.UINT32)
     5213#define RSCAN0TMID11L (RSCAN0.TMID11.UINT16[R_IO_L])
     5214#define RSCAN0TMID11LL (RSCAN0.TMID11.UINT8[R_IO_LL])
     5215#define RSCAN0TMID11LH (RSCAN0.TMID11.UINT8[R_IO_LH])
     5216#define RSCAN0TMID11H (RSCAN0.TMID11.UINT16[R_IO_H])
     5217#define RSCAN0TMID11HL (RSCAN0.TMID11.UINT8[R_IO_HL])
     5218#define RSCAN0TMID11HH (RSCAN0.TMID11.UINT8[R_IO_HH])
     5219#define RSCAN0TMPTR11 (RSCAN0.TMPTR11.UINT32)
     5220#define RSCAN0TMPTR11L (RSCAN0.TMPTR11.UINT16[R_IO_L])
     5221#define RSCAN0TMPTR11LL (RSCAN0.TMPTR11.UINT8[R_IO_LL])
     5222#define RSCAN0TMPTR11LH (RSCAN0.TMPTR11.UINT8[R_IO_LH])
     5223#define RSCAN0TMPTR11H (RSCAN0.TMPTR11.UINT16[R_IO_H])
     5224#define RSCAN0TMPTR11HL (RSCAN0.TMPTR11.UINT8[R_IO_HL])
     5225#define RSCAN0TMPTR11HH (RSCAN0.TMPTR11.UINT8[R_IO_HH])
     5226#define RSCAN0TMDF011 (RSCAN0.TMDF011.UINT32)
     5227#define RSCAN0TMDF011L (RSCAN0.TMDF011.UINT16[R_IO_L])
     5228#define RSCAN0TMDF011LL (RSCAN0.TMDF011.UINT8[R_IO_LL])
     5229#define RSCAN0TMDF011LH (RSCAN0.TMDF011.UINT8[R_IO_LH])
     5230#define RSCAN0TMDF011H (RSCAN0.TMDF011.UINT16[R_IO_H])
     5231#define RSCAN0TMDF011HL (RSCAN0.TMDF011.UINT8[R_IO_HL])
     5232#define RSCAN0TMDF011HH (RSCAN0.TMDF011.UINT8[R_IO_HH])
     5233#define RSCAN0TMDF111 (RSCAN0.TMDF111.UINT32)
     5234#define RSCAN0TMDF111L (RSCAN0.TMDF111.UINT16[R_IO_L])
     5235#define RSCAN0TMDF111LL (RSCAN0.TMDF111.UINT8[R_IO_LL])
     5236#define RSCAN0TMDF111LH (RSCAN0.TMDF111.UINT8[R_IO_LH])
     5237#define RSCAN0TMDF111H (RSCAN0.TMDF111.UINT16[R_IO_H])
     5238#define RSCAN0TMDF111HL (RSCAN0.TMDF111.UINT8[R_IO_HL])
     5239#define RSCAN0TMDF111HH (RSCAN0.TMDF111.UINT8[R_IO_HH])
     5240#define RSCAN0TMID12 (RSCAN0.TMID12.UINT32)
     5241#define RSCAN0TMID12L (RSCAN0.TMID12.UINT16[R_IO_L])
     5242#define RSCAN0TMID12LL (RSCAN0.TMID12.UINT8[R_IO_LL])
     5243#define RSCAN0TMID12LH (RSCAN0.TMID12.UINT8[R_IO_LH])
     5244#define RSCAN0TMID12H (RSCAN0.TMID12.UINT16[R_IO_H])
     5245#define RSCAN0TMID12HL (RSCAN0.TMID12.UINT8[R_IO_HL])
     5246#define RSCAN0TMID12HH (RSCAN0.TMID12.UINT8[R_IO_HH])
     5247#define RSCAN0TMPTR12 (RSCAN0.TMPTR12.UINT32)
     5248#define RSCAN0TMPTR12L (RSCAN0.TMPTR12.UINT16[R_IO_L])
     5249#define RSCAN0TMPTR12LL (RSCAN0.TMPTR12.UINT8[R_IO_LL])
     5250#define RSCAN0TMPTR12LH (RSCAN0.TMPTR12.UINT8[R_IO_LH])
     5251#define RSCAN0TMPTR12H (RSCAN0.TMPTR12.UINT16[R_IO_H])
     5252#define RSCAN0TMPTR12HL (RSCAN0.TMPTR12.UINT8[R_IO_HL])
     5253#define RSCAN0TMPTR12HH (RSCAN0.TMPTR12.UINT8[R_IO_HH])
     5254#define RSCAN0TMDF012 (RSCAN0.TMDF012.UINT32)
     5255#define RSCAN0TMDF012L (RSCAN0.TMDF012.UINT16[R_IO_L])
     5256#define RSCAN0TMDF012LL (RSCAN0.TMDF012.UINT8[R_IO_LL])
     5257#define RSCAN0TMDF012LH (RSCAN0.TMDF012.UINT8[R_IO_LH])
     5258#define RSCAN0TMDF012H (RSCAN0.TMDF012.UINT16[R_IO_H])
     5259#define RSCAN0TMDF012HL (RSCAN0.TMDF012.UINT8[R_IO_HL])
     5260#define RSCAN0TMDF012HH (RSCAN0.TMDF012.UINT8[R_IO_HH])
     5261#define RSCAN0TMDF112 (RSCAN0.TMDF112.UINT32)
     5262#define RSCAN0TMDF112L (RSCAN0.TMDF112.UINT16[R_IO_L])
     5263#define RSCAN0TMDF112LL (RSCAN0.TMDF112.UINT8[R_IO_LL])
     5264#define RSCAN0TMDF112LH (RSCAN0.TMDF112.UINT8[R_IO_LH])
     5265#define RSCAN0TMDF112H (RSCAN0.TMDF112.UINT16[R_IO_H])
     5266#define RSCAN0TMDF112HL (RSCAN0.TMDF112.UINT8[R_IO_HL])
     5267#define RSCAN0TMDF112HH (RSCAN0.TMDF112.UINT8[R_IO_HH])
     5268#define RSCAN0TMID13 (RSCAN0.TMID13.UINT32)
     5269#define RSCAN0TMID13L (RSCAN0.TMID13.UINT16[R_IO_L])
     5270#define RSCAN0TMID13LL (RSCAN0.TMID13.UINT8[R_IO_LL])
     5271#define RSCAN0TMID13LH (RSCAN0.TMID13.UINT8[R_IO_LH])
     5272#define RSCAN0TMID13H (RSCAN0.TMID13.UINT16[R_IO_H])
     5273#define RSCAN0TMID13HL (RSCAN0.TMID13.UINT8[R_IO_HL])
     5274#define RSCAN0TMID13HH (RSCAN0.TMID13.UINT8[R_IO_HH])
     5275#define RSCAN0TMPTR13 (RSCAN0.TMPTR13.UINT32)
     5276#define RSCAN0TMPTR13L (RSCAN0.TMPTR13.UINT16[R_IO_L])
     5277#define RSCAN0TMPTR13LL (RSCAN0.TMPTR13.UINT8[R_IO_LL])
     5278#define RSCAN0TMPTR13LH (RSCAN0.TMPTR13.UINT8[R_IO_LH])
     5279#define RSCAN0TMPTR13H (RSCAN0.TMPTR13.UINT16[R_IO_H])
     5280#define RSCAN0TMPTR13HL (RSCAN0.TMPTR13.UINT8[R_IO_HL])
     5281#define RSCAN0TMPTR13HH (RSCAN0.TMPTR13.UINT8[R_IO_HH])
     5282#define RSCAN0TMDF013 (RSCAN0.TMDF013.UINT32)
     5283#define RSCAN0TMDF013L (RSCAN0.TMDF013.UINT16[R_IO_L])
     5284#define RSCAN0TMDF013LL (RSCAN0.TMDF013.UINT8[R_IO_LL])
     5285#define RSCAN0TMDF013LH (RSCAN0.TMDF013.UINT8[R_IO_LH])
     5286#define RSCAN0TMDF013H (RSCAN0.TMDF013.UINT16[R_IO_H])
     5287#define RSCAN0TMDF013HL (RSCAN0.TMDF013.UINT8[R_IO_HL])
     5288#define RSCAN0TMDF013HH (RSCAN0.TMDF013.UINT8[R_IO_HH])
     5289#define RSCAN0TMDF113 (RSCAN0.TMDF113.UINT32)
     5290#define RSCAN0TMDF113L (RSCAN0.TMDF113.UINT16[R_IO_L])
     5291#define RSCAN0TMDF113LL (RSCAN0.TMDF113.UINT8[R_IO_LL])
     5292#define RSCAN0TMDF113LH (RSCAN0.TMDF113.UINT8[R_IO_LH])
     5293#define RSCAN0TMDF113H (RSCAN0.TMDF113.UINT16[R_IO_H])
     5294#define RSCAN0TMDF113HL (RSCAN0.TMDF113.UINT8[R_IO_HL])
     5295#define RSCAN0TMDF113HH (RSCAN0.TMDF113.UINT8[R_IO_HH])
     5296#define RSCAN0TMID14 (RSCAN0.TMID14.UINT32)
     5297#define RSCAN0TMID14L (RSCAN0.TMID14.UINT16[R_IO_L])
     5298#define RSCAN0TMID14LL (RSCAN0.TMID14.UINT8[R_IO_LL])
     5299#define RSCAN0TMID14LH (RSCAN0.TMID14.UINT8[R_IO_LH])
     5300#define RSCAN0TMID14H (RSCAN0.TMID14.UINT16[R_IO_H])
     5301#define RSCAN0TMID14HL (RSCAN0.TMID14.UINT8[R_IO_HL])
     5302#define RSCAN0TMID14HH (RSCAN0.TMID14.UINT8[R_IO_HH])
     5303#define RSCAN0TMPTR14 (RSCAN0.TMPTR14.UINT32)
     5304#define RSCAN0TMPTR14L (RSCAN0.TMPTR14.UINT16[R_IO_L])
     5305#define RSCAN0TMPTR14LL (RSCAN0.TMPTR14.UINT8[R_IO_LL])
     5306#define RSCAN0TMPTR14LH (RSCAN0.TMPTR14.UINT8[R_IO_LH])
     5307#define RSCAN0TMPTR14H (RSCAN0.TMPTR14.UINT16[R_IO_H])
     5308#define RSCAN0TMPTR14HL (RSCAN0.TMPTR14.UINT8[R_IO_HL])
     5309#define RSCAN0TMPTR14HH (RSCAN0.TMPTR14.UINT8[R_IO_HH])
     5310#define RSCAN0TMDF014 (RSCAN0.TMDF014.UINT32)
     5311#define RSCAN0TMDF014L (RSCAN0.TMDF014.UINT16[R_IO_L])
     5312#define RSCAN0TMDF014LL (RSCAN0.TMDF014.UINT8[R_IO_LL])
     5313#define RSCAN0TMDF014LH (RSCAN0.TMDF014.UINT8[R_IO_LH])
     5314#define RSCAN0TMDF014H (RSCAN0.TMDF014.UINT16[R_IO_H])
     5315#define RSCAN0TMDF014HL (RSCAN0.TMDF014.UINT8[R_IO_HL])
     5316#define RSCAN0TMDF014HH (RSCAN0.TMDF014.UINT8[R_IO_HH])
     5317#define RSCAN0TMDF114 (RSCAN0.TMDF114.UINT32)
     5318#define RSCAN0TMDF114L (RSCAN0.TMDF114.UINT16[R_IO_L])
     5319#define RSCAN0TMDF114LL (RSCAN0.TMDF114.UINT8[R_IO_LL])
     5320#define RSCAN0TMDF114LH (RSCAN0.TMDF114.UINT8[R_IO_LH])
     5321#define RSCAN0TMDF114H (RSCAN0.TMDF114.UINT16[R_IO_H])
     5322#define RSCAN0TMDF114HL (RSCAN0.TMDF114.UINT8[R_IO_HL])
     5323#define RSCAN0TMDF114HH (RSCAN0.TMDF114.UINT8[R_IO_HH])
     5324#define RSCAN0TMID15 (RSCAN0.TMID15.UINT32)
     5325#define RSCAN0TMID15L (RSCAN0.TMID15.UINT16[R_IO_L])
     5326#define RSCAN0TMID15LL (RSCAN0.TMID15.UINT8[R_IO_LL])
     5327#define RSCAN0TMID15LH (RSCAN0.TMID15.UINT8[R_IO_LH])
     5328#define RSCAN0TMID15H (RSCAN0.TMID15.UINT16[R_IO_H])
     5329#define RSCAN0TMID15HL (RSCAN0.TMID15.UINT8[R_IO_HL])
     5330#define RSCAN0TMID15HH (RSCAN0.TMID15.UINT8[R_IO_HH])
     5331#define RSCAN0TMPTR15 (RSCAN0.TMPTR15.UINT32)
     5332#define RSCAN0TMPTR15L (RSCAN0.TMPTR15.UINT16[R_IO_L])
     5333#define RSCAN0TMPTR15LL (RSCAN0.TMPTR15.UINT8[R_IO_LL])
     5334#define RSCAN0TMPTR15LH (RSCAN0.TMPTR15.UINT8[R_IO_LH])
     5335#define RSCAN0TMPTR15H (RSCAN0.TMPTR15.UINT16[R_IO_H])
     5336#define RSCAN0TMPTR15HL (RSCAN0.TMPTR15.UINT8[R_IO_HL])
     5337#define RSCAN0TMPTR15HH (RSCAN0.TMPTR15.UINT8[R_IO_HH])
     5338#define RSCAN0TMDF015 (RSCAN0.TMDF015.UINT32)
     5339#define RSCAN0TMDF015L (RSCAN0.TMDF015.UINT16[R_IO_L])
     5340#define RSCAN0TMDF015LL (RSCAN0.TMDF015.UINT8[R_IO_LL])
     5341#define RSCAN0TMDF015LH (RSCAN0.TMDF015.UINT8[R_IO_LH])
     5342#define RSCAN0TMDF015H (RSCAN0.TMDF015.UINT16[R_IO_H])
     5343#define RSCAN0TMDF015HL (RSCAN0.TMDF015.UINT8[R_IO_HL])
     5344#define RSCAN0TMDF015HH (RSCAN0.TMDF015.UINT8[R_IO_HH])
     5345#define RSCAN0TMDF115 (RSCAN0.TMDF115.UINT32)
     5346#define RSCAN0TMDF115L (RSCAN0.TMDF115.UINT16[R_IO_L])
     5347#define RSCAN0TMDF115LL (RSCAN0.TMDF115.UINT8[R_IO_LL])
     5348#define RSCAN0TMDF115LH (RSCAN0.TMDF115.UINT8[R_IO_LH])
     5349#define RSCAN0TMDF115H (RSCAN0.TMDF115.UINT16[R_IO_H])
     5350#define RSCAN0TMDF115HL (RSCAN0.TMDF115.UINT8[R_IO_HL])
     5351#define RSCAN0TMDF115HH (RSCAN0.TMDF115.UINT8[R_IO_HH])
     5352#define RSCAN0TMID16 (RSCAN0.TMID16.UINT32)
     5353#define RSCAN0TMID16L (RSCAN0.TMID16.UINT16[R_IO_L])
     5354#define RSCAN0TMID16LL (RSCAN0.TMID16.UINT8[R_IO_LL])
     5355#define RSCAN0TMID16LH (RSCAN0.TMID16.UINT8[R_IO_LH])
     5356#define RSCAN0TMID16H (RSCAN0.TMID16.UINT16[R_IO_H])
     5357#define RSCAN0TMID16HL (RSCAN0.TMID16.UINT8[R_IO_HL])
     5358#define RSCAN0TMID16HH (RSCAN0.TMID16.UINT8[R_IO_HH])
     5359#define RSCAN0TMPTR16 (RSCAN0.TMPTR16.UINT32)
     5360#define RSCAN0TMPTR16L (RSCAN0.TMPTR16.UINT16[R_IO_L])
     5361#define RSCAN0TMPTR16LL (RSCAN0.TMPTR16.UINT8[R_IO_LL])
     5362#define RSCAN0TMPTR16LH (RSCAN0.TMPTR16.UINT8[R_IO_LH])
     5363#define RSCAN0TMPTR16H (RSCAN0.TMPTR16.UINT16[R_IO_H])
     5364#define RSCAN0TMPTR16HL (RSCAN0.TMPTR16.UINT8[R_IO_HL])
     5365#define RSCAN0TMPTR16HH (RSCAN0.TMPTR16.UINT8[R_IO_HH])
     5366#define RSCAN0TMDF016 (RSCAN0.TMDF016.UINT32)
     5367#define RSCAN0TMDF016L (RSCAN0.TMDF016.UINT16[R_IO_L])
     5368#define RSCAN0TMDF016LL (RSCAN0.TMDF016.UINT8[R_IO_LL])
     5369#define RSCAN0TMDF016LH (RSCAN0.TMDF016.UINT8[R_IO_LH])
     5370#define RSCAN0TMDF016H (RSCAN0.TMDF016.UINT16[R_IO_H])
     5371#define RSCAN0TMDF016HL (RSCAN0.TMDF016.UINT8[R_IO_HL])
     5372#define RSCAN0TMDF016HH (RSCAN0.TMDF016.UINT8[R_IO_HH])
     5373#define RSCAN0TMDF116 (RSCAN0.TMDF116.UINT32)
     5374#define RSCAN0TMDF116L (RSCAN0.TMDF116.UINT16[R_IO_L])
     5375#define RSCAN0TMDF116LL (RSCAN0.TMDF116.UINT8[R_IO_LL])
     5376#define RSCAN0TMDF116LH (RSCAN0.TMDF116.UINT8[R_IO_LH])
     5377#define RSCAN0TMDF116H (RSCAN0.TMDF116.UINT16[R_IO_H])
     5378#define RSCAN0TMDF116HL (RSCAN0.TMDF116.UINT8[R_IO_HL])
     5379#define RSCAN0TMDF116HH (RSCAN0.TMDF116.UINT8[R_IO_HH])
     5380#define RSCAN0TMID17 (RSCAN0.TMID17.UINT32)
     5381#define RSCAN0TMID17L (RSCAN0.TMID17.UINT16[R_IO_L])
     5382#define RSCAN0TMID17LL (RSCAN0.TMID17.UINT8[R_IO_LL])
     5383#define RSCAN0TMID17LH (RSCAN0.TMID17.UINT8[R_IO_LH])
     5384#define RSCAN0TMID17H (RSCAN0.TMID17.UINT16[R_IO_H])
     5385#define RSCAN0TMID17HL (RSCAN0.TMID17.UINT8[R_IO_HL])
     5386#define RSCAN0TMID17HH (RSCAN0.TMID17.UINT8[R_IO_HH])
     5387#define RSCAN0TMPTR17 (RSCAN0.TMPTR17.UINT32)
     5388#define RSCAN0TMPTR17L (RSCAN0.TMPTR17.UINT16[R_IO_L])
     5389#define RSCAN0TMPTR17LL (RSCAN0.TMPTR17.UINT8[R_IO_LL])
     5390#define RSCAN0TMPTR17LH (RSCAN0.TMPTR17.UINT8[R_IO_LH])
     5391#define RSCAN0TMPTR17H (RSCAN0.TMPTR17.UINT16[R_IO_H])
     5392#define RSCAN0TMPTR17HL (RSCAN0.TMPTR17.UINT8[R_IO_HL])
     5393#define RSCAN0TMPTR17HH (RSCAN0.TMPTR17.UINT8[R_IO_HH])
     5394#define RSCAN0TMDF017 (RSCAN0.TMDF017.UINT32)
     5395#define RSCAN0TMDF017L (RSCAN0.TMDF017.UINT16[R_IO_L])
     5396#define RSCAN0TMDF017LL (RSCAN0.TMDF017.UINT8[R_IO_LL])
     5397#define RSCAN0TMDF017LH (RSCAN0.TMDF017.UINT8[R_IO_LH])
     5398#define RSCAN0TMDF017H (RSCAN0.TMDF017.UINT16[R_IO_H])
     5399#define RSCAN0TMDF017HL (RSCAN0.TMDF017.UINT8[R_IO_HL])
     5400#define RSCAN0TMDF017HH (RSCAN0.TMDF017.UINT8[R_IO_HH])
     5401#define RSCAN0TMDF117 (RSCAN0.TMDF117.UINT32)
     5402#define RSCAN0TMDF117L (RSCAN0.TMDF117.UINT16[R_IO_L])
     5403#define RSCAN0TMDF117LL (RSCAN0.TMDF117.UINT8[R_IO_LL])
     5404#define RSCAN0TMDF117LH (RSCAN0.TMDF117.UINT8[R_IO_LH])
     5405#define RSCAN0TMDF117H (RSCAN0.TMDF117.UINT16[R_IO_H])
     5406#define RSCAN0TMDF117HL (RSCAN0.TMDF117.UINT8[R_IO_HL])
     5407#define RSCAN0TMDF117HH (RSCAN0.TMDF117.UINT8[R_IO_HH])
     5408#define RSCAN0TMID18 (RSCAN0.TMID18.UINT32)
     5409#define RSCAN0TMID18L (RSCAN0.TMID18.UINT16[R_IO_L])
     5410#define RSCAN0TMID18LL (RSCAN0.TMID18.UINT8[R_IO_LL])
     5411#define RSCAN0TMID18LH (RSCAN0.TMID18.UINT8[R_IO_LH])
     5412#define RSCAN0TMID18H (RSCAN0.TMID18.UINT16[R_IO_H])
     5413#define RSCAN0TMID18HL (RSCAN0.TMID18.UINT8[R_IO_HL])
     5414#define RSCAN0TMID18HH (RSCAN0.TMID18.UINT8[R_IO_HH])
     5415#define RSCAN0TMPTR18 (RSCAN0.TMPTR18.UINT32)
     5416#define RSCAN0TMPTR18L (RSCAN0.TMPTR18.UINT16[R_IO_L])
     5417#define RSCAN0TMPTR18LL (RSCAN0.TMPTR18.UINT8[R_IO_LL])
     5418#define RSCAN0TMPTR18LH (RSCAN0.TMPTR18.UINT8[R_IO_LH])
     5419#define RSCAN0TMPTR18H (RSCAN0.TMPTR18.UINT16[R_IO_H])
     5420#define RSCAN0TMPTR18HL (RSCAN0.TMPTR18.UINT8[R_IO_HL])
     5421#define RSCAN0TMPTR18HH (RSCAN0.TMPTR18.UINT8[R_IO_HH])
     5422#define RSCAN0TMDF018 (RSCAN0.TMDF018.UINT32)
     5423#define RSCAN0TMDF018L (RSCAN0.TMDF018.UINT16[R_IO_L])
     5424#define RSCAN0TMDF018LL (RSCAN0.TMDF018.UINT8[R_IO_LL])
     5425#define RSCAN0TMDF018LH (RSCAN0.TMDF018.UINT8[R_IO_LH])
     5426#define RSCAN0TMDF018H (RSCAN0.TMDF018.UINT16[R_IO_H])
     5427#define RSCAN0TMDF018HL (RSCAN0.TMDF018.UINT8[R_IO_HL])
     5428#define RSCAN0TMDF018HH (RSCAN0.TMDF018.UINT8[R_IO_HH])
     5429#define RSCAN0TMDF118 (RSCAN0.TMDF118.UINT32)
     5430#define RSCAN0TMDF118L (RSCAN0.TMDF118.UINT16[R_IO_L])
     5431#define RSCAN0TMDF118LL (RSCAN0.TMDF118.UINT8[R_IO_LL])
     5432#define RSCAN0TMDF118LH (RSCAN0.TMDF118.UINT8[R_IO_LH])
     5433#define RSCAN0TMDF118H (RSCAN0.TMDF118.UINT16[R_IO_H])
     5434#define RSCAN0TMDF118HL (RSCAN0.TMDF118.UINT8[R_IO_HL])
     5435#define RSCAN0TMDF118HH (RSCAN0.TMDF118.UINT8[R_IO_HH])
     5436#define RSCAN0TMID19 (RSCAN0.TMID19.UINT32)
     5437#define RSCAN0TMID19L (RSCAN0.TMID19.UINT16[R_IO_L])
     5438#define RSCAN0TMID19LL (RSCAN0.TMID19.UINT8[R_IO_LL])
     5439#define RSCAN0TMID19LH (RSCAN0.TMID19.UINT8[R_IO_LH])
     5440#define RSCAN0TMID19H (RSCAN0.TMID19.UINT16[R_IO_H])
     5441#define RSCAN0TMID19HL (RSCAN0.TMID19.UINT8[R_IO_HL])
     5442#define RSCAN0TMID19HH (RSCAN0.TMID19.UINT8[R_IO_HH])
     5443#define RSCAN0TMPTR19 (RSCAN0.TMPTR19.UINT32)
     5444#define RSCAN0TMPTR19L (RSCAN0.TMPTR19.UINT16[R_IO_L])
     5445#define RSCAN0TMPTR19LL (RSCAN0.TMPTR19.UINT8[R_IO_LL])
     5446#define RSCAN0TMPTR19LH (RSCAN0.TMPTR19.UINT8[R_IO_LH])
     5447#define RSCAN0TMPTR19H (RSCAN0.TMPTR19.UINT16[R_IO_H])
     5448#define RSCAN0TMPTR19HL (RSCAN0.TMPTR19.UINT8[R_IO_HL])
     5449#define RSCAN0TMPTR19HH (RSCAN0.TMPTR19.UINT8[R_IO_HH])
     5450#define RSCAN0TMDF019 (RSCAN0.TMDF019.UINT32)
     5451#define RSCAN0TMDF019L (RSCAN0.TMDF019.UINT16[R_IO_L])
     5452#define RSCAN0TMDF019LL (RSCAN0.TMDF019.UINT8[R_IO_LL])
     5453#define RSCAN0TMDF019LH (RSCAN0.TMDF019.UINT8[R_IO_LH])
     5454#define RSCAN0TMDF019H (RSCAN0.TMDF019.UINT16[R_IO_H])
     5455#define RSCAN0TMDF019HL (RSCAN0.TMDF019.UINT8[R_IO_HL])
     5456#define RSCAN0TMDF019HH (RSCAN0.TMDF019.UINT8[R_IO_HH])
     5457#define RSCAN0TMDF119 (RSCAN0.TMDF119.UINT32)
     5458#define RSCAN0TMDF119L (RSCAN0.TMDF119.UINT16[R_IO_L])
     5459#define RSCAN0TMDF119LL (RSCAN0.TMDF119.UINT8[R_IO_LL])
     5460#define RSCAN0TMDF119LH (RSCAN0.TMDF119.UINT8[R_IO_LH])
     5461#define RSCAN0TMDF119H (RSCAN0.TMDF119.UINT16[R_IO_H])
     5462#define RSCAN0TMDF119HL (RSCAN0.TMDF119.UINT8[R_IO_HL])
     5463#define RSCAN0TMDF119HH (RSCAN0.TMDF119.UINT8[R_IO_HH])
     5464#define RSCAN0TMID20 (RSCAN0.TMID20.UINT32)
     5465#define RSCAN0TMID20L (RSCAN0.TMID20.UINT16[R_IO_L])
     5466#define RSCAN0TMID20LL (RSCAN0.TMID20.UINT8[R_IO_LL])
     5467#define RSCAN0TMID20LH (RSCAN0.TMID20.UINT8[R_IO_LH])
     5468#define RSCAN0TMID20H (RSCAN0.TMID20.UINT16[R_IO_H])
     5469#define RSCAN0TMID20HL (RSCAN0.TMID20.UINT8[R_IO_HL])
     5470#define RSCAN0TMID20HH (RSCAN0.TMID20.UINT8[R_IO_HH])
     5471#define RSCAN0TMPTR20 (RSCAN0.TMPTR20.UINT32)
     5472#define RSCAN0TMPTR20L (RSCAN0.TMPTR20.UINT16[R_IO_L])
     5473#define RSCAN0TMPTR20LL (RSCAN0.TMPTR20.UINT8[R_IO_LL])
     5474#define RSCAN0TMPTR20LH (RSCAN0.TMPTR20.UINT8[R_IO_LH])
     5475#define RSCAN0TMPTR20H (RSCAN0.TMPTR20.UINT16[R_IO_H])
     5476#define RSCAN0TMPTR20HL (RSCAN0.TMPTR20.UINT8[R_IO_HL])
     5477#define RSCAN0TMPTR20HH (RSCAN0.TMPTR20.UINT8[R_IO_HH])
     5478#define RSCAN0TMDF020 (RSCAN0.TMDF020.UINT32)
     5479#define RSCAN0TMDF020L (RSCAN0.TMDF020.UINT16[R_IO_L])
     5480#define RSCAN0TMDF020LL (RSCAN0.TMDF020.UINT8[R_IO_LL])
     5481#define RSCAN0TMDF020LH (RSCAN0.TMDF020.UINT8[R_IO_LH])
     5482#define RSCAN0TMDF020H (RSCAN0.TMDF020.UINT16[R_IO_H])
     5483#define RSCAN0TMDF020HL (RSCAN0.TMDF020.UINT8[R_IO_HL])
     5484#define RSCAN0TMDF020HH (RSCAN0.TMDF020.UINT8[R_IO_HH])
     5485#define RSCAN0TMDF120 (RSCAN0.TMDF120.UINT32)
     5486#define RSCAN0TMDF120L (RSCAN0.TMDF120.UINT16[R_IO_L])
     5487#define RSCAN0TMDF120LL (RSCAN0.TMDF120.UINT8[R_IO_LL])
     5488#define RSCAN0TMDF120LH (RSCAN0.TMDF120.UINT8[R_IO_LH])
     5489#define RSCAN0TMDF120H (RSCAN0.TMDF120.UINT16[R_IO_H])
     5490#define RSCAN0TMDF120HL (RSCAN0.TMDF120.UINT8[R_IO_HL])
     5491#define RSCAN0TMDF120HH (RSCAN0.TMDF120.UINT8[R_IO_HH])
     5492#define RSCAN0TMID21 (RSCAN0.TMID21.UINT32)
     5493#define RSCAN0TMID21L (RSCAN0.TMID21.UINT16[R_IO_L])
     5494#define RSCAN0TMID21LL (RSCAN0.TMID21.UINT8[R_IO_LL])
     5495#define RSCAN0TMID21LH (RSCAN0.TMID21.UINT8[R_IO_LH])
     5496#define RSCAN0TMID21H (RSCAN0.TMID21.UINT16[R_IO_H])
     5497#define RSCAN0TMID21HL (RSCAN0.TMID21.UINT8[R_IO_HL])
     5498#define RSCAN0TMID21HH (RSCAN0.TMID21.UINT8[R_IO_HH])
     5499#define RSCAN0TMPTR21 (RSCAN0.TMPTR21.UINT32)
     5500#define RSCAN0TMPTR21L (RSCAN0.TMPTR21.UINT16[R_IO_L])
     5501#define RSCAN0TMPTR21LL (RSCAN0.TMPTR21.UINT8[R_IO_LL])
     5502#define RSCAN0TMPTR21LH (RSCAN0.TMPTR21.UINT8[R_IO_LH])
     5503#define RSCAN0TMPTR21H (RSCAN0.TMPTR21.UINT16[R_IO_H])
     5504#define RSCAN0TMPTR21HL (RSCAN0.TMPTR21.UINT8[R_IO_HL])
     5505#define RSCAN0TMPTR21HH (RSCAN0.TMPTR21.UINT8[R_IO_HH])
     5506#define RSCAN0TMDF021 (RSCAN0.TMDF021.UINT32)
     5507#define RSCAN0TMDF021L (RSCAN0.TMDF021.UINT16[R_IO_L])
     5508#define RSCAN0TMDF021LL (RSCAN0.TMDF021.UINT8[R_IO_LL])
     5509#define RSCAN0TMDF021LH (RSCAN0.TMDF021.UINT8[R_IO_LH])
     5510#define RSCAN0TMDF021H (RSCAN0.TMDF021.UINT16[R_IO_H])
     5511#define RSCAN0TMDF021HL (RSCAN0.TMDF021.UINT8[R_IO_HL])
     5512#define RSCAN0TMDF021HH (RSCAN0.TMDF021.UINT8[R_IO_HH])
     5513#define RSCAN0TMDF121 (RSCAN0.TMDF121.UINT32)
     5514#define RSCAN0TMDF121L (RSCAN0.TMDF121.UINT16[R_IO_L])
     5515#define RSCAN0TMDF121LL (RSCAN0.TMDF121.UINT8[R_IO_LL])
     5516#define RSCAN0TMDF121LH (RSCAN0.TMDF121.UINT8[R_IO_LH])
     5517#define RSCAN0TMDF121H (RSCAN0.TMDF121.UINT16[R_IO_H])
     5518#define RSCAN0TMDF121HL (RSCAN0.TMDF121.UINT8[R_IO_HL])
     5519#define RSCAN0TMDF121HH (RSCAN0.TMDF121.UINT8[R_IO_HH])
     5520#define RSCAN0TMID22 (RSCAN0.TMID22.UINT32)
     5521#define RSCAN0TMID22L (RSCAN0.TMID22.UINT16[R_IO_L])
     5522#define RSCAN0TMID22LL (RSCAN0.TMID22.UINT8[R_IO_LL])
     5523#define RSCAN0TMID22LH (RSCAN0.TMID22.UINT8[R_IO_LH])
     5524#define RSCAN0TMID22H (RSCAN0.TMID22.UINT16[R_IO_H])
     5525#define RSCAN0TMID22HL (RSCAN0.TMID22.UINT8[R_IO_HL])
     5526#define RSCAN0TMID22HH (RSCAN0.TMID22.UINT8[R_IO_HH])
     5527#define RSCAN0TMPTR22 (RSCAN0.TMPTR22.UINT32)
     5528#define RSCAN0TMPTR22L (RSCAN0.TMPTR22.UINT16[R_IO_L])
     5529#define RSCAN0TMPTR22LL (RSCAN0.TMPTR22.UINT8[R_IO_LL])
     5530#define RSCAN0TMPTR22LH (RSCAN0.TMPTR22.UINT8[R_IO_LH])
     5531#define RSCAN0TMPTR22H (RSCAN0.TMPTR22.UINT16[R_IO_H])
     5532#define RSCAN0TMPTR22HL (RSCAN0.TMPTR22.UINT8[R_IO_HL])
     5533#define RSCAN0TMPTR22HH (RSCAN0.TMPTR22.UINT8[R_IO_HH])
     5534#define RSCAN0TMDF022 (RSCAN0.TMDF022.UINT32)
     5535#define RSCAN0TMDF022L (RSCAN0.TMDF022.UINT16[R_IO_L])
     5536#define RSCAN0TMDF022LL (RSCAN0.TMDF022.UINT8[R_IO_LL])
     5537#define RSCAN0TMDF022LH (RSCAN0.TMDF022.UINT8[R_IO_LH])
     5538#define RSCAN0TMDF022H (RSCAN0.TMDF022.UINT16[R_IO_H])
     5539#define RSCAN0TMDF022HL (RSCAN0.TMDF022.UINT8[R_IO_HL])
     5540#define RSCAN0TMDF022HH (RSCAN0.TMDF022.UINT8[R_IO_HH])
     5541#define RSCAN0TMDF122 (RSCAN0.TMDF122.UINT32)
     5542#define RSCAN0TMDF122L (RSCAN0.TMDF122.UINT16[R_IO_L])
     5543#define RSCAN0TMDF122LL (RSCAN0.TMDF122.UINT8[R_IO_LL])
     5544#define RSCAN0TMDF122LH (RSCAN0.TMDF122.UINT8[R_IO_LH])
     5545#define RSCAN0TMDF122H (RSCAN0.TMDF122.UINT16[R_IO_H])
     5546#define RSCAN0TMDF122HL (RSCAN0.TMDF122.UINT8[R_IO_HL])
     5547#define RSCAN0TMDF122HH (RSCAN0.TMDF122.UINT8[R_IO_HH])
     5548#define RSCAN0TMID23 (RSCAN0.TMID23.UINT32)
     5549#define RSCAN0TMID23L (RSCAN0.TMID23.UINT16[R_IO_L])
     5550#define RSCAN0TMID23LL (RSCAN0.TMID23.UINT8[R_IO_LL])
     5551#define RSCAN0TMID23LH (RSCAN0.TMID23.UINT8[R_IO_LH])
     5552#define RSCAN0TMID23H (RSCAN0.TMID23.UINT16[R_IO_H])
     5553#define RSCAN0TMID23HL (RSCAN0.TMID23.UINT8[R_IO_HL])
     5554#define RSCAN0TMID23HH (RSCAN0.TMID23.UINT8[R_IO_HH])
     5555#define RSCAN0TMPTR23 (RSCAN0.TMPTR23.UINT32)
     5556#define RSCAN0TMPTR23L (RSCAN0.TMPTR23.UINT16[R_IO_L])
     5557#define RSCAN0TMPTR23LL (RSCAN0.TMPTR23.UINT8[R_IO_LL])
     5558#define RSCAN0TMPTR23LH (RSCAN0.TMPTR23.UINT8[R_IO_LH])
     5559#define RSCAN0TMPTR23H (RSCAN0.TMPTR23.UINT16[R_IO_H])
     5560#define RSCAN0TMPTR23HL (RSCAN0.TMPTR23.UINT8[R_IO_HL])
     5561#define RSCAN0TMPTR23HH (RSCAN0.TMPTR23.UINT8[R_IO_HH])
     5562#define RSCAN0TMDF023 (RSCAN0.TMDF023.UINT32)
     5563#define RSCAN0TMDF023L (RSCAN0.TMDF023.UINT16[R_IO_L])
     5564#define RSCAN0TMDF023LL (RSCAN0.TMDF023.UINT8[R_IO_LL])
     5565#define RSCAN0TMDF023LH (RSCAN0.TMDF023.UINT8[R_IO_LH])
     5566#define RSCAN0TMDF023H (RSCAN0.TMDF023.UINT16[R_IO_H])
     5567#define RSCAN0TMDF023HL (RSCAN0.TMDF023.UINT8[R_IO_HL])
     5568#define RSCAN0TMDF023HH (RSCAN0.TMDF023.UINT8[R_IO_HH])
     5569#define RSCAN0TMDF123 (RSCAN0.TMDF123.UINT32)
     5570#define RSCAN0TMDF123L (RSCAN0.TMDF123.UINT16[R_IO_L])
     5571#define RSCAN0TMDF123LL (RSCAN0.TMDF123.UINT8[R_IO_LL])
     5572#define RSCAN0TMDF123LH (RSCAN0.TMDF123.UINT8[R_IO_LH])
     5573#define RSCAN0TMDF123H (RSCAN0.TMDF123.UINT16[R_IO_H])
     5574#define RSCAN0TMDF123HL (RSCAN0.TMDF123.UINT8[R_IO_HL])
     5575#define RSCAN0TMDF123HH (RSCAN0.TMDF123.UINT8[R_IO_HH])
     5576#define RSCAN0TMID24 (RSCAN0.TMID24.UINT32)
     5577#define RSCAN0TMID24L (RSCAN0.TMID24.UINT16[R_IO_L])
     5578#define RSCAN0TMID24LL (RSCAN0.TMID24.UINT8[R_IO_LL])
     5579#define RSCAN0TMID24LH (RSCAN0.TMID24.UINT8[R_IO_LH])
     5580#define RSCAN0TMID24H (RSCAN0.TMID24.UINT16[R_IO_H])
     5581#define RSCAN0TMID24HL (RSCAN0.TMID24.UINT8[R_IO_HL])
     5582#define RSCAN0TMID24HH (RSCAN0.TMID24.UINT8[R_IO_HH])
     5583#define RSCAN0TMPTR24 (RSCAN0.TMPTR24.UINT32)
     5584#define RSCAN0TMPTR24L (RSCAN0.TMPTR24.UINT16[R_IO_L])
     5585#define RSCAN0TMPTR24LL (RSCAN0.TMPTR24.UINT8[R_IO_LL])
     5586#define RSCAN0TMPTR24LH (RSCAN0.TMPTR24.UINT8[R_IO_LH])
     5587#define RSCAN0TMPTR24H (RSCAN0.TMPTR24.UINT16[R_IO_H])
     5588#define RSCAN0TMPTR24HL (RSCAN0.TMPTR24.UINT8[R_IO_HL])
     5589#define RSCAN0TMPTR24HH (RSCAN0.TMPTR24.UINT8[R_IO_HH])
     5590#define RSCAN0TMDF024 (RSCAN0.TMDF024.UINT32)
     5591#define RSCAN0TMDF024L (RSCAN0.TMDF024.UINT16[R_IO_L])
     5592#define RSCAN0TMDF024LL (RSCAN0.TMDF024.UINT8[R_IO_LL])
     5593#define RSCAN0TMDF024LH (RSCAN0.TMDF024.UINT8[R_IO_LH])
     5594#define RSCAN0TMDF024H (RSCAN0.TMDF024.UINT16[R_IO_H])
     5595#define RSCAN0TMDF024HL (RSCAN0.TMDF024.UINT8[R_IO_HL])
     5596#define RSCAN0TMDF024HH (RSCAN0.TMDF024.UINT8[R_IO_HH])
     5597#define RSCAN0TMDF124 (RSCAN0.TMDF124.UINT32)
     5598#define RSCAN0TMDF124L (RSCAN0.TMDF124.UINT16[R_IO_L])
     5599#define RSCAN0TMDF124LL (RSCAN0.TMDF124.UINT8[R_IO_LL])
     5600#define RSCAN0TMDF124LH (RSCAN0.TMDF124.UINT8[R_IO_LH])
     5601#define RSCAN0TMDF124H (RSCAN0.TMDF124.UINT16[R_IO_H])
     5602#define RSCAN0TMDF124HL (RSCAN0.TMDF124.UINT8[R_IO_HL])
     5603#define RSCAN0TMDF124HH (RSCAN0.TMDF124.UINT8[R_IO_HH])
     5604#define RSCAN0TMID25 (RSCAN0.TMID25.UINT32)
     5605#define RSCAN0TMID25L (RSCAN0.TMID25.UINT16[R_IO_L])
     5606#define RSCAN0TMID25LL (RSCAN0.TMID25.UINT8[R_IO_LL])
     5607#define RSCAN0TMID25LH (RSCAN0.TMID25.UINT8[R_IO_LH])
     5608#define RSCAN0TMID25H (RSCAN0.TMID25.UINT16[R_IO_H])
     5609#define RSCAN0TMID25HL (RSCAN0.TMID25.UINT8[R_IO_HL])
     5610#define RSCAN0TMID25HH (RSCAN0.TMID25.UINT8[R_IO_HH])
     5611#define RSCAN0TMPTR25 (RSCAN0.TMPTR25.UINT32)
     5612#define RSCAN0TMPTR25L (RSCAN0.TMPTR25.UINT16[R_IO_L])
     5613#define RSCAN0TMPTR25LL (RSCAN0.TMPTR25.UINT8[R_IO_LL])
     5614#define RSCAN0TMPTR25LH (RSCAN0.TMPTR25.UINT8[R_IO_LH])
     5615#define RSCAN0TMPTR25H (RSCAN0.TMPTR25.UINT16[R_IO_H])
     5616#define RSCAN0TMPTR25HL (RSCAN0.TMPTR25.UINT8[R_IO_HL])
     5617#define RSCAN0TMPTR25HH (RSCAN0.TMPTR25.UINT8[R_IO_HH])
     5618#define RSCAN0TMDF025 (RSCAN0.TMDF025.UINT32)
     5619#define RSCAN0TMDF025L (RSCAN0.TMDF025.UINT16[R_IO_L])
     5620#define RSCAN0TMDF025LL (RSCAN0.TMDF025.UINT8[R_IO_LL])
     5621#define RSCAN0TMDF025LH (RSCAN0.TMDF025.UINT8[R_IO_LH])
     5622#define RSCAN0TMDF025H (RSCAN0.TMDF025.UINT16[R_IO_H])
     5623#define RSCAN0TMDF025HL (RSCAN0.TMDF025.UINT8[R_IO_HL])
     5624#define RSCAN0TMDF025HH (RSCAN0.TMDF025.UINT8[R_IO_HH])
     5625#define RSCAN0TMDF125 (RSCAN0.TMDF125.UINT32)
     5626#define RSCAN0TMDF125L (RSCAN0.TMDF125.UINT16[R_IO_L])
     5627#define RSCAN0TMDF125LL (RSCAN0.TMDF125.UINT8[R_IO_LL])
     5628#define RSCAN0TMDF125LH (RSCAN0.TMDF125.UINT8[R_IO_LH])
     5629#define RSCAN0TMDF125H (RSCAN0.TMDF125.UINT16[R_IO_H])
     5630#define RSCAN0TMDF125HL (RSCAN0.TMDF125.UINT8[R_IO_HL])
     5631#define RSCAN0TMDF125HH (RSCAN0.TMDF125.UINT8[R_IO_HH])
     5632#define RSCAN0TMID26 (RSCAN0.TMID26.UINT32)
     5633#define RSCAN0TMID26L (RSCAN0.TMID26.UINT16[R_IO_L])
     5634#define RSCAN0TMID26LL (RSCAN0.TMID26.UINT8[R_IO_LL])
     5635#define RSCAN0TMID26LH (RSCAN0.TMID26.UINT8[R_IO_LH])
     5636#define RSCAN0TMID26H (RSCAN0.TMID26.UINT16[R_IO_H])
     5637#define RSCAN0TMID26HL (RSCAN0.TMID26.UINT8[R_IO_HL])
     5638#define RSCAN0TMID26HH (RSCAN0.TMID26.UINT8[R_IO_HH])
     5639#define RSCAN0TMPTR26 (RSCAN0.TMPTR26.UINT32)
     5640#define RSCAN0TMPTR26L (RSCAN0.TMPTR26.UINT16[R_IO_L])
     5641#define RSCAN0TMPTR26LL (RSCAN0.TMPTR26.UINT8[R_IO_LL])
     5642#define RSCAN0TMPTR26LH (RSCAN0.TMPTR26.UINT8[R_IO_LH])
     5643#define RSCAN0TMPTR26H (RSCAN0.TMPTR26.UINT16[R_IO_H])
     5644#define RSCAN0TMPTR26HL (RSCAN0.TMPTR26.UINT8[R_IO_HL])
     5645#define RSCAN0TMPTR26HH (RSCAN0.TMPTR26.UINT8[R_IO_HH])
     5646#define RSCAN0TMDF026 (RSCAN0.TMDF026.UINT32)
     5647#define RSCAN0TMDF026L (RSCAN0.TMDF026.UINT16[R_IO_L])
     5648#define RSCAN0TMDF026LL (RSCAN0.TMDF026.UINT8[R_IO_LL])
     5649#define RSCAN0TMDF026LH (RSCAN0.TMDF026.UINT8[R_IO_LH])
     5650#define RSCAN0TMDF026H (RSCAN0.TMDF026.UINT16[R_IO_H])
     5651#define RSCAN0TMDF026HL (RSCAN0.TMDF026.UINT8[R_IO_HL])
     5652#define RSCAN0TMDF026HH (RSCAN0.TMDF026.UINT8[R_IO_HH])
     5653#define RSCAN0TMDF126 (RSCAN0.TMDF126.UINT32)
     5654#define RSCAN0TMDF126L (RSCAN0.TMDF126.UINT16[R_IO_L])
     5655#define RSCAN0TMDF126LL (RSCAN0.TMDF126.UINT8[R_IO_LL])
     5656#define RSCAN0TMDF126LH (RSCAN0.TMDF126.UINT8[R_IO_LH])
     5657#define RSCAN0TMDF126H (RSCAN0.TMDF126.UINT16[R_IO_H])
     5658#define RSCAN0TMDF126HL (RSCAN0.TMDF126.UINT8[R_IO_HL])
     5659#define RSCAN0TMDF126HH (RSCAN0.TMDF126.UINT8[R_IO_HH])
     5660#define RSCAN0TMID27 (RSCAN0.TMID27.UINT32)
     5661#define RSCAN0TMID27L (RSCAN0.TMID27.UINT16[R_IO_L])
     5662#define RSCAN0TMID27LL (RSCAN0.TMID27.UINT8[R_IO_LL])
     5663#define RSCAN0TMID27LH (RSCAN0.TMID27.UINT8[R_IO_LH])
     5664#define RSCAN0TMID27H (RSCAN0.TMID27.UINT16[R_IO_H])
     5665#define RSCAN0TMID27HL (RSCAN0.TMID27.UINT8[R_IO_HL])
     5666#define RSCAN0TMID27HH (RSCAN0.TMID27.UINT8[R_IO_HH])
     5667#define RSCAN0TMPTR27 (RSCAN0.TMPTR27.UINT32)
     5668#define RSCAN0TMPTR27L (RSCAN0.TMPTR27.UINT16[R_IO_L])
     5669#define RSCAN0TMPTR27LL (RSCAN0.TMPTR27.UINT8[R_IO_LL])
     5670#define RSCAN0TMPTR27LH (RSCAN0.TMPTR27.UINT8[R_IO_LH])
     5671#define RSCAN0TMPTR27H (RSCAN0.TMPTR27.UINT16[R_IO_H])
     5672#define RSCAN0TMPTR27HL (RSCAN0.TMPTR27.UINT8[R_IO_HL])
     5673#define RSCAN0TMPTR27HH (RSCAN0.TMPTR27.UINT8[R_IO_HH])
     5674#define RSCAN0TMDF027 (RSCAN0.TMDF027.UINT32)
     5675#define RSCAN0TMDF027L (RSCAN0.TMDF027.UINT16[R_IO_L])
     5676#define RSCAN0TMDF027LL (RSCAN0.TMDF027.UINT8[R_IO_LL])
     5677#define RSCAN0TMDF027LH (RSCAN0.TMDF027.UINT8[R_IO_LH])
     5678#define RSCAN0TMDF027H (RSCAN0.TMDF027.UINT16[R_IO_H])
     5679#define RSCAN0TMDF027HL (RSCAN0.TMDF027.UINT8[R_IO_HL])
     5680#define RSCAN0TMDF027HH (RSCAN0.TMDF027.UINT8[R_IO_HH])
     5681#define RSCAN0TMDF127 (RSCAN0.TMDF127.UINT32)
     5682#define RSCAN0TMDF127L (RSCAN0.TMDF127.UINT16[R_IO_L])
     5683#define RSCAN0TMDF127LL (RSCAN0.TMDF127.UINT8[R_IO_LL])
     5684#define RSCAN0TMDF127LH (RSCAN0.TMDF127.UINT8[R_IO_LH])
     5685#define RSCAN0TMDF127H (RSCAN0.TMDF127.UINT16[R_IO_H])
     5686#define RSCAN0TMDF127HL (RSCAN0.TMDF127.UINT8[R_IO_HL])
     5687#define RSCAN0TMDF127HH (RSCAN0.TMDF127.UINT8[R_IO_HH])
     5688#define RSCAN0TMID28 (RSCAN0.TMID28.UINT32)
     5689#define RSCAN0TMID28L (RSCAN0.TMID28.UINT16[R_IO_L])
     5690#define RSCAN0TMID28LL (RSCAN0.TMID28.UINT8[R_IO_LL])
     5691#define RSCAN0TMID28LH (RSCAN0.TMID28.UINT8[R_IO_LH])
     5692#define RSCAN0TMID28H (RSCAN0.TMID28.UINT16[R_IO_H])
     5693#define RSCAN0TMID28HL (RSCAN0.TMID28.UINT8[R_IO_HL])
     5694#define RSCAN0TMID28HH (RSCAN0.TMID28.UINT8[R_IO_HH])
     5695#define RSCAN0TMPTR28 (RSCAN0.TMPTR28.UINT32)
     5696#define RSCAN0TMPTR28L (RSCAN0.TMPTR28.UINT16[R_IO_L])
     5697#define RSCAN0TMPTR28LL (RSCAN0.TMPTR28.UINT8[R_IO_LL])
     5698#define RSCAN0TMPTR28LH (RSCAN0.TMPTR28.UINT8[R_IO_LH])
     5699#define RSCAN0TMPTR28H (RSCAN0.TMPTR28.UINT16[R_IO_H])
     5700#define RSCAN0TMPTR28HL (RSCAN0.TMPTR28.UINT8[R_IO_HL])
     5701#define RSCAN0TMPTR28HH (RSCAN0.TMPTR28.UINT8[R_IO_HH])
     5702#define RSCAN0TMDF028 (RSCAN0.TMDF028.UINT32)
     5703#define RSCAN0TMDF028L (RSCAN0.TMDF028.UINT16[R_IO_L])
     5704#define RSCAN0TMDF028LL (RSCAN0.TMDF028.UINT8[R_IO_LL])
     5705#define RSCAN0TMDF028LH (RSCAN0.TMDF028.UINT8[R_IO_LH])
     5706#define RSCAN0TMDF028H (RSCAN0.TMDF028.UINT16[R_IO_H])
     5707#define RSCAN0TMDF028HL (RSCAN0.TMDF028.UINT8[R_IO_HL])
     5708#define RSCAN0TMDF028HH (RSCAN0.TMDF028.UINT8[R_IO_HH])
     5709#define RSCAN0TMDF128 (RSCAN0.TMDF128.UINT32)
     5710#define RSCAN0TMDF128L (RSCAN0.TMDF128.UINT16[R_IO_L])
     5711#define RSCAN0TMDF128LL (RSCAN0.TMDF128.UINT8[R_IO_LL])
     5712#define RSCAN0TMDF128LH (RSCAN0.TMDF128.UINT8[R_IO_LH])
     5713#define RSCAN0TMDF128H (RSCAN0.TMDF128.UINT16[R_IO_H])
     5714#define RSCAN0TMDF128HL (RSCAN0.TMDF128.UINT8[R_IO_HL])
     5715#define RSCAN0TMDF128HH (RSCAN0.TMDF128.UINT8[R_IO_HH])
     5716#define RSCAN0TMID29 (RSCAN0.TMID29.UINT32)
     5717#define RSCAN0TMID29L (RSCAN0.TMID29.UINT16[R_IO_L])
     5718#define RSCAN0TMID29LL (RSCAN0.TMID29.UINT8[R_IO_LL])
     5719#define RSCAN0TMID29LH (RSCAN0.TMID29.UINT8[R_IO_LH])
     5720#define RSCAN0TMID29H (RSCAN0.TMID29.UINT16[R_IO_H])
     5721#define RSCAN0TMID29HL (RSCAN0.TMID29.UINT8[R_IO_HL])
     5722#define RSCAN0TMID29HH (RSCAN0.TMID29.UINT8[R_IO_HH])
     5723#define RSCAN0TMPTR29 (RSCAN0.TMPTR29.UINT32)
     5724#define RSCAN0TMPTR29L (RSCAN0.TMPTR29.UINT16[R_IO_L])
     5725#define RSCAN0TMPTR29LL (RSCAN0.TMPTR29.UINT8[R_IO_LL])
     5726#define RSCAN0TMPTR29LH (RSCAN0.TMPTR29.UINT8[R_IO_LH])
     5727#define RSCAN0TMPTR29H (RSCAN0.TMPTR29.UINT16[R_IO_H])
     5728#define RSCAN0TMPTR29HL (RSCAN0.TMPTR29.UINT8[R_IO_HL])
     5729#define RSCAN0TMPTR29HH (RSCAN0.TMPTR29.UINT8[R_IO_HH])
     5730#define RSCAN0TMDF029 (RSCAN0.TMDF029.UINT32)
     5731#define RSCAN0TMDF029L (RSCAN0.TMDF029.UINT16[R_IO_L])
     5732#define RSCAN0TMDF029LL (RSCAN0.TMDF029.UINT8[R_IO_LL])
     5733#define RSCAN0TMDF029LH (RSCAN0.TMDF029.UINT8[R_IO_LH])
     5734#define RSCAN0TMDF029H (RSCAN0.TMDF029.UINT16[R_IO_H])
     5735#define RSCAN0TMDF029HL (RSCAN0.TMDF029.UINT8[R_IO_HL])
     5736#define RSCAN0TMDF029HH (RSCAN0.TMDF029.UINT8[R_IO_HH])
     5737#define RSCAN0TMDF129 (RSCAN0.TMDF129.UINT32)
     5738#define RSCAN0TMDF129L (RSCAN0.TMDF129.UINT16[R_IO_L])
     5739#define RSCAN0TMDF129LL (RSCAN0.TMDF129.UINT8[R_IO_LL])
     5740#define RSCAN0TMDF129LH (RSCAN0.TMDF129.UINT8[R_IO_LH])
     5741#define RSCAN0TMDF129H (RSCAN0.TMDF129.UINT16[R_IO_H])
     5742#define RSCAN0TMDF129HL (RSCAN0.TMDF129.UINT8[R_IO_HL])
     5743#define RSCAN0TMDF129HH (RSCAN0.TMDF129.UINT8[R_IO_HH])
     5744#define RSCAN0TMID30 (RSCAN0.TMID30.UINT32)
     5745#define RSCAN0TMID30L (RSCAN0.TMID30.UINT16[R_IO_L])
     5746#define RSCAN0TMID30LL (RSCAN0.TMID30.UINT8[R_IO_LL])
     5747#define RSCAN0TMID30LH (RSCAN0.TMID30.UINT8[R_IO_LH])
     5748#define RSCAN0TMID30H (RSCAN0.TMID30.UINT16[R_IO_H])
     5749#define RSCAN0TMID30HL (RSCAN0.TMID30.UINT8[R_IO_HL])
     5750#define RSCAN0TMID30HH (RSCAN0.TMID30.UINT8[R_IO_HH])
     5751#define RSCAN0TMPTR30 (RSCAN0.TMPTR30.UINT32)
     5752#define RSCAN0TMPTR30L (RSCAN0.TMPTR30.UINT16[R_IO_L])
     5753#define RSCAN0TMPTR30LL (RSCAN0.TMPTR30.UINT8[R_IO_LL])
     5754#define RSCAN0TMPTR30LH (RSCAN0.TMPTR30.UINT8[R_IO_LH])
     5755#define RSCAN0TMPTR30H (RSCAN0.TMPTR30.UINT16[R_IO_H])
     5756#define RSCAN0TMPTR30HL (RSCAN0.TMPTR30.UINT8[R_IO_HL])
     5757#define RSCAN0TMPTR30HH (RSCAN0.TMPTR30.UINT8[R_IO_HH])
     5758#define RSCAN0TMDF030 (RSCAN0.TMDF030.UINT32)
     5759#define RSCAN0TMDF030L (RSCAN0.TMDF030.UINT16[R_IO_L])
     5760#define RSCAN0TMDF030LL (RSCAN0.TMDF030.UINT8[R_IO_LL])
     5761#define RSCAN0TMDF030LH (RSCAN0.TMDF030.UINT8[R_IO_LH])
     5762#define RSCAN0TMDF030H (RSCAN0.TMDF030.UINT16[R_IO_H])
     5763#define RSCAN0TMDF030HL (RSCAN0.TMDF030.UINT8[R_IO_HL])
     5764#define RSCAN0TMDF030HH (RSCAN0.TMDF030.UINT8[R_IO_HH])
     5765#define RSCAN0TMDF130 (RSCAN0.TMDF130.UINT32)
     5766#define RSCAN0TMDF130L (RSCAN0.TMDF130.UINT16[R_IO_L])
     5767#define RSCAN0TMDF130LL (RSCAN0.TMDF130.UINT8[R_IO_LL])
     5768#define RSCAN0TMDF130LH (RSCAN0.TMDF130.UINT8[R_IO_LH])
     5769#define RSCAN0TMDF130H (RSCAN0.TMDF130.UINT16[R_IO_H])
     5770#define RSCAN0TMDF130HL (RSCAN0.TMDF130.UINT8[R_IO_HL])
     5771#define RSCAN0TMDF130HH (RSCAN0.TMDF130.UINT8[R_IO_HH])
     5772#define RSCAN0TMID31 (RSCAN0.TMID31.UINT32)
     5773#define RSCAN0TMID31L (RSCAN0.TMID31.UINT16[R_IO_L])
     5774#define RSCAN0TMID31LL (RSCAN0.TMID31.UINT8[R_IO_LL])
     5775#define RSCAN0TMID31LH (RSCAN0.TMID31.UINT8[R_IO_LH])
     5776#define RSCAN0TMID31H (RSCAN0.TMID31.UINT16[R_IO_H])
     5777#define RSCAN0TMID31HL (RSCAN0.TMID31.UINT8[R_IO_HL])
     5778#define RSCAN0TMID31HH (RSCAN0.TMID31.UINT8[R_IO_HH])
     5779#define RSCAN0TMPTR31 (RSCAN0.TMPTR31.UINT32)
     5780#define RSCAN0TMPTR31L (RSCAN0.TMPTR31.UINT16[R_IO_L])
     5781#define RSCAN0TMPTR31LL (RSCAN0.TMPTR31.UINT8[R_IO_LL])
     5782#define RSCAN0TMPTR31LH (RSCAN0.TMPTR31.UINT8[R_IO_LH])
     5783#define RSCAN0TMPTR31H (RSCAN0.TMPTR31.UINT16[R_IO_H])
     5784#define RSCAN0TMPTR31HL (RSCAN0.TMPTR31.UINT8[R_IO_HL])
     5785#define RSCAN0TMPTR31HH (RSCAN0.TMPTR31.UINT8[R_IO_HH])
     5786#define RSCAN0TMDF031 (RSCAN0.TMDF031.UINT32)
     5787#define RSCAN0TMDF031L (RSCAN0.TMDF031.UINT16[R_IO_L])
     5788#define RSCAN0TMDF031LL (RSCAN0.TMDF031.UINT8[R_IO_LL])
     5789#define RSCAN0TMDF031LH (RSCAN0.TMDF031.UINT8[R_IO_LH])
     5790#define RSCAN0TMDF031H (RSCAN0.TMDF031.UINT16[R_IO_H])
     5791#define RSCAN0TMDF031HL (RSCAN0.TMDF031.UINT8[R_IO_HL])
     5792#define RSCAN0TMDF031HH (RSCAN0.TMDF031.UINT8[R_IO_HH])
     5793#define RSCAN0TMDF131 (RSCAN0.TMDF131.UINT32)
     5794#define RSCAN0TMDF131L (RSCAN0.TMDF131.UINT16[R_IO_L])
     5795#define RSCAN0TMDF131LL (RSCAN0.TMDF131.UINT8[R_IO_LL])
     5796#define RSCAN0TMDF131LH (RSCAN0.TMDF131.UINT8[R_IO_LH])
     5797#define RSCAN0TMDF131H (RSCAN0.TMDF131.UINT16[R_IO_H])
     5798#define RSCAN0TMDF131HL (RSCAN0.TMDF131.UINT8[R_IO_HL])
     5799#define RSCAN0TMDF131HH (RSCAN0.TMDF131.UINT8[R_IO_HH])
     5800#define RSCAN0TMID32 (RSCAN0.TMID32.UINT32)
     5801#define RSCAN0TMID32L (RSCAN0.TMID32.UINT16[R_IO_L])
     5802#define RSCAN0TMID32LL (RSCAN0.TMID32.UINT8[R_IO_LL])
     5803#define RSCAN0TMID32LH (RSCAN0.TMID32.UINT8[R_IO_LH])
     5804#define RSCAN0TMID32H (RSCAN0.TMID32.UINT16[R_IO_H])
     5805#define RSCAN0TMID32HL (RSCAN0.TMID32.UINT8[R_IO_HL])
     5806#define RSCAN0TMID32HH (RSCAN0.TMID32.UINT8[R_IO_HH])
     5807#define RSCAN0TMPTR32 (RSCAN0.TMPTR32.UINT32)
     5808#define RSCAN0TMPTR32L (RSCAN0.TMPTR32.UINT16[R_IO_L])
     5809#define RSCAN0TMPTR32LL (RSCAN0.TMPTR32.UINT8[R_IO_LL])
     5810#define RSCAN0TMPTR32LH (RSCAN0.TMPTR32.UINT8[R_IO_LH])
     5811#define RSCAN0TMPTR32H (RSCAN0.TMPTR32.UINT16[R_IO_H])
     5812#define RSCAN0TMPTR32HL (RSCAN0.TMPTR32.UINT8[R_IO_HL])
     5813#define RSCAN0TMPTR32HH (RSCAN0.TMPTR32.UINT8[R_IO_HH])
     5814#define RSCAN0TMDF032 (RSCAN0.TMDF032.UINT32)
     5815#define RSCAN0TMDF032L (RSCAN0.TMDF032.UINT16[R_IO_L])
     5816#define RSCAN0TMDF032LL (RSCAN0.TMDF032.UINT8[R_IO_LL])
     5817#define RSCAN0TMDF032LH (RSCAN0.TMDF032.UINT8[R_IO_LH])
     5818#define RSCAN0TMDF032H (RSCAN0.TMDF032.UINT16[R_IO_H])
     5819#define RSCAN0TMDF032HL (RSCAN0.TMDF032.UINT8[R_IO_HL])
     5820#define RSCAN0TMDF032HH (RSCAN0.TMDF032.UINT8[R_IO_HH])
     5821#define RSCAN0TMDF132 (RSCAN0.TMDF132.UINT32)
     5822#define RSCAN0TMDF132L (RSCAN0.TMDF132.UINT16[R_IO_L])
     5823#define RSCAN0TMDF132LL (RSCAN0.TMDF132.UINT8[R_IO_LL])
     5824#define RSCAN0TMDF132LH (RSCAN0.TMDF132.UINT8[R_IO_LH])
     5825#define RSCAN0TMDF132H (RSCAN0.TMDF132.UINT16[R_IO_H])
     5826#define RSCAN0TMDF132HL (RSCAN0.TMDF132.UINT8[R_IO_HL])
     5827#define RSCAN0TMDF132HH (RSCAN0.TMDF132.UINT8[R_IO_HH])
     5828#define RSCAN0TMID33 (RSCAN0.TMID33.UINT32)
     5829#define RSCAN0TMID33L (RSCAN0.TMID33.UINT16[R_IO_L])
     5830#define RSCAN0TMID33LL (RSCAN0.TMID33.UINT8[R_IO_LL])
     5831#define RSCAN0TMID33LH (RSCAN0.TMID33.UINT8[R_IO_LH])
     5832#define RSCAN0TMID33H (RSCAN0.TMID33.UINT16[R_IO_H])
     5833#define RSCAN0TMID33HL (RSCAN0.TMID33.UINT8[R_IO_HL])
     5834#define RSCAN0TMID33HH (RSCAN0.TMID33.UINT8[R_IO_HH])
     5835#define RSCAN0TMPTR33 (RSCAN0.TMPTR33.UINT32)
     5836#define RSCAN0TMPTR33L (RSCAN0.TMPTR33.UINT16[R_IO_L])
     5837#define RSCAN0TMPTR33LL (RSCAN0.TMPTR33.UINT8[R_IO_LL])
     5838#define RSCAN0TMPTR33LH (RSCAN0.TMPTR33.UINT8[R_IO_LH])
     5839#define RSCAN0TMPTR33H (RSCAN0.TMPTR33.UINT16[R_IO_H])
     5840#define RSCAN0TMPTR33HL (RSCAN0.TMPTR33.UINT8[R_IO_HL])
     5841#define RSCAN0TMPTR33HH (RSCAN0.TMPTR33.UINT8[R_IO_HH])
     5842#define RSCAN0TMDF033 (RSCAN0.TMDF033.UINT32)
     5843#define RSCAN0TMDF033L (RSCAN0.TMDF033.UINT16[R_IO_L])
     5844#define RSCAN0TMDF033LL (RSCAN0.TMDF033.UINT8[R_IO_LL])
     5845#define RSCAN0TMDF033LH (RSCAN0.TMDF033.UINT8[R_IO_LH])
     5846#define RSCAN0TMDF033H (RSCAN0.TMDF033.UINT16[R_IO_H])
     5847#define RSCAN0TMDF033HL (RSCAN0.TMDF033.UINT8[R_IO_HL])
     5848#define RSCAN0TMDF033HH (RSCAN0.TMDF033.UINT8[R_IO_HH])
     5849#define RSCAN0TMDF133 (RSCAN0.TMDF133.UINT32)
     5850#define RSCAN0TMDF133L (RSCAN0.TMDF133.UINT16[R_IO_L])
     5851#define RSCAN0TMDF133LL (RSCAN0.TMDF133.UINT8[R_IO_LL])
     5852#define RSCAN0TMDF133LH (RSCAN0.TMDF133.UINT8[R_IO_LH])
     5853#define RSCAN0TMDF133H (RSCAN0.TMDF133.UINT16[R_IO_H])
     5854#define RSCAN0TMDF133HL (RSCAN0.TMDF133.UINT8[R_IO_HL])
     5855#define RSCAN0TMDF133HH (RSCAN0.TMDF133.UINT8[R_IO_HH])
     5856#define RSCAN0TMID34 (RSCAN0.TMID34.UINT32)
     5857#define RSCAN0TMID34L (RSCAN0.TMID34.UINT16[R_IO_L])
     5858#define RSCAN0TMID34LL (RSCAN0.TMID34.UINT8[R_IO_LL])
     5859#define RSCAN0TMID34LH (RSCAN0.TMID34.UINT8[R_IO_LH])
     5860#define RSCAN0TMID34H (RSCAN0.TMID34.UINT16[R_IO_H])
     5861#define RSCAN0TMID34HL (RSCAN0.TMID34.UINT8[R_IO_HL])
     5862#define RSCAN0TMID34HH (RSCAN0.TMID34.UINT8[R_IO_HH])
     5863#define RSCAN0TMPTR34 (RSCAN0.TMPTR34.UINT32)
     5864#define RSCAN0TMPTR34L (RSCAN0.TMPTR34.UINT16[R_IO_L])
     5865#define RSCAN0TMPTR34LL (RSCAN0.TMPTR34.UINT8[R_IO_LL])
     5866#define RSCAN0TMPTR34LH (RSCAN0.TMPTR34.UINT8[R_IO_LH])
     5867#define RSCAN0TMPTR34H (RSCAN0.TMPTR34.UINT16[R_IO_H])
     5868#define RSCAN0TMPTR34HL (RSCAN0.TMPTR34.UINT8[R_IO_HL])
     5869#define RSCAN0TMPTR34HH (RSCAN0.TMPTR34.UINT8[R_IO_HH])
     5870#define RSCAN0TMDF034 (RSCAN0.TMDF034.UINT32)
     5871#define RSCAN0TMDF034L (RSCAN0.TMDF034.UINT16[R_IO_L])
     5872#define RSCAN0TMDF034LL (RSCAN0.TMDF034.UINT8[R_IO_LL])
     5873#define RSCAN0TMDF034LH (RSCAN0.TMDF034.UINT8[R_IO_LH])
     5874#define RSCAN0TMDF034H (RSCAN0.TMDF034.UINT16[R_IO_H])
     5875#define RSCAN0TMDF034HL (RSCAN0.TMDF034.UINT8[R_IO_HL])
     5876#define RSCAN0TMDF034HH (RSCAN0.TMDF034.UINT8[R_IO_HH])
     5877#define RSCAN0TMDF134 (RSCAN0.TMDF134.UINT32)
     5878#define RSCAN0TMDF134L (RSCAN0.TMDF134.UINT16[R_IO_L])
     5879#define RSCAN0TMDF134LL (RSCAN0.TMDF134.UINT8[R_IO_LL])
     5880#define RSCAN0TMDF134LH (RSCAN0.TMDF134.UINT8[R_IO_LH])
     5881#define RSCAN0TMDF134H (RSCAN0.TMDF134.UINT16[R_IO_H])
     5882#define RSCAN0TMDF134HL (RSCAN0.TMDF134.UINT8[R_IO_HL])
     5883#define RSCAN0TMDF134HH (RSCAN0.TMDF134.UINT8[R_IO_HH])
     5884#define RSCAN0TMID35 (RSCAN0.TMID35.UINT32)
     5885#define RSCAN0TMID35L (RSCAN0.TMID35.UINT16[R_IO_L])
     5886#define RSCAN0TMID35LL (RSCAN0.TMID35.UINT8[R_IO_LL])
     5887#define RSCAN0TMID35LH (RSCAN0.TMID35.UINT8[R_IO_LH])
     5888#define RSCAN0TMID35H (RSCAN0.TMID35.UINT16[R_IO_H])
     5889#define RSCAN0TMID35HL (RSCAN0.TMID35.UINT8[R_IO_HL])
     5890#define RSCAN0TMID35HH (RSCAN0.TMID35.UINT8[R_IO_HH])
     5891#define RSCAN0TMPTR35 (RSCAN0.TMPTR35.UINT32)
     5892#define RSCAN0TMPTR35L (RSCAN0.TMPTR35.UINT16[R_IO_L])
     5893#define RSCAN0TMPTR35LL (RSCAN0.TMPTR35.UINT8[R_IO_LL])
     5894#define RSCAN0TMPTR35LH (RSCAN0.TMPTR35.UINT8[R_IO_LH])
     5895#define RSCAN0TMPTR35H (RSCAN0.TMPTR35.UINT16[R_IO_H])
     5896#define RSCAN0TMPTR35HL (RSCAN0.TMPTR35.UINT8[R_IO_HL])
     5897#define RSCAN0TMPTR35HH (RSCAN0.TMPTR35.UINT8[R_IO_HH])
     5898#define RSCAN0TMDF035 (RSCAN0.TMDF035.UINT32)
     5899#define RSCAN0TMDF035L (RSCAN0.TMDF035.UINT16[R_IO_L])
     5900#define RSCAN0TMDF035LL (RSCAN0.TMDF035.UINT8[R_IO_LL])
     5901#define RSCAN0TMDF035LH (RSCAN0.TMDF035.UINT8[R_IO_LH])
     5902#define RSCAN0TMDF035H (RSCAN0.TMDF035.UINT16[R_IO_H])
     5903#define RSCAN0TMDF035HL (RSCAN0.TMDF035.UINT8[R_IO_HL])
     5904#define RSCAN0TMDF035HH (RSCAN0.TMDF035.UINT8[R_IO_HH])
     5905#define RSCAN0TMDF135 (RSCAN0.TMDF135.UINT32)
     5906#define RSCAN0TMDF135L (RSCAN0.TMDF135.UINT16[R_IO_L])
     5907#define RSCAN0TMDF135LL (RSCAN0.TMDF135.UINT8[R_IO_LL])
     5908#define RSCAN0TMDF135LH (RSCAN0.TMDF135.UINT8[R_IO_LH])
     5909#define RSCAN0TMDF135H (RSCAN0.TMDF135.UINT16[R_IO_H])
     5910#define RSCAN0TMDF135HL (RSCAN0.TMDF135.UINT8[R_IO_HL])
     5911#define RSCAN0TMDF135HH (RSCAN0.TMDF135.UINT8[R_IO_HH])
     5912#define RSCAN0TMID36 (RSCAN0.TMID36.UINT32)
     5913#define RSCAN0TMID36L (RSCAN0.TMID36.UINT16[R_IO_L])
     5914#define RSCAN0TMID36LL (RSCAN0.TMID36.UINT8[R_IO_LL])
     5915#define RSCAN0TMID36LH (RSCAN0.TMID36.UINT8[R_IO_LH])
     5916#define RSCAN0TMID36H (RSCAN0.TMID36.UINT16[R_IO_H])
     5917#define RSCAN0TMID36HL (RSCAN0.TMID36.UINT8[R_IO_HL])
     5918#define RSCAN0TMID36HH (RSCAN0.TMID36.UINT8[R_IO_HH])
     5919#define RSCAN0TMPTR36 (RSCAN0.TMPTR36.UINT32)
     5920#define RSCAN0TMPTR36L (RSCAN0.TMPTR36.UINT16[R_IO_L])
     5921#define RSCAN0TMPTR36LL (RSCAN0.TMPTR36.UINT8[R_IO_LL])
     5922#define RSCAN0TMPTR36LH (RSCAN0.TMPTR36.UINT8[R_IO_LH])
     5923#define RSCAN0TMPTR36H (RSCAN0.TMPTR36.UINT16[R_IO_H])
     5924#define RSCAN0TMPTR36HL (RSCAN0.TMPTR36.UINT8[R_IO_HL])
     5925#define RSCAN0TMPTR36HH (RSCAN0.TMPTR36.UINT8[R_IO_HH])
     5926#define RSCAN0TMDF036 (RSCAN0.TMDF036.UINT32)
     5927#define RSCAN0TMDF036L (RSCAN0.TMDF036.UINT16[R_IO_L])
     5928#define RSCAN0TMDF036LL (RSCAN0.TMDF036.UINT8[R_IO_LL])
     5929#define RSCAN0TMDF036LH (RSCAN0.TMDF036.UINT8[R_IO_LH])
     5930#define RSCAN0TMDF036H (RSCAN0.TMDF036.UINT16[R_IO_H])
     5931#define RSCAN0TMDF036HL (RSCAN0.TMDF036.UINT8[R_IO_HL])
     5932#define RSCAN0TMDF036HH (RSCAN0.TMDF036.UINT8[R_IO_HH])
     5933#define RSCAN0TMDF136 (RSCAN0.TMDF136.UINT32)
     5934#define RSCAN0TMDF136L (RSCAN0.TMDF136.UINT16[R_IO_L])
     5935#define RSCAN0TMDF136LL (RSCAN0.TMDF136.UINT8[R_IO_LL])
     5936#define RSCAN0TMDF136LH (RSCAN0.TMDF136.UINT8[R_IO_LH])
     5937#define RSCAN0TMDF136H (RSCAN0.TMDF136.UINT16[R_IO_H])
     5938#define RSCAN0TMDF136HL (RSCAN0.TMDF136.UINT8[R_IO_HL])
     5939#define RSCAN0TMDF136HH (RSCAN0.TMDF136.UINT8[R_IO_HH])
     5940#define RSCAN0TMID37 (RSCAN0.TMID37.UINT32)
     5941#define RSCAN0TMID37L (RSCAN0.TMID37.UINT16[R_IO_L])
     5942#define RSCAN0TMID37LL (RSCAN0.TMID37.UINT8[R_IO_LL])
     5943#define RSCAN0TMID37LH (RSCAN0.TMID37.UINT8[R_IO_LH])
     5944#define RSCAN0TMID37H (RSCAN0.TMID37.UINT16[R_IO_H])
     5945#define RSCAN0TMID37HL (RSCAN0.TMID37.UINT8[R_IO_HL])
     5946#define RSCAN0TMID37HH (RSCAN0.TMID37.UINT8[R_IO_HH])
     5947#define RSCAN0TMPTR37 (RSCAN0.TMPTR37.UINT32)
     5948#define RSCAN0TMPTR37L (RSCAN0.TMPTR37.UINT16[R_IO_L])
     5949#define RSCAN0TMPTR37LL (RSCAN0.TMPTR37.UINT8[R_IO_LL])
     5950#define RSCAN0TMPTR37LH (RSCAN0.TMPTR37.UINT8[R_IO_LH])
     5951#define RSCAN0TMPTR37H (RSCAN0.TMPTR37.UINT16[R_IO_H])
     5952#define RSCAN0TMPTR37HL (RSCAN0.TMPTR37.UINT8[R_IO_HL])
     5953#define RSCAN0TMPTR37HH (RSCAN0.TMPTR37.UINT8[R_IO_HH])
     5954#define RSCAN0TMDF037 (RSCAN0.TMDF037.UINT32)
     5955#define RSCAN0TMDF037L (RSCAN0.TMDF037.UINT16[R_IO_L])
     5956#define RSCAN0TMDF037LL (RSCAN0.TMDF037.UINT8[R_IO_LL])
     5957#define RSCAN0TMDF037LH (RSCAN0.TMDF037.UINT8[R_IO_LH])
     5958#define RSCAN0TMDF037H (RSCAN0.TMDF037.UINT16[R_IO_H])
     5959#define RSCAN0TMDF037HL (RSCAN0.TMDF037.UINT8[R_IO_HL])
     5960#define RSCAN0TMDF037HH (RSCAN0.TMDF037.UINT8[R_IO_HH])
     5961#define RSCAN0TMDF137 (RSCAN0.TMDF137.UINT32)
     5962#define RSCAN0TMDF137L (RSCAN0.TMDF137.UINT16[R_IO_L])
     5963#define RSCAN0TMDF137LL (RSCAN0.TMDF137.UINT8[R_IO_LL])
     5964#define RSCAN0TMDF137LH (RSCAN0.TMDF137.UINT8[R_IO_LH])
     5965#define RSCAN0TMDF137H (RSCAN0.TMDF137.UINT16[R_IO_H])
     5966#define RSCAN0TMDF137HL (RSCAN0.TMDF137.UINT8[R_IO_HL])
     5967#define RSCAN0TMDF137HH (RSCAN0.TMDF137.UINT8[R_IO_HH])
     5968#define RSCAN0TMID38 (RSCAN0.TMID38.UINT32)
     5969#define RSCAN0TMID38L (RSCAN0.TMID38.UINT16[R_IO_L])
     5970#define RSCAN0TMID38LL (RSCAN0.TMID38.UINT8[R_IO_LL])
     5971#define RSCAN0TMID38LH (RSCAN0.TMID38.UINT8[R_IO_LH])
     5972#define RSCAN0TMID38H (RSCAN0.TMID38.UINT16[R_IO_H])
     5973#define RSCAN0TMID38HL (RSCAN0.TMID38.UINT8[R_IO_HL])
     5974#define RSCAN0TMID38HH (RSCAN0.TMID38.UINT8[R_IO_HH])
     5975#define RSCAN0TMPTR38 (RSCAN0.TMPTR38.UINT32)
     5976#define RSCAN0TMPTR38L (RSCAN0.TMPTR38.UINT16[R_IO_L])
     5977#define RSCAN0TMPTR38LL (RSCAN0.TMPTR38.UINT8[R_IO_LL])
     5978#define RSCAN0TMPTR38LH (RSCAN0.TMPTR38.UINT8[R_IO_LH])
     5979#define RSCAN0TMPTR38H (RSCAN0.TMPTR38.UINT16[R_IO_H])
     5980#define RSCAN0TMPTR38HL (RSCAN0.TMPTR38.UINT8[R_IO_HL])
     5981#define RSCAN0TMPTR38HH (RSCAN0.TMPTR38.UINT8[R_IO_HH])
     5982#define RSCAN0TMDF038 (RSCAN0.TMDF038.UINT32)
     5983#define RSCAN0TMDF038L (RSCAN0.TMDF038.UINT16[R_IO_L])
     5984#define RSCAN0TMDF038LL (RSCAN0.TMDF038.UINT8[R_IO_LL])
     5985#define RSCAN0TMDF038LH (RSCAN0.TMDF038.UINT8[R_IO_LH])
     5986#define RSCAN0TMDF038H (RSCAN0.TMDF038.UINT16[R_IO_H])
     5987#define RSCAN0TMDF038HL (RSCAN0.TMDF038.UINT8[R_IO_HL])
     5988#define RSCAN0TMDF038HH (RSCAN0.TMDF038.UINT8[R_IO_HH])
     5989#define RSCAN0TMDF138 (RSCAN0.TMDF138.UINT32)
     5990#define RSCAN0TMDF138L (RSCAN0.TMDF138.UINT16[R_IO_L])
     5991#define RSCAN0TMDF138LL (RSCAN0.TMDF138.UINT8[R_IO_LL])
     5992#define RSCAN0TMDF138LH (RSCAN0.TMDF138.UINT8[R_IO_LH])
     5993#define RSCAN0TMDF138H (RSCAN0.TMDF138.UINT16[R_IO_H])
     5994#define RSCAN0TMDF138HL (RSCAN0.TMDF138.UINT8[R_IO_HL])
     5995#define RSCAN0TMDF138HH (RSCAN0.TMDF138.UINT8[R_IO_HH])
     5996#define RSCAN0TMID39 (RSCAN0.TMID39.UINT32)
     5997#define RSCAN0TMID39L (RSCAN0.TMID39.UINT16[R_IO_L])
     5998#define RSCAN0TMID39LL (RSCAN0.TMID39.UINT8[R_IO_LL])
     5999#define RSCAN0TMID39LH (RSCAN0.TMID39.UINT8[R_IO_LH])
     6000#define RSCAN0TMID39H (RSCAN0.TMID39.UINT16[R_IO_H])
     6001#define RSCAN0TMID39HL (RSCAN0.TMID39.UINT8[R_IO_HL])
     6002#define RSCAN0TMID39HH (RSCAN0.TMID39.UINT8[R_IO_HH])
     6003#define RSCAN0TMPTR39 (RSCAN0.TMPTR39.UINT32)
     6004#define RSCAN0TMPTR39L (RSCAN0.TMPTR39.UINT16[R_IO_L])
     6005#define RSCAN0TMPTR39LL (RSCAN0.TMPTR39.UINT8[R_IO_LL])
     6006#define RSCAN0TMPTR39LH (RSCAN0.TMPTR39.UINT8[R_IO_LH])
     6007#define RSCAN0TMPTR39H (RSCAN0.TMPTR39.UINT16[R_IO_H])
     6008#define RSCAN0TMPTR39HL (RSCAN0.TMPTR39.UINT8[R_IO_HL])
     6009#define RSCAN0TMPTR39HH (RSCAN0.TMPTR39.UINT8[R_IO_HH])
     6010#define RSCAN0TMDF039 (RSCAN0.TMDF039.UINT32)
     6011#define RSCAN0TMDF039L (RSCAN0.TMDF039.UINT16[R_IO_L])
     6012#define RSCAN0TMDF039LL (RSCAN0.TMDF039.UINT8[R_IO_LL])
     6013#define RSCAN0TMDF039LH (RSCAN0.TMDF039.UINT8[R_IO_LH])
     6014#define RSCAN0TMDF039H (RSCAN0.TMDF039.UINT16[R_IO_H])
     6015#define RSCAN0TMDF039HL (RSCAN0.TMDF039.UINT8[R_IO_HL])
     6016#define RSCAN0TMDF039HH (RSCAN0.TMDF039.UINT8[R_IO_HH])
     6017#define RSCAN0TMDF139 (RSCAN0.TMDF139.UINT32)
     6018#define RSCAN0TMDF139L (RSCAN0.TMDF139.UINT16[R_IO_L])
     6019#define RSCAN0TMDF139LL (RSCAN0.TMDF139.UINT8[R_IO_LL])
     6020#define RSCAN0TMDF139LH (RSCAN0.TMDF139.UINT8[R_IO_LH])
     6021#define RSCAN0TMDF139H (RSCAN0.TMDF139.UINT16[R_IO_H])
     6022#define RSCAN0TMDF139HL (RSCAN0.TMDF139.UINT8[R_IO_HL])
     6023#define RSCAN0TMDF139HH (RSCAN0.TMDF139.UINT8[R_IO_HH])
     6024#define RSCAN0TMID40 (RSCAN0.TMID40.UINT32)
     6025#define RSCAN0TMID40L (RSCAN0.TMID40.UINT16[R_IO_L])
     6026#define RSCAN0TMID40LL (RSCAN0.TMID40.UINT8[R_IO_LL])
     6027#define RSCAN0TMID40LH (RSCAN0.TMID40.UINT8[R_IO_LH])
     6028#define RSCAN0TMID40H (RSCAN0.TMID40.UINT16[R_IO_H])
     6029#define RSCAN0TMID40HL (RSCAN0.TMID40.UINT8[R_IO_HL])
     6030#define RSCAN0TMID40HH (RSCAN0.TMID40.UINT8[R_IO_HH])
     6031#define RSCAN0TMPTR40 (RSCAN0.TMPTR40.UINT32)
     6032#define RSCAN0TMPTR40L (RSCAN0.TMPTR40.UINT16[R_IO_L])
     6033#define RSCAN0TMPTR40LL (RSCAN0.TMPTR40.UINT8[R_IO_LL])
     6034#define RSCAN0TMPTR40LH (RSCAN0.TMPTR40.UINT8[R_IO_LH])
     6035#define RSCAN0TMPTR40H (RSCAN0.TMPTR40.UINT16[R_IO_H])
     6036#define RSCAN0TMPTR40HL (RSCAN0.TMPTR40.UINT8[R_IO_HL])
     6037#define RSCAN0TMPTR40HH (RSCAN0.TMPTR40.UINT8[R_IO_HH])
     6038#define RSCAN0TMDF040 (RSCAN0.TMDF040.UINT32)
     6039#define RSCAN0TMDF040L (RSCAN0.TMDF040.UINT16[R_IO_L])
     6040#define RSCAN0TMDF040LL (RSCAN0.TMDF040.UINT8[R_IO_LL])
     6041#define RSCAN0TMDF040LH (RSCAN0.TMDF040.UINT8[R_IO_LH])
     6042#define RSCAN0TMDF040H (RSCAN0.TMDF040.UINT16[R_IO_H])
     6043#define RSCAN0TMDF040HL (RSCAN0.TMDF040.UINT8[R_IO_HL])
     6044#define RSCAN0TMDF040HH (RSCAN0.TMDF040.UINT8[R_IO_HH])
     6045#define RSCAN0TMDF140 (RSCAN0.TMDF140.UINT32)
     6046#define RSCAN0TMDF140L (RSCAN0.TMDF140.UINT16[R_IO_L])
     6047#define RSCAN0TMDF140LL (RSCAN0.TMDF140.UINT8[R_IO_LL])
     6048#define RSCAN0TMDF140LH (RSCAN0.TMDF140.UINT8[R_IO_LH])
     6049#define RSCAN0TMDF140H (RSCAN0.TMDF140.UINT16[R_IO_H])
     6050#define RSCAN0TMDF140HL (RSCAN0.TMDF140.UINT8[R_IO_HL])
     6051#define RSCAN0TMDF140HH (RSCAN0.TMDF140.UINT8[R_IO_HH])
     6052#define RSCAN0TMID41 (RSCAN0.TMID41.UINT32)
     6053#define RSCAN0TMID41L (RSCAN0.TMID41.UINT16[R_IO_L])
     6054#define RSCAN0TMID41LL (RSCAN0.TMID41.UINT8[R_IO_LL])
     6055#define RSCAN0TMID41LH (RSCAN0.TMID41.UINT8[R_IO_LH])
     6056#define RSCAN0TMID41H (RSCAN0.TMID41.UINT16[R_IO_H])
     6057#define RSCAN0TMID41HL (RSCAN0.TMID41.UINT8[R_IO_HL])
     6058#define RSCAN0TMID41HH (RSCAN0.TMID41.UINT8[R_IO_HH])
     6059#define RSCAN0TMPTR41 (RSCAN0.TMPTR41.UINT32)
     6060#define RSCAN0TMPTR41L (RSCAN0.TMPTR41.UINT16[R_IO_L])
     6061#define RSCAN0TMPTR41LL (RSCAN0.TMPTR41.UINT8[R_IO_LL])
     6062#define RSCAN0TMPTR41LH (RSCAN0.TMPTR41.UINT8[R_IO_LH])
     6063#define RSCAN0TMPTR41H (RSCAN0.TMPTR41.UINT16[R_IO_H])
     6064#define RSCAN0TMPTR41HL (RSCAN0.TMPTR41.UINT8[R_IO_HL])
     6065#define RSCAN0TMPTR41HH (RSCAN0.TMPTR41.UINT8[R_IO_HH])
     6066#define RSCAN0TMDF041 (RSCAN0.TMDF041.UINT32)
     6067#define RSCAN0TMDF041L (RSCAN0.TMDF041.UINT16[R_IO_L])
     6068#define RSCAN0TMDF041LL (RSCAN0.TMDF041.UINT8[R_IO_LL])
     6069#define RSCAN0TMDF041LH (RSCAN0.TMDF041.UINT8[R_IO_LH])
     6070#define RSCAN0TMDF041H (RSCAN0.TMDF041.UINT16[R_IO_H])
     6071#define RSCAN0TMDF041HL (RSCAN0.TMDF041.UINT8[R_IO_HL])
     6072#define RSCAN0TMDF041HH (RSCAN0.TMDF041.UINT8[R_IO_HH])
     6073#define RSCAN0TMDF141 (RSCAN0.TMDF141.UINT32)
     6074#define RSCAN0TMDF141L (RSCAN0.TMDF141.UINT16[R_IO_L])
     6075#define RSCAN0TMDF141LL (RSCAN0.TMDF141.UINT8[R_IO_LL])
     6076#define RSCAN0TMDF141LH (RSCAN0.TMDF141.UINT8[R_IO_LH])
     6077#define RSCAN0TMDF141H (RSCAN0.TMDF141.UINT16[R_IO_H])
     6078#define RSCAN0TMDF141HL (RSCAN0.TMDF141.UINT8[R_IO_HL])
     6079#define RSCAN0TMDF141HH (RSCAN0.TMDF141.UINT8[R_IO_HH])
     6080#define RSCAN0TMID42 (RSCAN0.TMID42.UINT32)
     6081#define RSCAN0TMID42L (RSCAN0.TMID42.UINT16[R_IO_L])
     6082#define RSCAN0TMID42LL (RSCAN0.TMID42.UINT8[R_IO_LL])
     6083#define RSCAN0TMID42LH (RSCAN0.TMID42.UINT8[R_IO_LH])
     6084#define RSCAN0TMID42H (RSCAN0.TMID42.UINT16[R_IO_H])
     6085#define RSCAN0TMID42HL (RSCAN0.TMID42.UINT8[R_IO_HL])
     6086#define RSCAN0TMID42HH (RSCAN0.TMID42.UINT8[R_IO_HH])
     6087#define RSCAN0TMPTR42 (RSCAN0.TMPTR42.UINT32)
     6088#define RSCAN0TMPTR42L (RSCAN0.TMPTR42.UINT16[R_IO_L])
     6089#define RSCAN0TMPTR42LL (RSCAN0.TMPTR42.UINT8[R_IO_LL])
     6090#define RSCAN0TMPTR42LH (RSCAN0.TMPTR42.UINT8[R_IO_LH])
     6091#define RSCAN0TMPTR42H (RSCAN0.TMPTR42.UINT16[R_IO_H])
     6092#define RSCAN0TMPTR42HL (RSCAN0.TMPTR42.UINT8[R_IO_HL])
     6093#define RSCAN0TMPTR42HH (RSCAN0.TMPTR42.UINT8[R_IO_HH])
     6094#define RSCAN0TMDF042 (RSCAN0.TMDF042.UINT32)
     6095#define RSCAN0TMDF042L (RSCAN0.TMDF042.UINT16[R_IO_L])
     6096#define RSCAN0TMDF042LL (RSCAN0.TMDF042.UINT8[R_IO_LL])
     6097#define RSCAN0TMDF042LH (RSCAN0.TMDF042.UINT8[R_IO_LH])
     6098#define RSCAN0TMDF042H (RSCAN0.TMDF042.UINT16[R_IO_H])
     6099#define RSCAN0TMDF042HL (RSCAN0.TMDF042.UINT8[R_IO_HL])
     6100#define RSCAN0TMDF042HH (RSCAN0.TMDF042.UINT8[R_IO_HH])
     6101#define RSCAN0TMDF142 (RSCAN0.TMDF142.UINT32)
     6102#define RSCAN0TMDF142L (RSCAN0.TMDF142.UINT16[R_IO_L])
     6103#define RSCAN0TMDF142LL (RSCAN0.TMDF142.UINT8[R_IO_LL])
     6104#define RSCAN0TMDF142LH (RSCAN0.TMDF142.UINT8[R_IO_LH])
     6105#define RSCAN0TMDF142H (RSCAN0.TMDF142.UINT16[R_IO_H])
     6106#define RSCAN0TMDF142HL (RSCAN0.TMDF142.UINT8[R_IO_HL])
     6107#define RSCAN0TMDF142HH (RSCAN0.TMDF142.UINT8[R_IO_HH])
     6108#define RSCAN0TMID43 (RSCAN0.TMID43.UINT32)
     6109#define RSCAN0TMID43L (RSCAN0.TMID43.UINT16[R_IO_L])
     6110#define RSCAN0TMID43LL (RSCAN0.TMID43.UINT8[R_IO_LL])
     6111#define RSCAN0TMID43LH (RSCAN0.TMID43.UINT8[R_IO_LH])
     6112#define RSCAN0TMID43H (RSCAN0.TMID43.UINT16[R_IO_H])
     6113#define RSCAN0TMID43HL (RSCAN0.TMID43.UINT8[R_IO_HL])
     6114#define RSCAN0TMID43HH (RSCAN0.TMID43.UINT8[R_IO_HH])
     6115#define RSCAN0TMPTR43 (RSCAN0.TMPTR43.UINT32)
     6116#define RSCAN0TMPTR43L (RSCAN0.TMPTR43.UINT16[R_IO_L])
     6117#define RSCAN0TMPTR43LL (RSCAN0.TMPTR43.UINT8[R_IO_LL])
     6118#define RSCAN0TMPTR43LH (RSCAN0.TMPTR43.UINT8[R_IO_LH])
     6119#define RSCAN0TMPTR43H (RSCAN0.TMPTR43.UINT16[R_IO_H])
     6120#define RSCAN0TMPTR43HL (RSCAN0.TMPTR43.UINT8[R_IO_HL])
     6121#define RSCAN0TMPTR43HH (RSCAN0.TMPTR43.UINT8[R_IO_HH])
     6122#define RSCAN0TMDF043 (RSCAN0.TMDF043.UINT32)
     6123#define RSCAN0TMDF043L (RSCAN0.TMDF043.UINT16[R_IO_L])
     6124#define RSCAN0TMDF043LL (RSCAN0.TMDF043.UINT8[R_IO_LL])
     6125#define RSCAN0TMDF043LH (RSCAN0.TMDF043.UINT8[R_IO_LH])
     6126#define RSCAN0TMDF043H (RSCAN0.TMDF043.UINT16[R_IO_H])
     6127#define RSCAN0TMDF043HL (RSCAN0.TMDF043.UINT8[R_IO_HL])
     6128#define RSCAN0TMDF043HH (RSCAN0.TMDF043.UINT8[R_IO_HH])
     6129#define RSCAN0TMDF143 (RSCAN0.TMDF143.UINT32)
     6130#define RSCAN0TMDF143L (RSCAN0.TMDF143.UINT16[R_IO_L])
     6131#define RSCAN0TMDF143LL (RSCAN0.TMDF143.UINT8[R_IO_LL])
     6132#define RSCAN0TMDF143LH (RSCAN0.TMDF143.UINT8[R_IO_LH])
     6133#define RSCAN0TMDF143H (RSCAN0.TMDF143.UINT16[R_IO_H])
     6134#define RSCAN0TMDF143HL (RSCAN0.TMDF143.UINT8[R_IO_HL])
     6135#define RSCAN0TMDF143HH (RSCAN0.TMDF143.UINT8[R_IO_HH])
     6136#define RSCAN0TMID44 (RSCAN0.TMID44.UINT32)
     6137#define RSCAN0TMID44L (RSCAN0.TMID44.UINT16[R_IO_L])
     6138#define RSCAN0TMID44LL (RSCAN0.TMID44.UINT8[R_IO_LL])
     6139#define RSCAN0TMID44LH (RSCAN0.TMID44.UINT8[R_IO_LH])
     6140#define RSCAN0TMID44H (RSCAN0.TMID44.UINT16[R_IO_H])
     6141#define RSCAN0TMID44HL (RSCAN0.TMID44.UINT8[R_IO_HL])
     6142#define RSCAN0TMID44HH (RSCAN0.TMID44.UINT8[R_IO_HH])
     6143#define RSCAN0TMPTR44 (RSCAN0.TMPTR44.UINT32)
     6144#define RSCAN0TMPTR44L (RSCAN0.TMPTR44.UINT16[R_IO_L])
     6145#define RSCAN0TMPTR44LL (RSCAN0.TMPTR44.UINT8[R_IO_LL])
     6146#define RSCAN0TMPTR44LH (RSCAN0.TMPTR44.UINT8[R_IO_LH])
     6147#define RSCAN0TMPTR44H (RSCAN0.TMPTR44.UINT16[R_IO_H])
     6148#define RSCAN0TMPTR44HL (RSCAN0.TMPTR44.UINT8[R_IO_HL])
     6149#define RSCAN0TMPTR44HH (RSCAN0.TMPTR44.UINT8[R_IO_HH])
     6150#define RSCAN0TMDF044 (RSCAN0.TMDF044.UINT32)
     6151#define RSCAN0TMDF044L (RSCAN0.TMDF044.UINT16[R_IO_L])
     6152#define RSCAN0TMDF044LL (RSCAN0.TMDF044.UINT8[R_IO_LL])
     6153#define RSCAN0TMDF044LH (RSCAN0.TMDF044.UINT8[R_IO_LH])
     6154#define RSCAN0TMDF044H (RSCAN0.TMDF044.UINT16[R_IO_H])
     6155#define RSCAN0TMDF044HL (RSCAN0.TMDF044.UINT8[R_IO_HL])
     6156#define RSCAN0TMDF044HH (RSCAN0.TMDF044.UINT8[R_IO_HH])
     6157#define RSCAN0TMDF144 (RSCAN0.TMDF144.UINT32)
     6158#define RSCAN0TMDF144L (RSCAN0.TMDF144.UINT16[R_IO_L])
     6159#define RSCAN0TMDF144LL (RSCAN0.TMDF144.UINT8[R_IO_LL])
     6160#define RSCAN0TMDF144LH (RSCAN0.TMDF144.UINT8[R_IO_LH])
     6161#define RSCAN0TMDF144H (RSCAN0.TMDF144.UINT16[R_IO_H])
     6162#define RSCAN0TMDF144HL (RSCAN0.TMDF144.UINT8[R_IO_HL])
     6163#define RSCAN0TMDF144HH (RSCAN0.TMDF144.UINT8[R_IO_HH])
     6164#define RSCAN0TMID45 (RSCAN0.TMID45.UINT32)
     6165#define RSCAN0TMID45L (RSCAN0.TMID45.UINT16[R_IO_L])
     6166#define RSCAN0TMID45LL (RSCAN0.TMID45.UINT8[R_IO_LL])
     6167#define RSCAN0TMID45LH (RSCAN0.TMID45.UINT8[R_IO_LH])
     6168#define RSCAN0TMID45H (RSCAN0.TMID45.UINT16[R_IO_H])
     6169#define RSCAN0TMID45HL (RSCAN0.TMID45.UINT8[R_IO_HL])
     6170#define RSCAN0TMID45HH (RSCAN0.TMID45.UINT8[R_IO_HH])
     6171#define RSCAN0TMPTR45 (RSCAN0.TMPTR45.UINT32)
     6172#define RSCAN0TMPTR45L (RSCAN0.TMPTR45.UINT16[R_IO_L])
     6173#define RSCAN0TMPTR45LL (RSCAN0.TMPTR45.UINT8[R_IO_LL])
     6174#define RSCAN0TMPTR45LH (RSCAN0.TMPTR45.UINT8[R_IO_LH])
     6175#define RSCAN0TMPTR45H (RSCAN0.TMPTR45.UINT16[R_IO_H])
     6176#define RSCAN0TMPTR45HL (RSCAN0.TMPTR45.UINT8[R_IO_HL])
     6177#define RSCAN0TMPTR45HH (RSCAN0.TMPTR45.UINT8[R_IO_HH])
     6178#define RSCAN0TMDF045 (RSCAN0.TMDF045.UINT32)
     6179#define RSCAN0TMDF045L (RSCAN0.TMDF045.UINT16[R_IO_L])
     6180#define RSCAN0TMDF045LL (RSCAN0.TMDF045.UINT8[R_IO_LL])
     6181#define RSCAN0TMDF045LH (RSCAN0.TMDF045.UINT8[R_IO_LH])
     6182#define RSCAN0TMDF045H (RSCAN0.TMDF045.UINT16[R_IO_H])
     6183#define RSCAN0TMDF045HL (RSCAN0.TMDF045.UINT8[R_IO_HL])
     6184#define RSCAN0TMDF045HH (RSCAN0.TMDF045.UINT8[R_IO_HH])
     6185#define RSCAN0TMDF145 (RSCAN0.TMDF145.UINT32)
     6186#define RSCAN0TMDF145L (RSCAN0.TMDF145.UINT16[R_IO_L])
     6187#define RSCAN0TMDF145LL (RSCAN0.TMDF145.UINT8[R_IO_LL])
     6188#define RSCAN0TMDF145LH (RSCAN0.TMDF145.UINT8[R_IO_LH])
     6189#define RSCAN0TMDF145H (RSCAN0.TMDF145.UINT16[R_IO_H])
     6190#define RSCAN0TMDF145HL (RSCAN0.TMDF145.UINT8[R_IO_HL])
     6191#define RSCAN0TMDF145HH (RSCAN0.TMDF145.UINT8[R_IO_HH])
     6192#define RSCAN0TMID46 (RSCAN0.TMID46.UINT32)
     6193#define RSCAN0TMID46L (RSCAN0.TMID46.UINT16[R_IO_L])
     6194#define RSCAN0TMID46LL (RSCAN0.TMID46.UINT8[R_IO_LL])
     6195#define RSCAN0TMID46LH (RSCAN0.TMID46.UINT8[R_IO_LH])
     6196#define RSCAN0TMID46H (RSCAN0.TMID46.UINT16[R_IO_H])
     6197#define RSCAN0TMID46HL (RSCAN0.TMID46.UINT8[R_IO_HL])
     6198#define RSCAN0TMID46HH (RSCAN0.TMID46.UINT8[R_IO_HH])
     6199#define RSCAN0TMPTR46 (RSCAN0.TMPTR46.UINT32)
     6200#define RSCAN0TMPTR46L (RSCAN0.TMPTR46.UINT16[R_IO_L])
     6201#define RSCAN0TMPTR46LL (RSCAN0.TMPTR46.UINT8[R_IO_LL])
     6202#define RSCAN0TMPTR46LH (RSCAN0.TMPTR46.UINT8[R_IO_LH])
     6203#define RSCAN0TMPTR46H (RSCAN0.TMPTR46.UINT16[R_IO_H])
     6204#define RSCAN0TMPTR46HL (RSCAN0.TMPTR46.UINT8[R_IO_HL])
     6205#define RSCAN0TMPTR46HH (RSCAN0.TMPTR46.UINT8[R_IO_HH])
     6206#define RSCAN0TMDF046 (RSCAN0.TMDF046.UINT32)
     6207#define RSCAN0TMDF046L (RSCAN0.TMDF046.UINT16[R_IO_L])
     6208#define RSCAN0TMDF046LL (RSCAN0.TMDF046.UINT8[R_IO_LL])
     6209#define RSCAN0TMDF046LH (RSCAN0.TMDF046.UINT8[R_IO_LH])
     6210#define RSCAN0TMDF046H (RSCAN0.TMDF046.UINT16[R_IO_H])
     6211#define RSCAN0TMDF046HL (RSCAN0.TMDF046.UINT8[R_IO_HL])
     6212#define RSCAN0TMDF046HH (RSCAN0.TMDF046.UINT8[R_IO_HH])
     6213#define RSCAN0TMDF146 (RSCAN0.TMDF146.UINT32)
     6214#define RSCAN0TMDF146L (RSCAN0.TMDF146.UINT16[R_IO_L])
     6215#define RSCAN0TMDF146LL (RSCAN0.TMDF146.UINT8[R_IO_LL])
     6216#define RSCAN0TMDF146LH (RSCAN0.TMDF146.UINT8[R_IO_LH])
     6217#define RSCAN0TMDF146H (RSCAN0.TMDF146.UINT16[R_IO_H])
     6218#define RSCAN0TMDF146HL (RSCAN0.TMDF146.UINT8[R_IO_HL])
     6219#define RSCAN0TMDF146HH (RSCAN0.TMDF146.UINT8[R_IO_HH])
     6220#define RSCAN0TMID47 (RSCAN0.TMID47.UINT32)
     6221#define RSCAN0TMID47L (RSCAN0.TMID47.UINT16[R_IO_L])
     6222#define RSCAN0TMID47LL (RSCAN0.TMID47.UINT8[R_IO_LL])
     6223#define RSCAN0TMID47LH (RSCAN0.TMID47.UINT8[R_IO_LH])
     6224#define RSCAN0TMID47H (RSCAN0.TMID47.UINT16[R_IO_H])
     6225#define RSCAN0TMID47HL (RSCAN0.TMID47.UINT8[R_IO_HL])
     6226#define RSCAN0TMID47HH (RSCAN0.TMID47.UINT8[R_IO_HH])
     6227#define RSCAN0TMPTR47 (RSCAN0.TMPTR47.UINT32)
     6228#define RSCAN0TMPTR47L (RSCAN0.TMPTR47.UINT16[R_IO_L])
     6229#define RSCAN0TMPTR47LL (RSCAN0.TMPTR47.UINT8[R_IO_LL])
     6230#define RSCAN0TMPTR47LH (RSCAN0.TMPTR47.UINT8[R_IO_LH])
     6231#define RSCAN0TMPTR47H (RSCAN0.TMPTR47.UINT16[R_IO_H])
     6232#define RSCAN0TMPTR47HL (RSCAN0.TMPTR47.UINT8[R_IO_HL])
     6233#define RSCAN0TMPTR47HH (RSCAN0.TMPTR47.UINT8[R_IO_HH])
     6234#define RSCAN0TMDF047 (RSCAN0.TMDF047.UINT32)
     6235#define RSCAN0TMDF047L (RSCAN0.TMDF047.UINT16[R_IO_L])
     6236#define RSCAN0TMDF047LL (RSCAN0.TMDF047.UINT8[R_IO_LL])
     6237#define RSCAN0TMDF047LH (RSCAN0.TMDF047.UINT8[R_IO_LH])
     6238#define RSCAN0TMDF047H (RSCAN0.TMDF047.UINT16[R_IO_H])
     6239#define RSCAN0TMDF047HL (RSCAN0.TMDF047.UINT8[R_IO_HL])
     6240#define RSCAN0TMDF047HH (RSCAN0.TMDF047.UINT8[R_IO_HH])
     6241#define RSCAN0TMDF147 (RSCAN0.TMDF147.UINT32)
     6242#define RSCAN0TMDF147L (RSCAN0.TMDF147.UINT16[R_IO_L])
     6243#define RSCAN0TMDF147LL (RSCAN0.TMDF147.UINT8[R_IO_LL])
     6244#define RSCAN0TMDF147LH (RSCAN0.TMDF147.UINT8[R_IO_LH])
     6245#define RSCAN0TMDF147H (RSCAN0.TMDF147.UINT16[R_IO_H])
     6246#define RSCAN0TMDF147HL (RSCAN0.TMDF147.UINT8[R_IO_HL])
     6247#define RSCAN0TMDF147HH (RSCAN0.TMDF147.UINT8[R_IO_HH])
     6248#define RSCAN0TMID48 (RSCAN0.TMID48.UINT32)
     6249#define RSCAN0TMID48L (RSCAN0.TMID48.UINT16[R_IO_L])
     6250#define RSCAN0TMID48LL (RSCAN0.TMID48.UINT8[R_IO_LL])
     6251#define RSCAN0TMID48LH (RSCAN0.TMID48.UINT8[R_IO_LH])
     6252#define RSCAN0TMID48H (RSCAN0.TMID48.UINT16[R_IO_H])
     6253#define RSCAN0TMID48HL (RSCAN0.TMID48.UINT8[R_IO_HL])
     6254#define RSCAN0TMID48HH (RSCAN0.TMID48.UINT8[R_IO_HH])
     6255#define RSCAN0TMPTR48 (RSCAN0.TMPTR48.UINT32)
     6256#define RSCAN0TMPTR48L (RSCAN0.TMPTR48.UINT16[R_IO_L])
     6257#define RSCAN0TMPTR48LL (RSCAN0.TMPTR48.UINT8[R_IO_LL])
     6258#define RSCAN0TMPTR48LH (RSCAN0.TMPTR48.UINT8[R_IO_LH])
     6259#define RSCAN0TMPTR48H (RSCAN0.TMPTR48.UINT16[R_IO_H])
     6260#define RSCAN0TMPTR48HL (RSCAN0.TMPTR48.UINT8[R_IO_HL])
     6261#define RSCAN0TMPTR48HH (RSCAN0.TMPTR48.UINT8[R_IO_HH])
     6262#define RSCAN0TMDF048 (RSCAN0.TMDF048.UINT32)
     6263#define RSCAN0TMDF048L (RSCAN0.TMDF048.UINT16[R_IO_L])
     6264#define RSCAN0TMDF048LL (RSCAN0.TMDF048.UINT8[R_IO_LL])
     6265#define RSCAN0TMDF048LH (RSCAN0.TMDF048.UINT8[R_IO_LH])
     6266#define RSCAN0TMDF048H (RSCAN0.TMDF048.UINT16[R_IO_H])
     6267#define RSCAN0TMDF048HL (RSCAN0.TMDF048.UINT8[R_IO_HL])
     6268#define RSCAN0TMDF048HH (RSCAN0.TMDF048.UINT8[R_IO_HH])
     6269#define RSCAN0TMDF148 (RSCAN0.TMDF148.UINT32)
     6270#define RSCAN0TMDF148L (RSCAN0.TMDF148.UINT16[R_IO_L])
     6271#define RSCAN0TMDF148LL (RSCAN0.TMDF148.UINT8[R_IO_LL])
     6272#define RSCAN0TMDF148LH (RSCAN0.TMDF148.UINT8[R_IO_LH])
     6273#define RSCAN0TMDF148H (RSCAN0.TMDF148.UINT16[R_IO_H])
     6274#define RSCAN0TMDF148HL (RSCAN0.TMDF148.UINT8[R_IO_HL])
     6275#define RSCAN0TMDF148HH (RSCAN0.TMDF148.UINT8[R_IO_HH])
     6276#define RSCAN0TMID49 (RSCAN0.TMID49.UINT32)
     6277#define RSCAN0TMID49L (RSCAN0.TMID49.UINT16[R_IO_L])
     6278#define RSCAN0TMID49LL (RSCAN0.TMID49.UINT8[R_IO_LL])
     6279#define RSCAN0TMID49LH (RSCAN0.TMID49.UINT8[R_IO_LH])
     6280#define RSCAN0TMID49H (RSCAN0.TMID49.UINT16[R_IO_H])
     6281#define RSCAN0TMID49HL (RSCAN0.TMID49.UINT8[R_IO_HL])
     6282#define RSCAN0TMID49HH (RSCAN0.TMID49.UINT8[R_IO_HH])
     6283#define RSCAN0TMPTR49 (RSCAN0.TMPTR49.UINT32)
     6284#define RSCAN0TMPTR49L (RSCAN0.TMPTR49.UINT16[R_IO_L])
     6285#define RSCAN0TMPTR49LL (RSCAN0.TMPTR49.UINT8[R_IO_LL])
     6286#define RSCAN0TMPTR49LH (RSCAN0.TMPTR49.UINT8[R_IO_LH])
     6287#define RSCAN0TMPTR49H (RSCAN0.TMPTR49.UINT16[R_IO_H])
     6288#define RSCAN0TMPTR49HL (RSCAN0.TMPTR49.UINT8[R_IO_HL])
     6289#define RSCAN0TMPTR49HH (RSCAN0.TMPTR49.UINT8[R_IO_HH])
     6290#define RSCAN0TMDF049 (RSCAN0.TMDF049.UINT32)
     6291#define RSCAN0TMDF049L (RSCAN0.TMDF049.UINT16[R_IO_L])
     6292#define RSCAN0TMDF049LL (RSCAN0.TMDF049.UINT8[R_IO_LL])
     6293#define RSCAN0TMDF049LH (RSCAN0.TMDF049.UINT8[R_IO_LH])
     6294#define RSCAN0TMDF049H (RSCAN0.TMDF049.UINT16[R_IO_H])
     6295#define RSCAN0TMDF049HL (RSCAN0.TMDF049.UINT8[R_IO_HL])
     6296#define RSCAN0TMDF049HH (RSCAN0.TMDF049.UINT8[R_IO_HH])
     6297#define RSCAN0TMDF149 (RSCAN0.TMDF149.UINT32)
     6298#define RSCAN0TMDF149L (RSCAN0.TMDF149.UINT16[R_IO_L])
     6299#define RSCAN0TMDF149LL (RSCAN0.TMDF149.UINT8[R_IO_LL])
     6300#define RSCAN0TMDF149LH (RSCAN0.TMDF149.UINT8[R_IO_LH])
     6301#define RSCAN0TMDF149H (RSCAN0.TMDF149.UINT16[R_IO_H])
     6302#define RSCAN0TMDF149HL (RSCAN0.TMDF149.UINT8[R_IO_HL])
     6303#define RSCAN0TMDF149HH (RSCAN0.TMDF149.UINT8[R_IO_HH])
     6304#define RSCAN0TMID50 (RSCAN0.TMID50.UINT32)
     6305#define RSCAN0TMID50L (RSCAN0.TMID50.UINT16[R_IO_L])
     6306#define RSCAN0TMID50LL (RSCAN0.TMID50.UINT8[R_IO_LL])
     6307#define RSCAN0TMID50LH (RSCAN0.TMID50.UINT8[R_IO_LH])
     6308#define RSCAN0TMID50H (RSCAN0.TMID50.UINT16[R_IO_H])
     6309#define RSCAN0TMID50HL (RSCAN0.TMID50.UINT8[R_IO_HL])
     6310#define RSCAN0TMID50HH (RSCAN0.TMID50.UINT8[R_IO_HH])
     6311#define RSCAN0TMPTR50 (RSCAN0.TMPTR50.UINT32)
     6312#define RSCAN0TMPTR50L (RSCAN0.TMPTR50.UINT16[R_IO_L])
     6313#define RSCAN0TMPTR50LL (RSCAN0.TMPTR50.UINT8[R_IO_LL])
     6314#define RSCAN0TMPTR50LH (RSCAN0.TMPTR50.UINT8[R_IO_LH])
     6315#define RSCAN0TMPTR50H (RSCAN0.TMPTR50.UINT16[R_IO_H])
     6316#define RSCAN0TMPTR50HL (RSCAN0.TMPTR50.UINT8[R_IO_HL])
     6317#define RSCAN0TMPTR50HH (RSCAN0.TMPTR50.UINT8[R_IO_HH])
     6318#define RSCAN0TMDF050 (RSCAN0.TMDF050.UINT32)
     6319#define RSCAN0TMDF050L (RSCAN0.TMDF050.UINT16[R_IO_L])
     6320#define RSCAN0TMDF050LL (RSCAN0.TMDF050.UINT8[R_IO_LL])
     6321#define RSCAN0TMDF050LH (RSCAN0.TMDF050.UINT8[R_IO_LH])
     6322#define RSCAN0TMDF050H (RSCAN0.TMDF050.UINT16[R_IO_H])
     6323#define RSCAN0TMDF050HL (RSCAN0.TMDF050.UINT8[R_IO_HL])
     6324#define RSCAN0TMDF050HH (RSCAN0.TMDF050.UINT8[R_IO_HH])
     6325#define RSCAN0TMDF150 (RSCAN0.TMDF150.UINT32)
     6326#define RSCAN0TMDF150L (RSCAN0.TMDF150.UINT16[R_IO_L])
     6327#define RSCAN0TMDF150LL (RSCAN0.TMDF150.UINT8[R_IO_LL])
     6328#define RSCAN0TMDF150LH (RSCAN0.TMDF150.UINT8[R_IO_LH])
     6329#define RSCAN0TMDF150H (RSCAN0.TMDF150.UINT16[R_IO_H])
     6330#define RSCAN0TMDF150HL (RSCAN0.TMDF150.UINT8[R_IO_HL])
     6331#define RSCAN0TMDF150HH (RSCAN0.TMDF150.UINT8[R_IO_HH])
     6332#define RSCAN0TMID51 (RSCAN0.TMID51.UINT32)
     6333#define RSCAN0TMID51L (RSCAN0.TMID51.UINT16[R_IO_L])
     6334#define RSCAN0TMID51LL (RSCAN0.TMID51.UINT8[R_IO_LL])
     6335#define RSCAN0TMID51LH (RSCAN0.TMID51.UINT8[R_IO_LH])
     6336#define RSCAN0TMID51H (RSCAN0.TMID51.UINT16[R_IO_H])
     6337#define RSCAN0TMID51HL (RSCAN0.TMID51.UINT8[R_IO_HL])
     6338#define RSCAN0TMID51HH (RSCAN0.TMID51.UINT8[R_IO_HH])
     6339#define RSCAN0TMPTR51 (RSCAN0.TMPTR51.UINT32)
     6340#define RSCAN0TMPTR51L (RSCAN0.TMPTR51.UINT16[R_IO_L])
     6341#define RSCAN0TMPTR51LL (RSCAN0.TMPTR51.UINT8[R_IO_LL])
     6342#define RSCAN0TMPTR51LH (RSCAN0.TMPTR51.UINT8[R_IO_LH])
     6343#define RSCAN0TMPTR51H (RSCAN0.TMPTR51.UINT16[R_IO_H])
     6344#define RSCAN0TMPTR51HL (RSCAN0.TMPTR51.UINT8[R_IO_HL])
     6345#define RSCAN0TMPTR51HH (RSCAN0.TMPTR51.UINT8[R_IO_HH])
     6346#define RSCAN0TMDF051 (RSCAN0.TMDF051.UINT32)
     6347#define RSCAN0TMDF051L (RSCAN0.TMDF051.UINT16[R_IO_L])
     6348#define RSCAN0TMDF051LL (RSCAN0.TMDF051.UINT8[R_IO_LL])
     6349#define RSCAN0TMDF051LH (RSCAN0.TMDF051.UINT8[R_IO_LH])
     6350#define RSCAN0TMDF051H (RSCAN0.TMDF051.UINT16[R_IO_H])
     6351#define RSCAN0TMDF051HL (RSCAN0.TMDF051.UINT8[R_IO_HL])
     6352#define RSCAN0TMDF051HH (RSCAN0.TMDF051.UINT8[R_IO_HH])
     6353#define RSCAN0TMDF151 (RSCAN0.TMDF151.UINT32)
     6354#define RSCAN0TMDF151L (RSCAN0.TMDF151.UINT16[R_IO_L])
     6355#define RSCAN0TMDF151LL (RSCAN0.TMDF151.UINT8[R_IO_LL])
     6356#define RSCAN0TMDF151LH (RSCAN0.TMDF151.UINT8[R_IO_LH])
     6357#define RSCAN0TMDF151H (RSCAN0.TMDF151.UINT16[R_IO_H])
     6358#define RSCAN0TMDF151HL (RSCAN0.TMDF151.UINT8[R_IO_HL])
     6359#define RSCAN0TMDF151HH (RSCAN0.TMDF151.UINT8[R_IO_HH])
     6360#define RSCAN0TMID52 (RSCAN0.TMID52.UINT32)
     6361#define RSCAN0TMID52L (RSCAN0.TMID52.UINT16[R_IO_L])
     6362#define RSCAN0TMID52LL (RSCAN0.TMID52.UINT8[R_IO_LL])
     6363#define RSCAN0TMID52LH (RSCAN0.TMID52.UINT8[R_IO_LH])
     6364#define RSCAN0TMID52H (RSCAN0.TMID52.UINT16[R_IO_H])
     6365#define RSCAN0TMID52HL (RSCAN0.TMID52.UINT8[R_IO_HL])
     6366#define RSCAN0TMID52HH (RSCAN0.TMID52.UINT8[R_IO_HH])
     6367#define RSCAN0TMPTR52 (RSCAN0.TMPTR52.UINT32)
     6368#define RSCAN0TMPTR52L (RSCAN0.TMPTR52.UINT16[R_IO_L])
     6369#define RSCAN0TMPTR52LL (RSCAN0.TMPTR52.UINT8[R_IO_LL])
     6370#define RSCAN0TMPTR52LH (RSCAN0.TMPTR52.UINT8[R_IO_LH])
     6371#define RSCAN0TMPTR52H (RSCAN0.TMPTR52.UINT16[R_IO_H])
     6372#define RSCAN0TMPTR52HL (RSCAN0.TMPTR52.UINT8[R_IO_HL])
     6373#define RSCAN0TMPTR52HH (RSCAN0.TMPTR52.UINT8[R_IO_HH])
     6374#define RSCAN0TMDF052 (RSCAN0.TMDF052.UINT32)
     6375#define RSCAN0TMDF052L (RSCAN0.TMDF052.UINT16[R_IO_L])
     6376#define RSCAN0TMDF052LL (RSCAN0.TMDF052.UINT8[R_IO_LL])
     6377#define RSCAN0TMDF052LH (RSCAN0.TMDF052.UINT8[R_IO_LH])
     6378#define RSCAN0TMDF052H (RSCAN0.TMDF052.UINT16[R_IO_H])
     6379#define RSCAN0TMDF052HL (RSCAN0.TMDF052.UINT8[R_IO_HL])
     6380#define RSCAN0TMDF052HH (RSCAN0.TMDF052.UINT8[R_IO_HH])
     6381#define RSCAN0TMDF152 (RSCAN0.TMDF152.UINT32)
     6382#define RSCAN0TMDF152L (RSCAN0.TMDF152.UINT16[R_IO_L])
     6383#define RSCAN0TMDF152LL (RSCAN0.TMDF152.UINT8[R_IO_LL])
     6384#define RSCAN0TMDF152LH (RSCAN0.TMDF152.UINT8[R_IO_LH])
     6385#define RSCAN0TMDF152H (RSCAN0.TMDF152.UINT16[R_IO_H])
     6386#define RSCAN0TMDF152HL (RSCAN0.TMDF152.UINT8[R_IO_HL])
     6387#define RSCAN0TMDF152HH (RSCAN0.TMDF152.UINT8[R_IO_HH])
     6388#define RSCAN0TMID53 (RSCAN0.TMID53.UINT32)
     6389#define RSCAN0TMID53L (RSCAN0.TMID53.UINT16[R_IO_L])
     6390#define RSCAN0TMID53LL (RSCAN0.TMID53.UINT8[R_IO_LL])
     6391#define RSCAN0TMID53LH (RSCAN0.TMID53.UINT8[R_IO_LH])
     6392#define RSCAN0TMID53H (RSCAN0.TMID53.UINT16[R_IO_H])
     6393#define RSCAN0TMID53HL (RSCAN0.TMID53.UINT8[R_IO_HL])
     6394#define RSCAN0TMID53HH (RSCAN0.TMID53.UINT8[R_IO_HH])
     6395#define RSCAN0TMPTR53 (RSCAN0.TMPTR53.UINT32)
     6396#define RSCAN0TMPTR53L (RSCAN0.TMPTR53.UINT16[R_IO_L])
     6397#define RSCAN0TMPTR53LL (RSCAN0.TMPTR53.UINT8[R_IO_LL])
     6398#define RSCAN0TMPTR53LH (RSCAN0.TMPTR53.UINT8[R_IO_LH])
     6399#define RSCAN0TMPTR53H (RSCAN0.TMPTR53.UINT16[R_IO_H])
     6400#define RSCAN0TMPTR53HL (RSCAN0.TMPTR53.UINT8[R_IO_HL])
     6401#define RSCAN0TMPTR53HH (RSCAN0.TMPTR53.UINT8[R_IO_HH])
     6402#define RSCAN0TMDF053 (RSCAN0.TMDF053.UINT32)
     6403#define RSCAN0TMDF053L (RSCAN0.TMDF053.UINT16[R_IO_L])
     6404#define RSCAN0TMDF053LL (RSCAN0.TMDF053.UINT8[R_IO_LL])
     6405#define RSCAN0TMDF053LH (RSCAN0.TMDF053.UINT8[R_IO_LH])
     6406#define RSCAN0TMDF053H (RSCAN0.TMDF053.UINT16[R_IO_H])
     6407#define RSCAN0TMDF053HL (RSCAN0.TMDF053.UINT8[R_IO_HL])
     6408#define RSCAN0TMDF053HH (RSCAN0.TMDF053.UINT8[R_IO_HH])
     6409#define RSCAN0TMDF153 (RSCAN0.TMDF153.UINT32)
     6410#define RSCAN0TMDF153L (RSCAN0.TMDF153.UINT16[R_IO_L])
     6411#define RSCAN0TMDF153LL (RSCAN0.TMDF153.UINT8[R_IO_LL])
     6412#define RSCAN0TMDF153LH (RSCAN0.TMDF153.UINT8[R_IO_LH])
     6413#define RSCAN0TMDF153H (RSCAN0.TMDF153.UINT16[R_IO_H])
     6414#define RSCAN0TMDF153HL (RSCAN0.TMDF153.UINT8[R_IO_HL])
     6415#define RSCAN0TMDF153HH (RSCAN0.TMDF153.UINT8[R_IO_HH])
     6416#define RSCAN0TMID54 (RSCAN0.TMID54.UINT32)
     6417#define RSCAN0TMID54L (RSCAN0.TMID54.UINT16[R_IO_L])
     6418#define RSCAN0TMID54LL (RSCAN0.TMID54.UINT8[R_IO_LL])
     6419#define RSCAN0TMID54LH (RSCAN0.TMID54.UINT8[R_IO_LH])
     6420#define RSCAN0TMID54H (RSCAN0.TMID54.UINT16[R_IO_H])
     6421#define RSCAN0TMID54HL (RSCAN0.TMID54.UINT8[R_IO_HL])
     6422#define RSCAN0TMID54HH (RSCAN0.TMID54.UINT8[R_IO_HH])
     6423#define RSCAN0TMPTR54 (RSCAN0.TMPTR54.UINT32)
     6424#define RSCAN0TMPTR54L (RSCAN0.TMPTR54.UINT16[R_IO_L])
     6425#define RSCAN0TMPTR54LL (RSCAN0.TMPTR54.UINT8[R_IO_LL])
     6426#define RSCAN0TMPTR54LH (RSCAN0.TMPTR54.UINT8[R_IO_LH])
     6427#define RSCAN0TMPTR54H (RSCAN0.TMPTR54.UINT16[R_IO_H])
     6428#define RSCAN0TMPTR54HL (RSCAN0.TMPTR54.UINT8[R_IO_HL])
     6429#define RSCAN0TMPTR54HH (RSCAN0.TMPTR54.UINT8[R_IO_HH])
     6430#define RSCAN0TMDF054 (RSCAN0.TMDF054.UINT32)
     6431#define RSCAN0TMDF054L (RSCAN0.TMDF054.UINT16[R_IO_L])
     6432#define RSCAN0TMDF054LL (RSCAN0.TMDF054.UINT8[R_IO_LL])
     6433#define RSCAN0TMDF054LH (RSCAN0.TMDF054.UINT8[R_IO_LH])
     6434#define RSCAN0TMDF054H (RSCAN0.TMDF054.UINT16[R_IO_H])
     6435#define RSCAN0TMDF054HL (RSCAN0.TMDF054.UINT8[R_IO_HL])
     6436#define RSCAN0TMDF054HH (RSCAN0.TMDF054.UINT8[R_IO_HH])
     6437#define RSCAN0TMDF154 (RSCAN0.TMDF154.UINT32)
     6438#define RSCAN0TMDF154L (RSCAN0.TMDF154.UINT16[R_IO_L])
     6439#define RSCAN0TMDF154LL (RSCAN0.TMDF154.UINT8[R_IO_LL])
     6440#define RSCAN0TMDF154LH (RSCAN0.TMDF154.UINT8[R_IO_LH])
     6441#define RSCAN0TMDF154H (RSCAN0.TMDF154.UINT16[R_IO_H])
     6442#define RSCAN0TMDF154HL (RSCAN0.TMDF154.UINT8[R_IO_HL])
     6443#define RSCAN0TMDF154HH (RSCAN0.TMDF154.UINT8[R_IO_HH])
     6444#define RSCAN0TMID55 (RSCAN0.TMID55.UINT32)
     6445#define RSCAN0TMID55L (RSCAN0.TMID55.UINT16[R_IO_L])
     6446#define RSCAN0TMID55LL (RSCAN0.TMID55.UINT8[R_IO_LL])
     6447#define RSCAN0TMID55LH (RSCAN0.TMID55.UINT8[R_IO_LH])
     6448#define RSCAN0TMID55H (RSCAN0.TMID55.UINT16[R_IO_H])
     6449#define RSCAN0TMID55HL (RSCAN0.TMID55.UINT8[R_IO_HL])
     6450#define RSCAN0TMID55HH (RSCAN0.TMID55.UINT8[R_IO_HH])
     6451#define RSCAN0TMPTR55 (RSCAN0.TMPTR55.UINT32)
     6452#define RSCAN0TMPTR55L (RSCAN0.TMPTR55.UINT16[R_IO_L])
     6453#define RSCAN0TMPTR55LL (RSCAN0.TMPTR55.UINT8[R_IO_LL])
     6454#define RSCAN0TMPTR55LH (RSCAN0.TMPTR55.UINT8[R_IO_LH])
     6455#define RSCAN0TMPTR55H (RSCAN0.TMPTR55.UINT16[R_IO_H])
     6456#define RSCAN0TMPTR55HL (RSCAN0.TMPTR55.UINT8[R_IO_HL])
     6457#define RSCAN0TMPTR55HH (RSCAN0.TMPTR55.UINT8[R_IO_HH])
     6458#define RSCAN0TMDF055 (RSCAN0.TMDF055.UINT32)
     6459#define RSCAN0TMDF055L (RSCAN0.TMDF055.UINT16[R_IO_L])
     6460#define RSCAN0TMDF055LL (RSCAN0.TMDF055.UINT8[R_IO_LL])
     6461#define RSCAN0TMDF055LH (RSCAN0.TMDF055.UINT8[R_IO_LH])
     6462#define RSCAN0TMDF055H (RSCAN0.TMDF055.UINT16[R_IO_H])
     6463#define RSCAN0TMDF055HL (RSCAN0.TMDF055.UINT8[R_IO_HL])
     6464#define RSCAN0TMDF055HH (RSCAN0.TMDF055.UINT8[R_IO_HH])
     6465#define RSCAN0TMDF155 (RSCAN0.TMDF155.UINT32)
     6466#define RSCAN0TMDF155L (RSCAN0.TMDF155.UINT16[R_IO_L])
     6467#define RSCAN0TMDF155LL (RSCAN0.TMDF155.UINT8[R_IO_LL])
     6468#define RSCAN0TMDF155LH (RSCAN0.TMDF155.UINT8[R_IO_LH])
     6469#define RSCAN0TMDF155H (RSCAN0.TMDF155.UINT16[R_IO_H])
     6470#define RSCAN0TMDF155HL (RSCAN0.TMDF155.UINT8[R_IO_HL])
     6471#define RSCAN0TMDF155HH (RSCAN0.TMDF155.UINT8[R_IO_HH])
     6472#define RSCAN0TMID56 (RSCAN0.TMID56.UINT32)
     6473#define RSCAN0TMID56L (RSCAN0.TMID56.UINT16[R_IO_L])
     6474#define RSCAN0TMID56LL (RSCAN0.TMID56.UINT8[R_IO_LL])
     6475#define RSCAN0TMID56LH (RSCAN0.TMID56.UINT8[R_IO_LH])
     6476#define RSCAN0TMID56H (RSCAN0.TMID56.UINT16[R_IO_H])
     6477#define RSCAN0TMID56HL (RSCAN0.TMID56.UINT8[R_IO_HL])
     6478#define RSCAN0TMID56HH (RSCAN0.TMID56.UINT8[R_IO_HH])
     6479#define RSCAN0TMPTR56 (RSCAN0.TMPTR56.UINT32)
     6480#define RSCAN0TMPTR56L (RSCAN0.TMPTR56.UINT16[R_IO_L])
     6481#define RSCAN0TMPTR56LL (RSCAN0.TMPTR56.UINT8[R_IO_LL])
     6482#define RSCAN0TMPTR56LH (RSCAN0.TMPTR56.UINT8[R_IO_LH])
     6483#define RSCAN0TMPTR56H (RSCAN0.TMPTR56.UINT16[R_IO_H])
     6484#define RSCAN0TMPTR56HL (RSCAN0.TMPTR56.UINT8[R_IO_HL])
     6485#define RSCAN0TMPTR56HH (RSCAN0.TMPTR56.UINT8[R_IO_HH])
     6486#define RSCAN0TMDF056 (RSCAN0.TMDF056.UINT32)
     6487#define RSCAN0TMDF056L (RSCAN0.TMDF056.UINT16[R_IO_L])
     6488#define RSCAN0TMDF056LL (RSCAN0.TMDF056.UINT8[R_IO_LL])
     6489#define RSCAN0TMDF056LH (RSCAN0.TMDF056.UINT8[R_IO_LH])
     6490#define RSCAN0TMDF056H (RSCAN0.TMDF056.UINT16[R_IO_H])
     6491#define RSCAN0TMDF056HL (RSCAN0.TMDF056.UINT8[R_IO_HL])
     6492#define RSCAN0TMDF056HH (RSCAN0.TMDF056.UINT8[R_IO_HH])
     6493#define RSCAN0TMDF156 (RSCAN0.TMDF156.UINT32)
     6494#define RSCAN0TMDF156L (RSCAN0.TMDF156.UINT16[R_IO_L])
     6495#define RSCAN0TMDF156LL (RSCAN0.TMDF156.UINT8[R_IO_LL])
     6496#define RSCAN0TMDF156LH (RSCAN0.TMDF156.UINT8[R_IO_LH])
     6497#define RSCAN0TMDF156H (RSCAN0.TMDF156.UINT16[R_IO_H])
     6498#define RSCAN0TMDF156HL (RSCAN0.TMDF156.UINT8[R_IO_HL])
     6499#define RSCAN0TMDF156HH (RSCAN0.TMDF156.UINT8[R_IO_HH])
     6500#define RSCAN0TMID57 (RSCAN0.TMID57.UINT32)
     6501#define RSCAN0TMID57L (RSCAN0.TMID57.UINT16[R_IO_L])
     6502#define RSCAN0TMID57LL (RSCAN0.TMID57.UINT8[R_IO_LL])
     6503#define RSCAN0TMID57LH (RSCAN0.TMID57.UINT8[R_IO_LH])
     6504#define RSCAN0TMID57H (RSCAN0.TMID57.UINT16[R_IO_H])
     6505#define RSCAN0TMID57HL (RSCAN0.TMID57.UINT8[R_IO_HL])
     6506#define RSCAN0TMID57HH (RSCAN0.TMID57.UINT8[R_IO_HH])
     6507#define RSCAN0TMPTR57 (RSCAN0.TMPTR57.UINT32)
     6508#define RSCAN0TMPTR57L (RSCAN0.TMPTR57.UINT16[R_IO_L])
     6509#define RSCAN0TMPTR57LL (RSCAN0.TMPTR57.UINT8[R_IO_LL])
     6510#define RSCAN0TMPTR57LH (RSCAN0.TMPTR57.UINT8[R_IO_LH])
     6511#define RSCAN0TMPTR57H (RSCAN0.TMPTR57.UINT16[R_IO_H])
     6512#define RSCAN0TMPTR57HL (RSCAN0.TMPTR57.UINT8[R_IO_HL])
     6513#define RSCAN0TMPTR57HH (RSCAN0.TMPTR57.UINT8[R_IO_HH])
     6514#define RSCAN0TMDF057 (RSCAN0.TMDF057.UINT32)
     6515#define RSCAN0TMDF057L (RSCAN0.TMDF057.UINT16[R_IO_L])
     6516#define RSCAN0TMDF057LL (RSCAN0.TMDF057.UINT8[R_IO_LL])
     6517#define RSCAN0TMDF057LH (RSCAN0.TMDF057.UINT8[R_IO_LH])
     6518#define RSCAN0TMDF057H (RSCAN0.TMDF057.UINT16[R_IO_H])
     6519#define RSCAN0TMDF057HL (RSCAN0.TMDF057.UINT8[R_IO_HL])
     6520#define RSCAN0TMDF057HH (RSCAN0.TMDF057.UINT8[R_IO_HH])
     6521#define RSCAN0TMDF157 (RSCAN0.TMDF157.UINT32)
     6522#define RSCAN0TMDF157L (RSCAN0.TMDF157.UINT16[R_IO_L])
     6523#define RSCAN0TMDF157LL (RSCAN0.TMDF157.UINT8[R_IO_LL])
     6524#define RSCAN0TMDF157LH (RSCAN0.TMDF157.UINT8[R_IO_LH])
     6525#define RSCAN0TMDF157H (RSCAN0.TMDF157.UINT16[R_IO_H])
     6526#define RSCAN0TMDF157HL (RSCAN0.TMDF157.UINT8[R_IO_HL])
     6527#define RSCAN0TMDF157HH (RSCAN0.TMDF157.UINT8[R_IO_HH])
     6528#define RSCAN0TMID58 (RSCAN0.TMID58.UINT32)
     6529#define RSCAN0TMID58L (RSCAN0.TMID58.UINT16[R_IO_L])
     6530#define RSCAN0TMID58LL (RSCAN0.TMID58.UINT8[R_IO_LL])
     6531#define RSCAN0TMID58LH (RSCAN0.TMID58.UINT8[R_IO_LH])
     6532#define RSCAN0TMID58H (RSCAN0.TMID58.UINT16[R_IO_H])
     6533#define RSCAN0TMID58HL (RSCAN0.TMID58.UINT8[R_IO_HL])
     6534#define RSCAN0TMID58HH (RSCAN0.TMID58.UINT8[R_IO_HH])
     6535#define RSCAN0TMPTR58 (RSCAN0.TMPTR58.UINT32)
     6536#define RSCAN0TMPTR58L (RSCAN0.TMPTR58.UINT16[R_IO_L])
     6537#define RSCAN0TMPTR58LL (RSCAN0.TMPTR58.UINT8[R_IO_LL])
     6538#define RSCAN0TMPTR58LH (RSCAN0.TMPTR58.UINT8[R_IO_LH])
     6539#define RSCAN0TMPTR58H (RSCAN0.TMPTR58.UINT16[R_IO_H])
     6540#define RSCAN0TMPTR58HL (RSCAN0.TMPTR58.UINT8[R_IO_HL])
     6541#define RSCAN0TMPTR58HH (RSCAN0.TMPTR58.UINT8[R_IO_HH])
     6542#define RSCAN0TMDF058 (RSCAN0.TMDF058.UINT32)
     6543#define RSCAN0TMDF058L (RSCAN0.TMDF058.UINT16[R_IO_L])
     6544#define RSCAN0TMDF058LL (RSCAN0.TMDF058.UINT8[R_IO_LL])
     6545#define RSCAN0TMDF058LH (RSCAN0.TMDF058.UINT8[R_IO_LH])
     6546#define RSCAN0TMDF058H (RSCAN0.TMDF058.UINT16[R_IO_H])
     6547#define RSCAN0TMDF058HL (RSCAN0.TMDF058.UINT8[R_IO_HL])
     6548#define RSCAN0TMDF058HH (RSCAN0.TMDF058.UINT8[R_IO_HH])
     6549#define RSCAN0TMDF158 (RSCAN0.TMDF158.UINT32)
     6550#define RSCAN0TMDF158L (RSCAN0.TMDF158.UINT16[R_IO_L])
     6551#define RSCAN0TMDF158LL (RSCAN0.TMDF158.UINT8[R_IO_LL])
     6552#define RSCAN0TMDF158LH (RSCAN0.TMDF158.UINT8[R_IO_LH])
     6553#define RSCAN0TMDF158H (RSCAN0.TMDF158.UINT16[R_IO_H])
     6554#define RSCAN0TMDF158HL (RSCAN0.TMDF158.UINT8[R_IO_HL])
     6555#define RSCAN0TMDF158HH (RSCAN0.TMDF158.UINT8[R_IO_HH])
     6556#define RSCAN0TMID59 (RSCAN0.TMID59.UINT32)
     6557#define RSCAN0TMID59L (RSCAN0.TMID59.UINT16[R_IO_L])
     6558#define RSCAN0TMID59LL (RSCAN0.TMID59.UINT8[R_IO_LL])
     6559#define RSCAN0TMID59LH (RSCAN0.TMID59.UINT8[R_IO_LH])
     6560#define RSCAN0TMID59H (RSCAN0.TMID59.UINT16[R_IO_H])
     6561#define RSCAN0TMID59HL (RSCAN0.TMID59.UINT8[R_IO_HL])
     6562#define RSCAN0TMID59HH (RSCAN0.TMID59.UINT8[R_IO_HH])
     6563#define RSCAN0TMPTR59 (RSCAN0.TMPTR59.UINT32)
     6564#define RSCAN0TMPTR59L (RSCAN0.TMPTR59.UINT16[R_IO_L])
     6565#define RSCAN0TMPTR59LL (RSCAN0.TMPTR59.UINT8[R_IO_LL])
     6566#define RSCAN0TMPTR59LH (RSCAN0.TMPTR59.UINT8[R_IO_LH])
     6567#define RSCAN0TMPTR59H (RSCAN0.TMPTR59.UINT16[R_IO_H])
     6568#define RSCAN0TMPTR59HL (RSCAN0.TMPTR59.UINT8[R_IO_HL])
     6569#define RSCAN0TMPTR59HH (RSCAN0.TMPTR59.UINT8[R_IO_HH])
     6570#define RSCAN0TMDF059 (RSCAN0.TMDF059.UINT32)
     6571#define RSCAN0TMDF059L (RSCAN0.TMDF059.UINT16[R_IO_L])
     6572#define RSCAN0TMDF059LL (RSCAN0.TMDF059.UINT8[R_IO_LL])
     6573#define RSCAN0TMDF059LH (RSCAN0.TMDF059.UINT8[R_IO_LH])
     6574#define RSCAN0TMDF059H (RSCAN0.TMDF059.UINT16[R_IO_H])
     6575#define RSCAN0TMDF059HL (RSCAN0.TMDF059.UINT8[R_IO_HL])
     6576#define RSCAN0TMDF059HH (RSCAN0.TMDF059.UINT8[R_IO_HH])
     6577#define RSCAN0TMDF159 (RSCAN0.TMDF159.UINT32)
     6578#define RSCAN0TMDF159L (RSCAN0.TMDF159.UINT16[R_IO_L])
     6579#define RSCAN0TMDF159LL (RSCAN0.TMDF159.UINT8[R_IO_LL])
     6580#define RSCAN0TMDF159LH (RSCAN0.TMDF159.UINT8[R_IO_LH])
     6581#define RSCAN0TMDF159H (RSCAN0.TMDF159.UINT16[R_IO_H])
     6582#define RSCAN0TMDF159HL (RSCAN0.TMDF159.UINT8[R_IO_HL])
     6583#define RSCAN0TMDF159HH (RSCAN0.TMDF159.UINT8[R_IO_HH])
     6584#define RSCAN0TMID60 (RSCAN0.TMID60.UINT32)
     6585#define RSCAN0TMID60L (RSCAN0.TMID60.UINT16[R_IO_L])
     6586#define RSCAN0TMID60LL (RSCAN0.TMID60.UINT8[R_IO_LL])
     6587#define RSCAN0TMID60LH (RSCAN0.TMID60.UINT8[R_IO_LH])
     6588#define RSCAN0TMID60H (RSCAN0.TMID60.UINT16[R_IO_H])
     6589#define RSCAN0TMID60HL (RSCAN0.TMID60.UINT8[R_IO_HL])
     6590#define RSCAN0TMID60HH (RSCAN0.TMID60.UINT8[R_IO_HH])
     6591#define RSCAN0TMPTR60 (RSCAN0.TMPTR60.UINT32)
     6592#define RSCAN0TMPTR60L (RSCAN0.TMPTR60.UINT16[R_IO_L])
     6593#define RSCAN0TMPTR60LL (RSCAN0.TMPTR60.UINT8[R_IO_LL])
     6594#define RSCAN0TMPTR60LH (RSCAN0.TMPTR60.UINT8[R_IO_LH])
     6595#define RSCAN0TMPTR60H (RSCAN0.TMPTR60.UINT16[R_IO_H])
     6596#define RSCAN0TMPTR60HL (RSCAN0.TMPTR60.UINT8[R_IO_HL])
     6597#define RSCAN0TMPTR60HH (RSCAN0.TMPTR60.UINT8[R_IO_HH])
     6598#define RSCAN0TMDF060 (RSCAN0.TMDF060.UINT32)
     6599#define RSCAN0TMDF060L (RSCAN0.TMDF060.UINT16[R_IO_L])
     6600#define RSCAN0TMDF060LL (RSCAN0.TMDF060.UINT8[R_IO_LL])
     6601#define RSCAN0TMDF060LH (RSCAN0.TMDF060.UINT8[R_IO_LH])
     6602#define RSCAN0TMDF060H (RSCAN0.TMDF060.UINT16[R_IO_H])
     6603#define RSCAN0TMDF060HL (RSCAN0.TMDF060.UINT8[R_IO_HL])
     6604#define RSCAN0TMDF060HH (RSCAN0.TMDF060.UINT8[R_IO_HH])
     6605#define RSCAN0TMDF160 (RSCAN0.TMDF160.UINT32)
     6606#define RSCAN0TMDF160L (RSCAN0.TMDF160.UINT16[R_IO_L])
     6607#define RSCAN0TMDF160LL (RSCAN0.TMDF160.UINT8[R_IO_LL])
     6608#define RSCAN0TMDF160LH (RSCAN0.TMDF160.UINT8[R_IO_LH])
     6609#define RSCAN0TMDF160H (RSCAN0.TMDF160.UINT16[R_IO_H])
     6610#define RSCAN0TMDF160HL (RSCAN0.TMDF160.UINT8[R_IO_HL])
     6611#define RSCAN0TMDF160HH (RSCAN0.TMDF160.UINT8[R_IO_HH])
     6612#define RSCAN0TMID61 (RSCAN0.TMID61.UINT32)
     6613#define RSCAN0TMID61L (RSCAN0.TMID61.UINT16[R_IO_L])
     6614#define RSCAN0TMID61LL (RSCAN0.TMID61.UINT8[R_IO_LL])
     6615#define RSCAN0TMID61LH (RSCAN0.TMID61.UINT8[R_IO_LH])
     6616#define RSCAN0TMID61H (RSCAN0.TMID61.UINT16[R_IO_H])
     6617#define RSCAN0TMID61HL (RSCAN0.TMID61.UINT8[R_IO_HL])
     6618#define RSCAN0TMID61HH (RSCAN0.TMID61.UINT8[R_IO_HH])
     6619#define RSCAN0TMPTR61 (RSCAN0.TMPTR61.UINT32)
     6620#define RSCAN0TMPTR61L (RSCAN0.TMPTR61.UINT16[R_IO_L])
     6621#define RSCAN0TMPTR61LL (RSCAN0.TMPTR61.UINT8[R_IO_LL])
     6622#define RSCAN0TMPTR61LH (RSCAN0.TMPTR61.UINT8[R_IO_LH])
     6623#define RSCAN0TMPTR61H (RSCAN0.TMPTR61.UINT16[R_IO_H])
     6624#define RSCAN0TMPTR61HL (RSCAN0.TMPTR61.UINT8[R_IO_HL])
     6625#define RSCAN0TMPTR61HH (RSCAN0.TMPTR61.UINT8[R_IO_HH])
     6626#define RSCAN0TMDF061 (RSCAN0.TMDF061.UINT32)
     6627#define RSCAN0TMDF061L (RSCAN0.TMDF061.UINT16[R_IO_L])
     6628#define RSCAN0TMDF061LL (RSCAN0.TMDF061.UINT8[R_IO_LL])
     6629#define RSCAN0TMDF061LH (RSCAN0.TMDF061.UINT8[R_IO_LH])
     6630#define RSCAN0TMDF061H (RSCAN0.TMDF061.UINT16[R_IO_H])
     6631#define RSCAN0TMDF061HL (RSCAN0.TMDF061.UINT8[R_IO_HL])
     6632#define RSCAN0TMDF061HH (RSCAN0.TMDF061.UINT8[R_IO_HH])
     6633#define RSCAN0TMDF161 (RSCAN0.TMDF161.UINT32)
     6634#define RSCAN0TMDF161L (RSCAN0.TMDF161.UINT16[R_IO_L])
     6635#define RSCAN0TMDF161LL (RSCAN0.TMDF161.UINT8[R_IO_LL])
     6636#define RSCAN0TMDF161LH (RSCAN0.TMDF161.UINT8[R_IO_LH])
     6637#define RSCAN0TMDF161H (RSCAN0.TMDF161.UINT16[R_IO_H])
     6638#define RSCAN0TMDF161HL (RSCAN0.TMDF161.UINT8[R_IO_HL])
     6639#define RSCAN0TMDF161HH (RSCAN0.TMDF161.UINT8[R_IO_HH])
     6640#define RSCAN0TMID62 (RSCAN0.TMID62.UINT32)
     6641#define RSCAN0TMID62L (RSCAN0.TMID62.UINT16[R_IO_L])
     6642#define RSCAN0TMID62LL (RSCAN0.TMID62.UINT8[R_IO_LL])
     6643#define RSCAN0TMID62LH (RSCAN0.TMID62.UINT8[R_IO_LH])
     6644#define RSCAN0TMID62H (RSCAN0.TMID62.UINT16[R_IO_H])
     6645#define RSCAN0TMID62HL (RSCAN0.TMID62.UINT8[R_IO_HL])
     6646#define RSCAN0TMID62HH (RSCAN0.TMID62.UINT8[R_IO_HH])
     6647#define RSCAN0TMPTR62 (RSCAN0.TMPTR62.UINT32)
     6648#define RSCAN0TMPTR62L (RSCAN0.TMPTR62.UINT16[R_IO_L])
     6649#define RSCAN0TMPTR62LL (RSCAN0.TMPTR62.UINT8[R_IO_LL])
     6650#define RSCAN0TMPTR62LH (RSCAN0.TMPTR62.UINT8[R_IO_LH])
     6651#define RSCAN0TMPTR62H (RSCAN0.TMPTR62.UINT16[R_IO_H])
     6652#define RSCAN0TMPTR62HL (RSCAN0.TMPTR62.UINT8[R_IO_HL])
     6653#define RSCAN0TMPTR62HH (RSCAN0.TMPTR62.UINT8[R_IO_HH])
     6654#define RSCAN0TMDF062 (RSCAN0.TMDF062.UINT32)
     6655#define RSCAN0TMDF062L (RSCAN0.TMDF062.UINT16[R_IO_L])
     6656#define RSCAN0TMDF062LL (RSCAN0.TMDF062.UINT8[R_IO_LL])
     6657#define RSCAN0TMDF062LH (RSCAN0.TMDF062.UINT8[R_IO_LH])
     6658#define RSCAN0TMDF062H (RSCAN0.TMDF062.UINT16[R_IO_H])
     6659#define RSCAN0TMDF062HL (RSCAN0.TMDF062.UINT8[R_IO_HL])
     6660#define RSCAN0TMDF062HH (RSCAN0.TMDF062.UINT8[R_IO_HH])
     6661#define RSCAN0TMDF162 (RSCAN0.TMDF162.UINT32)
     6662#define RSCAN0TMDF162L (RSCAN0.TMDF162.UINT16[R_IO_L])
     6663#define RSCAN0TMDF162LL (RSCAN0.TMDF162.UINT8[R_IO_LL])
     6664#define RSCAN0TMDF162LH (RSCAN0.TMDF162.UINT8[R_IO_LH])
     6665#define RSCAN0TMDF162H (RSCAN0.TMDF162.UINT16[R_IO_H])
     6666#define RSCAN0TMDF162HL (RSCAN0.TMDF162.UINT8[R_IO_HL])
     6667#define RSCAN0TMDF162HH (RSCAN0.TMDF162.UINT8[R_IO_HH])
     6668#define RSCAN0TMID63 (RSCAN0.TMID63.UINT32)
     6669#define RSCAN0TMID63L (RSCAN0.TMID63.UINT16[R_IO_L])
     6670#define RSCAN0TMID63LL (RSCAN0.TMID63.UINT8[R_IO_LL])
     6671#define RSCAN0TMID63LH (RSCAN0.TMID63.UINT8[R_IO_LH])
     6672#define RSCAN0TMID63H (RSCAN0.TMID63.UINT16[R_IO_H])
     6673#define RSCAN0TMID63HL (RSCAN0.TMID63.UINT8[R_IO_HL])
     6674#define RSCAN0TMID63HH (RSCAN0.TMID63.UINT8[R_IO_HH])
     6675#define RSCAN0TMPTR63 (RSCAN0.TMPTR63.UINT32)
     6676#define RSCAN0TMPTR63L (RSCAN0.TMPTR63.UINT16[R_IO_L])
     6677#define RSCAN0TMPTR63LL (RSCAN0.TMPTR63.UINT8[R_IO_LL])
     6678#define RSCAN0TMPTR63LH (RSCAN0.TMPTR63.UINT8[R_IO_LH])
     6679#define RSCAN0TMPTR63H (RSCAN0.TMPTR63.UINT16[R_IO_H])
     6680#define RSCAN0TMPTR63HL (RSCAN0.TMPTR63.UINT8[R_IO_HL])
     6681#define RSCAN0TMPTR63HH (RSCAN0.TMPTR63.UINT8[R_IO_HH])
     6682#define RSCAN0TMDF063 (RSCAN0.TMDF063.UINT32)
     6683#define RSCAN0TMDF063L (RSCAN0.TMDF063.UINT16[R_IO_L])
     6684#define RSCAN0TMDF063LL (RSCAN0.TMDF063.UINT8[R_IO_LL])
     6685#define RSCAN0TMDF063LH (RSCAN0.TMDF063.UINT8[R_IO_LH])
     6686#define RSCAN0TMDF063H (RSCAN0.TMDF063.UINT16[R_IO_H])
     6687#define RSCAN0TMDF063HL (RSCAN0.TMDF063.UINT8[R_IO_HL])
     6688#define RSCAN0TMDF063HH (RSCAN0.TMDF063.UINT8[R_IO_HH])
     6689#define RSCAN0TMDF163 (RSCAN0.TMDF163.UINT32)
     6690#define RSCAN0TMDF163L (RSCAN0.TMDF163.UINT16[R_IO_L])
     6691#define RSCAN0TMDF163LL (RSCAN0.TMDF163.UINT8[R_IO_LL])
     6692#define RSCAN0TMDF163LH (RSCAN0.TMDF163.UINT8[R_IO_LH])
     6693#define RSCAN0TMDF163H (RSCAN0.TMDF163.UINT16[R_IO_H])
     6694#define RSCAN0TMDF163HL (RSCAN0.TMDF163.UINT8[R_IO_HL])
     6695#define RSCAN0TMDF163HH (RSCAN0.TMDF163.UINT8[R_IO_HH])
     6696#define RSCAN0TMID64 (RSCAN0.TMID64.UINT32)
     6697#define RSCAN0TMID64L (RSCAN0.TMID64.UINT16[R_IO_L])
     6698#define RSCAN0TMID64LL (RSCAN0.TMID64.UINT8[R_IO_LL])
     6699#define RSCAN0TMID64LH (RSCAN0.TMID64.UINT8[R_IO_LH])
     6700#define RSCAN0TMID64H (RSCAN0.TMID64.UINT16[R_IO_H])
     6701#define RSCAN0TMID64HL (RSCAN0.TMID64.UINT8[R_IO_HL])
     6702#define RSCAN0TMID64HH (RSCAN0.TMID64.UINT8[R_IO_HH])
     6703#define RSCAN0TMPTR64 (RSCAN0.TMPTR64.UINT32)
     6704#define RSCAN0TMPTR64L (RSCAN0.TMPTR64.UINT16[R_IO_L])
     6705#define RSCAN0TMPTR64LL (RSCAN0.TMPTR64.UINT8[R_IO_LL])
     6706#define RSCAN0TMPTR64LH (RSCAN0.TMPTR64.UINT8[R_IO_LH])
     6707#define RSCAN0TMPTR64H (RSCAN0.TMPTR64.UINT16[R_IO_H])
     6708#define RSCAN0TMPTR64HL (RSCAN0.TMPTR64.UINT8[R_IO_HL])
     6709#define RSCAN0TMPTR64HH (RSCAN0.TMPTR64.UINT8[R_IO_HH])
     6710#define RSCAN0TMDF064 (RSCAN0.TMDF064.UINT32)
     6711#define RSCAN0TMDF064L (RSCAN0.TMDF064.UINT16[R_IO_L])
     6712#define RSCAN0TMDF064LL (RSCAN0.TMDF064.UINT8[R_IO_LL])
     6713#define RSCAN0TMDF064LH (RSCAN0.TMDF064.UINT8[R_IO_LH])
     6714#define RSCAN0TMDF064H (RSCAN0.TMDF064.UINT16[R_IO_H])
     6715#define RSCAN0TMDF064HL (RSCAN0.TMDF064.UINT8[R_IO_HL])
     6716#define RSCAN0TMDF064HH (RSCAN0.TMDF064.UINT8[R_IO_HH])
     6717#define RSCAN0TMDF164 (RSCAN0.TMDF164.UINT32)
     6718#define RSCAN0TMDF164L (RSCAN0.TMDF164.UINT16[R_IO_L])
     6719#define RSCAN0TMDF164LL (RSCAN0.TMDF164.UINT8[R_IO_LL])
     6720#define RSCAN0TMDF164LH (RSCAN0.TMDF164.UINT8[R_IO_LH])
     6721#define RSCAN0TMDF164H (RSCAN0.TMDF164.UINT16[R_IO_H])
     6722#define RSCAN0TMDF164HL (RSCAN0.TMDF164.UINT8[R_IO_HL])
     6723#define RSCAN0TMDF164HH (RSCAN0.TMDF164.UINT8[R_IO_HH])
     6724#define RSCAN0TMID65 (RSCAN0.TMID65.UINT32)
     6725#define RSCAN0TMID65L (RSCAN0.TMID65.UINT16[R_IO_L])
     6726#define RSCAN0TMID65LL (RSCAN0.TMID65.UINT8[R_IO_LL])
     6727#define RSCAN0TMID65LH (RSCAN0.TMID65.UINT8[R_IO_LH])
     6728#define RSCAN0TMID65H (RSCAN0.TMID65.UINT16[R_IO_H])
     6729#define RSCAN0TMID65HL (RSCAN0.TMID65.UINT8[R_IO_HL])
     6730#define RSCAN0TMID65HH (RSCAN0.TMID65.UINT8[R_IO_HH])
     6731#define RSCAN0TMPTR65 (RSCAN0.TMPTR65.UINT32)
     6732#define RSCAN0TMPTR65L (RSCAN0.TMPTR65.UINT16[R_IO_L])
     6733#define RSCAN0TMPTR65LL (RSCAN0.TMPTR65.UINT8[R_IO_LL])
     6734#define RSCAN0TMPTR65LH (RSCAN0.TMPTR65.UINT8[R_IO_LH])
     6735#define RSCAN0TMPTR65H (RSCAN0.TMPTR65.UINT16[R_IO_H])
     6736#define RSCAN0TMPTR65HL (RSCAN0.TMPTR65.UINT8[R_IO_HL])
     6737#define RSCAN0TMPTR65HH (RSCAN0.TMPTR65.UINT8[R_IO_HH])
     6738#define RSCAN0TMDF065 (RSCAN0.TMDF065.UINT32)
     6739#define RSCAN0TMDF065L (RSCAN0.TMDF065.UINT16[R_IO_L])
     6740#define RSCAN0TMDF065LL (RSCAN0.TMDF065.UINT8[R_IO_LL])
     6741#define RSCAN0TMDF065LH (RSCAN0.TMDF065.UINT8[R_IO_LH])
     6742#define RSCAN0TMDF065H (RSCAN0.TMDF065.UINT16[R_IO_H])
     6743#define RSCAN0TMDF065HL (RSCAN0.TMDF065.UINT8[R_IO_HL])
     6744#define RSCAN0TMDF065HH (RSCAN0.TMDF065.UINT8[R_IO_HH])
     6745#define RSCAN0TMDF165 (RSCAN0.TMDF165.UINT32)
     6746#define RSCAN0TMDF165L (RSCAN0.TMDF165.UINT16[R_IO_L])
     6747#define RSCAN0TMDF165LL (RSCAN0.TMDF165.UINT8[R_IO_LL])
     6748#define RSCAN0TMDF165LH (RSCAN0.TMDF165.UINT8[R_IO_LH])
     6749#define RSCAN0TMDF165H (RSCAN0.TMDF165.UINT16[R_IO_H])
     6750#define RSCAN0TMDF165HL (RSCAN0.TMDF165.UINT8[R_IO_HL])
     6751#define RSCAN0TMDF165HH (RSCAN0.TMDF165.UINT8[R_IO_HH])
     6752#define RSCAN0TMID66 (RSCAN0.TMID66.UINT32)
     6753#define RSCAN0TMID66L (RSCAN0.TMID66.UINT16[R_IO_L])
     6754#define RSCAN0TMID66LL (RSCAN0.TMID66.UINT8[R_IO_LL])
     6755#define RSCAN0TMID66LH (RSCAN0.TMID66.UINT8[R_IO_LH])
     6756#define RSCAN0TMID66H (RSCAN0.TMID66.UINT16[R_IO_H])
     6757#define RSCAN0TMID66HL (RSCAN0.TMID66.UINT8[R_IO_HL])
     6758#define RSCAN0TMID66HH (RSCAN0.TMID66.UINT8[R_IO_HH])
     6759#define RSCAN0TMPTR66 (RSCAN0.TMPTR66.UINT32)
     6760#define RSCAN0TMPTR66L (RSCAN0.TMPTR66.UINT16[R_IO_L])
     6761#define RSCAN0TMPTR66LL (RSCAN0.TMPTR66.UINT8[R_IO_LL])
     6762#define RSCAN0TMPTR66LH (RSCAN0.TMPTR66.UINT8[R_IO_LH])
     6763#define RSCAN0TMPTR66H (RSCAN0.TMPTR66.UINT16[R_IO_H])
     6764#define RSCAN0TMPTR66HL (RSCAN0.TMPTR66.UINT8[R_IO_HL])
     6765#define RSCAN0TMPTR66HH (RSCAN0.TMPTR66.UINT8[R_IO_HH])
     6766#define RSCAN0TMDF066 (RSCAN0.TMDF066.UINT32)
     6767#define RSCAN0TMDF066L (RSCAN0.TMDF066.UINT16[R_IO_L])
     6768#define RSCAN0TMDF066LL (RSCAN0.TMDF066.UINT8[R_IO_LL])
     6769#define RSCAN0TMDF066LH (RSCAN0.TMDF066.UINT8[R_IO_LH])
     6770#define RSCAN0TMDF066H (RSCAN0.TMDF066.UINT16[R_IO_H])
     6771#define RSCAN0TMDF066HL (RSCAN0.TMDF066.UINT8[R_IO_HL])
     6772#define RSCAN0TMDF066HH (RSCAN0.TMDF066.UINT8[R_IO_HH])
     6773#define RSCAN0TMDF166 (RSCAN0.TMDF166.UINT32)
     6774#define RSCAN0TMDF166L (RSCAN0.TMDF166.UINT16[R_IO_L])
     6775#define RSCAN0TMDF166LL (RSCAN0.TMDF166.UINT8[R_IO_LL])
     6776#define RSCAN0TMDF166LH (RSCAN0.TMDF166.UINT8[R_IO_LH])
     6777#define RSCAN0TMDF166H (RSCAN0.TMDF166.UINT16[R_IO_H])
     6778#define RSCAN0TMDF166HL (RSCAN0.TMDF166.UINT8[R_IO_HL])
     6779#define RSCAN0TMDF166HH (RSCAN0.TMDF166.UINT8[R_IO_HH])
     6780#define RSCAN0TMID67 (RSCAN0.TMID67.UINT32)
     6781#define RSCAN0TMID67L (RSCAN0.TMID67.UINT16[R_IO_L])
     6782#define RSCAN0TMID67LL (RSCAN0.TMID67.UINT8[R_IO_LL])
     6783#define RSCAN0TMID67LH (RSCAN0.TMID67.UINT8[R_IO_LH])
     6784#define RSCAN0TMID67H (RSCAN0.TMID67.UINT16[R_IO_H])
     6785#define RSCAN0TMID67HL (RSCAN0.TMID67.UINT8[R_IO_HL])
     6786#define RSCAN0TMID67HH (RSCAN0.TMID67.UINT8[R_IO_HH])
     6787#define RSCAN0TMPTR67 (RSCAN0.TMPTR67.UINT32)
     6788#define RSCAN0TMPTR67L (RSCAN0.TMPTR67.UINT16[R_IO_L])
     6789#define RSCAN0TMPTR67LL (RSCAN0.TMPTR67.UINT8[R_IO_LL])
     6790#define RSCAN0TMPTR67LH (RSCAN0.TMPTR67.UINT8[R_IO_LH])
     6791#define RSCAN0TMPTR67H (RSCAN0.TMPTR67.UINT16[R_IO_H])
     6792#define RSCAN0TMPTR67HL (RSCAN0.TMPTR67.UINT8[R_IO_HL])
     6793#define RSCAN0TMPTR67HH (RSCAN0.TMPTR67.UINT8[R_IO_HH])
     6794#define RSCAN0TMDF067 (RSCAN0.TMDF067.UINT32)
     6795#define RSCAN0TMDF067L (RSCAN0.TMDF067.UINT16[R_IO_L])
     6796#define RSCAN0TMDF067LL (RSCAN0.TMDF067.UINT8[R_IO_LL])
     6797#define RSCAN0TMDF067LH (RSCAN0.TMDF067.UINT8[R_IO_LH])
     6798#define RSCAN0TMDF067H (RSCAN0.TMDF067.UINT16[R_IO_H])
     6799#define RSCAN0TMDF067HL (RSCAN0.TMDF067.UINT8[R_IO_HL])
     6800#define RSCAN0TMDF067HH (RSCAN0.TMDF067.UINT8[R_IO_HH])
     6801#define RSCAN0TMDF167 (RSCAN0.TMDF167.UINT32)
     6802#define RSCAN0TMDF167L (RSCAN0.TMDF167.UINT16[R_IO_L])
     6803#define RSCAN0TMDF167LL (RSCAN0.TMDF167.UINT8[R_IO_LL])
     6804#define RSCAN0TMDF167LH (RSCAN0.TMDF167.UINT8[R_IO_LH])
     6805#define RSCAN0TMDF167H (RSCAN0.TMDF167.UINT16[R_IO_H])
     6806#define RSCAN0TMDF167HL (RSCAN0.TMDF167.UINT8[R_IO_HL])
     6807#define RSCAN0TMDF167HH (RSCAN0.TMDF167.UINT8[R_IO_HH])
     6808#define RSCAN0TMID68 (RSCAN0.TMID68.UINT32)
     6809#define RSCAN0TMID68L (RSCAN0.TMID68.UINT16[R_IO_L])
     6810#define RSCAN0TMID68LL (RSCAN0.TMID68.UINT8[R_IO_LL])
     6811#define RSCAN0TMID68LH (RSCAN0.TMID68.UINT8[R_IO_LH])
     6812#define RSCAN0TMID68H (RSCAN0.TMID68.UINT16[R_IO_H])
     6813#define RSCAN0TMID68HL (RSCAN0.TMID68.UINT8[R_IO_HL])
     6814#define RSCAN0TMID68HH (RSCAN0.TMID68.UINT8[R_IO_HH])
     6815#define RSCAN0TMPTR68 (RSCAN0.TMPTR68.UINT32)
     6816#define RSCAN0TMPTR68L (RSCAN0.TMPTR68.UINT16[R_IO_L])
     6817#define RSCAN0TMPTR68LL (RSCAN0.TMPTR68.UINT8[R_IO_LL])
     6818#define RSCAN0TMPTR68LH (RSCAN0.TMPTR68.UINT8[R_IO_LH])
     6819#define RSCAN0TMPTR68H (RSCAN0.TMPTR68.UINT16[R_IO_H])
     6820#define RSCAN0TMPTR68HL (RSCAN0.TMPTR68.UINT8[R_IO_HL])
     6821#define RSCAN0TMPTR68HH (RSCAN0.TMPTR68.UINT8[R_IO_HH])
     6822#define RSCAN0TMDF068 (RSCAN0.TMDF068.UINT32)
     6823#define RSCAN0TMDF068L (RSCAN0.TMDF068.UINT16[R_IO_L])
     6824#define RSCAN0TMDF068LL (RSCAN0.TMDF068.UINT8[R_IO_LL])
     6825#define RSCAN0TMDF068LH (RSCAN0.TMDF068.UINT8[R_IO_LH])
     6826#define RSCAN0TMDF068H (RSCAN0.TMDF068.UINT16[R_IO_H])
     6827#define RSCAN0TMDF068HL (RSCAN0.TMDF068.UINT8[R_IO_HL])
     6828#define RSCAN0TMDF068HH (RSCAN0.TMDF068.UINT8[R_IO_HH])
     6829#define RSCAN0TMDF168 (RSCAN0.TMDF168.UINT32)
     6830#define RSCAN0TMDF168L (RSCAN0.TMDF168.UINT16[R_IO_L])
     6831#define RSCAN0TMDF168LL (RSCAN0.TMDF168.UINT8[R_IO_LL])
     6832#define RSCAN0TMDF168LH (RSCAN0.TMDF168.UINT8[R_IO_LH])
     6833#define RSCAN0TMDF168H (RSCAN0.TMDF168.UINT16[R_IO_H])
     6834#define RSCAN0TMDF168HL (RSCAN0.TMDF168.UINT8[R_IO_HL])
     6835#define RSCAN0TMDF168HH (RSCAN0.TMDF168.UINT8[R_IO_HH])
     6836#define RSCAN0TMID69 (RSCAN0.TMID69.UINT32)
     6837#define RSCAN0TMID69L (RSCAN0.TMID69.UINT16[R_IO_L])
     6838#define RSCAN0TMID69LL (RSCAN0.TMID69.UINT8[R_IO_LL])
     6839#define RSCAN0TMID69LH (RSCAN0.TMID69.UINT8[R_IO_LH])
     6840#define RSCAN0TMID69H (RSCAN0.TMID69.UINT16[R_IO_H])
     6841#define RSCAN0TMID69HL (RSCAN0.TMID69.UINT8[R_IO_HL])
     6842#define RSCAN0TMID69HH (RSCAN0.TMID69.UINT8[R_IO_HH])
     6843#define RSCAN0TMPTR69 (RSCAN0.TMPTR69.UINT32)
     6844#define RSCAN0TMPTR69L (RSCAN0.TMPTR69.UINT16[R_IO_L])
     6845#define RSCAN0TMPTR69LL (RSCAN0.TMPTR69.UINT8[R_IO_LL])
     6846#define RSCAN0TMPTR69LH (RSCAN0.TMPTR69.UINT8[R_IO_LH])
     6847#define RSCAN0TMPTR69H (RSCAN0.TMPTR69.UINT16[R_IO_H])
     6848#define RSCAN0TMPTR69HL (RSCAN0.TMPTR69.UINT8[R_IO_HL])
     6849#define RSCAN0TMPTR69HH (RSCAN0.TMPTR69.UINT8[R_IO_HH])
     6850#define RSCAN0TMDF069 (RSCAN0.TMDF069.UINT32)
     6851#define RSCAN0TMDF069L (RSCAN0.TMDF069.UINT16[R_IO_L])
     6852#define RSCAN0TMDF069LL (RSCAN0.TMDF069.UINT8[R_IO_LL])
     6853#define RSCAN0TMDF069LH (RSCAN0.TMDF069.UINT8[R_IO_LH])
     6854#define RSCAN0TMDF069H (RSCAN0.TMDF069.UINT16[R_IO_H])
     6855#define RSCAN0TMDF069HL (RSCAN0.TMDF069.UINT8[R_IO_HL])
     6856#define RSCAN0TMDF069HH (RSCAN0.TMDF069.UINT8[R_IO_HH])
     6857#define RSCAN0TMDF169 (RSCAN0.TMDF169.UINT32)
     6858#define RSCAN0TMDF169L (RSCAN0.TMDF169.UINT16[R_IO_L])
     6859#define RSCAN0TMDF169LL (RSCAN0.TMDF169.UINT8[R_IO_LL])
     6860#define RSCAN0TMDF169LH (RSCAN0.TMDF169.UINT8[R_IO_LH])
     6861#define RSCAN0TMDF169H (RSCAN0.TMDF169.UINT16[R_IO_H])
     6862#define RSCAN0TMDF169HL (RSCAN0.TMDF169.UINT8[R_IO_HL])
     6863#define RSCAN0TMDF169HH (RSCAN0.TMDF169.UINT8[R_IO_HH])
     6864#define RSCAN0TMID70 (RSCAN0.TMID70.UINT32)
     6865#define RSCAN0TMID70L (RSCAN0.TMID70.UINT16[R_IO_L])
     6866#define RSCAN0TMID70LL (RSCAN0.TMID70.UINT8[R_IO_LL])
     6867#define RSCAN0TMID70LH (RSCAN0.TMID70.UINT8[R_IO_LH])
     6868#define RSCAN0TMID70H (RSCAN0.TMID70.UINT16[R_IO_H])
     6869#define RSCAN0TMID70HL (RSCAN0.TMID70.UINT8[R_IO_HL])
     6870#define RSCAN0TMID70HH (RSCAN0.TMID70.UINT8[R_IO_HH])
     6871#define RSCAN0TMPTR70 (RSCAN0.TMPTR70.UINT32)
     6872#define RSCAN0TMPTR70L (RSCAN0.TMPTR70.UINT16[R_IO_L])
     6873#define RSCAN0TMPTR70LL (RSCAN0.TMPTR70.UINT8[R_IO_LL])
     6874#define RSCAN0TMPTR70LH (RSCAN0.TMPTR70.UINT8[R_IO_LH])
     6875#define RSCAN0TMPTR70H (RSCAN0.TMPTR70.UINT16[R_IO_H])
     6876#define RSCAN0TMPTR70HL (RSCAN0.TMPTR70.UINT8[R_IO_HL])
     6877#define RSCAN0TMPTR70HH (RSCAN0.TMPTR70.UINT8[R_IO_HH])
     6878#define RSCAN0TMDF070 (RSCAN0.TMDF070.UINT32)
     6879#define RSCAN0TMDF070L (RSCAN0.TMDF070.UINT16[R_IO_L])
     6880#define RSCAN0TMDF070LL (RSCAN0.TMDF070.UINT8[R_IO_LL])
     6881#define RSCAN0TMDF070LH (RSCAN0.TMDF070.UINT8[R_IO_LH])
     6882#define RSCAN0TMDF070H (RSCAN0.TMDF070.UINT16[R_IO_H])
     6883#define RSCAN0TMDF070HL (RSCAN0.TMDF070.UINT8[R_IO_HL])
     6884#define RSCAN0TMDF070HH (RSCAN0.TMDF070.UINT8[R_IO_HH])
     6885#define RSCAN0TMDF170 (RSCAN0.TMDF170.UINT32)
     6886#define RSCAN0TMDF170L (RSCAN0.TMDF170.UINT16[R_IO_L])
     6887#define RSCAN0TMDF170LL (RSCAN0.TMDF170.UINT8[R_IO_LL])
     6888#define RSCAN0TMDF170LH (RSCAN0.TMDF170.UINT8[R_IO_LH])
     6889#define RSCAN0TMDF170H (RSCAN0.TMDF170.UINT16[R_IO_H])
     6890#define RSCAN0TMDF170HL (RSCAN0.TMDF170.UINT8[R_IO_HL])
     6891#define RSCAN0TMDF170HH (RSCAN0.TMDF170.UINT8[R_IO_HH])
     6892#define RSCAN0TMID71 (RSCAN0.TMID71.UINT32)
     6893#define RSCAN0TMID71L (RSCAN0.TMID71.UINT16[R_IO_L])
     6894#define RSCAN0TMID71LL (RSCAN0.TMID71.UINT8[R_IO_LL])
     6895#define RSCAN0TMID71LH (RSCAN0.TMID71.UINT8[R_IO_LH])
     6896#define RSCAN0TMID71H (RSCAN0.TMID71.UINT16[R_IO_H])
     6897#define RSCAN0TMID71HL (RSCAN0.TMID71.UINT8[R_IO_HL])
     6898#define RSCAN0TMID71HH (RSCAN0.TMID71.UINT8[R_IO_HH])
     6899#define RSCAN0TMPTR71 (RSCAN0.TMPTR71.UINT32)
     6900#define RSCAN0TMPTR71L (RSCAN0.TMPTR71.UINT16[R_IO_L])
     6901#define RSCAN0TMPTR71LL (RSCAN0.TMPTR71.UINT8[R_IO_LL])
     6902#define RSCAN0TMPTR71LH (RSCAN0.TMPTR71.UINT8[R_IO_LH])
     6903#define RSCAN0TMPTR71H (RSCAN0.TMPTR71.UINT16[R_IO_H])
     6904#define RSCAN0TMPTR71HL (RSCAN0.TMPTR71.UINT8[R_IO_HL])
     6905#define RSCAN0TMPTR71HH (RSCAN0.TMPTR71.UINT8[R_IO_HH])
     6906#define RSCAN0TMDF071 (RSCAN0.TMDF071.UINT32)
     6907#define RSCAN0TMDF071L (RSCAN0.TMDF071.UINT16[R_IO_L])
     6908#define RSCAN0TMDF071LL (RSCAN0.TMDF071.UINT8[R_IO_LL])
     6909#define RSCAN0TMDF071LH (RSCAN0.TMDF071.UINT8[R_IO_LH])
     6910#define RSCAN0TMDF071H (RSCAN0.TMDF071.UINT16[R_IO_H])
     6911#define RSCAN0TMDF071HL (RSCAN0.TMDF071.UINT8[R_IO_HL])
     6912#define RSCAN0TMDF071HH (RSCAN0.TMDF071.UINT8[R_IO_HH])
     6913#define RSCAN0TMDF171 (RSCAN0.TMDF171.UINT32)
     6914#define RSCAN0TMDF171L (RSCAN0.TMDF171.UINT16[R_IO_L])
     6915#define RSCAN0TMDF171LL (RSCAN0.TMDF171.UINT8[R_IO_LL])
     6916#define RSCAN0TMDF171LH (RSCAN0.TMDF171.UINT8[R_IO_LH])
     6917#define RSCAN0TMDF171H (RSCAN0.TMDF171.UINT16[R_IO_H])
     6918#define RSCAN0TMDF171HL (RSCAN0.TMDF171.UINT8[R_IO_HL])
     6919#define RSCAN0TMDF171HH (RSCAN0.TMDF171.UINT8[R_IO_HH])
     6920#define RSCAN0TMID72 (RSCAN0.TMID72.UINT32)
     6921#define RSCAN0TMID72L (RSCAN0.TMID72.UINT16[R_IO_L])
     6922#define RSCAN0TMID72LL (RSCAN0.TMID72.UINT8[R_IO_LL])
     6923#define RSCAN0TMID72LH (RSCAN0.TMID72.UINT8[R_IO_LH])
     6924#define RSCAN0TMID72H (RSCAN0.TMID72.UINT16[R_IO_H])
     6925#define RSCAN0TMID72HL (RSCAN0.TMID72.UINT8[R_IO_HL])
     6926#define RSCAN0TMID72HH (RSCAN0.TMID72.UINT8[R_IO_HH])
     6927#define RSCAN0TMPTR72 (RSCAN0.TMPTR72.UINT32)
     6928#define RSCAN0TMPTR72L (RSCAN0.TMPTR72.UINT16[R_IO_L])
     6929#define RSCAN0TMPTR72LL (RSCAN0.TMPTR72.UINT8[R_IO_LL])
     6930#define RSCAN0TMPTR72LH (RSCAN0.TMPTR72.UINT8[R_IO_LH])
     6931#define RSCAN0TMPTR72H (RSCAN0.TMPTR72.UINT16[R_IO_H])
     6932#define RSCAN0TMPTR72HL (RSCAN0.TMPTR72.UINT8[R_IO_HL])
     6933#define RSCAN0TMPTR72HH (RSCAN0.TMPTR72.UINT8[R_IO_HH])
     6934#define RSCAN0TMDF072 (RSCAN0.TMDF072.UINT32)
     6935#define RSCAN0TMDF072L (RSCAN0.TMDF072.UINT16[R_IO_L])
     6936#define RSCAN0TMDF072LL (RSCAN0.TMDF072.UINT8[R_IO_LL])
     6937#define RSCAN0TMDF072LH (RSCAN0.TMDF072.UINT8[R_IO_LH])
     6938#define RSCAN0TMDF072H (RSCAN0.TMDF072.UINT16[R_IO_H])
     6939#define RSCAN0TMDF072HL (RSCAN0.TMDF072.UINT8[R_IO_HL])
     6940#define RSCAN0TMDF072HH (RSCAN0.TMDF072.UINT8[R_IO_HH])
     6941#define RSCAN0TMDF172 (RSCAN0.TMDF172.UINT32)
     6942#define RSCAN0TMDF172L (RSCAN0.TMDF172.UINT16[R_IO_L])
     6943#define RSCAN0TMDF172LL (RSCAN0.TMDF172.UINT8[R_IO_LL])
     6944#define RSCAN0TMDF172LH (RSCAN0.TMDF172.UINT8[R_IO_LH])
     6945#define RSCAN0TMDF172H (RSCAN0.TMDF172.UINT16[R_IO_H])
     6946#define RSCAN0TMDF172HL (RSCAN0.TMDF172.UINT8[R_IO_HL])
     6947#define RSCAN0TMDF172HH (RSCAN0.TMDF172.UINT8[R_IO_HH])
     6948#define RSCAN0TMID73 (RSCAN0.TMID73.UINT32)
     6949#define RSCAN0TMID73L (RSCAN0.TMID73.UINT16[R_IO_L])
     6950#define RSCAN0TMID73LL (RSCAN0.TMID73.UINT8[R_IO_LL])
     6951#define RSCAN0TMID73LH (RSCAN0.TMID73.UINT8[R_IO_LH])
     6952#define RSCAN0TMID73H (RSCAN0.TMID73.UINT16[R_IO_H])
     6953#define RSCAN0TMID73HL (RSCAN0.TMID73.UINT8[R_IO_HL])
     6954#define RSCAN0TMID73HH (RSCAN0.TMID73.UINT8[R_IO_HH])
     6955#define RSCAN0TMPTR73 (RSCAN0.TMPTR73.UINT32)
     6956#define RSCAN0TMPTR73L (RSCAN0.TMPTR73.UINT16[R_IO_L])
     6957#define RSCAN0TMPTR73LL (RSCAN0.TMPTR73.UINT8[R_IO_LL])
     6958#define RSCAN0TMPTR73LH (RSCAN0.TMPTR73.UINT8[R_IO_LH])
     6959#define RSCAN0TMPTR73H (RSCAN0.TMPTR73.UINT16[R_IO_H])
     6960#define RSCAN0TMPTR73HL (RSCAN0.TMPTR73.UINT8[R_IO_HL])
     6961#define RSCAN0TMPTR73HH (RSCAN0.TMPTR73.UINT8[R_IO_HH])
     6962#define RSCAN0TMDF073 (RSCAN0.TMDF073.UINT32)
     6963#define RSCAN0TMDF073L (RSCAN0.TMDF073.UINT16[R_IO_L])
     6964#define RSCAN0TMDF073LL (RSCAN0.TMDF073.UINT8[R_IO_LL])
     6965#define RSCAN0TMDF073LH (RSCAN0.TMDF073.UINT8[R_IO_LH])
     6966#define RSCAN0TMDF073H (RSCAN0.TMDF073.UINT16[R_IO_H])
     6967#define RSCAN0TMDF073HL (RSCAN0.TMDF073.UINT8[R_IO_HL])
     6968#define RSCAN0TMDF073HH (RSCAN0.TMDF073.UINT8[R_IO_HH])
     6969#define RSCAN0TMDF173 (RSCAN0.TMDF173.UINT32)
     6970#define RSCAN0TMDF173L (RSCAN0.TMDF173.UINT16[R_IO_L])
     6971#define RSCAN0TMDF173LL (RSCAN0.TMDF173.UINT8[R_IO_LL])
     6972#define RSCAN0TMDF173LH (RSCAN0.TMDF173.UINT8[R_IO_LH])
     6973#define RSCAN0TMDF173H (RSCAN0.TMDF173.UINT16[R_IO_H])
     6974#define RSCAN0TMDF173HL (RSCAN0.TMDF173.UINT8[R_IO_HL])
     6975#define RSCAN0TMDF173HH (RSCAN0.TMDF173.UINT8[R_IO_HH])
     6976#define RSCAN0TMID74 (RSCAN0.TMID74.UINT32)
     6977#define RSCAN0TMID74L (RSCAN0.TMID74.UINT16[R_IO_L])
     6978#define RSCAN0TMID74LL (RSCAN0.TMID74.UINT8[R_IO_LL])
     6979#define RSCAN0TMID74LH (RSCAN0.TMID74.UINT8[R_IO_LH])
     6980#define RSCAN0TMID74H (RSCAN0.TMID74.UINT16[R_IO_H])
     6981#define RSCAN0TMID74HL (RSCAN0.TMID74.UINT8[R_IO_HL])
     6982#define RSCAN0TMID74HH (RSCAN0.TMID74.UINT8[R_IO_HH])
     6983#define RSCAN0TMPTR74 (RSCAN0.TMPTR74.UINT32)
     6984#define RSCAN0TMPTR74L (RSCAN0.TMPTR74.UINT16[R_IO_L])
     6985#define RSCAN0TMPTR74LL (RSCAN0.TMPTR74.UINT8[R_IO_LL])
     6986#define RSCAN0TMPTR74LH (RSCAN0.TMPTR74.UINT8[R_IO_LH])
     6987#define RSCAN0TMPTR74H (RSCAN0.TMPTR74.UINT16[R_IO_H])
     6988#define RSCAN0TMPTR74HL (RSCAN0.TMPTR74.UINT8[R_IO_HL])
     6989#define RSCAN0TMPTR74HH (RSCAN0.TMPTR74.UINT8[R_IO_HH])
     6990#define RSCAN0TMDF074 (RSCAN0.TMDF074.UINT32)
     6991#define RSCAN0TMDF074L (RSCAN0.TMDF074.UINT16[R_IO_L])
     6992#define RSCAN0TMDF074LL (RSCAN0.TMDF074.UINT8[R_IO_LL])
     6993#define RSCAN0TMDF074LH (RSCAN0.TMDF074.UINT8[R_IO_LH])
     6994#define RSCAN0TMDF074H (RSCAN0.TMDF074.UINT16[R_IO_H])
     6995#define RSCAN0TMDF074HL (RSCAN0.TMDF074.UINT8[R_IO_HL])
     6996#define RSCAN0TMDF074HH (RSCAN0.TMDF074.UINT8[R_IO_HH])
     6997#define RSCAN0TMDF174 (RSCAN0.TMDF174.UINT32)
     6998#define RSCAN0TMDF174L (RSCAN0.TMDF174.UINT16[R_IO_L])
     6999#define RSCAN0TMDF174LL (RSCAN0.TMDF174.UINT8[R_IO_LL])
     7000#define RSCAN0TMDF174LH (RSCAN0.TMDF174.UINT8[R_IO_LH])
     7001#define RSCAN0TMDF174H (RSCAN0.TMDF174.UINT16[R_IO_H])
     7002#define RSCAN0TMDF174HL (RSCAN0.TMDF174.UINT8[R_IO_HL])
     7003#define RSCAN0TMDF174HH (RSCAN0.TMDF174.UINT8[R_IO_HH])
     7004#define RSCAN0TMID75 (RSCAN0.TMID75.UINT32)
     7005#define RSCAN0TMID75L (RSCAN0.TMID75.UINT16[R_IO_L])
     7006#define RSCAN0TMID75LL (RSCAN0.TMID75.UINT8[R_IO_LL])
     7007#define RSCAN0TMID75LH (RSCAN0.TMID75.UINT8[R_IO_LH])
     7008#define RSCAN0TMID75H (RSCAN0.TMID75.UINT16[R_IO_H])
     7009#define RSCAN0TMID75HL (RSCAN0.TMID75.UINT8[R_IO_HL])
     7010#define RSCAN0TMID75HH (RSCAN0.TMID75.UINT8[R_IO_HH])
     7011#define RSCAN0TMPTR75 (RSCAN0.TMPTR75.UINT32)
     7012#define RSCAN0TMPTR75L (RSCAN0.TMPTR75.UINT16[R_IO_L])
     7013#define RSCAN0TMPTR75LL (RSCAN0.TMPTR75.UINT8[R_IO_LL])
     7014#define RSCAN0TMPTR75LH (RSCAN0.TMPTR75.UINT8[R_IO_LH])
     7015#define RSCAN0TMPTR75H (RSCAN0.TMPTR75.UINT16[R_IO_H])
     7016#define RSCAN0TMPTR75HL (RSCAN0.TMPTR75.UINT8[R_IO_HL])
     7017#define RSCAN0TMPTR75HH (RSCAN0.TMPTR75.UINT8[R_IO_HH])
     7018#define RSCAN0TMDF075 (RSCAN0.TMDF075.UINT32)
     7019#define RSCAN0TMDF075L (RSCAN0.TMDF075.UINT16[R_IO_L])
     7020#define RSCAN0TMDF075LL (RSCAN0.TMDF075.UINT8[R_IO_LL])
     7021#define RSCAN0TMDF075LH (RSCAN0.TMDF075.UINT8[R_IO_LH])
     7022#define RSCAN0TMDF075H (RSCAN0.TMDF075.UINT16[R_IO_H])
     7023#define RSCAN0TMDF075HL (RSCAN0.TMDF075.UINT8[R_IO_HL])
     7024#define RSCAN0TMDF075HH (RSCAN0.TMDF075.UINT8[R_IO_HH])
     7025#define RSCAN0TMDF175 (RSCAN0.TMDF175.UINT32)
     7026#define RSCAN0TMDF175L (RSCAN0.TMDF175.UINT16[R_IO_L])
     7027#define RSCAN0TMDF175LL (RSCAN0.TMDF175.UINT8[R_IO_LL])
     7028#define RSCAN0TMDF175LH (RSCAN0.TMDF175.UINT8[R_IO_LH])
     7029#define RSCAN0TMDF175H (RSCAN0.TMDF175.UINT16[R_IO_H])
     7030#define RSCAN0TMDF175HL (RSCAN0.TMDF175.UINT8[R_IO_HL])
     7031#define RSCAN0TMDF175HH (RSCAN0.TMDF175.UINT8[R_IO_HH])
     7032#define RSCAN0TMID76 (RSCAN0.TMID76.UINT32)
     7033#define RSCAN0TMID76L (RSCAN0.TMID76.UINT16[R_IO_L])
     7034#define RSCAN0TMID76LL (RSCAN0.TMID76.UINT8[R_IO_LL])
     7035#define RSCAN0TMID76LH (RSCAN0.TMID76.UINT8[R_IO_LH])
     7036#define RSCAN0TMID76H (RSCAN0.TMID76.UINT16[R_IO_H])
     7037#define RSCAN0TMID76HL (RSCAN0.TMID76.UINT8[R_IO_HL])
     7038#define RSCAN0TMID76HH (RSCAN0.TMID76.UINT8[R_IO_HH])
     7039#define RSCAN0TMPTR76 (RSCAN0.TMPTR76.UINT32)
     7040#define RSCAN0TMPTR76L (RSCAN0.TMPTR76.UINT16[R_IO_L])
     7041#define RSCAN0TMPTR76LL (RSCAN0.TMPTR76.UINT8[R_IO_LL])
     7042#define RSCAN0TMPTR76LH (RSCAN0.TMPTR76.UINT8[R_IO_LH])
     7043#define RSCAN0TMPTR76H (RSCAN0.TMPTR76.UINT16[R_IO_H])
     7044#define RSCAN0TMPTR76HL (RSCAN0.TMPTR76.UINT8[R_IO_HL])
     7045#define RSCAN0TMPTR76HH (RSCAN0.TMPTR76.UINT8[R_IO_HH])
     7046#define RSCAN0TMDF076 (RSCAN0.TMDF076.UINT32)
     7047#define RSCAN0TMDF076L (RSCAN0.TMDF076.UINT16[R_IO_L])
     7048#define RSCAN0TMDF076LL (RSCAN0.TMDF076.UINT8[R_IO_LL])
     7049#define RSCAN0TMDF076LH (RSCAN0.TMDF076.UINT8[R_IO_LH])
     7050#define RSCAN0TMDF076H (RSCAN0.TMDF076.UINT16[R_IO_H])
     7051#define RSCAN0TMDF076HL (RSCAN0.TMDF076.UINT8[R_IO_HL])
     7052#define RSCAN0TMDF076HH (RSCAN0.TMDF076.UINT8[R_IO_HH])
     7053#define RSCAN0TMDF176 (RSCAN0.TMDF176.UINT32)
     7054#define RSCAN0TMDF176L (RSCAN0.TMDF176.UINT16[R_IO_L])
     7055#define RSCAN0TMDF176LL (RSCAN0.TMDF176.UINT8[R_IO_LL])
     7056#define RSCAN0TMDF176LH (RSCAN0.TMDF176.UINT8[R_IO_LH])
     7057#define RSCAN0TMDF176H (RSCAN0.TMDF176.UINT16[R_IO_H])
     7058#define RSCAN0TMDF176HL (RSCAN0.TMDF176.UINT8[R_IO_HL])
     7059#define RSCAN0TMDF176HH (RSCAN0.TMDF176.UINT8[R_IO_HH])
     7060#define RSCAN0TMID77 (RSCAN0.TMID77.UINT32)
     7061#define RSCAN0TMID77L (RSCAN0.TMID77.UINT16[R_IO_L])
     7062#define RSCAN0TMID77LL (RSCAN0.TMID77.UINT8[R_IO_LL])
     7063#define RSCAN0TMID77LH (RSCAN0.TMID77.UINT8[R_IO_LH])
     7064#define RSCAN0TMID77H (RSCAN0.TMID77.UINT16[R_IO_H])
     7065#define RSCAN0TMID77HL (RSCAN0.TMID77.UINT8[R_IO_HL])
     7066#define RSCAN0TMID77HH (RSCAN0.TMID77.UINT8[R_IO_HH])
     7067#define RSCAN0TMPTR77 (RSCAN0.TMPTR77.UINT32)
     7068#define RSCAN0TMPTR77L (RSCAN0.TMPTR77.UINT16[R_IO_L])
     7069#define RSCAN0TMPTR77LL (RSCAN0.TMPTR77.UINT8[R_IO_LL])
     7070#define RSCAN0TMPTR77LH (RSCAN0.TMPTR77.UINT8[R_IO_LH])
     7071#define RSCAN0TMPTR77H (RSCAN0.TMPTR77.UINT16[R_IO_H])
     7072#define RSCAN0TMPTR77HL (RSCAN0.TMPTR77.UINT8[R_IO_HL])
     7073#define RSCAN0TMPTR77HH (RSCAN0.TMPTR77.UINT8[R_IO_HH])
     7074#define RSCAN0TMDF077 (RSCAN0.TMDF077.UINT32)
     7075#define RSCAN0TMDF077L (RSCAN0.TMDF077.UINT16[R_IO_L])
     7076#define RSCAN0TMDF077LL (RSCAN0.TMDF077.UINT8[R_IO_LL])
     7077#define RSCAN0TMDF077LH (RSCAN0.TMDF077.UINT8[R_IO_LH])
     7078#define RSCAN0TMDF077H (RSCAN0.TMDF077.UINT16[R_IO_H])
     7079#define RSCAN0TMDF077HL (RSCAN0.TMDF077.UINT8[R_IO_HL])
     7080#define RSCAN0TMDF077HH (RSCAN0.TMDF077.UINT8[R_IO_HH])
     7081#define RSCAN0TMDF177 (RSCAN0.TMDF177.UINT32)
     7082#define RSCAN0TMDF177L (RSCAN0.TMDF177.UINT16[R_IO_L])
     7083#define RSCAN0TMDF177LL (RSCAN0.TMDF177.UINT8[R_IO_LL])
     7084#define RSCAN0TMDF177LH (RSCAN0.TMDF177.UINT8[R_IO_LH])
     7085#define RSCAN0TMDF177H (RSCAN0.TMDF177.UINT16[R_IO_H])
     7086#define RSCAN0TMDF177HL (RSCAN0.TMDF177.UINT8[R_IO_HL])
     7087#define RSCAN0TMDF177HH (RSCAN0.TMDF177.UINT8[R_IO_HH])
     7088#define RSCAN0TMID78 (RSCAN0.TMID78.UINT32)
     7089#define RSCAN0TMID78L (RSCAN0.TMID78.UINT16[R_IO_L])
     7090#define RSCAN0TMID78LL (RSCAN0.TMID78.UINT8[R_IO_LL])
     7091#define RSCAN0TMID78LH (RSCAN0.TMID78.UINT8[R_IO_LH])
     7092#define RSCAN0TMID78H (RSCAN0.TMID78.UINT16[R_IO_H])
     7093#define RSCAN0TMID78HL (RSCAN0.TMID78.UINT8[R_IO_HL])
     7094#define RSCAN0TMID78HH (RSCAN0.TMID78.UINT8[R_IO_HH])
     7095#define RSCAN0TMPTR78 (RSCAN0.TMPTR78.UINT32)
     7096#define RSCAN0TMPTR78L (RSCAN0.TMPTR78.UINT16[R_IO_L])
     7097#define RSCAN0TMPTR78LL (RSCAN0.TMPTR78.UINT8[R_IO_LL])
     7098#define RSCAN0TMPTR78LH (RSCAN0.TMPTR78.UINT8[R_IO_LH])
     7099#define RSCAN0TMPTR78H (RSCAN0.TMPTR78.UINT16[R_IO_H])
     7100#define RSCAN0TMPTR78HL (RSCAN0.TMPTR78.UINT8[R_IO_HL])
     7101#define RSCAN0TMPTR78HH (RSCAN0.TMPTR78.UINT8[R_IO_HH])
     7102#define RSCAN0TMDF078 (RSCAN0.TMDF078.UINT32)
     7103#define RSCAN0TMDF078L (RSCAN0.TMDF078.UINT16[R_IO_L])
     7104#define RSCAN0TMDF078LL (RSCAN0.TMDF078.UINT8[R_IO_LL])
     7105#define RSCAN0TMDF078LH (RSCAN0.TMDF078.UINT8[R_IO_LH])
     7106#define RSCAN0TMDF078H (RSCAN0.TMDF078.UINT16[R_IO_H])
     7107#define RSCAN0TMDF078HL (RSCAN0.TMDF078.UINT8[R_IO_HL])
     7108#define RSCAN0TMDF078HH (RSCAN0.TMDF078.UINT8[R_IO_HH])
     7109#define RSCAN0TMDF178 (RSCAN0.TMDF178.UINT32)
     7110#define RSCAN0TMDF178L (RSCAN0.TMDF178.UINT16[R_IO_L])
     7111#define RSCAN0TMDF178LL (RSCAN0.TMDF178.UINT8[R_IO_LL])
     7112#define RSCAN0TMDF178LH (RSCAN0.TMDF178.UINT8[R_IO_LH])
     7113#define RSCAN0TMDF178H (RSCAN0.TMDF178.UINT16[R_IO_H])
     7114#define RSCAN0TMDF178HL (RSCAN0.TMDF178.UINT8[R_IO_HL])
     7115#define RSCAN0TMDF178HH (RSCAN0.TMDF178.UINT8[R_IO_HH])
     7116#define RSCAN0TMID79 (RSCAN0.TMID79.UINT32)
     7117#define RSCAN0TMID79L (RSCAN0.TMID79.UINT16[R_IO_L])
     7118#define RSCAN0TMID79LL (RSCAN0.TMID79.UINT8[R_IO_LL])
     7119#define RSCAN0TMID79LH (RSCAN0.TMID79.UINT8[R_IO_LH])
     7120#define RSCAN0TMID79H (RSCAN0.TMID79.UINT16[R_IO_H])
     7121#define RSCAN0TMID79HL (RSCAN0.TMID79.UINT8[R_IO_HL])
     7122#define RSCAN0TMID79HH (RSCAN0.TMID79.UINT8[R_IO_HH])
     7123#define RSCAN0TMPTR79 (RSCAN0.TMPTR79.UINT32)
     7124#define RSCAN0TMPTR79L (RSCAN0.TMPTR79.UINT16[R_IO_L])
     7125#define RSCAN0TMPTR79LL (RSCAN0.TMPTR79.UINT8[R_IO_LL])
     7126#define RSCAN0TMPTR79LH (RSCAN0.TMPTR79.UINT8[R_IO_LH])
     7127#define RSCAN0TMPTR79H (RSCAN0.TMPTR79.UINT16[R_IO_H])
     7128#define RSCAN0TMPTR79HL (RSCAN0.TMPTR79.UINT8[R_IO_HL])
     7129#define RSCAN0TMPTR79HH (RSCAN0.TMPTR79.UINT8[R_IO_HH])
     7130#define RSCAN0TMDF079 (RSCAN0.TMDF079.UINT32)
     7131#define RSCAN0TMDF079L (RSCAN0.TMDF079.UINT16[R_IO_L])
     7132#define RSCAN0TMDF079LL (RSCAN0.TMDF079.UINT8[R_IO_LL])
     7133#define RSCAN0TMDF079LH (RSCAN0.TMDF079.UINT8[R_IO_LH])
     7134#define RSCAN0TMDF079H (RSCAN0.TMDF079.UINT16[R_IO_H])
     7135#define RSCAN0TMDF079HL (RSCAN0.TMDF079.UINT8[R_IO_HL])
     7136#define RSCAN0TMDF079HH (RSCAN0.TMDF079.UINT8[R_IO_HH])
     7137#define RSCAN0TMDF179 (RSCAN0.TMDF179.UINT32)
     7138#define RSCAN0TMDF179L (RSCAN0.TMDF179.UINT16[R_IO_L])
     7139#define RSCAN0TMDF179LL (RSCAN0.TMDF179.UINT8[R_IO_LL])
     7140#define RSCAN0TMDF179LH (RSCAN0.TMDF179.UINT8[R_IO_LH])
     7141#define RSCAN0TMDF179H (RSCAN0.TMDF179.UINT16[R_IO_H])
     7142#define RSCAN0TMDF179HL (RSCAN0.TMDF179.UINT8[R_IO_HL])
     7143#define RSCAN0TMDF179HH (RSCAN0.TMDF179.UINT8[R_IO_HH])
     7144#define RSCAN0THLACC0 (RSCAN0.THLACC0.UINT32)
     7145#define RSCAN0THLACC0L (RSCAN0.THLACC0.UINT16[R_IO_L])
     7146#define RSCAN0THLACC0LL (RSCAN0.THLACC0.UINT8[R_IO_LL])
     7147#define RSCAN0THLACC0LH (RSCAN0.THLACC0.UINT8[R_IO_LH])
     7148#define RSCAN0THLACC0H (RSCAN0.THLACC0.UINT16[R_IO_H])
     7149#define RSCAN0THLACC0HL (RSCAN0.THLACC0.UINT8[R_IO_HL])
     7150#define RSCAN0THLACC0HH (RSCAN0.THLACC0.UINT8[R_IO_HH])
     7151#define RSCAN0THLACC1 (RSCAN0.THLACC1.UINT32)
     7152#define RSCAN0THLACC1L (RSCAN0.THLACC1.UINT16[R_IO_L])
     7153#define RSCAN0THLACC1LL (RSCAN0.THLACC1.UINT8[R_IO_LL])
     7154#define RSCAN0THLACC1LH (RSCAN0.THLACC1.UINT8[R_IO_LH])
     7155#define RSCAN0THLACC1H (RSCAN0.THLACC1.UINT16[R_IO_H])
     7156#define RSCAN0THLACC1HL (RSCAN0.THLACC1.UINT8[R_IO_HL])
     7157#define RSCAN0THLACC1HH (RSCAN0.THLACC1.UINT8[R_IO_HH])
     7158#define RSCAN0THLACC2 (RSCAN0.THLACC2.UINT32)
     7159#define RSCAN0THLACC2L (RSCAN0.THLACC2.UINT16[R_IO_L])
     7160#define RSCAN0THLACC2LL (RSCAN0.THLACC2.UINT8[R_IO_LL])
     7161#define RSCAN0THLACC2LH (RSCAN0.THLACC2.UINT8[R_IO_LH])
     7162#define RSCAN0THLACC2H (RSCAN0.THLACC2.UINT16[R_IO_H])
     7163#define RSCAN0THLACC2HL (RSCAN0.THLACC2.UINT8[R_IO_HL])
     7164#define RSCAN0THLACC2HH (RSCAN0.THLACC2.UINT8[R_IO_HH])
     7165#define RSCAN0THLACC3 (RSCAN0.THLACC3.UINT32)
     7166#define RSCAN0THLACC3L (RSCAN0.THLACC3.UINT16[R_IO_L])
     7167#define RSCAN0THLACC3LL (RSCAN0.THLACC3.UINT8[R_IO_LL])
     7168#define RSCAN0THLACC3LH (RSCAN0.THLACC3.UINT8[R_IO_LH])
     7169#define RSCAN0THLACC3H (RSCAN0.THLACC3.UINT16[R_IO_H])
     7170#define RSCAN0THLACC3HL (RSCAN0.THLACC3.UINT8[R_IO_HL])
     7171#define RSCAN0THLACC3HH (RSCAN0.THLACC3.UINT8[R_IO_HH])
     7172#define RSCAN0THLACC4 (RSCAN0.THLACC4.UINT32)
     7173#define RSCAN0THLACC4L (RSCAN0.THLACC4.UINT16[R_IO_L])
     7174#define RSCAN0THLACC4LL (RSCAN0.THLACC4.UINT8[R_IO_LL])
     7175#define RSCAN0THLACC4LH (RSCAN0.THLACC4.UINT8[R_IO_LH])
     7176#define RSCAN0THLACC4H (RSCAN0.THLACC4.UINT16[R_IO_H])
     7177#define RSCAN0THLACC4HL (RSCAN0.THLACC4.UINT8[R_IO_HL])
     7178#define RSCAN0THLACC4HH (RSCAN0.THLACC4.UINT8[R_IO_HH])
     7179
     7180#define RSCAN0_GAFLCFG0_COUNT (2)
     7181#define RSCAN0_RMND0_COUNT (3)
     7182#define RSCAN0_RFCC0_COUNT (8)
     7183#define RSCAN0_RFSTS0_COUNT (8)
     7184#define RSCAN0_RFPCTR0_COUNT (8)
     7185#define RSCAN0_CFCC0_COUNT (15)
     7186#define RSCAN0_CFSTS0_COUNT (15)
     7187#define RSCAN0_CFPCTR0_COUNT (15)
     7188#define RSCAN0_TMC0_COUNT (80)
     7189#define RSCAN0_TMSTS0_COUNT (80)
     7190#define RSCAN0_TMTRSTS0_COUNT (3)
     7191#define RSCAN0_TMTARSTS0_COUNT (3)
     7192#define RSCAN0_TMTCSTS0_COUNT (3)
     7193#define RSCAN0_TMTASTS0_COUNT (3)
     7194#define RSCAN0_TMIEC0_COUNT (3)
     7195#define RSCAN0_TXQCC0_COUNT (5)
     7196#define RSCAN0_TXQSTS0_COUNT (5)
     7197#define RSCAN0_TXQPCTR0_COUNT (5)
     7198#define RSCAN0_THLCC0_COUNT (5)
     7199#define RSCAN0_THLSTS0_COUNT (5)
     7200#define RSCAN0_THLPCTR0_COUNT (5)
     7201#define RSCAN0_GTINTSTS0_COUNT (2)
     7202#define RSCAN0_THLACC0_COUNT (5)
     7203
     7204
     7205typedef struct st_rscan0
     7206{
     7207                                                           /* RSCAN0           */
     7208
     7209/* start of struct st_rscan_from_rscan0cncfg */
     7210    union iodefine_reg32_t  C0CFG;                         /*  C0CFG           */
     7211    union iodefine_reg32_t  C0CTR;                         /*  C0CTR           */
     7212    union iodefine_reg32_t  C0STS;                         /*  C0STS           */
     7213    union iodefine_reg32_t  C0ERFL;                        /*  C0ERFL          */
     7214
     7215/* end of struct st_rscan_from_rscan0cncfg */
     7216   
     7217/* start of struct st_rscan_from_rscan0cncfg */
     7218    union iodefine_reg32_t  C1CFG;                         /*  C1CFG           */
     7219    union iodefine_reg32_t  C1CTR;                         /*  C1CTR           */
     7220    union iodefine_reg32_t  C1STS;                         /*  C1STS           */
     7221    union iodefine_reg32_t  C1ERFL;                        /*  C1ERFL          */
     7222
     7223/* end of struct st_rscan_from_rscan0cncfg */
     7224   
     7225/* start of struct st_rscan_from_rscan0cncfg */
     7226    union iodefine_reg32_t  C2CFG;                         /*  C2CFG           */
     7227    union iodefine_reg32_t  C2CTR;                         /*  C2CTR           */
     7228    union iodefine_reg32_t  C2STS;                         /*  C2STS           */
     7229    union iodefine_reg32_t  C2ERFL;                        /*  C2ERFL          */
     7230
     7231/* end of struct st_rscan_from_rscan0cncfg */
     7232   
     7233/* start of struct st_rscan_from_rscan0cncfg */
     7234    union iodefine_reg32_t  C3CFG;                         /*  C3CFG           */
     7235    union iodefine_reg32_t  C3CTR;                         /*  C3CTR           */
     7236    union iodefine_reg32_t  C3STS;                         /*  C3STS           */
     7237    union iodefine_reg32_t  C3ERFL;                        /*  C3ERFL          */
     7238
     7239/* end of struct st_rscan_from_rscan0cncfg */
     7240   
     7241/* start of struct st_rscan_from_rscan0cncfg */
     7242    union iodefine_reg32_t  C4CFG;                         /*  C4CFG           */
     7243    union iodefine_reg32_t  C4CTR;                         /*  C4CTR           */
     7244    union iodefine_reg32_t  C4STS;                         /*  C4STS           */
     7245    union iodefine_reg32_t  C4ERFL;                        /*  C4ERFL          */
     7246
     7247/* end of struct st_rscan_from_rscan0cncfg */
     7248   
     7249    volatile uint8_t   dummy159[52];                           /*                  */
     7250    union iodefine_reg32_t  GCFG;                          /*  GCFG            */
     7251    union iodefine_reg32_t  GCTR;                          /*  GCTR            */
     7252    union iodefine_reg32_t  GSTS;                          /*  GSTS            */
     7253    union iodefine_reg32_t  GERFL;                         /*  GERFL           */
     7254    union iodefine_reg32_16_t  GTSC;                       /*  GTSC            */
     7255    union iodefine_reg32_t  GAFLECTR;                      /*  GAFLECTR        */
     7256
     7257/* #define RSCAN0_GAFLCFG0_COUNT (2) */
     7258    union iodefine_reg32_t  GAFLCFG0;                      /*  GAFLCFG0        */
     7259    union iodefine_reg32_t  GAFLCFG1;                      /*  GAFLCFG1        */
     7260    union iodefine_reg32_t  RMNB;                          /*  RMNB            */
     7261
     7262/* #define RSCAN0_RMND0_COUNT (3) */
     7263    union iodefine_reg32_t  RMND0;                         /*  RMND0           */
     7264    union iodefine_reg32_t  RMND1;                         /*  RMND1           */
     7265    union iodefine_reg32_t  RMND2;                         /*  RMND2           */
     7266   
     7267    volatile uint8_t   dummy160[4];                            /*                  */
     7268
     7269/* #define RSCAN0_RFCC0_COUNT (8) */
     7270    union iodefine_reg32_t  RFCC0;                         /*  RFCC0           */
     7271    union iodefine_reg32_t  RFCC1;                         /*  RFCC1           */
     7272    union iodefine_reg32_t  RFCC2;                         /*  RFCC2           */
     7273    union iodefine_reg32_t  RFCC3;                         /*  RFCC3           */
     7274    union iodefine_reg32_t  RFCC4;                         /*  RFCC4           */
     7275    union iodefine_reg32_t  RFCC5;                         /*  RFCC5           */
     7276    union iodefine_reg32_t  RFCC6;                         /*  RFCC6           */
     7277    union iodefine_reg32_t  RFCC7;                         /*  RFCC7           */
     7278
     7279/* #define RSCAN0_RFSTS0_COUNT (8) */
     7280    union iodefine_reg32_t  RFSTS0;                        /*  RFSTS0          */
     7281    union iodefine_reg32_t  RFSTS1;                        /*  RFSTS1          */
     7282    union iodefine_reg32_t  RFSTS2;                        /*  RFSTS2          */
     7283    union iodefine_reg32_t  RFSTS3;                        /*  RFSTS3          */
     7284    union iodefine_reg32_t  RFSTS4;                        /*  RFSTS4          */
     7285    union iodefine_reg32_t  RFSTS5;                        /*  RFSTS5          */
     7286    union iodefine_reg32_t  RFSTS6;                        /*  RFSTS6          */
     7287    union iodefine_reg32_t  RFSTS7;                        /*  RFSTS7          */
     7288
     7289/* #define RSCAN0_RFPCTR0_COUNT (8) */
     7290    union iodefine_reg32_t  RFPCTR0;                       /*  RFPCTR0         */
     7291    union iodefine_reg32_t  RFPCTR1;                       /*  RFPCTR1         */
     7292    union iodefine_reg32_t  RFPCTR2;                       /*  RFPCTR2         */
     7293    union iodefine_reg32_t  RFPCTR3;                       /*  RFPCTR3         */
     7294    union iodefine_reg32_t  RFPCTR4;                       /*  RFPCTR4         */
     7295    union iodefine_reg32_t  RFPCTR5;                       /*  RFPCTR5         */
     7296    union iodefine_reg32_t  RFPCTR6;                       /*  RFPCTR6         */
     7297    union iodefine_reg32_t  RFPCTR7;                       /*  RFPCTR7         */
     7298
     7299/* #define RSCAN0_CFCC0_COUNT (15) */
     7300    union iodefine_reg32_t  CFCC0;                         /*  CFCC0           */
     7301    union iodefine_reg32_t  CFCC1;                         /*  CFCC1           */
     7302    union iodefine_reg32_t  CFCC2;                         /*  CFCC2           */
     7303    union iodefine_reg32_t  CFCC3;                         /*  CFCC3           */
     7304    union iodefine_reg32_t  CFCC4;                         /*  CFCC4           */
     7305    union iodefine_reg32_t  CFCC5;                         /*  CFCC5           */
     7306    union iodefine_reg32_t  CFCC6;                         /*  CFCC6           */
     7307    union iodefine_reg32_t  CFCC7;                         /*  CFCC7           */
     7308    union iodefine_reg32_t  CFCC8;                         /*  CFCC8           */
     7309    union iodefine_reg32_t  CFCC9;                         /*  CFCC9           */
     7310    union iodefine_reg32_t  CFCC10;                        /*  CFCC10          */
     7311    union iodefine_reg32_t  CFCC11;                        /*  CFCC11          */
     7312    union iodefine_reg32_t  CFCC12;                        /*  CFCC12          */
     7313    union iodefine_reg32_t  CFCC13;                        /*  CFCC13          */
     7314    union iodefine_reg32_t  CFCC14;                        /*  CFCC14          */
     7315   
     7316    volatile uint8_t   dummy161[36];                           /*                  */
     7317
     7318/* #define RSCAN0_CFSTS0_COUNT (15) */
     7319    union iodefine_reg32_t  CFSTS0;                        /*  CFSTS0          */
     7320    union iodefine_reg32_t  CFSTS1;                        /*  CFSTS1          */
     7321    union iodefine_reg32_t  CFSTS2;                        /*  CFSTS2          */
     7322    union iodefine_reg32_t  CFSTS3;                        /*  CFSTS3          */
     7323    union iodefine_reg32_t  CFSTS4;                        /*  CFSTS4          */
     7324    union iodefine_reg32_t  CFSTS5;                        /*  CFSTS5          */
     7325    union iodefine_reg32_t  CFSTS6;                        /*  CFSTS6          */
     7326    union iodefine_reg32_t  CFSTS7;                        /*  CFSTS7          */
     7327    union iodefine_reg32_t  CFSTS8;                        /*  CFSTS8          */
     7328    union iodefine_reg32_t  CFSTS9;                        /*  CFSTS9          */
     7329    union iodefine_reg32_t  CFSTS10;                       /*  CFSTS10         */
     7330    union iodefine_reg32_t  CFSTS11;                       /*  CFSTS11         */
     7331    union iodefine_reg32_t  CFSTS12;                       /*  CFSTS12         */
     7332    union iodefine_reg32_t  CFSTS13;                       /*  CFSTS13         */
     7333    union iodefine_reg32_t  CFSTS14;                       /*  CFSTS14         */
     7334   
     7335    volatile uint8_t   dummy162[36];                           /*                  */
     7336
     7337/* #define RSCAN0_CFPCTR0_COUNT (15) */
     7338    union iodefine_reg32_t  CFPCTR0;                       /*  CFPCTR0         */
     7339    union iodefine_reg32_t  CFPCTR1;                       /*  CFPCTR1         */
     7340    union iodefine_reg32_t  CFPCTR2;                       /*  CFPCTR2         */
     7341    union iodefine_reg32_t  CFPCTR3;                       /*  CFPCTR3         */
     7342    union iodefine_reg32_t  CFPCTR4;                       /*  CFPCTR4         */
     7343    union iodefine_reg32_t  CFPCTR5;                       /*  CFPCTR5         */
     7344    union iodefine_reg32_t  CFPCTR6;                       /*  CFPCTR6         */
     7345    union iodefine_reg32_t  CFPCTR7;                       /*  CFPCTR7         */
     7346    union iodefine_reg32_t  CFPCTR8;                       /*  CFPCTR8         */
     7347    union iodefine_reg32_t  CFPCTR9;                       /*  CFPCTR9         */
     7348    union iodefine_reg32_t  CFPCTR10;                      /*  CFPCTR10        */
     7349    union iodefine_reg32_t  CFPCTR11;                      /*  CFPCTR11        */
     7350    union iodefine_reg32_t  CFPCTR12;                      /*  CFPCTR12        */
     7351    union iodefine_reg32_t  CFPCTR13;                      /*  CFPCTR13        */
     7352    union iodefine_reg32_t  CFPCTR14;                      /*  CFPCTR14        */
     7353   
     7354    volatile uint8_t   dummy163[36];                           /*                  */
     7355    union iodefine_reg32_t  FESTS;                         /*  FESTS           */
     7356    union iodefine_reg32_t  FFSTS;                         /*  FFSTS           */
     7357    union iodefine_reg32_t  FMSTS;                         /*  FMSTS           */
     7358    union iodefine_reg32_t  RFISTS;                        /*  RFISTS          */
     7359    union iodefine_reg32_t  CFRISTS;                       /*  CFRISTS         */
     7360    union iodefine_reg32_t  CFTISTS;                       /*  CFTISTS         */
     7361   
     7362
     7363/* #define RSCAN0_TMC0_COUNT (80) */
     7364    volatile uint8_t   TMC0;                                   /*  TMC0            */
     7365    volatile uint8_t   TMC1;                                   /*  TMC1            */
     7366    volatile uint8_t   TMC2;                                   /*  TMC2            */
     7367    volatile uint8_t   TMC3;                                   /*  TMC3            */
     7368    volatile uint8_t   TMC4;                                   /*  TMC4            */
     7369    volatile uint8_t   TMC5;                                   /*  TMC5            */
     7370    volatile uint8_t   TMC6;                                   /*  TMC6            */
     7371    volatile uint8_t   TMC7;                                   /*  TMC7            */
     7372    volatile uint8_t   TMC8;                                   /*  TMC8            */
     7373    volatile uint8_t   TMC9;                                   /*  TMC9            */
     7374    volatile uint8_t   TMC10;                                  /*  TMC10           */
     7375    volatile uint8_t   TMC11;                                  /*  TMC11           */
     7376    volatile uint8_t   TMC12;                                  /*  TMC12           */
     7377    volatile uint8_t   TMC13;                                  /*  TMC13           */
     7378    volatile uint8_t   TMC14;                                  /*  TMC14           */
     7379    volatile uint8_t   TMC15;                                  /*  TMC15           */
     7380    volatile uint8_t   TMC16;                                  /*  TMC16           */
     7381    volatile uint8_t   TMC17;                                  /*  TMC17           */
     7382    volatile uint8_t   TMC18;                                  /*  TMC18           */
     7383    volatile uint8_t   TMC19;                                  /*  TMC19           */
     7384    volatile uint8_t   TMC20;                                  /*  TMC20           */
     7385    volatile uint8_t   TMC21;                                  /*  TMC21           */
     7386    volatile uint8_t   TMC22;                                  /*  TMC22           */
     7387    volatile uint8_t   TMC23;                                  /*  TMC23           */
     7388    volatile uint8_t   TMC24;                                  /*  TMC24           */
     7389    volatile uint8_t   TMC25;                                  /*  TMC25           */
     7390    volatile uint8_t   TMC26;                                  /*  TMC26           */
     7391    volatile uint8_t   TMC27;                                  /*  TMC27           */
     7392    volatile uint8_t   TMC28;                                  /*  TMC28           */
     7393    volatile uint8_t   TMC29;                                  /*  TMC29           */
     7394    volatile uint8_t   TMC30;                                  /*  TMC30           */
     7395    volatile uint8_t   TMC31;                                  /*  TMC31           */
     7396    volatile uint8_t   TMC32;                                  /*  TMC32           */
     7397    volatile uint8_t   TMC33;                                  /*  TMC33           */
     7398    volatile uint8_t   TMC34;                                  /*  TMC34           */
     7399    volatile uint8_t   TMC35;                                  /*  TMC35           */
     7400    volatile uint8_t   TMC36;                                  /*  TMC36           */
     7401    volatile uint8_t   TMC37;                                  /*  TMC37           */
     7402    volatile uint8_t   TMC38;                                  /*  TMC38           */
     7403    volatile uint8_t   TMC39;                                  /*  TMC39           */
     7404    volatile uint8_t   TMC40;                                  /*  TMC40           */
     7405    volatile uint8_t   TMC41;                                  /*  TMC41           */
     7406    volatile uint8_t   TMC42;                                  /*  TMC42           */
     7407    volatile uint8_t   TMC43;                                  /*  TMC43           */
     7408    volatile uint8_t   TMC44;                                  /*  TMC44           */
     7409    volatile uint8_t   TMC45;                                  /*  TMC45           */
     7410    volatile uint8_t   TMC46;                                  /*  TMC46           */
     7411    volatile uint8_t   TMC47;                                  /*  TMC47           */
     7412    volatile uint8_t   TMC48;                                  /*  TMC48           */
     7413    volatile uint8_t   TMC49;                                  /*  TMC49           */
     7414    volatile uint8_t   TMC50;                                  /*  TMC50           */
     7415    volatile uint8_t   TMC51;                                  /*  TMC51           */
     7416    volatile uint8_t   TMC52;                                  /*  TMC52           */
     7417    volatile uint8_t   TMC53;                                  /*  TMC53           */
     7418    volatile uint8_t   TMC54;                                  /*  TMC54           */
     7419    volatile uint8_t   TMC55;                                  /*  TMC55           */
     7420    volatile uint8_t   TMC56;                                  /*  TMC56           */
     7421    volatile uint8_t   TMC57;                                  /*  TMC57           */
     7422    volatile uint8_t   TMC58;                                  /*  TMC58           */
     7423    volatile uint8_t   TMC59;                                  /*  TMC59           */
     7424    volatile uint8_t   TMC60;                                  /*  TMC60           */
     7425    volatile uint8_t   TMC61;                                  /*  TMC61           */
     7426    volatile uint8_t   TMC62;                                  /*  TMC62           */
     7427    volatile uint8_t   TMC63;                                  /*  TMC63           */
     7428    volatile uint8_t   TMC64;                                  /*  TMC64           */
     7429    volatile uint8_t   TMC65;                                  /*  TMC65           */
     7430    volatile uint8_t   TMC66;                                  /*  TMC66           */
     7431    volatile uint8_t   TMC67;                                  /*  TMC67           */
     7432    volatile uint8_t   TMC68;                                  /*  TMC68           */
     7433    volatile uint8_t   TMC69;                                  /*  TMC69           */
     7434    volatile uint8_t   TMC70;                                  /*  TMC70           */
     7435    volatile uint8_t   TMC71;                                  /*  TMC71           */
     7436    volatile uint8_t   TMC72;                                  /*  TMC72           */
     7437    volatile uint8_t   TMC73;                                  /*  TMC73           */
     7438    volatile uint8_t   TMC74;                                  /*  TMC74           */
     7439    volatile uint8_t   TMC75;                                  /*  TMC75           */
     7440    volatile uint8_t   TMC76;                                  /*  TMC76           */
     7441    volatile uint8_t   TMC77;                                  /*  TMC77           */
     7442    volatile uint8_t   TMC78;                                  /*  TMC78           */
     7443    volatile uint8_t   TMC79;                                  /*  TMC79           */
     7444    volatile uint8_t   dummy164[48];                           /*                  */
     7445
     7446/* #define RSCAN0_TMSTS0_COUNT (80) */
     7447    volatile uint8_t   TMSTS0;                                 /*  TMSTS0          */
     7448    volatile uint8_t   TMSTS1;                                 /*  TMSTS1          */
     7449    volatile uint8_t   TMSTS2;                                 /*  TMSTS2          */
     7450    volatile uint8_t   TMSTS3;                                 /*  TMSTS3          */
     7451    volatile uint8_t   TMSTS4;                                 /*  TMSTS4          */
     7452    volatile uint8_t   TMSTS5;                                 /*  TMSTS5          */
     7453    volatile uint8_t   TMSTS6;                                 /*  TMSTS6          */
     7454    volatile uint8_t   TMSTS7;                                 /*  TMSTS7          */
     7455    volatile uint8_t   TMSTS8;                                 /*  TMSTS8          */
     7456    volatile uint8_t   TMSTS9;                                 /*  TMSTS9          */
     7457    volatile uint8_t   TMSTS10;                                /*  TMSTS10         */
     7458    volatile uint8_t   TMSTS11;                                /*  TMSTS11         */
     7459    volatile uint8_t   TMSTS12;                                /*  TMSTS12         */
     7460    volatile uint8_t   TMSTS13;                                /*  TMSTS13         */
     7461    volatile uint8_t   TMSTS14;                                /*  TMSTS14         */
     7462    volatile uint8_t   TMSTS15;                                /*  TMSTS15         */
     7463    volatile uint8_t   TMSTS16;                                /*  TMSTS16         */
     7464    volatile uint8_t   TMSTS17;                                /*  TMSTS17         */
     7465    volatile uint8_t   TMSTS18;                                /*  TMSTS18         */
     7466    volatile uint8_t   TMSTS19;                                /*  TMSTS19         */
     7467    volatile uint8_t   TMSTS20;                                /*  TMSTS20         */
     7468    volatile uint8_t   TMSTS21;                                /*  TMSTS21         */
     7469    volatile uint8_t   TMSTS22;                                /*  TMSTS22         */
     7470    volatile uint8_t   TMSTS23;                                /*  TMSTS23         */
     7471    volatile uint8_t   TMSTS24;                                /*  TMSTS24         */
     7472    volatile uint8_t   TMSTS25;                                /*  TMSTS25         */
     7473    volatile uint8_t   TMSTS26;                                /*  TMSTS26         */
     7474    volatile uint8_t   TMSTS27;                                /*  TMSTS27         */
     7475    volatile uint8_t   TMSTS28;                                /*  TMSTS28         */
     7476    volatile uint8_t   TMSTS29;                                /*  TMSTS29         */
     7477    volatile uint8_t   TMSTS30;                                /*  TMSTS30         */
     7478    volatile uint8_t   TMSTS31;                                /*  TMSTS31         */
     7479    volatile uint8_t   TMSTS32;                                /*  TMSTS32         */
     7480    volatile uint8_t   TMSTS33;                                /*  TMSTS33         */
     7481    volatile uint8_t   TMSTS34;                                /*  TMSTS34         */
     7482    volatile uint8_t   TMSTS35;                                /*  TMSTS35         */
     7483    volatile uint8_t   TMSTS36;                                /*  TMSTS36         */
     7484    volatile uint8_t   TMSTS37;                                /*  TMSTS37         */
     7485    volatile uint8_t   TMSTS38;                                /*  TMSTS38         */
     7486    volatile uint8_t   TMSTS39;                                /*  TMSTS39         */
     7487    volatile uint8_t   TMSTS40;                                /*  TMSTS40         */
     7488    volatile uint8_t   TMSTS41;                                /*  TMSTS41         */
     7489    volatile uint8_t   TMSTS42;                                /*  TMSTS42         */
     7490    volatile uint8_t   TMSTS43;                                /*  TMSTS43         */
     7491    volatile uint8_t   TMSTS44;                                /*  TMSTS44         */
     7492    volatile uint8_t   TMSTS45;                                /*  TMSTS45         */
     7493    volatile uint8_t   TMSTS46;                                /*  TMSTS46         */
     7494    volatile uint8_t   TMSTS47;                                /*  TMSTS47         */
     7495    volatile uint8_t   TMSTS48;                                /*  TMSTS48         */
     7496    volatile uint8_t   TMSTS49;                                /*  TMSTS49         */
     7497    volatile uint8_t   TMSTS50;                                /*  TMSTS50         */
     7498    volatile uint8_t   TMSTS51;                                /*  TMSTS51         */
     7499    volatile uint8_t   TMSTS52;                                /*  TMSTS52         */
     7500    volatile uint8_t   TMSTS53;                                /*  TMSTS53         */
     7501    volatile uint8_t   TMSTS54;                                /*  TMSTS54         */
     7502    volatile uint8_t   TMSTS55;                                /*  TMSTS55         */
     7503    volatile uint8_t   TMSTS56;                                /*  TMSTS56         */
     7504    volatile uint8_t   TMSTS57;                                /*  TMSTS57         */
     7505    volatile uint8_t   TMSTS58;                                /*  TMSTS58         */
     7506    volatile uint8_t   TMSTS59;                                /*  TMSTS59         */
     7507    volatile uint8_t   TMSTS60;                                /*  TMSTS60         */
     7508    volatile uint8_t   TMSTS61;                                /*  TMSTS61         */
     7509    volatile uint8_t   TMSTS62;                                /*  TMSTS62         */
     7510    volatile uint8_t   TMSTS63;                                /*  TMSTS63         */
     7511    volatile uint8_t   TMSTS64;                                /*  TMSTS64         */
     7512    volatile uint8_t   TMSTS65;                                /*  TMSTS65         */
     7513    volatile uint8_t   TMSTS66;                                /*  TMSTS66         */
     7514    volatile uint8_t   TMSTS67;                                /*  TMSTS67         */
     7515    volatile uint8_t   TMSTS68;                                /*  TMSTS68         */
     7516    volatile uint8_t   TMSTS69;                                /*  TMSTS69         */
     7517    volatile uint8_t   TMSTS70;                                /*  TMSTS70         */
     7518    volatile uint8_t   TMSTS71;                                /*  TMSTS71         */
     7519    volatile uint8_t   TMSTS72;                                /*  TMSTS72         */
     7520    volatile uint8_t   TMSTS73;                                /*  TMSTS73         */
     7521    volatile uint8_t   TMSTS74;                                /*  TMSTS74         */
     7522    volatile uint8_t   TMSTS75;                                /*  TMSTS75         */
     7523    volatile uint8_t   TMSTS76;                                /*  TMSTS76         */
     7524    volatile uint8_t   TMSTS77;                                /*  TMSTS77         */
     7525    volatile uint8_t   TMSTS78;                                /*  TMSTS78         */
     7526    volatile uint8_t   TMSTS79;                                /*  TMSTS79         */
     7527    volatile uint8_t   dummy165[48];                           /*                  */
     7528
     7529/* #define RSCAN0_TMTRSTS0_COUNT (3) */
     7530    union iodefine_reg32_t  TMTRSTS0;                      /*  TMTRSTS0        */
     7531    union iodefine_reg32_t  TMTRSTS1;                      /*  TMTRSTS1        */
     7532    union iodefine_reg32_t  TMTRSTS2;                      /*  TMTRSTS2        */
     7533   
     7534    volatile uint8_t   dummy166[4];                            /*                  */
     7535
     7536/* #define RSCAN0_TMTARSTS0_COUNT (3) */
     7537    union iodefine_reg32_t  TMTARSTS0;                     /*  TMTARSTS0       */
     7538    union iodefine_reg32_t  TMTARSTS1;                     /*  TMTARSTS1       */
     7539    union iodefine_reg32_t  TMTARSTS2;                     /*  TMTARSTS2       */
     7540   
     7541    volatile uint8_t   dummy167[4];                            /*                  */
     7542
     7543/* #define RSCAN0_TMTCSTS0_COUNT (3) */
     7544    union iodefine_reg32_t  TMTCSTS0;                      /*  TMTCSTS0        */
     7545    union iodefine_reg32_t  TMTCSTS1;                      /*  TMTCSTS1        */
     7546    union iodefine_reg32_t  TMTCSTS2;                      /*  TMTCSTS2        */
     7547   
     7548    volatile uint8_t   dummy168[4];                            /*                  */
     7549
     7550/* #define RSCAN0_TMTASTS0_COUNT (3) */
     7551    union iodefine_reg32_t  TMTASTS0;                      /*  TMTASTS0        */
     7552    union iodefine_reg32_t  TMTASTS1;                      /*  TMTASTS1        */
     7553    union iodefine_reg32_t  TMTASTS2;                      /*  TMTASTS2        */
     7554   
     7555    volatile uint8_t   dummy169[4];                            /*                  */
     7556
     7557/* #define RSCAN0_TMIEC0_COUNT (3) */
     7558    union iodefine_reg32_t  TMIEC0;                        /*  TMIEC0          */
     7559    union iodefine_reg32_t  TMIEC1;                        /*  TMIEC1          */
     7560    union iodefine_reg32_t  TMIEC2;                        /*  TMIEC2          */
     7561   
     7562    volatile uint8_t   dummy170[4];                            /*                  */
     7563
     7564/* #define RSCAN0_TXQCC0_COUNT (5) */
     7565    union iodefine_reg32_t  TXQCC0;                        /*  TXQCC0          */
     7566    union iodefine_reg32_t  TXQCC1;                        /*  TXQCC1          */
     7567    union iodefine_reg32_t  TXQCC2;                        /*  TXQCC2          */
     7568    union iodefine_reg32_t  TXQCC3;                        /*  TXQCC3          */
     7569    union iodefine_reg32_t  TXQCC4;                        /*  TXQCC4          */
     7570   
     7571    volatile uint8_t   dummy171[12];                           /*                  */
     7572
     7573/* #define RSCAN0_TXQSTS0_COUNT (5) */
     7574    union iodefine_reg32_t  TXQSTS0;                       /*  TXQSTS0         */
     7575    union iodefine_reg32_t  TXQSTS1;                       /*  TXQSTS1         */
     7576    union iodefine_reg32_t  TXQSTS2;                       /*  TXQSTS2         */
     7577    union iodefine_reg32_t  TXQSTS3;                       /*  TXQSTS3         */
     7578    union iodefine_reg32_t  TXQSTS4;                       /*  TXQSTS4         */
     7579   
     7580    volatile uint8_t   dummy172[12];                           /*                  */
     7581
     7582/* #define RSCAN0_TXQPCTR0_COUNT (5) */
     7583    union iodefine_reg32_t  TXQPCTR0;                      /*  TXQPCTR0        */
     7584    union iodefine_reg32_t  TXQPCTR1;                      /*  TXQPCTR1        */
     7585    union iodefine_reg32_t  TXQPCTR2;                      /*  TXQPCTR2        */
     7586    union iodefine_reg32_t  TXQPCTR3;                      /*  TXQPCTR3        */
     7587    union iodefine_reg32_t  TXQPCTR4;                      /*  TXQPCTR4        */
     7588   
     7589    volatile uint8_t   dummy173[12];                           /*                  */
     7590
     7591/* #define RSCAN0_THLCC0_COUNT (5) */
     7592    union iodefine_reg32_t  THLCC0;                        /*  THLCC0          */
     7593    union iodefine_reg32_t  THLCC1;                        /*  THLCC1          */
     7594    union iodefine_reg32_t  THLCC2;                        /*  THLCC2          */
     7595    union iodefine_reg32_t  THLCC3;                        /*  THLCC3          */
     7596    union iodefine_reg32_t  THLCC4;                        /*  THLCC4          */
     7597   
     7598    volatile uint8_t   dummy174[12];                           /*                  */
     7599
     7600/* #define RSCAN0_THLSTS0_COUNT (5) */
     7601    union iodefine_reg32_t  THLSTS0;                       /*  THLSTS0         */
     7602    union iodefine_reg32_t  THLSTS1;                       /*  THLSTS1         */
     7603    union iodefine_reg32_t  THLSTS2;                       /*  THLSTS2         */
     7604    union iodefine_reg32_t  THLSTS3;                       /*  THLSTS3         */
     7605    union iodefine_reg32_t  THLSTS4;                       /*  THLSTS4         */
     7606   
     7607    volatile uint8_t   dummy175[12];                           /*                  */
     7608
     7609/* #define RSCAN0_THLPCTR0_COUNT (5) */
     7610    union iodefine_reg32_t  THLPCTR0;                      /*  THLPCTR0        */
     7611    union iodefine_reg32_t  THLPCTR1;                      /*  THLPCTR1        */
     7612    union iodefine_reg32_t  THLPCTR2;                      /*  THLPCTR2        */
     7613    union iodefine_reg32_t  THLPCTR3;                      /*  THLPCTR3        */
     7614    union iodefine_reg32_t  THLPCTR4;                      /*  THLPCTR4        */
     7615   
     7616    volatile uint8_t   dummy176[12];                           /*                  */
     7617
     7618/* #define RSCAN0_GTINTSTS0_COUNT (2) */
     7619    union iodefine_reg32_t  GTINTSTS0;                     /*  GTINTSTS0       */
     7620    union iodefine_reg32_t  GTINTSTS1;                     /*  GTINTSTS1       */
     7621    union iodefine_reg32_t  GTSTCFG;                       /*  GTSTCFG         */
     7622    union iodefine_reg32_t  GTSTCTR;                       /*  GTSTCTR         */
     7623   
     7624    volatile uint8_t   dummy177[12];                           /*                  */
     7625    union iodefine_reg32_16_t  GLOCKK;                     /*  GLOCKK          */
     7626   
     7627    volatile uint8_t   dummy178[128];                          /*                  */
     7628   
     7629/* start of struct st_rscan_from_rscan0gaflidj */
     7630    union iodefine_reg32_t  GAFLID0;                       /*  GAFLID0         */
     7631    union iodefine_reg32_t  GAFLM0;                        /*  GAFLM0          */
     7632    union iodefine_reg32_t  GAFLP00;                       /*  GAFLP00         */
     7633    union iodefine_reg32_t  GAFLP10;                       /*  GAFLP10         */
     7634
     7635/* end of struct st_rscan_from_rscan0gaflidj */
     7636   
     7637/* start of struct st_rscan_from_rscan0gaflidj */
     7638    union iodefine_reg32_t  GAFLID1;                       /*  GAFLID1         */
     7639    union iodefine_reg32_t  GAFLM1;                        /*  GAFLM1          */
     7640    union iodefine_reg32_t  GAFLP01;                       /*  GAFLP01         */
     7641    union iodefine_reg32_t  GAFLP11;                       /*  GAFLP11         */
     7642
     7643/* end of struct st_rscan_from_rscan0gaflidj */
     7644   
     7645/* start of struct st_rscan_from_rscan0gaflidj */
     7646    union iodefine_reg32_t  GAFLID2;                       /*  GAFLID2         */
     7647    union iodefine_reg32_t  GAFLM2;                        /*  GAFLM2          */
     7648    union iodefine_reg32_t  GAFLP02;                       /*  GAFLP02         */
     7649    union iodefine_reg32_t  GAFLP12;                       /*  GAFLP12         */
     7650
     7651/* end of struct st_rscan_from_rscan0gaflidj */
     7652   
     7653/* start of struct st_rscan_from_rscan0gaflidj */
     7654    union iodefine_reg32_t  GAFLID3;                       /*  GAFLID3         */
     7655    union iodefine_reg32_t  GAFLM3;                        /*  GAFLM3          */
     7656    union iodefine_reg32_t  GAFLP03;                       /*  GAFLP03         */
     7657    union iodefine_reg32_t  GAFLP13;                       /*  GAFLP13         */
     7658
     7659/* end of struct st_rscan_from_rscan0gaflidj */
     7660   
     7661/* start of struct st_rscan_from_rscan0gaflidj */
     7662    union iodefine_reg32_t  GAFLID4;                       /*  GAFLID4         */
     7663    union iodefine_reg32_t  GAFLM4;                        /*  GAFLM4          */
     7664    union iodefine_reg32_t  GAFLP04;                       /*  GAFLP04         */
     7665    union iodefine_reg32_t  GAFLP14;                       /*  GAFLP14         */
     7666
     7667/* end of struct st_rscan_from_rscan0gaflidj */
     7668   
     7669/* start of struct st_rscan_from_rscan0gaflidj */
     7670    union iodefine_reg32_t  GAFLID5;                       /*  GAFLID5         */
     7671    union iodefine_reg32_t  GAFLM5;                        /*  GAFLM5          */
     7672    union iodefine_reg32_t  GAFLP05;                       /*  GAFLP05         */
     7673    union iodefine_reg32_t  GAFLP15;                       /*  GAFLP15         */
     7674
     7675/* end of struct st_rscan_from_rscan0gaflidj */
     7676   
     7677/* start of struct st_rscan_from_rscan0gaflidj */
     7678    union iodefine_reg32_t  GAFLID6;                       /*  GAFLID6         */
     7679    union iodefine_reg32_t  GAFLM6;                        /*  GAFLM6          */
     7680    union iodefine_reg32_t  GAFLP06;                       /*  GAFLP06         */
     7681    union iodefine_reg32_t  GAFLP16;                       /*  GAFLP16         */
     7682
     7683/* end of struct st_rscan_from_rscan0gaflidj */
     7684   
     7685/* start of struct st_rscan_from_rscan0gaflidj */
     7686    union iodefine_reg32_t  GAFLID7;                       /*  GAFLID7         */
     7687    union iodefine_reg32_t  GAFLM7;                        /*  GAFLM7          */
     7688    union iodefine_reg32_t  GAFLP07;                       /*  GAFLP07         */
     7689    union iodefine_reg32_t  GAFLP17;                       /*  GAFLP17         */
     7690
     7691/* end of struct st_rscan_from_rscan0gaflidj */
     7692   
     7693/* start of struct st_rscan_from_rscan0gaflidj */
     7694    union iodefine_reg32_t  GAFLID8;                       /*  GAFLID8         */
     7695    union iodefine_reg32_t  GAFLM8;                        /*  GAFLM8          */
     7696    union iodefine_reg32_t  GAFLP08;                       /*  GAFLP08         */
     7697    union iodefine_reg32_t  GAFLP18;                       /*  GAFLP18         */
     7698
     7699/* end of struct st_rscan_from_rscan0gaflidj */
     7700   
     7701/* start of struct st_rscan_from_rscan0gaflidj */
     7702    union iodefine_reg32_t  GAFLID9;                       /*  GAFLID9         */
     7703    union iodefine_reg32_t  GAFLM9;                        /*  GAFLM9          */
     7704    union iodefine_reg32_t  GAFLP09;                       /*  GAFLP09         */
     7705    union iodefine_reg32_t  GAFLP19;                       /*  GAFLP19         */
     7706
     7707/* end of struct st_rscan_from_rscan0gaflidj */
     7708   
     7709/* start of struct st_rscan_from_rscan0gaflidj */
     7710    union iodefine_reg32_t  GAFLID10;                      /*  GAFLID10        */
     7711    union iodefine_reg32_t  GAFLM10;                       /*  GAFLM10         */
     7712    union iodefine_reg32_t  GAFLP010;                      /*  GAFLP010        */
     7713    union iodefine_reg32_t  GAFLP110;                      /*  GAFLP110        */
     7714
     7715/* end of struct st_rscan_from_rscan0gaflidj */
     7716   
     7717/* start of struct st_rscan_from_rscan0gaflidj */
     7718    union iodefine_reg32_t  GAFLID11;                      /*  GAFLID11        */
     7719    union iodefine_reg32_t  GAFLM11;                       /*  GAFLM11         */
     7720    union iodefine_reg32_t  GAFLP011;                      /*  GAFLP011        */
     7721    union iodefine_reg32_t  GAFLP111;                      /*  GAFLP111        */
     7722
     7723/* end of struct st_rscan_from_rscan0gaflidj */
     7724   
     7725/* start of struct st_rscan_from_rscan0gaflidj */
     7726    union iodefine_reg32_t  GAFLID12;                      /*  GAFLID12        */
     7727    union iodefine_reg32_t  GAFLM12;                       /*  GAFLM12         */
     7728    union iodefine_reg32_t  GAFLP012;                      /*  GAFLP012        */
     7729    union iodefine_reg32_t  GAFLP112;                      /*  GAFLP112        */
     7730
     7731/* end of struct st_rscan_from_rscan0gaflidj */
     7732   
     7733/* start of struct st_rscan_from_rscan0gaflidj */
     7734    union iodefine_reg32_t  GAFLID13;                      /*  GAFLID13        */
     7735    union iodefine_reg32_t  GAFLM13;                       /*  GAFLM13         */
     7736    union iodefine_reg32_t  GAFLP013;                      /*  GAFLP013        */
     7737    union iodefine_reg32_t  GAFLP113;                      /*  GAFLP113        */
     7738
     7739/* end of struct st_rscan_from_rscan0gaflidj */
     7740   
     7741/* start of struct st_rscan_from_rscan0gaflidj */
     7742    union iodefine_reg32_t  GAFLID14;                      /*  GAFLID14        */
     7743    union iodefine_reg32_t  GAFLM14;                       /*  GAFLM14         */
     7744    union iodefine_reg32_t  GAFLP014;                      /*  GAFLP014        */
     7745    union iodefine_reg32_t  GAFLP114;                      /*  GAFLP114        */
     7746
     7747/* end of struct st_rscan_from_rscan0gaflidj */
     7748   
     7749/* start of struct st_rscan_from_rscan0gaflidj */
     7750    union iodefine_reg32_t  GAFLID15;                      /*  GAFLID15        */
     7751    union iodefine_reg32_t  GAFLM15;                       /*  GAFLM15         */
     7752    union iodefine_reg32_t  GAFLP015;                      /*  GAFLP015        */
     7753    union iodefine_reg32_t  GAFLP115;                      /*  GAFLP115        */
     7754
     7755/* end of struct st_rscan_from_rscan0gaflidj */
     7756   
     7757/* start of struct st_rscan_from_rscan0rmidp */
     7758    union iodefine_reg32_t  RMID0;                         /*  RMID0           */
     7759    union iodefine_reg32_t  RMPTR0;                        /*  RMPTR0          */
     7760    union iodefine_reg32_t  RMDF00;                        /*  RMDF00          */
     7761    union iodefine_reg32_t  RMDF10;                        /*  RMDF10          */
     7762
     7763/* end of struct st_rscan_from_rscan0rmidp */
     7764   
     7765/* start of struct st_rscan_from_rscan0rmidp */
     7766    union iodefine_reg32_t  RMID1;                         /*  RMID1           */
     7767    union iodefine_reg32_t  RMPTR1;                        /*  RMPTR1          */
     7768    union iodefine_reg32_t  RMDF01;                        /*  RMDF01          */
     7769    union iodefine_reg32_t  RMDF11;                        /*  RMDF11          */
     7770
     7771/* end of struct st_rscan_from_rscan0rmidp */
     7772   
     7773/* start of struct st_rscan_from_rscan0rmidp */
     7774    union iodefine_reg32_t  RMID2;                         /*  RMID2           */
     7775    union iodefine_reg32_t  RMPTR2;                        /*  RMPTR2          */
     7776    union iodefine_reg32_t  RMDF02;                        /*  RMDF02          */
     7777    union iodefine_reg32_t  RMDF12;                        /*  RMDF12          */
     7778
     7779/* end of struct st_rscan_from_rscan0rmidp */
     7780   
     7781/* start of struct st_rscan_from_rscan0rmidp */
     7782    union iodefine_reg32_t  RMID3;                         /*  RMID3           */
     7783    union iodefine_reg32_t  RMPTR3;                        /*  RMPTR3          */
     7784    union iodefine_reg32_t  RMDF03;                        /*  RMDF03          */
     7785    union iodefine_reg32_t  RMDF13;                        /*  RMDF13          */
     7786
     7787/* end of struct st_rscan_from_rscan0rmidp */
     7788   
     7789/* start of struct st_rscan_from_rscan0rmidp */
     7790    union iodefine_reg32_t  RMID4;                         /*  RMID4           */
     7791    union iodefine_reg32_t  RMPTR4;                        /*  RMPTR4          */
     7792    union iodefine_reg32_t  RMDF04;                        /*  RMDF04          */
     7793    union iodefine_reg32_t  RMDF14;                        /*  RMDF14          */
     7794
     7795/* end of struct st_rscan_from_rscan0rmidp */
     7796   
     7797/* start of struct st_rscan_from_rscan0rmidp */
     7798    union iodefine_reg32_t  RMID5;                         /*  RMID5           */
     7799    union iodefine_reg32_t  RMPTR5;                        /*  RMPTR5          */
     7800    union iodefine_reg32_t  RMDF05;                        /*  RMDF05          */
     7801    union iodefine_reg32_t  RMDF15;                        /*  RMDF15          */
     7802
     7803/* end of struct st_rscan_from_rscan0rmidp */
     7804   
     7805/* start of struct st_rscan_from_rscan0rmidp */
     7806    union iodefine_reg32_t  RMID6;                         /*  RMID6           */
     7807    union iodefine_reg32_t  RMPTR6;                        /*  RMPTR6          */
     7808    union iodefine_reg32_t  RMDF06;                        /*  RMDF06          */
     7809    union iodefine_reg32_t  RMDF16;                        /*  RMDF16          */
     7810
     7811/* end of struct st_rscan_from_rscan0rmidp */
     7812   
     7813/* start of struct st_rscan_from_rscan0rmidp */
     7814    union iodefine_reg32_t  RMID7;                         /*  RMID7           */
     7815    union iodefine_reg32_t  RMPTR7;                        /*  RMPTR7          */
     7816    union iodefine_reg32_t  RMDF07;                        /*  RMDF07          */
     7817    union iodefine_reg32_t  RMDF17;                        /*  RMDF17          */
     7818
     7819/* end of struct st_rscan_from_rscan0rmidp */
     7820   
     7821/* start of struct st_rscan_from_rscan0rmidp */
     7822    union iodefine_reg32_t  RMID8;                         /*  RMID8           */
     7823    union iodefine_reg32_t  RMPTR8;                        /*  RMPTR8          */
     7824    union iodefine_reg32_t  RMDF08;                        /*  RMDF08          */
     7825    union iodefine_reg32_t  RMDF18;                        /*  RMDF18          */
     7826
     7827/* end of struct st_rscan_from_rscan0rmidp */
     7828   
     7829/* start of struct st_rscan_from_rscan0rmidp */
     7830    union iodefine_reg32_t  RMID9;                         /*  RMID9           */
     7831    union iodefine_reg32_t  RMPTR9;                        /*  RMPTR9          */
     7832    union iodefine_reg32_t  RMDF09;                        /*  RMDF09          */
     7833    union iodefine_reg32_t  RMDF19;                        /*  RMDF19          */
     7834
     7835/* end of struct st_rscan_from_rscan0rmidp */
     7836   
     7837/* start of struct st_rscan_from_rscan0rmidp */
     7838    union iodefine_reg32_t  RMID10;                        /*  RMID10          */
     7839    union iodefine_reg32_t  RMPTR10;                       /*  RMPTR10         */
     7840    union iodefine_reg32_t  RMDF010;                       /*  RMDF010         */
     7841    union iodefine_reg32_t  RMDF110;                       /*  RMDF110         */
     7842
     7843/* end of struct st_rscan_from_rscan0rmidp */
     7844   
     7845/* start of struct st_rscan_from_rscan0rmidp */
     7846    union iodefine_reg32_t  RMID11;                        /*  RMID11          */
     7847    union iodefine_reg32_t  RMPTR11;                       /*  RMPTR11         */
     7848    union iodefine_reg32_t  RMDF011;                       /*  RMDF011         */
     7849    union iodefine_reg32_t  RMDF111;                       /*  RMDF111         */
     7850
     7851/* end of struct st_rscan_from_rscan0rmidp */
     7852   
     7853/* start of struct st_rscan_from_rscan0rmidp */
     7854    union iodefine_reg32_t  RMID12;                        /*  RMID12          */
     7855    union iodefine_reg32_t  RMPTR12;                       /*  RMPTR12         */
     7856    union iodefine_reg32_t  RMDF012;                       /*  RMDF012         */
     7857    union iodefine_reg32_t  RMDF112;                       /*  RMDF112         */
     7858
     7859/* end of struct st_rscan_from_rscan0rmidp */
     7860   
     7861/* start of struct st_rscan_from_rscan0rmidp */
     7862    union iodefine_reg32_t  RMID13;                        /*  RMID13          */
     7863    union iodefine_reg32_t  RMPTR13;                       /*  RMPTR13         */
     7864    union iodefine_reg32_t  RMDF013;                       /*  RMDF013         */
     7865    union iodefine_reg32_t  RMDF113;                       /*  RMDF113         */
     7866
     7867/* end of struct st_rscan_from_rscan0rmidp */
     7868   
     7869/* start of struct st_rscan_from_rscan0rmidp */
     7870    union iodefine_reg32_t  RMID14;                        /*  RMID14          */
     7871    union iodefine_reg32_t  RMPTR14;                       /*  RMPTR14         */
     7872    union iodefine_reg32_t  RMDF014;                       /*  RMDF014         */
     7873    union iodefine_reg32_t  RMDF114;                       /*  RMDF114         */
     7874
     7875/* end of struct st_rscan_from_rscan0rmidp */
     7876   
     7877/* start of struct st_rscan_from_rscan0rmidp */
     7878    union iodefine_reg32_t  RMID15;                        /*  RMID15          */
     7879    union iodefine_reg32_t  RMPTR15;                       /*  RMPTR15         */
     7880    union iodefine_reg32_t  RMDF015;                       /*  RMDF015         */
     7881    union iodefine_reg32_t  RMDF115;                       /*  RMDF115         */
     7882
     7883/* end of struct st_rscan_from_rscan0rmidp */
     7884   
     7885/* start of struct st_rscan_from_rscan0rmidp */
     7886    union iodefine_reg32_t  RMID16;                        /*  RMID16          */
     7887    union iodefine_reg32_t  RMPTR16;                       /*  RMPTR16         */
     7888    union iodefine_reg32_t  RMDF016;                       /*  RMDF016         */
     7889    union iodefine_reg32_t  RMDF116;                       /*  RMDF116         */
     7890
     7891/* end of struct st_rscan_from_rscan0rmidp */
     7892   
     7893/* start of struct st_rscan_from_rscan0rmidp */
     7894    union iodefine_reg32_t  RMID17;                        /*  RMID17          */
     7895    union iodefine_reg32_t  RMPTR17;                       /*  RMPTR17         */
     7896    union iodefine_reg32_t  RMDF017;                       /*  RMDF017         */
     7897    union iodefine_reg32_t  RMDF117;                       /*  RMDF117         */
     7898
     7899/* end of struct st_rscan_from_rscan0rmidp */
     7900   
     7901/* start of struct st_rscan_from_rscan0rmidp */
     7902    union iodefine_reg32_t  RMID18;                        /*  RMID18          */
     7903    union iodefine_reg32_t  RMPTR18;                       /*  RMPTR18         */
     7904    union iodefine_reg32_t  RMDF018;                       /*  RMDF018         */
     7905    union iodefine_reg32_t  RMDF118;                       /*  RMDF118         */
     7906
     7907/* end of struct st_rscan_from_rscan0rmidp */
     7908   
     7909/* start of struct st_rscan_from_rscan0rmidp */
     7910    union iodefine_reg32_t  RMID19;                        /*  RMID19          */
     7911    union iodefine_reg32_t  RMPTR19;                       /*  RMPTR19         */
     7912    union iodefine_reg32_t  RMDF019;                       /*  RMDF019         */
     7913    union iodefine_reg32_t  RMDF119;                       /*  RMDF119         */
     7914
     7915/* end of struct st_rscan_from_rscan0rmidp */
     7916   
     7917/* start of struct st_rscan_from_rscan0rmidp */
     7918    union iodefine_reg32_t  RMID20;                        /*  RMID20          */
     7919    union iodefine_reg32_t  RMPTR20;                       /*  RMPTR20         */
     7920    union iodefine_reg32_t  RMDF020;                       /*  RMDF020         */
     7921    union iodefine_reg32_t  RMDF120;                       /*  RMDF120         */
     7922
     7923/* end of struct st_rscan_from_rscan0rmidp */
     7924   
     7925/* start of struct st_rscan_from_rscan0rmidp */
     7926    union iodefine_reg32_t  RMID21;                        /*  RMID21          */
     7927    union iodefine_reg32_t  RMPTR21;                       /*  RMPTR21         */
     7928    union iodefine_reg32_t  RMDF021;                       /*  RMDF021         */
     7929    union iodefine_reg32_t  RMDF121;                       /*  RMDF121         */
     7930
     7931/* end of struct st_rscan_from_rscan0rmidp */
     7932   
     7933/* start of struct st_rscan_from_rscan0rmidp */
     7934    union iodefine_reg32_t  RMID22;                        /*  RMID22          */
     7935    union iodefine_reg32_t  RMPTR22;                       /*  RMPTR22         */
     7936    union iodefine_reg32_t  RMDF022;                       /*  RMDF022         */
     7937    union iodefine_reg32_t  RMDF122;                       /*  RMDF122         */
     7938
     7939/* end of struct st_rscan_from_rscan0rmidp */
     7940   
     7941/* start of struct st_rscan_from_rscan0rmidp */
     7942    union iodefine_reg32_t  RMID23;                        /*  RMID23          */
     7943    union iodefine_reg32_t  RMPTR23;                       /*  RMPTR23         */
     7944    union iodefine_reg32_t  RMDF023;                       /*  RMDF023         */
     7945    union iodefine_reg32_t  RMDF123;                       /*  RMDF123         */
     7946
     7947/* end of struct st_rscan_from_rscan0rmidp */
     7948   
     7949/* start of struct st_rscan_from_rscan0rmidp */
     7950    union iodefine_reg32_t  RMID24;                        /*  RMID24          */
     7951    union iodefine_reg32_t  RMPTR24;                       /*  RMPTR24         */
     7952    union iodefine_reg32_t  RMDF024;                       /*  RMDF024         */
     7953    union iodefine_reg32_t  RMDF124;                       /*  RMDF124         */
     7954
     7955/* end of struct st_rscan_from_rscan0rmidp */
     7956   
     7957/* start of struct st_rscan_from_rscan0rmidp */
     7958    union iodefine_reg32_t  RMID25;                        /*  RMID25          */
     7959    union iodefine_reg32_t  RMPTR25;                       /*  RMPTR25         */
     7960    union iodefine_reg32_t  RMDF025;                       /*  RMDF025         */
     7961    union iodefine_reg32_t  RMDF125;                       /*  RMDF125         */
     7962
     7963/* end of struct st_rscan_from_rscan0rmidp */
     7964   
     7965/* start of struct st_rscan_from_rscan0rmidp */
     7966    union iodefine_reg32_t  RMID26;                        /*  RMID26          */
     7967    union iodefine_reg32_t  RMPTR26;                       /*  RMPTR26         */
     7968    union iodefine_reg32_t  RMDF026;                       /*  RMDF026         */
     7969    union iodefine_reg32_t  RMDF126;                       /*  RMDF126         */
     7970
     7971/* end of struct st_rscan_from_rscan0rmidp */
     7972   
     7973/* start of struct st_rscan_from_rscan0rmidp */
     7974    union iodefine_reg32_t  RMID27;                        /*  RMID27          */
     7975    union iodefine_reg32_t  RMPTR27;                       /*  RMPTR27         */
     7976    union iodefine_reg32_t  RMDF027;                       /*  RMDF027         */
     7977    union iodefine_reg32_t  RMDF127;                       /*  RMDF127         */
     7978
     7979/* end of struct st_rscan_from_rscan0rmidp */
     7980   
     7981/* start of struct st_rscan_from_rscan0rmidp */
     7982    union iodefine_reg32_t  RMID28;                        /*  RMID28          */
     7983    union iodefine_reg32_t  RMPTR28;                       /*  RMPTR28         */
     7984    union iodefine_reg32_t  RMDF028;                       /*  RMDF028         */
     7985    union iodefine_reg32_t  RMDF128;                       /*  RMDF128         */
     7986
     7987/* end of struct st_rscan_from_rscan0rmidp */
     7988   
     7989/* start of struct st_rscan_from_rscan0rmidp */
     7990    union iodefine_reg32_t  RMID29;                        /*  RMID29          */
     7991    union iodefine_reg32_t  RMPTR29;                       /*  RMPTR29         */
     7992    union iodefine_reg32_t  RMDF029;                       /*  RMDF029         */
     7993    union iodefine_reg32_t  RMDF129;                       /*  RMDF129         */
     7994
     7995/* end of struct st_rscan_from_rscan0rmidp */
     7996   
     7997/* start of struct st_rscan_from_rscan0rmidp */
     7998    union iodefine_reg32_t  RMID30;                        /*  RMID30          */
     7999    union iodefine_reg32_t  RMPTR30;                       /*  RMPTR30         */
     8000    union iodefine_reg32_t  RMDF030;                       /*  RMDF030         */
     8001    union iodefine_reg32_t  RMDF130;                       /*  RMDF130         */
     8002
     8003/* end of struct st_rscan_from_rscan0rmidp */
     8004   
     8005/* start of struct st_rscan_from_rscan0rmidp */
     8006    union iodefine_reg32_t  RMID31;                        /*  RMID31          */
     8007    union iodefine_reg32_t  RMPTR31;                       /*  RMPTR31         */
     8008    union iodefine_reg32_t  RMDF031;                       /*  RMDF031         */
     8009    union iodefine_reg32_t  RMDF131;                       /*  RMDF131         */
     8010
     8011/* end of struct st_rscan_from_rscan0rmidp */
     8012   
     8013/* start of struct st_rscan_from_rscan0rmidp */
     8014    union iodefine_reg32_t  RMID32;                        /*  RMID32          */
     8015    union iodefine_reg32_t  RMPTR32;                       /*  RMPTR32         */
     8016    union iodefine_reg32_t  RMDF032;                       /*  RMDF032         */
     8017    union iodefine_reg32_t  RMDF132;                       /*  RMDF132         */
     8018
     8019/* end of struct st_rscan_from_rscan0rmidp */
     8020   
     8021/* start of struct st_rscan_from_rscan0rmidp */
     8022    union iodefine_reg32_t  RMID33;                        /*  RMID33          */
     8023    union iodefine_reg32_t  RMPTR33;                       /*  RMPTR33         */
     8024    union iodefine_reg32_t  RMDF033;                       /*  RMDF033         */
     8025    union iodefine_reg32_t  RMDF133;                       /*  RMDF133         */
     8026
     8027/* end of struct st_rscan_from_rscan0rmidp */
     8028   
     8029/* start of struct st_rscan_from_rscan0rmidp */
     8030    union iodefine_reg32_t  RMID34;                        /*  RMID34          */
     8031    union iodefine_reg32_t  RMPTR34;                       /*  RMPTR34         */
     8032    union iodefine_reg32_t  RMDF034;                       /*  RMDF034         */
     8033    union iodefine_reg32_t  RMDF134;                       /*  RMDF134         */
     8034
     8035/* end of struct st_rscan_from_rscan0rmidp */
     8036   
     8037/* start of struct st_rscan_from_rscan0rmidp */
     8038    union iodefine_reg32_t  RMID35;                        /*  RMID35          */
     8039    union iodefine_reg32_t  RMPTR35;                       /*  RMPTR35         */
     8040    union iodefine_reg32_t  RMDF035;                       /*  RMDF035         */
     8041    union iodefine_reg32_t  RMDF135;                       /*  RMDF135         */
     8042
     8043/* end of struct st_rscan_from_rscan0rmidp */
     8044   
     8045/* start of struct st_rscan_from_rscan0rmidp */
     8046    union iodefine_reg32_t  RMID36;                        /*  RMID36          */
     8047    union iodefine_reg32_t  RMPTR36;                       /*  RMPTR36         */
     8048    union iodefine_reg32_t  RMDF036;                       /*  RMDF036         */
     8049    union iodefine_reg32_t  RMDF136;                       /*  RMDF136         */
     8050
     8051/* end of struct st_rscan_from_rscan0rmidp */
     8052   
     8053/* start of struct st_rscan_from_rscan0rmidp */
     8054    union iodefine_reg32_t  RMID37;                        /*  RMID37          */
     8055    union iodefine_reg32_t  RMPTR37;                       /*  RMPTR37         */
     8056    union iodefine_reg32_t  RMDF037;                       /*  RMDF037         */
     8057    union iodefine_reg32_t  RMDF137;                       /*  RMDF137         */
     8058
     8059/* end of struct st_rscan_from_rscan0rmidp */
     8060   
     8061/* start of struct st_rscan_from_rscan0rmidp */
     8062    union iodefine_reg32_t  RMID38;                        /*  RMID38          */
     8063    union iodefine_reg32_t  RMPTR38;                       /*  RMPTR38         */
     8064    union iodefine_reg32_t  RMDF038;                       /*  RMDF038         */
     8065    union iodefine_reg32_t  RMDF138;                       /*  RMDF138         */
     8066
     8067/* end of struct st_rscan_from_rscan0rmidp */
     8068   
     8069/* start of struct st_rscan_from_rscan0rmidp */
     8070    union iodefine_reg32_t  RMID39;                        /*  RMID39          */
     8071    union iodefine_reg32_t  RMPTR39;                       /*  RMPTR39         */
     8072    union iodefine_reg32_t  RMDF039;                       /*  RMDF039         */
     8073    union iodefine_reg32_t  RMDF139;                       /*  RMDF139         */
     8074
     8075/* end of struct st_rscan_from_rscan0rmidp */
     8076   
     8077/* start of struct st_rscan_from_rscan0rmidp */
     8078    union iodefine_reg32_t  RMID40;                        /*  RMID40          */
     8079    union iodefine_reg32_t  RMPTR40;                       /*  RMPTR40         */
     8080    union iodefine_reg32_t  RMDF040;                       /*  RMDF040         */
     8081    union iodefine_reg32_t  RMDF140;                       /*  RMDF140         */
     8082
     8083/* end of struct st_rscan_from_rscan0rmidp */
     8084   
     8085/* start of struct st_rscan_from_rscan0rmidp */
     8086    union iodefine_reg32_t  RMID41;                        /*  RMID41          */
     8087    union iodefine_reg32_t  RMPTR41;                       /*  RMPTR41         */
     8088    union iodefine_reg32_t  RMDF041;                       /*  RMDF041         */
     8089    union iodefine_reg32_t  RMDF141;                       /*  RMDF141         */
     8090
     8091/* end of struct st_rscan_from_rscan0rmidp */
     8092   
     8093/* start of struct st_rscan_from_rscan0rmidp */
     8094    union iodefine_reg32_t  RMID42;                        /*  RMID42          */
     8095    union iodefine_reg32_t  RMPTR42;                       /*  RMPTR42         */
     8096    union iodefine_reg32_t  RMDF042;                       /*  RMDF042         */
     8097    union iodefine_reg32_t  RMDF142;                       /*  RMDF142         */
     8098
     8099/* end of struct st_rscan_from_rscan0rmidp */
     8100   
     8101/* start of struct st_rscan_from_rscan0rmidp */
     8102    union iodefine_reg32_t  RMID43;                        /*  RMID43          */
     8103    union iodefine_reg32_t  RMPTR43;                       /*  RMPTR43         */
     8104    union iodefine_reg32_t  RMDF043;                       /*  RMDF043         */
     8105    union iodefine_reg32_t  RMDF143;                       /*  RMDF143         */
     8106
     8107/* end of struct st_rscan_from_rscan0rmidp */
     8108   
     8109/* start of struct st_rscan_from_rscan0rmidp */
     8110    union iodefine_reg32_t  RMID44;                        /*  RMID44          */
     8111    union iodefine_reg32_t  RMPTR44;                       /*  RMPTR44         */
     8112    union iodefine_reg32_t  RMDF044;                       /*  RMDF044         */
     8113    union iodefine_reg32_t  RMDF144;                       /*  RMDF144         */
     8114
     8115/* end of struct st_rscan_from_rscan0rmidp */
     8116   
     8117/* start of struct st_rscan_from_rscan0rmidp */
     8118    union iodefine_reg32_t  RMID45;                        /*  RMID45          */
     8119    union iodefine_reg32_t  RMPTR45;                       /*  RMPTR45         */
     8120    union iodefine_reg32_t  RMDF045;                       /*  RMDF045         */
     8121    union iodefine_reg32_t  RMDF145;                       /*  RMDF145         */
     8122
     8123/* end of struct st_rscan_from_rscan0rmidp */
     8124   
     8125/* start of struct st_rscan_from_rscan0rmidp */
     8126    union iodefine_reg32_t  RMID46;                        /*  RMID46          */
     8127    union iodefine_reg32_t  RMPTR46;                       /*  RMPTR46         */
     8128    union iodefine_reg32_t  RMDF046;                       /*  RMDF046         */
     8129    union iodefine_reg32_t  RMDF146;                       /*  RMDF146         */
     8130
     8131/* end of struct st_rscan_from_rscan0rmidp */
     8132   
     8133/* start of struct st_rscan_from_rscan0rmidp */
     8134    union iodefine_reg32_t  RMID47;                        /*  RMID47          */
     8135    union iodefine_reg32_t  RMPTR47;                       /*  RMPTR47         */
     8136    union iodefine_reg32_t  RMDF047;                       /*  RMDF047         */
     8137    union iodefine_reg32_t  RMDF147;                       /*  RMDF147         */
     8138
     8139/* end of struct st_rscan_from_rscan0rmidp */
     8140   
     8141/* start of struct st_rscan_from_rscan0rmidp */
     8142    union iodefine_reg32_t  RMID48;                        /*  RMID48          */
     8143    union iodefine_reg32_t  RMPTR48;                       /*  RMPTR48         */
     8144    union iodefine_reg32_t  RMDF048;                       /*  RMDF048         */
     8145    union iodefine_reg32_t  RMDF148;                       /*  RMDF148         */
     8146
     8147/* end of struct st_rscan_from_rscan0rmidp */
     8148   
     8149/* start of struct st_rscan_from_rscan0rmidp */
     8150    union iodefine_reg32_t  RMID49;                        /*  RMID49          */
     8151    union iodefine_reg32_t  RMPTR49;                       /*  RMPTR49         */
     8152    union iodefine_reg32_t  RMDF049;                       /*  RMDF049         */
     8153    union iodefine_reg32_t  RMDF149;                       /*  RMDF149         */
     8154
     8155/* end of struct st_rscan_from_rscan0rmidp */
     8156   
     8157/* start of struct st_rscan_from_rscan0rmidp */
     8158    union iodefine_reg32_t  RMID50;                        /*  RMID50          */
     8159    union iodefine_reg32_t  RMPTR50;                       /*  RMPTR50         */
     8160    union iodefine_reg32_t  RMDF050;                       /*  RMDF050         */
     8161    union iodefine_reg32_t  RMDF150;                       /*  RMDF150         */
     8162
     8163/* end of struct st_rscan_from_rscan0rmidp */
     8164   
     8165/* start of struct st_rscan_from_rscan0rmidp */
     8166    union iodefine_reg32_t  RMID51;                        /*  RMID51          */
     8167    union iodefine_reg32_t  RMPTR51;                       /*  RMPTR51         */
     8168    union iodefine_reg32_t  RMDF051;                       /*  RMDF051         */
     8169    union iodefine_reg32_t  RMDF151;                       /*  RMDF151         */
     8170
     8171/* end of struct st_rscan_from_rscan0rmidp */
     8172   
     8173/* start of struct st_rscan_from_rscan0rmidp */
     8174    union iodefine_reg32_t  RMID52;                        /*  RMID52          */
     8175    union iodefine_reg32_t  RMPTR52;                       /*  RMPTR52         */
     8176    union iodefine_reg32_t  RMDF052;                       /*  RMDF052         */
     8177    union iodefine_reg32_t  RMDF152;                       /*  RMDF152         */
     8178
     8179/* end of struct st_rscan_from_rscan0rmidp */
     8180   
     8181/* start of struct st_rscan_from_rscan0rmidp */
     8182    union iodefine_reg32_t  RMID53;                        /*  RMID53          */
     8183    union iodefine_reg32_t  RMPTR53;                       /*  RMPTR53         */
     8184    union iodefine_reg32_t  RMDF053;                       /*  RMDF053         */
     8185    union iodefine_reg32_t  RMDF153;                       /*  RMDF153         */
     8186
     8187/* end of struct st_rscan_from_rscan0rmidp */
     8188   
     8189/* start of struct st_rscan_from_rscan0rmidp */
     8190    union iodefine_reg32_t  RMID54;                        /*  RMID54          */
     8191    union iodefine_reg32_t  RMPTR54;                       /*  RMPTR54         */
     8192    union iodefine_reg32_t  RMDF054;                       /*  RMDF054         */
     8193    union iodefine_reg32_t  RMDF154;                       /*  RMDF154         */
     8194
     8195/* end of struct st_rscan_from_rscan0rmidp */
     8196   
     8197/* start of struct st_rscan_from_rscan0rmidp */
     8198    union iodefine_reg32_t  RMID55;                        /*  RMID55          */
     8199    union iodefine_reg32_t  RMPTR55;                       /*  RMPTR55         */
     8200    union iodefine_reg32_t  RMDF055;                       /*  RMDF055         */
     8201    union iodefine_reg32_t  RMDF155;                       /*  RMDF155         */
     8202
     8203/* end of struct st_rscan_from_rscan0rmidp */
     8204   
     8205/* start of struct st_rscan_from_rscan0rmidp */
     8206    union iodefine_reg32_t  RMID56;                        /*  RMID56          */
     8207    union iodefine_reg32_t  RMPTR56;                       /*  RMPTR56         */
     8208    union iodefine_reg32_t  RMDF056;                       /*  RMDF056         */
     8209    union iodefine_reg32_t  RMDF156;                       /*  RMDF156         */
     8210
     8211/* end of struct st_rscan_from_rscan0rmidp */
     8212   
     8213/* start of struct st_rscan_from_rscan0rmidp */
     8214    union iodefine_reg32_t  RMID57;                        /*  RMID57          */
     8215    union iodefine_reg32_t  RMPTR57;                       /*  RMPTR57         */
     8216    union iodefine_reg32_t  RMDF057;                       /*  RMDF057         */
     8217    union iodefine_reg32_t  RMDF157;                       /*  RMDF157         */
     8218
     8219/* end of struct st_rscan_from_rscan0rmidp */
     8220   
     8221/* start of struct st_rscan_from_rscan0rmidp */
     8222    union iodefine_reg32_t  RMID58;                        /*  RMID58          */
     8223    union iodefine_reg32_t  RMPTR58;                       /*  RMPTR58         */
     8224    union iodefine_reg32_t  RMDF058;                       /*  RMDF058         */
     8225    union iodefine_reg32_t  RMDF158;                       /*  RMDF158         */
     8226
     8227/* end of struct st_rscan_from_rscan0rmidp */
     8228   
     8229/* start of struct st_rscan_from_rscan0rmidp */
     8230    union iodefine_reg32_t  RMID59;                        /*  RMID59          */
     8231    union iodefine_reg32_t  RMPTR59;                       /*  RMPTR59         */
     8232    union iodefine_reg32_t  RMDF059;                       /*  RMDF059         */
     8233    union iodefine_reg32_t  RMDF159;                       /*  RMDF159         */
     8234
     8235/* end of struct st_rscan_from_rscan0rmidp */
     8236   
     8237/* start of struct st_rscan_from_rscan0rmidp */
     8238    union iodefine_reg32_t  RMID60;                        /*  RMID60          */
     8239    union iodefine_reg32_t  RMPTR60;                       /*  RMPTR60         */
     8240    union iodefine_reg32_t  RMDF060;                       /*  RMDF060         */
     8241    union iodefine_reg32_t  RMDF160;                       /*  RMDF160         */
     8242
     8243/* end of struct st_rscan_from_rscan0rmidp */
     8244   
     8245/* start of struct st_rscan_from_rscan0rmidp */
     8246    union iodefine_reg32_t  RMID61;                        /*  RMID61          */
     8247    union iodefine_reg32_t  RMPTR61;                       /*  RMPTR61         */
     8248    union iodefine_reg32_t  RMDF061;                       /*  RMDF061         */
     8249    union iodefine_reg32_t  RMDF161;                       /*  RMDF161         */
     8250
     8251/* end of struct st_rscan_from_rscan0rmidp */
     8252   
     8253/* start of struct st_rscan_from_rscan0rmidp */
     8254    union iodefine_reg32_t  RMID62;                        /*  RMID62          */
     8255    union iodefine_reg32_t  RMPTR62;                       /*  RMPTR62         */
     8256    union iodefine_reg32_t  RMDF062;                       /*  RMDF062         */
     8257    union iodefine_reg32_t  RMDF162;                       /*  RMDF162         */
     8258
     8259/* end of struct st_rscan_from_rscan0rmidp */
     8260   
     8261/* start of struct st_rscan_from_rscan0rmidp */
     8262    union iodefine_reg32_t  RMID63;                        /*  RMID63          */
     8263    union iodefine_reg32_t  RMPTR63;                       /*  RMPTR63         */
     8264    union iodefine_reg32_t  RMDF063;                       /*  RMDF063         */
     8265    union iodefine_reg32_t  RMDF163;                       /*  RMDF163         */
     8266
     8267/* end of struct st_rscan_from_rscan0rmidp */
     8268   
     8269/* start of struct st_rscan_from_rscan0rmidp */
     8270    union iodefine_reg32_t  RMID64;                        /*  RMID64          */
     8271    union iodefine_reg32_t  RMPTR64;                       /*  RMPTR64         */
     8272    union iodefine_reg32_t  RMDF064;                       /*  RMDF064         */
     8273    union iodefine_reg32_t  RMDF164;                       /*  RMDF164         */
     8274
     8275/* end of struct st_rscan_from_rscan0rmidp */
     8276   
     8277/* start of struct st_rscan_from_rscan0rmidp */
     8278    union iodefine_reg32_t  RMID65;                        /*  RMID65          */
     8279    union iodefine_reg32_t  RMPTR65;                       /*  RMPTR65         */
     8280    union iodefine_reg32_t  RMDF065;                       /*  RMDF065         */
     8281    union iodefine_reg32_t  RMDF165;                       /*  RMDF165         */
     8282
     8283/* end of struct st_rscan_from_rscan0rmidp */
     8284   
     8285/* start of struct st_rscan_from_rscan0rmidp */
     8286    union iodefine_reg32_t  RMID66;                        /*  RMID66          */
     8287    union iodefine_reg32_t  RMPTR66;                       /*  RMPTR66         */
     8288    union iodefine_reg32_t  RMDF066;                       /*  RMDF066         */
     8289    union iodefine_reg32_t  RMDF166;                       /*  RMDF166         */
     8290
     8291/* end of struct st_rscan_from_rscan0rmidp */
     8292   
     8293/* start of struct st_rscan_from_rscan0rmidp */
     8294    union iodefine_reg32_t  RMID67;                        /*  RMID67          */
     8295    union iodefine_reg32_t  RMPTR67;                       /*  RMPTR67         */
     8296    union iodefine_reg32_t  RMDF067;                       /*  RMDF067         */
     8297    union iodefine_reg32_t  RMDF167;                       /*  RMDF167         */
     8298
     8299/* end of struct st_rscan_from_rscan0rmidp */
     8300   
     8301/* start of struct st_rscan_from_rscan0rmidp */
     8302    union iodefine_reg32_t  RMID68;                        /*  RMID68          */
     8303    union iodefine_reg32_t  RMPTR68;                       /*  RMPTR68         */
     8304    union iodefine_reg32_t  RMDF068;                       /*  RMDF068         */
     8305    union iodefine_reg32_t  RMDF168;                       /*  RMDF168         */
     8306
     8307/* end of struct st_rscan_from_rscan0rmidp */
     8308   
     8309/* start of struct st_rscan_from_rscan0rmidp */
     8310    union iodefine_reg32_t  RMID69;                        /*  RMID69          */
     8311    union iodefine_reg32_t  RMPTR69;                       /*  RMPTR69         */
     8312    union iodefine_reg32_t  RMDF069;                       /*  RMDF069         */
     8313    union iodefine_reg32_t  RMDF169;                       /*  RMDF169         */
     8314
     8315/* end of struct st_rscan_from_rscan0rmidp */
     8316   
     8317/* start of struct st_rscan_from_rscan0rmidp */
     8318    union iodefine_reg32_t  RMID70;                        /*  RMID70          */
     8319    union iodefine_reg32_t  RMPTR70;                       /*  RMPTR70         */
     8320    union iodefine_reg32_t  RMDF070;                       /*  RMDF070         */
     8321    union iodefine_reg32_t  RMDF170;                       /*  RMDF170         */
     8322
     8323/* end of struct st_rscan_from_rscan0rmidp */
     8324   
     8325/* start of struct st_rscan_from_rscan0rmidp */
     8326    union iodefine_reg32_t  RMID71;                        /*  RMID71          */
     8327    union iodefine_reg32_t  RMPTR71;                       /*  RMPTR71         */
     8328    union iodefine_reg32_t  RMDF071;                       /*  RMDF071         */
     8329    union iodefine_reg32_t  RMDF171;                       /*  RMDF171         */
     8330
     8331/* end of struct st_rscan_from_rscan0rmidp */
     8332   
     8333/* start of struct st_rscan_from_rscan0rmidp */
     8334    union iodefine_reg32_t  RMID72;                        /*  RMID72          */
     8335    union iodefine_reg32_t  RMPTR72;                       /*  RMPTR72         */
     8336    union iodefine_reg32_t  RMDF072;                       /*  RMDF072         */
     8337    union iodefine_reg32_t  RMDF172;                       /*  RMDF172         */
     8338
     8339/* end of struct st_rscan_from_rscan0rmidp */
     8340   
     8341/* start of struct st_rscan_from_rscan0rmidp */
     8342    union iodefine_reg32_t  RMID73;                        /*  RMID73          */
     8343    union iodefine_reg32_t  RMPTR73;                       /*  RMPTR73         */
     8344    union iodefine_reg32_t  RMDF073;                       /*  RMDF073         */
     8345    union iodefine_reg32_t  RMDF173;                       /*  RMDF173         */
     8346
     8347/* end of struct st_rscan_from_rscan0rmidp */
     8348   
     8349/* start of struct st_rscan_from_rscan0rmidp */
     8350    union iodefine_reg32_t  RMID74;                        /*  RMID74          */
     8351    union iodefine_reg32_t  RMPTR74;                       /*  RMPTR74         */
     8352    union iodefine_reg32_t  RMDF074;                       /*  RMDF074         */
     8353    union iodefine_reg32_t  RMDF174;                       /*  RMDF174         */
     8354
     8355/* end of struct st_rscan_from_rscan0rmidp */
     8356   
     8357/* start of struct st_rscan_from_rscan0rmidp */
     8358    union iodefine_reg32_t  RMID75;                        /*  RMID75          */
     8359    union iodefine_reg32_t  RMPTR75;                       /*  RMPTR75         */
     8360    union iodefine_reg32_t  RMDF075;                       /*  RMDF075         */
     8361    union iodefine_reg32_t  RMDF175;                       /*  RMDF175         */
     8362
     8363/* end of struct st_rscan_from_rscan0rmidp */
     8364   
     8365/* start of struct st_rscan_from_rscan0rmidp */
     8366    union iodefine_reg32_t  RMID76;                        /*  RMID76          */
     8367    union iodefine_reg32_t  RMPTR76;                       /*  RMPTR76         */
     8368    union iodefine_reg32_t  RMDF076;                       /*  RMDF076         */
     8369    union iodefine_reg32_t  RMDF176;                       /*  RMDF176         */
     8370
     8371/* end of struct st_rscan_from_rscan0rmidp */
     8372   
     8373/* start of struct st_rscan_from_rscan0rmidp */
     8374    union iodefine_reg32_t  RMID77;                        /*  RMID77          */
     8375    union iodefine_reg32_t  RMPTR77;                       /*  RMPTR77         */
     8376    union iodefine_reg32_t  RMDF077;                       /*  RMDF077         */
     8377    union iodefine_reg32_t  RMDF177;                       /*  RMDF177         */
     8378
     8379/* end of struct st_rscan_from_rscan0rmidp */
     8380   
     8381/* start of struct st_rscan_from_rscan0rmidp */
     8382    union iodefine_reg32_t  RMID78;                        /*  RMID78          */
     8383    union iodefine_reg32_t  RMPTR78;                       /*  RMPTR78         */
     8384    union iodefine_reg32_t  RMDF078;                       /*  RMDF078         */
     8385    union iodefine_reg32_t  RMDF178;                       /*  RMDF178         */
     8386
     8387/* end of struct st_rscan_from_rscan0rmidp */
     8388   
     8389/* start of struct st_rscan_from_rscan0rmidp */
     8390    union iodefine_reg32_t  RMID79;                        /*  RMID79          */
     8391    union iodefine_reg32_t  RMPTR79;                       /*  RMPTR79         */
     8392    union iodefine_reg32_t  RMDF079;                       /*  RMDF079         */
     8393    union iodefine_reg32_t  RMDF179;                       /*  RMDF179         */
     8394
     8395/* end of struct st_rscan_from_rscan0rmidp */
     8396   
     8397    volatile uint8_t   dummy179[768];                          /*                  */
     8398   
     8399/* start of struct st_rscan_from_rscan0rfidm */
     8400    union iodefine_reg32_t  RFID0;                         /*  RFID0           */
     8401    union iodefine_reg32_t  RFPTR0;                        /*  RFPTR0          */
     8402    union iodefine_reg32_t  RFDF00;                        /*  RFDF00          */
     8403    union iodefine_reg32_t  RFDF10;                        /*  RFDF10          */
     8404
     8405/* end of struct st_rscan_from_rscan0rfidm */
     8406   
     8407/* start of struct st_rscan_from_rscan0rfidm */
     8408    union iodefine_reg32_t  RFID1;                         /*  RFID1           */
     8409    union iodefine_reg32_t  RFPTR1;                        /*  RFPTR1          */
     8410    union iodefine_reg32_t  RFDF01;                        /*  RFDF01          */
     8411    union iodefine_reg32_t  RFDF11;                        /*  RFDF11          */
     8412
     8413/* end of struct st_rscan_from_rscan0rfidm */
     8414   
     8415/* start of struct st_rscan_from_rscan0rfidm */
     8416    union iodefine_reg32_t  RFID2;                         /*  RFID2           */
     8417    union iodefine_reg32_t  RFPTR2;                        /*  RFPTR2          */
     8418    union iodefine_reg32_t  RFDF02;                        /*  RFDF02          */
     8419    union iodefine_reg32_t  RFDF12;                        /*  RFDF12          */
     8420
     8421/* end of struct st_rscan_from_rscan0rfidm */
     8422   
     8423/* start of struct st_rscan_from_rscan0rfidm */
     8424    union iodefine_reg32_t  RFID3;                         /*  RFID3           */
     8425    union iodefine_reg32_t  RFPTR3;                        /*  RFPTR3          */
     8426    union iodefine_reg32_t  RFDF03;                        /*  RFDF03          */
     8427    union iodefine_reg32_t  RFDF13;                        /*  RFDF13          */
     8428
     8429/* end of struct st_rscan_from_rscan0rfidm */
     8430   
     8431/* start of struct st_rscan_from_rscan0rfidm */
     8432    union iodefine_reg32_t  RFID4;                         /*  RFID4           */
     8433    union iodefine_reg32_t  RFPTR4;                        /*  RFPTR4          */
     8434    union iodefine_reg32_t  RFDF04;                        /*  RFDF04          */
     8435    union iodefine_reg32_t  RFDF14;                        /*  RFDF14          */
     8436
     8437/* end of struct st_rscan_from_rscan0rfidm */
     8438   
     8439/* start of struct st_rscan_from_rscan0rfidm */
     8440    union iodefine_reg32_t  RFID5;                         /*  RFID5           */
     8441    union iodefine_reg32_t  RFPTR5;                        /*  RFPTR5          */
     8442    union iodefine_reg32_t  RFDF05;                        /*  RFDF05          */
     8443    union iodefine_reg32_t  RFDF15;                        /*  RFDF15          */
     8444
     8445/* end of struct st_rscan_from_rscan0rfidm */
     8446   
     8447/* start of struct st_rscan_from_rscan0rfidm */
     8448    union iodefine_reg32_t  RFID6;                         /*  RFID6           */
     8449    union iodefine_reg32_t  RFPTR6;                        /*  RFPTR6          */
     8450    union iodefine_reg32_t  RFDF06;                        /*  RFDF06          */
     8451    union iodefine_reg32_t  RFDF16;                        /*  RFDF16          */
     8452
     8453/* end of struct st_rscan_from_rscan0rfidm */
     8454   
     8455/* start of struct st_rscan_from_rscan0rfidm */
     8456    union iodefine_reg32_t  RFID7;                         /*  RFID7           */
     8457    union iodefine_reg32_t  RFPTR7;                        /*  RFPTR7          */
     8458    union iodefine_reg32_t  RFDF07;                        /*  RFDF07          */
     8459    union iodefine_reg32_t  RFDF17;                        /*  RFDF17          */
     8460
     8461/* end of struct st_rscan_from_rscan0rfidm */
     8462   
     8463/* start of struct st_rscan_from_rscan0cfidm */
     8464    union iodefine_reg32_t  CFID0;                         /*  CFID0           */
     8465    union iodefine_reg32_t  CFPTR0;                        /*  CFPTR0          */
     8466    union iodefine_reg32_t  CFDF00;                        /*  CFDF00          */
     8467    union iodefine_reg32_t  CFDF10;                        /*  CFDF10          */
     8468
     8469/* end of struct st_rscan_from_rscan0cfidm */
     8470   
     8471/* start of struct st_rscan_from_rscan0cfidm */
     8472    union iodefine_reg32_t  CFID1;                         /*  CFID1           */
     8473    union iodefine_reg32_t  CFPTR1;                        /*  CFPTR1          */
     8474    union iodefine_reg32_t  CFDF01;                        /*  CFDF01          */
     8475    union iodefine_reg32_t  CFDF11;                        /*  CFDF11          */
     8476
     8477/* end of struct st_rscan_from_rscan0cfidm */
     8478   
     8479/* start of struct st_rscan_from_rscan0cfidm */
     8480    union iodefine_reg32_t  CFID2;                         /*  CFID2           */
     8481    union iodefine_reg32_t  CFPTR2;                        /*  CFPTR2          */
     8482    union iodefine_reg32_t  CFDF02;                        /*  CFDF02          */
     8483    union iodefine_reg32_t  CFDF12;                        /*  CFDF12          */
     8484
     8485/* end of struct st_rscan_from_rscan0cfidm */
     8486   
     8487/* start of struct st_rscan_from_rscan0cfidm */
     8488    union iodefine_reg32_t  CFID3;                         /*  CFID3           */
     8489    union iodefine_reg32_t  CFPTR3;                        /*  CFPTR3          */
     8490    union iodefine_reg32_t  CFDF03;                        /*  CFDF03          */
     8491    union iodefine_reg32_t  CFDF13;                        /*  CFDF13          */
     8492
     8493/* end of struct st_rscan_from_rscan0cfidm */
     8494   
     8495/* start of struct st_rscan_from_rscan0cfidm */
     8496    union iodefine_reg32_t  CFID4;                         /*  CFID4           */
     8497    union iodefine_reg32_t  CFPTR4;                        /*  CFPTR4          */
     8498    union iodefine_reg32_t  CFDF04;                        /*  CFDF04          */
     8499    union iodefine_reg32_t  CFDF14;                        /*  CFDF14          */
     8500
     8501/* end of struct st_rscan_from_rscan0cfidm */
     8502   
     8503/* start of struct st_rscan_from_rscan0cfidm */
     8504    union iodefine_reg32_t  CFID5;                         /*  CFID5           */
     8505    union iodefine_reg32_t  CFPTR5;                        /*  CFPTR5          */
     8506    union iodefine_reg32_t  CFDF05;                        /*  CFDF05          */
     8507    union iodefine_reg32_t  CFDF15;                        /*  CFDF15          */
     8508
     8509/* end of struct st_rscan_from_rscan0cfidm */
     8510   
     8511/* start of struct st_rscan_from_rscan0cfidm */
     8512    union iodefine_reg32_t  CFID6;                         /*  CFID6           */
     8513    union iodefine_reg32_t  CFPTR6;                        /*  CFPTR6          */
     8514    union iodefine_reg32_t  CFDF06;                        /*  CFDF06          */
     8515    union iodefine_reg32_t  CFDF16;                        /*  CFDF16          */
     8516
     8517/* end of struct st_rscan_from_rscan0cfidm */
     8518   
     8519/* start of struct st_rscan_from_rscan0cfidm */
     8520    union iodefine_reg32_t  CFID7;                         /*  CFID7           */
     8521    union iodefine_reg32_t  CFPTR7;                        /*  CFPTR7          */
     8522    union iodefine_reg32_t  CFDF07;                        /*  CFDF07          */
     8523    union iodefine_reg32_t  CFDF17;                        /*  CFDF17          */
     8524
     8525/* end of struct st_rscan_from_rscan0cfidm */
     8526   
     8527/* start of struct st_rscan_from_rscan0cfidm */
     8528    union iodefine_reg32_t  CFID8;                         /*  CFID8           */
     8529    union iodefine_reg32_t  CFPTR8;                        /*  CFPTR8          */
     8530    union iodefine_reg32_t  CFDF08;                        /*  CFDF08          */
     8531    union iodefine_reg32_t  CFDF18;                        /*  CFDF18          */
     8532
     8533/* end of struct st_rscan_from_rscan0cfidm */
     8534   
     8535/* start of struct st_rscan_from_rscan0cfidm */
     8536    union iodefine_reg32_t  CFID9;                         /*  CFID9           */
     8537    union iodefine_reg32_t  CFPTR9;                        /*  CFPTR9          */
     8538    union iodefine_reg32_t  CFDF09;                        /*  CFDF09          */
     8539    union iodefine_reg32_t  CFDF19;                        /*  CFDF19          */
     8540
     8541/* end of struct st_rscan_from_rscan0cfidm */
     8542   
     8543/* start of struct st_rscan_from_rscan0cfidm */
     8544    union iodefine_reg32_t  CFID10;                        /*  CFID10          */
     8545    union iodefine_reg32_t  CFPTR10;                       /*  CFPTR10         */
     8546    union iodefine_reg32_t  CFDF010;                       /*  CFDF010         */
     8547    union iodefine_reg32_t  CFDF110;                       /*  CFDF110         */
     8548
     8549/* end of struct st_rscan_from_rscan0cfidm */
     8550   
     8551/* start of struct st_rscan_from_rscan0cfidm */
     8552    union iodefine_reg32_t  CFID11;                        /*  CFID11          */
     8553    union iodefine_reg32_t  CFPTR11;                       /*  CFPTR11         */
     8554    union iodefine_reg32_t  CFDF011;                       /*  CFDF011         */
     8555    union iodefine_reg32_t  CFDF111;                       /*  CFDF111         */
     8556
     8557/* end of struct st_rscan_from_rscan0cfidm */
     8558   
     8559/* start of struct st_rscan_from_rscan0cfidm */
     8560    union iodefine_reg32_t  CFID12;                        /*  CFID12          */
     8561    union iodefine_reg32_t  CFPTR12;                       /*  CFPTR12         */
     8562    union iodefine_reg32_t  CFDF012;                       /*  CFDF012         */
     8563    union iodefine_reg32_t  CFDF112;                       /*  CFDF112         */
     8564
     8565/* end of struct st_rscan_from_rscan0cfidm */
     8566   
     8567/* start of struct st_rscan_from_rscan0cfidm */
     8568    union iodefine_reg32_t  CFID13;                        /*  CFID13          */
     8569    union iodefine_reg32_t  CFPTR13;                       /*  CFPTR13         */
     8570    union iodefine_reg32_t  CFDF013;                       /*  CFDF013         */
     8571    union iodefine_reg32_t  CFDF113;                       /*  CFDF113         */
     8572
     8573/* end of struct st_rscan_from_rscan0cfidm */
     8574   
     8575/* start of struct st_rscan_from_rscan0cfidm */
     8576    union iodefine_reg32_t  CFID14;                        /*  CFID14          */
     8577    union iodefine_reg32_t  CFPTR14;                       /*  CFPTR14         */
     8578    union iodefine_reg32_t  CFDF014;                       /*  CFDF014         */
     8579    union iodefine_reg32_t  CFDF114;                       /*  CFDF114         */
     8580
     8581/* end of struct st_rscan_from_rscan0cfidm */
     8582   
     8583    volatile uint8_t   dummy180[144];                          /*                  */
     8584   
     8585/* start of struct st_rscan_from_rscan0tmidp */
     8586    union iodefine_reg32_t  TMID0;                         /*  TMID0           */
     8587    union iodefine_reg32_t  TMPTR0;                        /*  TMPTR0          */
     8588    union iodefine_reg32_t  TMDF00;                        /*  TMDF00          */
     8589    union iodefine_reg32_t  TMDF10;                        /*  TMDF10          */
     8590
     8591/* end of struct st_rscan_from_rscan0tmidp */
     8592   
     8593/* start of struct st_rscan_from_rscan0tmidp */
     8594    union iodefine_reg32_t  TMID1;                         /*  TMID1           */
     8595    union iodefine_reg32_t  TMPTR1;                        /*  TMPTR1          */
     8596    union iodefine_reg32_t  TMDF01;                        /*  TMDF01          */
     8597    union iodefine_reg32_t  TMDF11;                        /*  TMDF11          */
     8598
     8599/* end of struct st_rscan_from_rscan0tmidp */
     8600   
     8601/* start of struct st_rscan_from_rscan0tmidp */
     8602    union iodefine_reg32_t  TMID2;                         /*  TMID2           */
     8603    union iodefine_reg32_t  TMPTR2;                        /*  TMPTR2          */
     8604    union iodefine_reg32_t  TMDF02;                        /*  TMDF02          */
     8605    union iodefine_reg32_t  TMDF12;                        /*  TMDF12          */
     8606
     8607/* end of struct st_rscan_from_rscan0tmidp */
     8608   
     8609/* start of struct st_rscan_from_rscan0tmidp */
     8610    union iodefine_reg32_t  TMID3;                         /*  TMID3           */
     8611    union iodefine_reg32_t  TMPTR3;                        /*  TMPTR3          */
     8612    union iodefine_reg32_t  TMDF03;                        /*  TMDF03          */
     8613    union iodefine_reg32_t  TMDF13;                        /*  TMDF13          */
     8614
     8615/* end of struct st_rscan_from_rscan0tmidp */
     8616   
     8617/* start of struct st_rscan_from_rscan0tmidp */
     8618    union iodefine_reg32_t  TMID4;                         /*  TMID4           */
     8619    union iodefine_reg32_t  TMPTR4;                        /*  TMPTR4          */
     8620    union iodefine_reg32_t  TMDF04;                        /*  TMDF04          */
     8621    union iodefine_reg32_t  TMDF14;                        /*  TMDF14          */
     8622
     8623/* end of struct st_rscan_from_rscan0tmidp */
     8624   
     8625/* start of struct st_rscan_from_rscan0tmidp */
     8626    union iodefine_reg32_t  TMID5;                         /*  TMID5           */
     8627    union iodefine_reg32_t  TMPTR5;                        /*  TMPTR5          */
     8628    union iodefine_reg32_t  TMDF05;                        /*  TMDF05          */
     8629    union iodefine_reg32_t  TMDF15;                        /*  TMDF15          */
     8630
     8631/* end of struct st_rscan_from_rscan0tmidp */
     8632   
     8633/* start of struct st_rscan_from_rscan0tmidp */
     8634    union iodefine_reg32_t  TMID6;                         /*  TMID6           */
     8635    union iodefine_reg32_t  TMPTR6;                        /*  TMPTR6          */
     8636    union iodefine_reg32_t  TMDF06;                        /*  TMDF06          */
     8637    union iodefine_reg32_t  TMDF16;                        /*  TMDF16          */
     8638
     8639/* end of struct st_rscan_from_rscan0tmidp */
     8640   
     8641/* start of struct st_rscan_from_rscan0tmidp */
     8642    union iodefine_reg32_t  TMID7;                         /*  TMID7           */
     8643    union iodefine_reg32_t  TMPTR7;                        /*  TMPTR7          */
     8644    union iodefine_reg32_t  TMDF07;                        /*  TMDF07          */
     8645    union iodefine_reg32_t  TMDF17;                        /*  TMDF17          */
     8646
     8647/* end of struct st_rscan_from_rscan0tmidp */
     8648   
     8649/* start of struct st_rscan_from_rscan0tmidp */
     8650    union iodefine_reg32_t  TMID8;                         /*  TMID8           */
     8651    union iodefine_reg32_t  TMPTR8;                        /*  TMPTR8          */
     8652    union iodefine_reg32_t  TMDF08;                        /*  TMDF08          */
     8653    union iodefine_reg32_t  TMDF18;                        /*  TMDF18          */
     8654
     8655/* end of struct st_rscan_from_rscan0tmidp */
     8656   
     8657/* start of struct st_rscan_from_rscan0tmidp */
     8658    union iodefine_reg32_t  TMID9;                         /*  TMID9           */
     8659    union iodefine_reg32_t  TMPTR9;                        /*  TMPTR9          */
     8660    union iodefine_reg32_t  TMDF09;                        /*  TMDF09          */
     8661    union iodefine_reg32_t  TMDF19;                        /*  TMDF19          */
     8662
     8663/* end of struct st_rscan_from_rscan0tmidp */
     8664   
     8665/* start of struct st_rscan_from_rscan0tmidp */
     8666    union iodefine_reg32_t  TMID10;                        /*  TMID10          */
     8667    union iodefine_reg32_t  TMPTR10;                       /*  TMPTR10         */
     8668    union iodefine_reg32_t  TMDF010;                       /*  TMDF010         */
     8669    union iodefine_reg32_t  TMDF110;                       /*  TMDF110         */
     8670
     8671/* end of struct st_rscan_from_rscan0tmidp */
     8672   
     8673/* start of struct st_rscan_from_rscan0tmidp */
     8674    union iodefine_reg32_t  TMID11;                        /*  TMID11          */
     8675    union iodefine_reg32_t  TMPTR11;                       /*  TMPTR11         */
     8676    union iodefine_reg32_t  TMDF011;                       /*  TMDF011         */
     8677    union iodefine_reg32_t  TMDF111;                       /*  TMDF111         */
     8678
     8679/* end of struct st_rscan_from_rscan0tmidp */
     8680   
     8681/* start of struct st_rscan_from_rscan0tmidp */
     8682    union iodefine_reg32_t  TMID12;                        /*  TMID12          */
     8683    union iodefine_reg32_t  TMPTR12;                       /*  TMPTR12         */
     8684    union iodefine_reg32_t  TMDF012;                       /*  TMDF012         */
     8685    union iodefine_reg32_t  TMDF112;                       /*  TMDF112         */
     8686
     8687/* end of struct st_rscan_from_rscan0tmidp */
     8688   
     8689/* start of struct st_rscan_from_rscan0tmidp */
     8690    union iodefine_reg32_t  TMID13;                        /*  TMID13          */
     8691    union iodefine_reg32_t  TMPTR13;                       /*  TMPTR13         */
     8692    union iodefine_reg32_t  TMDF013;                       /*  TMDF013         */
     8693    union iodefine_reg32_t  TMDF113;                       /*  TMDF113         */
     8694
     8695/* end of struct st_rscan_from_rscan0tmidp */
     8696   
     8697/* start of struct st_rscan_from_rscan0tmidp */
     8698    union iodefine_reg32_t  TMID14;                        /*  TMID14          */
     8699    union iodefine_reg32_t  TMPTR14;                       /*  TMPTR14         */
     8700    union iodefine_reg32_t  TMDF014;                       /*  TMDF014         */
     8701    union iodefine_reg32_t  TMDF114;                       /*  TMDF114         */
     8702
     8703/* end of struct st_rscan_from_rscan0tmidp */
     8704   
     8705/* start of struct st_rscan_from_rscan0tmidp */
     8706    union iodefine_reg32_t  TMID15;                        /*  TMID15          */
     8707    union iodefine_reg32_t  TMPTR15;                       /*  TMPTR15         */
     8708    union iodefine_reg32_t  TMDF015;                       /*  TMDF015         */
     8709    union iodefine_reg32_t  TMDF115;                       /*  TMDF115         */
     8710
     8711/* end of struct st_rscan_from_rscan0tmidp */
     8712   
     8713/* start of struct st_rscan_from_rscan0tmidp */
     8714    union iodefine_reg32_t  TMID16;                        /*  TMID16          */
     8715    union iodefine_reg32_t  TMPTR16;                       /*  TMPTR16         */
     8716    union iodefine_reg32_t  TMDF016;                       /*  TMDF016         */
     8717    union iodefine_reg32_t  TMDF116;                       /*  TMDF116         */
     8718
     8719/* end of struct st_rscan_from_rscan0tmidp */
     8720   
     8721/* start of struct st_rscan_from_rscan0tmidp */
     8722    union iodefine_reg32_t  TMID17;                        /*  TMID17          */
     8723    union iodefine_reg32_t  TMPTR17;                       /*  TMPTR17         */
     8724    union iodefine_reg32_t  TMDF017;                       /*  TMDF017         */
     8725    union iodefine_reg32_t  TMDF117;                       /*  TMDF117         */
     8726
     8727/* end of struct st_rscan_from_rscan0tmidp */
     8728   
     8729/* start of struct st_rscan_from_rscan0tmidp */
     8730    union iodefine_reg32_t  TMID18;                        /*  TMID18          */
     8731    union iodefine_reg32_t  TMPTR18;                       /*  TMPTR18         */
     8732    union iodefine_reg32_t  TMDF018;                       /*  TMDF018         */
     8733    union iodefine_reg32_t  TMDF118;                       /*  TMDF118         */
     8734
     8735/* end of struct st_rscan_from_rscan0tmidp */
     8736   
     8737/* start of struct st_rscan_from_rscan0tmidp */
     8738    union iodefine_reg32_t  TMID19;                        /*  TMID19          */
     8739    union iodefine_reg32_t  TMPTR19;                       /*  TMPTR19         */
     8740    union iodefine_reg32_t  TMDF019;                       /*  TMDF019         */
     8741    union iodefine_reg32_t  TMDF119;                       /*  TMDF119         */
     8742
     8743/* end of struct st_rscan_from_rscan0tmidp */
     8744   
     8745/* start of struct st_rscan_from_rscan0tmidp */
     8746    union iodefine_reg32_t  TMID20;                        /*  TMID20          */
     8747    union iodefine_reg32_t  TMPTR20;                       /*  TMPTR20         */
     8748    union iodefine_reg32_t  TMDF020;                       /*  TMDF020         */
     8749    union iodefine_reg32_t  TMDF120;                       /*  TMDF120         */
     8750
     8751/* end of struct st_rscan_from_rscan0tmidp */
     8752   
     8753/* start of struct st_rscan_from_rscan0tmidp */
     8754    union iodefine_reg32_t  TMID21;                        /*  TMID21          */
     8755    union iodefine_reg32_t  TMPTR21;                       /*  TMPTR21         */
     8756    union iodefine_reg32_t  TMDF021;                       /*  TMDF021         */
     8757    union iodefine_reg32_t  TMDF121;                       /*  TMDF121         */
     8758
     8759/* end of struct st_rscan_from_rscan0tmidp */
     8760   
     8761/* start of struct st_rscan_from_rscan0tmidp */
     8762    union iodefine_reg32_t  TMID22;                        /*  TMID22          */
     8763    union iodefine_reg32_t  TMPTR22;                       /*  TMPTR22         */
     8764    union iodefine_reg32_t  TMDF022;                       /*  TMDF022         */
     8765    union iodefine_reg32_t  TMDF122;                       /*  TMDF122         */
     8766
     8767/* end of struct st_rscan_from_rscan0tmidp */
     8768   
     8769/* start of struct st_rscan_from_rscan0tmidp */
     8770    union iodefine_reg32_t  TMID23;                        /*  TMID23          */
     8771    union iodefine_reg32_t  TMPTR23;                       /*  TMPTR23         */
     8772    union iodefine_reg32_t  TMDF023;                       /*  TMDF023         */
     8773    union iodefine_reg32_t  TMDF123;                       /*  TMDF123         */
     8774
     8775/* end of struct st_rscan_from_rscan0tmidp */
     8776   
     8777/* start of struct st_rscan_from_rscan0tmidp */
     8778    union iodefine_reg32_t  TMID24;                        /*  TMID24          */
     8779    union iodefine_reg32_t  TMPTR24;                       /*  TMPTR24         */
     8780    union iodefine_reg32_t  TMDF024;                       /*  TMDF024         */
     8781    union iodefine_reg32_t  TMDF124;                       /*  TMDF124         */
     8782
     8783/* end of struct st_rscan_from_rscan0tmidp */
     8784   
     8785/* start of struct st_rscan_from_rscan0tmidp */
     8786    union iodefine_reg32_t  TMID25;                        /*  TMID25          */
     8787    union iodefine_reg32_t  TMPTR25;                       /*  TMPTR25         */
     8788    union iodefine_reg32_t  TMDF025;                       /*  TMDF025         */
     8789    union iodefine_reg32_t  TMDF125;                       /*  TMDF125         */
     8790
     8791/* end of struct st_rscan_from_rscan0tmidp */
     8792   
     8793/* start of struct st_rscan_from_rscan0tmidp */
     8794    union iodefine_reg32_t  TMID26;                        /*  TMID26          */
     8795    union iodefine_reg32_t  TMPTR26;                       /*  TMPTR26         */
     8796    union iodefine_reg32_t  TMDF026;                       /*  TMDF026         */
     8797    union iodefine_reg32_t  TMDF126;                       /*  TMDF126         */
     8798
     8799/* end of struct st_rscan_from_rscan0tmidp */
     8800   
     8801/* start of struct st_rscan_from_rscan0tmidp */
     8802    union iodefine_reg32_t  TMID27;                        /*  TMID27          */
     8803    union iodefine_reg32_t  TMPTR27;                       /*  TMPTR27         */
     8804    union iodefine_reg32_t  TMDF027;                       /*  TMDF027         */
     8805    union iodefine_reg32_t  TMDF127;                       /*  TMDF127         */
     8806
     8807/* end of struct st_rscan_from_rscan0tmidp */
     8808   
     8809/* start of struct st_rscan_from_rscan0tmidp */
     8810    union iodefine_reg32_t  TMID28;                        /*  TMID28          */
     8811    union iodefine_reg32_t  TMPTR28;                       /*  TMPTR28         */
     8812    union iodefine_reg32_t  TMDF028;                       /*  TMDF028         */
     8813    union iodefine_reg32_t  TMDF128;                       /*  TMDF128         */
     8814
     8815/* end of struct st_rscan_from_rscan0tmidp */
     8816   
     8817/* start of struct st_rscan_from_rscan0tmidp */
     8818    union iodefine_reg32_t  TMID29;                        /*  TMID29          */
     8819    union iodefine_reg32_t  TMPTR29;                       /*  TMPTR29         */
     8820    union iodefine_reg32_t  TMDF029;                       /*  TMDF029         */
     8821    union iodefine_reg32_t  TMDF129;                       /*  TMDF129         */
     8822
     8823/* end of struct st_rscan_from_rscan0tmidp */
     8824   
     8825/* start of struct st_rscan_from_rscan0tmidp */
     8826    union iodefine_reg32_t  TMID30;                        /*  TMID30          */
     8827    union iodefine_reg32_t  TMPTR30;                       /*  TMPTR30         */
     8828    union iodefine_reg32_t  TMDF030;                       /*  TMDF030         */
     8829    union iodefine_reg32_t  TMDF130;                       /*  TMDF130         */
     8830
     8831/* end of struct st_rscan_from_rscan0tmidp */
     8832   
     8833/* start of struct st_rscan_from_rscan0tmidp */
     8834    union iodefine_reg32_t  TMID31;                        /*  TMID31          */
     8835    union iodefine_reg32_t  TMPTR31;                       /*  TMPTR31         */
     8836    union iodefine_reg32_t  TMDF031;                       /*  TMDF031         */
     8837    union iodefine_reg32_t  TMDF131;                       /*  TMDF131         */
     8838
     8839/* end of struct st_rscan_from_rscan0tmidp */
     8840   
     8841/* start of struct st_rscan_from_rscan0tmidp */
     8842    union iodefine_reg32_t  TMID32;                        /*  TMID32          */
     8843    union iodefine_reg32_t  TMPTR32;                       /*  TMPTR32         */
     8844    union iodefine_reg32_t  TMDF032;                       /*  TMDF032         */
     8845    union iodefine_reg32_t  TMDF132;                       /*  TMDF132         */
     8846
     8847/* end of struct st_rscan_from_rscan0tmidp */
     8848   
     8849/* start of struct st_rscan_from_rscan0tmidp */
     8850    union iodefine_reg32_t  TMID33;                        /*  TMID33          */
     8851    union iodefine_reg32_t  TMPTR33;                       /*  TMPTR33         */
     8852    union iodefine_reg32_t  TMDF033;                       /*  TMDF033         */
     8853    union iodefine_reg32_t  TMDF133;                       /*  TMDF133         */
     8854
     8855/* end of struct st_rscan_from_rscan0tmidp */
     8856   
     8857/* start of struct st_rscan_from_rscan0tmidp */
     8858    union iodefine_reg32_t  TMID34;                        /*  TMID34          */
     8859    union iodefine_reg32_t  TMPTR34;                       /*  TMPTR34         */
     8860    union iodefine_reg32_t  TMDF034;                       /*  TMDF034         */
     8861    union iodefine_reg32_t  TMDF134;                       /*  TMDF134         */
     8862
     8863/* end of struct st_rscan_from_rscan0tmidp */
     8864   
     8865/* start of struct st_rscan_from_rscan0tmidp */
     8866    union iodefine_reg32_t  TMID35;                        /*  TMID35          */
     8867    union iodefine_reg32_t  TMPTR35;                       /*  TMPTR35         */
     8868    union iodefine_reg32_t  TMDF035;                       /*  TMDF035         */
     8869    union iodefine_reg32_t  TMDF135;                       /*  TMDF135         */
     8870
     8871/* end of struct st_rscan_from_rscan0tmidp */
     8872   
     8873/* start of struct st_rscan_from_rscan0tmidp */
     8874    union iodefine_reg32_t  TMID36;                        /*  TMID36          */
     8875    union iodefine_reg32_t  TMPTR36;                       /*  TMPTR36         */
     8876    union iodefine_reg32_t  TMDF036;                       /*  TMDF036         */
     8877    union iodefine_reg32_t  TMDF136;                       /*  TMDF136         */
     8878
     8879/* end of struct st_rscan_from_rscan0tmidp */
     8880   
     8881/* start of struct st_rscan_from_rscan0tmidp */
     8882    union iodefine_reg32_t  TMID37;                        /*  TMID37          */
     8883    union iodefine_reg32_t  TMPTR37;                       /*  TMPTR37         */
     8884    union iodefine_reg32_t  TMDF037;                       /*  TMDF037         */
     8885    union iodefine_reg32_t  TMDF137;                       /*  TMDF137         */
     8886
     8887/* end of struct st_rscan_from_rscan0tmidp */
     8888   
     8889/* start of struct st_rscan_from_rscan0tmidp */
     8890    union iodefine_reg32_t  TMID38;                        /*  TMID38          */
     8891    union iodefine_reg32_t  TMPTR38;                       /*  TMPTR38         */
     8892    union iodefine_reg32_t  TMDF038;                       /*  TMDF038         */
     8893    union iodefine_reg32_t  TMDF138;                       /*  TMDF138         */
     8894
     8895/* end of struct st_rscan_from_rscan0tmidp */
     8896   
     8897/* start of struct st_rscan_from_rscan0tmidp */
     8898    union iodefine_reg32_t  TMID39;                        /*  TMID39          */
     8899    union iodefine_reg32_t  TMPTR39;                       /*  TMPTR39         */
     8900    union iodefine_reg32_t  TMDF039;                       /*  TMDF039         */
     8901    union iodefine_reg32_t  TMDF139;                       /*  TMDF139         */
     8902
     8903/* end of struct st_rscan_from_rscan0tmidp */
     8904   
     8905/* start of struct st_rscan_from_rscan0tmidp */
     8906    union iodefine_reg32_t  TMID40;                        /*  TMID40          */
     8907    union iodefine_reg32_t  TMPTR40;                       /*  TMPTR40         */
     8908    union iodefine_reg32_t  TMDF040;                       /*  TMDF040         */
     8909    union iodefine_reg32_t  TMDF140;                       /*  TMDF140         */
     8910
     8911/* end of struct st_rscan_from_rscan0tmidp */
     8912   
     8913/* start of struct st_rscan_from_rscan0tmidp */
     8914    union iodefine_reg32_t  TMID41;                        /*  TMID41          */
     8915    union iodefine_reg32_t  TMPTR41;                       /*  TMPTR41         */
     8916    union iodefine_reg32_t  TMDF041;                       /*  TMDF041         */
     8917    union iodefine_reg32_t  TMDF141;                       /*  TMDF141         */
     8918
     8919/* end of struct st_rscan_from_rscan0tmidp */
     8920   
     8921/* start of struct st_rscan_from_rscan0tmidp */
     8922    union iodefine_reg32_t  TMID42;                        /*  TMID42          */
     8923    union iodefine_reg32_t  TMPTR42;                       /*  TMPTR42         */
     8924    union iodefine_reg32_t  TMDF042;                       /*  TMDF042         */
     8925    union iodefine_reg32_t  TMDF142;                       /*  TMDF142         */
     8926
     8927/* end of struct st_rscan_from_rscan0tmidp */
     8928   
     8929/* start of struct st_rscan_from_rscan0tmidp */
     8930    union iodefine_reg32_t  TMID43;                        /*  TMID43          */
     8931    union iodefine_reg32_t  TMPTR43;                       /*  TMPTR43         */
     8932    union iodefine_reg32_t  TMDF043;                       /*  TMDF043         */
     8933    union iodefine_reg32_t  TMDF143;                       /*  TMDF143         */
     8934
     8935/* end of struct st_rscan_from_rscan0tmidp */
     8936   
     8937/* start of struct st_rscan_from_rscan0tmidp */
     8938    union iodefine_reg32_t  TMID44;                        /*  TMID44          */
     8939    union iodefine_reg32_t  TMPTR44;                       /*  TMPTR44         */
     8940    union iodefine_reg32_t  TMDF044;                       /*  TMDF044         */
     8941    union iodefine_reg32_t  TMDF144;                       /*  TMDF144         */
     8942
     8943/* end of struct st_rscan_from_rscan0tmidp */
     8944   
     8945/* start of struct st_rscan_from_rscan0tmidp */
     8946    union iodefine_reg32_t  TMID45;                        /*  TMID45          */
     8947    union iodefine_reg32_t  TMPTR45;                       /*  TMPTR45         */
     8948    union iodefine_reg32_t  TMDF045;                       /*  TMDF045         */
     8949    union iodefine_reg32_t  TMDF145;                       /*  TMDF145         */
     8950
     8951/* end of struct st_rscan_from_rscan0tmidp */
     8952   
     8953/* start of struct st_rscan_from_rscan0tmidp */
     8954    union iodefine_reg32_t  TMID46;                        /*  TMID46          */
     8955    union iodefine_reg32_t  TMPTR46;                       /*  TMPTR46         */
     8956    union iodefine_reg32_t  TMDF046;                       /*  TMDF046         */
     8957    union iodefine_reg32_t  TMDF146;                       /*  TMDF146         */
     8958
     8959/* end of struct st_rscan_from_rscan0tmidp */
     8960   
     8961/* start of struct st_rscan_from_rscan0tmidp */
     8962    union iodefine_reg32_t  TMID47;                        /*  TMID47          */
     8963    union iodefine_reg32_t  TMPTR47;                       /*  TMPTR47         */
     8964    union iodefine_reg32_t  TMDF047;                       /*  TMDF047         */
     8965    union iodefine_reg32_t  TMDF147;                       /*  TMDF147         */
     8966
     8967/* end of struct st_rscan_from_rscan0tmidp */
     8968   
     8969/* start of struct st_rscan_from_rscan0tmidp */
     8970    union iodefine_reg32_t  TMID48;                        /*  TMID48          */
     8971    union iodefine_reg32_t  TMPTR48;                       /*  TMPTR48         */
     8972    union iodefine_reg32_t  TMDF048;                       /*  TMDF048         */
     8973    union iodefine_reg32_t  TMDF148;                       /*  TMDF148         */
     8974
     8975/* end of struct st_rscan_from_rscan0tmidp */
     8976   
     8977/* start of struct st_rscan_from_rscan0tmidp */
     8978    union iodefine_reg32_t  TMID49;                        /*  TMID49          */
     8979    union iodefine_reg32_t  TMPTR49;                       /*  TMPTR49         */
     8980    union iodefine_reg32_t  TMDF049;                       /*  TMDF049         */
     8981    union iodefine_reg32_t  TMDF149;                       /*  TMDF149         */
     8982
     8983/* end of struct st_rscan_from_rscan0tmidp */
     8984   
     8985/* start of struct st_rscan_from_rscan0tmidp */
     8986    union iodefine_reg32_t  TMID50;                        /*  TMID50          */
     8987    union iodefine_reg32_t  TMPTR50;                       /*  TMPTR50         */
     8988    union iodefine_reg32_t  TMDF050;                       /*  TMDF050         */
     8989    union iodefine_reg32_t  TMDF150;                       /*  TMDF150         */
     8990
     8991/* end of struct st_rscan_from_rscan0tmidp */
     8992   
     8993/* start of struct st_rscan_from_rscan0tmidp */
     8994    union iodefine_reg32_t  TMID51;                        /*  TMID51          */
     8995    union iodefine_reg32_t  TMPTR51;                       /*  TMPTR51         */
     8996    union iodefine_reg32_t  TMDF051;                       /*  TMDF051         */
     8997    union iodefine_reg32_t  TMDF151;                       /*  TMDF151         */
     8998
     8999/* end of struct st_rscan_from_rscan0tmidp */
     9000   
     9001/* start of struct st_rscan_from_rscan0tmidp */
     9002    union iodefine_reg32_t  TMID52;                        /*  TMID52          */
     9003    union iodefine_reg32_t  TMPTR52;                       /*  TMPTR52         */
     9004    union iodefine_reg32_t  TMDF052;                       /*  TMDF052         */
     9005    union iodefine_reg32_t  TMDF152;                       /*  TMDF152         */
     9006
     9007/* end of struct st_rscan_from_rscan0tmidp */
     9008   
     9009/* start of struct st_rscan_from_rscan0tmidp */
     9010    union iodefine_reg32_t  TMID53;                        /*  TMID53          */
     9011    union iodefine_reg32_t  TMPTR53;                       /*  TMPTR53         */
     9012    union iodefine_reg32_t  TMDF053;                       /*  TMDF053         */
     9013    union iodefine_reg32_t  TMDF153;                       /*  TMDF153         */
     9014
     9015/* end of struct st_rscan_from_rscan0tmidp */
     9016   
     9017/* start of struct st_rscan_from_rscan0tmidp */
     9018    union iodefine_reg32_t  TMID54;                        /*  TMID54          */
     9019    union iodefine_reg32_t  TMPTR54;                       /*  TMPTR54         */
     9020    union iodefine_reg32_t  TMDF054;                       /*  TMDF054         */
     9021    union iodefine_reg32_t  TMDF154;                       /*  TMDF154         */
     9022
     9023/* end of struct st_rscan_from_rscan0tmidp */
     9024   
     9025/* start of struct st_rscan_from_rscan0tmidp */
     9026    union iodefine_reg32_t  TMID55;                        /*  TMID55          */
     9027    union iodefine_reg32_t  TMPTR55;                       /*  TMPTR55         */
     9028    union iodefine_reg32_t  TMDF055;                       /*  TMDF055         */
     9029    union iodefine_reg32_t  TMDF155;                       /*  TMDF155         */
     9030
     9031/* end of struct st_rscan_from_rscan0tmidp */
     9032   
     9033/* start of struct st_rscan_from_rscan0tmidp */
     9034    union iodefine_reg32_t  TMID56;                        /*  TMID56          */
     9035    union iodefine_reg32_t  TMPTR56;                       /*  TMPTR56         */
     9036    union iodefine_reg32_t  TMDF056;                       /*  TMDF056         */
     9037    union iodefine_reg32_t  TMDF156;                       /*  TMDF156         */
     9038
     9039/* end of struct st_rscan_from_rscan0tmidp */
     9040   
     9041/* start of struct st_rscan_from_rscan0tmidp */
     9042    union iodefine_reg32_t  TMID57;                        /*  TMID57          */
     9043    union iodefine_reg32_t  TMPTR57;                       /*  TMPTR57         */
     9044    union iodefine_reg32_t  TMDF057;                       /*  TMDF057         */
     9045    union iodefine_reg32_t  TMDF157;                       /*  TMDF157         */
     9046
     9047/* end of struct st_rscan_from_rscan0tmidp */
     9048   
     9049/* start of struct st_rscan_from_rscan0tmidp */
     9050    union iodefine_reg32_t  TMID58;                        /*  TMID58          */
     9051    union iodefine_reg32_t  TMPTR58;                       /*  TMPTR58         */
     9052    union iodefine_reg32_t  TMDF058;                       /*  TMDF058         */
     9053    union iodefine_reg32_t  TMDF158;                       /*  TMDF158         */
     9054
     9055/* end of struct st_rscan_from_rscan0tmidp */
     9056   
     9057/* start of struct st_rscan_from_rscan0tmidp */
     9058    union iodefine_reg32_t  TMID59;                        /*  TMID59          */
     9059    union iodefine_reg32_t  TMPTR59;                       /*  TMPTR59         */
     9060    union iodefine_reg32_t  TMDF059;                       /*  TMDF059         */
     9061    union iodefine_reg32_t  TMDF159;                       /*  TMDF159         */
     9062
     9063/* end of struct st_rscan_from_rscan0tmidp */
     9064   
     9065/* start of struct st_rscan_from_rscan0tmidp */
     9066    union iodefine_reg32_t  TMID60;                        /*  TMID60          */
     9067    union iodefine_reg32_t  TMPTR60;                       /*  TMPTR60         */
     9068    union iodefine_reg32_t  TMDF060;                       /*  TMDF060         */
     9069    union iodefine_reg32_t  TMDF160;                       /*  TMDF160         */
     9070
     9071/* end of struct st_rscan_from_rscan0tmidp */
     9072   
     9073/* start of struct st_rscan_from_rscan0tmidp */
     9074    union iodefine_reg32_t  TMID61;                        /*  TMID61          */
     9075    union iodefine_reg32_t  TMPTR61;                       /*  TMPTR61         */
     9076    union iodefine_reg32_t  TMDF061;                       /*  TMDF061         */
     9077    union iodefine_reg32_t  TMDF161;                       /*  TMDF161         */
     9078
     9079/* end of struct st_rscan_from_rscan0tmidp */
     9080   
     9081/* start of struct st_rscan_from_rscan0tmidp */
     9082    union iodefine_reg32_t  TMID62;                        /*  TMID62          */
     9083    union iodefine_reg32_t  TMPTR62;                       /*  TMPTR62         */
     9084    union iodefine_reg32_t  TMDF062;                       /*  TMDF062         */
     9085    union iodefine_reg32_t  TMDF162;                       /*  TMDF162         */
     9086
     9087/* end of struct st_rscan_from_rscan0tmidp */
     9088   
     9089/* start of struct st_rscan_from_rscan0tmidp */
     9090    union iodefine_reg32_t  TMID63;                        /*  TMID63          */
     9091    union iodefine_reg32_t  TMPTR63;                       /*  TMPTR63         */
     9092    union iodefine_reg32_t  TMDF063;                       /*  TMDF063         */
     9093    union iodefine_reg32_t  TMDF163;                       /*  TMDF163         */
     9094
     9095/* end of struct st_rscan_from_rscan0tmidp */
     9096   
     9097/* start of struct st_rscan_from_rscan0tmidp */
     9098    union iodefine_reg32_t  TMID64;                        /*  TMID64          */
     9099    union iodefine_reg32_t  TMPTR64;                       /*  TMPTR64         */
     9100    union iodefine_reg32_t  TMDF064;                       /*  TMDF064         */
     9101    union iodefine_reg32_t  TMDF164;                       /*  TMDF164         */
     9102
     9103/* end of struct st_rscan_from_rscan0tmidp */
     9104   
     9105/* start of struct st_rscan_from_rscan0tmidp */
     9106    union iodefine_reg32_t  TMID65;                        /*  TMID65          */
     9107    union iodefine_reg32_t  TMPTR65;                       /*  TMPTR65         */
     9108    union iodefine_reg32_t  TMDF065;                       /*  TMDF065         */
     9109    union iodefine_reg32_t  TMDF165;                       /*  TMDF165         */
     9110
     9111/* end of struct st_rscan_from_rscan0tmidp */
     9112   
     9113/* start of struct st_rscan_from_rscan0tmidp */
     9114    union iodefine_reg32_t  TMID66;                        /*  TMID66          */
     9115    union iodefine_reg32_t  TMPTR66;                       /*  TMPTR66         */
     9116    union iodefine_reg32_t  TMDF066;                       /*  TMDF066         */
     9117    union iodefine_reg32_t  TMDF166;                       /*  TMDF166         */
     9118
     9119/* end of struct st_rscan_from_rscan0tmidp */
     9120   
     9121/* start of struct st_rscan_from_rscan0tmidp */
     9122    union iodefine_reg32_t  TMID67;                        /*  TMID67          */
     9123    union iodefine_reg32_t  TMPTR67;                       /*  TMPTR67         */
     9124    union iodefine_reg32_t  TMDF067;                       /*  TMDF067         */
     9125    union iodefine_reg32_t  TMDF167;                       /*  TMDF167         */
     9126
     9127/* end of struct st_rscan_from_rscan0tmidp */
     9128   
     9129/* start of struct st_rscan_from_rscan0tmidp */
     9130    union iodefine_reg32_t  TMID68;                        /*  TMID68          */
     9131    union iodefine_reg32_t  TMPTR68;                       /*  TMPTR68         */
     9132    union iodefine_reg32_t  TMDF068;                       /*  TMDF068         */
     9133    union iodefine_reg32_t  TMDF168;                       /*  TMDF168         */
     9134
     9135/* end of struct st_rscan_from_rscan0tmidp */
     9136   
     9137/* start of struct st_rscan_from_rscan0tmidp */
     9138    union iodefine_reg32_t  TMID69;                        /*  TMID69          */
     9139    union iodefine_reg32_t  TMPTR69;                       /*  TMPTR69         */
     9140    union iodefine_reg32_t  TMDF069;                       /*  TMDF069         */
     9141    union iodefine_reg32_t  TMDF169;                       /*  TMDF169         */
     9142
     9143/* end of struct st_rscan_from_rscan0tmidp */
     9144   
     9145/* start of struct st_rscan_from_rscan0tmidp */
     9146    union iodefine_reg32_t  TMID70;                        /*  TMID70          */
     9147    union iodefine_reg32_t  TMPTR70;                       /*  TMPTR70         */
     9148    union iodefine_reg32_t  TMDF070;                       /*  TMDF070         */
     9149    union iodefine_reg32_t  TMDF170;                       /*  TMDF170         */
     9150
     9151/* end of struct st_rscan_from_rscan0tmidp */
     9152   
     9153/* start of struct st_rscan_from_rscan0tmidp */
     9154    union iodefine_reg32_t  TMID71;                        /*  TMID71          */
     9155    union iodefine_reg32_t  TMPTR71;                       /*  TMPTR71         */
     9156    union iodefine_reg32_t  TMDF071;                       /*  TMDF071         */
     9157    union iodefine_reg32_t  TMDF171;                       /*  TMDF171         */
     9158
     9159/* end of struct st_rscan_from_rscan0tmidp */
     9160   
     9161/* start of struct st_rscan_from_rscan0tmidp */
     9162    union iodefine_reg32_t  TMID72;                        /*  TMID72          */
     9163    union iodefine_reg32_t  TMPTR72;                       /*  TMPTR72         */
     9164    union iodefine_reg32_t  TMDF072;                       /*  TMDF072         */
     9165    union iodefine_reg32_t  TMDF172;                       /*  TMDF172         */
     9166
     9167/* end of struct st_rscan_from_rscan0tmidp */
     9168   
     9169/* start of struct st_rscan_from_rscan0tmidp */
     9170    union iodefine_reg32_t  TMID73;                        /*  TMID73          */
     9171    union iodefine_reg32_t  TMPTR73;                       /*  TMPTR73         */
     9172    union iodefine_reg32_t  TMDF073;                       /*  TMDF073         */
     9173    union iodefine_reg32_t  TMDF173;                       /*  TMDF173         */
     9174
     9175/* end of struct st_rscan_from_rscan0tmidp */
     9176   
     9177/* start of struct st_rscan_from_rscan0tmidp */
     9178    union iodefine_reg32_t  TMID74;                        /*  TMID74          */
     9179    union iodefine_reg32_t  TMPTR74;                       /*  TMPTR74         */
     9180    union iodefine_reg32_t  TMDF074;                       /*  TMDF074         */
     9181    union iodefine_reg32_t  TMDF174;                       /*  TMDF174         */
     9182
     9183/* end of struct st_rscan_from_rscan0tmidp */
     9184   
     9185/* start of struct st_rscan_from_rscan0tmidp */
     9186    union iodefine_reg32_t  TMID75;                        /*  TMID75          */
     9187    union iodefine_reg32_t  TMPTR75;                       /*  TMPTR75         */
     9188    union iodefine_reg32_t  TMDF075;                       /*  TMDF075         */
     9189    union iodefine_reg32_t  TMDF175;                       /*  TMDF175         */
     9190
     9191/* end of struct st_rscan_from_rscan0tmidp */
     9192   
     9193/* start of struct st_rscan_from_rscan0tmidp */
     9194    union iodefine_reg32_t  TMID76;                        /*  TMID76          */
     9195    union iodefine_reg32_t  TMPTR76;                       /*  TMPTR76         */
     9196    union iodefine_reg32_t  TMDF076;                       /*  TMDF076         */
     9197    union iodefine_reg32_t  TMDF176;                       /*  TMDF176         */
     9198
     9199/* end of struct st_rscan_from_rscan0tmidp */
     9200   
     9201/* start of struct st_rscan_from_rscan0tmidp */
     9202    union iodefine_reg32_t  TMID77;                        /*  TMID77          */
     9203    union iodefine_reg32_t  TMPTR77;                       /*  TMPTR77         */
     9204    union iodefine_reg32_t  TMDF077;                       /*  TMDF077         */
     9205    union iodefine_reg32_t  TMDF177;                       /*  TMDF177         */
     9206
     9207/* end of struct st_rscan_from_rscan0tmidp */
     9208   
     9209/* start of struct st_rscan_from_rscan0tmidp */
     9210    union iodefine_reg32_t  TMID78;                        /*  TMID78          */
     9211    union iodefine_reg32_t  TMPTR78;                       /*  TMPTR78         */
     9212    union iodefine_reg32_t  TMDF078;                       /*  TMDF078         */
     9213    union iodefine_reg32_t  TMDF178;                       /*  TMDF178         */
     9214
     9215/* end of struct st_rscan_from_rscan0tmidp */
     9216   
     9217/* start of struct st_rscan_from_rscan0tmidp */
     9218    union iodefine_reg32_t  TMID79;                        /*  TMID79          */
     9219    union iodefine_reg32_t  TMPTR79;                       /*  TMPTR79         */
     9220    union iodefine_reg32_t  TMDF079;                       /*  TMDF079         */
     9221    union iodefine_reg32_t  TMDF179;                       /*  TMDF179         */
     9222
     9223/* end of struct st_rscan_from_rscan0tmidp */
     9224   
     9225    volatile uint8_t   dummy181[768];                          /*                  */
     9226
     9227/* #define RSCAN0_THLACC0_COUNT (5) */
     9228    union iodefine_reg32_t  THLACC0;                       /*  THLACC0         */
     9229    union iodefine_reg32_t  THLACC1;                       /*  THLACC1         */
     9230    union iodefine_reg32_t  THLACC2;                       /*  THLACC2         */
     9231    union iodefine_reg32_t  THLACC3;                       /*  THLACC3         */
     9232    union iodefine_reg32_t  THLACC4;                       /*  THLACC4         */
     9233   
     9234} r_io_rscan0_t;
     9235
     9236
     9237typedef struct st_rscan_from_rscan0cncfg
     9238{
     9239 
     9240    union iodefine_reg32_t  CnCFG;                         /*  CnCFG           */
     9241    union iodefine_reg32_t  CnCTR;                         /*  CnCTR           */
     9242    union iodefine_reg32_t  CnSTS;                         /*  CnSTS           */
     9243    union iodefine_reg32_t  CnERFL;                        /*  CnERFL          */
     9244} r_io_rscan_from_rscan0cncfg_t;
     9245
     9246
     9247typedef struct st_rscan_from_rscan0gaflidj
     9248{
     9249 
     9250    union iodefine_reg32_t  GAFLIDj;                       /*  GAFLIDj         */
     9251    union iodefine_reg32_t  GAFLMj;                        /*  GAFLMj          */
     9252    union iodefine_reg32_t  GAFLP0j;                       /*  GAFLP0j         */
     9253    union iodefine_reg32_t  GAFLP1j;                       /*  GAFLP1j         */
     9254} r_io_rscan_from_rscan0gaflidj_t;
     9255
     9256
     9257typedef struct st_rscan_from_rscan0rmidp
     9258{
     9259 
     9260    union iodefine_reg32_t  RMIDp;                         /*  RMIDp           */
     9261    union iodefine_reg32_t  RMPTRp;                        /*  RMPTRp          */
     9262    union iodefine_reg32_t  RMDF0p;                        /*  RMDF0p          */
     9263    union iodefine_reg32_t  RMDF1p;                        /*  RMDF1p          */
     9264} r_io_rscan_from_rscan0rmidp_t;
     9265
     9266
     9267typedef struct st_rscan_from_rscan0rfidm
     9268{
     9269 
     9270    union iodefine_reg32_t  RFIDm;                         /*  RFIDm           */
     9271    union iodefine_reg32_t  RFPTRm;                        /*  RFPTRm          */
     9272    union iodefine_reg32_t  RFDF0m;                        /*  RFDF0m          */
     9273    union iodefine_reg32_t  RFDF1m;                        /*  RFDF1m          */
     9274} r_io_rscan_from_rscan0rfidm_t;
     9275
     9276
     9277typedef struct st_rscan_from_rscan0tmidp
     9278{
     9279 
     9280    union iodefine_reg32_t  TMIDp;                         /*  TMIDp           */
     9281    union iodefine_reg32_t  TMPTRp;                        /*  TMPTRp          */
     9282    union iodefine_reg32_t  TMDF0p;                        /*  TMDF0p          */
     9283    union iodefine_reg32_t  TMDF1p;                        /*  TMDF1p          */
     9284} r_io_rscan_from_rscan0tmidp_t;
     9285
     9286
     9287typedef struct st_rscan_from_rscan0cfidm
     9288{
     9289 
     9290    union iodefine_reg32_t  CFIDm;                         /*  CFIDm           */
     9291    union iodefine_reg32_t  CFPTRm;                        /*  CFPTRm          */
     9292    union iodefine_reg32_t  CFDF0m;                        /*  CFDF0m          */
     9293    union iodefine_reg32_t  CFDF1m;                        /*  CFDF1m          */
     9294} r_io_rscan_from_rscan0cfidm_t;
     9295
     9296
     9297/* Channel array defines of RSCAN0 (2)*/
     9298#ifdef  DECLARE_RSCAN_FROM_RSCAN0_CFIDm_CHANNELS
     9299volatile struct st_rscan_from_rscan0cfidm*  RSCAN_FROM_RSCAN0_CFIDm[ RSCAN_FROM_RSCAN0_CFIDm_COUNT ] =
     9300    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     9301    RSCAN_FROM_RSCAN0_CFIDm_ADDRESS_LIST;
     9302    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     9303#endif  /* DECLARE_RSCAN_FROM_RSCAN0_CFIDm_CHANNELS */
     9304
     9305#ifdef  DECLARE_RSCAN_FROM_RSCAN0_TMIDp_CHANNELS
     9306volatile struct st_rscan_from_rscan0tmidp*  RSCAN_FROM_RSCAN0_TMIDp[ RSCAN_FROM_RSCAN0_TMIDp_COUNT ] =
     9307    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     9308    RSCAN_FROM_RSCAN0_TMIDp_ADDRESS_LIST;
     9309    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     9310#endif  /* DECLARE_RSCAN_FROM_RSCAN0_TMIDp_CHANNELS */
     9311
     9312#ifdef  DECLARE_RSCAN_FROM_RSCAN0_RFIDm_CHANNELS
     9313volatile struct st_rscan_from_rscan0rfidm*  RSCAN_FROM_RSCAN0_RFIDm[ RSCAN_FROM_RSCAN0_RFIDm_COUNT ] =
     9314    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     9315    RSCAN_FROM_RSCAN0_RFIDm_ADDRESS_LIST;
     9316    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     9317#endif  /* DECLARE_RSCAN_FROM_RSCAN0_RFIDm_CHANNELS */
     9318
     9319#ifdef  DECLARE_RSCAN_FROM_RSCAN0_RMIDp_CHANNELS
     9320volatile struct st_rscan_from_rscan0rmidp*  RSCAN_FROM_RSCAN0_RMIDp[ RSCAN_FROM_RSCAN0_RMIDp_COUNT ] =
     9321    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     9322    RSCAN_FROM_RSCAN0_RMIDp_ADDRESS_LIST;
     9323    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     9324#endif  /* DECLARE_RSCAN_FROM_RSCAN0_RMIDp_CHANNELS */
     9325
     9326#ifdef  DECLARE_RSCAN_FROM_RSCAN0_GAFLIDj_CHANNELS
     9327volatile struct st_rscan_from_rscan0gaflidj*  RSCAN_FROM_RSCAN0_GAFLIDj[ RSCAN_FROM_RSCAN0_GAFLIDj_COUNT ] =
     9328    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     9329    RSCAN_FROM_RSCAN0_GAFLIDj_ADDRESS_LIST;
     9330    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     9331#endif  /* DECLARE_RSCAN_FROM_RSCAN0_GAFLIDj_CHANNELS */
     9332
     9333#ifdef  DECLARE_RSCAN_FROM_RSCAN0_CnCFG_CHANNELS
     9334volatile struct st_rscan_from_rscan0cncfg*  RSCAN_FROM_RSCAN0_CnCFG[ RSCAN_FROM_RSCAN0_CnCFG_COUNT ] =
     9335    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     9336    RSCAN_FROM_RSCAN0_CnCFG_ADDRESS_LIST;
     9337    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     9338#endif  /* DECLARE_RSCAN_FROM_RSCAN0_CnCFG_CHANNELS */
     9339/* End of channel array defines of RSCAN0 (2)*/
     9340
     9341
    90359342/* <-SEC M1.10.1 */
     9343/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
    90369344/* <-QAC 0857 */
    90379345/* <-QAC 0639 */

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/rspi_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef RSPI_IODEFINE_H
    3030#define RSPI_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3134/* ->SEC M1.10.1 : Not magic number */
    3235
    33 #include "reg32_t.h"
    34 
    35 struct st_rspi
    36 {                                                          /* RSPI             */
     36#define RSPI0   (*(struct st_rspi    *)0xE800C800uL) /* RSPI0 */
     37#define RSPI1   (*(struct st_rspi    *)0xE800D000uL) /* RSPI1 */
     38#define RSPI2   (*(struct st_rspi    *)0xE800D800uL) /* RSPI2 */
     39#define RSPI3   (*(struct st_rspi    *)0xE800E000uL) /* RSPI3 */
     40#define RSPI4   (*(struct st_rspi    *)0xE800E800uL) /* RSPI4 */
     41
     42
     43/* Start of channel array defines of RSPI */
     44
     45/* Channel array defines of RSPI */
     46/*(Sample) value = RSPI[ channel ]->SPCR; */
     47#define RSPI_COUNT  (5)
     48#define RSPI_ADDRESS_LIST \
     49{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     50    &RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \
     51}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     52
     53/* End of channel array defines of RSPI */
     54
     55
     56#define SPCR_0 (RSPI0.SPCR)
     57#define SSLP_0 (RSPI0.SSLP)
     58#define SPPCR_0 (RSPI0.SPPCR)
     59#define SPSR_0 (RSPI0.SPSR)
     60#define SPDR_0   (RSPI0.SPDR.UINT32)
     61#define SPDR_0L  (RSPI0.SPDR.UINT16[R_IO_L])
     62#define SPDR_0H  (RSPI0.SPDR.UINT16[R_IO_H])
     63#define SPDR_0LL (RSPI0.SPDR.UINT8[R_IO_LL])
     64#define SPDR_0LH (RSPI0.SPDR.UINT8[R_IO_LH])
     65#define SPDR_0HL (RSPI0.SPDR.UINT8[R_IO_HL])
     66#define SPDR_0HH (RSPI0.SPDR.UINT8[R_IO_HH])
     67#define SPSCR_0 (RSPI0.SPSCR)
     68#define SPSSR_0 (RSPI0.SPSSR)
     69#define SPBR_0 (RSPI0.SPBR)
     70#define SPDCR_0 (RSPI0.SPDCR)
     71#define SPCKD_0 (RSPI0.SPCKD)
     72#define SSLND_0 (RSPI0.SSLND)
     73#define SPND_0 (RSPI0.SPND)
     74#define SPCMD0_0 (RSPI0.SPCMD0)
     75#define SPCMD1_0 (RSPI0.SPCMD1)
     76#define SPCMD2_0 (RSPI0.SPCMD2)
     77#define SPCMD3_0 (RSPI0.SPCMD3)
     78#define SPBFCR_0 (RSPI0.SPBFCR)
     79#define SPBFDR_0 (RSPI0.SPBFDR)
     80#define SPCR_1 (RSPI1.SPCR)
     81#define SSLP_1 (RSPI1.SSLP)
     82#define SPPCR_1 (RSPI1.SPPCR)
     83#define SPSR_1 (RSPI1.SPSR)
     84#define SPDR_1   (RSPI1.SPDR.UINT32)
     85#define SPDR_1L  (RSPI1.SPDR.UINT16[R_IO_L])
     86#define SPDR_1H  (RSPI1.SPDR.UINT16[R_IO_H])
     87#define SPDR_1LL (RSPI1.SPDR.UINT8[R_IO_LL])
     88#define SPDR_1LH (RSPI1.SPDR.UINT8[R_IO_LH])
     89#define SPDR_1HL (RSPI1.SPDR.UINT8[R_IO_HL])
     90#define SPDR_1HH (RSPI1.SPDR.UINT8[R_IO_HH])
     91#define SPSCR_1 (RSPI1.SPSCR)
     92#define SPSSR_1 (RSPI1.SPSSR)
     93#define SPBR_1 (RSPI1.SPBR)
     94#define SPDCR_1 (RSPI1.SPDCR)
     95#define SPCKD_1 (RSPI1.SPCKD)
     96#define SSLND_1 (RSPI1.SSLND)
     97#define SPND_1 (RSPI1.SPND)
     98#define SPCMD0_1 (RSPI1.SPCMD0)
     99#define SPCMD1_1 (RSPI1.SPCMD1)
     100#define SPCMD2_1 (RSPI1.SPCMD2)
     101#define SPCMD3_1 (RSPI1.SPCMD3)
     102#define SPBFCR_1 (RSPI1.SPBFCR)
     103#define SPBFDR_1 (RSPI1.SPBFDR)
     104#define SPCR_2 (RSPI2.SPCR)
     105#define SSLP_2 (RSPI2.SSLP)
     106#define SPPCR_2 (RSPI2.SPPCR)
     107#define SPSR_2 (RSPI2.SPSR)
     108#define SPDR_2   (RSPI2.SPDR.UINT32)
     109#define SPDR_2L  (RSPI2.SPDR.UINT16[R_IO_L])
     110#define SPDR_2H  (RSPI2.SPDR.UINT16[R_IO_H])
     111#define SPDR_2LL (RSPI2.SPDR.UINT8[R_IO_LL])
     112#define SPDR_2LH (RSPI2.SPDR.UINT8[R_IO_LH])
     113#define SPDR_2HL (RSPI2.SPDR.UINT8[R_IO_HL])
     114#define SPDR_2HH (RSPI2.SPDR.UINT8[R_IO_HH])
     115#define SPSCR_2 (RSPI2.SPSCR)
     116#define SPSSR_2 (RSPI2.SPSSR)
     117#define SPBR_2 (RSPI2.SPBR)
     118#define SPDCR_2 (RSPI2.SPDCR)
     119#define SPCKD_2 (RSPI2.SPCKD)
     120#define SSLND_2 (RSPI2.SSLND)
     121#define SPND_2 (RSPI2.SPND)
     122#define SPCMD0_2 (RSPI2.SPCMD0)
     123#define SPCMD1_2 (RSPI2.SPCMD1)
     124#define SPCMD2_2 (RSPI2.SPCMD2)
     125#define SPCMD3_2 (RSPI2.SPCMD3)
     126#define SPBFCR_2 (RSPI2.SPBFCR)
     127#define SPBFDR_2 (RSPI2.SPBFDR)
     128#define SPCR_3 (RSPI3.SPCR)
     129#define SSLP_3 (RSPI3.SSLP)
     130#define SPPCR_3 (RSPI3.SPPCR)
     131#define SPSR_3 (RSPI3.SPSR)
     132#define SPDR_3   (RSPI3.SPDR.UINT32)
     133#define SPDR_3L  (RSPI3.SPDR.UINT16[R_IO_L])
     134#define SPDR_3H  (RSPI3.SPDR.UINT16[R_IO_H])
     135#define SPDR_3LL (RSPI3.SPDR.UINT8[R_IO_LL])
     136#define SPDR_3LH (RSPI3.SPDR.UINT8[R_IO_LH])
     137#define SPDR_3HL (RSPI3.SPDR.UINT8[R_IO_HL])
     138#define SPDR_3HH (RSPI3.SPDR.UINT8[R_IO_HH])
     139#define SPSCR_3 (RSPI3.SPSCR)
     140#define SPSSR_3 (RSPI3.SPSSR)
     141#define SPBR_3 (RSPI3.SPBR)
     142#define SPDCR_3 (RSPI3.SPDCR)
     143#define SPCKD_3 (RSPI3.SPCKD)
     144#define SSLND_3 (RSPI3.SSLND)
     145#define SPND_3 (RSPI3.SPND)
     146#define SPCMD0_3 (RSPI3.SPCMD0)
     147#define SPCMD1_3 (RSPI3.SPCMD1)
     148#define SPCMD2_3 (RSPI3.SPCMD2)
     149#define SPCMD3_3 (RSPI3.SPCMD3)
     150#define SPBFCR_3 (RSPI3.SPBFCR)
     151#define SPBFDR_3 (RSPI3.SPBFDR)
     152#define SPCR_4 (RSPI4.SPCR)
     153#define SSLP_4 (RSPI4.SSLP)
     154#define SPPCR_4 (RSPI4.SPPCR)
     155#define SPSR_4 (RSPI4.SPSR)
     156#define SPDR_4   (RSPI4.SPDR.UINT32)
     157#define SPDR_4L  (RSPI4.SPDR.UINT16[R_IO_L])
     158#define SPDR_4H  (RSPI4.SPDR.UINT16[R_IO_H])
     159#define SPDR_4LL (RSPI4.SPDR.UINT8[R_IO_LL])
     160#define SPDR_4LH (RSPI4.SPDR.UINT8[R_IO_LH])
     161#define SPDR_4HL (RSPI4.SPDR.UINT8[R_IO_HL])
     162#define SPDR_4HH (RSPI4.SPDR.UINT8[R_IO_HH])
     163#define SPSCR_4 (RSPI4.SPSCR)
     164#define SPSSR_4 (RSPI4.SPSSR)
     165#define SPBR_4 (RSPI4.SPBR)
     166#define SPDCR_4 (RSPI4.SPDCR)
     167#define SPCKD_4 (RSPI4.SPCKD)
     168#define SSLND_4 (RSPI4.SSLND)
     169#define SPND_4 (RSPI4.SPND)
     170#define SPCMD0_4 (RSPI4.SPCMD0)
     171#define SPCMD1_4 (RSPI4.SPCMD1)
     172#define SPCMD2_4 (RSPI4.SPCMD2)
     173#define SPCMD3_4 (RSPI4.SPCMD3)
     174#define SPBFCR_4 (RSPI4.SPBFCR)
     175#define SPBFDR_4 (RSPI4.SPBFDR)
     176
     177#define SPCMD_COUNT (4)
     178
     179
     180typedef struct st_rspi
     181{
     182                                                           /* RSPI             */
    37183    volatile uint8_t   SPCR;                                   /*  SPCR            */
    38184    volatile uint8_t   SSLP;                                   /*  SSLP            */
    39185    volatile uint8_t   SPPCR;                                  /*  SPPCR           */
    40186    volatile uint8_t   SPSR;                                   /*  SPSR            */
    41     union reg32_t  SPDR;                          /*  SPDR            */
     187    union iodefine_reg32_t  SPDR;                          /*  SPDR            */
    42188   
    43189    volatile uint8_t   SPSCR;                                  /*  SPSCR           */
    … …  
    49195    volatile uint8_t   SPND;                                   /*  SPND            */
    50196    volatile uint8_t   dummy1[1];                              /*                  */
    51 #define SPCMD_COUNT 4
     197
     198/* #define SPCMD_COUNT (4) */
    52199    volatile uint16_t SPCMD0;                                 /*  SPCMD0          */
    53200    volatile uint16_t SPCMD1;                                 /*  SPCMD1          */
    … …  
    58205    volatile uint8_t   dummy3[1];                              /*                  */
    59206    volatile uint16_t SPBFDR;                                 /*  SPBFDR          */
    60 };
    61 
    62 
    63 #define RSPI0   (*(struct st_rspi    *)0xE800C800uL) /* RSPI0 */
    64 #define RSPI1   (*(struct st_rspi    *)0xE800D000uL) /* RSPI1 */
    65 #define RSPI2   (*(struct st_rspi    *)0xE800D800uL) /* RSPI2 */
    66 #define RSPI3   (*(struct st_rspi    *)0xE800E000uL) /* RSPI3 */
    67 #define RSPI4   (*(struct st_rspi    *)0xE800E800uL) /* RSPI4 */
    68 
    69 
    70 /* Start of channnel array defines of RSPI */
    71 
    72 /* Channnel array defines of RSPI */
    73 /*(Sample) value = RSPI[ channel ]->SPCR; */
    74 #define RSPI_COUNT  5
    75 #define RSPI_ADDRESS_LIST \
    76 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    77     &RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \
    78 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    79 
    80 /* End of channnel array defines of RSPI */
    81 
    82 
    83 #define SPCR_0 RSPI0.SPCR
    84 #define SSLP_0 RSPI0.SSLP
    85 #define SPPCR_0 RSPI0.SPPCR
    86 #define SPSR_0 RSPI0.SPSR
    87 #define SPDR_0   RSPI0.SPDR.UINT32
    88 #define SPDR_0L  RSPI0.SPDR.UINT16[L]
    89 #define SPDR_0H  RSPI0.SPDR.UINT16[H]
    90 #define SPDR_0LL RSPI0.SPDR.UINT8[LL]
    91 #define SPDR_0LH RSPI0.SPDR.UINT8[LH]
    92 #define SPDR_0HL RSPI0.SPDR.UINT8[HL]
    93 #define SPDR_0HH RSPI0.SPDR.UINT8[HH]
    94 #define SPSCR_0 RSPI0.SPSCR
    95 #define SPSSR_0 RSPI0.SPSSR
    96 #define SPBR_0 RSPI0.SPBR
    97 #define SPDCR_0 RSPI0.SPDCR
    98 #define SPCKD_0 RSPI0.SPCKD
    99 #define SSLND_0 RSPI0.SSLND
    100 #define SPND_0 RSPI0.SPND
    101 #define SPCMD0_0 RSPI0.SPCMD0
    102 #define SPCMD1_0 RSPI0.SPCMD1
    103 #define SPCMD2_0 RSPI0.SPCMD2
    104 #define SPCMD3_0 RSPI0.SPCMD3
    105 #define SPBFCR_0 RSPI0.SPBFCR
    106 #define SPBFDR_0 RSPI0.SPBFDR
    107 #define SPCR_1 RSPI1.SPCR
    108 #define SSLP_1 RSPI1.SSLP
    109 #define SPPCR_1 RSPI1.SPPCR
    110 #define SPSR_1 RSPI1.SPSR
    111 #define SPDR_1   RSPI1.SPDR.UINT32
    112 #define SPDR_1L  RSPI1.SPDR.UINT16[L]
    113 #define SPDR_1H  RSPI1.SPDR.UINT16[H]
    114 #define SPDR_1LL RSPI1.SPDR.UINT8[LL]
    115 #define SPDR_1LH RSPI1.SPDR.UINT8[LH]
    116 #define SPDR_1HL RSPI1.SPDR.UINT8[HL]
    117 #define SPDR_1HH RSPI1.SPDR.UINT8[HH]
    118 #define SPSCR_1 RSPI1.SPSCR
    119 #define SPSSR_1 RSPI1.SPSSR
    120 #define SPBR_1 RSPI1.SPBR
    121 #define SPDCR_1 RSPI1.SPDCR
    122 #define SPCKD_1 RSPI1.SPCKD
    123 #define SSLND_1 RSPI1.SSLND
    124 #define SPND_1 RSPI1.SPND
    125 #define SPCMD0_1 RSPI1.SPCMD0
    126 #define SPCMD1_1 RSPI1.SPCMD1
    127 #define SPCMD2_1 RSPI1.SPCMD2
    128 #define SPCMD3_1 RSPI1.SPCMD3
    129 #define SPBFCR_1 RSPI1.SPBFCR
    130 #define SPBFDR_1 RSPI1.SPBFDR
    131 #define SPCR_2 RSPI2.SPCR
    132 #define SSLP_2 RSPI2.SSLP
    133 #define SPPCR_2 RSPI2.SPPCR
    134 #define SPSR_2 RSPI2.SPSR
    135 #define SPDR_2   RSPI2.SPDR.UINT32
    136 #define SPDR_2L  RSPI2.SPDR.UINT16[L]
    137 #define SPDR_2H  RSPI2.SPDR.UINT16[H]
    138 #define SPDR_2LL RSPI2.SPDR.UINT8[LL]
    139 #define SPDR_2LH RSPI2.SPDR.UINT8[LH]
    140 #define SPDR_2HL RSPI2.SPDR.UINT8[HL]
    141 #define SPDR_2HH RSPI2.SPDR.UINT8[HH]
    142 #define SPSCR_2 RSPI2.SPSCR
    143 #define SPSSR_2 RSPI2.SPSSR
    144 #define SPBR_2 RSPI2.SPBR
    145 #define SPDCR_2 RSPI2.SPDCR
    146 #define SPCKD_2 RSPI2.SPCKD
    147 #define SSLND_2 RSPI2.SSLND
    148 #define SPND_2 RSPI2.SPND
    149 #define SPCMD0_2 RSPI2.SPCMD0
    150 #define SPCMD1_2 RSPI2.SPCMD1
    151 #define SPCMD2_2 RSPI2.SPCMD2
    152 #define SPCMD3_2 RSPI2.SPCMD3
    153 #define SPBFCR_2 RSPI2.SPBFCR
    154 #define SPBFDR_2 RSPI2.SPBFDR
    155 #define SPCR_3 RSPI3.SPCR
    156 #define SSLP_3 RSPI3.SSLP
    157 #define SPPCR_3 RSPI3.SPPCR
    158 #define SPSR_3 RSPI3.SPSR
    159 #define SPDR_3   RSPI3.SPDR.UINT32
    160 #define SPDR_3L  RSPI3.SPDR.UINT16[L]
    161 #define SPDR_3H  RSPI3.SPDR.UINT16[H]
    162 #define SPDR_3LL RSPI3.SPDR.UINT8[LL]
    163 #define SPDR_3LH RSPI3.SPDR.UINT8[LH]
    164 #define SPDR_3HL RSPI3.SPDR.UINT8[HL]
    165 #define SPDR_3HH RSPI3.SPDR.UINT8[HH]
    166 #define SPSCR_3 RSPI3.SPSCR
    167 #define SPSSR_3 RSPI3.SPSSR
    168 #define SPBR_3 RSPI3.SPBR
    169 #define SPDCR_3 RSPI3.SPDCR
    170 #define SPCKD_3 RSPI3.SPCKD
    171 #define SSLND_3 RSPI3.SSLND
    172 #define SPND_3 RSPI3.SPND
    173 #define SPCMD0_3 RSPI3.SPCMD0
    174 #define SPCMD1_3 RSPI3.SPCMD1
    175 #define SPCMD2_3 RSPI3.SPCMD2
    176 #define SPCMD3_3 RSPI3.SPCMD3
    177 #define SPBFCR_3 RSPI3.SPBFCR
    178 #define SPBFDR_3 RSPI3.SPBFDR
    179 #define SPCR_4 RSPI4.SPCR
    180 #define SSLP_4 RSPI4.SSLP
    181 #define SPPCR_4 RSPI4.SPPCR
    182 #define SPSR_4 RSPI4.SPSR
    183 #define SPDR_4   RSPI4.SPDR.UINT32
    184 #define SPDR_4L  RSPI4.SPDR.UINT16[L]
    185 #define SPDR_4H  RSPI4.SPDR.UINT16[H]
    186 #define SPDR_4LL RSPI4.SPDR.UINT8[LL]
    187 #define SPDR_4LH RSPI4.SPDR.UINT8[LH]
    188 #define SPDR_4HL RSPI4.SPDR.UINT8[HL]
    189 #define SPDR_4HH RSPI4.SPDR.UINT8[HH]
    190 #define SPSCR_4 RSPI4.SPSCR
    191 #define SPSSR_4 RSPI4.SPSSR
    192 #define SPBR_4 RSPI4.SPBR
    193 #define SPDCR_4 RSPI4.SPDCR
    194 #define SPCKD_4 RSPI4.SPCKD
    195 #define SSLND_4 RSPI4.SSLND
    196 #define SPND_4 RSPI4.SPND
    197 #define SPCMD0_4 RSPI4.SPCMD0
    198 #define SPCMD1_4 RSPI4.SPCMD1
    199 #define SPCMD2_4 RSPI4.SPCMD2
    200 #define SPCMD3_4 RSPI4.SPCMD3
    201 #define SPBFCR_4 RSPI4.SPBFCR
    202 #define SPBFDR_4 RSPI4.SPBFDR
     207} r_io_rspi_t;
     208
     209
     210/* Channel array defines of RSPI (2)*/
     211#ifdef  DECLARE_RSPI_CHANNELS
     212volatile struct st_rspi*  RSPI[ RSPI_COUNT ] =
     213    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     214    RSPI_ADDRESS_LIST;
     215    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     216#endif  /* DECLARE_RSPI_CHANNELS */
     217/* End of channel array defines of RSPI (2)*/
     218
     219
    203220/* <-SEC M1.10.1 */
     221/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     222/* <-QAC 0857 */
     223/* <-QAC 0639 */
    204224#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/rtc_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef RTC_IODEFINE_H
    3030#define RTC_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3134/* ->SEC M1.10.1 : Not magic number */
    3235
    33 struct st_rtc
    34 {                                                          /* RTC              */
     36#define RTC     (*(struct st_rtc     *)0xFCFF1000uL) /* RTC */
     37
     38
     39#define RTCR64CNT (RTC.R64CNT)
     40#define RTCRSECCNT (RTC.RSECCNT)
     41#define RTCRMINCNT (RTC.RMINCNT)
     42#define RTCRHRCNT (RTC.RHRCNT)
     43#define RTCRWKCNT (RTC.RWKCNT)
     44#define RTCRDAYCNT (RTC.RDAYCNT)
     45#define RTCRMONCNT (RTC.RMONCNT)
     46#define RTCRYRCNT (RTC.RYRCNT)
     47#define RTCRSECAR (RTC.RSECAR)
     48#define RTCRMINAR (RTC.RMINAR)
     49#define RTCRHRAR (RTC.RHRAR)
     50#define RTCRWKAR (RTC.RWKAR)
     51#define RTCRDAYAR (RTC.RDAYAR)
     52#define RTCRMONAR (RTC.RMONAR)
     53#define RTCRCR1 (RTC.RCR1)
     54#define RTCRCR2 (RTC.RCR2)
     55#define RTCRYRAR (RTC.RYRAR)
     56#define RTCRCR3 (RTC.RCR3)
     57#define RTCRCR5 (RTC.RCR5)
     58#define RTCRFRH (RTC.RFRH)
     59#define RTCRFRL (RTC.RFRL)
     60
     61
     62typedef struct st_rtc
     63{
     64                                                           /* RTC              */
    3565    volatile uint8_t   R64CNT;                                 /*  R64CNT          */
    3666    volatile uint8_t   dummy537[1];                            /*                  */
    … …  
    72102    volatile uint16_t RFRH;                                   /*  RFRH            */
    73103    volatile uint16_t RFRL;                                   /*  RFRL            */
    74 };
     104} r_io_rtc_t;
    75105
    76106
    77 #define RTC     (*(struct st_rtc     *)0xFCFF1000uL) /* RTC */
    78 
    79 
    80 #define RTCR64CNT RTC.R64CNT
    81 #define RTCRSECCNT RTC.RSECCNT
    82 #define RTCRMINCNT RTC.RMINCNT
    83 #define RTCRHRCNT RTC.RHRCNT
    84 #define RTCRWKCNT RTC.RWKCNT
    85 #define RTCRDAYCNT RTC.RDAYCNT
    86 #define RTCRMONCNT RTC.RMONCNT
    87 #define RTCRYRCNT RTC.RYRCNT
    88 #define RTCRSECAR RTC.RSECAR
    89 #define RTCRMINAR RTC.RMINAR
    90 #define RTCRHRAR RTC.RHRAR
    91 #define RTCRWKAR RTC.RWKAR
    92 #define RTCRDAYAR RTC.RDAYAR
    93 #define RTCRMONAR RTC.RMONAR
    94 #define RTCRCR1 RTC.RCR1
    95 #define RTCRCR2 RTC.RCR2
    96 #define RTCRYRAR RTC.RYRAR
    97 #define RTCRCR3 RTC.RCR3
    98 #define RTCRCR5 RTC.RCR5
    99 #define RTCRFRH RTC.RFRH
    100 #define RTCRFRL RTC.RFRL
    101107/* <-SEC M1.10.1 */
     108/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     109/* <-QAC 0857 */
     110/* <-QAC 0639 */
    102111#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/scif_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef SCIF_IODEFINE_H
    3030#define SCIF_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
    3132/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3234/* ->SEC M1.10.1 : Not magic number */
    3335
    34 struct st_scif
    35 {                                                          /* SCIF             */
     36#define SCIF0   (*(struct st_scif    *)0xE8007000uL) /* SCIF0 */
     37#define SCIF1   (*(struct st_scif    *)0xE8007800uL) /* SCIF1 */
     38#define SCIF2   (*(struct st_scif    *)0xE8008000uL) /* SCIF2 */
     39#define SCIF3   (*(struct st_scif    *)0xE8008800uL) /* SCIF3 */
     40#define SCIF4   (*(struct st_scif    *)0xE8009000uL) /* SCIF4 */
     41#define SCIF5   (*(struct st_scif    *)0xE8009800uL) /* SCIF5 */
     42#define SCIF6   (*(struct st_scif    *)0xE800A000uL) /* SCIF6 */
     43#define SCIF7   (*(struct st_scif    *)0xE800A800uL) /* SCIF7 */
     44
     45
     46/* Start of channel array defines of SCIF */
     47
     48/* Channel array defines of SCIF */
     49/*(Sample) value = SCIF[ channel ]->SCSMR; */
     50#define SCIF_COUNT  (8)
     51#define SCIF_ADDRESS_LIST \
     52{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     53    &SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4, &SCIF5, &SCIF6, &SCIF7 \
     54}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     55
     56/* End of channel array defines of SCIF */
     57
     58
     59#define SCSMR_0 (SCIF0.SCSMR)
     60#define SCBRR_0 (SCIF0.SCBRR)
     61#define SCSCR_0 (SCIF0.SCSCR)
     62#define SCFTDR_0 (SCIF0.SCFTDR)
     63#define SCFSR_0 (SCIF0.SCFSR)
     64#define SCFRDR_0 (SCIF0.SCFRDR)
     65#define SCFCR_0 (SCIF0.SCFCR)
     66#define SCFDR_0 (SCIF0.SCFDR)
     67#define SCSPTR_0 (SCIF0.SCSPTR)
     68#define SCLSR_0 (SCIF0.SCLSR)
     69#define SCEMR_0 (SCIF0.SCEMR)
     70#define SCSMR_1 (SCIF1.SCSMR)
     71#define SCBRR_1 (SCIF1.SCBRR)
     72#define SCSCR_1 (SCIF1.SCSCR)
     73#define SCFTDR_1 (SCIF1.SCFTDR)
     74#define SCFSR_1 (SCIF1.SCFSR)
     75#define SCFRDR_1 (SCIF1.SCFRDR)
     76#define SCFCR_1 (SCIF1.SCFCR)
     77#define SCFDR_1 (SCIF1.SCFDR)
     78#define SCSPTR_1 (SCIF1.SCSPTR)
     79#define SCLSR_1 (SCIF1.SCLSR)
     80#define SCEMR_1 (SCIF1.SCEMR)
     81#define SCSMR_2 (SCIF2.SCSMR)
     82#define SCBRR_2 (SCIF2.SCBRR)
     83#define SCSCR_2 (SCIF2.SCSCR)
     84#define SCFTDR_2 (SCIF2.SCFTDR)
     85#define SCFSR_2 (SCIF2.SCFSR)
     86#define SCFRDR_2 (SCIF2.SCFRDR)
     87#define SCFCR_2 (SCIF2.SCFCR)
     88#define SCFDR_2 (SCIF2.SCFDR)
     89#define SCSPTR_2 (SCIF2.SCSPTR)
     90#define SCLSR_2 (SCIF2.SCLSR)
     91#define SCEMR_2 (SCIF2.SCEMR)
     92#define SCSMR_3 (SCIF3.SCSMR)
     93#define SCBRR_3 (SCIF3.SCBRR)
     94#define SCSCR_3 (SCIF3.SCSCR)
     95#define SCFTDR_3 (SCIF3.SCFTDR)
     96#define SCFSR_3 (SCIF3.SCFSR)
     97#define SCFRDR_3 (SCIF3.SCFRDR)
     98#define SCFCR_3 (SCIF3.SCFCR)
     99#define SCFDR_3 (SCIF3.SCFDR)
     100#define SCSPTR_3 (SCIF3.SCSPTR)
     101#define SCLSR_3 (SCIF3.SCLSR)
     102#define SCEMR_3 (SCIF3.SCEMR)
     103#define SCSMR_4 (SCIF4.SCSMR)
     104#define SCBRR_4 (SCIF4.SCBRR)
     105#define SCSCR_4 (SCIF4.SCSCR)
     106#define SCFTDR_4 (SCIF4.SCFTDR)
     107#define SCFSR_4 (SCIF4.SCFSR)
     108#define SCFRDR_4 (SCIF4.SCFRDR)
     109#define SCFCR_4 (SCIF4.SCFCR)
     110#define SCFDR_4 (SCIF4.SCFDR)
     111#define SCSPTR_4 (SCIF4.SCSPTR)
     112#define SCLSR_4 (SCIF4.SCLSR)
     113#define SCEMR_4 (SCIF4.SCEMR)
     114#define SCSMR_5 (SCIF5.SCSMR)
     115#define SCBRR_5 (SCIF5.SCBRR)
     116#define SCSCR_5 (SCIF5.SCSCR)
     117#define SCFTDR_5 (SCIF5.SCFTDR)
     118#define SCFSR_5 (SCIF5.SCFSR)
     119#define SCFRDR_5 (SCIF5.SCFRDR)
     120#define SCFCR_5 (SCIF5.SCFCR)
     121#define SCFDR_5 (SCIF5.SCFDR)
     122#define SCSPTR_5 (SCIF5.SCSPTR)
     123#define SCLSR_5 (SCIF5.SCLSR)
     124#define SCEMR_5 (SCIF5.SCEMR)
     125#define SCSMR_6 (SCIF6.SCSMR)
     126#define SCBRR_6 (SCIF6.SCBRR)
     127#define SCSCR_6 (SCIF6.SCSCR)
     128#define SCFTDR_6 (SCIF6.SCFTDR)
     129#define SCFSR_6 (SCIF6.SCFSR)
     130#define SCFRDR_6 (SCIF6.SCFRDR)
     131#define SCFCR_6 (SCIF6.SCFCR)
     132#define SCFDR_6 (SCIF6.SCFDR)
     133#define SCSPTR_6 (SCIF6.SCSPTR)
     134#define SCLSR_6 (SCIF6.SCLSR)
     135#define SCEMR_6 (SCIF6.SCEMR)
     136#define SCSMR_7 (SCIF7.SCSMR)
     137#define SCBRR_7 (SCIF7.SCBRR)
     138#define SCSCR_7 (SCIF7.SCSCR)
     139#define SCFTDR_7 (SCIF7.SCFTDR)
     140#define SCFSR_7 (SCIF7.SCFSR)
     141#define SCFRDR_7 (SCIF7.SCFRDR)
     142#define SCFCR_7 (SCIF7.SCFCR)
     143#define SCFDR_7 (SCIF7.SCFDR)
     144#define SCSPTR_7 (SCIF7.SCSPTR)
     145#define SCLSR_7 (SCIF7.SCLSR)
     146#define SCEMR_7 (SCIF7.SCEMR)
     147
     148
     149typedef struct st_scif
     150{
     151                                                           /* SCIF             */
    36152    volatile uint16_t SCSMR;                                  /*  SCSMR           */
    37153    volatile uint8_t   dummy1[2];                              /*                  */
    … …  
    55171    volatile uint8_t   dummy10[2];                             /*                  */
    56172    volatile uint16_t SCEMR;                                  /*  SCEMR           */
    57 };
     173} r_io_scif_t;
    58174
    59175
    60 #define SCIF0   (*(struct st_scif    *)0xE8007000uL) /* SCIF0 */
    61 #define SCIF1   (*(struct st_scif    *)0xE8007800uL) /* SCIF1 */
    62 #define SCIF2   (*(struct st_scif    *)0xE8008000uL) /* SCIF2 */
    63 #define SCIF3   (*(struct st_scif    *)0xE8008800uL) /* SCIF3 */
    64 #define SCIF4   (*(struct st_scif    *)0xE8009000uL) /* SCIF4 */
    65 #define SCIF5   (*(struct st_scif    *)0xE8009800uL) /* SCIF5 */
    66 #define SCIF6   (*(struct st_scif    *)0xE800A000uL) /* SCIF6 */
    67 #define SCIF7   (*(struct st_scif    *)0xE800A800uL) /* SCIF7 */
    68 
    69 #define P_SCIF0   (0xE8007000uL) /* SCIF0 */
    70 #define P_SCIF1   (0xE8007800uL) /* SCIF1 */
    71 #define P_SCIF2   (0xE8008000uL) /* SCIF2 */
    72 #define P_SCIF3   (0xE8008800uL) /* SCIF3 */
    73 #define P_SCIF4   (0xE8009000uL) /* SCIF4 */
    74 #define P_SCIF5   (0xE8009800uL) /* SCIF5 */
    75 #define P_SCIF6   (0xE800A000uL) /* SCIF6 */
    76 #define P_SCIF7   (0xE800A800uL) /* SCIF7 */
     176/* Channel array defines of SCIF (2)*/
     177#ifdef  DECLARE_SCIF_CHANNELS
     178volatile struct st_scif*  SCIF[ SCIF_COUNT ] =
     179    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     180    SCIF_ADDRESS_LIST;
     181    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     182#endif  /* DECLARE_SCIF_CHANNELS */
     183/* End of channel array defines of SCIF (2)*/
    77184
    78185
    79 /* Start of channnel array defines of SCIF */
    80 
    81 /* Channnel array defines of SCIF */
    82 /*(Sample) value = SCIF[ channel ]->SCSMR; */
    83 #define SCIF_COUNT  8
    84 #define SCIF_ADDRESS_LIST \
    85 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    86     &SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4, &SCIF5, &SCIF6, &SCIF7 \
    87 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    88 
    89 /* End of channnel array defines of SCIF */
    90 
    91 
    92 #define SCSMR_0 SCIF0.SCSMR
    93 #define SCBRR_0 SCIF0.SCBRR
    94 #define SCSCR_0 SCIF0.SCSCR
    95 #define SCFTDR_0 SCIF0.SCFTDR
    96 #define SCFSR_0 SCIF0.SCFSR
    97 #define SCFRDR_0 SCIF0.SCFRDR
    98 #define SCFCR_0 SCIF0.SCFCR
    99 #define SCFDR_0 SCIF0.SCFDR
    100 #define SCSPTR_0 SCIF0.SCSPTR
    101 #define SCLSR_0 SCIF0.SCLSR
    102 #define SCEMR_0 SCIF0.SCEMR
    103 #define SCSMR_1 SCIF1.SCSMR
    104 #define SCBRR_1 SCIF1.SCBRR
    105 #define SCSCR_1 SCIF1.SCSCR
    106 #define SCFTDR_1 SCIF1.SCFTDR
    107 #define SCFSR_1 SCIF1.SCFSR
    108 #define SCFRDR_1 SCIF1.SCFRDR
    109 #define SCFCR_1 SCIF1.SCFCR
    110 #define SCFDR_1 SCIF1.SCFDR
    111 #define SCSPTR_1 SCIF1.SCSPTR
    112 #define SCLSR_1 SCIF1.SCLSR
    113 #define SCEMR_1 SCIF1.SCEMR
    114 #define SCSMR_2 SCIF2.SCSMR
    115 #define SCBRR_2 SCIF2.SCBRR
    116 #define SCSCR_2 SCIF2.SCSCR
    117 #define SCFTDR_2 SCIF2.SCFTDR
    118 #define SCFSR_2 SCIF2.SCFSR
    119 #define SCFRDR_2 SCIF2.SCFRDR
    120 #define SCFCR_2 SCIF2.SCFCR
    121 #define SCFDR_2 SCIF2.SCFDR
    122 #define SCSPTR_2 SCIF2.SCSPTR
    123 #define SCLSR_2 SCIF2.SCLSR
    124 #define SCEMR_2 SCIF2.SCEMR
    125 #define SCSMR_3 SCIF3.SCSMR
    126 #define SCBRR_3 SCIF3.SCBRR
    127 #define SCSCR_3 SCIF3.SCSCR
    128 #define SCFTDR_3 SCIF3.SCFTDR
    129 #define SCFSR_3 SCIF3.SCFSR
    130 #define SCFRDR_3 SCIF3.SCFRDR
    131 #define SCFCR_3 SCIF3.SCFCR
    132 #define SCFDR_3 SCIF3.SCFDR
    133 #define SCSPTR_3 SCIF3.SCSPTR
    134 #define SCLSR_3 SCIF3.SCLSR
    135 #define SCEMR_3 SCIF3.SCEMR
    136 #define SCSMR_4 SCIF4.SCSMR
    137 #define SCBRR_4 SCIF4.SCBRR
    138 #define SCSCR_4 SCIF4.SCSCR
    139 #define SCFTDR_4 SCIF4.SCFTDR
    140 #define SCFSR_4 SCIF4.SCFSR
    141 #define SCFRDR_4 SCIF4.SCFRDR
    142 #define SCFCR_4 SCIF4.SCFCR
    143 #define SCFDR_4 SCIF4.SCFDR
    144 #define SCSPTR_4 SCIF4.SCSPTR
    145 #define SCLSR_4 SCIF4.SCLSR
    146 #define SCEMR_4 SCIF4.SCEMR
    147 #define SCSMR_5 SCIF5.SCSMR
    148 #define SCBRR_5 SCIF5.SCBRR
    149 #define SCSCR_5 SCIF5.SCSCR
    150 #define SCFTDR_5 SCIF5.SCFTDR
    151 #define SCFSR_5 SCIF5.SCFSR
    152 #define SCFRDR_5 SCIF5.SCFRDR
    153 #define SCFCR_5 SCIF5.SCFCR
    154 #define SCFDR_5 SCIF5.SCFDR
    155 #define SCSPTR_5 SCIF5.SCSPTR
    156 #define SCLSR_5 SCIF5.SCLSR
    157 #define SCEMR_5 SCIF5.SCEMR
    158 #define SCSMR_6 SCIF6.SCSMR
    159 #define SCBRR_6 SCIF6.SCBRR
    160 #define SCSCR_6 SCIF6.SCSCR
    161 #define SCFTDR_6 SCIF6.SCFTDR
    162 #define SCFSR_6 SCIF6.SCFSR
    163 #define SCFRDR_6 SCIF6.SCFRDR
    164 #define SCFCR_6 SCIF6.SCFCR
    165 #define SCFDR_6 SCIF6.SCFDR
    166 #define SCSPTR_6 SCIF6.SCSPTR
    167 #define SCLSR_6 SCIF6.SCLSR
    168 #define SCEMR_6 SCIF6.SCEMR
    169 #define SCSMR_7 SCIF7.SCSMR
    170 #define SCBRR_7 SCIF7.SCBRR
    171 #define SCSCR_7 SCIF7.SCSCR
    172 #define SCFTDR_7 SCIF7.SCFTDR
    173 #define SCFSR_7 SCIF7.SCFSR
    174 #define SCFRDR_7 SCIF7.SCFRDR
    175 #define SCFCR_7 SCIF7.SCFCR
    176 #define SCFDR_7 SCIF7.SCFDR
    177 #define SCSPTR_7 SCIF7.SCSPTR
    178 #define SCLSR_7 SCIF7.SCLSR
    179 #define SCEMR_7 SCIF7.SCEMR
    180186/* <-SEC M1.10.1 */
     187/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
    181188/* <-QAC 0857 */
     189/* <-QAC 0639 */
    182190#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/scim_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef SCIM_IODEFINE_H
    3030#define SCIM_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3134/* ->SEC M1.10.1 : Not magic number */
    3235
    33 struct st_scim
    34 {                                                          /* SCIM             */
     36#define SCIM0   (*(struct st_scim    *)0xE800B000uL) /* SCIM0 */
     37#define SCIM1   (*(struct st_scim    *)0xE800B800uL) /* SCIM1 */
     38
     39
     40/* Start of channel array defines of SCIM */
     41
     42/* Channel array defines of SCIM */
     43/*(Sample) value = SCIM[ channel ]->SMR; */
     44#define SCIM_COUNT  (2)
     45#define SCIM_ADDRESS_LIST \
     46{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     47    &SCIM0, &SCIM1 \
     48}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     49
     50/* End of channel array defines of SCIM */
     51
     52
     53#define SMR0 (SCIM0.SMR)
     54#define BRR0 (SCIM0.BRR)
     55#define SCR0 (SCIM0.SCR)
     56#define TDR0 (SCIM0.TDR)
     57#define SSR0 (SCIM0.SSR)
     58#define RDR0 (SCIM0.RDR)
     59#define SCMR0 (SCIM0.SCMR)
     60#define SEMR0 (SCIM0.SEMR)
     61#define SNFR0 (SCIM0.SNFR)
     62#define SECR0 (SCIM0.SECR)
     63#define SMR1 (SCIM1.SMR)
     64#define BRR1 (SCIM1.BRR)
     65#define SCR1 (SCIM1.SCR)
     66#define TDR1 (SCIM1.TDR)
     67#define SSR1 (SCIM1.SSR)
     68#define RDR1 (SCIM1.RDR)
     69#define SCMR1 (SCIM1.SCMR)
     70#define SEMR1 (SCIM1.SEMR)
     71#define SNFR1 (SCIM1.SNFR)
     72#define SECR1 (SCIM1.SECR)
     73
     74
     75typedef struct st_scim
     76{
     77                                                           /* SCIM             */
    3578    volatile uint8_t   SMR;                                    /*  SMR             */
    3679    volatile uint8_t   BRR;                                    /*  BRR             */
    … …  
    4487    volatile uint8_t   dummy1[4];                              /*                  */
    4588    volatile uint8_t   SECR;                                   /*  SECR            */
    46 };
     89} r_io_scim_t;
    4790
    4891
    49 #define SCIM0   (*(struct st_scim    *)0xE800B000uL) /* SCIM0 */
    50 #define SCIM1   (*(struct st_scim    *)0xE800B800uL) /* SCIM1 */
     92/* Channel array defines of SCIM (2)*/
     93#ifdef  DECLARE_SCIM_CHANNELS
     94volatile struct st_scim*  SCIM[ SCIM_COUNT ] =
     95    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     96    SCIM_ADDRESS_LIST;
     97    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     98#endif  /* DECLARE_SCIM_CHANNELS */
     99/* End of channel array defines of SCIM (2)*/
    51100
    52101
    53 /* Start of channnel array defines of SCIM */
    54 
    55 /* Channnel array defines of SCIM */
    56 /*(Sample) value = SCIM[ channel ]->SMR; */
    57 #define SCIM_COUNT  2
    58 #define SCIM_ADDRESS_LIST \
    59 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    60     &SCIM0, &SCIM1 \
    61 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    62 
    63 /* End of channnel array defines of SCIM */
    64 
    65 
    66 #define SMR0 SCIM0.SMR
    67 #define BRR0 SCIM0.BRR
    68 #define SCR0 SCIM0.SCR
    69 #define TDR0 SCIM0.TDR
    70 #define SSR0 SCIM0.SSR
    71 #define RDR0 SCIM0.RDR
    72 #define SCMR0 SCIM0.SCMR
    73 #define SEMR0 SCIM0.SEMR
    74 #define SNFR0 SCIM0.SNFR
    75 #define SECR0 SCIM0.SECR
    76 #define SMR1 SCIM1.SMR
    77 #define BRR1 SCIM1.BRR
    78 #define SCR1 SCIM1.SCR
    79 #define TDR1 SCIM1.TDR
    80 #define SSR1 SCIM1.SSR
    81 #define RDR1 SCIM1.RDR
    82 #define SCMR1 SCIM1.SCMR
    83 #define SEMR1 SCIM1.SEMR
    84 #define SNFR1 SCIM1.SNFR
    85 #define SECR1 SCIM1.SECR
    86102/* <-SEC M1.10.1 */
     103/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     104/* <-QAC 0857 */
     105/* <-QAC 0639 */
    87106#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/scux_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef SCUX_IODEFINE_H
    3030#define SCUX_IODEFINE_H
    3131/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3234/* ->SEC M1.10.1 : Not magic number */
    3335
    34 struct st_scux
    35 {                                                          /* SCUX             */
     36#define SCUX    (*(struct st_scux    *)0xE8208000uL) /* SCUX */
     37
     38
     39/* Start of channel array defines of SCUX */
     40
     41/* Channel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */
     42/*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */
     43#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT  (4)
     44#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \
     45{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     46    &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \
     47}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     48#define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */
     49#define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */
     50#define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */
     51#define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */
     52
     53
     54/* Channel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */
     55/*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */
     56#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT  (2)
     57#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \
     58{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     59    &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \
     60}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     61#define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */
     62#define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */
     63
     64
     65/* Channel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */
     66/*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */
     67#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT  (4)
     68#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \
     69{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     70    &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \
     71}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     72#define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */
     73#define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */
     74#define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */
     75#define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */
     76
     77
     78/* Channel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */
     79/*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */
     80#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT  (4)
     81#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \
     82{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     83    &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \
     84}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     85#define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */
     86#define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */
     87#define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */
     88#define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */
     89
     90
     91/* Channel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */
     92/*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */
     93#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT  (4)
     94#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \
     95{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     96    &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \
     97}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     98#define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */
     99#define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */
     100#define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */
     101#define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */
     102
     103
     104/* Channel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */
     105/*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */
     106#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT  (4)
     107#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \
     108{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     109    &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \
     110}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     111#define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */
     112#define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */
     113#define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */
     114#define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */
     115
     116/* End of channel array defines of SCUX */
     117
     118
     119#define SCUXIPCIR_IPC0_0 (SCUX.IPCIR_IPC0_0)
     120#define SCUXIPSLR_IPC0_0 (SCUX.IPSLR_IPC0_0)
     121#define SCUXIPCIR_IPC0_1 (SCUX.IPCIR_IPC0_1)
     122#define SCUXIPSLR_IPC0_1 (SCUX.IPSLR_IPC0_1)
     123#define SCUXIPCIR_IPC0_2 (SCUX.IPCIR_IPC0_2)
     124#define SCUXIPSLR_IPC0_2 (SCUX.IPSLR_IPC0_2)
     125#define SCUXIPCIR_IPC0_3 (SCUX.IPCIR_IPC0_3)
     126#define SCUXIPSLR_IPC0_3 (SCUX.IPSLR_IPC0_3)
     127#define SCUXOPCIR_OPC0_0 (SCUX.OPCIR_OPC0_0)
     128#define SCUXOPSLR_OPC0_0 (SCUX.OPSLR_OPC0_0)
     129#define SCUXOPCIR_OPC0_1 (SCUX.OPCIR_OPC0_1)
     130#define SCUXOPSLR_OPC0_1 (SCUX.OPSLR_OPC0_1)
     131#define SCUXOPCIR_OPC0_2 (SCUX.OPCIR_OPC0_2)
     132#define SCUXOPSLR_OPC0_2 (SCUX.OPSLR_OPC0_2)
     133#define SCUXOPCIR_OPC0_3 (SCUX.OPCIR_OPC0_3)
     134#define SCUXOPSLR_OPC0_3 (SCUX.OPSLR_OPC0_3)
     135#define SCUXFFDIR_FFD0_0 (SCUX.FFDIR_FFD0_0)
     136#define SCUXFDAIR_FFD0_0 (SCUX.FDAIR_FFD0_0)
     137#define SCUXDRQSR_FFD0_0 (SCUX.DRQSR_FFD0_0)
     138#define SCUXFFDPR_FFD0_0 (SCUX.FFDPR_FFD0_0)
     139#define SCUXFFDBR_FFD0_0 (SCUX.FFDBR_FFD0_0)
     140#define SCUXDEVMR_FFD0_0 (SCUX.DEVMR_FFD0_0)
     141#define SCUXDEVCR_FFD0_0 (SCUX.DEVCR_FFD0_0)
     142#define SCUXFFDIR_FFD0_1 (SCUX.FFDIR_FFD0_1)
     143#define SCUXFDAIR_FFD0_1 (SCUX.FDAIR_FFD0_1)
     144#define SCUXDRQSR_FFD0_1 (SCUX.DRQSR_FFD0_1)
     145#define SCUXFFDPR_FFD0_1 (SCUX.FFDPR_FFD0_1)
     146#define SCUXFFDBR_FFD0_1 (SCUX.FFDBR_FFD0_1)
     147#define SCUXDEVMR_FFD0_1 (SCUX.DEVMR_FFD0_1)
     148#define SCUXDEVCR_FFD0_1 (SCUX.DEVCR_FFD0_1)
     149#define SCUXFFDIR_FFD0_2 (SCUX.FFDIR_FFD0_2)
     150#define SCUXFDAIR_FFD0_2 (SCUX.FDAIR_FFD0_2)
     151#define SCUXDRQSR_FFD0_2 (SCUX.DRQSR_FFD0_2)
     152#define SCUXFFDPR_FFD0_2 (SCUX.FFDPR_FFD0_2)
     153#define SCUXFFDBR_FFD0_2 (SCUX.FFDBR_FFD0_2)
     154#define SCUXDEVMR_FFD0_2 (SCUX.DEVMR_FFD0_2)
     155#define SCUXDEVCR_FFD0_2 (SCUX.DEVCR_FFD0_2)
     156#define SCUXFFDIR_FFD0_3 (SCUX.FFDIR_FFD0_3)
     157#define SCUXFDAIR_FFD0_3 (SCUX.FDAIR_FFD0_3)
     158#define SCUXDRQSR_FFD0_3 (SCUX.DRQSR_FFD0_3)
     159#define SCUXFFDPR_FFD0_3 (SCUX.FFDPR_FFD0_3)
     160#define SCUXFFDBR_FFD0_3 (SCUX.FFDBR_FFD0_3)
     161#define SCUXDEVMR_FFD0_3 (SCUX.DEVMR_FFD0_3)
     162#define SCUXDEVCR_FFD0_3 (SCUX.DEVCR_FFD0_3)
     163#define SCUXFFUIR_FFU0_0 (SCUX.FFUIR_FFU0_0)
     164#define SCUXFUAIR_FFU0_0 (SCUX.FUAIR_FFU0_0)
     165#define SCUXURQSR_FFU0_0 (SCUX.URQSR_FFU0_0)
     166#define SCUXFFUPR_FFU0_0 (SCUX.FFUPR_FFU0_0)
     167#define SCUXUEVMR_FFU0_0 (SCUX.UEVMR_FFU0_0)
     168#define SCUXUEVCR_FFU0_0 (SCUX.UEVCR_FFU0_0)
     169#define SCUXFFUIR_FFU0_1 (SCUX.FFUIR_FFU0_1)
     170#define SCUXFUAIR_FFU0_1 (SCUX.FUAIR_FFU0_1)
     171#define SCUXURQSR_FFU0_1 (SCUX.URQSR_FFU0_1)
     172#define SCUXFFUPR_FFU0_1 (SCUX.FFUPR_FFU0_1)
     173#define SCUXUEVMR_FFU0_1 (SCUX.UEVMR_FFU0_1)
     174#define SCUXUEVCR_FFU0_1 (SCUX.UEVCR_FFU0_1)
     175#define SCUXFFUIR_FFU0_2 (SCUX.FFUIR_FFU0_2)
     176#define SCUXFUAIR_FFU0_2 (SCUX.FUAIR_FFU0_2)
     177#define SCUXURQSR_FFU0_2 (SCUX.URQSR_FFU0_2)
     178#define SCUXFFUPR_FFU0_2 (SCUX.FFUPR_FFU0_2)
     179#define SCUXUEVMR_FFU0_2 (SCUX.UEVMR_FFU0_2)
     180#define SCUXUEVCR_FFU0_2 (SCUX.UEVCR_FFU0_2)
     181#define SCUXFFUIR_FFU0_3 (SCUX.FFUIR_FFU0_3)
     182#define SCUXFUAIR_FFU0_3 (SCUX.FUAIR_FFU0_3)
     183#define SCUXURQSR_FFU0_3 (SCUX.URQSR_FFU0_3)
     184#define SCUXFFUPR_FFU0_3 (SCUX.FFUPR_FFU0_3)
     185#define SCUXUEVMR_FFU0_3 (SCUX.UEVMR_FFU0_3)
     186#define SCUXUEVCR_FFU0_3 (SCUX.UEVCR_FFU0_3)
     187#define SCUXSRCIR0_2SRC0_0 (SCUX.SRCIR0_2SRC0_0)
     188#define SCUXSADIR0_2SRC0_0 (SCUX.SADIR0_2SRC0_0)
     189#define SCUXSRCBR0_2SRC0_0 (SCUX.SRCBR0_2SRC0_0)
     190#define SCUXIFSCR0_2SRC0_0 (SCUX.IFSCR0_2SRC0_0)
     191#define SCUXIFSVR0_2SRC0_0 (SCUX.IFSVR0_2SRC0_0)
     192#define SCUXSRCCR0_2SRC0_0 (SCUX.SRCCR0_2SRC0_0)
     193#define SCUXMNFSR0_2SRC0_0 (SCUX.MNFSR0_2SRC0_0)
     194#define SCUXBFSSR0_2SRC0_0 (SCUX.BFSSR0_2SRC0_0)
     195#define SCUXSC2SR0_2SRC0_0 (SCUX.SC2SR0_2SRC0_0)
     196#define SCUXWATSR0_2SRC0_0 (SCUX.WATSR0_2SRC0_0)
     197#define SCUXSEVMR0_2SRC0_0 (SCUX.SEVMR0_2SRC0_0)
     198#define SCUXSEVCR0_2SRC0_0 (SCUX.SEVCR0_2SRC0_0)
     199#define SCUXSRCIR1_2SRC0_0 (SCUX.SRCIR1_2SRC0_0)
     200#define SCUXSADIR1_2SRC0_0 (SCUX.SADIR1_2SRC0_0)
     201#define SCUXSRCBR1_2SRC0_0 (SCUX.SRCBR1_2SRC0_0)
     202#define SCUXIFSCR1_2SRC0_0 (SCUX.IFSCR1_2SRC0_0)
     203#define SCUXIFSVR1_2SRC0_0 (SCUX.IFSVR1_2SRC0_0)
     204#define SCUXSRCCR1_2SRC0_0 (SCUX.SRCCR1_2SRC0_0)
     205#define SCUXMNFSR1_2SRC0_0 (SCUX.MNFSR1_2SRC0_0)
     206#define SCUXBFSSR1_2SRC0_0 (SCUX.BFSSR1_2SRC0_0)
     207#define SCUXSC2SR1_2SRC0_0 (SCUX.SC2SR1_2SRC0_0)
     208#define SCUXWATSR1_2SRC0_0 (SCUX.WATSR1_2SRC0_0)
     209#define SCUXSEVMR1_2SRC0_0 (SCUX.SEVMR1_2SRC0_0)
     210#define SCUXSEVCR1_2SRC0_0 (SCUX.SEVCR1_2SRC0_0)
     211#define SCUXSRCIRR_2SRC0_0 (SCUX.SRCIRR_2SRC0_0)
     212#define SCUXSRCIR0_2SRC0_1 (SCUX.SRCIR0_2SRC0_1)
     213#define SCUXSADIR0_2SRC0_1 (SCUX.SADIR0_2SRC0_1)
     214#define SCUXSRCBR0_2SRC0_1 (SCUX.SRCBR0_2SRC0_1)
     215#define SCUXIFSCR0_2SRC0_1 (SCUX.IFSCR0_2SRC0_1)
     216#define SCUXIFSVR0_2SRC0_1 (SCUX.IFSVR0_2SRC0_1)
     217#define SCUXSRCCR0_2SRC0_1 (SCUX.SRCCR0_2SRC0_1)
     218#define SCUXMNFSR0_2SRC0_1 (SCUX.MNFSR0_2SRC0_1)
     219#define SCUXBFSSR0_2SRC0_1 (SCUX.BFSSR0_2SRC0_1)
     220#define SCUXSC2SR0_2SRC0_1 (SCUX.SC2SR0_2SRC0_1)
     221#define SCUXWATSR0_2SRC0_1 (SCUX.WATSR0_2SRC0_1)
     222#define SCUXSEVMR0_2SRC0_1 (SCUX.SEVMR0_2SRC0_1)
     223#define SCUXSEVCR0_2SRC0_1 (SCUX.SEVCR0_2SRC0_1)
     224#define SCUXSRCIR1_2SRC0_1 (SCUX.SRCIR1_2SRC0_1)
     225#define SCUXSADIR1_2SRC0_1 (SCUX.SADIR1_2SRC0_1)
     226#define SCUXSRCBR1_2SRC0_1 (SCUX.SRCBR1_2SRC0_1)
     227#define SCUXIFSCR1_2SRC0_1 (SCUX.IFSCR1_2SRC0_1)
     228#define SCUXIFSVR1_2SRC0_1 (SCUX.IFSVR1_2SRC0_1)
     229#define SCUXSRCCR1_2SRC0_1 (SCUX.SRCCR1_2SRC0_1)
     230#define SCUXMNFSR1_2SRC0_1 (SCUX.MNFSR1_2SRC0_1)
     231#define SCUXBFSSR1_2SRC0_1 (SCUX.BFSSR1_2SRC0_1)
     232#define SCUXSC2SR1_2SRC0_1 (SCUX.SC2SR1_2SRC0_1)
     233#define SCUXWATSR1_2SRC0_1 (SCUX.WATSR1_2SRC0_1)
     234#define SCUXSEVMR1_2SRC0_1 (SCUX.SEVMR1_2SRC0_1)
     235#define SCUXSEVCR1_2SRC0_1 (SCUX.SEVCR1_2SRC0_1)
     236#define SCUXSRCIRR_2SRC0_1 (SCUX.SRCIRR_2SRC0_1)
     237#define SCUXDVUIR_DVU0_0 (SCUX.DVUIR_DVU0_0)
     238#define SCUXVADIR_DVU0_0 (SCUX.VADIR_DVU0_0)
     239#define SCUXDVUBR_DVU0_0 (SCUX.DVUBR_DVU0_0)
     240#define SCUXDVUCR_DVU0_0 (SCUX.DVUCR_DVU0_0)
     241#define SCUXZCMCR_DVU0_0 (SCUX.ZCMCR_DVU0_0)
     242#define SCUXVRCTR_DVU0_0 (SCUX.VRCTR_DVU0_0)
     243#define SCUXVRPDR_DVU0_0 (SCUX.VRPDR_DVU0_0)
     244#define SCUXVRDBR_DVU0_0 (SCUX.VRDBR_DVU0_0)
     245#define SCUXVRWTR_DVU0_0 (SCUX.VRWTR_DVU0_0)
     246#define SCUXVOL0R_DVU0_0 (SCUX.VOL0R_DVU0_0)
     247#define SCUXVOL1R_DVU0_0 (SCUX.VOL1R_DVU0_0)
     248#define SCUXVOL2R_DVU0_0 (SCUX.VOL2R_DVU0_0)
     249#define SCUXVOL3R_DVU0_0 (SCUX.VOL3R_DVU0_0)
     250#define SCUXVOL4R_DVU0_0 (SCUX.VOL4R_DVU0_0)
     251#define SCUXVOL5R_DVU0_0 (SCUX.VOL5R_DVU0_0)
     252#define SCUXVOL6R_DVU0_0 (SCUX.VOL6R_DVU0_0)
     253#define SCUXVOL7R_DVU0_0 (SCUX.VOL7R_DVU0_0)
     254#define SCUXDVUER_DVU0_0 (SCUX.DVUER_DVU0_0)
     255#define SCUXDVUSR_DVU0_0 (SCUX.DVUSR_DVU0_0)
     256#define SCUXVEVMR_DVU0_0 (SCUX.VEVMR_DVU0_0)
     257#define SCUXVEVCR_DVU0_0 (SCUX.VEVCR_DVU0_0)
     258#define SCUXDVUIR_DVU0_1 (SCUX.DVUIR_DVU0_1)
     259#define SCUXVADIR_DVU0_1 (SCUX.VADIR_DVU0_1)
     260#define SCUXDVUBR_DVU0_1 (SCUX.DVUBR_DVU0_1)
     261#define SCUXDVUCR_DVU0_1 (SCUX.DVUCR_DVU0_1)
     262#define SCUXZCMCR_DVU0_1 (SCUX.ZCMCR_DVU0_1)
     263#define SCUXVRCTR_DVU0_1 (SCUX.VRCTR_DVU0_1)
     264#define SCUXVRPDR_DVU0_1 (SCUX.VRPDR_DVU0_1)
     265#define SCUXVRDBR_DVU0_1 (SCUX.VRDBR_DVU0_1)
     266#define SCUXVRWTR_DVU0_1 (SCUX.VRWTR_DVU0_1)
     267#define SCUXVOL0R_DVU0_1 (SCUX.VOL0R_DVU0_1)
     268#define SCUXVOL1R_DVU0_1 (SCUX.VOL1R_DVU0_1)
     269#define SCUXVOL2R_DVU0_1 (SCUX.VOL2R_DVU0_1)
     270#define SCUXVOL3R_DVU0_1 (SCUX.VOL3R_DVU0_1)
     271#define SCUXVOL4R_DVU0_1 (SCUX.VOL4R_DVU0_1)
     272#define SCUXVOL5R_DVU0_1 (SCUX.VOL5R_DVU0_1)
     273#define SCUXVOL6R_DVU0_1 (SCUX.VOL6R_DVU0_1)
     274#define SCUXVOL7R_DVU0_1 (SCUX.VOL7R_DVU0_1)
     275#define SCUXDVUER_DVU0_1 (SCUX.DVUER_DVU0_1)
     276#define SCUXDVUSR_DVU0_1 (SCUX.DVUSR_DVU0_1)
     277#define SCUXVEVMR_DVU0_1 (SCUX.VEVMR_DVU0_1)
     278#define SCUXVEVCR_DVU0_1 (SCUX.VEVCR_DVU0_1)
     279#define SCUXDVUIR_DVU0_2 (SCUX.DVUIR_DVU0_2)
     280#define SCUXVADIR_DVU0_2 (SCUX.VADIR_DVU0_2)
     281#define SCUXDVUBR_DVU0_2 (SCUX.DVUBR_DVU0_2)
     282#define SCUXDVUCR_DVU0_2 (SCUX.DVUCR_DVU0_2)
     283#define SCUXZCMCR_DVU0_2 (SCUX.ZCMCR_DVU0_2)
     284#define SCUXVRCTR_DVU0_2 (SCUX.VRCTR_DVU0_2)
     285#define SCUXVRPDR_DVU0_2 (SCUX.VRPDR_DVU0_2)
     286#define SCUXVRDBR_DVU0_2 (SCUX.VRDBR_DVU0_2)
     287#define SCUXVRWTR_DVU0_2 (SCUX.VRWTR_DVU0_2)
     288#define SCUXVOL0R_DVU0_2 (SCUX.VOL0R_DVU0_2)
     289#define SCUXVOL1R_DVU0_2 (SCUX.VOL1R_DVU0_2)
     290#define SCUXVOL2R_DVU0_2 (SCUX.VOL2R_DVU0_2)
     291#define SCUXVOL3R_DVU0_2 (SCUX.VOL3R_DVU0_2)
     292#define SCUXVOL4R_DVU0_2 (SCUX.VOL4R_DVU0_2)
     293#define SCUXVOL5R_DVU0_2 (SCUX.VOL5R_DVU0_2)
     294#define SCUXVOL6R_DVU0_2 (SCUX.VOL6R_DVU0_2)
     295#define SCUXVOL7R_DVU0_2 (SCUX.VOL7R_DVU0_2)
     296#define SCUXDVUER_DVU0_2 (SCUX.DVUER_DVU0_2)
     297#define SCUXDVUSR_DVU0_2 (SCUX.DVUSR_DVU0_2)
     298#define SCUXVEVMR_DVU0_2 (SCUX.VEVMR_DVU0_2)
     299#define SCUXVEVCR_DVU0_2 (SCUX.VEVCR_DVU0_2)
     300#define SCUXDVUIR_DVU0_3 (SCUX.DVUIR_DVU0_3)
     301#define SCUXVADIR_DVU0_3 (SCUX.VADIR_DVU0_3)
     302#define SCUXDVUBR_DVU0_3 (SCUX.DVUBR_DVU0_3)
     303#define SCUXDVUCR_DVU0_3 (SCUX.DVUCR_DVU0_3)
     304#define SCUXZCMCR_DVU0_3 (SCUX.ZCMCR_DVU0_3)
     305#define SCUXVRCTR_DVU0_3 (SCUX.VRCTR_DVU0_3)
     306#define SCUXVRPDR_DVU0_3 (SCUX.VRPDR_DVU0_3)
     307#define SCUXVRDBR_DVU0_3 (SCUX.VRDBR_DVU0_3)
     308#define SCUXVRWTR_DVU0_3 (SCUX.VRWTR_DVU0_3)
     309#define SCUXVOL0R_DVU0_3 (SCUX.VOL0R_DVU0_3)
     310#define SCUXVOL1R_DVU0_3 (SCUX.VOL1R_DVU0_3)
     311#define SCUXVOL2R_DVU0_3 (SCUX.VOL2R_DVU0_3)
     312#define SCUXVOL3R_DVU0_3 (SCUX.VOL3R_DVU0_3)
     313#define SCUXVOL4R_DVU0_3 (SCUX.VOL4R_DVU0_3)
     314#define SCUXVOL5R_DVU0_3 (SCUX.VOL5R_DVU0_3)
     315#define SCUXVOL6R_DVU0_3 (SCUX.VOL6R_DVU0_3)
     316#define SCUXVOL7R_DVU0_3 (SCUX.VOL7R_DVU0_3)
     317#define SCUXDVUER_DVU0_3 (SCUX.DVUER_DVU0_3)
     318#define SCUXDVUSR_DVU0_3 (SCUX.DVUSR_DVU0_3)
     319#define SCUXVEVMR_DVU0_3 (SCUX.VEVMR_DVU0_3)
     320#define SCUXVEVCR_DVU0_3 (SCUX.VEVCR_DVU0_3)
     321#define SCUXMIXIR_MIX0_0 (SCUX.MIXIR_MIX0_0)
     322#define SCUXMADIR_MIX0_0 (SCUX.MADIR_MIX0_0)
     323#define SCUXMIXBR_MIX0_0 (SCUX.MIXBR_MIX0_0)
     324#define SCUXMIXMR_MIX0_0 (SCUX.MIXMR_MIX0_0)
     325#define SCUXMVPDR_MIX0_0 (SCUX.MVPDR_MIX0_0)
     326#define SCUXMDBAR_MIX0_0 (SCUX.MDBAR_MIX0_0)
     327#define SCUXMDBBR_MIX0_0 (SCUX.MDBBR_MIX0_0)
     328#define SCUXMDBCR_MIX0_0 (SCUX.MDBCR_MIX0_0)
     329#define SCUXMDBDR_MIX0_0 (SCUX.MDBDR_MIX0_0)
     330#define SCUXMDBER_MIX0_0 (SCUX.MDBER_MIX0_0)
     331#define SCUXMIXSR_MIX0_0 (SCUX.MIXSR_MIX0_0)
     332#define SCUXSWRSR_CIM (SCUX.SWRSR_CIM)
     333#define SCUXDMACR_CIM (SCUX.DMACR_CIM)
     334#define SCUXDMATD0_CIM (SCUX.DMATD0_CIM.UINT32)
     335#define SCUXDMATD0_CIML (SCUX.DMATD0_CIM.UINT16[R_IO_L])
     336#define SCUXDMATD0_CIMH (SCUX.DMATD0_CIM.UINT16[R_IO_H])
     337#define SCUXDMATD1_CIM (SCUX.DMATD1_CIM.UINT32)
     338#define SCUXDMATD1_CIML (SCUX.DMATD1_CIM.UINT16[R_IO_L])
     339#define SCUXDMATD1_CIMH (SCUX.DMATD1_CIM.UINT16[R_IO_H])
     340#define SCUXDMATD2_CIM (SCUX.DMATD2_CIM.UINT32)
     341#define SCUXDMATD2_CIML (SCUX.DMATD2_CIM.UINT16[R_IO_L])
     342#define SCUXDMATD2_CIMH (SCUX.DMATD2_CIM.UINT16[R_IO_H])
     343#define SCUXDMATD3_CIM (SCUX.DMATD3_CIM.UINT32)
     344#define SCUXDMATD3_CIML (SCUX.DMATD3_CIM.UINT16[R_IO_L])
     345#define SCUXDMATD3_CIMH (SCUX.DMATD3_CIM.UINT16[R_IO_H])
     346#define SCUXDMATU0_CIM (SCUX.DMATU0_CIM.UINT32)
     347#define SCUXDMATU0_CIML (SCUX.DMATU0_CIM.UINT16[R_IO_L])
     348#define SCUXDMATU0_CIMH (SCUX.DMATU0_CIM.UINT16[R_IO_H])
     349#define SCUXDMATU1_CIM (SCUX.DMATU1_CIM.UINT32)
     350#define SCUXDMATU1_CIML (SCUX.DMATU1_CIM.UINT16[R_IO_L])
     351#define SCUXDMATU1_CIMH (SCUX.DMATU1_CIM.UINT16[R_IO_H])
     352#define SCUXDMATU2_CIM (SCUX.DMATU2_CIM.UINT32)
     353#define SCUXDMATU2_CIML (SCUX.DMATU2_CIM.UINT16[R_IO_L])
     354#define SCUXDMATU2_CIMH (SCUX.DMATU2_CIM.UINT16[R_IO_H])
     355#define SCUXDMATU3_CIM (SCUX.DMATU3_CIM.UINT32)
     356#define SCUXDMATU3_CIML (SCUX.DMATU3_CIM.UINT16[R_IO_L])
     357#define SCUXDMATU3_CIMH (SCUX.DMATU3_CIM.UINT16[R_IO_H])
     358#define SCUXSSIRSEL_CIM (SCUX.SSIRSEL_CIM)
     359#define SCUXFDTSEL0_CIM (SCUX.FDTSEL0_CIM)
     360#define SCUXFDTSEL1_CIM (SCUX.FDTSEL1_CIM)
     361#define SCUXFDTSEL2_CIM (SCUX.FDTSEL2_CIM)
     362#define SCUXFDTSEL3_CIM (SCUX.FDTSEL3_CIM)
     363#define SCUXFUTSEL0_CIM (SCUX.FUTSEL0_CIM)
     364#define SCUXFUTSEL1_CIM (SCUX.FUTSEL1_CIM)
     365#define SCUXFUTSEL2_CIM (SCUX.FUTSEL2_CIM)
     366#define SCUXFUTSEL3_CIM (SCUX.FUTSEL3_CIM)
     367#define SCUXSSIPMD_CIM (SCUX.SSIPMD_CIM)
     368#define SCUXSSICTRL_CIM (SCUX.SSICTRL_CIM)
     369#define SCUXSRCRSEL0_CIM (SCUX.SRCRSEL0_CIM)
     370#define SCUXSRCRSEL1_CIM (SCUX.SRCRSEL1_CIM)
     371#define SCUXSRCRSEL2_CIM (SCUX.SRCRSEL2_CIM)
     372#define SCUXSRCRSEL3_CIM (SCUX.SRCRSEL3_CIM)
     373#define SCUXMIXRSEL_CIM (SCUX.MIXRSEL_CIM)
     374
     375#define SCUX_DMATDnCIM_COUNT (4)
     376#define SCUX_DMATUnCIM_COUNT (4)
     377#define SCUX_FDTSELnCIM_COUNT (4)
     378#define SCUX_FUTSELnCIM_COUNT (4)
     379#define SCUX_SRCRSELnCIM_COUNT (4)
     380
     381
     382typedef struct st_scux
     383{
     384                                                           /* SCUX             */
     385
    36386/* start of struct st_scux_from_ipcir_ipc0_n */
    37387    volatile uint32_t  IPCIR_IPC0_0;                           /*  IPCIR_IPC0_0    */
    38388    volatile uint32_t  IPSLR_IPC0_0;                           /*  IPSLR_IPC0_0    */
    39389    volatile uint8_t   dummy259[248];                          /*                  */
     390
    40391/* end of struct st_scux_from_ipcir_ipc0_n */
     392
    41393/* start of struct st_scux_from_ipcir_ipc0_n */
    42394    volatile uint32_t  IPCIR_IPC0_1;                           /*  IPCIR_IPC0_1    */
    43395    volatile uint32_t  IPSLR_IPC0_1;                           /*  IPSLR_IPC0_1    */
    44396    volatile uint8_t   dummy260[248];                          /*                  */
     397
    45398/* end of struct st_scux_from_ipcir_ipc0_n */
     399
    46400/* start of struct st_scux_from_ipcir_ipc0_n */
    47401    volatile uint32_t  IPCIR_IPC0_2;                           /*  IPCIR_IPC0_2    */
    48402    volatile uint32_t  IPSLR_IPC0_2;                           /*  IPSLR_IPC0_2    */
    49403    volatile uint8_t   dummy261[248];                          /*                  */
     404
    50405/* end of struct st_scux_from_ipcir_ipc0_n */
     406
    51407/* start of struct st_scux_from_ipcir_ipc0_n */
    52408    volatile uint32_t  IPCIR_IPC0_3;                           /*  IPCIR_IPC0_3    */
    53409    volatile uint32_t  IPSLR_IPC0_3;                           /*  IPSLR_IPC0_3    */
    54410    volatile uint8_t   dummy262[248];                          /*                  */
     411
    55412/* end of struct st_scux_from_ipcir_ipc0_n */
     413
    56414/* start of struct st_scux_from_opcir_opc0_n */
    57415    volatile uint32_t  OPCIR_OPC0_0;                           /*  OPCIR_OPC0_0    */
    58416    volatile uint32_t  OPSLR_OPC0_0;                           /*  OPSLR_OPC0_0    */
    59417    volatile uint8_t   dummy263[248];                          /*                  */
     418
    60419/* end of struct st_scux_from_opcir_opc0_n */
     420
    61421/* start of struct st_scux_from_opcir_opc0_n */
    62422    volatile uint32_t  OPCIR_OPC0_1;                           /*  OPCIR_OPC0_1    */
    63423    volatile uint32_t  OPSLR_OPC0_1;                           /*  OPSLR_OPC0_1    */
    64424    volatile uint8_t   dummy264[248];                          /*                  */
     425
    65426/* end of struct st_scux_from_opcir_opc0_n */
     427
    66428/* start of struct st_scux_from_opcir_opc0_n */
    67429    volatile uint32_t  OPCIR_OPC0_2;                           /*  OPCIR_OPC0_2    */
    68430    volatile uint32_t  OPSLR_OPC0_2;                           /*  OPSLR_OPC0_2    */
    69431    volatile uint8_t   dummy265[248];                          /*                  */
     432
    70433/* end of struct st_scux_from_opcir_opc0_n */
     434
    71435/* start of struct st_scux_from_opcir_opc0_n */
    72436    volatile uint32_t  OPCIR_OPC0_3;                           /*  OPCIR_OPC0_3    */
    73437    volatile uint32_t  OPSLR_OPC0_3;                           /*  OPSLR_OPC0_3    */
    74438    volatile uint8_t   dummy266[248];                          /*                  */
     439
    75440/* end of struct st_scux_from_opcir_opc0_n */
     441
    76442/* start of struct st_scux_from_ffdir_ffd0_n */
    77443    volatile uint32_t  FFDIR_FFD0_0;                           /*  FFDIR_FFD0_0    */
    … …  
    83449    volatile uint8_t   dummy267[4];                            /*                  */
    84450    volatile uint32_t  DEVCR_FFD0_0;                           /*  DEVCR_FFD0_0    */
     451
    85452/* end of struct st_scux_from_ffdir_ffd0_n */
    86453    volatile uint8_t   dummy268[224];                          /*                  */
     454
    87455/* start of struct st_scux_from_ffdir_ffd0_n */
    88456    volatile uint32_t  FFDIR_FFD0_1;                           /*  FFDIR_FFD0_1    */
    … …  
    94462    volatile uint8_t   dummy269[4];                            /*                  */
    95463    volatile uint32_t  DEVCR_FFD0_1;                           /*  DEVCR_FFD0_1    */
     464
    96465/* end of struct st_scux_from_ffdir_ffd0_n */
    97466    volatile uint8_t   dummy270[224];                          /*                  */
     467
    98468/* start of struct st_scux_from_ffdir_ffd0_n */
    99469    volatile uint32_t  FFDIR_FFD0_2;                           /*  FFDIR_FFD0_2    */
    … …  
    105475    volatile uint8_t   dummy271[4];                            /*                  */
    106476    volatile uint32_t  DEVCR_FFD0_2;                           /*  DEVCR_FFD0_2    */
     477
    107478/* end of struct st_scux_from_ffdir_ffd0_n */
    108479    volatile uint8_t   dummy272[224];                          /*                  */
     480
    109481/* start of struct st_scux_from_ffdir_ffd0_n */
    110482    volatile uint32_t  FFDIR_FFD0_3;                           /*  FFDIR_FFD0_3    */
    … …  
    116488    volatile uint8_t   dummy273[4];                            /*                  */
    117489    volatile uint32_t  DEVCR_FFD0_3;                           /*  DEVCR_FFD0_3    */
     490
    118491/* end of struct st_scux_from_ffdir_ffd0_n */
    119492    volatile uint8_t   dummy274[224];                          /*                  */
     493
    120494/* start of struct st_scux_from_ffuir_ffu0_n */
    121495    volatile uint32_t  FFUIR_FFU0_0;                           /*  FFUIR_FFU0_0    */
    … …  
    126500    volatile uint8_t   dummy275[4];                            /*                  */
    127501    volatile uint32_t  UEVCR_FFU0_0;                           /*  UEVCR_FFU0_0    */
     502
    128503/* end of struct st_scux_from_ffuir_ffu0_n */
    129504    volatile uint8_t   dummy276[228];                          /*                  */
     505
    130506/* start of struct st_scux_from_ffuir_ffu0_n */
    131507    volatile uint32_t  FFUIR_FFU0_1;                           /*  FFUIR_FFU0_1    */
    … …  
    136512    volatile uint8_t   dummy277[4];                            /*                  */
    137513    volatile uint32_t  UEVCR_FFU0_1;                           /*  UEVCR_FFU0_1    */
     514
    138515/* end of struct st_scux_from_ffuir_ffu0_n */
    139516    volatile uint8_t   dummy278[228];                          /*                  */
     517
    140518/* start of struct st_scux_from_ffuir_ffu0_n */
    141519    volatile uint32_t  FFUIR_FFU0_2;                           /*  FFUIR_FFU0_2    */
    … …  
    146524    volatile uint8_t   dummy279[4];                            /*                  */
    147525    volatile uint32_t  UEVCR_FFU0_2;                           /*  UEVCR_FFU0_2    */
     526
    148527/* end of struct st_scux_from_ffuir_ffu0_n */
    149528    volatile uint8_t   dummy280[228];                          /*                  */
     529
    150530/* start of struct st_scux_from_ffuir_ffu0_n */
    151531    volatile uint32_t  FFUIR_FFU0_3;                           /*  FFUIR_FFU0_3    */
    … …  
    156536    volatile uint8_t   dummy281[4];                            /*                  */
    157537    volatile uint32_t  UEVCR_FFU0_3;                           /*  UEVCR_FFU0_3    */
     538
    158539/* end of struct st_scux_from_ffuir_ffu0_n */
    159540    volatile uint8_t   dummy282[228];                          /*                  */
     541
    160542/* start of struct st_scux_from_srcir0_2src0_n */
    161543    volatile uint32_t  SRCIR0_2SRC0_0;                         /*  SRCIR0_2SRC0_0  */
    … …  
    186568    volatile uint32_t  SEVCR1_2SRC0_0;                         /*  SEVCR1_2SRC0_0  */
    187569    volatile uint32_t  SRCIRR_2SRC0_0;                         /*  SRCIRR_2SRC0_0  */
     570
    188571/* end of struct st_scux_from_srcir0_2src0_n */
    189572    volatile uint8_t   dummy285[148];                          /*                  */
     573
    190574/* start of struct st_scux_from_srcir0_2src0_n */
    191575    volatile uint32_t  SRCIR0_2SRC0_1;                         /*  SRCIR0_2SRC0_1  */
    … …  
    216600    volatile uint32_t  SEVCR1_2SRC0_1;                         /*  SEVCR1_2SRC0_1  */
    217601    volatile uint32_t  SRCIRR_2SRC0_1;                         /*  SRCIRR_2SRC0_1  */
     602
    218603/* end of struct st_scux_from_srcir0_2src0_n */
    219604    volatile uint8_t   dummy288[148];                          /*                  */
     605
    220606/* start of struct st_scux_from_dvuir_dvu0_n */
    221607    volatile uint32_t  DVUIR_DVU0_0;                           /*  DVUIR_DVU0_0    */
    … …  
    241627    volatile uint8_t   dummy289[4];                            /*                  */
    242628    volatile uint32_t  VEVCR_DVU0_0;                           /*  VEVCR_DVU0_0    */
     629
    243630/* end of struct st_scux_from_dvuir_dvu0_n */
    244631    volatile uint8_t   dummy290[168];                          /*                  */
     632
    245633/* start of struct st_scux_from_dvuir_dvu0_n */
    246634    volatile uint32_t  DVUIR_DVU0_1;                           /*  DVUIR_DVU0_1    */
    … …  
    266654    volatile uint8_t   dummy291[4];                            /*                  */
    267655    volatile uint32_t  VEVCR_DVU0_1;                           /*  VEVCR_DVU0_1    */
     656
    268657/* end of struct st_scux_from_dvuir_dvu0_n */
    269658    volatile uint8_t   dummy292[168];                          /*                  */
     659
    270660/* start of struct st_scux_from_dvuir_dvu0_n */
    271661    volatile uint32_t  DVUIR_DVU0_2;                           /*  DVUIR_DVU0_2    */
    … …  
    291681    volatile uint8_t   dummy293[4];                            /*                  */
    292682    volatile uint32_t  VEVCR_DVU0_2;                           /*  VEVCR_DVU0_2    */
     683
    293684/* end of struct st_scux_from_dvuir_dvu0_n */
    294685    volatile uint8_t   dummy294[168];                          /*                  */
     686
    295687/* start of struct st_scux_from_dvuir_dvu0_n */
    296688    volatile uint32_t  DVUIR_DVU0_3;                           /*  DVUIR_DVU0_3    */
    … …  
    316708    volatile uint8_t   dummy295[4];                            /*                  */
    317709    volatile uint32_t  VEVCR_DVU0_3;                           /*  VEVCR_DVU0_3    */
     710
    318711/* end of struct st_scux_from_dvuir_dvu0_n */
    319712    volatile uint8_t   dummy296[168];                          /*                  */
    … …  
    332725    volatile uint32_t  SWRSR_CIM;                              /*  SWRSR_CIM       */
    333726    volatile uint32_t  DMACR_CIM;                              /*  DMACR_CIM       */
    334 #define SCUX_DMATDn_CIM_COUNT 4
     727
     728/* #define SCUX_DMATDnCIM_COUNT (4) */
    335729    union iodefine_reg32_16_t  DMATD0_CIM;                 /*  DMATD0_CIM      */
    336730    union iodefine_reg32_16_t  DMATD1_CIM;                 /*  DMATD1_CIM      */
    337731    union iodefine_reg32_16_t  DMATD2_CIM;                 /*  DMATD2_CIM      */
    338732    union iodefine_reg32_16_t  DMATD3_CIM;                 /*  DMATD3_CIM      */
    339 #define SCUX_DMATUn_CIM_COUNT 4
     733
     734/* #define SCUX_DMATUnCIM_COUNT (4) */
    340735    union iodefine_reg32_16_t  DMATU0_CIM;                 /*  DMATU0_CIM      */
    341736    union iodefine_reg32_16_t  DMATU1_CIM;                 /*  DMATU1_CIM      */
    … …  
    345740    volatile uint8_t   dummy298[16];                           /*                  */
    346741    volatile uint32_t  SSIRSEL_CIM;                            /*  SSIRSEL_CIM     */
    347 #define SCUX_FDTSELn_CIM_COUNT 4
     742
     743/* #define SCUX_FDTSELnCIM_COUNT (4) */
    348744    volatile uint32_t  FDTSEL0_CIM;                            /*  FDTSEL0_CIM     */
    349745    volatile uint32_t  FDTSEL1_CIM;                            /*  FDTSEL1_CIM     */
    350746    volatile uint32_t  FDTSEL2_CIM;                            /*  FDTSEL2_CIM     */
    351747    volatile uint32_t  FDTSEL3_CIM;                            /*  FDTSEL3_CIM     */
    352 #define SCUX_FUTSELn_CIM_COUNT 4
     748
     749/* #define SCUX_FUTSELnCIM_COUNT (4) */
    353750    volatile uint32_t  FUTSEL0_CIM;                            /*  FUTSEL0_CIM     */
    354751    volatile uint32_t  FUTSEL1_CIM;                            /*  FUTSEL1_CIM     */
    … …  
    357754    volatile uint32_t  SSIPMD_CIM;                             /*  SSIPMD_CIM      */
    358755    volatile uint32_t  SSICTRL_CIM;                            /*  SSICTRL_CIM     */
    359 #define SCUX_SRCRSELn_CIM_COUNT 4
     756
     757/* #define SCUX_SRCRSELnCIM_COUNT (4) */
    360758    volatile uint32_t  SRCRSEL0_CIM;                           /*  SRCRSEL0_CIM    */
    361759    volatile uint32_t  SRCRSEL1_CIM;                           /*  SRCRSEL1_CIM    */
    … …  
    363761    volatile uint32_t  SRCRSEL3_CIM;                           /*  SRCRSEL3_CIM    */
    364762    volatile uint32_t  MIXRSEL_CIM;                            /*  MIXRSEL_CIM     */
    365 };
    366 
    367 
    368 struct st_scux_from_ipcir_ipc0_n
     763} r_io_scux_t;
     764
     765
     766typedef struct st_scux_from_ipcir_ipc0_n
    369767{
     768 
    370769    volatile uint32_t  IPCIR_IPC0_0;                           /*  IPCIR_IPC0_0    */
    371770    volatile uint32_t  IPSLR_IPC0_0;                           /*  IPSLR_IPC0_0    */
    372771    volatile uint8_t   dummy1[248];                            /*                  */
    373 };
    374 
    375 
    376 struct st_scux_from_opcir_opc0_n
     772} r_io_scux_from_ipcir_ipc0_n_t;
     773
     774
     775typedef struct st_scux_from_opcir_opc0_n
    377776{
     777 
    378778    volatile uint32_t  OPCIR_OPC0_0;                           /*  OPCIR_OPC0_0    */
    379779    volatile uint32_t  OPSLR_OPC0_0;                           /*  OPSLR_OPC0_0    */
    380780    volatile uint8_t   dummy1[248];                            /*                  */
    381 };
    382 
    383 
    384 struct st_scux_from_ffdir_ffd0_n
     781} r_io_scux_from_opcir_opc0_n_t;
     782
     783
     784typedef struct st_scux_from_ffdir_ffd0_n
    385785{
     786 
    386787    volatile uint32_t  FFDIR_FFD0_0;                           /*  FFDIR_FFD0_0    */
    387788    volatile uint32_t  FDAIR_FFD0_0;                           /*  FDAIR_FFD0_0    */
    … …  
    392793    volatile uint8_t   dummy1[4];                              /*                  */
    393794    volatile uint32_t  DEVCR_FFD0_0;                           /*  DEVCR_FFD0_0    */
    394 };
    395 
    396 
    397 struct st_scux_from_ffuir_ffu0_n
     795} r_io_scux_from_ffdir_ffd0_n_t;
     796
     797
     798typedef struct st_scux_from_ffuir_ffu0_n
    398799{
     800 
    399801    volatile uint32_t  FFUIR_FFU0_0;                           /*  FFUIR_FFU0_0    */
    400802    volatile uint32_t  FUAIR_FFU0_0;                           /*  FUAIR_FFU0_0    */
    … …  
    404806    volatile uint8_t   dummy1[4];                              /*                  */
    405807    volatile uint32_t  UEVCR_FFU0_0;                           /*  UEVCR_FFU0_0    */
    406 };
    407 
    408 
    409 struct st_scux_from_srcir0_2src0_n
     808} r_io_scux_from_ffuir_ffu0_n_t;
     809
     810
     811typedef struct st_scux_from_srcir0_2src0_n
    410812{
     813 
    411814    volatile uint32_t  SRCIR0_2SRC0_0;                         /*  SRCIR0_2SRC0_0  */
    412815    volatile uint32_t  SADIR0_2SRC0_0;                         /*  SADIR0_2SRC0_0  */
    … …  
    436839    volatile uint32_t  SEVCR1_2SRC0_0;                         /*  SEVCR1_2SRC0_0  */
    437840    volatile uint32_t  SRCIRR_2SRC0_0;                         /*  SRCIRR_2SRC0_0  */
    438 };
    439 
    440 
    441 struct st_scux_from_dvuir_dvu0_n
     841} r_io_scux_from_srcir0_2src0_n_t;
     842
     843
     844typedef struct st_scux_from_dvuir_dvu0_n
    442845{
     846 
    443847    volatile uint32_t  DVUIR_DVU0_0;                           /*  DVUIR_DVU0_0    */
    444848    volatile uint32_t  VADIR_DVU0_0;                           /*  VADIR_DVU0_0    */
    … …  
    463867    volatile uint8_t   dummy1[4];                              /*                  */
    464868    volatile uint32_t  VEVCR_DVU0_0;                           /*  VEVCR_DVU0_0    */
    465 };
    466 
    467 
    468 #define SCUX    (*(struct st_scux    *)0xE8208000uL) /* SCUX */
    469 
    470 
    471 /* Start of channnel array defines of SCUX */
    472 
    473 /* Channnel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */
    474 /*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */
    475 #define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT  4
    476 #define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \
    477 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    478     &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \
    479 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    480 #define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */
    481 #define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */
    482 #define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */
    483 #define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */
    484 
    485 
    486 /* Channnel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */
    487 /*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */
    488 #define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT  2
    489 #define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \
    490 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    491     &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \
    492 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    493 #define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */
    494 #define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */
    495 
    496 
    497 /* Channnel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */
    498 /*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */
    499 #define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT  4
    500 #define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \
    501 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    502     &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \
    503 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    504 #define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */
    505 #define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */
    506 #define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */
    507 #define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */
    508 
    509 
    510 /* Channnel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */
    511 /*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */
    512 #define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT  4
    513 #define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \
    514 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    515     &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \
    516 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    517 #define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */
    518 #define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */
    519 #define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */
    520 #define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */
    521 
    522 
    523 /* Channnel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */
    524 /*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */
    525 #define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT  4
    526 #define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \
    527 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    528     &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \
    529 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    530 #define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */
    531 #define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */
    532 #define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */
    533 #define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */
    534 
    535 
    536 /* Channnel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */
    537 /*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */
    538 #define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT  4
    539 #define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \
    540 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    541     &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \
    542 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    543 #define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */
    544 #define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */
    545 #define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */
    546 #define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */
    547 
    548 /* End of channnel array defines of SCUX */
    549 
    550 
    551 #define SCUXIPCIR_IPC0_0 SCUX.IPCIR_IPC0_0
    552 #define SCUXIPSLR_IPC0_0 SCUX.IPSLR_IPC0_0
    553 #define SCUXIPCIR_IPC0_1 SCUX.IPCIR_IPC0_1
    554 #define SCUXIPSLR_IPC0_1 SCUX.IPSLR_IPC0_1
    555 #define SCUXIPCIR_IPC0_2 SCUX.IPCIR_IPC0_2
    556 #define SCUXIPSLR_IPC0_2 SCUX.IPSLR_IPC0_2
    557 #define SCUXIPCIR_IPC0_3 SCUX.IPCIR_IPC0_3
    558 #define SCUXIPSLR_IPC0_3 SCUX.IPSLR_IPC0_3
    559 #define SCUXOPCIR_OPC0_0 SCUX.OPCIR_OPC0_0
    560 #define SCUXOPSLR_OPC0_0 SCUX.OPSLR_OPC0_0
    561 #define SCUXOPCIR_OPC0_1 SCUX.OPCIR_OPC0_1
    562 #define SCUXOPSLR_OPC0_1 SCUX.OPSLR_OPC0_1
    563 #define SCUXOPCIR_OPC0_2 SCUX.OPCIR_OPC0_2
    564 #define SCUXOPSLR_OPC0_2 SCUX.OPSLR_OPC0_2
    565 #define SCUXOPCIR_OPC0_3 SCUX.OPCIR_OPC0_3
    566 #define SCUXOPSLR_OPC0_3 SCUX.OPSLR_OPC0_3
    567 #define SCUXFFDIR_FFD0_0 SCUX.FFDIR_FFD0_0
    568 #define SCUXFDAIR_FFD0_0 SCUX.FDAIR_FFD0_0
    569 #define SCUXDRQSR_FFD0_0 SCUX.DRQSR_FFD0_0
    570 #define SCUXFFDPR_FFD0_0 SCUX.FFDPR_FFD0_0
    571 #define SCUXFFDBR_FFD0_0 SCUX.FFDBR_FFD0_0
    572 #define SCUXDEVMR_FFD0_0 SCUX.DEVMR_FFD0_0
    573 #define SCUXDEVCR_FFD0_0 SCUX.DEVCR_FFD0_0
    574 #define SCUXFFDIR_FFD0_1 SCUX.FFDIR_FFD0_1
    575 #define SCUXFDAIR_FFD0_1 SCUX.FDAIR_FFD0_1
    576 #define SCUXDRQSR_FFD0_1 SCUX.DRQSR_FFD0_1
    577 #define SCUXFFDPR_FFD0_1 SCUX.FFDPR_FFD0_1
    578 #define SCUXFFDBR_FFD0_1 SCUX.FFDBR_FFD0_1
    579 #define SCUXDEVMR_FFD0_1 SCUX.DEVMR_FFD0_1
    580 #define SCUXDEVCR_FFD0_1 SCUX.DEVCR_FFD0_1
    581 #define SCUXFFDIR_FFD0_2 SCUX.FFDIR_FFD0_2
    582 #define SCUXFDAIR_FFD0_2 SCUX.FDAIR_FFD0_2
    583 #define SCUXDRQSR_FFD0_2 SCUX.DRQSR_FFD0_2
    584 #define SCUXFFDPR_FFD0_2 SCUX.FFDPR_FFD0_2
    585 #define SCUXFFDBR_FFD0_2 SCUX.FFDBR_FFD0_2
    586 #define SCUXDEVMR_FFD0_2 SCUX.DEVMR_FFD0_2
    587 #define SCUXDEVCR_FFD0_2 SCUX.DEVCR_FFD0_2
    588 #define SCUXFFDIR_FFD0_3 SCUX.FFDIR_FFD0_3
    589 #define SCUXFDAIR_FFD0_3 SCUX.FDAIR_FFD0_3
    590 #define SCUXDRQSR_FFD0_3 SCUX.DRQSR_FFD0_3
    591 #define SCUXFFDPR_FFD0_3 SCUX.FFDPR_FFD0_3
    592 #define SCUXFFDBR_FFD0_3 SCUX.FFDBR_FFD0_3
    593 #define SCUXDEVMR_FFD0_3 SCUX.DEVMR_FFD0_3
    594 #define SCUXDEVCR_FFD0_3 SCUX.DEVCR_FFD0_3
    595 #define SCUXFFUIR_FFU0_0 SCUX.FFUIR_FFU0_0
    596 #define SCUXFUAIR_FFU0_0 SCUX.FUAIR_FFU0_0
    597 #define SCUXURQSR_FFU0_0 SCUX.URQSR_FFU0_0
    598 #define SCUXFFUPR_FFU0_0 SCUX.FFUPR_FFU0_0
    599 #define SCUXUEVMR_FFU0_0 SCUX.UEVMR_FFU0_0
    600 #define SCUXUEVCR_FFU0_0 SCUX.UEVCR_FFU0_0
    601 #define SCUXFFUIR_FFU0_1 SCUX.FFUIR_FFU0_1
    602 #define SCUXFUAIR_FFU0_1 SCUX.FUAIR_FFU0_1
    603 #define SCUXURQSR_FFU0_1 SCUX.URQSR_FFU0_1
    604 #define SCUXFFUPR_FFU0_1 SCUX.FFUPR_FFU0_1
    605 #define SCUXUEVMR_FFU0_1 SCUX.UEVMR_FFU0_1
    606 #define SCUXUEVCR_FFU0_1 SCUX.UEVCR_FFU0_1
    607 #define SCUXFFUIR_FFU0_2 SCUX.FFUIR_FFU0_2
    608 #define SCUXFUAIR_FFU0_2 SCUX.FUAIR_FFU0_2
    609 #define SCUXURQSR_FFU0_2 SCUX.URQSR_FFU0_2
    610 #define SCUXFFUPR_FFU0_2 SCUX.FFUPR_FFU0_2
    611 #define SCUXUEVMR_FFU0_2 SCUX.UEVMR_FFU0_2
    612 #define SCUXUEVCR_FFU0_2 SCUX.UEVCR_FFU0_2
    613 #define SCUXFFUIR_FFU0_3 SCUX.FFUIR_FFU0_3
    614 #define SCUXFUAIR_FFU0_3 SCUX.FUAIR_FFU0_3
    615 #define SCUXURQSR_FFU0_3 SCUX.URQSR_FFU0_3
    616 #define SCUXFFUPR_FFU0_3 SCUX.FFUPR_FFU0_3
    617 #define SCUXUEVMR_FFU0_3 SCUX.UEVMR_FFU0_3
    618 #define SCUXUEVCR_FFU0_3 SCUX.UEVCR_FFU0_3
    619 #define SCUXSRCIR0_2SRC0_0 SCUX.SRCIR0_2SRC0_0
    620 #define SCUXSADIR0_2SRC0_0 SCUX.SADIR0_2SRC0_0
    621 #define SCUXSRCBR0_2SRC0_0 SCUX.SRCBR0_2SRC0_0
    622 #define SCUXIFSCR0_2SRC0_0 SCUX.IFSCR0_2SRC0_0
    623 #define SCUXIFSVR0_2SRC0_0 SCUX.IFSVR0_2SRC0_0
    624 #define SCUXSRCCR0_2SRC0_0 SCUX.SRCCR0_2SRC0_0
    625 #define SCUXMNFSR0_2SRC0_0 SCUX.MNFSR0_2SRC0_0
    626 #define SCUXBFSSR0_2SRC0_0 SCUX.BFSSR0_2SRC0_0
    627 #define SCUXSC2SR0_2SRC0_0 SCUX.SC2SR0_2SRC0_0
    628 #define SCUXWATSR0_2SRC0_0 SCUX.WATSR0_2SRC0_0
    629 #define SCUXSEVMR0_2SRC0_0 SCUX.SEVMR0_2SRC0_0
    630 #define SCUXSEVCR0_2SRC0_0 SCUX.SEVCR0_2SRC0_0
    631 #define SCUXSRCIR1_2SRC0_0 SCUX.SRCIR1_2SRC0_0
    632 #define SCUXSADIR1_2SRC0_0 SCUX.SADIR1_2SRC0_0
    633 #define SCUXSRCBR1_2SRC0_0 SCUX.SRCBR1_2SRC0_0
    634 #define SCUXIFSCR1_2SRC0_0 SCUX.IFSCR1_2SRC0_0
    635 #define SCUXIFSVR1_2SRC0_0 SCUX.IFSVR1_2SRC0_0
    636 #define SCUXSRCCR1_2SRC0_0 SCUX.SRCCR1_2SRC0_0
    637 #define SCUXMNFSR1_2SRC0_0 SCUX.MNFSR1_2SRC0_0
    638 #define SCUXBFSSR1_2SRC0_0 SCUX.BFSSR1_2SRC0_0
    639 #define SCUXSC2SR1_2SRC0_0 SCUX.SC2SR1_2SRC0_0
    640 #define SCUXWATSR1_2SRC0_0 SCUX.WATSR1_2SRC0_0
    641 #define SCUXSEVMR1_2SRC0_0 SCUX.SEVMR1_2SRC0_0
    642 #define SCUXSEVCR1_2SRC0_0 SCUX.SEVCR1_2SRC0_0
    643 #define SCUXSRCIRR_2SRC0_0 SCUX.SRCIRR_2SRC0_0
    644 #define SCUXSRCIR0_2SRC0_1 SCUX.SRCIR0_2SRC0_1
    645 #define SCUXSADIR0_2SRC0_1 SCUX.SADIR0_2SRC0_1
    646 #define SCUXSRCBR0_2SRC0_1 SCUX.SRCBR0_2SRC0_1
    647 #define SCUXIFSCR0_2SRC0_1 SCUX.IFSCR0_2SRC0_1
    648 #define SCUXIFSVR0_2SRC0_1 SCUX.IFSVR0_2SRC0_1
    649 #define SCUXSRCCR0_2SRC0_1 SCUX.SRCCR0_2SRC0_1
    650 #define SCUXMNFSR0_2SRC0_1 SCUX.MNFSR0_2SRC0_1
    651 #define SCUXBFSSR0_2SRC0_1 SCUX.BFSSR0_2SRC0_1
    652 #define SCUXSC2SR0_2SRC0_1 SCUX.SC2SR0_2SRC0_1
    653 #define SCUXWATSR0_2SRC0_1 SCUX.WATSR0_2SRC0_1
    654 #define SCUXSEVMR0_2SRC0_1 SCUX.SEVMR0_2SRC0_1
    655 #define SCUXSEVCR0_2SRC0_1 SCUX.SEVCR0_2SRC0_1
    656 #define SCUXSRCIR1_2SRC0_1 SCUX.SRCIR1_2SRC0_1
    657 #define SCUXSADIR1_2SRC0_1 SCUX.SADIR1_2SRC0_1
    658 #define SCUXSRCBR1_2SRC0_1 SCUX.SRCBR1_2SRC0_1
    659 #define SCUXIFSCR1_2SRC0_1 SCUX.IFSCR1_2SRC0_1
    660 #define SCUXIFSVR1_2SRC0_1 SCUX.IFSVR1_2SRC0_1
    661 #define SCUXSRCCR1_2SRC0_1 SCUX.SRCCR1_2SRC0_1
    662 #define SCUXMNFSR1_2SRC0_1 SCUX.MNFSR1_2SRC0_1
    663 #define SCUXBFSSR1_2SRC0_1 SCUX.BFSSR1_2SRC0_1
    664 #define SCUXSC2SR1_2SRC0_1 SCUX.SC2SR1_2SRC0_1
    665 #define SCUXWATSR1_2SRC0_1 SCUX.WATSR1_2SRC0_1
    666 #define SCUXSEVMR1_2SRC0_1 SCUX.SEVMR1_2SRC0_1
    667 #define SCUXSEVCR1_2SRC0_1 SCUX.SEVCR1_2SRC0_1
    668 #define SCUXSRCIRR_2SRC0_1 SCUX.SRCIRR_2SRC0_1
    669 #define SCUXDVUIR_DVU0_0 SCUX.DVUIR_DVU0_0
    670 #define SCUXVADIR_DVU0_0 SCUX.VADIR_DVU0_0
    671 #define SCUXDVUBR_DVU0_0 SCUX.DVUBR_DVU0_0
    672 #define SCUXDVUCR_DVU0_0 SCUX.DVUCR_DVU0_0
    673 #define SCUXZCMCR_DVU0_0 SCUX.ZCMCR_DVU0_0
    674 #define SCUXVRCTR_DVU0_0 SCUX.VRCTR_DVU0_0
    675 #define SCUXVRPDR_DVU0_0 SCUX.VRPDR_DVU0_0
    676 #define SCUXVRDBR_DVU0_0 SCUX.VRDBR_DVU0_0
    677 #define SCUXVRWTR_DVU0_0 SCUX.VRWTR_DVU0_0
    678 #define SCUXVOL0R_DVU0_0 SCUX.VOL0R_DVU0_0
    679 #define SCUXVOL1R_DVU0_0 SCUX.VOL1R_DVU0_0
    680 #define SCUXVOL2R_DVU0_0 SCUX.VOL2R_DVU0_0
    681 #define SCUXVOL3R_DVU0_0 SCUX.VOL3R_DVU0_0
    682 #define SCUXVOL4R_DVU0_0 SCUX.VOL4R_DVU0_0
    683 #define SCUXVOL5R_DVU0_0 SCUX.VOL5R_DVU0_0
    684 #define SCUXVOL6R_DVU0_0 SCUX.VOL6R_DVU0_0
    685 #define SCUXVOL7R_DVU0_0 SCUX.VOL7R_DVU0_0
    686 #define SCUXDVUER_DVU0_0 SCUX.DVUER_DVU0_0
    687 #define SCUXDVUSR_DVU0_0 SCUX.DVUSR_DVU0_0
    688 #define SCUXVEVMR_DVU0_0 SCUX.VEVMR_DVU0_0
    689 #define SCUXVEVCR_DVU0_0 SCUX.VEVCR_DVU0_0
    690 #define SCUXDVUIR_DVU0_1 SCUX.DVUIR_DVU0_1
    691 #define SCUXVADIR_DVU0_1 SCUX.VADIR_DVU0_1
    692 #define SCUXDVUBR_DVU0_1 SCUX.DVUBR_DVU0_1
    693 #define SCUXDVUCR_DVU0_1 SCUX.DVUCR_DVU0_1
    694 #define SCUXZCMCR_DVU0_1 SCUX.ZCMCR_DVU0_1
    695 #define SCUXVRCTR_DVU0_1 SCUX.VRCTR_DVU0_1
    696 #define SCUXVRPDR_DVU0_1 SCUX.VRPDR_DVU0_1
    697 #define SCUXVRDBR_DVU0_1 SCUX.VRDBR_DVU0_1
    698 #define SCUXVRWTR_DVU0_1 SCUX.VRWTR_DVU0_1
    699 #define SCUXVOL0R_DVU0_1 SCUX.VOL0R_DVU0_1
    700 #define SCUXVOL1R_DVU0_1 SCUX.VOL1R_DVU0_1
    701 #define SCUXVOL2R_DVU0_1 SCUX.VOL2R_DVU0_1
    702 #define SCUXVOL3R_DVU0_1 SCUX.VOL3R_DVU0_1
    703 #define SCUXVOL4R_DVU0_1 SCUX.VOL4R_DVU0_1
    704 #define SCUXVOL5R_DVU0_1 SCUX.VOL5R_DVU0_1
    705 #define SCUXVOL6R_DVU0_1 SCUX.VOL6R_DVU0_1
    706 #define SCUXVOL7R_DVU0_1 SCUX.VOL7R_DVU0_1
    707 #define SCUXDVUER_DVU0_1 SCUX.DVUER_DVU0_1
    708 #define SCUXDVUSR_DVU0_1 SCUX.DVUSR_DVU0_1
    709 #define SCUXVEVMR_DVU0_1 SCUX.VEVMR_DVU0_1
    710 #define SCUXVEVCR_DVU0_1 SCUX.VEVCR_DVU0_1
    711 #define SCUXDVUIR_DVU0_2 SCUX.DVUIR_DVU0_2
    712 #define SCUXVADIR_DVU0_2 SCUX.VADIR_DVU0_2
    713 #define SCUXDVUBR_DVU0_2 SCUX.DVUBR_DVU0_2
    714 #define SCUXDVUCR_DVU0_2 SCUX.DVUCR_DVU0_2
    715 #define SCUXZCMCR_DVU0_2 SCUX.ZCMCR_DVU0_2
    716 #define SCUXVRCTR_DVU0_2 SCUX.VRCTR_DVU0_2
    717 #define SCUXVRPDR_DVU0_2 SCUX.VRPDR_DVU0_2
    718 #define SCUXVRDBR_DVU0_2 SCUX.VRDBR_DVU0_2
    719 #define SCUXVRWTR_DVU0_2 SCUX.VRWTR_DVU0_2
    720 #define SCUXVOL0R_DVU0_2 SCUX.VOL0R_DVU0_2
    721 #define SCUXVOL1R_DVU0_2 SCUX.VOL1R_DVU0_2
    722 #define SCUXVOL2R_DVU0_2 SCUX.VOL2R_DVU0_2
    723 #define SCUXVOL3R_DVU0_2 SCUX.VOL3R_DVU0_2
    724 #define SCUXVOL4R_DVU0_2 SCUX.VOL4R_DVU0_2
    725 #define SCUXVOL5R_DVU0_2 SCUX.VOL5R_DVU0_2
    726 #define SCUXVOL6R_DVU0_2 SCUX.VOL6R_DVU0_2
    727 #define SCUXVOL7R_DVU0_2 SCUX.VOL7R_DVU0_2
    728 #define SCUXDVUER_DVU0_2 SCUX.DVUER_DVU0_2
    729 #define SCUXDVUSR_DVU0_2 SCUX.DVUSR_DVU0_2
    730 #define SCUXVEVMR_DVU0_2 SCUX.VEVMR_DVU0_2
    731 #define SCUXVEVCR_DVU0_2 SCUX.VEVCR_DVU0_2
    732 #define SCUXDVUIR_DVU0_3 SCUX.DVUIR_DVU0_3
    733 #define SCUXVADIR_DVU0_3 SCUX.VADIR_DVU0_3
    734 #define SCUXDVUBR_DVU0_3 SCUX.DVUBR_DVU0_3
    735 #define SCUXDVUCR_DVU0_3 SCUX.DVUCR_DVU0_3
    736 #define SCUXZCMCR_DVU0_3 SCUX.ZCMCR_DVU0_3
    737 #define SCUXVRCTR_DVU0_3 SCUX.VRCTR_DVU0_3
    738 #define SCUXVRPDR_DVU0_3 SCUX.VRPDR_DVU0_3
    739 #define SCUXVRDBR_DVU0_3 SCUX.VRDBR_DVU0_3
    740 #define SCUXVRWTR_DVU0_3 SCUX.VRWTR_DVU0_3
    741 #define SCUXVOL0R_DVU0_3 SCUX.VOL0R_DVU0_3
    742 #define SCUXVOL1R_DVU0_3 SCUX.VOL1R_DVU0_3
    743 #define SCUXVOL2R_DVU0_3 SCUX.VOL2R_DVU0_3
    744 #define SCUXVOL3R_DVU0_3 SCUX.VOL3R_DVU0_3
    745 #define SCUXVOL4R_DVU0_3 SCUX.VOL4R_DVU0_3
    746 #define SCUXVOL5R_DVU0_3 SCUX.VOL5R_DVU0_3
    747 #define SCUXVOL6R_DVU0_3 SCUX.VOL6R_DVU0_3
    748 #define SCUXVOL7R_DVU0_3 SCUX.VOL7R_DVU0_3
    749 #define SCUXDVUER_DVU0_3 SCUX.DVUER_DVU0_3
    750 #define SCUXDVUSR_DVU0_3 SCUX.DVUSR_DVU0_3
    751 #define SCUXVEVMR_DVU0_3 SCUX.VEVMR_DVU0_3
    752 #define SCUXVEVCR_DVU0_3 SCUX.VEVCR_DVU0_3
    753 #define SCUXMIXIR_MIX0_0 SCUX.MIXIR_MIX0_0
    754 #define SCUXMADIR_MIX0_0 SCUX.MADIR_MIX0_0
    755 #define SCUXMIXBR_MIX0_0 SCUX.MIXBR_MIX0_0
    756 #define SCUXMIXMR_MIX0_0 SCUX.MIXMR_MIX0_0
    757 #define SCUXMVPDR_MIX0_0 SCUX.MVPDR_MIX0_0
    758 #define SCUXMDBAR_MIX0_0 SCUX.MDBAR_MIX0_0
    759 #define SCUXMDBBR_MIX0_0 SCUX.MDBBR_MIX0_0
    760 #define SCUXMDBCR_MIX0_0 SCUX.MDBCR_MIX0_0
    761 #define SCUXMDBDR_MIX0_0 SCUX.MDBDR_MIX0_0
    762 #define SCUXMDBER_MIX0_0 SCUX.MDBER_MIX0_0
    763 #define SCUXMIXSR_MIX0_0 SCUX.MIXSR_MIX0_0
    764 #define SCUXSWRSR_CIM SCUX.SWRSR_CIM
    765 #define SCUXDMACR_CIM SCUX.DMACR_CIM
    766 #define SCUXDMATD0_CIM SCUX.DMATD0_CIM.UINT32
    767 #define SCUXDMATD0_CIML SCUX.DMATD0_CIM.UINT16[L]
    768 #define SCUXDMATD0_CIMH SCUX.DMATD0_CIM.UINT16[H]
    769 #define SCUXDMATD1_CIM SCUX.DMATD1_CIM.UINT32
    770 #define SCUXDMATD1_CIML SCUX.DMATD1_CIM.UINT16[L]
    771 #define SCUXDMATD1_CIMH SCUX.DMATD1_CIM.UINT16[H]
    772 #define SCUXDMATD2_CIM SCUX.DMATD2_CIM.UINT32
    773 #define SCUXDMATD2_CIML SCUX.DMATD2_CIM.UINT16[L]
    774 #define SCUXDMATD2_CIMH SCUX.DMATD2_CIM.UINT16[H]
    775 #define SCUXDMATD3_CIM SCUX.DMATD3_CIM.UINT32
    776 #define SCUXDMATD3_CIML SCUX.DMATD3_CIM.UINT16[L]
    777 #define SCUXDMATD3_CIMH SCUX.DMATD3_CIM.UINT16[H]
    778 #define SCUXDMATU0_CIM SCUX.DMATU0_CIM.UINT32
    779 #define SCUXDMATU0_CIML SCUX.DMATU0_CIM.UINT16[L]
    780 #define SCUXDMATU0_CIMH SCUX.DMATU0_CIM.UINT16[H]
    781 #define SCUXDMATU1_CIM SCUX.DMATU1_CIM.UINT32
    782 #define SCUXDMATU1_CIML SCUX.DMATU1_CIM.UINT16[L]
    783 #define SCUXDMATU1_CIMH SCUX.DMATU1_CIM.UINT16[H]
    784 #define SCUXDMATU2_CIM SCUX.DMATU2_CIM.UINT32
    785 #define SCUXDMATU2_CIML SCUX.DMATU2_CIM.UINT16[L]
    786 #define SCUXDMATU2_CIMH SCUX.DMATU2_CIM.UINT16[H]
    787 #define SCUXDMATU3_CIM SCUX.DMATU3_CIM.UINT32
    788 #define SCUXDMATU3_CIML SCUX.DMATU3_CIM.UINT16[L]
    789 #define SCUXDMATU3_CIMH SCUX.DMATU3_CIM.UINT16[H]
    790 #define SCUXSSIRSEL_CIM SCUX.SSIRSEL_CIM
    791 #define SCUXFDTSEL0_CIM SCUX.FDTSEL0_CIM
    792 #define SCUXFDTSEL1_CIM SCUX.FDTSEL1_CIM
    793 #define SCUXFDTSEL2_CIM SCUX.FDTSEL2_CIM
    794 #define SCUXFDTSEL3_CIM SCUX.FDTSEL3_CIM
    795 #define SCUXFUTSEL0_CIM SCUX.FUTSEL0_CIM
    796 #define SCUXFUTSEL1_CIM SCUX.FUTSEL1_CIM
    797 #define SCUXFUTSEL2_CIM SCUX.FUTSEL2_CIM
    798 #define SCUXFUTSEL3_CIM SCUX.FUTSEL3_CIM
    799 #define SCUXSSIPMD_CIM SCUX.SSIPMD_CIM
    800 #define SCUXSSICTRL_CIM SCUX.SSICTRL_CIM
    801 #define SCUXSRCRSEL0_CIM SCUX.SRCRSEL0_CIM
    802 #define SCUXSRCRSEL1_CIM SCUX.SRCRSEL1_CIM
    803 #define SCUXSRCRSEL2_CIM SCUX.SRCRSEL2_CIM
    804 #define SCUXSRCRSEL3_CIM SCUX.SRCRSEL3_CIM
    805 #define SCUXMIXRSEL_CIM SCUX.MIXRSEL_CIM
     869} r_io_scux_from_dvuir_dvu0_n_t;
     870
     871
     872/* Channel array defines of SCUX (2)*/
     873#ifdef  DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS
     874volatile struct st_scux_from_dvuir_dvu0_n*  SCUX_FROM_DVUIR_DVU0_0_ARRAY[ SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT ] =
     875    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     876    SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST;
     877    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     878#endif  /* DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS */
     879
     880#ifdef  DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS
     881volatile struct st_scux_from_srcir0_2src0_n*  SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT ] =
     882    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     883    SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST;
     884    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     885#endif  /* DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS */
     886
     887#ifdef  DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS
     888volatile struct st_scux_from_ffuir_ffu0_n*  SCUX_FROM_FFUIR_FFU0_0_ARRAY[ SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT ] =
     889    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     890    SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST;
     891    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     892#endif  /* DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS */
     893
     894#ifdef  DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS
     895volatile struct st_scux_from_ffdir_ffd0_n*  SCUX_FROM_FFDIR_FFD0_0_ARRAY[ SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT ] =
     896    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     897    SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST;
     898    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     899#endif  /* DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS */
     900
     901#ifdef  DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS
     902volatile struct st_scux_from_opcir_opc0_n*  SCUX_FROM_OPCIR_OPC0_0_ARRAY[ SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT ] =
     903    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     904    SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST;
     905    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     906#endif  /* DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS */
     907
     908#ifdef  DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS
     909volatile struct st_scux_from_ipcir_ipc0_n*  SCUX_FROM_IPCIR_IPC0_0_ARRAY[ SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT ] =
     910    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     911    SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST;
     912    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     913#endif  /* DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS */
     914/* End of channel array defines of SCUX (2)*/
     915
     916
    806917/* <-SEC M1.10.1 */
     918/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     919/* <-QAC 0857 */
    807920/* <-QAC 0639 */
    808921#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/sdg_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef SDG_IODEFINE_H
    3030#define SDG_IODEFINE_H
    31 
    32 struct st_sdg
    33 {                                                          /* SDG              */
    34     volatile uint8_t   SGCR1;                                  /*  SGCR1           */
    35     volatile uint8_t   SGCSR;                                  /*  SGCSR           */
    36     volatile uint8_t   SGCR2;                                  /*  SGCR2           */
    37     volatile uint8_t   SGLR;                                   /*  SGLR            */
    38     volatile uint8_t   SGTFR;                                  /*  SGTFR           */
    39     volatile uint8_t   SGSFR;                                  /*  SGSFR           */
    40 };
    41 
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
     34/* ->SEC M1.10.1 : Not magic number */
    4235
    4336#define SDG0    (*(struct st_sdg     *)0xFCFF4800uL) /* SDG0 */
    … …  
    4740
    4841
    49 /* Start of channnel array defines of SDG */
     42/* Start of channel array defines of SDG */
    5043
    51 /* Channnel array defines of SDG */
     44/* Channel array defines of SDG */
    5245/*(Sample) value = SDG[ channel ]->SGCR1; */
    53 #define SDG_COUNT  4
     46#define SDG_COUNT  (4)
    5447#define SDG_ADDRESS_LIST \
    5548{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    … …  
    5750}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    5851
    59 /* End of channnel array defines of SDG */
     52/* End of channel array defines of SDG */
    6053
    6154
    62 #define SGCR1_0 SDG0.SGCR1
    63 #define SGCSR_0 SDG0.SGCSR
    64 #define SGCR2_0 SDG0.SGCR2
    65 #define SGLR_0 SDG0.SGLR
    66 #define SGTFR_0 SDG0.SGTFR
    67 #define SGSFR_0 SDG0.SGSFR
    68 #define SGCR1_1 SDG1.SGCR1
    69 #define SGCSR_1 SDG1.SGCSR
    70 #define SGCR2_1 SDG1.SGCR2
    71 #define SGLR_1 SDG1.SGLR
    72 #define SGTFR_1 SDG1.SGTFR
    73 #define SGSFR_1 SDG1.SGSFR
    74 #define SGCR1_2 SDG2.SGCR1
    75 #define SGCSR_2 SDG2.SGCSR
    76 #define SGCR2_2 SDG2.SGCR2
    77 #define SGLR_2 SDG2.SGLR
    78 #define SGTFR_2 SDG2.SGTFR
    79 #define SGSFR_2 SDG2.SGSFR
    80 #define SGCR1_3 SDG3.SGCR1
    81 #define SGCSR_3 SDG3.SGCSR
    82 #define SGCR2_3 SDG3.SGCR2
    83 #define SGLR_3 SDG3.SGLR
    84 #define SGTFR_3 SDG3.SGTFR
    85 #define SGSFR_3 SDG3.SGSFR
     55#define SGCR1_0 (SDG0.SGCR1)
     56#define SGCSR_0 (SDG0.SGCSR)
     57#define SGCR2_0 (SDG0.SGCR2)
     58#define SGLR_0 (SDG0.SGLR)
     59#define SGTFR_0 (SDG0.SGTFR)
     60#define SGSFR_0 (SDG0.SGSFR)
     61#define SGCR1_1 (SDG1.SGCR1)
     62#define SGCSR_1 (SDG1.SGCSR)
     63#define SGCR2_1 (SDG1.SGCR2)
     64#define SGLR_1 (SDG1.SGLR)
     65#define SGTFR_1 (SDG1.SGTFR)
     66#define SGSFR_1 (SDG1.SGSFR)
     67#define SGCR1_2 (SDG2.SGCR1)
     68#define SGCSR_2 (SDG2.SGCSR)
     69#define SGCR2_2 (SDG2.SGCR2)
     70#define SGLR_2 (SDG2.SGLR)
     71#define SGTFR_2 (SDG2.SGTFR)
     72#define SGSFR_2 (SDG2.SGSFR)
     73#define SGCR1_3 (SDG3.SGCR1)
     74#define SGCSR_3 (SDG3.SGCSR)
     75#define SGCR2_3 (SDG3.SGCR2)
     76#define SGLR_3 (SDG3.SGLR)
     77#define SGTFR_3 (SDG3.SGTFR)
     78#define SGSFR_3 (SDG3.SGSFR)
     79
     80
     81typedef struct st_sdg
     82{
     83                                                           /* SDG              */
     84    volatile uint8_t   SGCR1;                                  /*  SGCR1           */
     85    volatile uint8_t   SGCSR;                                  /*  SGCSR           */
     86    volatile uint8_t   SGCR2;                                  /*  SGCR2           */
     87    volatile uint8_t   SGLR;                                   /*  SGLR            */
     88    volatile uint8_t   SGTFR;                                  /*  SGTFR           */
     89    volatile uint8_t   SGSFR;                                  /*  SGSFR           */
     90} r_io_sdg_t;
     91
     92
     93/* Channel array defines of SDG (2)*/
     94#ifdef  DECLARE_SDG_CHANNELS
     95volatile struct st_sdg*  SDG[ SDG_COUNT ] =
     96    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     97    SDG_ADDRESS_LIST;
     98    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     99#endif  /* DECLARE_SDG_CHANNELS */
     100/* End of channel array defines of SDG (2)*/
     101
     102
     103/* <-SEC M1.10.1 */
     104/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     105/* <-QAC 0857 */
     106/* <-QAC 0639 */
    86107#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/spdif_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef SPDIF_IODEFINE_H
    3030#define SPDIF_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
     34/* ->SEC M1.10.1 : Not magic number */
    3135
    32 struct st_spdif
    33 {                                                          /* SPDIF            */
     36#define SPDIF   (*(struct st_spdif   *)0xE8012000uL) /* SPDIF */
     37
     38
     39#define SPDIFTLCA (SPDIF.TLCA)
     40#define SPDIFTRCA (SPDIF.TRCA)
     41#define SPDIFTLCS (SPDIF.TLCS)
     42#define SPDIFTRCS (SPDIF.TRCS)
     43#define SPDIFTUI (SPDIF.TUI)
     44#define SPDIFRLCA (SPDIF.RLCA)
     45#define SPDIFRRCA (SPDIF.RRCA)
     46#define SPDIFRLCS (SPDIF.RLCS)
     47#define SPDIFRRCS (SPDIF.RRCS)
     48#define SPDIFRUI (SPDIF.RUI)
     49#define SPDIFCTRL (SPDIF.CTRL)
     50#define SPDIFSTAT (SPDIF.STAT)
     51#define SPDIFTDAD (SPDIF.TDAD)
     52#define SPDIFRDAD (SPDIF.RDAD)
     53
     54
     55typedef struct st_spdif
     56{
     57                                                           /* SPDIF            */
    3458    volatile uint32_t  TLCA;                                   /*  TLCA            */
    3559    volatile uint32_t  TRCA;                                   /*  TRCA            */
    … …  
    4670    volatile uint32_t  TDAD;                                   /*  TDAD            */
    4771    volatile uint32_t  RDAD;                                   /*  RDAD            */
    48 };
     72} r_io_spdif_t;
    4973
    5074
    51 #define SPDIF   (*(struct st_spdif   *)0xE8012000uL) /* SPDIF */
    52 
    53 
    54 #define SPDIFTLCA SPDIF.TLCA
    55 #define SPDIFTRCA SPDIF.TRCA
    56 #define SPDIFTLCS SPDIF.TLCS
    57 #define SPDIFTRCS SPDIF.TRCS
    58 #define SPDIFTUI SPDIF.TUI
    59 #define SPDIFRLCA SPDIF.RLCA
    60 #define SPDIFRRCA SPDIF.RRCA
    61 #define SPDIFRLCS SPDIF.RLCS
    62 #define SPDIFRRCS SPDIF.RRCS
    63 #define SPDIFRUI SPDIF.RUI
    64 #define SPDIFCTRL SPDIF.CTRL
    65 #define SPDIFSTAT SPDIF.STAT
    66 #define SPDIFTDAD SPDIF.TDAD
    67 #define SPDIFRDAD SPDIF.RDAD
     75/* <-SEC M1.10.1 */
     76/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     77/* <-QAC 0857 */
     78/* <-QAC 0639 */
    6879#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef SPIBSC_IODEFINE_H
    3030#define SPIBSC_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3134/* ->SEC M1.10.1 : Not magic number */
    3235
    33 struct st_spibsc
    34 {                                                          /* SPIBSC           */
     36#define SPIBSC0 (*(struct st_spibsc  *)0x3FEFA000uL) /* SPIBSC0 */
     37#define SPIBSC1 (*(struct st_spibsc  *)0x3FEFB000uL) /* SPIBSC1 */
     38
     39
     40/* Start of channel array defines of SPIBSC */
     41
     42/* Channel array defines of SPIBSC */
     43/*(Sample) value = SPIBSC[ channel ]->CMNCR; */
     44#define SPIBSC_COUNT  (2)
     45#define SPIBSC_ADDRESS_LIST \
     46{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     47    &SPIBSC0, &SPIBSC1 \
     48}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     49
     50/* End of channel array defines of SPIBSC */
     51
     52
     53#define CMNCR_0 (SPIBSC0.CMNCR)
     54#define SSLDR_0 (SPIBSC0.SSLDR)
     55#define SPBCR_0 (SPIBSC0.SPBCR)
     56#define DRCR_0 (SPIBSC0.DRCR)
     57#define DRCMR_0 (SPIBSC0.DRCMR)
     58#define DREAR_0 (SPIBSC0.DREAR)
     59#define DROPR_0 (SPIBSC0.DROPR)
     60#define DRENR_0 (SPIBSC0.DRENR)
     61#define SMCR_0 (SPIBSC0.SMCR)
     62#define SMCMR_0 (SPIBSC0.SMCMR)
     63#define SMADR_0 (SPIBSC0.SMADR)
     64#define SMOPR_0 (SPIBSC0.SMOPR)
     65#define SMENR_0 (SPIBSC0.SMENR)
     66#define SMRDR0_0   (SPIBSC0.SMRDR0.UINT32)
     67#define SMRDR0_0L  (SPIBSC0.SMRDR0.UINT16[R_IO_L])
     68#define SMRDR0_0H  (SPIBSC0.SMRDR0.UINT16[R_IO_H])
     69#define SMRDR0_0LL (SPIBSC0.SMRDR0.UINT8[R_IO_LL])
     70#define SMRDR0_0LH (SPIBSC0.SMRDR0.UINT8[R_IO_LH])
     71#define SMRDR0_0HL (SPIBSC0.SMRDR0.UINT8[R_IO_HL])
     72#define SMRDR0_0HH (SPIBSC0.SMRDR0.UINT8[R_IO_HH])
     73#define SMRDR1_0   (SPIBSC0.SMRDR1.UINT32)
     74#define SMRDR1_0L  (SPIBSC0.SMRDR1.UINT16[R_IO_L])
     75#define SMRDR1_0H  (SPIBSC0.SMRDR1.UINT16[R_IO_H])
     76#define SMRDR1_0LL (SPIBSC0.SMRDR1.UINT8[R_IO_LL])
     77#define SMRDR1_0LH (SPIBSC0.SMRDR1.UINT8[R_IO_LH])
     78#define SMRDR1_0HL (SPIBSC0.SMRDR1.UINT8[R_IO_HL])
     79#define SMRDR1_0HH (SPIBSC0.SMRDR1.UINT8[R_IO_HH])
     80#define SMWDR0_0   (SPIBSC0.SMWDR0.UINT32)
     81#define SMWDR0_0L  (SPIBSC0.SMWDR0.UINT16[R_IO_L])
     82#define SMWDR0_0H  (SPIBSC0.SMWDR0.UINT16[R_IO_H])
     83#define SMWDR0_0LL (SPIBSC0.SMWDR0.UINT8[R_IO_LL])
     84#define SMWDR0_0LH (SPIBSC0.SMWDR0.UINT8[R_IO_LH])
     85#define SMWDR0_0HL (SPIBSC0.SMWDR0.UINT8[R_IO_HL])
     86#define SMWDR0_0HH (SPIBSC0.SMWDR0.UINT8[R_IO_HH])
     87#define SMWDR1_0   (SPIBSC0.SMWDR1.UINT32)
     88#define SMWDR1_0L  (SPIBSC0.SMWDR1.UINT16[R_IO_L])
     89#define SMWDR1_0H  (SPIBSC0.SMWDR1.UINT16[R_IO_H])
     90#define SMWDR1_0LL (SPIBSC0.SMWDR1.UINT8[R_IO_LL])
     91#define SMWDR1_0LH (SPIBSC0.SMWDR1.UINT8[R_IO_LH])
     92#define SMWDR1_0HL (SPIBSC0.SMWDR1.UINT8[R_IO_HL])
     93#define SMWDR1_0HH (SPIBSC0.SMWDR1.UINT8[R_IO_HH])
     94#define CMNSR_0 (SPIBSC0.CMNSR)
     95#define CKDLY_0 (SPIBSC0.CKDLY)
     96#define DRDMCR_0 (SPIBSC0.DRDMCR)
     97#define DRDRENR_0 (SPIBSC0.DRDRENR)
     98#define SMDMCR_0 (SPIBSC0.SMDMCR)
     99#define SMDRENR_0 (SPIBSC0.SMDRENR)
     100#define SPODLY_0 (SPIBSC0.SPODLY)
     101#define CMNCR_1 (SPIBSC1.CMNCR)
     102#define SSLDR_1 (SPIBSC1.SSLDR)
     103#define SPBCR_1 (SPIBSC1.SPBCR)
     104#define DRCR_1 (SPIBSC1.DRCR)
     105#define DRCMR_1 (SPIBSC1.DRCMR)
     106#define DREAR_1 (SPIBSC1.DREAR)
     107#define DROPR_1 (SPIBSC1.DROPR)
     108#define DRENR_1 (SPIBSC1.DRENR)
     109#define SMCR_1 (SPIBSC1.SMCR)
     110#define SMCMR_1 (SPIBSC1.SMCMR)
     111#define SMADR_1 (SPIBSC1.SMADR)
     112#define SMOPR_1 (SPIBSC1.SMOPR)
     113#define SMENR_1 (SPIBSC1.SMENR)
     114#define SMRDR0_1   (SPIBSC1.SMRDR0.UINT32)
     115#define SMRDR0_1L  (SPIBSC1.SMRDR0.UINT16[R_IO_L])
     116#define SMRDR0_1H  (SPIBSC1.SMRDR0.UINT16[R_IO_H])
     117#define SMRDR0_1LL (SPIBSC1.SMRDR0.UINT8[R_IO_LL])
     118#define SMRDR0_1LH (SPIBSC1.SMRDR0.UINT8[R_IO_LH])
     119#define SMRDR0_1HL (SPIBSC1.SMRDR0.UINT8[R_IO_HL])
     120#define SMRDR0_1HH (SPIBSC1.SMRDR0.UINT8[R_IO_HH])
     121#define SMRDR1_1   (SPIBSC1.SMRDR1.UINT32)
     122#define SMRDR1_1L  (SPIBSC1.SMRDR1.UINT16[R_IO_L])
     123#define SMRDR1_1H  (SPIBSC1.SMRDR1.UINT16[R_IO_H])
     124#define SMRDR1_1LL (SPIBSC1.SMRDR1.UINT8[R_IO_LL])
     125#define SMRDR1_1LH (SPIBSC1.SMRDR1.UINT8[R_IO_LH])
     126#define SMRDR1_1HL (SPIBSC1.SMRDR1.UINT8[R_IO_HL])
     127#define SMRDR1_1HH (SPIBSC1.SMRDR1.UINT8[R_IO_HH])
     128#define SMWDR0_1   (SPIBSC1.SMWDR0.UINT32)
     129#define SMWDR0_1L  (SPIBSC1.SMWDR0.UINT16[R_IO_L])
     130#define SMWDR0_1H  (SPIBSC1.SMWDR0.UINT16[R_IO_H])
     131#define SMWDR0_1LL (SPIBSC1.SMWDR0.UINT8[R_IO_LL])
     132#define SMWDR0_1LH (SPIBSC1.SMWDR0.UINT8[R_IO_LH])
     133#define SMWDR0_1HL (SPIBSC1.SMWDR0.UINT8[R_IO_HL])
     134#define SMWDR0_1HH (SPIBSC1.SMWDR0.UINT8[R_IO_HH])
     135#define SMWDR1_1   (SPIBSC1.SMWDR1.UINT32)
     136#define SMWDR1_1L  (SPIBSC1.SMWDR1.UINT16[R_IO_L])
     137#define SMWDR1_1H  (SPIBSC1.SMWDR1.UINT16[R_IO_H])
     138#define SMWDR1_1LL (SPIBSC1.SMWDR1.UINT8[R_IO_LL])
     139#define SMWDR1_1LH (SPIBSC1.SMWDR1.UINT8[R_IO_LH])
     140#define SMWDR1_1HL (SPIBSC1.SMWDR1.UINT8[R_IO_HL])
     141#define SMWDR1_1HH (SPIBSC1.SMWDR1.UINT8[R_IO_HH])
     142#define CMNSR_1 (SPIBSC1.CMNSR)
     143#define CKDLY_1 (SPIBSC1.CKDLY)
     144#define DRDMCR_1 (SPIBSC1.DRDMCR)
     145#define DRDRENR_1 (SPIBSC1.DRDRENR)
     146#define SMDMCR_1 (SPIBSC1.SMDMCR)
     147#define SMDRENR_1 (SPIBSC1.SMDRENR)
     148#define SPODLY_1 (SPIBSC1.SPODLY)
     149
     150
     151typedef struct st_spibsc
     152{
     153                                                           /* SPIBSC           */
    35154    volatile uint32_t  CMNCR;                                  /*  CMNCR           */
    36155    volatile uint32_t  SSLDR;                                  /*  SSLDR           */
    … …  
    53172   
    54173    volatile uint32_t  CMNSR;                                  /*  CMNSR           */
    55     volatile uint8_t   dummy2[12];                             /*                  */
     174    volatile uint8_t   dummy2[4];                              /*                  */
     175    volatile uint32_t  CKDLY;                                  /*  CKDLY           */
     176    volatile uint8_t   dummy3[4];                              /*                  */
    56177    volatile uint32_t  DRDMCR;                                 /*  DRDMCR          */
    57178    volatile uint32_t  DRDRENR;                                /*  DRDRENR         */
    58179    volatile uint32_t  SMDMCR;                                 /*  SMDMCR          */
    59180    volatile uint32_t  SMDRENR;                                /*  SMDRENR         */
    60 };
     181    volatile uint32_t  SPODLY;                                 /*  SPODLY          */
     182} r_io_spibsc_t;
    61183
    62184
    63 #define SPIBSC0 (*(struct st_spibsc  *)0x3FEFA000uL) /* SPIBSC0 */
    64 #define SPIBSC1 (*(struct st_spibsc  *)0x3FEFB000uL) /* SPIBSC1 */
     185/* Channel array defines of SPIBSC (2)*/
     186#ifdef  DECLARE_SPIBSC_CHANNELS
     187volatile struct st_spibsc*  SPIBSC[ SPIBSC_COUNT ] =
     188    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     189    SPIBSC_ADDRESS_LIST;
     190    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     191#endif  /* DECLARE_SPIBSC_CHANNELS */
     192/* End of channel array defines of SPIBSC (2)*/
    65193
    66194
    67 /* Start of channnel array defines of SPIBSC */
    68 
    69 /* Channnel array defines of SPIBSC */
    70 /*(Sample) value = SPIBSC[ channel ]->CMNCR; */
    71 #define SPIBSC_COUNT  2
    72 #define SPIBSC_ADDRESS_LIST \
    73 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    74     &SPIBSC0, &SPIBSC1 \
    75 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    76 
    77 /* End of channnel array defines of SPIBSC */
    78 
    79 
    80 #define CMNCR_0 SPIBSC0.CMNCR
    81 #define SSLDR_0 SPIBSC0.SSLDR
    82 #define SPBCR_0 SPIBSC0.SPBCR
    83 #define DRCR_0 SPIBSC0.DRCR
    84 #define DRCMR_0 SPIBSC0.DRCMR
    85 #define DREAR_0 SPIBSC0.DREAR
    86 #define DROPR_0 SPIBSC0.DROPR
    87 #define DRENR_0 SPIBSC0.DRENR
    88 #define SMCR_0 SPIBSC0.SMCR
    89 #define SMCMR_0 SPIBSC0.SMCMR
    90 #define SMADR_0 SPIBSC0.SMADR
    91 #define SMOPR_0 SPIBSC0.SMOPR
    92 #define SMENR_0 SPIBSC0.SMENR
    93 #define SMRDR0_0   SPIBSC0.SMRDR0.UINT32
    94 #define SMRDR0_0L  SPIBSC0.SMRDR0.UINT16[L]
    95 #define SMRDR0_0H  SPIBSC0.SMRDR0.UINT16[H]
    96 #define SMRDR0_0LL SPIBSC0.SMRDR0.UINT8[LL]
    97 #define SMRDR0_0LH SPIBSC0.SMRDR0.UINT8[LH]
    98 #define SMRDR0_0HL SPIBSC0.SMRDR0.UINT8[HL]
    99 #define SMRDR0_0HH SPIBSC0.SMRDR0.UINT8[HH]
    100 #define SMRDR1_0   SPIBSC0.SMRDR1.UINT32
    101 #define SMRDR1_0L  SPIBSC0.SMRDR1.UINT16[L]
    102 #define SMRDR1_0H  SPIBSC0.SMRDR1.UINT16[H]
    103 #define SMRDR1_0LL SPIBSC0.SMRDR1.UINT8[LL]
    104 #define SMRDR1_0LH SPIBSC0.SMRDR1.UINT8[LH]
    105 #define SMRDR1_0HL SPIBSC0.SMRDR1.UINT8[HL]
    106 #define SMRDR1_0HH SPIBSC0.SMRDR1.UINT8[HH]
    107 #define SMWDR0_0   SPIBSC0.SMWDR0.UINT32
    108 #define SMWDR0_0L  SPIBSC0.SMWDR0.UINT16[L]
    109 #define SMWDR0_0H  SPIBSC0.SMWDR0.UINT16[H]
    110 #define SMWDR0_0LL SPIBSC0.SMWDR0.UINT8[LL]
    111 #define SMWDR0_0LH SPIBSC0.SMWDR0.UINT8[LH]
    112 #define SMWDR0_0HL SPIBSC0.SMWDR0.UINT8[HL]
    113 #define SMWDR0_0HH SPIBSC0.SMWDR0.UINT8[HH]
    114 #define SMWDR1_0   SPIBSC0.SMWDR1.UINT32
    115 #define SMWDR1_0L  SPIBSC0.SMWDR1.UINT16[L]
    116 #define SMWDR1_0H  SPIBSC0.SMWDR1.UINT16[H]
    117 #define SMWDR1_0LL SPIBSC0.SMWDR1.UINT8[LL]
    118 #define SMWDR1_0LH SPIBSC0.SMWDR1.UINT8[LH]
    119 #define SMWDR1_0HL SPIBSC0.SMWDR1.UINT8[HL]
    120 #define SMWDR1_0HH SPIBSC0.SMWDR1.UINT8[HH]
    121 #define CMNSR_0 SPIBSC0.CMNSR
    122 #define DRDMCR_0 SPIBSC0.DRDMCR
    123 #define DRDRENR_0 SPIBSC0.DRDRENR
    124 #define SMDMCR_0 SPIBSC0.SMDMCR
    125 #define SMDRENR_0 SPIBSC0.SMDRENR
    126 #define CMNCR_1 SPIBSC1.CMNCR
    127 #define SSLDR_1 SPIBSC1.SSLDR
    128 #define SPBCR_1 SPIBSC1.SPBCR
    129 #define DRCR_1 SPIBSC1.DRCR
    130 #define DRCMR_1 SPIBSC1.DRCMR
    131 #define DREAR_1 SPIBSC1.DREAR
    132 #define DROPR_1 SPIBSC1.DROPR
    133 #define DRENR_1 SPIBSC1.DRENR
    134 #define SMCR_1 SPIBSC1.SMCR
    135 #define SMCMR_1 SPIBSC1.SMCMR
    136 #define SMADR_1 SPIBSC1.SMADR
    137 #define SMOPR_1 SPIBSC1.SMOPR
    138 #define SMENR_1 SPIBSC1.SMENR
    139 #define SMRDR0_1   SPIBSC1.SMRDR0.UINT32
    140 #define SMRDR0_1L  SPIBSC1.SMRDR0.UINT16[L]
    141 #define SMRDR0_1H  SPIBSC1.SMRDR0.UINT16[H]
    142 #define SMRDR0_1LL SPIBSC1.SMRDR0.UINT8[LL]
    143 #define SMRDR0_1LH SPIBSC1.SMRDR0.UINT8[LH]
    144 #define SMRDR0_1HL SPIBSC1.SMRDR0.UINT8[HL]
    145 #define SMRDR0_1HH SPIBSC1.SMRDR0.UINT8[HH]
    146 #define SMRDR1_1   SPIBSC1.SMRDR1.UINT32
    147 #define SMRDR1_1L  SPIBSC1.SMRDR1.UINT16[L]
    148 #define SMRDR1_1H  SPIBSC1.SMRDR1.UINT16[H]
    149 #define SMRDR1_1LL SPIBSC1.SMRDR1.UINT8[LL]
    150 #define SMRDR1_1LH SPIBSC1.SMRDR1.UINT8[LH]
    151 #define SMRDR1_1HL SPIBSC1.SMRDR1.UINT8[HL]
    152 #define SMRDR1_1HH SPIBSC1.SMRDR1.UINT8[HH]
    153 #define SMWDR0_1   SPIBSC1.SMWDR0.UINT32
    154 #define SMWDR0_1L  SPIBSC1.SMWDR0.UINT16[L]
    155 #define SMWDR0_1H  SPIBSC1.SMWDR0.UINT16[H]
    156 #define SMWDR0_1LL SPIBSC1.SMWDR0.UINT8[LL]
    157 #define SMWDR0_1LH SPIBSC1.SMWDR0.UINT8[LH]
    158 #define SMWDR0_1HL SPIBSC1.SMWDR0.UINT8[HL]
    159 #define SMWDR0_1HH SPIBSC1.SMWDR0.UINT8[HH]
    160 #define SMWDR1_1   SPIBSC1.SMWDR1.UINT32
    161 #define SMWDR1_1L  SPIBSC1.SMWDR1.UINT16[L]
    162 #define SMWDR1_1H  SPIBSC1.SMWDR1.UINT16[H]
    163 #define SMWDR1_1LL SPIBSC1.SMWDR1.UINT8[LL]
    164 #define SMWDR1_1LH SPIBSC1.SMWDR1.UINT8[LH]
    165 #define SMWDR1_1HL SPIBSC1.SMWDR1.UINT8[HL]
    166 #define SMWDR1_1HH SPIBSC1.SMWDR1.UINT8[HH]
    167 #define CMNSR_1 SPIBSC1.CMNSR
    168 #define DRDMCR_1 SPIBSC1.DRDMCR
    169 #define DRDRENR_1 SPIBSC1.DRDRENR
    170 #define SMDMCR_1 SPIBSC1.SMDMCR
    171 #define SMDRENR_1 SPIBSC1.SMDRENR
    172195/* <-SEC M1.10.1 */
     196/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     197/* <-QAC 0857 */
     198/* <-QAC 0639 */
    173199#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/ssif_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef SSIF_IODEFINE_H
    3030#define SSIF_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3134/* ->SEC M1.10.1 : Not magic number */
    3235
    33 struct st_ssif
    34 {                                                          /* SSIF             */
     36#define SSIF0   (*(struct st_ssif    *)0xE820B000uL) /* SSIF0 */
     37#define SSIF1   (*(struct st_ssif    *)0xE820B800uL) /* SSIF1 */
     38#define SSIF2   (*(struct st_ssif    *)0xE820C000uL) /* SSIF2 */
     39#define SSIF3   (*(struct st_ssif    *)0xE820C800uL) /* SSIF3 */
     40#define SSIF4   (*(struct st_ssif    *)0xE820D000uL) /* SSIF4 */
     41#define SSIF5   (*(struct st_ssif    *)0xE820D800uL) /* SSIF5 */
     42
     43
     44/* Start of channel array defines of SSIF */
     45
     46/* Channel array defines of SSIF */
     47/*(Sample) value = SSIF[ channel ]->SSICR; */
     48#define SSIF_COUNT  (6)
     49#define SSIF_ADDRESS_LIST \
     50{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     51    &SSIF0, &SSIF1, &SSIF2, &SSIF3, &SSIF4, &SSIF5 \
     52}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     53
     54/* End of channel array defines of SSIF */
     55
     56
     57#define SSICR_0 (SSIF0.SSICR)
     58#define SSISR_0 (SSIF0.SSISR)
     59#define SSIFCR_0 (SSIF0.SSIFCR)
     60#define SSIFSR_0 (SSIF0.SSIFSR)
     61#define SSIFTDR_0 (SSIF0.SSIFTDR)
     62#define SSIFRDR_0 (SSIF0.SSIFRDR)
     63#define SSITDMR_0 (SSIF0.SSITDMR)
     64#define SSIFCCR_0 (SSIF0.SSIFCCR)
     65#define SSIFCMR_0 (SSIF0.SSIFCMR)
     66#define SSIFCSR_0 (SSIF0.SSIFCSR)
     67#define SSICR_1 (SSIF1.SSICR)
     68#define SSISR_1 (SSIF1.SSISR)
     69#define SSIFCR_1 (SSIF1.SSIFCR)
     70#define SSIFSR_1 (SSIF1.SSIFSR)
     71#define SSIFTDR_1 (SSIF1.SSIFTDR)
     72#define SSIFRDR_1 (SSIF1.SSIFRDR)
     73#define SSITDMR_1 (SSIF1.SSITDMR)
     74#define SSIFCCR_1 (SSIF1.SSIFCCR)
     75#define SSIFCMR_1 (SSIF1.SSIFCMR)
     76#define SSIFCSR_1 (SSIF1.SSIFCSR)
     77#define SSICR_2 (SSIF2.SSICR)
     78#define SSISR_2 (SSIF2.SSISR)
     79#define SSIFCR_2 (SSIF2.SSIFCR)
     80#define SSIFSR_2 (SSIF2.SSIFSR)
     81#define SSIFTDR_2 (SSIF2.SSIFTDR)
     82#define SSIFRDR_2 (SSIF2.SSIFRDR)
     83#define SSITDMR_2 (SSIF2.SSITDMR)
     84#define SSIFCCR_2 (SSIF2.SSIFCCR)
     85#define SSIFCMR_2 (SSIF2.SSIFCMR)
     86#define SSIFCSR_2 (SSIF2.SSIFCSR)
     87#define SSICR_3 (SSIF3.SSICR)
     88#define SSISR_3 (SSIF3.SSISR)
     89#define SSIFCR_3 (SSIF3.SSIFCR)
     90#define SSIFSR_3 (SSIF3.SSIFSR)
     91#define SSIFTDR_3 (SSIF3.SSIFTDR)
     92#define SSIFRDR_3 (SSIF3.SSIFRDR)
     93#define SSITDMR_3 (SSIF3.SSITDMR)
     94#define SSIFCCR_3 (SSIF3.SSIFCCR)
     95#define SSIFCMR_3 (SSIF3.SSIFCMR)
     96#define SSIFCSR_3 (SSIF3.SSIFCSR)
     97#define SSICR_4 (SSIF4.SSICR)
     98#define SSISR_4 (SSIF4.SSISR)
     99#define SSIFCR_4 (SSIF4.SSIFCR)
     100#define SSIFSR_4 (SSIF4.SSIFSR)
     101#define SSIFTDR_4 (SSIF4.SSIFTDR)
     102#define SSIFRDR_4 (SSIF4.SSIFRDR)
     103#define SSITDMR_4 (SSIF4.SSITDMR)
     104#define SSIFCCR_4 (SSIF4.SSIFCCR)
     105#define SSIFCMR_4 (SSIF4.SSIFCMR)
     106#define SSIFCSR_4 (SSIF4.SSIFCSR)
     107#define SSICR_5 (SSIF5.SSICR)
     108#define SSISR_5 (SSIF5.SSISR)
     109#define SSIFCR_5 (SSIF5.SSIFCR)
     110#define SSIFSR_5 (SSIF5.SSIFSR)
     111#define SSIFTDR_5 (SSIF5.SSIFTDR)
     112#define SSIFRDR_5 (SSIF5.SSIFRDR)
     113#define SSITDMR_5 (SSIF5.SSITDMR)
     114#define SSIFCCR_5 (SSIF5.SSIFCCR)
     115#define SSIFCMR_5 (SSIF5.SSIFCMR)
     116#define SSIFCSR_5 (SSIF5.SSIFCSR)
     117
     118
     119typedef struct st_ssif
     120{
     121                                                           /* SSIF             */
    35122    volatile uint32_t  SSICR;                                  /*  SSICR           */
    36123    volatile uint32_t  SSISR;                                  /*  SSISR           */
    … …  
    44131    volatile uint32_t  SSIFCMR;                                /*  SSIFCMR         */
    45132    volatile uint32_t  SSIFCSR;                                /*  SSIFCSR         */
    46 };
     133} r_io_ssif_t;
    47134
    48135
    49 #define SSIF0   (*(struct st_ssif    *)0xE820B000uL) /* SSIF0 */
    50 #define SSIF1   (*(struct st_ssif    *)0xE820B800uL) /* SSIF1 */
    51 #define SSIF2   (*(struct st_ssif    *)0xE820C000uL) /* SSIF2 */
    52 #define SSIF3   (*(struct st_ssif    *)0xE820C800uL) /* SSIF3 */
    53 #define SSIF4   (*(struct st_ssif    *)0xE820D000uL) /* SSIF4 */
    54 #define SSIF5   (*(struct st_ssif    *)0xE820D800uL) /* SSIF5 */
     136/* Channel array defines of SSIF (2)*/
     137#ifdef  DECLARE_SSIF_CHANNELS
     138volatile struct st_ssif*  SSIF[ SSIF_COUNT ] =
     139    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     140    SSIF_ADDRESS_LIST;
     141    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     142#endif  /* DECLARE_SSIF_CHANNELS */
     143/* End of channel array defines of SSIF (2)*/
    55144
    56145
    57 /* Start of channnel array defines of SSIF */
    58 
    59 /* Channnel array defines of SSIF */
    60 /*(Sample) value = SSIF[ channel ]->SSICR; */
    61 #define SSIF_COUNT  6
    62 #define SSIF_ADDRESS_LIST \
    63 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    64     &SSIF0, &SSIF1, &SSIF2, &SSIF3, &SSIF4, &SSIF5 \
    65 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    66 
    67 /* End of channnel array defines of SSIF */
    68 
    69 
    70 #define SSICR_0 SSIF0.SSICR
    71 #define SSISR_0 SSIF0.SSISR
    72 #define SSIFCR_0 SSIF0.SSIFCR
    73 #define SSIFSR_0 SSIF0.SSIFSR
    74 #define SSIFTDR_0 SSIF0.SSIFTDR
    75 #define SSIFRDR_0 SSIF0.SSIFRDR
    76 #define SSITDMR_0 SSIF0.SSITDMR
    77 #define SSIFCCR_0 SSIF0.SSIFCCR
    78 #define SSIFCMR_0 SSIF0.SSIFCMR
    79 #define SSIFCSR_0 SSIF0.SSIFCSR
    80 #define SSICR_1 SSIF1.SSICR
    81 #define SSISR_1 SSIF1.SSISR
    82 #define SSIFCR_1 SSIF1.SSIFCR
    83 #define SSIFSR_1 SSIF1.SSIFSR
    84 #define SSIFTDR_1 SSIF1.SSIFTDR
    85 #define SSIFRDR_1 SSIF1.SSIFRDR
    86 #define SSITDMR_1 SSIF1.SSITDMR
    87 #define SSIFCCR_1 SSIF1.SSIFCCR
    88 #define SSIFCMR_1 SSIF1.SSIFCMR
    89 #define SSIFCSR_1 SSIF1.SSIFCSR
    90 #define SSICR_2 SSIF2.SSICR
    91 #define SSISR_2 SSIF2.SSISR
    92 #define SSIFCR_2 SSIF2.SSIFCR
    93 #define SSIFSR_2 SSIF2.SSIFSR
    94 #define SSIFTDR_2 SSIF2.SSIFTDR
    95 #define SSIFRDR_2 SSIF2.SSIFRDR
    96 #define SSITDMR_2 SSIF2.SSITDMR
    97 #define SSIFCCR_2 SSIF2.SSIFCCR
    98 #define SSIFCMR_2 SSIF2.SSIFCMR
    99 #define SSIFCSR_2 SSIF2.SSIFCSR
    100 #define SSICR_3 SSIF3.SSICR
    101 #define SSISR_3 SSIF3.SSISR
    102 #define SSIFCR_3 SSIF3.SSIFCR
    103 #define SSIFSR_3 SSIF3.SSIFSR
    104 #define SSIFTDR_3 SSIF3.SSIFTDR
    105 #define SSIFRDR_3 SSIF3.SSIFRDR
    106 #define SSITDMR_3 SSIF3.SSITDMR
    107 #define SSIFCCR_3 SSIF3.SSIFCCR
    108 #define SSIFCMR_3 SSIF3.SSIFCMR
    109 #define SSIFCSR_3 SSIF3.SSIFCSR
    110 #define SSICR_4 SSIF4.SSICR
    111 #define SSISR_4 SSIF4.SSISR
    112 #define SSIFCR_4 SSIF4.SSIFCR
    113 #define SSIFSR_4 SSIF4.SSIFSR
    114 #define SSIFTDR_4 SSIF4.SSIFTDR
    115 #define SSIFRDR_4 SSIF4.SSIFRDR
    116 #define SSITDMR_4 SSIF4.SSITDMR
    117 #define SSIFCCR_4 SSIF4.SSIFCCR
    118 #define SSIFCMR_4 SSIF4.SSIFCMR
    119 #define SSIFCSR_4 SSIF4.SSIFCSR
    120 #define SSICR_5 SSIF5.SSICR
    121 #define SSISR_5 SSIF5.SSISR
    122 #define SSIFCR_5 SSIF5.SSIFCR
    123 #define SSIFSR_5 SSIF5.SSIFSR
    124 #define SSIFTDR_5 SSIF5.SSIFTDR
    125 #define SSIFRDR_5 SSIF5.SSIFRDR
    126 #define SSITDMR_5 SSIF5.SSITDMR
    127 #define SSIFCCR_5 SSIF5.SSIFCCR
    128 #define SSIFCMR_5 SSIF5.SSIFCMR
    129 #define SSIFCSR_5 SSIF5.SSIFCSR
    130146/* <-SEC M1.10.1 */
     147/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     148/* <-QAC 0857 */
     149/* <-QAC 0639 */
    131150#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/usb20_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef USB20_IODEFINE_H
    3030#define USB20_IODEFINE_H
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3134/* ->SEC M1.10.1 : Not magic number */
    3235
    33 struct st_usb20
    34 {                                                          /* USB20            */
     36#define USB200  (*(struct st_usb20   *)0xE8010000uL) /* USB200 */
     37#define USB201  (*(struct st_usb20   *)0xE8207000uL) /* USB201 */
     38
     39
     40/* Start of channel array defines of USB20 */
     41
     42/* Channel array defines of USB20 */
     43/*(Sample) value = USB20[ channel ]->SYSCFG0; */
     44#define USB20_COUNT  (2)
     45#define USB20_ADDRESS_LIST \
     46{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     47    &USB200, &USB201 \
     48}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     49
     50
     51
     52/* Channel array defines of USB20_FROM_D0FIFOB0 */
     53/*(Sample) value = USB20_FROM_D0FIFOB0[ channel ][ index ]->D0FIFOB0; */
     54#define USB20_FROM_D0FIFOB0_COUNT  (2)
     55#define USB20_FROM_D0FIFOB0_ADDRESS_LIST \
     56{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     57{ \
     58    &USB200_FROM_D0FIFOB0, &USB200_FROM_D1FIFOB0 },{ \
     59    &USB201_FROM_D0FIFOB0, &USB201_FROM_D1FIFOB0 \
     60} \
     61}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     62#define USB200_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D0FIFOB0) /* USB200_FROM_D0FIFOB0 */
     63#define USB200_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D1FIFOB0) /* USB200_FROM_D1FIFOB0 */
     64#define USB201_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D0FIFOB0) /* USB201_FROM_D0FIFOB0 */
     65#define USB201_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D1FIFOB0) /* USB201_FROM_D1FIFOB0 */
     66
     67
     68
     69
     70/* Channel array defines of USB20_FROM_PIPE1ATRE */
     71/*(Sample) value = USB20_FROM_PIPE1ATRE[ channel ][ index ]->PIPE1TRE; */
     72#define USB20_FROM_PIPE1ATRE_COUNT  (5)
     73#define USB20_FROM_PIPE1ATRE_ADDRESS_LIST \
     74{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     75{ \
     76    &USB200_FROM_PIPE1TRE, &USB200_FROM_PIPE2TRE, &USB200_FROM_PIPE3TRE, &USB200_FROM_PIPE4TRE, &USB200_FROM_PIPE5TRE },{ \
     77    &USB201_FROM_PIPE1TRE, &USB201_FROM_PIPE2TRE, &USB201_FROM_PIPE3TRE, &USB201_FROM_PIPE4TRE, &USB201_FROM_PIPE5TRE \
     78} \
     79}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     80#define USB200_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE1TRE) /* USB200_FROM_PIPE1TRE */
     81#define USB200_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE2TRE) /* USB200_FROM_PIPE2TRE */
     82#define USB200_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE3TRE) /* USB200_FROM_PIPE3TRE */
     83#define USB200_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE4TRE) /* USB200_FROM_PIPE4TRE */
     84#define USB200_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE5TRE) /* USB200_FROM_PIPE5TRE */
     85#define USB201_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE1TRE) /* USB201_FROM_PIPE1TRE */
     86#define USB201_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE2TRE) /* USB201_FROM_PIPE2TRE */
     87#define USB201_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE3TRE) /* USB201_FROM_PIPE3TRE */
     88#define USB201_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE4TRE) /* USB201_FROM_PIPE4TRE */
     89#define USB201_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE5TRE) /* USB201_FROM_PIPE5TRE */
     90
     91
     92
     93
     94/* Channel array defines of USB20_FROM_D0FIFOSEL */
     95/*(Sample) value = USB20_FROM_D0FIFOSEL[ channel ][ index ]->D0FIFOSEL; */
     96#define USB20_FROM_D0FIFOSEL_COUNT  (2)
     97#define USB20_FROM_D0FIFOSEL_ADDRESS_LIST \
     98{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     99{ \
     100    &USB200_FROM_D0FIFOSEL, &USB200_FROM_D1FIFOSEL },{ \
     101    &USB201_FROM_D0FIFOSEL, &USB201_FROM_D1FIFOSEL \
     102} \
     103}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     104#define USB200_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D0FIFOSEL) /* USB200_FROM_D0FIFOSEL */
     105#define USB200_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D1FIFOSEL) /* USB200_FROM_D1FIFOSEL */
     106#define USB201_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D0FIFOSEL) /* USB201_FROM_D0FIFOSEL */
     107#define USB201_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D1FIFOSEL) /* USB201_FROM_D1FIFOSEL */
     108
     109
     110/* End of channel array defines of USB20 */
     111
     112
     113#define SYSCFG0_0 (USB200.SYSCFG0)
     114#define BUSWAIT_0 (USB200.BUSWAIT)
     115#define SYSSTS0_0 (USB200.SYSSTS0)
     116#define DVSTCTR0_0 (USB200.DVSTCTR0)
     117#define TESTMODE_0 (USB200.TESTMODE)
     118#define D0FBCFG_0 (USB200.D0FBCFG)
     119#define D1FBCFG_0 (USB200.D1FBCFG)
     120#define CFIFO_0   (USB200.CFIFO.UINT32)
     121#define CFIFO_0L  (USB200.CFIFO.UINT16[R_IO_L])
     122#define CFIFO_0H  (USB200.CFIFO.UINT16[R_IO_H])
     123#define CFIFO_0LL (USB200.CFIFO.UINT8[R_IO_LL])
     124#define CFIFO_0LH (USB200.CFIFO.UINT8[R_IO_LH])
     125#define CFIFO_0HL (USB200.CFIFO.UINT8[R_IO_HL])
     126#define CFIFO_0HH (USB200.CFIFO.UINT8[R_IO_HH])
     127#define D0FIFO_0   (USB200.D0FIFO.UINT32)
     128#define D0FIFO_0L  (USB200.D0FIFO.UINT16[R_IO_L])
     129#define D0FIFO_0H  (USB200.D0FIFO.UINT16[R_IO_H])
     130#define D0FIFO_0LL (USB200.D0FIFO.UINT8[R_IO_LL])
     131#define D0FIFO_0LH (USB200.D0FIFO.UINT8[R_IO_LH])
     132#define D0FIFO_0HL (USB200.D0FIFO.UINT8[R_IO_HL])
     133#define D0FIFO_0HH (USB200.D0FIFO.UINT8[R_IO_HH])
     134#define D1FIFO_0   (USB200.D1FIFO.UINT32)
     135#define D1FIFO_0L  (USB200.D1FIFO.UINT16[R_IO_L])
     136#define D1FIFO_0H  (USB200.D1FIFO.UINT16[R_IO_H])
     137#define D1FIFO_0LL (USB200.D1FIFO.UINT8[R_IO_LL])
     138#define D1FIFO_0LH (USB200.D1FIFO.UINT8[R_IO_LH])
     139#define D1FIFO_0HL (USB200.D1FIFO.UINT8[R_IO_HL])
     140#define D1FIFO_0HH (USB200.D1FIFO.UINT8[R_IO_HH])
     141#define CFIFOSEL_0 (USB200.CFIFOSEL)
     142#define CFIFOCTR_0 (USB200.CFIFOCTR)
     143#define D0FIFOSEL_0 (USB200.D0FIFOSEL)
     144#define D0FIFOCTR_0 (USB200.D0FIFOCTR)
     145#define D1FIFOSEL_0 (USB200.D1FIFOSEL)
     146#define D1FIFOCTR_0 (USB200.D1FIFOCTR)
     147#define INTENB0_0 (USB200.INTENB0)
     148#define INTENB1_0 (USB200.INTENB1)
     149#define BRDYENB_0 (USB200.BRDYENB)
     150#define NRDYENB_0 (USB200.NRDYENB)
     151#define BEMPENB_0 (USB200.BEMPENB)
     152#define SOFCFG_0 (USB200.SOFCFG)
     153#define INTSTS0_0 (USB200.INTSTS0)
     154#define INTSTS1_0 (USB200.INTSTS1)
     155#define BRDYSTS_0 (USB200.BRDYSTS)
     156#define NRDYSTS_0 (USB200.NRDYSTS)
     157#define BEMPSTS_0 (USB200.BEMPSTS)
     158#define FRMNUM_0 (USB200.FRMNUM)
     159#define UFRMNUM_0 (USB200.UFRMNUM)
     160#define USBADDR_0 (USB200.USBADDR)
     161#define USBREQ_0 (USB200.USBREQ)
     162#define USBVAL_0 (USB200.USBVAL)
     163#define USBINDX_0 (USB200.USBINDX)
     164#define USBLENG_0 (USB200.USBLENG)
     165#define DCPCFG_0 (USB200.DCPCFG)
     166#define DCPMAXP_0 (USB200.DCPMAXP)
     167#define DCPCTR_0 (USB200.DCPCTR)
     168#define PIPESEL_0 (USB200.PIPESEL)
     169#define PIPECFG_0 (USB200.PIPECFG)
     170#define PIPEBUF_0 (USB200.PIPEBUF)
     171#define PIPEMAXP_0 (USB200.PIPEMAXP)
     172#define PIPEPERI_0 (USB200.PIPEPERI)
     173#define PIPE1CTR_0 (USB200.PIPE1CTR)
     174#define PIPE2CTR_0 (USB200.PIPE2CTR)
     175#define PIPE3CTR_0 (USB200.PIPE3CTR)
     176#define PIPE4CTR_0 (USB200.PIPE4CTR)
     177#define PIPE5CTR_0 (USB200.PIPE5CTR)
     178#define PIPE6CTR_0 (USB200.PIPE6CTR)
     179#define PIPE7CTR_0 (USB200.PIPE7CTR)
     180#define PIPE8CTR_0 (USB200.PIPE8CTR)
     181#define PIPE9CTR_0 (USB200.PIPE9CTR)
     182#define PIPEACTR_0 (USB200.PIPEACTR)
     183#define PIPEBCTR_0 (USB200.PIPEBCTR)
     184#define PIPECCTR_0 (USB200.PIPECCTR)
     185#define PIPEDCTR_0 (USB200.PIPEDCTR)
     186#define PIPEECTR_0 (USB200.PIPEECTR)
     187#define PIPEFCTR_0 (USB200.PIPEFCTR)
     188#define PIPE1TRE_0 (USB200.PIPE1TRE)
     189#define PIPE1TRN_0 (USB200.PIPE1TRN)
     190#define PIPE2TRE_0 (USB200.PIPE2TRE)
     191#define PIPE2TRN_0 (USB200.PIPE2TRN)
     192#define PIPE3TRE_0 (USB200.PIPE3TRE)
     193#define PIPE3TRN_0 (USB200.PIPE3TRN)
     194#define PIPE4TRE_0 (USB200.PIPE4TRE)
     195#define PIPE4TRN_0 (USB200.PIPE4TRN)
     196#define PIPE5TRE_0 (USB200.PIPE5TRE)
     197#define PIPE5TRN_0 (USB200.PIPE5TRN)
     198#define PIPEBTRE_0 (USB200.PIPEBTRE)
     199#define PIPEBTRN_0 (USB200.PIPEBTRN)
     200#define PIPECTRE_0 (USB200.PIPECTRE)
     201#define PIPECTRN_0 (USB200.PIPECTRN)
     202#define PIPEDTRE_0 (USB200.PIPEDTRE)
     203#define PIPEDTRN_0 (USB200.PIPEDTRN)
     204#define PIPEETRE_0 (USB200.PIPEETRE)
     205#define PIPEETRN_0 (USB200.PIPEETRN)
     206#define PIPEFTRE_0 (USB200.PIPEFTRE)
     207#define PIPEFTRN_0 (USB200.PIPEFTRN)
     208#define PIPE9TRE_0 (USB200.PIPE9TRE)
     209#define PIPE9TRN_0 (USB200.PIPE9TRN)
     210#define PIPEATRE_0 (USB200.PIPEATRE)
     211#define PIPEATRN_0 (USB200.PIPEATRN)
     212#define DEVADD0_0 (USB200.DEVADD0)
     213#define DEVADD1_0 (USB200.DEVADD1)
     214#define DEVADD2_0 (USB200.DEVADD2)
     215#define DEVADD3_0 (USB200.DEVADD3)
     216#define DEVADD4_0 (USB200.DEVADD4)
     217#define DEVADD5_0 (USB200.DEVADD5)
     218#define DEVADD6_0 (USB200.DEVADD6)
     219#define DEVADD7_0 (USB200.DEVADD7)
     220#define DEVADD8_0 (USB200.DEVADD8)
     221#define DEVADD9_0 (USB200.DEVADD9)
     222#define DEVADDA_0 (USB200.DEVADDA)
     223#define SUSPMODE_0 (USB200.SUSPMODE)
     224#define D0FIFOB0_0 (USB200.D0FIFOB0)
     225#define D0FIFOB1_0 (USB200.D0FIFOB1)
     226#define D0FIFOB2_0 (USB200.D0FIFOB2)
     227#define D0FIFOB3_0 (USB200.D0FIFOB3)
     228#define D0FIFOB4_0 (USB200.D0FIFOB4)
     229#define D0FIFOB5_0 (USB200.D0FIFOB5)
     230#define D0FIFOB6_0 (USB200.D0FIFOB6)
     231#define D0FIFOB7_0 (USB200.D0FIFOB7)
     232#define D1FIFOB0_0 (USB200.D1FIFOB0)
     233#define D1FIFOB1_0 (USB200.D1FIFOB1)
     234#define D1FIFOB2_0 (USB200.D1FIFOB2)
     235#define D1FIFOB3_0 (USB200.D1FIFOB3)
     236#define D1FIFOB4_0 (USB200.D1FIFOB4)
     237#define D1FIFOB5_0 (USB200.D1FIFOB5)
     238#define D1FIFOB6_0 (USB200.D1FIFOB6)
     239#define D1FIFOB7_0 (USB200.D1FIFOB7)
     240#define SYSCFG0_1 (USB201.SYSCFG0)
     241#define BUSWAIT_1 (USB201.BUSWAIT)
     242#define SYSSTS0_1 (USB201.SYSSTS0)
     243#define DVSTCTR0_1 (USB201.DVSTCTR0)
     244#define TESTMODE_1 (USB201.TESTMODE)
     245#define D0FBCFG_1 (USB201.D0FBCFG)
     246#define D1FBCFG_1 (USB201.D1FBCFG)
     247#define CFIFO_1   (USB201.CFIFO.UINT32)
     248#define CFIFO_1L  (USB201.CFIFO.UINT16[R_IO_L])
     249#define CFIFO_1H  (USB201.CFIFO.UINT16[R_IO_H])
     250#define CFIFO_1LL (USB201.CFIFO.UINT8[R_IO_LL])
     251#define CFIFO_1LH (USB201.CFIFO.UINT8[R_IO_LH])
     252#define CFIFO_1HL (USB201.CFIFO.UINT8[R_IO_HL])
     253#define CFIFO_1HH (USB201.CFIFO.UINT8[R_IO_HH])
     254#define D0FIFO_1   (USB201.D0FIFO.UINT32)
     255#define D0FIFO_1L  (USB201.D0FIFO.UINT16[R_IO_L])
     256#define D0FIFO_1H  (USB201.D0FIFO.UINT16[R_IO_H])
     257#define D0FIFO_1LL (USB201.D0FIFO.UINT8[R_IO_LL])
     258#define D0FIFO_1LH (USB201.D0FIFO.UINT8[R_IO_LH])
     259#define D0FIFO_1HL (USB201.D0FIFO.UINT8[R_IO_HL])
     260#define D0FIFO_1HH (USB201.D0FIFO.UINT8[R_IO_HH])
     261#define D1FIFO_1   (USB201.D1FIFO.UINT32)
     262#define D1FIFO_1L  (USB201.D1FIFO.UINT16[R_IO_L])
     263#define D1FIFO_1H  (USB201.D1FIFO.UINT16[R_IO_H])
     264#define D1FIFO_1LL (USB201.D1FIFO.UINT8[R_IO_LL])
     265#define D1FIFO_1LH (USB201.D1FIFO.UINT8[R_IO_LH])
     266#define D1FIFO_1HL (USB201.D1FIFO.UINT8[R_IO_HL])
     267#define D1FIFO_1HH (USB201.D1FIFO.UINT8[R_IO_HH])
     268#define CFIFOSEL_1 (USB201.CFIFOSEL)
     269#define CFIFOCTR_1 (USB201.CFIFOCTR)
     270#define D0FIFOSEL_1 (USB201.D0FIFOSEL)
     271#define D0FIFOCTR_1 (USB201.D0FIFOCTR)
     272#define D1FIFOSEL_1 (USB201.D1FIFOSEL)
     273#define D1FIFOCTR_1 (USB201.D1FIFOCTR)
     274#define INTENB0_1 (USB201.INTENB0)
     275#define INTENB1_1 (USB201.INTENB1)
     276#define BRDYENB_1 (USB201.BRDYENB)
     277#define NRDYENB_1 (USB201.NRDYENB)
     278#define BEMPENB_1 (USB201.BEMPENB)
     279#define SOFCFG_1 (USB201.SOFCFG)
     280#define INTSTS0_1 (USB201.INTSTS0)
     281#define INTSTS1_1 (USB201.INTSTS1)
     282#define BRDYSTS_1 (USB201.BRDYSTS)
     283#define NRDYSTS_1 (USB201.NRDYSTS)
     284#define BEMPSTS_1 (USB201.BEMPSTS)
     285#define FRMNUM_1 (USB201.FRMNUM)
     286#define UFRMNUM_1 (USB201.UFRMNUM)
     287#define USBADDR_1 (USB201.USBADDR)
     288#define USBREQ_1 (USB201.USBREQ)
     289#define USBVAL_1 (USB201.USBVAL)
     290#define USBINDX_1 (USB201.USBINDX)
     291#define USBLENG_1 (USB201.USBLENG)
     292#define DCPCFG_1 (USB201.DCPCFG)
     293#define DCPMAXP_1 (USB201.DCPMAXP)
     294#define DCPCTR_1 (USB201.DCPCTR)
     295#define PIPESEL_1 (USB201.PIPESEL)
     296#define PIPECFG_1 (USB201.PIPECFG)
     297#define PIPEBUF_1 (USB201.PIPEBUF)
     298#define PIPEMAXP_1 (USB201.PIPEMAXP)
     299#define PIPEPERI_1 (USB201.PIPEPERI)
     300#define PIPE1CTR_1 (USB201.PIPE1CTR)
     301#define PIPE2CTR_1 (USB201.PIPE2CTR)
     302#define PIPE3CTR_1 (USB201.PIPE3CTR)
     303#define PIPE4CTR_1 (USB201.PIPE4CTR)
     304#define PIPE5CTR_1 (USB201.PIPE5CTR)
     305#define PIPE6CTR_1 (USB201.PIPE6CTR)
     306#define PIPE7CTR_1 (USB201.PIPE7CTR)
     307#define PIPE8CTR_1 (USB201.PIPE8CTR)
     308#define PIPE9CTR_1 (USB201.PIPE9CTR)
     309#define PIPEACTR_1 (USB201.PIPEACTR)
     310#define PIPEBCTR_1 (USB201.PIPEBCTR)
     311#define PIPECCTR_1 (USB201.PIPECCTR)
     312#define PIPEDCTR_1 (USB201.PIPEDCTR)
     313#define PIPEECTR_1 (USB201.PIPEECTR)
     314#define PIPEFCTR_1 (USB201.PIPEFCTR)
     315#define PIPE1TRE_1 (USB201.PIPE1TRE)
     316#define PIPE1TRN_1 (USB201.PIPE1TRN)
     317#define PIPE2TRE_1 (USB201.PIPE2TRE)
     318#define PIPE2TRN_1 (USB201.PIPE2TRN)
     319#define PIPE3TRE_1 (USB201.PIPE3TRE)
     320#define PIPE3TRN_1 (USB201.PIPE3TRN)
     321#define PIPE4TRE_1 (USB201.PIPE4TRE)
     322#define PIPE4TRN_1 (USB201.PIPE4TRN)
     323#define PIPE5TRE_1 (USB201.PIPE5TRE)
     324#define PIPE5TRN_1 (USB201.PIPE5TRN)
     325#define PIPEBTRE_1 (USB201.PIPEBTRE)
     326#define PIPEBTRN_1 (USB201.PIPEBTRN)
     327#define PIPECTRE_1 (USB201.PIPECTRE)
     328#define PIPECTRN_1 (USB201.PIPECTRN)
     329#define PIPEDTRE_1 (USB201.PIPEDTRE)
     330#define PIPEDTRN_1 (USB201.PIPEDTRN)
     331#define PIPEETRE_1 (USB201.PIPEETRE)
     332#define PIPEETRN_1 (USB201.PIPEETRN)
     333#define PIPEFTRE_1 (USB201.PIPEFTRE)
     334#define PIPEFTRN_1 (USB201.PIPEFTRN)
     335#define PIPE9TRE_1 (USB201.PIPE9TRE)
     336#define PIPE9TRN_1 (USB201.PIPE9TRN)
     337#define PIPEATRE_1 (USB201.PIPEATRE)
     338#define PIPEATRN_1 (USB201.PIPEATRN)
     339#define DEVADD0_1 (USB201.DEVADD0)
     340#define DEVADD1_1 (USB201.DEVADD1)
     341#define DEVADD2_1 (USB201.DEVADD2)
     342#define DEVADD3_1 (USB201.DEVADD3)
     343#define DEVADD4_1 (USB201.DEVADD4)
     344#define DEVADD5_1 (USB201.DEVADD5)
     345#define DEVADD6_1 (USB201.DEVADD6)
     346#define DEVADD7_1 (USB201.DEVADD7)
     347#define DEVADD8_1 (USB201.DEVADD8)
     348#define DEVADD9_1 (USB201.DEVADD9)
     349#define DEVADDA_1 (USB201.DEVADDA)
     350#define SUSPMODE_1 (USB201.SUSPMODE)
     351#define D0FIFOB0_1 (USB201.D0FIFOB0)
     352#define D0FIFOB1_1 (USB201.D0FIFOB1)
     353#define D0FIFOB2_1 (USB201.D0FIFOB2)
     354#define D0FIFOB3_1 (USB201.D0FIFOB3)
     355#define D0FIFOB4_1 (USB201.D0FIFOB4)
     356#define D0FIFOB5_1 (USB201.D0FIFOB5)
     357#define D0FIFOB6_1 (USB201.D0FIFOB6)
     358#define D0FIFOB7_1 (USB201.D0FIFOB7)
     359#define D1FIFOB0_1 (USB201.D1FIFOB0)
     360#define D1FIFOB1_1 (USB201.D1FIFOB1)
     361#define D1FIFOB2_1 (USB201.D1FIFOB2)
     362#define D1FIFOB3_1 (USB201.D1FIFOB3)
     363#define D1FIFOB4_1 (USB201.D1FIFOB4)
     364#define D1FIFOB5_1 (USB201.D1FIFOB5)
     365#define D1FIFOB6_1 (USB201.D1FIFOB6)
     366#define D1FIFOB7_1 (USB201.D1FIFOB7)
     367
     368#define USB20_D0FBCFG_COUNT (2)
     369#define USB20_D0FIFO_COUNT (2)
     370#define USB20_INTENB0_COUNT (2)
     371#define USB20_INTSTS0_COUNT (2)
     372#define USB20_PIPE1CTR_COUNT (0xF)
     373#define USB20_DEVADD0_COUNT (0xB)
     374#define USB20_D0FIFOB0_COUNT (0x8)
     375
     376
     377typedef struct st_usb20
     378{
     379                                                           /* USB20            */
    35380    volatile uint16_t SYSCFG0;                                /*  SYSCFG0         */
    36381    volatile uint16_t BUSWAIT;                                /*  BUSWAIT         */
    … …  
    41386    volatile uint16_t TESTMODE;                               /*  TESTMODE        */
    42387    volatile uint8_t   dummy3[2];                              /*                  */
    43 #define USB20_D0FBCFG_COUNT 2
     388
     389/* #define USB20_D0FBCFG_COUNT (2) */
    44390    volatile uint16_t D0FBCFG;                                /*  D0FBCFG         */
    45391    volatile uint16_t D1FBCFG;                                /*  D1FBCFG         */
    46392    union iodefine_reg32_t  CFIFO;                         /*  CFIFO           */
    47 #define USB20_D0FIFO_COUNT 2
     393
     394/* #define USB20_D0FIFO_COUNT (2) */
    48395    union iodefine_reg32_t  D0FIFO;                        /*  D0FIFO          */
    49396    union iodefine_reg32_t  D1FIFO;                        /*  D1FIFO          */
    … …  
    52399    volatile uint16_t CFIFOCTR;                               /*  CFIFOCTR        */
    53400    volatile uint8_t   dummy4[4];                              /*                  */
     401
    54402/* start of struct st_usb20_from_d0fifosel */
    55403    volatile uint16_t D0FIFOSEL;                              /*  D0FIFOSEL       */
    56404    volatile uint16_t D0FIFOCTR;                              /*  D0FIFOCTR       */
     405
    57406/* end of struct st_usb20_from_d0fifosel */
     407
    58408/* start of struct st_usb20_from_d0fifosel */
    59409    volatile uint16_t D1FIFOSEL;                              /*  D1FIFOSEL       */
    60410    volatile uint16_t D1FIFOCTR;                              /*  D1FIFOCTR       */
     411
    61412/* end of struct st_usb20_from_d0fifosel */
    62 #define USB20_INTENB0_COUNT 2
     413
     414/* #define USB20_INTENB0_COUNT (2) */
    63415    volatile uint16_t INTENB0;                                /*  INTENB0         */
    64416    volatile uint16_t INTENB1;                                /*  INTENB1         */
    … …  
    69421    volatile uint16_t SOFCFG;                                 /*  SOFCFG          */
    70422    volatile uint8_t   dummy6[2];                              /*                  */
    71 #define USB20_INTSTS0_COUNT 2
     423
     424/* #define USB20_INTSTS0_COUNT (2) */
    72425    volatile uint16_t INTSTS0;                                /*  INTSTS0         */
    73426    volatile uint16_t INTSTS1;                                /*  INTSTS1         */
    … …  
    94447    volatile uint16_t PIPEMAXP;                               /*  PIPEMAXP        */
    95448    volatile uint16_t PIPEPERI;                               /*  PIPEPERI        */
    96 #define USB20_PIPE1CTR_COUNT 0xF
     449
     450/* #define USB20_PIPE1CTR_COUNT (0xF) */
    97451    volatile uint16_t PIPE1CTR;                               /*  PIPE1CTR        */
    98452    volatile uint16_t PIPE2CTR;                               /*  PIPE2CTR        */
    … …  
    111465    volatile uint16_t PIPEFCTR;                               /*  PIPEFCTR        */
    112466    volatile uint8_t   dummy11[2];                             /*                  */
     467
    113468/* start of struct st_usb20_from_pipe1tre */
    114469    volatile uint16_t PIPE1TRE;                               /*  PIPE1TRE        */
    115470    volatile uint16_t PIPE1TRN;                               /*  PIPE1TRN        */
     471
    116472/* end of struct st_usb20_from_pipe1tre */
     473
    117474/* start of struct st_usb20_from_pipe1tre */
    118475    volatile uint16_t PIPE2TRE;                               /*  PIPE2TRE        */
    119476    volatile uint16_t PIPE2TRN;                               /*  PIPE2TRN        */
     477
    120478/* end of struct st_usb20_from_pipe1tre */
     479
    121480/* start of struct st_usb20_from_pipe1tre */
    122481    volatile uint16_t PIPE3TRE;                               /*  PIPE3TRE        */
    123482    volatile uint16_t PIPE3TRN;                               /*  PIPE3TRN        */
     483
    124484/* end of struct st_usb20_from_pipe1tre */
     485
    125486/* start of struct st_usb20_from_pipe1tre */
    126487    volatile uint16_t PIPE4TRE;                               /*  PIPE4TRE        */
    127488    volatile uint16_t PIPE4TRN;                               /*  PIPE4TRN        */
     489
    128490/* end of struct st_usb20_from_pipe1tre */
     491
    129492/* start of struct st_usb20_from_pipe1tre */
    130493    volatile uint16_t PIPE5TRE;                               /*  PIPE5TRE        */
    131494    volatile uint16_t PIPE5TRN;                               /*  PIPE5TRN        */
     495
    132496/* end of struct st_usb20_from_pipe1tre */
    133497    volatile uint16_t PIPEBTRE;                               /*  PIPEBTRE        */
    … …  
    146510    volatile uint16_t PIPEATRN;                               /*  PIPEATRN        */
    147511    volatile uint8_t   dummy12[16];                            /*                  */
    148 #define USB20_DEVADD0_COUNT 0xB
     512
     513/* #define USB20_DEVADD0_COUNT (0xB) */
    149514    volatile uint16_t DEVADD0;                                /*  DEVADD0         */
    150515    volatile uint16_t DEVADD1;                                /*  DEVADD1         */
    … …  
    161526    volatile uint16_t SUSPMODE;                               /*  SUSPMODE        */
    162527    volatile uint8_t   dummy14[92];                            /*                  */
     528
    163529/* start of struct st_usb20_from_dmfifob0 */
    164530    volatile uint32_t  D0FIFOB0;                               /*  D0FIFOB0        */
    … …  
    170536    volatile uint32_t  D0FIFOB6;                               /*  D0FIFOB6        */
    171537    volatile uint32_t  D0FIFOB7;                               /*  D0FIFOB7        */
     538
    172539/* end of struct st_usb20_from_dmfifob0 */
     540
    173541/* start of struct st_usb20_from_dmfifob0 */
    174542    volatile uint32_t  D1FIFOB0;                               /*  D1FIFOB0        */
    … …  
    180548    volatile uint32_t  D1FIFOB6;                               /*  D1FIFOB6        */
    181549    volatile uint32_t  D1FIFOB7;                               /*  D1FIFOB7        */
     550
    182551/* end of struct st_usb20_from_dmfifob0 */
    183 };
    184 
    185 
    186 struct st_usb20_from_d0fifosel
     552} r_io_usb20_t;
     553
     554
     555typedef struct st_usb20_from_d0fifosel
    187556{
     557 
    188558    volatile uint16_t D0FIFOSEL;                              /*  D0FIFOSEL       */
    189559    volatile uint16_t D0FIFOCTR;                              /*  D0FIFOCTR       */
    190 };
    191 
    192 
    193 struct st_usb20_from_pipe1tre
     560} r_io_usb20_from_d0fifosel_t;
     561
     562
     563typedef struct st_usb20_from_pipe1tre
    194564{
     565 
    195566    volatile uint16_t PIPE1TRE;                               /*  PIPE1TRE        */
    196567    volatile uint16_t PIPE1TRN;                               /*  PIPE1TRN        */
    197 };
    198 
    199 
    200 struct st_usb20_from_dmfifob0
     568} r_io_usb20_from_pipe1tre_t;
     569
     570
     571typedef struct st_usb20_from_dmfifob0
    201572{
    202 #define USB20_D0FIFOB0_COUNT 0x8
     573 
     574
     575/* #define USB20_D0FIFOB0_COUNT (0x8) */
    203576    volatile uint32_t  D0FIFOB0;                               /*  D0FIFOB0        */
    204577    volatile uint32_t  D0FIFOB1;                               /*  D0FIFOB1        */
    … …  
    209582    volatile uint32_t  D0FIFOB6;                               /*  D0FIFOB6        */
    210583    volatile uint32_t  D0FIFOB7;                               /*  D0FIFOB7        */
    211 };
    212 
    213 
    214 #define USB200  (*(struct st_usb20   *)0xE8010000uL) /* USB200 */
    215 #define USB201  (*(struct st_usb20   *)0xE8207000uL) /* USB201 */
    216 
    217 
    218 /* Start of channnel array defines of USB20 */
    219 
    220 /* Channnel array defines of USB20 */
    221 /*(Sample) value = USB20[ channel ]->SYSCFG0; */
    222 #define USB20_COUNT  2
    223 #define USB20_ADDRESS_LIST \
    224 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    225     &USB200, &USB201 \
    226 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    227 
    228 
    229 
    230 /* Channnel array defines of USB20_FROM_D0FIFOB0 */
    231 /*(Sample) value = USB20_FROM_D0FIFOB0[ channel ][ index ]->D0FIFOB0; */
    232 #define USB20_FROM_D0FIFOB0_COUNT  2
    233 #define USB20_FROM_D0FIFOB0_ADDRESS_LIST \
    234 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    235 { \
    236     &USB200_FROM_D0FIFOB0, &USB200_FROM_D1FIFOB0 },{ \
    237     &USB201_FROM_D0FIFOB0, &USB201_FROM_D1FIFOB0 \
    238 } \
    239 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    240 #define USB200_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D0FIFOB0) /* USB200_FROM_D0FIFOB0 */
    241 #define USB200_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D1FIFOB0) /* USB200_FROM_D1FIFOB0 */
    242 #define USB201_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D0FIFOB0) /* USB201_FROM_D0FIFOB0 */
    243 #define USB201_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D1FIFOB0) /* USB201_FROM_D1FIFOB0 */
    244 
    245 
    246 
    247 
    248 /* Channnel array defines of USB20_FROM_PIPE1ATRE */
    249 /*(Sample) value = USB20_FROM_PIPE1ATRE[ channel ][ index ]->PIPE1TRE; */
    250 #define USB20_FROM_PIPE1ATRE_COUNT  5
    251 #define USB20_FROM_PIPE1ATRE_ADDRESS_LIST \
    252 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    253 { \
    254     &USB200_FROM_PIPE1TRE, &USB200_FROM_PIPE2TRE, &USB200_FROM_PIPE3TRE, &USB200_FROM_PIPE4TRE, &USB200_FROM_PIPE5TRE },{ \
    255     &USB201_FROM_PIPE1TRE, &USB201_FROM_PIPE2TRE, &USB201_FROM_PIPE3TRE, &USB201_FROM_PIPE4TRE, &USB201_FROM_PIPE5TRE \
    256 } \
    257 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    258 #define USB200_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE1TRE) /* USB200_FROM_PIPE1TRE */
    259 #define USB200_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE2TRE) /* USB200_FROM_PIPE2TRE */
    260 #define USB200_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE3TRE) /* USB200_FROM_PIPE3TRE */
    261 #define USB200_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE4TRE) /* USB200_FROM_PIPE4TRE */
    262 #define USB200_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE5TRE) /* USB200_FROM_PIPE5TRE */
    263 #define USB201_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE1TRE) /* USB201_FROM_PIPE1TRE */
    264 #define USB201_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE2TRE) /* USB201_FROM_PIPE2TRE */
    265 #define USB201_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE3TRE) /* USB201_FROM_PIPE3TRE */
    266 #define USB201_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE4TRE) /* USB201_FROM_PIPE4TRE */
    267 #define USB201_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE5TRE) /* USB201_FROM_PIPE5TRE */
    268 
    269 
    270 
    271 
    272 /* Channnel array defines of USB20_FROM_D0FIFOSEL */
    273 /*(Sample) value = USB20_FROM_D0FIFOSEL[ channel ][ index ]->D0FIFOSEL; */
    274 #define USB20_FROM_D0FIFOSEL_COUNT  2
    275 #define USB20_FROM_D0FIFOSEL_ADDRESS_LIST \
    276 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    277 { \
    278     &USB200_FROM_D0FIFOSEL, &USB200_FROM_D1FIFOSEL },{ \
    279     &USB201_FROM_D0FIFOSEL, &USB201_FROM_D1FIFOSEL \
    280 } \
    281 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    282 #define USB200_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D0FIFOSEL) /* USB200_FROM_D0FIFOSEL */
    283 #define USB200_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D1FIFOSEL) /* USB200_FROM_D1FIFOSEL */
    284 #define USB201_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D0FIFOSEL) /* USB201_FROM_D0FIFOSEL */
    285 #define USB201_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D1FIFOSEL) /* USB201_FROM_D1FIFOSEL */
    286 
    287 
    288 /* End of channnel array defines of USB20 */
    289 
    290 
    291 #define SYSCFG0_0 USB200.SYSCFG0
    292 #define BUSWAIT_0 USB200.BUSWAIT
    293 #define SYSSTS0_0 USB200.SYSSTS0
    294 #define DVSTCTR0_0 USB200.DVSTCTR0
    295 #define TESTMODE_0 USB200.TESTMODE
    296 #define D0FBCFG_0 USB200.D0FBCFG
    297 #define D1FBCFG_0 USB200.D1FBCFG
    298 #define CFIFO_0   USB200.CFIFO.UINT32
    299 #define CFIFO_0L  USB200.CFIFO.UINT16[L]
    300 #define CFIFO_0H  USB200.CFIFO.UINT16[H]
    301 #define CFIFO_0LL USB200.CFIFO.UINT8[LL]
    302 #define CFIFO_0LH USB200.CFIFO.UINT8[LH]
    303 #define CFIFO_0HL USB200.CFIFO.UINT8[HL]
    304 #define CFIFO_0HH USB200.CFIFO.UINT8[HH]
    305 #define D0FIFO_0   USB200.D0FIFO.UINT32
    306 #define D0FIFO_0L  USB200.D0FIFO.UINT16[L]
    307 #define D0FIFO_0H  USB200.D0FIFO.UINT16[H]
    308 #define D0FIFO_0LL USB200.D0FIFO.UINT8[LL]
    309 #define D0FIFO_0LH USB200.D0FIFO.UINT8[LH]
    310 #define D0FIFO_0HL USB200.D0FIFO.UINT8[HL]
    311 #define D0FIFO_0HH USB200.D0FIFO.UINT8[HH]
    312 #define D1FIFO_0   USB200.D1FIFO.UINT32
    313 #define D1FIFO_0L  USB200.D1FIFO.UINT16[L]
    314 #define D1FIFO_0H  USB200.D1FIFO.UINT16[H]
    315 #define D1FIFO_0LL USB200.D1FIFO.UINT8[LL]
    316 #define D1FIFO_0LH USB200.D1FIFO.UINT8[LH]
    317 #define D1FIFO_0HL USB200.D1FIFO.UINT8[HL]
    318 #define D1FIFO_0HH USB200.D1FIFO.UINT8[HH]
    319 #define CFIFOSEL_0 USB200.CFIFOSEL
    320 #define CFIFOCTR_0 USB200.CFIFOCTR
    321 #define D0FIFOSEL_0 USB200.D0FIFOSEL
    322 #define D0FIFOCTR_0 USB200.D0FIFOCTR
    323 #define D1FIFOSEL_0 USB200.D1FIFOSEL
    324 #define D1FIFOCTR_0 USB200.D1FIFOCTR
    325 #define INTENB0_0 USB200.INTENB0
    326 #define INTENB1_0 USB200.INTENB1
    327 #define BRDYENB_0 USB200.BRDYENB
    328 #define NRDYENB_0 USB200.NRDYENB
    329 #define BEMPENB_0 USB200.BEMPENB
    330 #define SOFCFG_0 USB200.SOFCFG
    331 #define INTSTS0_0 USB200.INTSTS0
    332 #define INTSTS1_0 USB200.INTSTS1
    333 #define BRDYSTS_0 USB200.BRDYSTS
    334 #define NRDYSTS_0 USB200.NRDYSTS
    335 #define BEMPSTS_0 USB200.BEMPSTS
    336 #define FRMNUM_0 USB200.FRMNUM
    337 #define UFRMNUM_0 USB200.UFRMNUM
    338 #define USBADDR_0 USB200.USBADDR
    339 #define USBREQ_0 USB200.USBREQ
    340 #define USBVAL_0 USB200.USBVAL
    341 #define USBINDX_0 USB200.USBINDX
    342 #define USBLENG_0 USB200.USBLENG
    343 #define DCPCFG_0 USB200.DCPCFG
    344 #define DCPMAXP_0 USB200.DCPMAXP
    345 #define DCPCTR_0 USB200.DCPCTR
    346 #define PIPESEL_0 USB200.PIPESEL
    347 #define PIPECFG_0 USB200.PIPECFG
    348 #define PIPEBUF_0 USB200.PIPEBUF
    349 #define PIPEMAXP_0 USB200.PIPEMAXP
    350 #define PIPEPERI_0 USB200.PIPEPERI
    351 #define PIPE1CTR_0 USB200.PIPE1CTR
    352 #define PIPE2CTR_0 USB200.PIPE2CTR
    353 #define PIPE3CTR_0 USB200.PIPE3CTR
    354 #define PIPE4CTR_0 USB200.PIPE4CTR
    355 #define PIPE5CTR_0 USB200.PIPE5CTR
    356 #define PIPE6CTR_0 USB200.PIPE6CTR
    357 #define PIPE7CTR_0 USB200.PIPE7CTR
    358 #define PIPE8CTR_0 USB200.PIPE8CTR
    359 #define PIPE9CTR_0 USB200.PIPE9CTR
    360 #define PIPEACTR_0 USB200.PIPEACTR
    361 #define PIPEBCTR_0 USB200.PIPEBCTR
    362 #define PIPECCTR_0 USB200.PIPECCTR
    363 #define PIPEDCTR_0 USB200.PIPEDCTR
    364 #define PIPEECTR_0 USB200.PIPEECTR
    365 #define PIPEFCTR_0 USB200.PIPEFCTR
    366 #define PIPE1TRE_0 USB200.PIPE1TRE
    367 #define PIPE1TRN_0 USB200.PIPE1TRN
    368 #define PIPE2TRE_0 USB200.PIPE2TRE
    369 #define PIPE2TRN_0 USB200.PIPE2TRN
    370 #define PIPE3TRE_0 USB200.PIPE3TRE
    371 #define PIPE3TRN_0 USB200.PIPE3TRN
    372 #define PIPE4TRE_0 USB200.PIPE4TRE
    373 #define PIPE4TRN_0 USB200.PIPE4TRN
    374 #define PIPE5TRE_0 USB200.PIPE5TRE
    375 #define PIPE5TRN_0 USB200.PIPE5TRN
    376 #define PIPEBTRE_0 USB200.PIPEBTRE
    377 #define PIPEBTRN_0 USB200.PIPEBTRN
    378 #define PIPECTRE_0 USB200.PIPECTRE
    379 #define PIPECTRN_0 USB200.PIPECTRN
    380 #define PIPEDTRE_0 USB200.PIPEDTRE
    381 #define PIPEDTRN_0 USB200.PIPEDTRN
    382 #define PIPEETRE_0 USB200.PIPEETRE
    383 #define PIPEETRN_0 USB200.PIPEETRN
    384 #define PIPEFTRE_0 USB200.PIPEFTRE
    385 #define PIPEFTRN_0 USB200.PIPEFTRN
    386 #define PIPE9TRE_0 USB200.PIPE9TRE
    387 #define PIPE9TRN_0 USB200.PIPE9TRN
    388 #define PIPEATRE_0 USB200.PIPEATRE
    389 #define PIPEATRN_0 USB200.PIPEATRN
    390 #define DEVADD0_0 USB200.DEVADD0
    391 #define DEVADD1_0 USB200.DEVADD1
    392 #define DEVADD2_0 USB200.DEVADD2
    393 #define DEVADD3_0 USB200.DEVADD3
    394 #define DEVADD4_0 USB200.DEVADD4
    395 #define DEVADD5_0 USB200.DEVADD5
    396 #define DEVADD6_0 USB200.DEVADD6
    397 #define DEVADD7_0 USB200.DEVADD7
    398 #define DEVADD8_0 USB200.DEVADD8
    399 #define DEVADD9_0 USB200.DEVADD9
    400 #define DEVADDA_0 USB200.DEVADDA
    401 #define SUSPMODE_0 USB200.SUSPMODE
    402 #define D0FIFOB0_0 USB200.D0FIFOB0
    403 #define D0FIFOB1_0 USB200.D0FIFOB1
    404 #define D0FIFOB2_0 USB200.D0FIFOB2
    405 #define D0FIFOB3_0 USB200.D0FIFOB3
    406 #define D0FIFOB4_0 USB200.D0FIFOB4
    407 #define D0FIFOB5_0 USB200.D0FIFOB5
    408 #define D0FIFOB6_0 USB200.D0FIFOB6
    409 #define D0FIFOB7_0 USB200.D0FIFOB7
    410 #define D1FIFOB0_0 USB200.D1FIFOB0
    411 #define D1FIFOB1_0 USB200.D1FIFOB1
    412 #define D1FIFOB2_0 USB200.D1FIFOB2
    413 #define D1FIFOB3_0 USB200.D1FIFOB3
    414 #define D1FIFOB4_0 USB200.D1FIFOB4
    415 #define D1FIFOB5_0 USB200.D1FIFOB5
    416 #define D1FIFOB6_0 USB200.D1FIFOB6
    417 #define D1FIFOB7_0 USB200.D1FIFOB7
    418 #define SYSCFG0_1 USB201.SYSCFG0
    419 #define BUSWAIT_1 USB201.BUSWAIT
    420 #define SYSSTS0_1 USB201.SYSSTS0
    421 #define DVSTCTR0_1 USB201.DVSTCTR0
    422 #define TESTMODE_1 USB201.TESTMODE
    423 #define D0FBCFG_1 USB201.D0FBCFG
    424 #define D1FBCFG_1 USB201.D1FBCFG
    425 #define CFIFO_1   USB201.CFIFO.UINT32
    426 #define CFIFO_1L  USB201.CFIFO.UINT16[L]
    427 #define CFIFO_1H  USB201.CFIFO.UINT16[H]
    428 #define CFIFO_1LL USB201.CFIFO.UINT8[LL]
    429 #define CFIFO_1LH USB201.CFIFO.UINT8[LH]
    430 #define CFIFO_1HL USB201.CFIFO.UINT8[HL]
    431 #define CFIFO_1HH USB201.CFIFO.UINT8[HH]
    432 #define D0FIFO_1   USB201.D0FIFO.UINT32
    433 #define D0FIFO_1L  USB201.D0FIFO.UINT16[L]
    434 #define D0FIFO_1H  USB201.D0FIFO.UINT16[H]
    435 #define D0FIFO_1LL USB201.D0FIFO.UINT8[LL]
    436 #define D0FIFO_1LH USB201.D0FIFO.UINT8[LH]
    437 #define D0FIFO_1HL USB201.D0FIFO.UINT8[HL]
    438 #define D0FIFO_1HH USB201.D0FIFO.UINT8[HH]
    439 #define D1FIFO_1   USB201.D1FIFO.UINT32
    440 #define D1FIFO_1L  USB201.D1FIFO.UINT16[L]
    441 #define D1FIFO_1H  USB201.D1FIFO.UINT16[H]
    442 #define D1FIFO_1LL USB201.D1FIFO.UINT8[LL]
    443 #define D1FIFO_1LH USB201.D1FIFO.UINT8[LH]
    444 #define D1FIFO_1HL USB201.D1FIFO.UINT8[HL]
    445 #define D1FIFO_1HH USB201.D1FIFO.UINT8[HH]
    446 #define CFIFOSEL_1 USB201.CFIFOSEL
    447 #define CFIFOCTR_1 USB201.CFIFOCTR
    448 #define D0FIFOSEL_1 USB201.D0FIFOSEL
    449 #define D0FIFOCTR_1 USB201.D0FIFOCTR
    450 #define D1FIFOSEL_1 USB201.D1FIFOSEL
    451 #define D1FIFOCTR_1 USB201.D1FIFOCTR
    452 #define INTENB0_1 USB201.INTENB0
    453 #define INTENB1_1 USB201.INTENB1
    454 #define BRDYENB_1 USB201.BRDYENB
    455 #define NRDYENB_1 USB201.NRDYENB
    456 #define BEMPENB_1 USB201.BEMPENB
    457 #define SOFCFG_1 USB201.SOFCFG
    458 #define INTSTS0_1 USB201.INTSTS0
    459 #define INTSTS1_1 USB201.INTSTS1
    460 #define BRDYSTS_1 USB201.BRDYSTS
    461 #define NRDYSTS_1 USB201.NRDYSTS
    462 #define BEMPSTS_1 USB201.BEMPSTS
    463 #define FRMNUM_1 USB201.FRMNUM
    464 #define UFRMNUM_1 USB201.UFRMNUM
    465 #define USBADDR_1 USB201.USBADDR
    466 #define USBREQ_1 USB201.USBREQ
    467 #define USBVAL_1 USB201.USBVAL
    468 #define USBINDX_1 USB201.USBINDX
    469 #define USBLENG_1 USB201.USBLENG
    470 #define DCPCFG_1 USB201.DCPCFG
    471 #define DCPMAXP_1 USB201.DCPMAXP
    472 #define DCPCTR_1 USB201.DCPCTR
    473 #define PIPESEL_1 USB201.PIPESEL
    474 #define PIPECFG_1 USB201.PIPECFG
    475 #define PIPEBUF_1 USB201.PIPEBUF
    476 #define PIPEMAXP_1 USB201.PIPEMAXP
    477 #define PIPEPERI_1 USB201.PIPEPERI
    478 #define PIPE1CTR_1 USB201.PIPE1CTR
    479 #define PIPE2CTR_1 USB201.PIPE2CTR
    480 #define PIPE3CTR_1 USB201.PIPE3CTR
    481 #define PIPE4CTR_1 USB201.PIPE4CTR
    482 #define PIPE5CTR_1 USB201.PIPE5CTR
    483 #define PIPE6CTR_1 USB201.PIPE6CTR
    484 #define PIPE7CTR_1 USB201.PIPE7CTR
    485 #define PIPE8CTR_1 USB201.PIPE8CTR
    486 #define PIPE9CTR_1 USB201.PIPE9CTR
    487 #define PIPEACTR_1 USB201.PIPEACTR
    488 #define PIPEBCTR_1 USB201.PIPEBCTR
    489 #define PIPECCTR_1 USB201.PIPECCTR
    490 #define PIPEDCTR_1 USB201.PIPEDCTR
    491 #define PIPEECTR_1 USB201.PIPEECTR
    492 #define PIPEFCTR_1 USB201.PIPEFCTR
    493 #define PIPE1TRE_1 USB201.PIPE1TRE
    494 #define PIPE1TRN_1 USB201.PIPE1TRN
    495 #define PIPE2TRE_1 USB201.PIPE2TRE
    496 #define PIPE2TRN_1 USB201.PIPE2TRN
    497 #define PIPE3TRE_1 USB201.PIPE3TRE
    498 #define PIPE3TRN_1 USB201.PIPE3TRN
    499 #define PIPE4TRE_1 USB201.PIPE4TRE
    500 #define PIPE4TRN_1 USB201.PIPE4TRN
    501 #define PIPE5TRE_1 USB201.PIPE5TRE
    502 #define PIPE5TRN_1 USB201.PIPE5TRN
    503 #define PIPEBTRE_1 USB201.PIPEBTRE
    504 #define PIPEBTRN_1 USB201.PIPEBTRN
    505 #define PIPECTRE_1 USB201.PIPECTRE
    506 #define PIPECTRN_1 USB201.PIPECTRN
    507 #define PIPEDTRE_1 USB201.PIPEDTRE
    508 #define PIPEDTRN_1 USB201.PIPEDTRN
    509 #define PIPEETRE_1 USB201.PIPEETRE
    510 #define PIPEETRN_1 USB201.PIPEETRN
    511 #define PIPEFTRE_1 USB201.PIPEFTRE
    512 #define PIPEFTRN_1 USB201.PIPEFTRN
    513 #define PIPE9TRE_1 USB201.PIPE9TRE
    514 #define PIPE9TRN_1 USB201.PIPE9TRN
    515 #define PIPEATRE_1 USB201.PIPEATRE
    516 #define PIPEATRN_1 USB201.PIPEATRN
    517 #define DEVADD0_1 USB201.DEVADD0
    518 #define DEVADD1_1 USB201.DEVADD1
    519 #define DEVADD2_1 USB201.DEVADD2
    520 #define DEVADD3_1 USB201.DEVADD3
    521 #define DEVADD4_1 USB201.DEVADD4
    522 #define DEVADD5_1 USB201.DEVADD5
    523 #define DEVADD6_1 USB201.DEVADD6
    524 #define DEVADD7_1 USB201.DEVADD7
    525 #define DEVADD8_1 USB201.DEVADD8
    526 #define DEVADD9_1 USB201.DEVADD9
    527 #define DEVADDA_1 USB201.DEVADDA
    528 #define SUSPMODE_1 USB201.SUSPMODE
    529 #define D0FIFOB0_1 USB201.D0FIFOB0
    530 #define D0FIFOB1_1 USB201.D0FIFOB1
    531 #define D0FIFOB2_1 USB201.D0FIFOB2
    532 #define D0FIFOB3_1 USB201.D0FIFOB3
    533 #define D0FIFOB4_1 USB201.D0FIFOB4
    534 #define D0FIFOB5_1 USB201.D0FIFOB5
    535 #define D0FIFOB6_1 USB201.D0FIFOB6
    536 #define D0FIFOB7_1 USB201.D0FIFOB7
    537 #define D1FIFOB0_1 USB201.D1FIFOB0
    538 #define D1FIFOB1_1 USB201.D1FIFOB1
    539 #define D1FIFOB2_1 USB201.D1FIFOB2
    540 #define D1FIFOB3_1 USB201.D1FIFOB3
    541 #define D1FIFOB4_1 USB201.D1FIFOB4
    542 #define D1FIFOB5_1 USB201.D1FIFOB5
    543 #define D1FIFOB6_1 USB201.D1FIFOB6
    544 #define D1FIFOB7_1 USB201.D1FIFOB7
     584} r_io_usb20_from_dmfifob0_t;
     585
     586
     587/* Channel array defines of USB20 (2)*/
     588#ifdef  DECLARE_USB20_CHANNELS
     589volatile struct st_usb20*  USB20[ USB20_COUNT ] =
     590    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     591    USB20_ADDRESS_LIST;
     592    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     593#endif  /* DECLARE_USB20_CHANNELS */
     594
     595#ifdef  DECLARE_USB20_FROM_D0FIFOB0_CHANNELS
     596volatile struct st_usb20_from_dmfifob0*  USB20_FROM_D0FIFOB0[ USB20_COUNT ][ USB20_FROM_D0FIFOB0_COUNT ] =
     597    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     598    USB20_FROM_D0FIFOB0_ADDRESS_LIST;
     599    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     600#endif  /* DECLARE_USB20_FROM_D0FIFOB0_CHANNELS */
     601
     602#ifdef  DECLARE_USB20_FROM_PIPE1ATRE_CHANNELS
     603volatile struct st_usb20_from_pipe1tre*  USB20_FROM_PIPE1ATRE[ USB20_COUNT ][ USB20_FROM_PIPE1ATRE_COUNT ] =
     604    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     605    USB20_FROM_PIPE1ATRE_ADDRESS_LIST;
     606    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     607#endif  /* DECLARE_USB20_FROM_PIPE1ATRE_CHANNELS */
     608
     609#ifdef  DECLARE_USB20_FROM_D0FIFOSEL_CHANNELS
     610volatile struct st_usb20_from_d0fifosel*  USB20_FROM_D0FIFOSEL[ USB20_COUNT ][ USB20_FROM_D0FIFOSEL_COUNT ] =
     611    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     612    USB20_FROM_D0FIFOSEL_ADDRESS_LIST;
     613    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     614#endif  /* DECLARE_USB20_FROM_D0FIFOSEL_CHANNELS */
     615/* End of channel array defines of USB20 (2)*/
     616
     617
    545618/* <-SEC M1.10.1 */
     619/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     620/* <-QAC 0857 */
     621/* <-QAC 0639 */
    546622#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef VDC5_IODEFINE_H
    3030#define VDC5_IODEFINE_H
    3131/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
    3234/* ->SEC M1.10.1 : Not magic number */
    3335
    34 struct st_vdc5
    35 {                                                          /* VDC5             */
     36#define VDC50   (*(struct st_vdc5    *)0xFCFF7400uL) /* VDC50 */
     37#define VDC51   (*(struct st_vdc5    *)0xFCFF9400uL) /* VDC51 */
     38
     39
     40/* Start of channel array defines of VDC5 */
     41
     42/* Channel array defines of VDC5 */
     43/*(Sample) value = VDC5[ channel ]->INP_UPDATE; */
     44#define VDC5_COUNT  (2)
     45#define VDC5_ADDRESS_LIST \
     46{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     47    &VDC50, &VDC51 \
     48}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     49
     50
     51
     52/* Channel array defines of VDC50_FROM_GR2_AB7_ARRAY */
     53/*(Sample) value = VDC50_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
     54#define VDC50_FROM_GR2_AB7_ARRAY_COUNT  (2)
     55#define VDC50_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \
     56{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     57{ \
     58    &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 },{ \
     59    &VDC51_FROM_GR2_AB7, &VDC51_FROM_GR3_AB7 \
     60} \
     61}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     62#define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */
     63#define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */
     64#define VDC51_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR2_AB7) /* VDC51_FROM_GR2_AB7 */
     65#define VDC51_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR3_AB7) /* VDC51_FROM_GR3_AB7 */
     66
     67
     68
     69
     70/* Channel array defines of VDC50_FROM_GR2_UPDATE_ARRAY */
     71/*(Sample) value = VDC50_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
     72#define VDC50_FROM_GR2_UPDATE_ARRAY_COUNT  (2)
     73#define VDC50_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \
     74{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     75{ \
     76    &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE },{ \
     77    &VDC51_FROM_GR2_UPDATE, &VDC51_FROM_GR3_UPDATE \
     78} \
     79}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     80#define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */
     81#define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */
     82#define VDC51_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR2_UPDATE) /* VDC51_FROM_GR2_UPDATE */
     83#define VDC51_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR3_UPDATE) /* VDC51_FROM_GR3_UPDATE */
     84
     85
     86
     87
     88/* Channel array defines of VDC50_FROM_SC0_SCL1_PBUF0_ARRAY */
     89/*(Sample) value = VDC50_FROM_SC0_SCL1_PBUF0_ARRAY[ channel ][ index ]->SC0_SCL1_PBUF0; */
     90#define VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT  (2)
     91#define VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST \
     92{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     93{ \
     94    &VDC50_FROM_SC0_SCL1_PBUF0, &VDC50_FROM_SC1_SCL1_PBUF0 },{ \
     95    &VDC51_FROM_SC0_SCL1_PBUF0, &VDC51_FROM_SC1_SCL1_PBUF0 \
     96} \
     97}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     98#define VDC50_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC0_SCL1_PBUF0) /* VDC50_FROM_SC0_SCL1_PBUF0 */
     99#define VDC50_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC1_SCL1_PBUF0) /* VDC50_FROM_SC1_SCL1_PBUF0 */
     100#define VDC51_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC0_SCL1_PBUF0) /* VDC51_FROM_SC0_SCL1_PBUF0 */
     101#define VDC51_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC1_SCL1_PBUF0) /* VDC51_FROM_SC1_SCL1_PBUF0 */
     102
     103
     104
     105
     106/* Channel array defines of VDC50_FROM_SC0_SCL0_UPDATE_ARRAY */
     107/*(Sample) value = VDC50_FROM_SC0_SCL0_UPDATE_ARRAY[ channel ][ index ]->SC0_SCL0_UPDATE; */
     108#define VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT  (2)
     109#define VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST \
     110{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     111{ \
     112    &VDC50_FROM_SC0_SCL0_UPDATE, &VDC50_FROM_SC1_SCL0_UPDATE },{ \
     113    &VDC51_FROM_SC0_SCL0_UPDATE, &VDC51_FROM_SC1_SCL0_UPDATE \
     114} \
     115}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     116#define VDC50_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC0_SCL0_UPDATE) /* VDC50_FROM_SC0_SCL0_UPDATE */
     117#define VDC50_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC1_SCL0_UPDATE) /* VDC50_FROM_SC1_SCL0_UPDATE */
     118#define VDC51_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC0_SCL0_UPDATE) /* VDC51_FROM_SC0_SCL0_UPDATE */
     119#define VDC51_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC1_SCL0_UPDATE) /* VDC51_FROM_SC1_SCL0_UPDATE */
     120
     121
     122
     123
     124/* Channel array defines of VDC50_FROM_ADJ0_UPDATE_ARRAY */
     125/*(Sample) value = VDC50_FROM_ADJ0_UPDATE_ARRAY[ channel ][ index ]->ADJ0_UPDATE; */
     126#define VDC50_FROM_ADJ0_UPDATE_ARRAY_COUNT  (2)
     127#define VDC50_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST \
     128{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     129{ \
     130    &VDC50_FROM_ADJ0_UPDATE, &VDC50_FROM_ADJ1_UPDATE },{ \
     131    &VDC51_FROM_ADJ0_UPDATE, &VDC51_FROM_ADJ1_UPDATE \
     132} \
     133}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     134#define VDC50_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ0_UPDATE) /* VDC50_FROM_ADJ0_UPDATE */
     135#define VDC50_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ1_UPDATE) /* VDC50_FROM_ADJ1_UPDATE */
     136#define VDC51_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ0_UPDATE) /* VDC51_FROM_ADJ0_UPDATE */
     137#define VDC51_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ1_UPDATE) /* VDC51_FROM_ADJ1_UPDATE */
     138
     139
     140
     141
     142/* Channel array defines of VDC50_FROM_GR0_AB7_ARRAY */
     143/*(Sample) value = VDC50_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
     144#define VDC50_FROM_GR0_AB7_ARRAY_COUNT  (2)
     145#define VDC50_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \
     146{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     147{ \
     148    &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR1_AB7 },{ \
     149    &VDC51_FROM_GR0_AB7, &VDC51_FROM_GR1_AB7 \
     150} \
     151}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     152#define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */
     153#define VDC50_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR1_AB7) /* VDC50_FROM_GR1_AB7 */
     154#define VDC51_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR0_AB7) /* VDC51_FROM_GR0_AB7 */
     155#define VDC51_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR1_AB7) /* VDC51_FROM_GR1_AB7 */
     156
     157
     158
     159
     160/* Channel array defines of VDC50_FROM_GR0_UPDATE_ARRAY */
     161/*(Sample) value = VDC50_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
     162#define VDC50_FROM_GR0_UPDATE_ARRAY_COUNT  (2)
     163#define VDC50_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \
     164{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     165{ \
     166    &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR1_UPDATE },{ \
     167    &VDC51_FROM_GR0_UPDATE, &VDC51_FROM_GR1_UPDATE \
     168} \
     169}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
     170#define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */
     171#define VDC50_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR1_UPDATE) /* VDC50_FROM_GR1_UPDATE */
     172#define VDC51_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR0_UPDATE) /* VDC51_FROM_GR0_UPDATE */
     173#define VDC51_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR1_UPDATE) /* VDC51_FROM_GR1_UPDATE */
     174
     175
     176/* End of channel array defines of VDC5 */
     177
     178
     179#define VDC50INP_UPDATE (VDC50.INP_UPDATE)
     180#define VDC50INP_SEL_CNT (VDC50.INP_SEL_CNT)
     181#define VDC50INP_EXT_SYNC_CNT (VDC50.INP_EXT_SYNC_CNT)
     182#define VDC50INP_VSYNC_PH_ADJ (VDC50.INP_VSYNC_PH_ADJ)
     183#define VDC50INP_DLY_ADJ (VDC50.INP_DLY_ADJ)
     184#define VDC50IMGCNT_UPDATE (VDC50.IMGCNT_UPDATE)
     185#define VDC50IMGCNT_NR_CNT0 (VDC50.IMGCNT_NR_CNT0)
     186#define VDC50IMGCNT_NR_CNT1 (VDC50.IMGCNT_NR_CNT1)
     187#define VDC50IMGCNT_MTX_MODE (VDC50.IMGCNT_MTX_MODE)
     188#define VDC50IMGCNT_MTX_YG_ADJ0 (VDC50.IMGCNT_MTX_YG_ADJ0)
     189#define VDC50IMGCNT_MTX_YG_ADJ1 (VDC50.IMGCNT_MTX_YG_ADJ1)
     190#define VDC50IMGCNT_MTX_CBB_ADJ0 (VDC50.IMGCNT_MTX_CBB_ADJ0)
     191#define VDC50IMGCNT_MTX_CBB_ADJ1 (VDC50.IMGCNT_MTX_CBB_ADJ1)
     192#define VDC50IMGCNT_MTX_CRR_ADJ0 (VDC50.IMGCNT_MTX_CRR_ADJ0)
     193#define VDC50IMGCNT_MTX_CRR_ADJ1 (VDC50.IMGCNT_MTX_CRR_ADJ1)
     194#define VDC50IMGCNT_DRC_REG (VDC50.IMGCNT_DRC_REG)
     195#define VDC50SC0_SCL0_UPDATE (VDC50.SC0_SCL0_UPDATE)
     196#define VDC50SC0_SCL0_FRC1 (VDC50.SC0_SCL0_FRC1)
     197#define VDC50SC0_SCL0_FRC2 (VDC50.SC0_SCL0_FRC2)
     198#define VDC50SC0_SCL0_FRC3 (VDC50.SC0_SCL0_FRC3)
     199#define VDC50SC0_SCL0_FRC4 (VDC50.SC0_SCL0_FRC4)
     200#define VDC50SC0_SCL0_FRC5 (VDC50.SC0_SCL0_FRC5)
     201#define VDC50SC0_SCL0_FRC6 (VDC50.SC0_SCL0_FRC6)
     202#define VDC50SC0_SCL0_FRC7 (VDC50.SC0_SCL0_FRC7)
     203#define VDC50SC0_SCL0_FRC9 (VDC50.SC0_SCL0_FRC9)
     204#define VDC50SC0_SCL0_MON0 (VDC50.SC0_SCL0_MON0)
     205#define VDC50SC0_SCL0_INT (VDC50.SC0_SCL0_INT)
     206#define VDC50SC0_SCL0_DS1 (VDC50.SC0_SCL0_DS1)
     207#define VDC50SC0_SCL0_DS2 (VDC50.SC0_SCL0_DS2)
     208#define VDC50SC0_SCL0_DS3 (VDC50.SC0_SCL0_DS3)
     209#define VDC50SC0_SCL0_DS4 (VDC50.SC0_SCL0_DS4)
     210#define VDC50SC0_SCL0_DS5 (VDC50.SC0_SCL0_DS5)
     211#define VDC50SC0_SCL0_DS6 (VDC50.SC0_SCL0_DS6)
     212#define VDC50SC0_SCL0_DS7 (VDC50.SC0_SCL0_DS7)
     213#define VDC50SC0_SCL0_US1 (VDC50.SC0_SCL0_US1)
     214#define VDC50SC0_SCL0_US2 (VDC50.SC0_SCL0_US2)
     215#define VDC50SC0_SCL0_US3 (VDC50.SC0_SCL0_US3)
     216#define VDC50SC0_SCL0_US4 (VDC50.SC0_SCL0_US4)
     217#define VDC50SC0_SCL0_US5 (VDC50.SC0_SCL0_US5)
     218#define VDC50SC0_SCL0_US6 (VDC50.SC0_SCL0_US6)
     219#define VDC50SC0_SCL0_US7 (VDC50.SC0_SCL0_US7)
     220#define VDC50SC0_SCL0_US8 (VDC50.SC0_SCL0_US8)
     221#define VDC50SC0_SCL0_OVR1 (VDC50.SC0_SCL0_OVR1)
     222#define VDC50SC0_SCL1_UPDATE (VDC50.SC0_SCL1_UPDATE)
     223#define VDC50SC0_SCL1_WR1 (VDC50.SC0_SCL1_WR1)
     224#define VDC50SC0_SCL1_WR2 (VDC50.SC0_SCL1_WR2)
     225#define VDC50SC0_SCL1_WR3 (VDC50.SC0_SCL1_WR3)
     226#define VDC50SC0_SCL1_WR4 (VDC50.SC0_SCL1_WR4)
     227#define VDC50SC0_SCL1_WR5 (VDC50.SC0_SCL1_WR5)
     228#define VDC50SC0_SCL1_WR6 (VDC50.SC0_SCL1_WR6)
     229#define VDC50SC0_SCL1_WR7 (VDC50.SC0_SCL1_WR7)
     230#define VDC50SC0_SCL1_WR8 (VDC50.SC0_SCL1_WR8)
     231#define VDC50SC0_SCL1_WR9 (VDC50.SC0_SCL1_WR9)
     232#define VDC50SC0_SCL1_WR10 (VDC50.SC0_SCL1_WR10)
     233#define VDC50SC0_SCL1_WR11 (VDC50.SC0_SCL1_WR11)
     234#define VDC50SC0_SCL1_MON1 (VDC50.SC0_SCL1_MON1)
     235#define VDC50SC0_SCL1_PBUF0 (VDC50.SC0_SCL1_PBUF0)
     236#define VDC50SC0_SCL1_PBUF1 (VDC50.SC0_SCL1_PBUF1)
     237#define VDC50SC0_SCL1_PBUF2 (VDC50.SC0_SCL1_PBUF2)
     238#define VDC50SC0_SCL1_PBUF3 (VDC50.SC0_SCL1_PBUF3)
     239#define VDC50SC0_SCL1_PBUF_FLD (VDC50.SC0_SCL1_PBUF_FLD)
     240#define VDC50SC0_SCL1_PBUF_CNT (VDC50.SC0_SCL1_PBUF_CNT)
     241#define VDC50GR0_UPDATE (VDC50.GR0_UPDATE)
     242#define VDC50GR0_FLM_RD (VDC50.GR0_FLM_RD)
     243#define VDC50GR0_FLM1 (VDC50.GR0_FLM1)
     244#define VDC50GR0_FLM2 (VDC50.GR0_FLM2)
     245#define VDC50GR0_FLM3 (VDC50.GR0_FLM3)
     246#define VDC50GR0_FLM4 (VDC50.GR0_FLM4)
     247#define VDC50GR0_FLM5 (VDC50.GR0_FLM5)
     248#define VDC50GR0_FLM6 (VDC50.GR0_FLM6)
     249#define VDC50GR0_AB1 (VDC50.GR0_AB1)
     250#define VDC50GR0_AB2 (VDC50.GR0_AB2)
     251#define VDC50GR0_AB3 (VDC50.GR0_AB3)
     252#define VDC50GR0_AB7 (VDC50.GR0_AB7)
     253#define VDC50GR0_AB8 (VDC50.GR0_AB8)
     254#define VDC50GR0_AB9 (VDC50.GR0_AB9)
     255#define VDC50GR0_AB10 (VDC50.GR0_AB10)
     256#define VDC50GR0_AB11 (VDC50.GR0_AB11)
     257#define VDC50GR0_BASE (VDC50.GR0_BASE)
     258#define VDC50GR0_CLUT (VDC50.GR0_CLUT)
     259#define VDC50ADJ0_UPDATE (VDC50.ADJ0_UPDATE)
     260#define VDC50ADJ0_BKSTR_SET (VDC50.ADJ0_BKSTR_SET)
     261#define VDC50ADJ0_ENH_TIM1 (VDC50.ADJ0_ENH_TIM1)
     262#define VDC50ADJ0_ENH_TIM2 (VDC50.ADJ0_ENH_TIM2)
     263#define VDC50ADJ0_ENH_TIM3 (VDC50.ADJ0_ENH_TIM3)
     264#define VDC50ADJ0_ENH_SHP1 (VDC50.ADJ0_ENH_SHP1)
     265#define VDC50ADJ0_ENH_SHP2 (VDC50.ADJ0_ENH_SHP2)
     266#define VDC50ADJ0_ENH_SHP3 (VDC50.ADJ0_ENH_SHP3)
     267#define VDC50ADJ0_ENH_SHP4 (VDC50.ADJ0_ENH_SHP4)
     268#define VDC50ADJ0_ENH_SHP5 (VDC50.ADJ0_ENH_SHP5)
     269#define VDC50ADJ0_ENH_SHP6 (VDC50.ADJ0_ENH_SHP6)
     270#define VDC50ADJ0_ENH_LTI1 (VDC50.ADJ0_ENH_LTI1)
     271#define VDC50ADJ0_ENH_LTI2 (VDC50.ADJ0_ENH_LTI2)
     272#define VDC50ADJ0_MTX_MODE (VDC50.ADJ0_MTX_MODE)
     273#define VDC50ADJ0_MTX_YG_ADJ0 (VDC50.ADJ0_MTX_YG_ADJ0)
     274#define VDC50ADJ0_MTX_YG_ADJ1 (VDC50.ADJ0_MTX_YG_ADJ1)
     275#define VDC50ADJ0_MTX_CBB_ADJ0 (VDC50.ADJ0_MTX_CBB_ADJ0)
     276#define VDC50ADJ0_MTX_CBB_ADJ1 (VDC50.ADJ0_MTX_CBB_ADJ1)
     277#define VDC50ADJ0_MTX_CRR_ADJ0 (VDC50.ADJ0_MTX_CRR_ADJ0)
     278#define VDC50ADJ0_MTX_CRR_ADJ1 (VDC50.ADJ0_MTX_CRR_ADJ1)
     279#define VDC50GR2_UPDATE (VDC50.GR2_UPDATE)
     280#define VDC50GR2_FLM_RD (VDC50.GR2_FLM_RD)
     281#define VDC50GR2_FLM1 (VDC50.GR2_FLM1)
     282#define VDC50GR2_FLM2 (VDC50.GR2_FLM2)
     283#define VDC50GR2_FLM3 (VDC50.GR2_FLM3)
     284#define VDC50GR2_FLM4 (VDC50.GR2_FLM4)
     285#define VDC50GR2_FLM5 (VDC50.GR2_FLM5)
     286#define VDC50GR2_FLM6 (VDC50.GR2_FLM6)
     287#define VDC50GR2_AB1 (VDC50.GR2_AB1)
     288#define VDC50GR2_AB2 (VDC50.GR2_AB2)
     289#define VDC50GR2_AB3 (VDC50.GR2_AB3)
     290#define VDC50GR2_AB4 (VDC50.GR2_AB4)
     291#define VDC50GR2_AB5 (VDC50.GR2_AB5)
     292#define VDC50GR2_AB6 (VDC50.GR2_AB6)
     293#define VDC50GR2_AB7 (VDC50.GR2_AB7)
     294#define VDC50GR2_AB8 (VDC50.GR2_AB8)
     295#define VDC50GR2_AB9 (VDC50.GR2_AB9)
     296#define VDC50GR2_AB10 (VDC50.GR2_AB10)
     297#define VDC50GR2_AB11 (VDC50.GR2_AB11)
     298#define VDC50GR2_BASE (VDC50.GR2_BASE)
     299#define VDC50GR2_CLUT (VDC50.GR2_CLUT)
     300#define VDC50GR2_MON (VDC50.GR2_MON)
     301#define VDC50GR3_UPDATE (VDC50.GR3_UPDATE)
     302#define VDC50GR3_FLM_RD (VDC50.GR3_FLM_RD)
     303#define VDC50GR3_FLM1 (VDC50.GR3_FLM1)
     304#define VDC50GR3_FLM2 (VDC50.GR3_FLM2)
     305#define VDC50GR3_FLM3 (VDC50.GR3_FLM3)
     306#define VDC50GR3_FLM4 (VDC50.GR3_FLM4)
     307#define VDC50GR3_FLM5 (VDC50.GR3_FLM5)
     308#define VDC50GR3_FLM6 (VDC50.GR3_FLM6)
     309#define VDC50GR3_AB1 (VDC50.GR3_AB1)
     310#define VDC50GR3_AB2 (VDC50.GR3_AB2)
     311#define VDC50GR3_AB3 (VDC50.GR3_AB3)
     312#define VDC50GR3_AB4 (VDC50.GR3_AB4)
     313#define VDC50GR3_AB5 (VDC50.GR3_AB5)
     314#define VDC50GR3_AB6 (VDC50.GR3_AB6)
     315#define VDC50GR3_AB7 (VDC50.GR3_AB7)
     316#define VDC50GR3_AB8 (VDC50.GR3_AB8)
     317#define VDC50GR3_AB9 (VDC50.GR3_AB9)
     318#define VDC50GR3_AB10 (VDC50.GR3_AB10)
     319#define VDC50GR3_AB11 (VDC50.GR3_AB11)
     320#define VDC50GR3_BASE (VDC50.GR3_BASE)
     321#define VDC50GR3_CLUT_INT (VDC50.GR3_CLUT_INT)
     322#define VDC50GR3_MON (VDC50.GR3_MON)
     323#define VDC50GAM_G_UPDATE (VDC50.GAM_G_UPDATE)
     324#define VDC50GAM_SW (VDC50.GAM_SW)
     325#define VDC50GAM_G_LUT1 (VDC50.GAM_G_LUT1)
     326#define VDC50GAM_G_LUT2 (VDC50.GAM_G_LUT2)
     327#define VDC50GAM_G_LUT3 (VDC50.GAM_G_LUT3)
     328#define VDC50GAM_G_LUT4 (VDC50.GAM_G_LUT4)
     329#define VDC50GAM_G_LUT5 (VDC50.GAM_G_LUT5)
     330#define VDC50GAM_G_LUT6 (VDC50.GAM_G_LUT6)
     331#define VDC50GAM_G_LUT7 (VDC50.GAM_G_LUT7)
     332#define VDC50GAM_G_LUT8 (VDC50.GAM_G_LUT8)
     333#define VDC50GAM_G_LUT9 (VDC50.GAM_G_LUT9)
     334#define VDC50GAM_G_LUT10 (VDC50.GAM_G_LUT10)
     335#define VDC50GAM_G_LUT11 (VDC50.GAM_G_LUT11)
     336#define VDC50GAM_G_LUT12 (VDC50.GAM_G_LUT12)
     337#define VDC50GAM_G_LUT13 (VDC50.GAM_G_LUT13)
     338#define VDC50GAM_G_LUT14 (VDC50.GAM_G_LUT14)
     339#define VDC50GAM_G_LUT15 (VDC50.GAM_G_LUT15)
     340#define VDC50GAM_G_LUT16 (VDC50.GAM_G_LUT16)
     341#define VDC50GAM_G_AREA1 (VDC50.GAM_G_AREA1)
     342#define VDC50GAM_G_AREA2 (VDC50.GAM_G_AREA2)
     343#define VDC50GAM_G_AREA3 (VDC50.GAM_G_AREA3)
     344#define VDC50GAM_G_AREA4 (VDC50.GAM_G_AREA4)
     345#define VDC50GAM_G_AREA5 (VDC50.GAM_G_AREA5)
     346#define VDC50GAM_G_AREA6 (VDC50.GAM_G_AREA6)
     347#define VDC50GAM_G_AREA7 (VDC50.GAM_G_AREA7)
     348#define VDC50GAM_G_AREA8 (VDC50.GAM_G_AREA8)
     349#define VDC50GAM_B_UPDATE (VDC50.GAM_B_UPDATE)
     350#define VDC50GAM_B_LUT1 (VDC50.GAM_B_LUT1)
     351#define VDC50GAM_B_LUT2 (VDC50.GAM_B_LUT2)
     352#define VDC50GAM_B_LUT3 (VDC50.GAM_B_LUT3)
     353#define VDC50GAM_B_LUT4 (VDC50.GAM_B_LUT4)
     354#define VDC50GAM_B_LUT5 (VDC50.GAM_B_LUT5)
     355#define VDC50GAM_B_LUT6 (VDC50.GAM_B_LUT6)
     356#define VDC50GAM_B_LUT7 (VDC50.GAM_B_LUT7)
     357#define VDC50GAM_B_LUT8 (VDC50.GAM_B_LUT8)
     358#define VDC50GAM_B_LUT9 (VDC50.GAM_B_LUT9)
     359#define VDC50GAM_B_LUT10 (VDC50.GAM_B_LUT10)
     360#define VDC50GAM_B_LUT11 (VDC50.GAM_B_LUT11)
     361#define VDC50GAM_B_LUT12 (VDC50.GAM_B_LUT12)
     362#define VDC50GAM_B_LUT13 (VDC50.GAM_B_LUT13)
     363#define VDC50GAM_B_LUT14 (VDC50.GAM_B_LUT14)
     364#define VDC50GAM_B_LUT15 (VDC50.GAM_B_LUT15)
     365#define VDC50GAM_B_LUT16 (VDC50.GAM_B_LUT16)
     366#define VDC50GAM_B_AREA1 (VDC50.GAM_B_AREA1)
     367#define VDC50GAM_B_AREA2 (VDC50.GAM_B_AREA2)
     368#define VDC50GAM_B_AREA3 (VDC50.GAM_B_AREA3)
     369#define VDC50GAM_B_AREA4 (VDC50.GAM_B_AREA4)
     370#define VDC50GAM_B_AREA5 (VDC50.GAM_B_AREA5)
     371#define VDC50GAM_B_AREA6 (VDC50.GAM_B_AREA6)
     372#define VDC50GAM_B_AREA7 (VDC50.GAM_B_AREA7)
     373#define VDC50GAM_B_AREA8 (VDC50.GAM_B_AREA8)
     374#define VDC50GAM_R_UPDATE (VDC50.GAM_R_UPDATE)
     375#define VDC50GAM_R_LUT1 (VDC50.GAM_R_LUT1)
     376#define VDC50GAM_R_LUT2 (VDC50.GAM_R_LUT2)
     377#define VDC50GAM_R_LUT3 (VDC50.GAM_R_LUT3)
     378#define VDC50GAM_R_LUT4 (VDC50.GAM_R_LUT4)
     379#define VDC50GAM_R_LUT5 (VDC50.GAM_R_LUT5)
     380#define VDC50GAM_R_LUT6 (VDC50.GAM_R_LUT6)
     381#define VDC50GAM_R_LUT7 (VDC50.GAM_R_LUT7)
     382#define VDC50GAM_R_LUT8 (VDC50.GAM_R_LUT8)
     383#define VDC50GAM_R_LUT9 (VDC50.GAM_R_LUT9)
     384#define VDC50GAM_R_LUT10 (VDC50.GAM_R_LUT10)
     385#define VDC50GAM_R_LUT11 (VDC50.GAM_R_LUT11)
     386#define VDC50GAM_R_LUT12 (VDC50.GAM_R_LUT12)
     387#define VDC50GAM_R_LUT13 (VDC50.GAM_R_LUT13)
     388#define VDC50GAM_R_LUT14 (VDC50.GAM_R_LUT14)
     389#define VDC50GAM_R_LUT15 (VDC50.GAM_R_LUT15)
     390#define VDC50GAM_R_LUT16 (VDC50.GAM_R_LUT16)
     391#define VDC50GAM_R_AREA1 (VDC50.GAM_R_AREA1)
     392#define VDC50GAM_R_AREA2 (VDC50.GAM_R_AREA2)
     393#define VDC50GAM_R_AREA3 (VDC50.GAM_R_AREA3)
     394#define VDC50GAM_R_AREA4 (VDC50.GAM_R_AREA4)
     395#define VDC50GAM_R_AREA5 (VDC50.GAM_R_AREA5)
     396#define VDC50GAM_R_AREA6 (VDC50.GAM_R_AREA6)
     397#define VDC50GAM_R_AREA7 (VDC50.GAM_R_AREA7)
     398#define VDC50GAM_R_AREA8 (VDC50.GAM_R_AREA8)
     399#define VDC50TCON_UPDATE (VDC50.TCON_UPDATE)
     400#define VDC50TCON_TIM (VDC50.TCON_TIM)
     401#define VDC50TCON_TIM_STVA1 (VDC50.TCON_TIM_STVA1)
     402#define VDC50TCON_TIM_STVA2 (VDC50.TCON_TIM_STVA2)
     403#define VDC50TCON_TIM_STVB1 (VDC50.TCON_TIM_STVB1)
     404#define VDC50TCON_TIM_STVB2 (VDC50.TCON_TIM_STVB2)
     405#define VDC50TCON_TIM_STH1 (VDC50.TCON_TIM_STH1)
     406#define VDC50TCON_TIM_STH2 (VDC50.TCON_TIM_STH2)
     407#define VDC50TCON_TIM_STB1 (VDC50.TCON_TIM_STB1)
     408#define VDC50TCON_TIM_STB2 (VDC50.TCON_TIM_STB2)
     409#define VDC50TCON_TIM_CPV1 (VDC50.TCON_TIM_CPV1)
     410#define VDC50TCON_TIM_CPV2 (VDC50.TCON_TIM_CPV2)
     411#define VDC50TCON_TIM_POLA1 (VDC50.TCON_TIM_POLA1)
     412#define VDC50TCON_TIM_POLA2 (VDC50.TCON_TIM_POLA2)
     413#define VDC50TCON_TIM_POLB1 (VDC50.TCON_TIM_POLB1)
     414#define VDC50TCON_TIM_POLB2 (VDC50.TCON_TIM_POLB2)
     415#define VDC50TCON_TIM_DE (VDC50.TCON_TIM_DE)
     416#define VDC50OUT_UPDATE (VDC50.OUT_UPDATE)
     417#define VDC50OUT_SET (VDC50.OUT_SET)
     418#define VDC50OUT_BRIGHT1 (VDC50.OUT_BRIGHT1)
     419#define VDC50OUT_BRIGHT2 (VDC50.OUT_BRIGHT2)
     420#define VDC50OUT_CONTRAST (VDC50.OUT_CONTRAST)
     421#define VDC50OUT_PDTHA (VDC50.OUT_PDTHA)
     422#define VDC50OUT_CLK_PHASE (VDC50.OUT_CLK_PHASE)
     423#define VDC50SYSCNT_INT1 (VDC50.SYSCNT_INT1)
     424#define VDC50SYSCNT_INT2 (VDC50.SYSCNT_INT2)
     425#define VDC50SYSCNT_INT3 (VDC50.SYSCNT_INT3)
     426#define VDC50SYSCNT_INT4 (VDC50.SYSCNT_INT4)
     427#define VDC50SYSCNT_INT5 (VDC50.SYSCNT_INT5)
     428#define VDC50SYSCNT_INT6 (VDC50.SYSCNT_INT6)
     429#define VDC50SYSCNT_PANEL_CLK (VDC50.SYSCNT_PANEL_CLK)
     430#define VDC50SYSCNT_CLUT (VDC50.SYSCNT_CLUT)
     431#define VDC50SC1_SCL0_UPDATE (VDC50.SC1_SCL0_UPDATE)
     432#define VDC50SC1_SCL0_FRC1 (VDC50.SC1_SCL0_FRC1)
     433#define VDC50SC1_SCL0_FRC2 (VDC50.SC1_SCL0_FRC2)
     434#define VDC50SC1_SCL0_FRC3 (VDC50.SC1_SCL0_FRC3)
     435#define VDC50SC1_SCL0_FRC4 (VDC50.SC1_SCL0_FRC4)
     436#define VDC50SC1_SCL0_FRC5 (VDC50.SC1_SCL0_FRC5)
     437#define VDC50SC1_SCL0_FRC6 (VDC50.SC1_SCL0_FRC6)
     438#define VDC50SC1_SCL0_FRC7 (VDC50.SC1_SCL0_FRC7)
     439#define VDC50SC1_SCL0_FRC9 (VDC50.SC1_SCL0_FRC9)
     440#define VDC50SC1_SCL0_MON0 (VDC50.SC1_SCL0_MON0)
     441#define VDC50SC1_SCL0_INT (VDC50.SC1_SCL0_INT)
     442#define VDC50SC1_SCL0_DS1 (VDC50.SC1_SCL0_DS1)
     443#define VDC50SC1_SCL0_DS2 (VDC50.SC1_SCL0_DS2)
     444#define VDC50SC1_SCL0_DS3 (VDC50.SC1_SCL0_DS3)
     445#define VDC50SC1_SCL0_DS4 (VDC50.SC1_SCL0_DS4)
     446#define VDC50SC1_SCL0_DS5 (VDC50.SC1_SCL0_DS5)
     447#define VDC50SC1_SCL0_DS6 (VDC50.SC1_SCL0_DS6)
     448#define VDC50SC1_SCL0_DS7 (VDC50.SC1_SCL0_DS7)
     449#define VDC50SC1_SCL0_US1 (VDC50.SC1_SCL0_US1)
     450#define VDC50SC1_SCL0_US2 (VDC50.SC1_SCL0_US2)
     451#define VDC50SC1_SCL0_US3 (VDC50.SC1_SCL0_US3)
     452#define VDC50SC1_SCL0_US4 (VDC50.SC1_SCL0_US4)
     453#define VDC50SC1_SCL0_US5 (VDC50.SC1_SCL0_US5)
     454#define VDC50SC1_SCL0_US6 (VDC50.SC1_SCL0_US6)
     455#define VDC50SC1_SCL0_US7 (VDC50.SC1_SCL0_US7)
     456#define VDC50SC1_SCL0_US8 (VDC50.SC1_SCL0_US8)
     457#define VDC50SC1_SCL0_OVR1 (VDC50.SC1_SCL0_OVR1)
     458#define VDC50SC1_SCL1_UPDATE (VDC50.SC1_SCL1_UPDATE)
     459#define VDC50SC1_SCL1_WR1 (VDC50.SC1_SCL1_WR1)
     460#define VDC50SC1_SCL1_WR2 (VDC50.SC1_SCL1_WR2)
     461#define VDC50SC1_SCL1_WR3 (VDC50.SC1_SCL1_WR3)
     462#define VDC50SC1_SCL1_WR4 (VDC50.SC1_SCL1_WR4)
     463#define VDC50SC1_SCL1_WR5 (VDC50.SC1_SCL1_WR5)
     464#define VDC50SC1_SCL1_WR6 (VDC50.SC1_SCL1_WR6)
     465#define VDC50SC1_SCL1_WR7 (VDC50.SC1_SCL1_WR7)
     466#define VDC50SC1_SCL1_WR8 (VDC50.SC1_SCL1_WR8)
     467#define VDC50SC1_SCL1_WR9 (VDC50.SC1_SCL1_WR9)
     468#define VDC50SC1_SCL1_WR10 (VDC50.SC1_SCL1_WR10)
     469#define VDC50SC1_SCL1_WR11 (VDC50.SC1_SCL1_WR11)
     470#define VDC50SC1_SCL1_MON1 (VDC50.SC1_SCL1_MON1)
     471#define VDC50SC1_SCL1_PBUF0 (VDC50.SC1_SCL1_PBUF0)
     472#define VDC50SC1_SCL1_PBUF1 (VDC50.SC1_SCL1_PBUF1)
     473#define VDC50SC1_SCL1_PBUF2 (VDC50.SC1_SCL1_PBUF2)
     474#define VDC50SC1_SCL1_PBUF3 (VDC50.SC1_SCL1_PBUF3)
     475#define VDC50SC1_SCL1_PBUF_FLD (VDC50.SC1_SCL1_PBUF_FLD)
     476#define VDC50SC1_SCL1_PBUF_CNT (VDC50.SC1_SCL1_PBUF_CNT)
     477#define VDC50GR1_UPDATE (VDC50.GR1_UPDATE)
     478#define VDC50GR1_FLM_RD (VDC50.GR1_FLM_RD)
     479#define VDC50GR1_FLM1 (VDC50.GR1_FLM1)
     480#define VDC50GR1_FLM2 (VDC50.GR1_FLM2)
     481#define VDC50GR1_FLM3 (VDC50.GR1_FLM3)
     482#define VDC50GR1_FLM4 (VDC50.GR1_FLM4)
     483#define VDC50GR1_FLM5 (VDC50.GR1_FLM5)
     484#define VDC50GR1_FLM6 (VDC50.GR1_FLM6)
     485#define VDC50GR1_AB1 (VDC50.GR1_AB1)
     486#define VDC50GR1_AB2 (VDC50.GR1_AB2)
     487#define VDC50GR1_AB3 (VDC50.GR1_AB3)
     488#define VDC50GR1_AB4 (VDC50.GR1_AB4)
     489#define VDC50GR1_AB5 (VDC50.GR1_AB5)
     490#define VDC50GR1_AB6 (VDC50.GR1_AB6)
     491#define VDC50GR1_AB7 (VDC50.GR1_AB7)
     492#define VDC50GR1_AB8 (VDC50.GR1_AB8)
     493#define VDC50GR1_AB9 (VDC50.GR1_AB9)
     494#define VDC50GR1_AB10 (VDC50.GR1_AB10)
     495#define VDC50GR1_AB11 (VDC50.GR1_AB11)
     496#define VDC50GR1_BASE (VDC50.GR1_BASE)
     497#define VDC50GR1_CLUT (VDC50.GR1_CLUT)
     498#define VDC50GR1_MON (VDC50.GR1_MON)
     499#define VDC50ADJ1_UPDATE (VDC50.ADJ1_UPDATE)
     500#define VDC50ADJ1_BKSTR_SET (VDC50.ADJ1_BKSTR_SET)
     501#define VDC50ADJ1_ENH_TIM1 (VDC50.ADJ1_ENH_TIM1)
     502#define VDC50ADJ1_ENH_TIM2 (VDC50.ADJ1_ENH_TIM2)
     503#define VDC50ADJ1_ENH_TIM3 (VDC50.ADJ1_ENH_TIM3)
     504#define VDC50ADJ1_ENH_SHP1 (VDC50.ADJ1_ENH_SHP1)
     505#define VDC50ADJ1_ENH_SHP2 (VDC50.ADJ1_ENH_SHP2)
     506#define VDC50ADJ1_ENH_SHP3 (VDC50.ADJ1_ENH_SHP3)
     507#define VDC50ADJ1_ENH_SHP4 (VDC50.ADJ1_ENH_SHP4)
     508#define VDC50ADJ1_ENH_SHP5 (VDC50.ADJ1_ENH_SHP5)
     509#define VDC50ADJ1_ENH_SHP6 (VDC50.ADJ1_ENH_SHP6)
     510#define VDC50ADJ1_ENH_LTI1 (VDC50.ADJ1_ENH_LTI1)
     511#define VDC50ADJ1_ENH_LTI2 (VDC50.ADJ1_ENH_LTI2)
     512#define VDC50ADJ1_MTX_MODE (VDC50.ADJ1_MTX_MODE)
     513#define VDC50ADJ1_MTX_YG_ADJ0 (VDC50.ADJ1_MTX_YG_ADJ0)
     514#define VDC50ADJ1_MTX_YG_ADJ1 (VDC50.ADJ1_MTX_YG_ADJ1)
     515#define VDC50ADJ1_MTX_CBB_ADJ0 (VDC50.ADJ1_MTX_CBB_ADJ0)
     516#define VDC50ADJ1_MTX_CBB_ADJ1 (VDC50.ADJ1_MTX_CBB_ADJ1)
     517#define VDC50ADJ1_MTX_CRR_ADJ0 (VDC50.ADJ1_MTX_CRR_ADJ0)
     518#define VDC50ADJ1_MTX_CRR_ADJ1 (VDC50.ADJ1_MTX_CRR_ADJ1)
     519#define VDC50GR_VIN_UPDATE (VDC50.GR_VIN_UPDATE)
     520#define VDC50GR_VIN_AB1 (VDC50.GR_VIN_AB1)
     521#define VDC50GR_VIN_AB2 (VDC50.GR_VIN_AB2)
     522#define VDC50GR_VIN_AB3 (VDC50.GR_VIN_AB3)
     523#define VDC50GR_VIN_AB4 (VDC50.GR_VIN_AB4)
     524#define VDC50GR_VIN_AB5 (VDC50.GR_VIN_AB5)
     525#define VDC50GR_VIN_AB6 (VDC50.GR_VIN_AB6)
     526#define VDC50GR_VIN_AB7 (VDC50.GR_VIN_AB7)
     527#define VDC50GR_VIN_BASE (VDC50.GR_VIN_BASE)
     528#define VDC50GR_VIN_MON (VDC50.GR_VIN_MON)
     529#define VDC50OIR_SCL0_UPDATE (VDC50.OIR_SCL0_UPDATE)
     530#define VDC50OIR_SCL0_FRC1 (VDC50.OIR_SCL0_FRC1)
     531#define VDC50OIR_SCL0_FRC2 (VDC50.OIR_SCL0_FRC2)
     532#define VDC50OIR_SCL0_FRC3 (VDC50.OIR_SCL0_FRC3)
     533#define VDC50OIR_SCL0_FRC4 (VDC50.OIR_SCL0_FRC4)
     534#define VDC50OIR_SCL0_FRC5 (VDC50.OIR_SCL0_FRC5)
     535#define VDC50OIR_SCL0_FRC6 (VDC50.OIR_SCL0_FRC6)
     536#define VDC50OIR_SCL0_FRC7 (VDC50.OIR_SCL0_FRC7)
     537#define VDC50OIR_SCL0_DS1 (VDC50.OIR_SCL0_DS1)
     538#define VDC50OIR_SCL0_DS2 (VDC50.OIR_SCL0_DS2)
     539#define VDC50OIR_SCL0_DS3 (VDC50.OIR_SCL0_DS3)
     540#define VDC50OIR_SCL0_DS7 (VDC50.OIR_SCL0_DS7)
     541#define VDC50OIR_SCL0_US1 (VDC50.OIR_SCL0_US1)
     542#define VDC50OIR_SCL0_US2 (VDC50.OIR_SCL0_US2)
     543#define VDC50OIR_SCL0_US3 (VDC50.OIR_SCL0_US3)
     544#define VDC50OIR_SCL0_US8 (VDC50.OIR_SCL0_US8)
     545#define VDC50OIR_SCL0_OVR1 (VDC50.OIR_SCL0_OVR1)
     546#define VDC50OIR_SCL1_UPDATE (VDC50.OIR_SCL1_UPDATE)
     547#define VDC50OIR_SCL1_WR1 (VDC50.OIR_SCL1_WR1)
     548#define VDC50OIR_SCL1_WR2 (VDC50.OIR_SCL1_WR2)
     549#define VDC50OIR_SCL1_WR3 (VDC50.OIR_SCL1_WR3)
     550#define VDC50OIR_SCL1_WR4 (VDC50.OIR_SCL1_WR4)
     551#define VDC50OIR_SCL1_WR5 (VDC50.OIR_SCL1_WR5)
     552#define VDC50OIR_SCL1_WR6 (VDC50.OIR_SCL1_WR6)
     553#define VDC50OIR_SCL1_WR7 (VDC50.OIR_SCL1_WR7)
     554#define VDC50GR_OIR_UPDATE (VDC50.GR_OIR_UPDATE)
     555#define VDC50GR_OIR_FLM_RD (VDC50.GR_OIR_FLM_RD)
     556#define VDC50GR_OIR_FLM1 (VDC50.GR_OIR_FLM1)
     557#define VDC50GR_OIR_FLM2 (VDC50.GR_OIR_FLM2)
     558#define VDC50GR_OIR_FLM3 (VDC50.GR_OIR_FLM3)
     559#define VDC50GR_OIR_FLM4 (VDC50.GR_OIR_FLM4)
     560#define VDC50GR_OIR_FLM5 (VDC50.GR_OIR_FLM5)
     561#define VDC50GR_OIR_FLM6 (VDC50.GR_OIR_FLM6)
     562#define VDC50GR_OIR_AB1 (VDC50.GR_OIR_AB1)
     563#define VDC50GR_OIR_AB2 (VDC50.GR_OIR_AB2)
     564#define VDC50GR_OIR_AB3 (VDC50.GR_OIR_AB3)
     565#define VDC50GR_OIR_AB7 (VDC50.GR_OIR_AB7)
     566#define VDC50GR_OIR_AB8 (VDC50.GR_OIR_AB8)
     567#define VDC50GR_OIR_AB9 (VDC50.GR_OIR_AB9)
     568#define VDC50GR_OIR_AB10 (VDC50.GR_OIR_AB10)
     569#define VDC50GR_OIR_AB11 (VDC50.GR_OIR_AB11)
     570#define VDC50GR_OIR_BASE (VDC50.GR_OIR_BASE)
     571#define VDC50GR_OIR_CLUT (VDC50.GR_OIR_CLUT)
     572#define VDC50GR_OIR_MON (VDC50.GR_OIR_MON)
     573#define VDC51INP_UPDATE (VDC51.INP_UPDATE)
     574#define VDC51INP_SEL_CNT (VDC51.INP_SEL_CNT)
     575#define VDC51INP_EXT_SYNC_CNT (VDC51.INP_EXT_SYNC_CNT)
     576#define VDC51INP_VSYNC_PH_ADJ (VDC51.INP_VSYNC_PH_ADJ)
     577#define VDC51INP_DLY_ADJ (VDC51.INP_DLY_ADJ)
     578#define VDC51IMGCNT_UPDATE (VDC51.IMGCNT_UPDATE)
     579#define VDC51IMGCNT_NR_CNT0 (VDC51.IMGCNT_NR_CNT0)
     580#define VDC51IMGCNT_NR_CNT1 (VDC51.IMGCNT_NR_CNT1)
     581#define VDC51IMGCNT_MTX_MODE (VDC51.IMGCNT_MTX_MODE)
     582#define VDC51IMGCNT_MTX_YG_ADJ0 (VDC51.IMGCNT_MTX_YG_ADJ0)
     583#define VDC51IMGCNT_MTX_YG_ADJ1 (VDC51.IMGCNT_MTX_YG_ADJ1)
     584#define VDC51IMGCNT_MTX_CBB_ADJ0 (VDC51.IMGCNT_MTX_CBB_ADJ0)
     585#define VDC51IMGCNT_MTX_CBB_ADJ1 (VDC51.IMGCNT_MTX_CBB_ADJ1)
     586#define VDC51IMGCNT_MTX_CRR_ADJ0 (VDC51.IMGCNT_MTX_CRR_ADJ0)
     587#define VDC51IMGCNT_MTX_CRR_ADJ1 (VDC51.IMGCNT_MTX_CRR_ADJ1)
     588#define VDC51IMGCNT_DRC_REG (VDC51.IMGCNT_DRC_REG)
     589#define VDC51SC0_SCL0_UPDATE (VDC51.SC0_SCL0_UPDATE)
     590#define VDC51SC0_SCL0_FRC1 (VDC51.SC0_SCL0_FRC1)
     591#define VDC51SC0_SCL0_FRC2 (VDC51.SC0_SCL0_FRC2)
     592#define VDC51SC0_SCL0_FRC3 (VDC51.SC0_SCL0_FRC3)
     593#define VDC51SC0_SCL0_FRC4 (VDC51.SC0_SCL0_FRC4)
     594#define VDC51SC0_SCL0_FRC5 (VDC51.SC0_SCL0_FRC5)
     595#define VDC51SC0_SCL0_FRC6 (VDC51.SC0_SCL0_FRC6)
     596#define VDC51SC0_SCL0_FRC7 (VDC51.SC0_SCL0_FRC7)
     597#define VDC51SC0_SCL0_FRC9 (VDC51.SC0_SCL0_FRC9)
     598#define VDC51SC0_SCL0_MON0 (VDC51.SC0_SCL0_MON0)
     599#define VDC51SC0_SCL0_INT (VDC51.SC0_SCL0_INT)
     600#define VDC51SC0_SCL0_DS1 (VDC51.SC0_SCL0_DS1)
     601#define VDC51SC0_SCL0_DS2 (VDC51.SC0_SCL0_DS2)
     602#define VDC51SC0_SCL0_DS3 (VDC51.SC0_SCL0_DS3)
     603#define VDC51SC0_SCL0_DS4 (VDC51.SC0_SCL0_DS4)
     604#define VDC51SC0_SCL0_DS5 (VDC51.SC0_SCL0_DS5)
     605#define VDC51SC0_SCL0_DS6 (VDC51.SC0_SCL0_DS6)
     606#define VDC51SC0_SCL0_DS7 (VDC51.SC0_SCL0_DS7)
     607#define VDC51SC0_SCL0_US1 (VDC51.SC0_SCL0_US1)
     608#define VDC51SC0_SCL0_US2 (VDC51.SC0_SCL0_US2)
     609#define VDC51SC0_SCL0_US3 (VDC51.SC0_SCL0_US3)
     610#define VDC51SC0_SCL0_US4 (VDC51.SC0_SCL0_US4)
     611#define VDC51SC0_SCL0_US5 (VDC51.SC0_SCL0_US5)
     612#define VDC51SC0_SCL0_US6 (VDC51.SC0_SCL0_US6)
     613#define VDC51SC0_SCL0_US7 (VDC51.SC0_SCL0_US7)
     614#define VDC51SC0_SCL0_US8 (VDC51.SC0_SCL0_US8)
     615#define VDC51SC0_SCL0_OVR1 (VDC51.SC0_SCL0_OVR1)
     616#define VDC51SC0_SCL1_UPDATE (VDC51.SC0_SCL1_UPDATE)
     617#define VDC51SC0_SCL1_WR1 (VDC51.SC0_SCL1_WR1)
     618#define VDC51SC0_SCL1_WR2 (VDC51.SC0_SCL1_WR2)
     619#define VDC51SC0_SCL1_WR3 (VDC51.SC0_SCL1_WR3)
     620#define VDC51SC0_SCL1_WR4 (VDC51.SC0_SCL1_WR4)
     621#define VDC51SC0_SCL1_WR5 (VDC51.SC0_SCL1_WR5)
     622#define VDC51SC0_SCL1_WR6 (VDC51.SC0_SCL1_WR6)
     623#define VDC51SC0_SCL1_WR7 (VDC51.SC0_SCL1_WR7)
     624#define VDC51SC0_SCL1_WR8 (VDC51.SC0_SCL1_WR8)
     625#define VDC51SC0_SCL1_WR9 (VDC51.SC0_SCL1_WR9)
     626#define VDC51SC0_SCL1_WR10 (VDC51.SC0_SCL1_WR10)
     627#define VDC51SC0_SCL1_WR11 (VDC51.SC0_SCL1_WR11)
     628#define VDC51SC0_SCL1_MON1 (VDC51.SC0_SCL1_MON1)
     629#define VDC51SC0_SCL1_PBUF0 (VDC51.SC0_SCL1_PBUF0)
     630#define VDC51SC0_SCL1_PBUF1 (VDC51.SC0_SCL1_PBUF1)
     631#define VDC51SC0_SCL1_PBUF2 (VDC51.SC0_SCL1_PBUF2)
     632#define VDC51SC0_SCL1_PBUF3 (VDC51.SC0_SCL1_PBUF3)
     633#define VDC51SC0_SCL1_PBUF_FLD (VDC51.SC0_SCL1_PBUF_FLD)
     634#define VDC51SC0_SCL1_PBUF_CNT (VDC51.SC0_SCL1_PBUF_CNT)
     635#define VDC51GR0_UPDATE (VDC51.GR0_UPDATE)
     636#define VDC51GR0_FLM_RD (VDC51.GR0_FLM_RD)
     637#define VDC51GR0_FLM1 (VDC51.GR0_FLM1)
     638#define VDC51GR0_FLM2 (VDC51.GR0_FLM2)
     639#define VDC51GR0_FLM3 (VDC51.GR0_FLM3)
     640#define VDC51GR0_FLM4 (VDC51.GR0_FLM4)
     641#define VDC51GR0_FLM5 (VDC51.GR0_FLM5)
     642#define VDC51GR0_FLM6 (VDC51.GR0_FLM6)
     643#define VDC51GR0_AB1 (VDC51.GR0_AB1)
     644#define VDC51GR0_AB2 (VDC51.GR0_AB2)
     645#define VDC51GR0_AB3 (VDC51.GR0_AB3)
     646#define VDC51GR0_AB7 (VDC51.GR0_AB7)
     647#define VDC51GR0_AB8 (VDC51.GR0_AB8)
     648#define VDC51GR0_AB9 (VDC51.GR0_AB9)
     649#define VDC51GR0_AB10 (VDC51.GR0_AB10)
     650#define VDC51GR0_AB11 (VDC51.GR0_AB11)
     651#define VDC51GR0_BASE (VDC51.GR0_BASE)
     652#define VDC51GR0_CLUT (VDC51.GR0_CLUT)
     653#define VDC51ADJ0_UPDATE (VDC51.ADJ0_UPDATE)
     654#define VDC51ADJ0_BKSTR_SET (VDC51.ADJ0_BKSTR_SET)
     655#define VDC51ADJ0_ENH_TIM1 (VDC51.ADJ0_ENH_TIM1)
     656#define VDC51ADJ0_ENH_TIM2 (VDC51.ADJ0_ENH_TIM2)
     657#define VDC51ADJ0_ENH_TIM3 (VDC51.ADJ0_ENH_TIM3)
     658#define VDC51ADJ0_ENH_SHP1 (VDC51.ADJ0_ENH_SHP1)
     659#define VDC51ADJ0_ENH_SHP2 (VDC51.ADJ0_ENH_SHP2)
     660#define VDC51ADJ0_ENH_SHP3 (VDC51.ADJ0_ENH_SHP3)
     661#define VDC51ADJ0_ENH_SHP4 (VDC51.ADJ0_ENH_SHP4)
     662#define VDC51ADJ0_ENH_SHP5 (VDC51.ADJ0_ENH_SHP5)
     663#define VDC51ADJ0_ENH_SHP6 (VDC51.ADJ0_ENH_SHP6)
     664#define VDC51ADJ0_ENH_LTI1 (VDC51.ADJ0_ENH_LTI1)
     665#define VDC51ADJ0_ENH_LTI2 (VDC51.ADJ0_ENH_LTI2)
     666#define VDC51ADJ0_MTX_MODE (VDC51.ADJ0_MTX_MODE)
     667#define VDC51ADJ0_MTX_YG_ADJ0 (VDC51.ADJ0_MTX_YG_ADJ0)
     668#define VDC51ADJ0_MTX_YG_ADJ1 (VDC51.ADJ0_MTX_YG_ADJ1)
     669#define VDC51ADJ0_MTX_CBB_ADJ0 (VDC51.ADJ0_MTX_CBB_ADJ0)
     670#define VDC51ADJ0_MTX_CBB_ADJ1 (VDC51.ADJ0_MTX_CBB_ADJ1)
     671#define VDC51ADJ0_MTX_CRR_ADJ0 (VDC51.ADJ0_MTX_CRR_ADJ0)
     672#define VDC51ADJ0_MTX_CRR_ADJ1 (VDC51.ADJ0_MTX_CRR_ADJ1)
     673#define VDC51GR2_UPDATE (VDC51.GR2_UPDATE)
     674#define VDC51GR2_FLM_RD (VDC51.GR2_FLM_RD)
     675#define VDC51GR2_FLM1 (VDC51.GR2_FLM1)
     676#define VDC51GR2_FLM2 (VDC51.GR2_FLM2)
     677#define VDC51GR2_FLM3 (VDC51.GR2_FLM3)
     678#define VDC51GR2_FLM4 (VDC51.GR2_FLM4)
     679#define VDC51GR2_FLM5 (VDC51.GR2_FLM5)
     680#define VDC51GR2_FLM6 (VDC51.GR2_FLM6)
     681#define VDC51GR2_AB1 (VDC51.GR2_AB1)
     682#define VDC51GR2_AB2 (VDC51.GR2_AB2)
     683#define VDC51GR2_AB3 (VDC51.GR2_AB3)
     684#define VDC51GR2_AB4 (VDC51.GR2_AB4)
     685#define VDC51GR2_AB5 (VDC51.GR2_AB5)
     686#define VDC51GR2_AB6 (VDC51.GR2_AB6)
     687#define VDC51GR2_AB7 (VDC51.GR2_AB7)
     688#define VDC51GR2_AB8 (VDC51.GR2_AB8)
     689#define VDC51GR2_AB9 (VDC51.GR2_AB9)
     690#define VDC51GR2_AB10 (VDC51.GR2_AB10)
     691#define VDC51GR2_AB11 (VDC51.GR2_AB11)
     692#define VDC51GR2_BASE (VDC51.GR2_BASE)
     693#define VDC51GR2_CLUT (VDC51.GR2_CLUT)
     694#define VDC51GR2_MON (VDC51.GR2_MON)
     695#define VDC51GR3_UPDATE (VDC51.GR3_UPDATE)
     696#define VDC51GR3_FLM_RD (VDC51.GR3_FLM_RD)
     697#define VDC51GR3_FLM1 (VDC51.GR3_FLM1)
     698#define VDC51GR3_FLM2 (VDC51.GR3_FLM2)
     699#define VDC51GR3_FLM3 (VDC51.GR3_FLM3)
     700#define VDC51GR3_FLM4 (VDC51.GR3_FLM4)
     701#define VDC51GR3_FLM5 (VDC51.GR3_FLM5)
     702#define VDC51GR3_FLM6 (VDC51.GR3_FLM6)
     703#define VDC51GR3_AB1 (VDC51.GR3_AB1)
     704#define VDC51GR3_AB2 (VDC51.GR3_AB2)
     705#define VDC51GR3_AB3 (VDC51.GR3_AB3)
     706#define VDC51GR3_AB4 (VDC51.GR3_AB4)
     707#define VDC51GR3_AB5 (VDC51.GR3_AB5)
     708#define VDC51GR3_AB6 (VDC51.GR3_AB6)
     709#define VDC51GR3_AB7 (VDC51.GR3_AB7)
     710#define VDC51GR3_AB8 (VDC51.GR3_AB8)
     711#define VDC51GR3_AB9 (VDC51.GR3_AB9)
     712#define VDC51GR3_AB10 (VDC51.GR3_AB10)
     713#define VDC51GR3_AB11 (VDC51.GR3_AB11)
     714#define VDC51GR3_BASE (VDC51.GR3_BASE)
     715#define VDC51GR3_CLUT_INT (VDC51.GR3_CLUT_INT)
     716#define VDC51GR3_MON (VDC51.GR3_MON)
     717#define VDC51GAM_G_UPDATE (VDC51.GAM_G_UPDATE)
     718#define VDC51GAM_SW (VDC51.GAM_SW)
     719#define VDC51GAM_G_LUT1 (VDC51.GAM_G_LUT1)
     720#define VDC51GAM_G_LUT2 (VDC51.GAM_G_LUT2)
     721#define VDC51GAM_G_LUT3 (VDC51.GAM_G_LUT3)
     722#define VDC51GAM_G_LUT4 (VDC51.GAM_G_LUT4)
     723#define VDC51GAM_G_LUT5 (VDC51.GAM_G_LUT5)
     724#define VDC51GAM_G_LUT6 (VDC51.GAM_G_LUT6)
     725#define VDC51GAM_G_LUT7 (VDC51.GAM_G_LUT7)
     726#define VDC51GAM_G_LUT8 (VDC51.GAM_G_LUT8)
     727#define VDC51GAM_G_LUT9 (VDC51.GAM_G_LUT9)
     728#define VDC51GAM_G_LUT10 (VDC51.GAM_G_LUT10)
     729#define VDC51GAM_G_LUT11 (VDC51.GAM_G_LUT11)
     730#define VDC51GAM_G_LUT12 (VDC51.GAM_G_LUT12)
     731#define VDC51GAM_G_LUT13 (VDC51.GAM_G_LUT13)
     732#define VDC51GAM_G_LUT14 (VDC51.GAM_G_LUT14)
     733#define VDC51GAM_G_LUT15 (VDC51.GAM_G_LUT15)
     734#define VDC51GAM_G_LUT16 (VDC51.GAM_G_LUT16)
     735#define VDC51GAM_G_AREA1 (VDC51.GAM_G_AREA1)
     736#define VDC51GAM_G_AREA2 (VDC51.GAM_G_AREA2)
     737#define VDC51GAM_G_AREA3 (VDC51.GAM_G_AREA3)
     738#define VDC51GAM_G_AREA4 (VDC51.GAM_G_AREA4)
     739#define VDC51GAM_G_AREA5 (VDC51.GAM_G_AREA5)
     740#define VDC51GAM_G_AREA6 (VDC51.GAM_G_AREA6)
     741#define VDC51GAM_G_AREA7 (VDC51.GAM_G_AREA7)
     742#define VDC51GAM_G_AREA8 (VDC51.GAM_G_AREA8)
     743#define VDC51GAM_B_UPDATE (VDC51.GAM_B_UPDATE)
     744#define VDC51GAM_B_LUT1 (VDC51.GAM_B_LUT1)
     745#define VDC51GAM_B_LUT2 (VDC51.GAM_B_LUT2)
     746#define VDC51GAM_B_LUT3 (VDC51.GAM_B_LUT3)
     747#define VDC51GAM_B_LUT4 (VDC51.GAM_B_LUT4)
     748#define VDC51GAM_B_LUT5 (VDC51.GAM_B_LUT5)
     749#define VDC51GAM_B_LUT6 (VDC51.GAM_B_LUT6)
     750#define VDC51GAM_B_LUT7 (VDC51.GAM_B_LUT7)
     751#define VDC51GAM_B_LUT8 (VDC51.GAM_B_LUT8)
     752#define VDC51GAM_B_LUT9 (VDC51.GAM_B_LUT9)
     753#define VDC51GAM_B_LUT10 (VDC51.GAM_B_LUT10)
     754#define VDC51GAM_B_LUT11 (VDC51.GAM_B_LUT11)
     755#define VDC51GAM_B_LUT12 (VDC51.GAM_B_LUT12)
     756#define VDC51GAM_B_LUT13 (VDC51.GAM_B_LUT13)
     757#define VDC51GAM_B_LUT14 (VDC51.GAM_B_LUT14)
     758#define VDC51GAM_B_LUT15 (VDC51.GAM_B_LUT15)
     759#define VDC51GAM_B_LUT16 (VDC51.GAM_B_LUT16)
     760#define VDC51GAM_B_AREA1 (VDC51.GAM_B_AREA1)
     761#define VDC51GAM_B_AREA2 (VDC51.GAM_B_AREA2)
     762#define VDC51GAM_B_AREA3 (VDC51.GAM_B_AREA3)
     763#define VDC51GAM_B_AREA4 (VDC51.GAM_B_AREA4)
     764#define VDC51GAM_B_AREA5 (VDC51.GAM_B_AREA5)
     765#define VDC51GAM_B_AREA6 (VDC51.GAM_B_AREA6)
     766#define VDC51GAM_B_AREA7 (VDC51.GAM_B_AREA7)
     767#define VDC51GAM_B_AREA8 (VDC51.GAM_B_AREA8)
     768#define VDC51GAM_R_UPDATE (VDC51.GAM_R_UPDATE)
     769#define VDC51GAM_R_LUT1 (VDC51.GAM_R_LUT1)
     770#define VDC51GAM_R_LUT2 (VDC51.GAM_R_LUT2)
     771#define VDC51GAM_R_LUT3 (VDC51.GAM_R_LUT3)
     772#define VDC51GAM_R_LUT4 (VDC51.GAM_R_LUT4)
     773#define VDC51GAM_R_LUT5 (VDC51.GAM_R_LUT5)
     774#define VDC51GAM_R_LUT6 (VDC51.GAM_R_LUT6)
     775#define VDC51GAM_R_LUT7 (VDC51.GAM_R_LUT7)
     776#define VDC51GAM_R_LUT8 (VDC51.GAM_R_LUT8)
     777#define VDC51GAM_R_LUT9 (VDC51.GAM_R_LUT9)
     778#define VDC51GAM_R_LUT10 (VDC51.GAM_R_LUT10)
     779#define VDC51GAM_R_LUT11 (VDC51.GAM_R_LUT11)
     780#define VDC51GAM_R_LUT12 (VDC51.GAM_R_LUT12)
     781#define VDC51GAM_R_LUT13 (VDC51.GAM_R_LUT13)
     782#define VDC51GAM_R_LUT14 (VDC51.GAM_R_LUT14)
     783#define VDC51GAM_R_LUT15 (VDC51.GAM_R_LUT15)
     784#define VDC51GAM_R_LUT16 (VDC51.GAM_R_LUT16)
     785#define VDC51GAM_R_AREA1 (VDC51.GAM_R_AREA1)
     786#define VDC51GAM_R_AREA2 (VDC51.GAM_R_AREA2)
     787#define VDC51GAM_R_AREA3 (VDC51.GAM_R_AREA3)
     788#define VDC51GAM_R_AREA4 (VDC51.GAM_R_AREA4)
     789#define VDC51GAM_R_AREA5 (VDC51.GAM_R_AREA5)
     790#define VDC51GAM_R_AREA6 (VDC51.GAM_R_AREA6)
     791#define VDC51GAM_R_AREA7 (VDC51.GAM_R_AREA7)
     792#define VDC51GAM_R_AREA8 (VDC51.GAM_R_AREA8)
     793#define VDC51TCON_UPDATE (VDC51.TCON_UPDATE)
     794#define VDC51TCON_TIM (VDC51.TCON_TIM)
     795#define VDC51TCON_TIM_STVA1 (VDC51.TCON_TIM_STVA1)
     796#define VDC51TCON_TIM_STVA2 (VDC51.TCON_TIM_STVA2)
     797#define VDC51TCON_TIM_STVB1 (VDC51.TCON_TIM_STVB1)
     798#define VDC51TCON_TIM_STVB2 (VDC51.TCON_TIM_STVB2)
     799#define VDC51TCON_TIM_STH1 (VDC51.TCON_TIM_STH1)
     800#define VDC51TCON_TIM_STH2 (VDC51.TCON_TIM_STH2)
     801#define VDC51TCON_TIM_STB1 (VDC51.TCON_TIM_STB1)
     802#define VDC51TCON_TIM_STB2 (VDC51.TCON_TIM_STB2)
     803#define VDC51TCON_TIM_CPV1 (VDC51.TCON_TIM_CPV1)
     804#define VDC51TCON_TIM_CPV2 (VDC51.TCON_TIM_CPV2)
     805#define VDC51TCON_TIM_POLA1 (VDC51.TCON_TIM_POLA1)
     806#define VDC51TCON_TIM_POLA2 (VDC51.TCON_TIM_POLA2)
     807#define VDC51TCON_TIM_POLB1 (VDC51.TCON_TIM_POLB1)
     808#define VDC51TCON_TIM_POLB2 (VDC51.TCON_TIM_POLB2)
     809#define VDC51TCON_TIM_DE (VDC51.TCON_TIM_DE)
     810#define VDC51OUT_UPDATE (VDC51.OUT_UPDATE)
     811#define VDC51OUT_SET (VDC51.OUT_SET)
     812#define VDC51OUT_BRIGHT1 (VDC51.OUT_BRIGHT1)
     813#define VDC51OUT_BRIGHT2 (VDC51.OUT_BRIGHT2)
     814#define VDC51OUT_CONTRAST (VDC51.OUT_CONTRAST)
     815#define VDC51OUT_PDTHA (VDC51.OUT_PDTHA)
     816#define VDC51OUT_CLK_PHASE (VDC51.OUT_CLK_PHASE)
     817#define VDC51SYSCNT_INT1 (VDC51.SYSCNT_INT1)
     818#define VDC51SYSCNT_INT2 (VDC51.SYSCNT_INT2)
     819#define VDC51SYSCNT_INT3 (VDC51.SYSCNT_INT3)
     820#define VDC51SYSCNT_INT4 (VDC51.SYSCNT_INT4)
     821#define VDC51SYSCNT_INT5 (VDC51.SYSCNT_INT5)
     822#define VDC51SYSCNT_INT6 (VDC51.SYSCNT_INT6)
     823#define VDC51SYSCNT_PANEL_CLK (VDC51.SYSCNT_PANEL_CLK)
     824#define VDC51SYSCNT_CLUT (VDC51.SYSCNT_CLUT)
     825#define VDC51SC1_SCL0_UPDATE (VDC51.SC1_SCL0_UPDATE)
     826#define VDC51SC1_SCL0_FRC1 (VDC51.SC1_SCL0_FRC1)
     827#define VDC51SC1_SCL0_FRC2 (VDC51.SC1_SCL0_FRC2)
     828#define VDC51SC1_SCL0_FRC3 (VDC51.SC1_SCL0_FRC3)
     829#define VDC51SC1_SCL0_FRC4 (VDC51.SC1_SCL0_FRC4)
     830#define VDC51SC1_SCL0_FRC5 (VDC51.SC1_SCL0_FRC5)
     831#define VDC51SC1_SCL0_FRC6 (VDC51.SC1_SCL0_FRC6)
     832#define VDC51SC1_SCL0_FRC7 (VDC51.SC1_SCL0_FRC7)
     833#define VDC51SC1_SCL0_FRC9 (VDC51.SC1_SCL0_FRC9)
     834#define VDC51SC1_SCL0_MON0 (VDC51.SC1_SCL0_MON0)
     835#define VDC51SC1_SCL0_INT (VDC51.SC1_SCL0_INT)
     836#define VDC51SC1_SCL0_DS1 (VDC51.SC1_SCL0_DS1)
     837#define VDC51SC1_SCL0_DS2 (VDC51.SC1_SCL0_DS2)
     838#define VDC51SC1_SCL0_DS3 (VDC51.SC1_SCL0_DS3)
     839#define VDC51SC1_SCL0_DS4 (VDC51.SC1_SCL0_DS4)
     840#define VDC51SC1_SCL0_DS5 (VDC51.SC1_SCL0_DS5)
     841#define VDC51SC1_SCL0_DS6 (VDC51.SC1_SCL0_DS6)
     842#define VDC51SC1_SCL0_DS7 (VDC51.SC1_SCL0_DS7)
     843#define VDC51SC1_SCL0_US1 (VDC51.SC1_SCL0_US1)
     844#define VDC51SC1_SCL0_US2 (VDC51.SC1_SCL0_US2)
     845#define VDC51SC1_SCL0_US3 (VDC51.SC1_SCL0_US3)
     846#define VDC51SC1_SCL0_US4 (VDC51.SC1_SCL0_US4)
     847#define VDC51SC1_SCL0_US5 (VDC51.SC1_SCL0_US5)
     848#define VDC51SC1_SCL0_US6 (VDC51.SC1_SCL0_US6)
     849#define VDC51SC1_SCL0_US7 (VDC51.SC1_SCL0_US7)
     850#define VDC51SC1_SCL0_US8 (VDC51.SC1_SCL0_US8)
     851#define VDC51SC1_SCL0_OVR1 (VDC51.SC1_SCL0_OVR1)
     852#define VDC51SC1_SCL1_UPDATE (VDC51.SC1_SCL1_UPDATE)
     853#define VDC51SC1_SCL1_WR1 (VDC51.SC1_SCL1_WR1)
     854#define VDC51SC1_SCL1_WR2 (VDC51.SC1_SCL1_WR2)
     855#define VDC51SC1_SCL1_WR3 (VDC51.SC1_SCL1_WR3)
     856#define VDC51SC1_SCL1_WR4 (VDC51.SC1_SCL1_WR4)
     857#define VDC51SC1_SCL1_WR5 (VDC51.SC1_SCL1_WR5)
     858#define VDC51SC1_SCL1_WR6 (VDC51.SC1_SCL1_WR6)
     859#define VDC51SC1_SCL1_WR7 (VDC51.SC1_SCL1_WR7)
     860#define VDC51SC1_SCL1_WR8 (VDC51.SC1_SCL1_WR8)
     861#define VDC51SC1_SCL1_WR9 (VDC51.SC1_SCL1_WR9)
     862#define VDC51SC1_SCL1_WR10 (VDC51.SC1_SCL1_WR10)
     863#define VDC51SC1_SCL1_WR11 (VDC51.SC1_SCL1_WR11)
     864#define VDC51SC1_SCL1_MON1 (VDC51.SC1_SCL1_MON1)
     865#define VDC51SC1_SCL1_PBUF0 (VDC51.SC1_SCL1_PBUF0)
     866#define VDC51SC1_SCL1_PBUF1 (VDC51.SC1_SCL1_PBUF1)
     867#define VDC51SC1_SCL1_PBUF2 (VDC51.SC1_SCL1_PBUF2)
     868#define VDC51SC1_SCL1_PBUF3 (VDC51.SC1_SCL1_PBUF3)
     869#define VDC51SC1_SCL1_PBUF_FLD (VDC51.SC1_SCL1_PBUF_FLD)
     870#define VDC51SC1_SCL1_PBUF_CNT (VDC51.SC1_SCL1_PBUF_CNT)
     871#define VDC51GR1_UPDATE (VDC51.GR1_UPDATE)
     872#define VDC51GR1_FLM_RD (VDC51.GR1_FLM_RD)
     873#define VDC51GR1_FLM1 (VDC51.GR1_FLM1)
     874#define VDC51GR1_FLM2 (VDC51.GR1_FLM2)
     875#define VDC51GR1_FLM3 (VDC51.GR1_FLM3)
     876#define VDC51GR1_FLM4 (VDC51.GR1_FLM4)
     877#define VDC51GR1_FLM5 (VDC51.GR1_FLM5)
     878#define VDC51GR1_FLM6 (VDC51.GR1_FLM6)
     879#define VDC51GR1_AB1 (VDC51.GR1_AB1)
     880#define VDC51GR1_AB2 (VDC51.GR1_AB2)
     881#define VDC51GR1_AB3 (VDC51.GR1_AB3)
     882#define VDC51GR1_AB4 (VDC51.GR1_AB4)
     883#define VDC51GR1_AB5 (VDC51.GR1_AB5)
     884#define VDC51GR1_AB6 (VDC51.GR1_AB6)
     885#define VDC51GR1_AB7 (VDC51.GR1_AB7)
     886#define VDC51GR1_AB8 (VDC51.GR1_AB8)
     887#define VDC51GR1_AB9 (VDC51.GR1_AB9)
     888#define VDC51GR1_AB10 (VDC51.GR1_AB10)
     889#define VDC51GR1_AB11 (VDC51.GR1_AB11)
     890#define VDC51GR1_BASE (VDC51.GR1_BASE)
     891#define VDC51GR1_CLUT (VDC51.GR1_CLUT)
     892#define VDC51GR1_MON (VDC51.GR1_MON)
     893#define VDC51ADJ1_UPDATE (VDC51.ADJ1_UPDATE)
     894#define VDC51ADJ1_BKSTR_SET (VDC51.ADJ1_BKSTR_SET)
     895#define VDC51ADJ1_ENH_TIM1 (VDC51.ADJ1_ENH_TIM1)
     896#define VDC51ADJ1_ENH_TIM2 (VDC51.ADJ1_ENH_TIM2)
     897#define VDC51ADJ1_ENH_TIM3 (VDC51.ADJ1_ENH_TIM3)
     898#define VDC51ADJ1_ENH_SHP1 (VDC51.ADJ1_ENH_SHP1)
     899#define VDC51ADJ1_ENH_SHP2 (VDC51.ADJ1_ENH_SHP2)
     900#define VDC51ADJ1_ENH_SHP3 (VDC51.ADJ1_ENH_SHP3)
     901#define VDC51ADJ1_ENH_SHP4 (VDC51.ADJ1_ENH_SHP4)
     902#define VDC51ADJ1_ENH_SHP5 (VDC51.ADJ1_ENH_SHP5)
     903#define VDC51ADJ1_ENH_SHP6 (VDC51.ADJ1_ENH_SHP6)
     904#define VDC51ADJ1_ENH_LTI1 (VDC51.ADJ1_ENH_LTI1)
     905#define VDC51ADJ1_ENH_LTI2 (VDC51.ADJ1_ENH_LTI2)
     906#define VDC51ADJ1_MTX_MODE (VDC51.ADJ1_MTX_MODE)
     907#define VDC51ADJ1_MTX_YG_ADJ0 (VDC51.ADJ1_MTX_YG_ADJ0)
     908#define VDC51ADJ1_MTX_YG_ADJ1 (VDC51.ADJ1_MTX_YG_ADJ1)
     909#define VDC51ADJ1_MTX_CBB_ADJ0 (VDC51.ADJ1_MTX_CBB_ADJ0)
     910#define VDC51ADJ1_MTX_CBB_ADJ1 (VDC51.ADJ1_MTX_CBB_ADJ1)
     911#define VDC51ADJ1_MTX_CRR_ADJ0 (VDC51.ADJ1_MTX_CRR_ADJ0)
     912#define VDC51ADJ1_MTX_CRR_ADJ1 (VDC51.ADJ1_MTX_CRR_ADJ1)
     913#define VDC51GR_VIN_UPDATE (VDC51.GR_VIN_UPDATE)
     914#define VDC51GR_VIN_AB1 (VDC51.GR_VIN_AB1)
     915#define VDC51GR_VIN_AB2 (VDC51.GR_VIN_AB2)
     916#define VDC51GR_VIN_AB3 (VDC51.GR_VIN_AB3)
     917#define VDC51GR_VIN_AB4 (VDC51.GR_VIN_AB4)
     918#define VDC51GR_VIN_AB5 (VDC51.GR_VIN_AB5)
     919#define VDC51GR_VIN_AB6 (VDC51.GR_VIN_AB6)
     920#define VDC51GR_VIN_AB7 (VDC51.GR_VIN_AB7)
     921#define VDC51GR_VIN_BASE (VDC51.GR_VIN_BASE)
     922#define VDC51GR_VIN_MON (VDC51.GR_VIN_MON)
     923#define VDC51OIR_SCL0_UPDATE (VDC51.OIR_SCL0_UPDATE)
     924#define VDC51OIR_SCL0_FRC1 (VDC51.OIR_SCL0_FRC1)
     925#define VDC51OIR_SCL0_FRC2 (VDC51.OIR_SCL0_FRC2)
     926#define VDC51OIR_SCL0_FRC3 (VDC51.OIR_SCL0_FRC3)
     927#define VDC51OIR_SCL0_FRC4 (VDC51.OIR_SCL0_FRC4)
     928#define VDC51OIR_SCL0_FRC5 (VDC51.OIR_SCL0_FRC5)
     929#define VDC51OIR_SCL0_FRC6 (VDC51.OIR_SCL0_FRC6)
     930#define VDC51OIR_SCL0_FRC7 (VDC51.OIR_SCL0_FRC7)
     931#define VDC51OIR_SCL0_DS1 (VDC51.OIR_SCL0_DS1)
     932#define VDC51OIR_SCL0_DS2 (VDC51.OIR_SCL0_DS2)
     933#define VDC51OIR_SCL0_DS3 (VDC51.OIR_SCL0_DS3)
     934#define VDC51OIR_SCL0_DS7 (VDC51.OIR_SCL0_DS7)
     935#define VDC51OIR_SCL0_US1 (VDC51.OIR_SCL0_US1)
     936#define VDC51OIR_SCL0_US2 (VDC51.OIR_SCL0_US2)
     937#define VDC51OIR_SCL0_US3 (VDC51.OIR_SCL0_US3)
     938#define VDC51OIR_SCL0_US8 (VDC51.OIR_SCL0_US8)
     939#define VDC51OIR_SCL0_OVR1 (VDC51.OIR_SCL0_OVR1)
     940#define VDC51OIR_SCL1_UPDATE (VDC51.OIR_SCL1_UPDATE)
     941#define VDC51OIR_SCL1_WR1 (VDC51.OIR_SCL1_WR1)
     942#define VDC51OIR_SCL1_WR2 (VDC51.OIR_SCL1_WR2)
     943#define VDC51OIR_SCL1_WR3 (VDC51.OIR_SCL1_WR3)
     944#define VDC51OIR_SCL1_WR4 (VDC51.OIR_SCL1_WR4)
     945#define VDC51OIR_SCL1_WR5 (VDC51.OIR_SCL1_WR5)
     946#define VDC51OIR_SCL1_WR6 (VDC51.OIR_SCL1_WR6)
     947#define VDC51OIR_SCL1_WR7 (VDC51.OIR_SCL1_WR7)
     948#define VDC51GR_OIR_UPDATE (VDC51.GR_OIR_UPDATE)
     949#define VDC51GR_OIR_FLM_RD (VDC51.GR_OIR_FLM_RD)
     950#define VDC51GR_OIR_FLM1 (VDC51.GR_OIR_FLM1)
     951#define VDC51GR_OIR_FLM2 (VDC51.GR_OIR_FLM2)
     952#define VDC51GR_OIR_FLM3 (VDC51.GR_OIR_FLM3)
     953#define VDC51GR_OIR_FLM4 (VDC51.GR_OIR_FLM4)
     954#define VDC51GR_OIR_FLM5 (VDC51.GR_OIR_FLM5)
     955#define VDC51GR_OIR_FLM6 (VDC51.GR_OIR_FLM6)
     956#define VDC51GR_OIR_AB1 (VDC51.GR_OIR_AB1)
     957#define VDC51GR_OIR_AB2 (VDC51.GR_OIR_AB2)
     958#define VDC51GR_OIR_AB3 (VDC51.GR_OIR_AB3)
     959#define VDC51GR_OIR_AB7 (VDC51.GR_OIR_AB7)
     960#define VDC51GR_OIR_AB8 (VDC51.GR_OIR_AB8)
     961#define VDC51GR_OIR_AB9 (VDC51.GR_OIR_AB9)
     962#define VDC51GR_OIR_AB10 (VDC51.GR_OIR_AB10)
     963#define VDC51GR_OIR_AB11 (VDC51.GR_OIR_AB11)
     964#define VDC51GR_OIR_BASE (VDC51.GR_OIR_BASE)
     965#define VDC51GR_OIR_CLUT (VDC51.GR_OIR_CLUT)
     966#define VDC51GR_OIR_MON (VDC51.GR_OIR_MON)
     967
     968#define VDC5_IMGCNT_NR_CNT0_COUNT (2)
     969#define VDC5_SC0_SCL0_FRC1_COUNT (7)
     970#define VDC5_SC0_SCL0_DS1_COUNT (7)
     971#define VDC5_SC0_SCL0_US1_COUNT (8)
     972#define VDC5_SC0_SCL1_WR1_COUNT (4)
     973#define VDC5_SC0_SCL1_PBUF0_COUNT (4)
     974#define VDC5_GR0_FLM1_COUNT (6)
     975#define VDC5_GR0_AB1_COUNT (3)
     976#define VDC5_ADJ0_ENH_TIM1_COUNT (3)
     977#define VDC5_ADJ0_ENH_SHP1_COUNT (6)
     978#define VDC5_ADJ0_ENH_LTI1_COUNT (2)
     979#define VDC5_GR2_FLM1_COUNT (6)
     980#define VDC5_GR2_AB1_COUNT (3)
     981#define VDC5_GR3_FLM1_COUNT (6)
     982#define VDC5_GR3_AB1_COUNT (3)
     983#define VDC5_GAM_G_LUT1_COUNT (16)
     984#define VDC5_GAM_G_AREA1_COUNT (8)
     985#define VDC5_GAM_B_LUT1_COUNT (16)
     986#define VDC5_GAM_B_AREA1_COUNT (8)
     987#define VDC5_GAM_R_LUT1_COUNT (16)
     988#define VDC5_GAM_R_AREA1_COUNT (8)
     989#define VDC5_TCON_TIM_STVA1_COUNT (2)
     990#define VDC5_TCON_TIM_STVB1_COUNT (2)
     991#define VDC5_TCON_TIM_STH1_COUNT (2)
     992#define VDC5_TCON_TIM_STB1_COUNT (2)
     993#define VDC5_TCON_TIM_CPV1_COUNT (2)
     994#define VDC5_TCON_TIM_POLA1_COUNT (2)
     995#define VDC5_TCON_TIM_POLB1_COUNT (2)
     996#define VDC5_OUT_BRIGHT1_COUNT (2)
     997#define VDC5_SYSCNT_INT1_COUNT (6)
     998#define VDC5_SC1_SCL0_FRC1_COUNT (7)
     999#define VDC5_SC1_SC1_SCL0_DS1_COUNT (7)
     1000#define VDC5_SC1_SC1_SCL0_US1_COUNT (8)
     1001#define VDC5_SC1_SCL1_WR1_COUNT (4)
     1002#define VDC5_SC1_SCL1_PBUF0_COUNT (4)
     1003#define VDC5_GR1_FLM1_COUNT (6)
     1004#define VDC5_GR1_AB1_COUNT (3)
     1005#define VDC5_ADJ1_ENH_TIM1_COUNT (3)
     1006#define VDC5_ADJ1_ENH_SHP1_COUNT (6)
     1007#define VDC5_ADJ1_ENH_LTI1_COUNT (2)
     1008#define VDC5_GR_VIN_AB1_COUNT (7)
     1009#define VDC5_OIR_SCL0_FRC1_COUNT (7)
     1010#define VDC5_OIR_SCL0_DS1_COUNT (3)
     1011#define VDC5_OIR_SCL1_WR1_COUNT (4)
     1012#define VDC5_GR_OIR_FLM1_COUNT (6)
     1013#define VDC5_GR_OIR_AB1_COUNT (3)
     1014
     1015
     1016typedef struct st_vdc5
     1017{
     1018                                                           /* VDC5             */
    361019    volatile uint32_t  INP_UPDATE;                             /*  INP_UPDATE      */
    371020    volatile uint32_t  INP_SEL_CNT;                            /*  INP_SEL_CNT     */
    … …  
    411024    volatile uint8_t   dummy1[108];                            /*                  */
    421025    volatile uint32_t  IMGCNT_UPDATE;                          /*  IMGCNT_UPDATE   */
    43 #define VDC5_IMGCNT_NR_CNT0_COUNT 2
     1026
     1027/* #define VDC5_IMGCNT_NR_CNT0_COUNT (2) */
    441028    volatile uint32_t  IMGCNT_NR_CNT0;                         /*  IMGCNT_NR_CNT0  */
    451029    volatile uint32_t  IMGCNT_NR_CNT1;                         /*  IMGCNT_NR_CNT1  */
    … …  
    551039    volatile uint32_t  IMGCNT_DRC_REG;                         /*  IMGCNT_DRC_REG  */
    561040    volatile uint8_t   dummy4[60];                             /*                  */
     1041
    571042/* start of struct st_vdc5_from_sc0_scl0_update */
    581043    volatile uint32_t  SC0_SCL0_UPDATE;                        /*  SC0_SCL0_UPDATE */
    59 #define VDC5_SC0_SCL0_FRC1_COUNT 7
     1044
     1045/* #define VDC5_SC0_SCL0_FRC1_COUNT (7) */
    601046    volatile uint32_t  SC0_SCL0_FRC1;                          /*  SC0_SCL0_FRC1   */
    611047    volatile uint32_t  SC0_SCL0_FRC2;                          /*  SC0_SCL0_FRC2   */
    … …  
    691055    volatile uint16_t SC0_SCL0_MON0;                          /*  SC0_SCL0_MON0   */
    701056    volatile uint16_t SC0_SCL0_INT;                           /*  SC0_SCL0_INT    */
    71 #define VDC5_SC0_SCL0_DS1_COUNT 7
     1057
     1058/* #define VDC5_SC0_SCL0_DS1_COUNT (7) */
    721059    volatile uint32_t  SC0_SCL0_DS1;                           /*  SC0_SCL0_DS1    */
    731060    volatile uint32_t  SC0_SCL0_DS2;                           /*  SC0_SCL0_DS2    */
    … …  
    771064    volatile uint32_t  SC0_SCL0_DS6;                           /*  SC0_SCL0_DS6    */
    781065    volatile uint32_t  SC0_SCL0_DS7;                           /*  SC0_SCL0_DS7    */
    79 #define VDC5_SC0_SCL0_US1_COUNT 8
     1066
     1067/* #define VDC5_SC0_SCL0_US1_COUNT (8) */
    801068    volatile uint32_t  SC0_SCL0_US1;                           /*  SC0_SCL0_US1    */
    811069    volatile uint32_t  SC0_SCL0_US2;                           /*  SC0_SCL0_US2    */
    … …  
    911079    volatile uint32_t  SC0_SCL1_UPDATE;                        /*  SC0_SCL1_UPDATE */
    921080    volatile uint8_t   dummy8[4];                              /*                  */
    93 #define VDC5_SC0_SCL1_WR1_COUNT 4
     1081
     1082/* #define VDC5_SC0_SCL1_WR1_COUNT (4) */
    941083    volatile uint32_t  SC0_SCL1_WR1;                           /*  SC0_SCL1_WR1    */
    951084    volatile uint32_t  SC0_SCL1_WR2;                           /*  SC0_SCL1_WR2    */
    … …  
    1031092    volatile uint32_t  SC0_SCL1_WR9;                           /*  SC0_SCL1_WR9    */
    1041093    volatile uint32_t  SC0_SCL1_WR10;                          /*  SC0_SCL1_WR10   */
     1094
    1051095/* end of struct st_vdc5_from_sc0_scl0_update */
    1061096    volatile uint32_t  SC0_SCL1_WR11;                          /*  SC0_SCL1_WR11   */
    1071097    volatile uint32_t  SC0_SCL1_MON1;                          /*  SC0_SCL1_MON1   */
     1098
    1081099/* start of struct st_vdc5_from_sc0_scl1_pbuf0 */
    109 #define VDC5_SC0_SCL1_PBUF0_COUNT 4
     1100
     1101/* #define VDC5_SC0_SCL1_PBUF0_COUNT (4) */
    1101102    volatile uint32_t  SC0_SCL1_PBUF0;                         /*  SC0_SCL1_PBUF0  */
    1111103    volatile uint32_t  SC0_SCL1_PBUF1;                         /*  SC0_SCL1_PBUF1  */
    … …  
    1141106    volatile uint32_t  SC0_SCL1_PBUF_FLD;                      /*  SC0_SCL1_PBUF_FLD */
    1151107    volatile uint32_t  SC0_SCL1_PBUF_CNT;                      /*  SC0_SCL1_PBUF_CNT */
     1108
    1161109/* end of struct st_vdc5_from_sc0_scl1_pbuf0 */
    1171110    volatile uint8_t   dummy10[44];                            /*                  */
     1111
    1181112/* start of struct st_vdc5_from_gr0_update */
    1191113    volatile uint32_t  GR0_UPDATE;                             /*  GR0_UPDATE      */
    1201114    volatile uint32_t  GR0_FLM_RD;                             /*  GR0_FLM_RD      */
    121 #define VDC5_GR0_FLM1_COUNT 6
     1115
     1116/* #define VDC5_GR0_FLM1_COUNT (6) */
    1221117    volatile uint32_t  GR0_FLM1;                               /*  GR0_FLM1        */
    1231118    volatile uint32_t  GR0_FLM2;                               /*  GR0_FLM2        */
    … …  
    1261121    volatile uint32_t  GR0_FLM5;                               /*  GR0_FLM5        */
    1271122    volatile uint32_t  GR0_FLM6;                               /*  GR0_FLM6        */
    128 #define VDC5_GR0_AB1_COUNT 3
     1123
     1124/* #define VDC5_GR0_AB1_COUNT (3) */
    1291125    volatile uint32_t  GR0_AB1;                                /*  GR0_AB1         */
    1301126    volatile uint32_t  GR0_AB2;                                /*  GR0_AB2         */
    1311127    volatile uint32_t  GR0_AB3;                                /*  GR0_AB3         */
     1128
    1321129/* end of struct st_vdc5_from_gr0_update */
    1331130    volatile uint8_t   dummy11[12];                            /*                  */
     1131
    1341132/* start of struct st_vdc5_from_gr0_ab7 */
    1351133    volatile uint32_t  GR0_AB7;                                /*  GR0_AB7         */
    … …  
    1391137    volatile uint32_t  GR0_AB11;                               /*  GR0_AB11        */
    1401138    volatile uint32_t  GR0_BASE;                               /*  GR0_BASE        */
     1139
    1411140/* end of struct st_vdc5_from_gr0_ab7 */
    1421141    volatile uint32_t  GR0_CLUT;                               /*  GR0_CLUT        */
    1431142    volatile uint8_t   dummy12[44];                            /*                  */
     1143
    1441144/* start of struct st_vdc5_from_adj0_update */
    1451145    volatile uint32_t  ADJ0_UPDATE;                            /*  ADJ0_UPDATE     */
    1461146    volatile uint32_t  ADJ0_BKSTR_SET;                         /*  ADJ0_BKSTR_SET  */
    147 #define VDC5_ADJ0_ENH_TIM1_COUNT 3
     1147
     1148/* #define VDC5_ADJ0_ENH_TIM1_COUNT (3) */
    1481149    volatile uint32_t  ADJ0_ENH_TIM1;                          /*  ADJ0_ENH_TIM1   */
    1491150    volatile uint32_t  ADJ0_ENH_TIM2;                          /*  ADJ0_ENH_TIM2   */
    1501151    volatile uint32_t  ADJ0_ENH_TIM3;                          /*  ADJ0_ENH_TIM3   */
    151 #define VDC5_ADJ0_ENH_SHP1_COUNT 6
     1152
     1153/* #define VDC5_ADJ0_ENH_SHP1_COUNT (6) */
    1521154    volatile uint32_t  ADJ0_ENH_SHP1;                          /*  ADJ0_ENH_SHP1   */
    1531155    volatile uint32_t  ADJ0_ENH_SHP2;                          /*  ADJ0_ENH_SHP2   */
    … …  
    1561158    volatile uint32_t  ADJ0_ENH_SHP5;                          /*  ADJ0_ENH_SHP5   */
    1571159    volatile uint32_t  ADJ0_ENH_SHP6;                          /*  ADJ0_ENH_SHP6   */
    158 #define VDC5_ADJ0_ENH_LTI1_COUNT 2
     1160
     1161/* #define VDC5_ADJ0_ENH_LTI1_COUNT (2) */
    1591162    volatile uint32_t  ADJ0_ENH_LTI1;                          /*  ADJ0_ENH_LTI1   */
    1601163    volatile uint32_t  ADJ0_ENH_LTI2;                          /*  ADJ0_ENH_LTI2   */
    … …  
    1661169    volatile uint32_t  ADJ0_MTX_CRR_ADJ0;                      /*  ADJ0_MTX_CRR_ADJ0 */
    1671170    volatile uint32_t  ADJ0_MTX_CRR_ADJ1;                      /*  ADJ0_MTX_CRR_ADJ1 */
     1171
    1681172/* end of struct st_vdc5_from_adj0_update */
    1691173    volatile uint8_t   dummy13[48];                            /*                  */
     1174
    1701175/* start of struct st_vdc5_from_gr0_update */
    1711176    volatile uint32_t  GR2_UPDATE;                             /*  GR2_UPDATE      */
    1721177    volatile uint32_t  GR2_FLM_RD;                             /*  GR2_FLM_RD      */
    173 #define VDC5_GR2_FLM1_COUNT 6
     1178
     1179/* #define VDC5_GR2_FLM1_COUNT (6) */
    1741180    volatile uint32_t  GR2_FLM1;                               /*  GR2_FLM1        */
    1751181    volatile uint32_t  GR2_FLM2;                               /*  GR2_FLM2        */
    … …  
    1781184    volatile uint32_t  GR2_FLM5;                               /*  GR2_FLM5        */
    1791185    volatile uint32_t  GR2_FLM6;                               /*  GR2_FLM6        */
    180 #define VDC5_GR2_AB1_COUNT 3
     1186
     1187/* #define VDC5_GR2_AB1_COUNT (3) */
    1811188    volatile uint32_t  GR2_AB1;                                /*  GR2_AB1         */
    1821189    volatile uint32_t  GR2_AB2;                                /*  GR2_AB2         */
    1831190    volatile uint32_t  GR2_AB3;                                /*  GR2_AB3         */
     1191
    1841192/* end of struct st_vdc5_from_gr0_update */
    1851193    volatile uint32_t  GR2_AB4;                                /*  GR2_AB4         */
    1861194    volatile uint32_t  GR2_AB5;                                /*  GR2_AB5         */
    1871195    volatile uint32_t  GR2_AB6;                                /*  GR2_AB6         */
     1196
    1881197/* start of struct st_vdc5_from_gr0_ab7 */
    1891198    volatile uint32_t  GR2_AB7;                                /*  GR2_AB7         */
    … …  
    1931202    volatile uint32_t  GR2_AB11;                               /*  GR2_AB11        */
    1941203    volatile uint32_t  GR2_BASE;                               /*  GR2_BASE        */
     1204
    1951205/* end of struct st_vdc5_from_gr0_ab7 */
    1961206    volatile uint32_t  GR2_CLUT;                               /*  GR2_CLUT        */
    1971207    volatile uint32_t  GR2_MON;                                /*  GR2_MON         */
    1981208    volatile uint8_t   dummy14[40];                            /*                  */
     1209
    1991210/* start of struct st_vdc5_from_gr0_update */
    2001211    volatile uint32_t  GR3_UPDATE;                             /*  GR3_UPDATE      */
    2011212    volatile uint32_t  GR3_FLM_RD;                             /*  GR3_FLM_RD      */
    202 #define VDC5_GR3_FLM1_COUNT 6
     1213
     1214/* #define VDC5_GR3_FLM1_COUNT (6) */
    2031215    volatile uint32_t  GR3_FLM1;                               /*  GR3_FLM1        */
    2041216    volatile uint32_t  GR3_FLM2;                               /*  GR3_FLM2        */
    … …  
    2071219    volatile uint32_t  GR3_FLM5;                               /*  GR3_FLM5        */
    2081220    volatile uint32_t  GR3_FLM6;                               /*  GR3_FLM6        */
    209 #define VDC5_GR3_AB1_COUNT 3
     1221
     1222/* #define VDC5_GR3_AB1_COUNT (3) */
    2101223    volatile uint32_t  GR3_AB1;                                /*  GR3_AB1         */
    2111224    volatile uint32_t  GR3_AB2;                                /*  GR3_AB2         */
    2121225    volatile uint32_t  GR3_AB3;                                /*  GR3_AB3         */
     1226
    2131227/* end of struct st_vdc5_from_gr0_update */
    2141228    volatile uint32_t  GR3_AB4;                                /*  GR3_AB4         */
    2151229    volatile uint32_t  GR3_AB5;                                /*  GR3_AB5         */
    2161230    volatile uint32_t  GR3_AB6;                                /*  GR3_AB6         */
     1231
    2171232/* start of struct st_vdc5_from_gr0_ab7 */
    2181233    volatile uint32_t  GR3_AB7;                                /*  GR3_AB7         */
    … …  
    2221237    volatile uint32_t  GR3_AB11;                               /*  GR3_AB11        */
    2231238    volatile uint32_t  GR3_BASE;                               /*  GR3_BASE        */
     1239
    2241240/* end of struct st_vdc5_from_gr0_ab7 */
    2251241    volatile uint32_t  GR3_CLUT_INT;                           /*  GR3_CLUT_INT    */
    … …  
    2281244    volatile uint32_t  GAM_G_UPDATE;                           /*  GAM_G_UPDATE    */
    2291245    volatile uint32_t  GAM_SW;                                 /*  GAM_SW          */
    230 #define VDC5_GAM_G_LUT1_COUNT 16
     1246
     1247/* #define VDC5_GAM_G_LUT1_COUNT (16) */
    2311248    volatile uint32_t  GAM_G_LUT1;                             /*  GAM_G_LUT1      */
    2321249    volatile uint32_t  GAM_G_LUT2;                             /*  GAM_G_LUT2      */
    … …  
    2451262    volatile uint32_t  GAM_G_LUT15;                            /*  GAM_G_LUT15     */
    2461263    volatile uint32_t  GAM_G_LUT16;                            /*  GAM_G_LUT16     */
    247 #define VDC5_GAM_G_AREA1_COUNT 8
     1264
     1265/* #define VDC5_GAM_G_AREA1_COUNT (8) */
    2481266    volatile uint32_t  GAM_G_AREA1;                            /*  GAM_G_AREA1     */
    2491267    volatile uint32_t  GAM_G_AREA2;                            /*  GAM_G_AREA2     */
    … …  
    2571275    volatile uint32_t  GAM_B_UPDATE;                           /*  GAM_B_UPDATE    */
    2581276    volatile uint8_t   dummy17[4];                             /*                  */
    259 #define VDC5_GAM_B_LUT1_COUNT 16
     1277
     1278/* #define VDC5_GAM_B_LUT1_COUNT (16) */
    2601279    volatile uint32_t  GAM_B_LUT1;                             /*  GAM_B_LUT1      */
    2611280    volatile uint32_t  GAM_B_LUT2;                             /*  GAM_B_LUT2      */
    … …  
    2741293    volatile uint32_t  GAM_B_LUT15;                            /*  GAM_B_LUT15     */
    2751294    volatile uint32_t  GAM_B_LUT16;                            /*  GAM_B_LUT16     */
    276 #define VDC5_GAM_B_AREA1_COUNT 8
     1295
     1296/* #define VDC5_GAM_B_AREA1_COUNT (8) */
    2771297    volatile uint32_t  GAM_B_AREA1;                            /*  GAM_B_AREA1     */
    2781298    volatile uint32_t  GAM_B_AREA2;                            /*  GAM_B_AREA2     */
    … …  
    2861306    volatile uint32_t  GAM_R_UPDATE;                           /*  GAM_R_UPDATE    */
    2871307    volatile uint8_t   dummy19[4];                             /*                  */
    288 #define VDC5_GAM_R_LUT1_COUNT 16
     1308
     1309/* #define VDC5_GAM_R_LUT1_COUNT (16) */
    2891310    volatile uint32_t  GAM_R_LUT1;                             /*  GAM_R_LUT1      */
    2901311    volatile uint32_t  GAM_R_LUT2;                             /*  GAM_R_LUT2      */
    … …  
    3031324    volatile uint32_t  GAM_R_LUT15;                            /*  GAM_R_LUT15     */
    3041325    volatile uint32_t  GAM_R_LUT16;                            /*  GAM_R_LUT16     */
    305 #define VDC5_GAM_R_AREA1_COUNT 8
     1326
     1327/* #define VDC5_GAM_R_AREA1_COUNT (8) */
    3061328    volatile uint32_t  GAM_R_AREA1;                            /*  GAM_R_AREA1     */
    3071329    volatile uint32_t  GAM_R_AREA2;                            /*  GAM_R_AREA2     */
    … …  
    3151337    volatile uint32_t  TCON_UPDATE;                            /*  TCON_UPDATE     */
    3161338    volatile uint32_t  TCON_TIM;                               /*  TCON_TIM        */
    317 #define VDC5_TCON_TIM_STVA1_COUNT 2
     1339
     1340/* #define VDC5_TCON_TIM_STVA1_COUNT (2) */
    3181341    volatile uint32_t  TCON_TIM_STVA1;                         /*  TCON_TIM_STVA1  */
    3191342    volatile uint32_t  TCON_TIM_STVA2;                         /*  TCON_TIM_STVA2  */
    320 #define VDC5_TCON_TIM_STVB1_COUNT 2
     1343
     1344/* #define VDC5_TCON_TIM_STVB1_COUNT (2) */
    3211345    volatile uint32_t  TCON_TIM_STVB1;                         /*  TCON_TIM_STVB1  */
    3221346    volatile uint32_t  TCON_TIM_STVB2;                         /*  TCON_TIM_STVB2  */
    323 #define VDC5_TCON_TIM_STH1_COUNT 2
     1347
     1348/* #define VDC5_TCON_TIM_STH1_COUNT (2) */
    3241349    volatile uint32_t  TCON_TIM_STH1;                          /*  TCON_TIM_STH1   */
    3251350    volatile uint32_t  TCON_TIM_STH2;                          /*  TCON_TIM_STH2   */
    326 #define VDC5_TCON_TIM_STB1_COUNT 2
     1351
     1352/* #define VDC5_TCON_TIM_STB1_COUNT (2) */
    3271353    volatile uint32_t  TCON_TIM_STB1;                          /*  TCON_TIM_STB1   */
    3281354    volatile uint32_t  TCON_TIM_STB2;                          /*  TCON_TIM_STB2   */
    329 #define VDC5_TCON_TIM_CPV1_COUNT 2
     1355
     1356/* #define VDC5_TCON_TIM_CPV1_COUNT (2) */
    3301357    volatile uint32_t  TCON_TIM_CPV1;                          /*  TCON_TIM_CPV1   */
    3311358    volatile uint32_t  TCON_TIM_CPV2;                          /*  TCON_TIM_CPV2   */
    332 #define VDC5_TCON_TIM_POLA1_COUNT 2
     1359
     1360/* #define VDC5_TCON_TIM_POLA1_COUNT (2) */
    3331361    volatile uint32_t  TCON_TIM_POLA1;                         /*  TCON_TIM_POLA1  */
    3341362    volatile uint32_t  TCON_TIM_POLA2;                         /*  TCON_TIM_POLA2  */
    335 #define VDC5_TCON_TIM_POLB1_COUNT 2
     1363
     1364/* #define VDC5_TCON_TIM_POLB1_COUNT (2) */
    3361365    volatile uint32_t  TCON_TIM_POLB1;                         /*  TCON_TIM_POLB1  */
    3371366    volatile uint32_t  TCON_TIM_POLB2;                         /*  TCON_TIM_POLB2  */
    … …  
    3401369    volatile uint32_t  OUT_UPDATE;                             /*  OUT_UPDATE      */
    3411370    volatile uint32_t  OUT_SET;                                /*  OUT_SET         */
    342 #define VDC5_OUT_BRIGHT1_COUNT 2
     1371
     1372/* #define VDC5_OUT_BRIGHT1_COUNT (2) */
    3431373    volatile uint32_t  OUT_BRIGHT1;                            /*  OUT_BRIGHT1     */
    3441374    volatile uint32_t  OUT_BRIGHT2;                            /*  OUT_BRIGHT2     */
    … …  
    3481378    volatile uint32_t  OUT_CLK_PHASE;                          /*  OUT_CLK_PHASE   */
    3491379    volatile uint8_t   dummy23[88];                            /*                  */
    350 #define VDC5_SYSCNT_INT1_COUNT 6
     1380
     1381/* #define VDC5_SYSCNT_INT1_COUNT (6) */
    3511382    volatile uint32_t  SYSCNT_INT1;                            /*  SYSCNT_INT1     */
    3521383    volatile uint32_t  SYSCNT_INT2;                            /*  SYSCNT_INT2     */
    … …  
    3581389    volatile uint16_t SYSCNT_CLUT;                            /*  SYSCNT_CLUT     */
    3591390    volatile uint8_t   dummy24[356];                           /*                  */
     1391
    3601392/* start of struct st_vdc5_from_sc0_scl0_update */
    3611393    volatile uint32_t  SC1_SCL0_UPDATE;                        /*  SC1_SCL0_UPDATE */
    362 #define VDC5_SC1_SCL0_FRC1_COUNT 7
     1394
     1395/* #define VDC5_SC1_SCL0_FRC1_COUNT (7) */
    3631396    volatile uint32_t  SC1_SCL0_FRC1;                          /*  SC1_SCL0_FRC1   */
    3641397    volatile uint32_t  SC1_SCL0_FRC2;                          /*  SC1_SCL0_FRC2   */
    … …  
    3721405    volatile uint16_t SC1_SCL0_MON0;                          /*  SC1_SCL0_MON0   */
    3731406    volatile uint16_t SC1_SCL0_INT;                           /*  SC1_SCL0_INT    */
    374 #define VDC5_SC1_SC1_SCL0_DS1_COUNT 7
     1407
     1408/* #define VDC5_SC1_SC1_SCL0_DS1_COUNT (7) */
    3751409    volatile uint32_t  SC1_SCL0_DS1;                           /*  SC1_SCL0_DS1    */
    3761410    volatile uint32_t  SC1_SCL0_DS2;                           /*  SC1_SCL0_DS2    */
    … …  
    3801414    volatile uint32_t  SC1_SCL0_DS6;                           /*  SC1_SCL0_DS6    */
    3811415    volatile uint32_t  SC1_SCL0_DS7;                           /*  SC1_SCL0_DS7    */
    382 #define VDC5_SC1_SC1_SCL0_US1_COUNT 8
     1416
     1417/* #define VDC5_SC1_SC1_SCL0_US1_COUNT (8) */
    3831418    volatile uint32_t  SC1_SCL0_US1;                           /*  SC1_SCL0_US1    */
    3841419    volatile uint32_t  SC1_SCL0_US2;                           /*  SC1_SCL0_US2    */
    … …  
    3941429    volatile uint32_t  SC1_SCL1_UPDATE;                        /*  SC1_SCL1_UPDATE */
    3951430    volatile uint8_t   dummy28[4];                             /*                  */
    396 #define VDC5_SC1_SCL1_WR1_COUNT 4
     1431
     1432/* #define VDC5_SC1_SCL1_WR1_COUNT (4) */
    3971433    volatile uint32_t  SC1_SCL1_WR1;                           /*  SC1_SCL1_WR1    */
    3981434    volatile uint32_t  SC1_SCL1_WR2;                           /*  SC1_SCL1_WR2    */
    … …  
    4061442    volatile uint32_t  SC1_SCL1_WR9;                           /*  SC1_SCL1_WR9    */
    4071443    volatile uint32_t  SC1_SCL1_WR10;                          /*  SC1_SCL1_WR10   */
     1444
    4081445/* end of struct st_vdc5_from_sc0_scl0_update */
    4091446    volatile uint32_t  SC1_SCL1_WR11;                          /*  SC1_SCL1_WR11   */
    4101447    volatile uint32_t  SC1_SCL1_MON1;                          /*  SC1_SCL1_MON1   */
     1448
    4111449/* start of struct st_vdc5_from_sc0_scl1_pbuf0 */
    412 #define VDC5_SC1_SCL1_PBUF0_COUNT 4
     1450
     1451/* #define VDC5_SC1_SCL1_PBUF0_COUNT (4) */
    4131452    volatile uint32_t  SC1_SCL1_PBUF0;                         /*  SC1_SCL1_PBUF0  */
    4141453    volatile uint32_t  SC1_SCL1_PBUF1;                         /*  SC1_SCL1_PBUF1  */
    … …  
    4171456    volatile uint32_t  SC1_SCL1_PBUF_FLD;                      /*  SC1_SCL1_PBUF_FLD */
    4181457    volatile uint32_t  SC1_SCL1_PBUF_CNT;                      /*  SC1_SCL1_PBUF_CNT */
     1458
    4191459/* end of struct st_vdc5_from_sc0_scl1_pbuf0 */
    4201460    volatile uint8_t   dummy30[44];                            /*                  */
     1461
    4211462/* start of struct st_vdc5_from_gr0_update */
    4221463    volatile uint32_t  GR1_UPDATE;                             /*  GR1_UPDATE      */
    4231464    volatile uint32_t  GR1_FLM_RD;                             /*  GR1_FLM_RD      */
    424 #define VDC5_GR1_FLM1_COUNT 6
     1465
     1466/* #define VDC5_GR1_FLM1_COUNT (6) */
    4251467    volatile uint32_t  GR1_FLM1;                               /*  GR1_FLM1        */
    4261468    volatile uint32_t  GR1_FLM2;                               /*  GR1_FLM2        */
    … …  
    4291471    volatile uint32_t  GR1_FLM5;                               /*  GR1_FLM5        */
    4301472    volatile uint32_t  GR1_FLM6;                               /*  GR1_FLM6        */
    431 #define VDC5_GR1_AB1_COUNT 3
     1473
     1474/* #define VDC5_GR1_AB1_COUNT (3) */
    4321475    volatile uint32_t  GR1_AB1;                                /*  GR1_AB1         */
    4331476    volatile uint32_t  GR1_AB2;                                /*  GR1_AB2         */
    4341477    volatile uint32_t  GR1_AB3;                                /*  GR1_AB3         */
     1478
    4351479/* end of struct st_vdc5_from_gr0_update */
    4361480    volatile uint32_t  GR1_AB4;                                /*  GR1_AB4         */
    4371481    volatile uint32_t  GR1_AB5;                                /*  GR1_AB5         */
    4381482    volatile uint32_t  GR1_AB6;                                /*  GR1_AB6         */
     1483
    4391484/* start of struct st_vdc5_from_gr0_ab7 */
    4401485    volatile uint32_t  GR1_AB7;                                /*  GR1_AB7         */
    … …  
    4441489    volatile uint32_t  GR1_AB11;                               /*  GR1_AB11        */
    4451490    volatile uint32_t  GR1_BASE;                               /*  GR1_BASE        */
     1491
    4461492/* end of struct st_vdc5_from_gr0_ab7 */
    4471493    volatile uint32_t  GR1_CLUT;                               /*  GR1_CLUT        */
    4481494    volatile uint32_t  GR1_MON;                                /*  GR1_MON         */
    4491495    volatile uint8_t   dummy31[40];                            /*                  */
     1496
    4501497/* start of struct st_vdc5_from_adj0_update */
    4511498    volatile uint32_t  ADJ1_UPDATE;                            /*  ADJ1_UPDATE     */
    4521499    volatile uint32_t  ADJ1_BKSTR_SET;                         /*  ADJ1_BKSTR_SET  */
    453 #define VDC5_ADJ1_ENH_TIM1_COUNT 3
     1500
     1501/* #define VDC5_ADJ1_ENH_TIM1_COUNT (3) */
    4541502    volatile uint32_t  ADJ1_ENH_TIM1;                          /*  ADJ1_ENH_TIM1   */
    4551503    volatile uint32_t  ADJ1_ENH_TIM2;                          /*  ADJ1_ENH_TIM2   */
    4561504    volatile uint32_t  ADJ1_ENH_TIM3;                          /*  ADJ1_ENH_TIM3   */
    457 #define VDC5_ADJ1_ENH_SHP1_COUNT 6
     1505
     1506/* #define VDC5_ADJ1_ENH_SHP1_COUNT (6) */
    4581507    volatile uint32_t  ADJ1_ENH_SHP1;                          /*  ADJ1_ENH_SHP1   */
    4591508    volatile uint32_t  ADJ1_ENH_SHP2;                          /*  ADJ1_ENH_SHP2   */
    … …  
    4621511    volatile uint32_t  ADJ1_ENH_SHP5;                          /*  ADJ1_ENH_SHP5   */
    4631512    volatile uint32_t  ADJ1_ENH_SHP6;                          /*  ADJ1_ENH_SHP6   */
    464 #define VDC5_ADJ1_ENH_LTI1_COUNT 2
     1513
     1514/* #define VDC5_ADJ1_ENH_LTI1_COUNT (2) */
    4651515    volatile uint32_t  ADJ1_ENH_LTI1;                          /*  ADJ1_ENH_LTI1   */
    4661516    volatile uint32_t  ADJ1_ENH_LTI2;                          /*  ADJ1_ENH_LTI2   */
    … …  
    4721522    volatile uint32_t  ADJ1_MTX_CRR_ADJ0;                      /*  ADJ1_MTX_CRR_ADJ0 */
    4731523    volatile uint32_t  ADJ1_MTX_CRR_ADJ1;                      /*  ADJ1_MTX_CRR_ADJ1 */
     1524
    4741525/* end of struct st_vdc5_from_adj0_update */
    4751526    volatile uint8_t   dummy32[48];                            /*                  */
    4761527    volatile uint32_t  GR_VIN_UPDATE;                          /*  GR_VIN_UPDATE   */
    4771528    volatile uint8_t   dummy33[28];                            /*                  */
    478 #define VDC5_GR_VIN_AB1_COUNT 7
     1529
     1530/* #define VDC5_GR_VIN_AB1_COUNT (7) */
    4791531    volatile uint32_t  GR_VIN_AB1;                             /*  GR_VIN_AB1      */
    4801532    volatile uint32_t  GR_VIN_AB2;                             /*  GR_VIN_AB2      */
    … …  
    4901542    volatile uint8_t   dummy36[40];                            /*                  */
    4911543    volatile uint32_t  OIR_SCL0_UPDATE;                        /*  OIR_SCL0_UPDATE */
    492 #define VDC5_OIR_SCL0_FRC1_COUNT 7
     1544
     1545/* #define VDC5_OIR_SCL0_FRC1_COUNT (7) */
    4931546    volatile uint32_t  OIR_SCL0_FRC1;                          /*  OIR_SCL0_FRC1   */
    4941547    volatile uint32_t  OIR_SCL0_FRC2;                          /*  OIR_SCL0_FRC2   */
    … …  
    4991552    volatile uint32_t  OIR_SCL0_FRC7;                          /*  OIR_SCL0_FRC7   */
    5001553    volatile uint8_t   dummy37[12];                            /*                  */
    501 #define VDC5_OIR_SCL0_DS1_COUNT 3
     1554
     1555/* #define VDC5_OIR_SCL0_DS1_COUNT (3) */
    5021556    volatile uint32_t  OIR_SCL0_DS1;                           /*  OIR_SCL0_DS1    */
    5031557    volatile uint32_t  OIR_SCL0_DS2;                           /*  OIR_SCL0_DS2    */
    … …  
    5151569    volatile uint32_t  OIR_SCL1_UPDATE;                        /*  OIR_SCL1_UPDATE */
    5161570    volatile uint8_t   dummy42[4];                             /*                  */
    517 #define VDC5_OIR_SCL1_WR1_COUNT 4
     1571
     1572/* #define VDC5_OIR_SCL1_WR1_COUNT (4) */
    5181573    volatile uint32_t  OIR_SCL1_WR1;                           /*  OIR_SCL1_WR1    */
    5191574    volatile uint32_t  OIR_SCL1_WR2;                           /*  OIR_SCL1_WR2    */
    … …  
    5271582    volatile uint32_t  GR_OIR_UPDATE;                          /*  GR_OIR_UPDATE   */
    5281583    volatile uint32_t  GR_OIR_FLM_RD;                          /*  GR_OIR_FLM_RD   */
    529 #define VDC5_GR_OIR_FLM1_COUNT 6
     1584
     1585/* #define VDC5_GR_OIR_FLM1_COUNT (6) */
    5301586    volatile uint32_t  GR_OIR_FLM1;                            /*  GR_OIR_FLM1     */
    5311587    volatile uint32_t  GR_OIR_FLM2;                            /*  GR_OIR_FLM2     */
    … …  
    5341590    volatile uint32_t  GR_OIR_FLM5;                            /*  GR_OIR_FLM5     */
    5351591    volatile uint32_t  GR_OIR_FLM6;                            /*  GR_OIR_FLM6     */
    536 #define VDC5_GR_OIR_AB1_COUNT 3
     1592
     1593/* #define VDC5_GR_OIR_AB1_COUNT (3) */
    5371594    volatile uint32_t  GR_OIR_AB1;                             /*  GR_OIR_AB1      */
    5381595    volatile uint32_t  GR_OIR_AB2;                             /*  GR_OIR_AB2      */
    … …  
    5471604    volatile uint32_t  GR_OIR_CLUT;                            /*  GR_OIR_CLUT     */
    5481605    volatile uint32_t  GR_OIR_MON;                             /*  GR_OIR_MON      */
    549 };
    550 
    551 
    552 struct st_vdc5_from_gr0_update
     1606} r_io_vdc5_t;
     1607
     1608
     1609typedef struct st_vdc5_from_gr0_update
    5531610{
     1611 
    5541612    volatile uint32_t  GR0_UPDATE;                             /*  GR0_UPDATE      */
    5551613    volatile uint32_t  GR0_FLM_RD;                             /*  GR0_FLM_RD      */
    … …  
    5631621    volatile uint32_t  GR0_AB2;                                /*  GR0_AB2         */
    5641622    volatile uint32_t  GR0_AB3;                                /*  GR0_AB3         */
    565 };
    566 
    567 
    568 struct st_vdc5_from_gr0_ab7
     1623} r_io_vdc5_from_gr0_update_t;
     1624
     1625
     1626typedef struct st_vdc5_from_gr0_ab7
    5691627{
     1628 
    5701629    volatile uint32_t  GR0_AB7;                                /*  GR0_AB7         */
    5711630    volatile uint32_t  GR0_AB8;                                /*  GR0_AB8         */
    … …  
    5741633    volatile uint32_t  GR0_AB11;                               /*  GR0_AB11        */
    5751634    volatile uint32_t  GR0_BASE;                               /*  GR0_BASE        */
    576 };
    577 
    578 
    579 struct st_vdc5_from_adj0_update
     1635} r_io_vdc5_from_gr0_ab7_t;
     1636
     1637
     1638typedef struct st_vdc5_from_adj0_update
    5801639{
     1640 
    5811641    volatile uint32_t  ADJ0_UPDATE;                            /*  ADJ0_UPDATE     */
    5821642    volatile uint32_t  ADJ0_BKSTR_SET;                         /*  ADJ0_BKSTR_SET  */
    … …  
    5991659    volatile uint32_t  ADJ0_MTX_CRR_ADJ0;                      /*  ADJ0_MTX_CRR_ADJ0 */
    6001660    volatile uint32_t  ADJ0_MTX_CRR_ADJ1;                      /*  ADJ0_MTX_CRR_ADJ1 */
    601 };
    602 
    603 
    604 struct st_vdc5_from_sc0_scl0_update
     1661} r_io_vdc5_from_adj0_update_t;
     1662
     1663
     1664typedef struct st_vdc5_from_sc0_scl0_update
    6051665{
     1666 
    6061667    volatile uint32_t  SC0_SCL0_UPDATE;                        /*  SC0_SCL0_UPDATE */
    6071668    volatile uint32_t  SC0_SCL0_FRC1;                          /*  SC0_SCL0_FRC1   */
    … …  
    6471708    volatile uint32_t  SC0_SCL1_WR9;                           /*  SC0_SCL1_WR9    */
    6481709    volatile uint32_t  SC0_SCL1_WR10;                          /*  SC0_SCL1_WR10   */
    649 };
    650 
    651 
    652 struct st_vdc5_from_sc0_scl1_pbuf0
     1710} r_io_vdc5_from_sc0_scl0_updat_t /* Short of r_io_vdc5_from_sc0_scl0_update_t */;
     1711
     1712
     1713typedef struct st_vdc5_from_sc0_scl1_pbuf0
    6531714{
     1715 
    6541716    volatile uint32_t  SC0_SCL1_PBUF0;                         /*  SC0_SCL1_PBUF0  */
    6551717    volatile uint32_t  SC0_SCL1_PBUF1;                         /*  SC0_SCL1_PBUF1  */
    … …  
    6581720    volatile uint32_t  SC0_SCL1_PBUF_FLD;                      /*  SC0_SCL1_PBUF_FLD */
    6591721    volatile uint32_t  SC0_SCL1_PBUF_CNT;                      /*  SC0_SCL1_PBUF_CNT */
    660 };
    661 
    662 
    663 #define VDC50   (*(struct st_vdc5    *)0xFCFF7400uL) /* VDC50 */
    664 #define VDC51   (*(struct st_vdc5    *)0xFCFF9400uL) /* VDC51 */
    665 
    666 
    667 /* Start of channnel array defines of VDC5 */
    668 
    669 /* Channnel array defines of VDC5 */
    670 /*(Sample) value = VDC5[ channel ]->INP_UPDATE; */
    671 #define VDC5_COUNT  2
    672 #define VDC5_ADDRESS_LIST \
    673 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    674     &VDC50, &VDC51 \
    675 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    676 
    677 
    678 
    679 /* Channnel array defines of VDC5n_FROM_GR2_AB7_ARRAY */
    680 /*(Sample) value = VDC5n_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
    681 #define VDC5n_FROM_GR2_AB7_ARRAY_COUNT  2
    682 #define VDC5n_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \
    683 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    684 { \
    685     &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 },{ \
    686     &VDC51_FROM_GR2_AB7, &VDC51_FROM_GR3_AB7 \
    687 } \
    688 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    689 #define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */
    690 #define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */
    691 #define VDC51_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR2_AB7) /* VDC51_FROM_GR2_AB7 */
    692 #define VDC51_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR3_AB7) /* VDC51_FROM_GR3_AB7 */
    693 
    694 
    695 
    696 
    697 /* Channnel array defines of VDC5n_FROM_GR2_UPDATE_ARRAY */
    698 /*(Sample) value = VDC5n_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
    699 #define VDC5n_FROM_GR2_UPDATE_ARRAY_COUNT  2
    700 #define VDC5n_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \
    701 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    702 { \
    703     &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE },{ \
    704     &VDC51_FROM_GR2_UPDATE, &VDC51_FROM_GR3_UPDATE \
    705 } \
    706 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    707 #define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */
    708 #define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */
    709 #define VDC51_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR2_UPDATE) /* VDC51_FROM_GR2_UPDATE */
    710 #define VDC51_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR3_UPDATE) /* VDC51_FROM_GR3_UPDATE */
    711 
    712 
    713 
    714 
    715 /* Channnel array defines of VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY */
    716 /*(Sample) value = VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY[ channel ][ index ]->SC0_SCL1_PBUF0; */
    717 #define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT  2
    718 #define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST \
    719 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    720 { \
    721     &VDC50_FROM_SC0_SCL1_PBUF0, &VDC50_FROM_SC1_SCL1_PBUF0 },{ \
    722     &VDC51_FROM_SC0_SCL1_PBUF0, &VDC51_FROM_SC1_SCL1_PBUF0 \
    723 } \
    724 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    725 #define VDC50_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC0_SCL1_PBUF0) /* VDC50_FROM_SC0_SCL1_PBUF0 */
    726 #define VDC50_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC1_SCL1_PBUF0) /* VDC50_FROM_SC1_SCL1_PBUF0 */
    727 #define VDC51_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC0_SCL1_PBUF0) /* VDC51_FROM_SC0_SCL1_PBUF0 */
    728 #define VDC51_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC1_SCL1_PBUF0) /* VDC51_FROM_SC1_SCL1_PBUF0 */
    729 
    730 
    731 
    732 
    733 /* Channnel array defines of VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY */
    734 /*(Sample) value = VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY[ channel ][ index ]->SC0_SCL0_UPDATE; */
    735 #define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT  2
    736 #define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST \
    737 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    738 { \
    739     &VDC50_FROM_SC0_SCL0_UPDATE, &VDC50_FROM_SC1_SCL0_UPDATE },{ \
    740     &VDC51_FROM_SC0_SCL0_UPDATE, &VDC51_FROM_SC1_SCL0_UPDATE \
    741 } \
    742 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    743 #define VDC50_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC0_SCL0_UPDATE) /* VDC50_FROM_SC0_SCL0_UPDATE */
    744 #define VDC50_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC1_SCL0_UPDATE) /* VDC50_FROM_SC1_SCL0_UPDATE */
    745 #define VDC51_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC0_SCL0_UPDATE) /* VDC51_FROM_SC0_SCL0_UPDATE */
    746 #define VDC51_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC1_SCL0_UPDATE) /* VDC51_FROM_SC1_SCL0_UPDATE */
    747 
    748 
    749 
    750 
    751 /* Channnel array defines of VDC5n_FROM_ADJ0_UPDATE_ARRAY */
    752 /*(Sample) value = VDC5n_FROM_ADJ0_UPDATE_ARRAY[ channel ][ index ]->ADJ0_UPDATE; */
    753 #define VDC5n_FROM_ADJ0_UPDATE_ARRAY_COUNT  2
    754 #define VDC5n_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST \
    755 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    756 { \
    757     &VDC50_FROM_ADJ0_UPDATE, &VDC50_FROM_ADJ1_UPDATE },{ \
    758     &VDC51_FROM_ADJ0_UPDATE, &VDC51_FROM_ADJ1_UPDATE \
    759 } \
    760 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    761 #define VDC50_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ0_UPDATE) /* VDC50_FROM_ADJ0_UPDATE */
    762 #define VDC50_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ1_UPDATE) /* VDC50_FROM_ADJ1_UPDATE */
    763 #define VDC51_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ0_UPDATE) /* VDC51_FROM_ADJ0_UPDATE */
    764 #define VDC51_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ1_UPDATE) /* VDC51_FROM_ADJ1_UPDATE */
    765 
    766 
    767 
    768 
    769 /* Channnel array defines of VDC5n_FROM_GR0_AB7_ARRAY */
    770 /*(Sample) value = VDC5n_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
    771 #define VDC5n_FROM_GR0_AB7_ARRAY_COUNT  2
    772 #define VDC5n_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \
    773 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    774 { \
    775     &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR1_AB7 },{ \
    776     &VDC51_FROM_GR0_AB7, &VDC51_FROM_GR1_AB7 \
    777 } \
    778 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    779 #define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */
    780 #define VDC50_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR1_AB7) /* VDC50_FROM_GR1_AB7 */
    781 #define VDC51_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR0_AB7) /* VDC51_FROM_GR0_AB7 */
    782 #define VDC51_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR1_AB7) /* VDC51_FROM_GR1_AB7 */
    783 
    784 
    785 
    786 
    787 /* Channnel array defines of VDC5n_FROM_GR0_UPDATE_ARRAY */
    788 /*(Sample) value = VDC5n_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
    789 #define VDC5n_FROM_GR0_UPDATE_ARRAY_COUNT  2
    790 #define VDC5n_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \
    791 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
    792 { \
    793     &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR1_UPDATE },{ \
    794     &VDC51_FROM_GR0_UPDATE, &VDC51_FROM_GR1_UPDATE \
    795 } \
    796 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
    797 #define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */
    798 #define VDC50_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR1_UPDATE) /* VDC50_FROM_GR1_UPDATE */
    799 #define VDC51_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR0_UPDATE) /* VDC51_FROM_GR0_UPDATE */
    800 #define VDC51_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR1_UPDATE) /* VDC51_FROM_GR1_UPDATE */
    801 
    802 
    803 /* End of channnel array defines of VDC5 */
    804 
    805 
    806 #define VDC50INP_UPDATE VDC50.INP_UPDATE
    807 #define VDC50INP_SEL_CNT VDC50.INP_SEL_CNT
    808 #define VDC50INP_EXT_SYNC_CNT VDC50.INP_EXT_SYNC_CNT
    809 #define VDC50INP_VSYNC_PH_ADJ VDC50.INP_VSYNC_PH_ADJ
    810 #define VDC50INP_DLY_ADJ VDC50.INP_DLY_ADJ
    811 #define VDC50IMGCNT_UPDATE VDC50.IMGCNT_UPDATE
    812 #define VDC50IMGCNT_NR_CNT0 VDC50.IMGCNT_NR_CNT0
    813 #define VDC50IMGCNT_NR_CNT1 VDC50.IMGCNT_NR_CNT1
    814 #define VDC50IMGCNT_MTX_MODE VDC50.IMGCNT_MTX_MODE
    815 #define VDC50IMGCNT_MTX_YG_ADJ0 VDC50.IMGCNT_MTX_YG_ADJ0
    816 #define VDC50IMGCNT_MTX_YG_ADJ1 VDC50.IMGCNT_MTX_YG_ADJ1
    817 #define VDC50IMGCNT_MTX_CBB_ADJ0 VDC50.IMGCNT_MTX_CBB_ADJ0
    818 #define VDC50IMGCNT_MTX_CBB_ADJ1 VDC50.IMGCNT_MTX_CBB_ADJ1
    819 #define VDC50IMGCNT_MTX_CRR_ADJ0 VDC50.IMGCNT_MTX_CRR_ADJ0
    820 #define VDC50IMGCNT_MTX_CRR_ADJ1 VDC50.IMGCNT_MTX_CRR_ADJ1
    821 #define VDC50IMGCNT_DRC_REG VDC50.IMGCNT_DRC_REG
    822 #define VDC50SC0_SCL0_UPDATE VDC50.SC0_SCL0_UPDATE
    823 #define VDC50SC0_SCL0_FRC1 VDC50.SC0_SCL0_FRC1
    824 #define VDC50SC0_SCL0_FRC2 VDC50.SC0_SCL0_FRC2
    825 #define VDC50SC0_SCL0_FRC3 VDC50.SC0_SCL0_FRC3
    826 #define VDC50SC0_SCL0_FRC4 VDC50.SC0_SCL0_FRC4
    827 #define VDC50SC0_SCL0_FRC5 VDC50.SC0_SCL0_FRC5
    828 #define VDC50SC0_SCL0_FRC6 VDC50.SC0_SCL0_FRC6
    829 #define VDC50SC0_SCL0_FRC7 VDC50.SC0_SCL0_FRC7
    830 #define VDC50SC0_SCL0_FRC9 VDC50.SC0_SCL0_FRC9
    831 #define VDC50SC0_SCL0_MON0 VDC50.SC0_SCL0_MON0
    832 #define VDC50SC0_SCL0_INT VDC50.SC0_SCL0_INT
    833 #define VDC50SC0_SCL0_DS1 VDC50.SC0_SCL0_DS1
    834 #define VDC50SC0_SCL0_DS2 VDC50.SC0_SCL0_DS2
    835 #define VDC50SC0_SCL0_DS3 VDC50.SC0_SCL0_DS3
    836 #define VDC50SC0_SCL0_DS4 VDC50.SC0_SCL0_DS4
    837 #define VDC50SC0_SCL0_DS5 VDC50.SC0_SCL0_DS5
    838 #define VDC50SC0_SCL0_DS6 VDC50.SC0_SCL0_DS6
    839 #define VDC50SC0_SCL0_DS7 VDC50.SC0_SCL0_DS7
    840 #define VDC50SC0_SCL0_US1 VDC50.SC0_SCL0_US1
    841 #define VDC50SC0_SCL0_US2 VDC50.SC0_SCL0_US2
    842 #define VDC50SC0_SCL0_US3 VDC50.SC0_SCL0_US3
    843 #define VDC50SC0_SCL0_US4 VDC50.SC0_SCL0_US4
    844 #define VDC50SC0_SCL0_US5 VDC50.SC0_SCL0_US5
    845 #define VDC50SC0_SCL0_US6 VDC50.SC0_SCL0_US6
    846 #define VDC50SC0_SCL0_US7 VDC50.SC0_SCL0_US7
    847 #define VDC50SC0_SCL0_US8 VDC50.SC0_SCL0_US8
    848 #define VDC50SC0_SCL0_OVR1 VDC50.SC0_SCL0_OVR1
    849 #define VDC50SC0_SCL1_UPDATE VDC50.SC0_SCL1_UPDATE
    850 #define VDC50SC0_SCL1_WR1 VDC50.SC0_SCL1_WR1
    851 #define VDC50SC0_SCL1_WR2 VDC50.SC0_SCL1_WR2
    852 #define VDC50SC0_SCL1_WR3 VDC50.SC0_SCL1_WR3
    853 #define VDC50SC0_SCL1_WR4 VDC50.SC0_SCL1_WR4
    854 #define VDC50SC0_SCL1_WR5 VDC50.SC0_SCL1_WR5
    855 #define VDC50SC0_SCL1_WR6 VDC50.SC0_SCL1_WR6
    856 #define VDC50SC0_SCL1_WR7 VDC50.SC0_SCL1_WR7
    857 #define VDC50SC0_SCL1_WR8 VDC50.SC0_SCL1_WR8
    858 #define VDC50SC0_SCL1_WR9 VDC50.SC0_SCL1_WR9
    859 #define VDC50SC0_SCL1_WR10 VDC50.SC0_SCL1_WR10
    860 #define VDC50SC0_SCL1_WR11 VDC50.SC0_SCL1_WR11
    861 #define VDC50SC0_SCL1_MON1 VDC50.SC0_SCL1_MON1
    862 #define VDC50SC0_SCL1_PBUF0 VDC50.SC0_SCL1_PBUF0
    863 #define VDC50SC0_SCL1_PBUF1 VDC50.SC0_SCL1_PBUF1
    864 #define VDC50SC0_SCL1_PBUF2 VDC50.SC0_SCL1_PBUF2
    865 #define VDC50SC0_SCL1_PBUF3 VDC50.SC0_SCL1_PBUF3
    866 #define VDC50SC0_SCL1_PBUF_FLD VDC50.SC0_SCL1_PBUF_FLD
    867 #define VDC50SC0_SCL1_PBUF_CNT VDC50.SC0_SCL1_PBUF_CNT
    868 #define VDC50GR0_UPDATE VDC50.GR0_UPDATE
    869 #define VDC50GR0_FLM_RD VDC50.GR0_FLM_RD
    870 #define VDC50GR0_FLM1 VDC50.GR0_FLM1
    871 #define VDC50GR0_FLM2 VDC50.GR0_FLM2
    872 #define VDC50GR0_FLM3 VDC50.GR0_FLM3
    873 #define VDC50GR0_FLM4 VDC50.GR0_FLM4
    874 #define VDC50GR0_FLM5 VDC50.GR0_FLM5
    875 #define VDC50GR0_FLM6 VDC50.GR0_FLM6
    876 #define VDC50GR0_AB1 VDC50.GR0_AB1
    877 #define VDC50GR0_AB2 VDC50.GR0_AB2
    878 #define VDC50GR0_AB3 VDC50.GR0_AB3
    879 #define VDC50GR0_AB7 VDC50.GR0_AB7
    880 #define VDC50GR0_AB8 VDC50.GR0_AB8
    881 #define VDC50GR0_AB9 VDC50.GR0_AB9
    882 #define VDC50GR0_AB10 VDC50.GR0_AB10
    883 #define VDC50GR0_AB11 VDC50.GR0_AB11
    884 #define VDC50GR0_BASE VDC50.GR0_BASE
    885 #define VDC50GR0_CLUT VDC50.GR0_CLUT
    886 #define VDC50ADJ0_UPDATE VDC50.ADJ0_UPDATE
    887 #define VDC50ADJ0_BKSTR_SET VDC50.ADJ0_BKSTR_SET
    888 #define VDC50ADJ0_ENH_TIM1 VDC50.ADJ0_ENH_TIM1
    889 #define VDC50ADJ0_ENH_TIM2 VDC50.ADJ0_ENH_TIM2
    890 #define VDC50ADJ0_ENH_TIM3 VDC50.ADJ0_ENH_TIM3
    891 #define VDC50ADJ0_ENH_SHP1 VDC50.ADJ0_ENH_SHP1
    892 #define VDC50ADJ0_ENH_SHP2 VDC50.ADJ0_ENH_SHP2
    893 #define VDC50ADJ0_ENH_SHP3 VDC50.ADJ0_ENH_SHP3
    894 #define VDC50ADJ0_ENH_SHP4 VDC50.ADJ0_ENH_SHP4
    895 #define VDC50ADJ0_ENH_SHP5 VDC50.ADJ0_ENH_SHP5
    896 #define VDC50ADJ0_ENH_SHP6 VDC50.ADJ0_ENH_SHP6
    897 #define VDC50ADJ0_ENH_LTI1 VDC50.ADJ0_ENH_LTI1
    898 #define VDC50ADJ0_ENH_LTI2 VDC50.ADJ0_ENH_LTI2
    899 #define VDC50ADJ0_MTX_MODE VDC50.ADJ0_MTX_MODE
    900 #define VDC50ADJ0_MTX_YG_ADJ0 VDC50.ADJ0_MTX_YG_ADJ0
    901 #define VDC50ADJ0_MTX_YG_ADJ1 VDC50.ADJ0_MTX_YG_ADJ1
    902 #define VDC50ADJ0_MTX_CBB_ADJ0 VDC50.ADJ0_MTX_CBB_ADJ0
    903 #define VDC50ADJ0_MTX_CBB_ADJ1 VDC50.ADJ0_MTX_CBB_ADJ1
    904 #define VDC50ADJ0_MTX_CRR_ADJ0 VDC50.ADJ0_MTX_CRR_ADJ0
    905 #define VDC50ADJ0_MTX_CRR_ADJ1 VDC50.ADJ0_MTX_CRR_ADJ1
    906 #define VDC50GR2_UPDATE VDC50.GR2_UPDATE
    907 #define VDC50GR2_FLM_RD VDC50.GR2_FLM_RD
    908 #define VDC50GR2_FLM1 VDC50.GR2_FLM1
    909 #define VDC50GR2_FLM2 VDC50.GR2_FLM2
    910 #define VDC50GR2_FLM3 VDC50.GR2_FLM3
    911 #define VDC50GR2_FLM4 VDC50.GR2_FLM4
    912 #define VDC50GR2_FLM5 VDC50.GR2_FLM5
    913 #define VDC50GR2_FLM6 VDC50.GR2_FLM6
    914 #define VDC50GR2_AB1 VDC50.GR2_AB1
    915 #define VDC50GR2_AB2 VDC50.GR2_AB2
    916 #define VDC50GR2_AB3 VDC50.GR2_AB3
    917 #define VDC50GR2_AB4 VDC50.GR2_AB4
    918 #define VDC50GR2_AB5 VDC50.GR2_AB5
    919 #define VDC50GR2_AB6 VDC50.GR2_AB6
    920 #define VDC50GR2_AB7 VDC50.GR2_AB7
    921 #define VDC50GR2_AB8 VDC50.GR2_AB8
    922 #define VDC50GR2_AB9 VDC50.GR2_AB9
    923 #define VDC50GR2_AB10 VDC50.GR2_AB10
    924 #define VDC50GR2_AB11 VDC50.GR2_AB11
    925 #define VDC50GR2_BASE VDC50.GR2_BASE
    926 #define VDC50GR2_CLUT VDC50.GR2_CLUT
    927 #define VDC50GR2_MON VDC50.GR2_MON
    928 #define VDC50GR3_UPDATE VDC50.GR3_UPDATE
    929 #define VDC50GR3_FLM_RD VDC50.GR3_FLM_RD
    930 #define VDC50GR3_FLM1 VDC50.GR3_FLM1
    931 #define VDC50GR3_FLM2 VDC50.GR3_FLM2
    932 #define VDC50GR3_FLM3 VDC50.GR3_FLM3
    933 #define VDC50GR3_FLM4 VDC50.GR3_FLM4
    934 #define VDC50GR3_FLM5 VDC50.GR3_FLM5
    935 #define VDC50GR3_FLM6 VDC50.GR3_FLM6
    936 #define VDC50GR3_AB1 VDC50.GR3_AB1
    937 #define VDC50GR3_AB2 VDC50.GR3_AB2
    938 #define VDC50GR3_AB3 VDC50.GR3_AB3
    939 #define VDC50GR3_AB4 VDC50.GR3_AB4
    940 #define VDC50GR3_AB5 VDC50.GR3_AB5
    941 #define VDC50GR3_AB6 VDC50.GR3_AB6
    942 #define VDC50GR3_AB7 VDC50.GR3_AB7
    943 #define VDC50GR3_AB8 VDC50.GR3_AB8
    944 #define VDC50GR3_AB9 VDC50.GR3_AB9
    945 #define VDC50GR3_AB10 VDC50.GR3_AB10
    946 #define VDC50GR3_AB11 VDC50.GR3_AB11
    947 #define VDC50GR3_BASE VDC50.GR3_BASE
    948 #define VDC50GR3_CLUT_INT VDC50.GR3_CLUT_INT
    949 #define VDC50GR3_MON VDC50.GR3_MON
    950 #define VDC50GAM_G_UPDATE VDC50.GAM_G_UPDATE
    951 #define VDC50GAM_SW VDC50.GAM_SW
    952 #define VDC50GAM_G_LUT1 VDC50.GAM_G_LUT1
    953 #define VDC50GAM_G_LUT2 VDC50.GAM_G_LUT2
    954 #define VDC50GAM_G_LUT3 VDC50.GAM_G_LUT3
    955 #define VDC50GAM_G_LUT4 VDC50.GAM_G_LUT4
    956 #define VDC50GAM_G_LUT5 VDC50.GAM_G_LUT5
    957 #define VDC50GAM_G_LUT6 VDC50.GAM_G_LUT6
    958 #define VDC50GAM_G_LUT7 VDC50.GAM_G_LUT7
    959 #define VDC50GAM_G_LUT8 VDC50.GAM_G_LUT8
    960 #define VDC50GAM_G_LUT9 VDC50.GAM_G_LUT9
    961 #define VDC50GAM_G_LUT10 VDC50.GAM_G_LUT10
    962 #define VDC50GAM_G_LUT11 VDC50.GAM_G_LUT11
    963 #define VDC50GAM_G_LUT12 VDC50.GAM_G_LUT12
    964 #define VDC50GAM_G_LUT13 VDC50.GAM_G_LUT13
    965 #define VDC50GAM_G_LUT14 VDC50.GAM_G_LUT14
    966 #define VDC50GAM_G_LUT15 VDC50.GAM_G_LUT15
    967 #define VDC50GAM_G_LUT16 VDC50.GAM_G_LUT16
    968 #define VDC50GAM_G_AREA1 VDC50.GAM_G_AREA1
    969 #define VDC50GAM_G_AREA2 VDC50.GAM_G_AREA2
    970 #define VDC50GAM_G_AREA3 VDC50.GAM_G_AREA3
    971 #define VDC50GAM_G_AREA4 VDC50.GAM_G_AREA4
    972 #define VDC50GAM_G_AREA5 VDC50.GAM_G_AREA5
    973 #define VDC50GAM_G_AREA6 VDC50.GAM_G_AREA6
    974 #define VDC50GAM_G_AREA7 VDC50.GAM_G_AREA7
    975 #define VDC50GAM_G_AREA8 VDC50.GAM_G_AREA8
    976 #define VDC50GAM_B_UPDATE VDC50.GAM_B_UPDATE
    977 #define VDC50GAM_B_LUT1 VDC50.GAM_B_LUT1
    978 #define VDC50GAM_B_LUT2 VDC50.GAM_B_LUT2
    979 #define VDC50GAM_B_LUT3 VDC50.GAM_B_LUT3
    980 #define VDC50GAM_B_LUT4 VDC50.GAM_B_LUT4
    981 #define VDC50GAM_B_LUT5 VDC50.GAM_B_LUT5
    982 #define VDC50GAM_B_LUT6 VDC50.GAM_B_LUT6
    983 #define VDC50GAM_B_LUT7 VDC50.GAM_B_LUT7
    984 #define VDC50GAM_B_LUT8 VDC50.GAM_B_LUT8
    985 #define VDC50GAM_B_LUT9 VDC50.GAM_B_LUT9
    986 #define VDC50GAM_B_LUT10 VDC50.GAM_B_LUT10
    987 #define VDC50GAM_B_LUT11 VDC50.GAM_B_LUT11
    988 #define VDC50GAM_B_LUT12 VDC50.GAM_B_LUT12
    989 #define VDC50GAM_B_LUT13 VDC50.GAM_B_LUT13
    990 #define VDC50GAM_B_LUT14 VDC50.GAM_B_LUT14
    991 #define VDC50GAM_B_LUT15 VDC50.GAM_B_LUT15
    992 #define VDC50GAM_B_LUT16 VDC50.GAM_B_LUT16
    993 #define VDC50GAM_B_AREA1 VDC50.GAM_B_AREA1
    994 #define VDC50GAM_B_AREA2 VDC50.GAM_B_AREA2
    995 #define VDC50GAM_B_AREA3 VDC50.GAM_B_AREA3
    996 #define VDC50GAM_B_AREA4 VDC50.GAM_B_AREA4
    997 #define VDC50GAM_B_AREA5 VDC50.GAM_B_AREA5
    998 #define VDC50GAM_B_AREA6 VDC50.GAM_B_AREA6
    999 #define VDC50GAM_B_AREA7 VDC50.GAM_B_AREA7
    1000 #define VDC50GAM_B_AREA8 VDC50.GAM_B_AREA8
    1001 #define VDC50GAM_R_UPDATE VDC50.GAM_R_UPDATE
    1002 #define VDC50GAM_R_LUT1 VDC50.GAM_R_LUT1
    1003 #define VDC50GAM_R_LUT2 VDC50.GAM_R_LUT2
    1004 #define VDC50GAM_R_LUT3 VDC50.GAM_R_LUT3
    1005 #define VDC50GAM_R_LUT4 VDC50.GAM_R_LUT4
    1006 #define VDC50GAM_R_LUT5 VDC50.GAM_R_LUT5
    1007 #define VDC50GAM_R_LUT6 VDC50.GAM_R_LUT6
    1008 #define VDC50GAM_R_LUT7 VDC50.GAM_R_LUT7
    1009 #define VDC50GAM_R_LUT8 VDC50.GAM_R_LUT8
    1010 #define VDC50GAM_R_LUT9 VDC50.GAM_R_LUT9
    1011 #define VDC50GAM_R_LUT10 VDC50.GAM_R_LUT10
    1012 #define VDC50GAM_R_LUT11 VDC50.GAM_R_LUT11
    1013 #define VDC50GAM_R_LUT12 VDC50.GAM_R_LUT12
    1014 #define VDC50GAM_R_LUT13 VDC50.GAM_R_LUT13
    1015 #define VDC50GAM_R_LUT14 VDC50.GAM_R_LUT14
    1016 #define VDC50GAM_R_LUT15 VDC50.GAM_R_LUT15
    1017 #define VDC50GAM_R_LUT16 VDC50.GAM_R_LUT16
    1018 #define VDC50GAM_R_AREA1 VDC50.GAM_R_AREA1
    1019 #define VDC50GAM_R_AREA2 VDC50.GAM_R_AREA2
    1020 #define VDC50GAM_R_AREA3 VDC50.GAM_R_AREA3
    1021 #define VDC50GAM_R_AREA4 VDC50.GAM_R_AREA4
    1022 #define VDC50GAM_R_AREA5 VDC50.GAM_R_AREA5
    1023 #define VDC50GAM_R_AREA6 VDC50.GAM_R_AREA6
    1024 #define VDC50GAM_R_AREA7 VDC50.GAM_R_AREA7
    1025 #define VDC50GAM_R_AREA8 VDC50.GAM_R_AREA8
    1026 #define VDC50TCON_UPDATE VDC50.TCON_UPDATE
    1027 #define VDC50TCON_TIM VDC50.TCON_TIM
    1028 #define VDC50TCON_TIM_STVA1 VDC50.TCON_TIM_STVA1
    1029 #define VDC50TCON_TIM_STVA2 VDC50.TCON_TIM_STVA2
    1030 #define VDC50TCON_TIM_STVB1 VDC50.TCON_TIM_STVB1
    1031 #define VDC50TCON_TIM_STVB2 VDC50.TCON_TIM_STVB2
    1032 #define VDC50TCON_TIM_STH1 VDC50.TCON_TIM_STH1
    1033 #define VDC50TCON_TIM_STH2 VDC50.TCON_TIM_STH2
    1034 #define VDC50TCON_TIM_STB1 VDC50.TCON_TIM_STB1
    1035 #define VDC50TCON_TIM_STB2 VDC50.TCON_TIM_STB2
    1036 #define VDC50TCON_TIM_CPV1 VDC50.TCON_TIM_CPV1
    1037 #define VDC50TCON_TIM_CPV2 VDC50.TCON_TIM_CPV2
    1038 #define VDC50TCON_TIM_POLA1 VDC50.TCON_TIM_POLA1
    1039 #define VDC50TCON_TIM_POLA2 VDC50.TCON_TIM_POLA2
    1040 #define VDC50TCON_TIM_POLB1 VDC50.TCON_TIM_POLB1
    1041 #define VDC50TCON_TIM_POLB2 VDC50.TCON_TIM_POLB2
    1042 #define VDC50TCON_TIM_DE VDC50.TCON_TIM_DE
    1043 #define VDC50OUT_UPDATE VDC50.OUT_UPDATE
    1044 #define VDC50OUT_SET VDC50.OUT_SET
    1045 #define VDC50OUT_BRIGHT1 VDC50.OUT_BRIGHT1
    1046 #define VDC50OUT_BRIGHT2 VDC50.OUT_BRIGHT2
    1047 #define VDC50OUT_CONTRAST VDC50.OUT_CONTRAST
    1048 #define VDC50OUT_PDTHA VDC50.OUT_PDTHA
    1049 #define VDC50OUT_CLK_PHASE VDC50.OUT_CLK_PHASE
    1050 #define VDC50SYSCNT_INT1 VDC50.SYSCNT_INT1
    1051 #define VDC50SYSCNT_INT2 VDC50.SYSCNT_INT2
    1052 #define VDC50SYSCNT_INT3 VDC50.SYSCNT_INT3
    1053 #define VDC50SYSCNT_INT4 VDC50.SYSCNT_INT4
    1054 #define VDC50SYSCNT_INT5 VDC50.SYSCNT_INT5
    1055 #define VDC50SYSCNT_INT6 VDC50.SYSCNT_INT6
    1056 #define VDC50SYSCNT_PANEL_CLK VDC50.SYSCNT_PANEL_CLK
    1057 #define VDC50SYSCNT_CLUT VDC50.SYSCNT_CLUT
    1058 #define VDC50SC1_SCL0_UPDATE VDC50.SC1_SCL0_UPDATE
    1059 #define VDC50SC1_SCL0_FRC1 VDC50.SC1_SCL0_FRC1
    1060 #define VDC50SC1_SCL0_FRC2 VDC50.SC1_SCL0_FRC2
    1061 #define VDC50SC1_SCL0_FRC3 VDC50.SC1_SCL0_FRC3
    1062 #define VDC50SC1_SCL0_FRC4 VDC50.SC1_SCL0_FRC4
    1063 #define VDC50SC1_SCL0_FRC5 VDC50.SC1_SCL0_FRC5
    1064 #define VDC50SC1_SCL0_FRC6 VDC50.SC1_SCL0_FRC6
    1065 #define VDC50SC1_SCL0_FRC7 VDC50.SC1_SCL0_FRC7
    1066 #define VDC50SC1_SCL0_FRC9 VDC50.SC1_SCL0_FRC9
    1067 #define VDC50SC1_SCL0_MON0 VDC50.SC1_SCL0_MON0
    1068 #define VDC50SC1_SCL0_INT VDC50.SC1_SCL0_INT
    1069 #define VDC50SC1_SCL0_DS1 VDC50.SC1_SCL0_DS1
    1070 #define VDC50SC1_SCL0_DS2 VDC50.SC1_SCL0_DS2
    1071 #define VDC50SC1_SCL0_DS3 VDC50.SC1_SCL0_DS3
    1072 #define VDC50SC1_SCL0_DS4 VDC50.SC1_SCL0_DS4
    1073 #define VDC50SC1_SCL0_DS5 VDC50.SC1_SCL0_DS5
    1074 #define VDC50SC1_SCL0_DS6 VDC50.SC1_SCL0_DS6
    1075 #define VDC50SC1_SCL0_DS7 VDC50.SC1_SCL0_DS7
    1076 #define VDC50SC1_SCL0_US1 VDC50.SC1_SCL0_US1
    1077 #define VDC50SC1_SCL0_US2 VDC50.SC1_SCL0_US2
    1078 #define VDC50SC1_SCL0_US3 VDC50.SC1_SCL0_US3
    1079 #define VDC50SC1_SCL0_US4 VDC50.SC1_SCL0_US4
    1080 #define VDC50SC1_SCL0_US5 VDC50.SC1_SCL0_US5
    1081 #define VDC50SC1_SCL0_US6 VDC50.SC1_SCL0_US6
    1082 #define VDC50SC1_SCL0_US7 VDC50.SC1_SCL0_US7
    1083 #define VDC50SC1_SCL0_US8 VDC50.SC1_SCL0_US8
    1084 #define VDC50SC1_SCL0_OVR1 VDC50.SC1_SCL0_OVR1
    1085 #define VDC50SC1_SCL1_UPDATE VDC50.SC1_SCL1_UPDATE
    1086 #define VDC50SC1_SCL1_WR1 VDC50.SC1_SCL1_WR1
    1087 #define VDC50SC1_SCL1_WR2 VDC50.SC1_SCL1_WR2
    1088 #define VDC50SC1_SCL1_WR3 VDC50.SC1_SCL1_WR3
    1089 #define VDC50SC1_SCL1_WR4 VDC50.SC1_SCL1_WR4
    1090 #define VDC50SC1_SCL1_WR5 VDC50.SC1_SCL1_WR5
    1091 #define VDC50SC1_SCL1_WR6 VDC50.SC1_SCL1_WR6
    1092 #define VDC50SC1_SCL1_WR7 VDC50.SC1_SCL1_WR7
    1093 #define VDC50SC1_SCL1_WR8 VDC50.SC1_SCL1_WR8
    1094 #define VDC50SC1_SCL1_WR9 VDC50.SC1_SCL1_WR9
    1095 #define VDC50SC1_SCL1_WR10 VDC50.SC1_SCL1_WR10
    1096 #define VDC50SC1_SCL1_WR11 VDC50.SC1_SCL1_WR11
    1097 #define VDC50SC1_SCL1_MON1 VDC50.SC1_SCL1_MON1
    1098 #define VDC50SC1_SCL1_PBUF0 VDC50.SC1_SCL1_PBUF0
    1099 #define VDC50SC1_SCL1_PBUF1 VDC50.SC1_SCL1_PBUF1
    1100 #define VDC50SC1_SCL1_PBUF2 VDC50.SC1_SCL1_PBUF2
    1101 #define VDC50SC1_SCL1_PBUF3 VDC50.SC1_SCL1_PBUF3
    1102 #define VDC50SC1_SCL1_PBUF_FLD VDC50.SC1_SCL1_PBUF_FLD
    1103 #define VDC50SC1_SCL1_PBUF_CNT VDC50.SC1_SCL1_PBUF_CNT
    1104 #define VDC50GR1_UPDATE VDC50.GR1_UPDATE
    1105 #define VDC50GR1_FLM_RD VDC50.GR1_FLM_RD
    1106 #define VDC50GR1_FLM1 VDC50.GR1_FLM1
    1107 #define VDC50GR1_FLM2 VDC50.GR1_FLM2
    1108 #define VDC50GR1_FLM3 VDC50.GR1_FLM3
    1109 #define VDC50GR1_FLM4 VDC50.GR1_FLM4
    1110 #define VDC50GR1_FLM5 VDC50.GR1_FLM5
    1111 #define VDC50GR1_FLM6 VDC50.GR1_FLM6
    1112 #define VDC50GR1_AB1 VDC50.GR1_AB1
    1113 #define VDC50GR1_AB2 VDC50.GR1_AB2
    1114 #define VDC50GR1_AB3 VDC50.GR1_AB3
    1115 #define VDC50GR1_AB4 VDC50.GR1_AB4
    1116 #define VDC50GR1_AB5 VDC50.GR1_AB5
    1117 #define VDC50GR1_AB6 VDC50.GR1_AB6
    1118 #define VDC50GR1_AB7 VDC50.GR1_AB7
    1119 #define VDC50GR1_AB8 VDC50.GR1_AB8
    1120 #define VDC50GR1_AB9 VDC50.GR1_AB9
    1121 #define VDC50GR1_AB10 VDC50.GR1_AB10
    1122 #define VDC50GR1_AB11 VDC50.GR1_AB11
    1123 #define VDC50GR1_BASE VDC50.GR1_BASE
    1124 #define VDC50GR1_CLUT VDC50.GR1_CLUT
    1125 #define VDC50GR1_MON VDC50.GR1_MON
    1126 #define VDC50ADJ1_UPDATE VDC50.ADJ1_UPDATE
    1127 #define VDC50ADJ1_BKSTR_SET VDC50.ADJ1_BKSTR_SET
    1128 #define VDC50ADJ1_ENH_TIM1 VDC50.ADJ1_ENH_TIM1
    1129 #define VDC50ADJ1_ENH_TIM2 VDC50.ADJ1_ENH_TIM2
    1130 #define VDC50ADJ1_ENH_TIM3 VDC50.ADJ1_ENH_TIM3
    1131 #define VDC50ADJ1_ENH_SHP1 VDC50.ADJ1_ENH_SHP1
    1132 #define VDC50ADJ1_ENH_SHP2 VDC50.ADJ1_ENH_SHP2
    1133 #define VDC50ADJ1_ENH_SHP3 VDC50.ADJ1_ENH_SHP3
    1134 #define VDC50ADJ1_ENH_SHP4 VDC50.ADJ1_ENH_SHP4
    1135 #define VDC50ADJ1_ENH_SHP5 VDC50.ADJ1_ENH_SHP5
    1136 #define VDC50ADJ1_ENH_SHP6 VDC50.ADJ1_ENH_SHP6
    1137 #define VDC50ADJ1_ENH_LTI1 VDC50.ADJ1_ENH_LTI1
    1138 #define VDC50ADJ1_ENH_LTI2 VDC50.ADJ1_ENH_LTI2
    1139 #define VDC50ADJ1_MTX_MODE VDC50.ADJ1_MTX_MODE
    1140 #define VDC50ADJ1_MTX_YG_ADJ0 VDC50.ADJ1_MTX_YG_ADJ0
    1141 #define VDC50ADJ1_MTX_YG_ADJ1 VDC50.ADJ1_MTX_YG_ADJ1
    1142 #define VDC50ADJ1_MTX_CBB_ADJ0 VDC50.ADJ1_MTX_CBB_ADJ0
    1143 #define VDC50ADJ1_MTX_CBB_ADJ1 VDC50.ADJ1_MTX_CBB_ADJ1
    1144 #define VDC50ADJ1_MTX_CRR_ADJ0 VDC50.ADJ1_MTX_CRR_ADJ0
    1145 #define VDC50ADJ1_MTX_CRR_ADJ1 VDC50.ADJ1_MTX_CRR_ADJ1
    1146 #define VDC50GR_VIN_UPDATE VDC50.GR_VIN_UPDATE
    1147 #define VDC50GR_VIN_AB1 VDC50.GR_VIN_AB1
    1148 #define VDC50GR_VIN_AB2 VDC50.GR_VIN_AB2
    1149 #define VDC50GR_VIN_AB3 VDC50.GR_VIN_AB3
    1150 #define VDC50GR_VIN_AB4 VDC50.GR_VIN_AB4
    1151 #define VDC50GR_VIN_AB5 VDC50.GR_VIN_AB5
    1152 #define VDC50GR_VIN_AB6 VDC50.GR_VIN_AB6
    1153 #define VDC50GR_VIN_AB7 VDC50.GR_VIN_AB7
    1154 #define VDC50GR_VIN_BASE VDC50.GR_VIN_BASE
    1155 #define VDC50GR_VIN_MON VDC50.GR_VIN_MON
    1156 #define VDC50OIR_SCL0_UPDATE VDC50.OIR_SCL0_UPDATE
    1157 #define VDC50OIR_SCL0_FRC1 VDC50.OIR_SCL0_FRC1
    1158 #define VDC50OIR_SCL0_FRC2 VDC50.OIR_SCL0_FRC2
    1159 #define VDC50OIR_SCL0_FRC3 VDC50.OIR_SCL0_FRC3
    1160 #define VDC50OIR_SCL0_FRC4 VDC50.OIR_SCL0_FRC4
    1161 #define VDC50OIR_SCL0_FRC5 VDC50.OIR_SCL0_FRC5
    1162 #define VDC50OIR_SCL0_FRC6 VDC50.OIR_SCL0_FRC6
    1163 #define VDC50OIR_SCL0_FRC7 VDC50.OIR_SCL0_FRC7
    1164 #define VDC50OIR_SCL0_DS1 VDC50.OIR_SCL0_DS1
    1165 #define VDC50OIR_SCL0_DS2 VDC50.OIR_SCL0_DS2
    1166 #define VDC50OIR_SCL0_DS3 VDC50.OIR_SCL0_DS3
    1167 #define VDC50OIR_SCL0_DS7 VDC50.OIR_SCL0_DS7
    1168 #define VDC50OIR_SCL0_US1 VDC50.OIR_SCL0_US1
    1169 #define VDC50OIR_SCL0_US2 VDC50.OIR_SCL0_US2
    1170 #define VDC50OIR_SCL0_US3 VDC50.OIR_SCL0_US3
    1171 #define VDC50OIR_SCL0_US8 VDC50.OIR_SCL0_US8
    1172 #define VDC50OIR_SCL0_OVR1 VDC50.OIR_SCL0_OVR1
    1173 #define VDC50OIR_SCL1_UPDATE VDC50.OIR_SCL1_UPDATE
    1174 #define VDC50OIR_SCL1_WR1 VDC50.OIR_SCL1_WR1
    1175 #define VDC50OIR_SCL1_WR2 VDC50.OIR_SCL1_WR2
    1176 #define VDC50OIR_SCL1_WR3 VDC50.OIR_SCL1_WR3
    1177 #define VDC50OIR_SCL1_WR4 VDC50.OIR_SCL1_WR4
    1178 #define VDC50OIR_SCL1_WR5 VDC50.OIR_SCL1_WR5
    1179 #define VDC50OIR_SCL1_WR6 VDC50.OIR_SCL1_WR6
    1180 #define VDC50OIR_SCL1_WR7 VDC50.OIR_SCL1_WR7
    1181 #define VDC50GR_OIR_UPDATE VDC50.GR_OIR_UPDATE
    1182 #define VDC50GR_OIR_FLM_RD VDC50.GR_OIR_FLM_RD
    1183 #define VDC50GR_OIR_FLM1 VDC50.GR_OIR_FLM1
    1184 #define VDC50GR_OIR_FLM2 VDC50.GR_OIR_FLM2
    1185 #define VDC50GR_OIR_FLM3 VDC50.GR_OIR_FLM3
    1186 #define VDC50GR_OIR_FLM4 VDC50.GR_OIR_FLM4
    1187 #define VDC50GR_OIR_FLM5 VDC50.GR_OIR_FLM5
    1188 #define VDC50GR_OIR_FLM6 VDC50.GR_OIR_FLM6
    1189 #define VDC50GR_OIR_AB1 VDC50.GR_OIR_AB1
    1190 #define VDC50GR_OIR_AB2 VDC50.GR_OIR_AB2
    1191 #define VDC50GR_OIR_AB3 VDC50.GR_OIR_AB3
    1192 #define VDC50GR_OIR_AB7 VDC50.GR_OIR_AB7
    1193 #define VDC50GR_OIR_AB8 VDC50.GR_OIR_AB8
    1194 #define VDC50GR_OIR_AB9 VDC50.GR_OIR_AB9
    1195 #define VDC50GR_OIR_AB10 VDC50.GR_OIR_AB10
    1196 #define VDC50GR_OIR_AB11 VDC50.GR_OIR_AB11
    1197 #define VDC50GR_OIR_BASE VDC50.GR_OIR_BASE
    1198 #define VDC50GR_OIR_CLUT VDC50.GR_OIR_CLUT
    1199 #define VDC50GR_OIR_MON VDC50.GR_OIR_MON
    1200 #define VDC51INP_UPDATE VDC51.INP_UPDATE
    1201 #define VDC51INP_SEL_CNT VDC51.INP_SEL_CNT
    1202 #define VDC51INP_EXT_SYNC_CNT VDC51.INP_EXT_SYNC_CNT
    1203 #define VDC51INP_VSYNC_PH_ADJ VDC51.INP_VSYNC_PH_ADJ
    1204 #define VDC51INP_DLY_ADJ VDC51.INP_DLY_ADJ
    1205 #define VDC51IMGCNT_UPDATE VDC51.IMGCNT_UPDATE
    1206 #define VDC51IMGCNT_NR_CNT0 VDC51.IMGCNT_NR_CNT0
    1207 #define VDC51IMGCNT_NR_CNT1 VDC51.IMGCNT_NR_CNT1
    1208 #define VDC51IMGCNT_MTX_MODE VDC51.IMGCNT_MTX_MODE
    1209 #define VDC51IMGCNT_MTX_YG_ADJ0 VDC51.IMGCNT_MTX_YG_ADJ0
    1210 #define VDC51IMGCNT_MTX_YG_ADJ1 VDC51.IMGCNT_MTX_YG_ADJ1
    1211 #define VDC51IMGCNT_MTX_CBB_ADJ0 VDC51.IMGCNT_MTX_CBB_ADJ0
    1212 #define VDC51IMGCNT_MTX_CBB_ADJ1 VDC51.IMGCNT_MTX_CBB_ADJ1
    1213 #define VDC51IMGCNT_MTX_CRR_ADJ0 VDC51.IMGCNT_MTX_CRR_ADJ0
    1214 #define VDC51IMGCNT_MTX_CRR_ADJ1 VDC51.IMGCNT_MTX_CRR_ADJ1
    1215 #define VDC51IMGCNT_DRC_REG VDC51.IMGCNT_DRC_REG
    1216 #define VDC51SC0_SCL0_UPDATE VDC51.SC0_SCL0_UPDATE
    1217 #define VDC51SC0_SCL0_FRC1 VDC51.SC0_SCL0_FRC1
    1218 #define VDC51SC0_SCL0_FRC2 VDC51.SC0_SCL0_FRC2
    1219 #define VDC51SC0_SCL0_FRC3 VDC51.SC0_SCL0_FRC3
    1220 #define VDC51SC0_SCL0_FRC4 VDC51.SC0_SCL0_FRC4
    1221 #define VDC51SC0_SCL0_FRC5 VDC51.SC0_SCL0_FRC5
    1222 #define VDC51SC0_SCL0_FRC6 VDC51.SC0_SCL0_FRC6
    1223 #define VDC51SC0_SCL0_FRC7 VDC51.SC0_SCL0_FRC7
    1224 #define VDC51SC0_SCL0_FRC9 VDC51.SC0_SCL0_FRC9
    1225 #define VDC51SC0_SCL0_MON0 VDC51.SC0_SCL0_MON0
    1226 #define VDC51SC0_SCL0_INT VDC51.SC0_SCL0_INT
    1227 #define VDC51SC0_SCL0_DS1 VDC51.SC0_SCL0_DS1
    1228 #define VDC51SC0_SCL0_DS2 VDC51.SC0_SCL0_DS2
    1229 #define VDC51SC0_SCL0_DS3 VDC51.SC0_SCL0_DS3
    1230 #define VDC51SC0_SCL0_DS4 VDC51.SC0_SCL0_DS4
    1231 #define VDC51SC0_SCL0_DS5 VDC51.SC0_SCL0_DS5
    1232 #define VDC51SC0_SCL0_DS6 VDC51.SC0_SCL0_DS6
    1233 #define VDC51SC0_SCL0_DS7 VDC51.SC0_SCL0_DS7
    1234 #define VDC51SC0_SCL0_US1 VDC51.SC0_SCL0_US1
    1235 #define VDC51SC0_SCL0_US2 VDC51.SC0_SCL0_US2
    1236 #define VDC51SC0_SCL0_US3 VDC51.SC0_SCL0_US3
    1237 #define VDC51SC0_SCL0_US4 VDC51.SC0_SCL0_US4
    1238 #define VDC51SC0_SCL0_US5 VDC51.SC0_SCL0_US5
    1239 #define VDC51SC0_SCL0_US6 VDC51.SC0_SCL0_US6
    1240 #define VDC51SC0_SCL0_US7 VDC51.SC0_SCL0_US7
    1241 #define VDC51SC0_SCL0_US8 VDC51.SC0_SCL0_US8
    1242 #define VDC51SC0_SCL0_OVR1 VDC51.SC0_SCL0_OVR1
    1243 #define VDC51SC0_SCL1_UPDATE VDC51.SC0_SCL1_UPDATE
    1244 #define VDC51SC0_SCL1_WR1 VDC51.SC0_SCL1_WR1
    1245 #define VDC51SC0_SCL1_WR2 VDC51.SC0_SCL1_WR2
    1246 #define VDC51SC0_SCL1_WR3 VDC51.SC0_SCL1_WR3
    1247 #define VDC51SC0_SCL1_WR4 VDC51.SC0_SCL1_WR4
    1248 #define VDC51SC0_SCL1_WR5 VDC51.SC0_SCL1_WR5
    1249 #define VDC51SC0_SCL1_WR6 VDC51.SC0_SCL1_WR6
    1250 #define VDC51SC0_SCL1_WR7 VDC51.SC0_SCL1_WR7
    1251 #define VDC51SC0_SCL1_WR8 VDC51.SC0_SCL1_WR8
    1252 #define VDC51SC0_SCL1_WR9 VDC51.SC0_SCL1_WR9
    1253 #define VDC51SC0_SCL1_WR10 VDC51.SC0_SCL1_WR10
    1254 #define VDC51SC0_SCL1_WR11 VDC51.SC0_SCL1_WR11
    1255 #define VDC51SC0_SCL1_MON1 VDC51.SC0_SCL1_MON1
    1256 #define VDC51SC0_SCL1_PBUF0 VDC51.SC0_SCL1_PBUF0
    1257 #define VDC51SC0_SCL1_PBUF1 VDC51.SC0_SCL1_PBUF1
    1258 #define VDC51SC0_SCL1_PBUF2 VDC51.SC0_SCL1_PBUF2
    1259 #define VDC51SC0_SCL1_PBUF3 VDC51.SC0_SCL1_PBUF3
    1260 #define VDC51SC0_SCL1_PBUF_FLD VDC51.SC0_SCL1_PBUF_FLD
    1261 #define VDC51SC0_SCL1_PBUF_CNT VDC51.SC0_SCL1_PBUF_CNT
    1262 #define VDC51GR0_UPDATE VDC51.GR0_UPDATE
    1263 #define VDC51GR0_FLM_RD VDC51.GR0_FLM_RD
    1264 #define VDC51GR0_FLM1 VDC51.GR0_FLM1
    1265 #define VDC51GR0_FLM2 VDC51.GR0_FLM2
    1266 #define VDC51GR0_FLM3 VDC51.GR0_FLM3
    1267 #define VDC51GR0_FLM4 VDC51.GR0_FLM4
    1268 #define VDC51GR0_FLM5 VDC51.GR0_FLM5
    1269 #define VDC51GR0_FLM6 VDC51.GR0_FLM6
    1270 #define VDC51GR0_AB1 VDC51.GR0_AB1
    1271 #define VDC51GR0_AB2 VDC51.GR0_AB2
    1272 #define VDC51GR0_AB3 VDC51.GR0_AB3
    1273 #define VDC51GR0_AB7 VDC51.GR0_AB7
    1274 #define VDC51GR0_AB8 VDC51.GR0_AB8
    1275 #define VDC51GR0_AB9 VDC51.GR0_AB9
    1276 #define VDC51GR0_AB10 VDC51.GR0_AB10
    1277 #define VDC51GR0_AB11 VDC51.GR0_AB11
    1278 #define VDC51GR0_BASE VDC51.GR0_BASE
    1279 #define VDC51GR0_CLUT VDC51.GR0_CLUT
    1280 #define VDC51ADJ0_UPDATE VDC51.ADJ0_UPDATE
    1281 #define VDC51ADJ0_BKSTR_SET VDC51.ADJ0_BKSTR_SET
    1282 #define VDC51ADJ0_ENH_TIM1 VDC51.ADJ0_ENH_TIM1
    1283 #define VDC51ADJ0_ENH_TIM2 VDC51.ADJ0_ENH_TIM2
    1284 #define VDC51ADJ0_ENH_TIM3 VDC51.ADJ0_ENH_TIM3
    1285 #define VDC51ADJ0_ENH_SHP1 VDC51.ADJ0_ENH_SHP1
    1286 #define VDC51ADJ0_ENH_SHP2 VDC51.ADJ0_ENH_SHP2
    1287 #define VDC51ADJ0_ENH_SHP3 VDC51.ADJ0_ENH_SHP3
    1288 #define VDC51ADJ0_ENH_SHP4 VDC51.ADJ0_ENH_SHP4
    1289 #define VDC51ADJ0_ENH_SHP5 VDC51.ADJ0_ENH_SHP5
    1290 #define VDC51ADJ0_ENH_SHP6 VDC51.ADJ0_ENH_SHP6
    1291 #define VDC51ADJ0_ENH_LTI1 VDC51.ADJ0_ENH_LTI1
    1292 #define VDC51ADJ0_ENH_LTI2 VDC51.ADJ0_ENH_LTI2
    1293 #define VDC51ADJ0_MTX_MODE VDC51.ADJ0_MTX_MODE
    1294 #define VDC51ADJ0_MTX_YG_ADJ0 VDC51.ADJ0_MTX_YG_ADJ0
    1295 #define VDC51ADJ0_MTX_YG_ADJ1 VDC51.ADJ0_MTX_YG_ADJ1
    1296 #define VDC51ADJ0_MTX_CBB_ADJ0 VDC51.ADJ0_MTX_CBB_ADJ0
    1297 #define VDC51ADJ0_MTX_CBB_ADJ1 VDC51.ADJ0_MTX_CBB_ADJ1
    1298 #define VDC51ADJ0_MTX_CRR_ADJ0 VDC51.ADJ0_MTX_CRR_ADJ0
    1299 #define VDC51ADJ0_MTX_CRR_ADJ1 VDC51.ADJ0_MTX_CRR_ADJ1
    1300 #define VDC51GR2_UPDATE VDC51.GR2_UPDATE
    1301 #define VDC51GR2_FLM_RD VDC51.GR2_FLM_RD
    1302 #define VDC51GR2_FLM1 VDC51.GR2_FLM1
    1303 #define VDC51GR2_FLM2 VDC51.GR2_FLM2
    1304 #define VDC51GR2_FLM3 VDC51.GR2_FLM3
    1305 #define VDC51GR2_FLM4 VDC51.GR2_FLM4
    1306 #define VDC51GR2_FLM5 VDC51.GR2_FLM5
    1307 #define VDC51GR2_FLM6 VDC51.GR2_FLM6
    1308 #define VDC51GR2_AB1 VDC51.GR2_AB1
    1309 #define VDC51GR2_AB2 VDC51.GR2_AB2
    1310 #define VDC51GR2_AB3 VDC51.GR2_AB3
    1311 #define VDC51GR2_AB4 VDC51.GR2_AB4
    1312 #define VDC51GR2_AB5 VDC51.GR2_AB5
    1313 #define VDC51GR2_AB6 VDC51.GR2_AB6
    1314 #define VDC51GR2_AB7 VDC51.GR2_AB7
    1315 #define VDC51GR2_AB8 VDC51.GR2_AB8
    1316 #define VDC51GR2_AB9 VDC51.GR2_AB9
    1317 #define VDC51GR2_AB10 VDC51.GR2_AB10
    1318 #define VDC51GR2_AB11 VDC51.GR2_AB11
    1319 #define VDC51GR2_BASE VDC51.GR2_BASE
    1320 #define VDC51GR2_CLUT VDC51.GR2_CLUT
    1321 #define VDC51GR2_MON VDC51.GR2_MON
    1322 #define VDC51GR3_UPDATE VDC51.GR3_UPDATE
    1323 #define VDC51GR3_FLM_RD VDC51.GR3_FLM_RD
    1324 #define VDC51GR3_FLM1 VDC51.GR3_FLM1
    1325 #define VDC51GR3_FLM2 VDC51.GR3_FLM2
    1326 #define VDC51GR3_FLM3 VDC51.GR3_FLM3
    1327 #define VDC51GR3_FLM4 VDC51.GR3_FLM4
    1328 #define VDC51GR3_FLM5 VDC51.GR3_FLM5
    1329 #define VDC51GR3_FLM6 VDC51.GR3_FLM6
    1330 #define VDC51GR3_AB1 VDC51.GR3_AB1
    1331 #define VDC51GR3_AB2 VDC51.GR3_AB2
    1332 #define VDC51GR3_AB3 VDC51.GR3_AB3
    1333 #define VDC51GR3_AB4 VDC51.GR3_AB4
    1334 #define VDC51GR3_AB5 VDC51.GR3_AB5
    1335 #define VDC51GR3_AB6 VDC51.GR3_AB6
    1336 #define VDC51GR3_AB7 VDC51.GR3_AB7
    1337 #define VDC51GR3_AB8 VDC51.GR3_AB8
    1338 #define VDC51GR3_AB9 VDC51.GR3_AB9
    1339 #define VDC51GR3_AB10 VDC51.GR3_AB10
    1340 #define VDC51GR3_AB11 VDC51.GR3_AB11
    1341 #define VDC51GR3_BASE VDC51.GR3_BASE
    1342 #define VDC51GR3_CLUT_INT VDC51.GR3_CLUT_INT
    1343 #define VDC51GR3_MON VDC51.GR3_MON
    1344 #define VDC51GAM_G_UPDATE VDC51.GAM_G_UPDATE
    1345 #define VDC51GAM_SW VDC51.GAM_SW
    1346 #define VDC51GAM_G_LUT1 VDC51.GAM_G_LUT1
    1347 #define VDC51GAM_G_LUT2 VDC51.GAM_G_LUT2
    1348 #define VDC51GAM_G_LUT3 VDC51.GAM_G_LUT3
    1349 #define VDC51GAM_G_LUT4 VDC51.GAM_G_LUT4
    1350 #define VDC51GAM_G_LUT5 VDC51.GAM_G_LUT5
    1351 #define VDC51GAM_G_LUT6 VDC51.GAM_G_LUT6
    1352 #define VDC51GAM_G_LUT7 VDC51.GAM_G_LUT7
    1353 #define VDC51GAM_G_LUT8 VDC51.GAM_G_LUT8
    1354 #define VDC51GAM_G_LUT9 VDC51.GAM_G_LUT9
    1355 #define VDC51GAM_G_LUT10 VDC51.GAM_G_LUT10
    1356 #define VDC51GAM_G_LUT11 VDC51.GAM_G_LUT11
    1357 #define VDC51GAM_G_LUT12 VDC51.GAM_G_LUT12
    1358 #define VDC51GAM_G_LUT13 VDC51.GAM_G_LUT13
    1359 #define VDC51GAM_G_LUT14 VDC51.GAM_G_LUT14
    1360 #define VDC51GAM_G_LUT15 VDC51.GAM_G_LUT15
    1361 #define VDC51GAM_G_LUT16 VDC51.GAM_G_LUT16
    1362 #define VDC51GAM_G_AREA1 VDC51.GAM_G_AREA1
    1363 #define VDC51GAM_G_AREA2 VDC51.GAM_G_AREA2
    1364 #define VDC51GAM_G_AREA3 VDC51.GAM_G_AREA3
    1365 #define VDC51GAM_G_AREA4 VDC51.GAM_G_AREA4
    1366 #define VDC51GAM_G_AREA5 VDC51.GAM_G_AREA5
    1367 #define VDC51GAM_G_AREA6 VDC51.GAM_G_AREA6
    1368 #define VDC51GAM_G_AREA7 VDC51.GAM_G_AREA7
    1369 #define VDC51GAM_G_AREA8 VDC51.GAM_G_AREA8
    1370 #define VDC51GAM_B_UPDATE VDC51.GAM_B_UPDATE
    1371 #define VDC51GAM_B_LUT1 VDC51.GAM_B_LUT1
    1372 #define VDC51GAM_B_LUT2 VDC51.GAM_B_LUT2
    1373 #define VDC51GAM_B_LUT3 VDC51.GAM_B_LUT3
    1374 #define VDC51GAM_B_LUT4 VDC51.GAM_B_LUT4
    1375 #define VDC51GAM_B_LUT5 VDC51.GAM_B_LUT5
    1376 #define VDC51GAM_B_LUT6 VDC51.GAM_B_LUT6
    1377 #define VDC51GAM_B_LUT7 VDC51.GAM_B_LUT7
    1378 #define VDC51GAM_B_LUT8 VDC51.GAM_B_LUT8
    1379 #define VDC51GAM_B_LUT9 VDC51.GAM_B_LUT9
    1380 #define VDC51GAM_B_LUT10 VDC51.GAM_B_LUT10
    1381 #define VDC51GAM_B_LUT11 VDC51.GAM_B_LUT11
    1382 #define VDC51GAM_B_LUT12 VDC51.GAM_B_LUT12
    1383 #define VDC51GAM_B_LUT13 VDC51.GAM_B_LUT13
    1384 #define VDC51GAM_B_LUT14 VDC51.GAM_B_LUT14
    1385 #define VDC51GAM_B_LUT15 VDC51.GAM_B_LUT15
    1386 #define VDC51GAM_B_LUT16 VDC51.GAM_B_LUT16
    1387 #define VDC51GAM_B_AREA1 VDC51.GAM_B_AREA1
    1388 #define VDC51GAM_B_AREA2 VDC51.GAM_B_AREA2
    1389 #define VDC51GAM_B_AREA3 VDC51.GAM_B_AREA3
    1390 #define VDC51GAM_B_AREA4 VDC51.GAM_B_AREA4
    1391 #define VDC51GAM_B_AREA5 VDC51.GAM_B_AREA5
    1392 #define VDC51GAM_B_AREA6 VDC51.GAM_B_AREA6
    1393 #define VDC51GAM_B_AREA7 VDC51.GAM_B_AREA7
    1394 #define VDC51GAM_B_AREA8 VDC51.GAM_B_AREA8
    1395 #define VDC51GAM_R_UPDATE VDC51.GAM_R_UPDATE
    1396 #define VDC51GAM_R_LUT1 VDC51.GAM_R_LUT1
    1397 #define VDC51GAM_R_LUT2 VDC51.GAM_R_LUT2
    1398 #define VDC51GAM_R_LUT3 VDC51.GAM_R_LUT3
    1399 #define VDC51GAM_R_LUT4 VDC51.GAM_R_LUT4
    1400 #define VDC51GAM_R_LUT5 VDC51.GAM_R_LUT5
    1401 #define VDC51GAM_R_LUT6 VDC51.GAM_R_LUT6
    1402 #define VDC51GAM_R_LUT7 VDC51.GAM_R_LUT7
    1403 #define VDC51GAM_R_LUT8 VDC51.GAM_R_LUT8
    1404 #define VDC51GAM_R_LUT9 VDC51.GAM_R_LUT9
    1405 #define VDC51GAM_R_LUT10 VDC51.GAM_R_LUT10
    1406 #define VDC51GAM_R_LUT11 VDC51.GAM_R_LUT11
    1407 #define VDC51GAM_R_LUT12 VDC51.GAM_R_LUT12
    1408 #define VDC51GAM_R_LUT13 VDC51.GAM_R_LUT13
    1409 #define VDC51GAM_R_LUT14 VDC51.GAM_R_LUT14
    1410 #define VDC51GAM_R_LUT15 VDC51.GAM_R_LUT15
    1411 #define VDC51GAM_R_LUT16 VDC51.GAM_R_LUT16
    1412 #define VDC51GAM_R_AREA1 VDC51.GAM_R_AREA1
    1413 #define VDC51GAM_R_AREA2 VDC51.GAM_R_AREA2
    1414 #define VDC51GAM_R_AREA3 VDC51.GAM_R_AREA3
    1415 #define VDC51GAM_R_AREA4 VDC51.GAM_R_AREA4
    1416 #define VDC51GAM_R_AREA5 VDC51.GAM_R_AREA5
    1417 #define VDC51GAM_R_AREA6 VDC51.GAM_R_AREA6
    1418 #define VDC51GAM_R_AREA7 VDC51.GAM_R_AREA7
    1419 #define VDC51GAM_R_AREA8 VDC51.GAM_R_AREA8
    1420 #define VDC51TCON_UPDATE VDC51.TCON_UPDATE
    1421 #define VDC51TCON_TIM VDC51.TCON_TIM
    1422 #define VDC51TCON_TIM_STVA1 VDC51.TCON_TIM_STVA1
    1423 #define VDC51TCON_TIM_STVA2 VDC51.TCON_TIM_STVA2
    1424 #define VDC51TCON_TIM_STVB1 VDC51.TCON_TIM_STVB1
    1425 #define VDC51TCON_TIM_STVB2 VDC51.TCON_TIM_STVB2
    1426 #define VDC51TCON_TIM_STH1 VDC51.TCON_TIM_STH1
    1427 #define VDC51TCON_TIM_STH2 VDC51.TCON_TIM_STH2
    1428 #define VDC51TCON_TIM_STB1 VDC51.TCON_TIM_STB1
    1429 #define VDC51TCON_TIM_STB2 VDC51.TCON_TIM_STB2
    1430 #define VDC51TCON_TIM_CPV1 VDC51.TCON_TIM_CPV1
    1431 #define VDC51TCON_TIM_CPV2 VDC51.TCON_TIM_CPV2
    1432 #define VDC51TCON_TIM_POLA1 VDC51.TCON_TIM_POLA1
    1433 #define VDC51TCON_TIM_POLA2 VDC51.TCON_TIM_POLA2
    1434 #define VDC51TCON_TIM_POLB1 VDC51.TCON_TIM_POLB1
    1435 #define VDC51TCON_TIM_POLB2 VDC51.TCON_TIM_POLB2
    1436 #define VDC51TCON_TIM_DE VDC51.TCON_TIM_DE
    1437 #define VDC51OUT_UPDATE VDC51.OUT_UPDATE
    1438 #define VDC51OUT_SET VDC51.OUT_SET
    1439 #define VDC51OUT_BRIGHT1 VDC51.OUT_BRIGHT1
    1440 #define VDC51OUT_BRIGHT2 VDC51.OUT_BRIGHT2
    1441 #define VDC51OUT_CONTRAST VDC51.OUT_CONTRAST
    1442 #define VDC51OUT_PDTHA VDC51.OUT_PDTHA
    1443 #define VDC51OUT_CLK_PHASE VDC51.OUT_CLK_PHASE
    1444 #define VDC51SYSCNT_INT1 VDC51.SYSCNT_INT1
    1445 #define VDC51SYSCNT_INT2 VDC51.SYSCNT_INT2
    1446 #define VDC51SYSCNT_INT3 VDC51.SYSCNT_INT3
    1447 #define VDC51SYSCNT_INT4 VDC51.SYSCNT_INT4
    1448 #define VDC51SYSCNT_INT5 VDC51.SYSCNT_INT5
    1449 #define VDC51SYSCNT_INT6 VDC51.SYSCNT_INT6
    1450 #define VDC51SYSCNT_PANEL_CLK VDC51.SYSCNT_PANEL_CLK
    1451 #define VDC51SYSCNT_CLUT VDC51.SYSCNT_CLUT
    1452 #define VDC51SC1_SCL0_UPDATE VDC51.SC1_SCL0_UPDATE
    1453 #define VDC51SC1_SCL0_FRC1 VDC51.SC1_SCL0_FRC1
    1454 #define VDC51SC1_SCL0_FRC2 VDC51.SC1_SCL0_FRC2
    1455 #define VDC51SC1_SCL0_FRC3 VDC51.SC1_SCL0_FRC3
    1456 #define VDC51SC1_SCL0_FRC4 VDC51.SC1_SCL0_FRC4
    1457 #define VDC51SC1_SCL0_FRC5 VDC51.SC1_SCL0_FRC5
    1458 #define VDC51SC1_SCL0_FRC6 VDC51.SC1_SCL0_FRC6
    1459 #define VDC51SC1_SCL0_FRC7 VDC51.SC1_SCL0_FRC7
    1460 #define VDC51SC1_SCL0_FRC9 VDC51.SC1_SCL0_FRC9
    1461 #define VDC51SC1_SCL0_MON0 VDC51.SC1_SCL0_MON0
    1462 #define VDC51SC1_SCL0_INT VDC51.SC1_SCL0_INT
    1463 #define VDC51SC1_SCL0_DS1 VDC51.SC1_SCL0_DS1
    1464 #define VDC51SC1_SCL0_DS2 VDC51.SC1_SCL0_DS2
    1465 #define VDC51SC1_SCL0_DS3 VDC51.SC1_SCL0_DS3
    1466 #define VDC51SC1_SCL0_DS4 VDC51.SC1_SCL0_DS4
    1467 #define VDC51SC1_SCL0_DS5 VDC51.SC1_SCL0_DS5
    1468 #define VDC51SC1_SCL0_DS6 VDC51.SC1_SCL0_DS6
    1469 #define VDC51SC1_SCL0_DS7 VDC51.SC1_SCL0_DS7
    1470 #define VDC51SC1_SCL0_US1 VDC51.SC1_SCL0_US1
    1471 #define VDC51SC1_SCL0_US2 VDC51.SC1_SCL0_US2
    1472 #define VDC51SC1_SCL0_US3 VDC51.SC1_SCL0_US3
    1473 #define VDC51SC1_SCL0_US4 VDC51.SC1_SCL0_US4
    1474 #define VDC51SC1_SCL0_US5 VDC51.SC1_SCL0_US5
    1475 #define VDC51SC1_SCL0_US6 VDC51.SC1_SCL0_US6
    1476 #define VDC51SC1_SCL0_US7 VDC51.SC1_SCL0_US7
    1477 #define VDC51SC1_SCL0_US8 VDC51.SC1_SCL0_US8
    1478 #define VDC51SC1_SCL0_OVR1 VDC51.SC1_SCL0_OVR1
    1479 #define VDC51SC1_SCL1_UPDATE VDC51.SC1_SCL1_UPDATE
    1480 #define VDC51SC1_SCL1_WR1 VDC51.SC1_SCL1_WR1
    1481 #define VDC51SC1_SCL1_WR2 VDC51.SC1_SCL1_WR2
    1482 #define VDC51SC1_SCL1_WR3 VDC51.SC1_SCL1_WR3
    1483 #define VDC51SC1_SCL1_WR4 VDC51.SC1_SCL1_WR4
    1484 #define VDC51SC1_SCL1_WR5 VDC51.SC1_SCL1_WR5
    1485 #define VDC51SC1_SCL1_WR6 VDC51.SC1_SCL1_WR6
    1486 #define VDC51SC1_SCL1_WR7 VDC51.SC1_SCL1_WR7
    1487 #define VDC51SC1_SCL1_WR8 VDC51.SC1_SCL1_WR8
    1488 #define VDC51SC1_SCL1_WR9 VDC51.SC1_SCL1_WR9
    1489 #define VDC51SC1_SCL1_WR10 VDC51.SC1_SCL1_WR10
    1490 #define VDC51SC1_SCL1_WR11 VDC51.SC1_SCL1_WR11
    1491 #define VDC51SC1_SCL1_MON1 VDC51.SC1_SCL1_MON1
    1492 #define VDC51SC1_SCL1_PBUF0 VDC51.SC1_SCL1_PBUF0
    1493 #define VDC51SC1_SCL1_PBUF1 VDC51.SC1_SCL1_PBUF1
    1494 #define VDC51SC1_SCL1_PBUF2 VDC51.SC1_SCL1_PBUF2
    1495 #define VDC51SC1_SCL1_PBUF3 VDC51.SC1_SCL1_PBUF3
    1496 #define VDC51SC1_SCL1_PBUF_FLD VDC51.SC1_SCL1_PBUF_FLD
    1497 #define VDC51SC1_SCL1_PBUF_CNT VDC51.SC1_SCL1_PBUF_CNT
    1498 #define VDC51GR1_UPDATE VDC51.GR1_UPDATE
    1499 #define VDC51GR1_FLM_RD VDC51.GR1_FLM_RD
    1500 #define VDC51GR1_FLM1 VDC51.GR1_FLM1
    1501 #define VDC51GR1_FLM2 VDC51.GR1_FLM2
    1502 #define VDC51GR1_FLM3 VDC51.GR1_FLM3
    1503 #define VDC51GR1_FLM4 VDC51.GR1_FLM4
    1504 #define VDC51GR1_FLM5 VDC51.GR1_FLM5
    1505 #define VDC51GR1_FLM6 VDC51.GR1_FLM6
    1506 #define VDC51GR1_AB1 VDC51.GR1_AB1
    1507 #define VDC51GR1_AB2 VDC51.GR1_AB2
    1508 #define VDC51GR1_AB3 VDC51.GR1_AB3
    1509 #define VDC51GR1_AB4 VDC51.GR1_AB4
    1510 #define VDC51GR1_AB5 VDC51.GR1_AB5
    1511 #define VDC51GR1_AB6 VDC51.GR1_AB6
    1512 #define VDC51GR1_AB7 VDC51.GR1_AB7
    1513 #define VDC51GR1_AB8 VDC51.GR1_AB8
    1514 #define VDC51GR1_AB9 VDC51.GR1_AB9
    1515 #define VDC51GR1_AB10 VDC51.GR1_AB10
    1516 #define VDC51GR1_AB11 VDC51.GR1_AB11
    1517 #define VDC51GR1_BASE VDC51.GR1_BASE
    1518 #define VDC51GR1_CLUT VDC51.GR1_CLUT
    1519 #define VDC51GR1_MON VDC51.GR1_MON
    1520 #define VDC51ADJ1_UPDATE VDC51.ADJ1_UPDATE
    1521 #define VDC51ADJ1_BKSTR_SET VDC51.ADJ1_BKSTR_SET
    1522 #define VDC51ADJ1_ENH_TIM1 VDC51.ADJ1_ENH_TIM1
    1523 #define VDC51ADJ1_ENH_TIM2 VDC51.ADJ1_ENH_TIM2
    1524 #define VDC51ADJ1_ENH_TIM3 VDC51.ADJ1_ENH_TIM3
    1525 #define VDC51ADJ1_ENH_SHP1 VDC51.ADJ1_ENH_SHP1
    1526 #define VDC51ADJ1_ENH_SHP2 VDC51.ADJ1_ENH_SHP2
    1527 #define VDC51ADJ1_ENH_SHP3 VDC51.ADJ1_ENH_SHP3
    1528 #define VDC51ADJ1_ENH_SHP4 VDC51.ADJ1_ENH_SHP4
    1529 #define VDC51ADJ1_ENH_SHP5 VDC51.ADJ1_ENH_SHP5
    1530 #define VDC51ADJ1_ENH_SHP6 VDC51.ADJ1_ENH_SHP6
    1531 #define VDC51ADJ1_ENH_LTI1 VDC51.ADJ1_ENH_LTI1
    1532 #define VDC51ADJ1_ENH_LTI2 VDC51.ADJ1_ENH_LTI2
    1533 #define VDC51ADJ1_MTX_MODE VDC51.ADJ1_MTX_MODE
    1534 #define VDC51ADJ1_MTX_YG_ADJ0 VDC51.ADJ1_MTX_YG_ADJ0
    1535 #define VDC51ADJ1_MTX_YG_ADJ1 VDC51.ADJ1_MTX_YG_ADJ1
    1536 #define VDC51ADJ1_MTX_CBB_ADJ0 VDC51.ADJ1_MTX_CBB_ADJ0
    1537 #define VDC51ADJ1_MTX_CBB_ADJ1 VDC51.ADJ1_MTX_CBB_ADJ1
    1538 #define VDC51ADJ1_MTX_CRR_ADJ0 VDC51.ADJ1_MTX_CRR_ADJ0
    1539 #define VDC51ADJ1_MTX_CRR_ADJ1 VDC51.ADJ1_MTX_CRR_ADJ1
    1540 #define VDC51GR_VIN_UPDATE VDC51.GR_VIN_UPDATE
    1541 #define VDC51GR_VIN_AB1 VDC51.GR_VIN_AB1
    1542 #define VDC51GR_VIN_AB2 VDC51.GR_VIN_AB2
    1543 #define VDC51GR_VIN_AB3 VDC51.GR_VIN_AB3
    1544 #define VDC51GR_VIN_AB4 VDC51.GR_VIN_AB4
    1545 #define VDC51GR_VIN_AB5 VDC51.GR_VIN_AB5
    1546 #define VDC51GR_VIN_AB6 VDC51.GR_VIN_AB6
    1547 #define VDC51GR_VIN_AB7 VDC51.GR_VIN_AB7
    1548 #define VDC51GR_VIN_BASE VDC51.GR_VIN_BASE
    1549 #define VDC51GR_VIN_MON VDC51.GR_VIN_MON
    1550 #define VDC51OIR_SCL0_UPDATE VDC51.OIR_SCL0_UPDATE
    1551 #define VDC51OIR_SCL0_FRC1 VDC51.OIR_SCL0_FRC1
    1552 #define VDC51OIR_SCL0_FRC2 VDC51.OIR_SCL0_FRC2
    1553 #define VDC51OIR_SCL0_FRC3 VDC51.OIR_SCL0_FRC3
    1554 #define VDC51OIR_SCL0_FRC4 VDC51.OIR_SCL0_FRC4
    1555 #define VDC51OIR_SCL0_FRC5 VDC51.OIR_SCL0_FRC5
    1556 #define VDC51OIR_SCL0_FRC6 VDC51.OIR_SCL0_FRC6
    1557 #define VDC51OIR_SCL0_FRC7 VDC51.OIR_SCL0_FRC7
    1558 #define VDC51OIR_SCL0_DS1 VDC51.OIR_SCL0_DS1
    1559 #define VDC51OIR_SCL0_DS2 VDC51.OIR_SCL0_DS2
    1560 #define VDC51OIR_SCL0_DS3 VDC51.OIR_SCL0_DS3
    1561 #define VDC51OIR_SCL0_DS7 VDC51.OIR_SCL0_DS7
    1562 #define VDC51OIR_SCL0_US1 VDC51.OIR_SCL0_US1
    1563 #define VDC51OIR_SCL0_US2 VDC51.OIR_SCL0_US2
    1564 #define VDC51OIR_SCL0_US3 VDC51.OIR_SCL0_US3
    1565 #define VDC51OIR_SCL0_US8 VDC51.OIR_SCL0_US8
    1566 #define VDC51OIR_SCL0_OVR1 VDC51.OIR_SCL0_OVR1
    1567 #define VDC51OIR_SCL1_UPDATE VDC51.OIR_SCL1_UPDATE
    1568 #define VDC51OIR_SCL1_WR1 VDC51.OIR_SCL1_WR1
    1569 #define VDC51OIR_SCL1_WR2 VDC51.OIR_SCL1_WR2
    1570 #define VDC51OIR_SCL1_WR3 VDC51.OIR_SCL1_WR3
    1571 #define VDC51OIR_SCL1_WR4 VDC51.OIR_SCL1_WR4
    1572 #define VDC51OIR_SCL1_WR5 VDC51.OIR_SCL1_WR5
    1573 #define VDC51OIR_SCL1_WR6 VDC51.OIR_SCL1_WR6
    1574 #define VDC51OIR_SCL1_WR7 VDC51.OIR_SCL1_WR7
    1575 #define VDC51GR_OIR_UPDATE VDC51.GR_OIR_UPDATE
    1576 #define VDC51GR_OIR_FLM_RD VDC51.GR_OIR_FLM_RD
    1577 #define VDC51GR_OIR_FLM1 VDC51.GR_OIR_FLM1
    1578 #define VDC51GR_OIR_FLM2 VDC51.GR_OIR_FLM2
    1579 #define VDC51GR_OIR_FLM3 VDC51.GR_OIR_FLM3
    1580 #define VDC51GR_OIR_FLM4 VDC51.GR_OIR_FLM4
    1581 #define VDC51GR_OIR_FLM5 VDC51.GR_OIR_FLM5
    1582 #define VDC51GR_OIR_FLM6 VDC51.GR_OIR_FLM6
    1583 #define VDC51GR_OIR_AB1 VDC51.GR_OIR_AB1
    1584 #define VDC51GR_OIR_AB2 VDC51.GR_OIR_AB2
    1585 #define VDC51GR_OIR_AB3 VDC51.GR_OIR_AB3
    1586 #define VDC51GR_OIR_AB7 VDC51.GR_OIR_AB7
    1587 #define VDC51GR_OIR_AB8 VDC51.GR_OIR_AB8
    1588 #define VDC51GR_OIR_AB9 VDC51.GR_OIR_AB9
    1589 #define VDC51GR_OIR_AB10 VDC51.GR_OIR_AB10
    1590 #define VDC51GR_OIR_AB11 VDC51.GR_OIR_AB11
    1591 #define VDC51GR_OIR_BASE VDC51.GR_OIR_BASE
    1592 #define VDC51GR_OIR_CLUT VDC51.GR_OIR_CLUT
    1593 #define VDC51GR_OIR_MON VDC51.GR_OIR_MON
     1722} r_io_vdc5_from_sc0_scl1_pbuf0_t;
     1723
     1724
     1725/* Channel array defines of VDC5 (2)*/
     1726#ifdef  DECLARE_VDC5_CHANNELS
     1727volatile struct st_vdc5*  VDC5[ VDC5_COUNT ] =
     1728    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     1729    VDC5_ADDRESS_LIST;
     1730    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     1731#endif  /* DECLARE_VDC5_CHANNELS */
     1732
     1733#ifdef  DECLARE_VDC50_FROM_GR2_AB7_ARRAY_CHANNELS
     1734volatile struct st_vdc5_from_gr0_ab7*  VDC50_FROM_GR2_AB7_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR2_AB7_ARRAY_COUNT ] =
     1735    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     1736    VDC50_FROM_GR2_AB7_ARRAY_ADDRESS_LIST;
     1737    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     1738#endif  /* DECLARE_VDC50_FROM_GR2_AB7_ARRAY_CHANNELS */
     1739
     1740#ifdef  DECLARE_VDC50_FROM_GR2_UPDATE_ARRAY_CHANNELS
     1741volatile struct st_vdc5_from_gr0_update*  VDC50_FROM_GR2_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR2_UPDATE_ARRAY_COUNT ] =
     1742    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     1743    VDC50_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST;
     1744    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     1745#endif  /* DECLARE_VDC50_FROM_GR2_UPDATE_ARRAY_CHANNELS */
     1746
     1747#ifdef  DECLARE_VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_CHANNELS
     1748volatile struct st_vdc5_from_sc0_scl1_pbuf0*  VDC50_FROM_SC0_SCL1_PBUF0_ARRAY[ VDC5_COUNT ][ VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT ] =
     1749    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     1750    VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST;
     1751    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     1752#endif  /* DECLARE_VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_CHANNELS */
     1753
     1754#ifdef  DECLARE_VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_CHANNELS
     1755volatile struct st_vdc5_from_sc0_scl0_update*  VDC50_FROM_SC0_SCL0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT ] =
     1756    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     1757    VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST;
     1758    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     1759#endif  /* DECLARE_VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_CHANNELS */
     1760
     1761#ifdef  DECLARE_VDC50_FROM_ADJ0_UPDATE_ARRAY_CHANNELS
     1762volatile struct st_vdc5_from_adj0_update*  VDC50_FROM_ADJ0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_ADJ0_UPDATE_ARRAY_COUNT ] =
     1763    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     1764    VDC50_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST;
     1765    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     1766#endif  /* DECLARE_VDC50_FROM_ADJ0_UPDATE_ARRAY_CHANNELS */
     1767
     1768#ifdef  DECLARE_VDC50_FROM_GR0_AB7_ARRAY_CHANNELS
     1769volatile struct st_vdc5_from_gr0_ab7*  VDC50_FROM_GR0_AB7_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR0_AB7_ARRAY_COUNT ] =
     1770    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     1771    VDC50_FROM_GR0_AB7_ARRAY_ADDRESS_LIST;
     1772    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     1773#endif  /* DECLARE_VDC50_FROM_GR0_AB7_ARRAY_CHANNELS */
     1774
     1775#ifdef  DECLARE_VDC50_FROM_GR0_UPDATE_ARRAY_CHANNELS
     1776volatile struct st_vdc5_from_gr0_update*  VDC50_FROM_GR0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR0_UPDATE_ARRAY_COUNT ] =
     1777    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
     1778    VDC50_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST;
     1779    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
     1780#endif  /* DECLARE_VDC50_FROM_GR0_UPDATE_ARRAY_CHANNELS */
     1781/* End of channel array defines of VDC5 (2)*/
     1782
     1783
    15941784/* <-SEC M1.10.1 */
     1785/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     1786/* <-QAC 0857 */
    15951787/* <-QAC 0639 */
    15961788#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/inc/iodefines/wdt_iodefine.h

    r352 r374  
    1919* following link:
    2020* http://www.renesas.com/disclaimer*
    21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     21* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
    2222*******************************************************************************/
    2323/*******************************************************************************
    … …  
    2525* $Rev: $
    2626* $Date::                           $
    27 * Description : Definition of I/O Register (V1.00a)
     27* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
    2828******************************************************************************/
    2929#ifndef WDT_IODEFINE_H
    3030#define WDT_IODEFINE_H
    31 
    32 struct st_wdt
    33 {                                                          /* WDT              */
    34     volatile uint16_t WTCSR;                                  /*  WTCSR           */
    35     volatile uint16_t WTCNT;                                  /*  WTCNT           */
    36     volatile uint16_t WRCSR;                                  /*  WRCSR           */
    37 };
    38 
     31/* ->QAC 0639 : Over 127 members (C90) */
     32/* ->QAC 0857 : Over 1024 #define (C90) */
     33/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
     34/* ->SEC M1.10.1 : Not magic number */
    3935
    4036#define WDT     (*(struct st_wdt     *)0xFCFE0000uL) /* WDT */
    4137
    4238
    43 #define WDTWTCSR WDT.WTCSR
    44 #define WDTWTCNT WDT.WTCNT
    45 #define WDTWRCSR WDT.WRCSR
     39#define WDTWTCSR (WDT.WTCSR)
     40#define WDTWTCNT (WDT.WTCNT)
     41#define WDTWRCSR (WDT.WRCSR)
     42
     43
     44typedef struct st_wdt
     45{
     46                                                           /* WDT              */
     47    volatile uint16_t WTCSR;                                  /*  WTCSR           */
     48    volatile uint16_t WTCNT;                                  /*  WTCNT           */
     49    volatile uint16_t WRCSR;                                  /*  WRCSR           */
     50} r_io_wdt_t;
     51
     52
     53/* <-SEC M1.10.1 */
     54/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
     55/* <-QAC 0857 */
     56/* <-QAC 0639 */
    4657#endif

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/mmu_RZ_A1H.c

    r373 r374  
    11/**************************************************************************//**
    2  * @file     mmu_Renesas_RZ_A1.c
    3  * @brief    MMU Startup File for
    4  *           mmu_Renesas_RZ_A1 Device Series
    5  * @version  V1.01
    6  * @date     2 Aug 2013
     2 * @file     mmu_RZ_A1H.c
     3 * @brief    MMU Configuration for RZ_A1H Device Series
     4 * @version  V1.00
     5 * @date     10 Mar 2017
    76 *
    87 * @note
    98 *
    109 ******************************************************************************/
    11 /* Copyright (c) 2011 - 2013 ARM LIMITED
    12 
    13    All rights reserved.
    14    Redistribution and use in source and binary forms, with or without
    15    modification, are permitted provided that the following conditions are met:
    16    - Redistributions of source code must retain the above copyright
    17      notice, this list of conditions and the following disclaimer.
    18    - Redistributions in binary form must reproduce the above copyright
    19      notice, this list of conditions and the following disclaimer in the
    20      documentation and/or other materials provided with the distribution.
    21    - Neither the name of ARM nor the names of its contributors may be used
    22      to endorse or promote products derived from this software without
    23      specific prior written permission.
    24    *
    25    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    26    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
    27    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
    28    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
    29    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
    30    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
    31    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
    32    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
    33    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
    34    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
    35    POSSIBILITY OF SUCH DAMAGE.
    36    ---------------------------------------------------------------------------*/
    37 
    38 
    39 #define Renesas_RZ_A1_SPI_MIO_BASE                 (0x3fe00000UL)                        /*!< (SPI_MIO   ) Base Address */
    40 #define Renesas_RZ_A1_BSC_BASE                     (0x3ff00000UL)                        /*!< (BSC       ) Base Address */
    41 #define Renesas_RZ_A1_PERIPH_BASE0                 (0xe8000000UL)                        /*!< (PERIPH0   ) Base Address */
    42 #define Renesas_RZ_A1_PERIPH_BASE1                 (0xfcf00000UL)                        /*!< (PERIPH1   ) Base Address */
     10/*
     11 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
     12 *
     13 * SPDX-License-Identifier: Apache-2.0
     14 *
     15 * Licensed under the Apache License, Version 2.0 (the License); you may
     16 * not use this file except in compliance with the License.
     17 * You may obtain a copy of the License at
     18 *
     19 * www.apache.org/licenses/LICENSE-2.0
     20 *
     21 * Unless required by applicable law or agreed to in writing, software
     22 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
     23 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
     24 * See the License for the specific language governing permissions and
     25 * limitations under the License.
     26 */
     27
     28/* Memory map description from: Renesas RZ_A1H_05E_121130.pdf
     29
     30                                                     Memory Type
     310xffffffff |--------------------------|             ------------
     32           |        Peripherals       |                Device
     330xfcf00000 |--------------------------|             ------------
     34           |        Page Fault        |                Fault
     350xe8300000 |--------------------------|             ------------
     36           |        Peripherals       |                Device
     370xe8000000 |--------------------------|             ------------
     38           |        Page Fault        |                Fault
     390x60A00000 |--------------------------|             ------------
     40           | On Chip RAM (10M) Mirror |                Fault
     410x60000000 |--------------------------|             ------------
     42           |  SPI multi I/O 64MB      |                Fault
     430x5c000000 |--------------------------|             ------------
     44           |  SPI multi I/O 64MB      |                Fault
     450x58000000 |--------------------------|             ------------
     46           |        CS5 Mirror        |                Fault
     470x54000000 |--------------------------|             ------------
     48           |        CS4 Mirror        |                Fault
     490x50000000 |--------------------------|             ------------
     50           |        CS3 Mirror        |                Fault
     510x4c000000 |--------------------------|             ------------
     52           |        CS2 Mirror        |                Fault
     530x48000000 |--------------------------|             ------------
     54           |        CS1 Mirror        |                Fault
     550x44000000 |--------------------------|             ------------
     56           |        CS0 Mirror        |                Fault
     570x40000000 |--------------------------|             ------------
     58           |          BSC             |                 RW
     590x3ff00000 |--------------------------|             ------------
     60           |      SPI_MIO_BASE        |                 RW
     610x3fe00000 |--------------------------|             ------------
     62           |        Page Fault        |                Fault
     630x20A00000 |--------------------------|             ------------
     64           |    On Chip RAM (10M)     |                 RW
     650x20000000 |--------------------------|             ------------
     66           |  SPI multi I/O 64MB      |                 RO
     670x1c000000 |--------------------------|             ------------
     68           |  SPI multi I/O 64MB      |                 RO
     690x18000000 |--------------------------|             ------------
     70           |  CS5 User Area 64MB      |                 RW
     710x14000000 |--------------------------|             ------------
     72           |  CS4 User Area 64MB      |                 RW
     730x10000000 |--------------------------|             ------------
     74           |      CS3 SDRAM 64MB      |                 RW
     750x0c000000 |--------------------------|             ------------
     76           |      CS2 SDRAM 64MB      |                 RW
     770x08000000 |--------------------------|             ------------
     78           |  CS1 NOR Flash 64MB      |                 RO
     790x04000000 |--------------------------|             ------------
     80           |  CS0 NOR Flash 64MB      |                 RO
     810x00000000 |--------------------------|             ------------
     82*/
     83
    4384// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
    4485// Write-Through support *not* available
    … …  
    4889
    4990//Note: You should use the Shareable attribute carefully.
    50 //For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless the inner cache settings.
    51 //CA9-RTX uses LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
    52 //Some A9 implementations does not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
     91//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
     92//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
     93//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
    5394
    5495//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
    … …  
    61102//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
    62103//Domain 0 is always the Client domain
    63 //Descriptors place all memory in domain 0
     104//Descriptors should place all memory in domain 0
    64105//There are no restrictions by privilege level (PL0 can access all memory)
    65106
    66 #include <stdint.h>
    67 #include "MBRZA1H.h"
     107
     108#include "RZ_A1H.h"
    68109
    69110//Import symbols from linker
    … …  
    97138#define RO_DATA_SIZE    (((uint32_t)Image$$RO_DATA$$Limit >> 20) - ((uint32_t)Image$$RO_DATA$$Base >> 20) + 1)
    98139#define RW_DATA_SIZE    (((uint32_t)Image$$RW_DATA$$Limit >> 20) - ((uint32_t)Image$$RW_DATA$$Base >> 20) + 1)
    99 #define RW_IRAM1_SIZE    (((uint32_t)Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)Image$$RW_IRAM1$$Base >> 20) + 1)
     140#define RW_IRAM1_SIZE   (((uint32_t)Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)Image$$RW_IRAM1$$Base >> 20) + 1)
    100141#else
    101142#define VECTORS_SIZE    (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1)
    102143#define RO_DATA_SIZE    (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1)
    103144#define RW_DATA_SIZE    (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1)
    104 #define RW_IRAM1_SIZE    (((uint32_t)&Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)&Image$$RW_IRAM1$$Base >> 20) + 1)
     145#define RW_IRAM1_SIZE   (((uint32_t)&Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)&Image$$RW_IRAM1$$Base >> 20) + 1)
    105146#endif
    106147
    … …  
    138179#endif
    139180
    140 void create_translation_table(void)
     181void MMU_CreateTranslationTable(void)
    141182{
    142183    mmu_region_attributes_Type region;
    … …  
    157198#endif
    158199    /*
    159      * Generate descriptors. Refer to MBRZA1H.h to get information about attributes
     200     * Generate descriptors. Refer to core_ca.h to get information about attributes
    160201     *
    161202     */
    … …  
    164205    section_normal_cod(Sect_Normal_Cod, region);
    165206    section_normal_ro(Sect_Normal_RO, region);
    166     section_normal_rw(Sect_Normal_RW, region);
     207    section_normal(Sect_Normal_RW, region);
    167208    //Create descriptors for peripherals
    168209    section_device_ro(Sect_Device_RO, region);
    … …  
    180221
    181222    //Create 4GB of faulting entries
    182     __TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
     223    MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
    183224
    184225    // R7S72100 memory map.
    185     __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE0    , 64, Sect_Normal_RO);
    186     __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE1    , 64, Sect_Normal_RO);
    187     __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE0       , 64, Sect_Normal_RW);
    188     __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE1       , 64, Sect_Normal_RW);
    189     __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA0        , 64, Sect_Normal_RW);
    190     __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA1        , 64, Sect_Normal_RW);
    191     __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO0           , 64, Sect_Normal_RO);
    192     __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO1           , 64, Sect_Normal_RO);
    193     __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_BASE  , 10, Sect_Normal_RW);
    194     __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_MIO_BASE      ,  1, Sect_Device_RW);
    195     __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_BSC_BASE          ,  1, Sect_Device_RW);
    196     __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE0      ,  3, Sect_Device_RW);
    197     __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE1      , 49, Sect_Device_RW);
     226    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE0    , 64, Sect_Normal_RO);
     227    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE1    , 64, Sect_Normal_RO);
     228    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE0       , 64, Sect_Normal_RW);
     229    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE1       , 64, Sect_Normal_RW);
     230    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA0        , 64, Sect_Normal_RW);
     231    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA1        , 64, Sect_Normal_RW);
     232    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO0           , 64, Sect_Normal_RO);
     233    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO1           , 64, Sect_Normal_RO);
     234    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_BASE  , 10, Sect_Normal_RW);
     235    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_MIO_BASE      ,  1, Sect_Device_RW);
     236    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_BSC_BASE          ,  1, Sect_Device_RW);
     237    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE0      ,  3, Sect_Device_RW);
     238    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE1      , 49, Sect_Device_RW);
    198239
    199240#if defined( __ICCARM__ )
    200241    //Define Image
    201     __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_Cod);
    202     __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod);
    203     __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW);
    204     __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW);
     242    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod);
     243    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod);
     244    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW);
     245    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW);
    205246#else
    206247    //Define Image
    207     __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_RO);
    208     __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod);
    209     __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW);
    210     __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW);
    211 #endif
    212 
    213 #if defined( __CC_ARM )
    214     __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE,         10, Sect_Normal_NC);
     248    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod);
     249    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod);
     250    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW);
     251    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW);
     252#endif
     253
     254#if defined( __CC_ARM )
     255    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE         ,              10, Sect_Normal_NC);
    215256#elif defined ( __ICCARM__ )
    216     __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE,         10, Sect_Normal_NC);
    217 
    218 #else
    219     __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC);
    220     __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC);
     257    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE         ,              10, Sect_Normal_NC);
     258
     259#else
     260    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC);
     261    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC);
    221262#endif
    222263
    … …  
    231272    ; 0     - IRGN[1] 0x1 (Inner WB WA) */
    232273    __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
     274    __ISB();
    233275
    234276    /* Set up domain access control register
    … …  
    236278    ; All translation table entries specify domain 0 */
    237279    __set_DACR(1);
     280    __ISB();
    238281}
    239 
    240 
    241 /*----------------------------------------------------------------------------
    242  * end of file
    243  *---------------------------------------------------------------------------*/

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/system_RZ_A1H.c

    r373 r374  
    1 /**************************************************************************//**
    2  * @file     system_MBRZA1H.c
    3  * @brief    CMSIS Device System Source File for
    4  *           ARM Cortex-A9 Device Series
     1/******************************************************************************
     2 * @file     system_RZ_A1H_H.c
     3 * @brief    CMSIS Device System Source File for ARM Cortex-A9 Device Series
    54 * @version  V1.00
    6  * @date     09 January 2015
     5 * @date     10 Mar 2017
    76 *
    87 * @note
    98 *
    109 ******************************************************************************/
    11 /* Copyright (c) 2011 - 2015 ARM LIMITED
     10/*
     11 * Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved.
     12 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
     13 *
     14 * SPDX-License-Identifier: Apache-2.0
     15 *
     16 * Licensed under the Apache License, Version 2.0 (the License); you may
     17 * not use this file except in compliance with the License.
     18 * You may obtain a copy of the License at
     19 *
     20 * www.apache.org/licenses/LICENSE-2.0
     21 *
     22 * Unless required by applicable law or agreed to in writing, software
     23 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
     24 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
     25 * See the License for the specific language governing permissions and
     26 * limitations under the License.
     27 */
    1228
    13    All rights reserved.
    14    Redistribution and use in source and binary forms, with or without
    15    modification, are permitted provided that the following conditions are met:
    16    - Redistributions of source code must retain the above copyright
    17      notice, this list of conditions and the following disclaimer.
    18    - Redistributions in binary form must reproduce the above copyright
    19      notice, this list of conditions and the following disclaimer in the
    20      documentation and/or other materials provided with the distribution.
    21    - Neither the name of ARM nor the names of its contributors may be used
    22      to endorse or promote products derived from this software without
    23      specific prior written permission.
    24    *
    25    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    26    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
    27    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
    28    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
    29    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
    30    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
    31    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
    32    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
    33    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
    34    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
    35    POSSIBILITY OF SUCH DAMAGE.
    36    ---------------------------------------------------------------------------*/
     29#include <RZ_A1H.h>
     30#include "RZ_A1_Init.h"
     31#include "irq_ctrl.h"
    3732
     33#define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040)
     34#define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040)
     35#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu)
    3836
    39 #include <stdint.h>
    40 #include "MBRZA1H.h"
    41 #include "RZ_A1_Init.h"
     37/*
     38 Port 0 (P0) MD pin assignment
     39 P0_0: MD_BOOT0
     40 P0_1: MD_BOOT1
     41 P0_2: MD_CLK
     42 P0_3: MD_CLKS
     43 */
    4244
     45/*----------------------------------------------------------------------------
     46  System Core Clock Variable
     47 *----------------------------------------------------------------------------*/
     48uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_P0_CLK;
    4349
    44 #if defined(__ARMCC_VERSION)
    45 extern void $Super$$main(void);
    46 __asm void FPUEnable(void);
    47 #else
    48 void FPUEnable(void);
     50/*----------------------------------------------------------------------------
     51  System Core Clock update function
     52 *----------------------------------------------------------------------------*/
     53void SystemCoreClockUpdate (void)
     54{
     55  uint32_t freq;
     56  uint16_t mode;
     57  uint16_t ifc;
    4958
    50 #endif
     59  mode = (GPIO.PPR0 >> 2U) & 0x01U;
    5160
    52 #define FRQCR_IFC_MSK          (0x0030)
    53 #define FRQCR_IFC_SHFT         (8)
    54 #define FRQCR_IFC_1P1          (0) /* x1/1 */
    55 #define FRQCR_IFC_2P3          (1) /* x2/3 */
    56 #define FRQCR_IFC_1P3          (3) /* x1/3 */
     61  if (mode == 0) {
     62    /* Clock Mode 0 */
     63    /* CLKIN is between 10MHz and 13.33MHz */
     64    /* Divider 1 uses 1/1 ratio, PLL x30 is ON */
     65    freq = CM0_RENESAS_RZ_A1_CLKIN * 30U;
     66  } else {
     67    /* Clock Mode 1 */
     68    /* CLKIN is 48MHz */
     69    /* Divider 1 uses 1/4 ratio, PLL x32 is ON */
     70    freq = (CM1_RENESAS_RZ_A1_CLKIN * 32U) / 4U;
     71  }
    5772
    58 extern uint32_t IRQNestLevel;
    59 unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075
    60 uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK;     /*!< System Clock Frequency (Core Clock)  */
     73  /* Get CPG.FRQCR[IFC] bits */
     74  ifc = (CPG.FRQCR >> 8U) & 0x03U;
    6175
     76  /* Determine Divider 2 output clock */
     77  if (ifc == 0x03U) {
     78    /* Division ratio is 1/3 */
     79    freq = (freq / 3U);
     80  }
     81  else {
     82    if (ifc == 0x01U) {
     83      /* Division ratio is 2/3 */
     84      freq = (freq * 2U) / 3U;
     85    }
     86  }
    6287
    63 /**
    64  * Initialize the cache.
    65  *
    66  * @param  none
    67  * @return none
    68  *
    69  * @brief Initialise caches. Requires PL1, so implemented as an SVC in case threads are USR mode.
    70  */
    71 #if defined(__ARMCC_VERSION)
    72 #pragma push
    73 #pragma arm
     88  SystemCoreClock = freq;
     89}
    7490
    75 void InitMemorySubsystem(void) {
    76 
    77     /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
    78      * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
    79      * You are not required to invalidate the main TLB, even though it is recommended for safety
    80      * reasons. This ensures compatibility with future revisions of the processor. */
    81 
    82     unsigned int l2_id;
    83 
    84     /* Invalidate undefined data */
    85     __ca9u_inv_tlb_all();
    86     __v7_inv_icache_all();
    87     __v7_inv_dcache_all();
    88     __v7_inv_btac();
    89 
    90     /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
    91      * invalidate in order to flush the valid data to the next level cache.
    92      */
    93     __enable_mmu();
    94 
    95     /* After MMU is enabled and data has been invalidated, enable caches and BTAC */
    96     __enable_caches();
    97     __enable_btac();
    98 
    99     /* If present, you may also need to Invalidate and Enable L2 cache here */
    100     l2_id = PL310_GetID();
    101     if (l2_id)
    102     {
    103        PL310_InvAllByWay();
    104        PL310_Enable();
    105     }
    106 }
    107 #pragma pop
    108 
    109 #elif defined(__GNUC__)
    110 
    111 void InitMemorySubsystem(void) {
    112  
    113     /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
    114      * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
    115      * You are not required to invalidate the main TLB, even though it is recommended for safety
    116      * reasons. This ensures compatibility with future revisions of the processor. */
    117  
    118     unsigned int l2_id;
    119  
    120     /* Invalidate undefined data */
    121     __ca9u_inv_tlb_all();
    122     __v7_inv_icache_all();
    123     __v7_inv_dcache_all();
    124     __v7_inv_btac();
    125  
    126     /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
    127      * invalidate in order to flush the valid data to the next level cache.
    128      */
    129     __enable_mmu();
    130  
    131     /* After MMU is enabled and data has been invalidated, enable caches and BTAC */
    132     __enable_caches();
    133     __enable_btac();
    134  
    135     /* If present, you may also need to Invalidate and Enable L2 cache here */
    136     l2_id = PL310_GetID();
    137     if (l2_id)
    138     {
    139        PL310_InvAllByWay();
    140        PL310_Enable();
    141     }
    142 }
    143 #elif defined ( __ICCARM__ )
    144 
    145 void InitMemorySubsystem(void) {
    146  
    147     /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
    148      * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
    149      * You are not required to invalidate the main TLB, even though it is recommended for safety
    150      * reasons. This ensures compatibility with future revisions of the processor. */
    151  
    152     unsigned int l2_id;
    153  
    154     /* Invalidate undefined data */
    155     __ca9u_inv_tlb_all();
    156     __v7_inv_icache_all();
    157     __v7_inv_dcache_all();
    158     __v7_inv_btac();
    159  
    160     /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
    161      * invalidate in order to flush the valid data to the next level cache.
    162      */
    163     __enable_mmu();
    164  
    165     /* After MMU is enabled and data has been invalidated, enable caches and BTAC */
    166     __enable_caches();
    167     __enable_btac();
    168  
    169     /* If present, you may also need to Invalidate and Enable L2 cache here */
    170     l2_id = PL310_GetID();
    171     if (l2_id)
    172     {
    173        PL310_InvAllByWay();
    174        PL310_Enable();
    175     }
    176 }
    177 #else
    178 
    179 #endif
    180 
    181 
    182 extern IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1];
    183 
    184 uint32_t IRQCount = sizeof IRQTable / 4;
    185 
     91/*----------------------------------------------------------------------------
     92  IRQ Handler Register/Unregister
     93 *----------------------------------------------------------------------------*/
    18694uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler)
    18795{
    188     if (irq < IRQCount) {
    189         IRQTable[irq] = handler;
    190         return 0;
    191     }
    192     else {
    193         return 1;
    194     }
     96    return IRQ_SetHandler(irq, handler);
    19597}
    19698
    19799uint32_t InterruptHandlerUnregister (IRQn_Type irq)
    198100{
    199     if (irq < IRQCount) {
    200         IRQTable[irq] = 0;
    201         return 0;
    202     }
    203     else {
    204         return 1;
    205     }
     101    return IRQ_SetHandler(irq, (IRQHandler_t)NULL);
    206102}
    207103
    208 /**
    209  * Update SystemCoreClock variable
    210  *
    211  * @param  none
    212  * @return none
    213  *
    214  * @brief  Updates the SystemCoreClock with current core Clock.
    215  */
    216 void SystemCoreClockUpdate (void)
     104/*----------------------------------------------------------------------------
     105  System Initialization
     106 *----------------------------------------------------------------------------*/
     107void SystemInit (void)
    217108{
    218     uint32_t frqcr_ifc = ((uint32_t)CPG.FRQCR & (uint32_t)FRQCR_IFC_MSK) >> FRQCR_IFC_SHFT;
     109/*       do not use global variables because this function is called before
     110         reaching pre-main. RW section may be overwritten afterwards.          */
     111 
     112  // Enable SRAM write access
     113  CPG.SYSCR3 = 0x0F;
    219114
    220     switch (frqcr_ifc) {
    221         case FRQCR_IFC_1P1:
    222             SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK;
    223             break;
    224         case FRQCR_IFC_2P3:
    225             SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK * 2 / 3;
    226             break;
    227         case FRQCR_IFC_1P3:
    228             SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK  / 3;
    229             break;
    230         default:
    231             /* do nothing */
    232             break;
    233     }
     115  RZ_A1_InitClock();
     116  RZ_A1_InitBus();
     117
     118  // Invalidate entire Unified TLB
     119  __set_TLBIALL(0);
     120
     121  // Invalidate entire branch predictor array
     122  __set_BPIALL(0);
     123  __DSB();
     124  __ISB();
     125
     126  //  Invalidate instruction cache and flush branch target cache
     127  __set_ICIALLU(0);
     128  __DSB();
     129  __ISB();
     130
     131  //  Invalidate data cache
     132  L1C_InvalidateDCacheAll();
     133
     134  // Create Translation Table
     135  MMU_CreateTranslationTable();
     136
     137  // Enable MMU
     138  MMU_Enable();
     139
     140  // Enable Caches
     141  L1C_EnableCaches();
     142  L1C_EnableBTAC();
     143
     144#if (__L2C_PRESENT == 1)
     145  L2C_InvAllByWay();
     146  // Enable L2C
     147  L2C_Enable();
     148#endif
     149
     150#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
     151  // Enable FPU
     152  __FPU_Enable();
     153#endif
     154
     155  // IRQ Initialize
     156  IRQ_Initialize();
    234157}
    235158
    236 
    237 /**
    238  * Initialize the system
    239  *
    240  * @param  none
    241  * @return none
    242  *
    243  * @brief  Setup the microcontroller system.
    244  *         Initialize the System.
    245  */
    246 void SystemInit (void)
    247 {
    248     IRQNestLevel = 0;
    249 /*       do not use global variables because this function is called before
    250          reaching pre-main. RW section maybe overwritten afterwards.          */
    251     RZ_A1_InitClock();
    252     RZ_A1_InitBus();
    253 
    254         //Configure GIC ICDICFR GIC_SetICDICFR()
    255     GIC_Enable();
    256     __enable_irq();
    257 
     159void mbed_sdk_init(void) {
     160    L1C_CleanDCacheAll();
     161    L1C_InvalidateICacheAll();
    258162}
    259 
    260 
    261 //Fault Status Register (IFSR/DFSR) definitions
    262 #define FSR_ALIGNMENT_FAULT                  0x01   //DFSR only. Fault on first lookup
    263 #define FSR_INSTRUCTION_CACHE_MAINTENANCE    0x04   //DFSR only - async/external
    264 #define FSR_SYNC_EXT_TTB_WALK_FIRST          0x0c   //sync/external
    265 #define FSR_SYNC_EXT_TTB_WALK_SECOND         0x0e   //sync/external
    266 #define FSR_SYNC_PARITY_TTB_WALK_FIRST       0x1c   //sync/external
    267 #define FSR_SYNC_PARITY_TTB_WALK_SECOND      0x1e   //sync/external
    268 #define FSR_TRANSLATION_FAULT_FIRST          0x05   //MMU Fault - internal
    269 #define FSR_TRANSLATION_FAULT_SECOND         0x07   //MMU Fault - internal
    270 #define FSR_ACCESS_FLAG_FAULT_FIRST          0x03   //MMU Fault - internal
    271 #define FSR_ACCESS_FLAG_FAULT_SECOND         0x06   //MMU Fault - internal
    272 #define FSR_DOMAIN_FAULT_FIRST               0x09   //MMU Fault - internal
    273 #define FSR_DOMAIN_FAULT_SECOND              0x0b   //MMU Fault - internal
    274 #define FSR_PERMISION_FAULT_FIRST            0x0f   //MMU Fault - internal
    275 #define FSR_PERMISION_FAULT_SECOND           0x0d   //MMU Fault - internal
    276 #define FSR_DEBUG_EVENT                      0x02   //internal
    277 #define FSR_SYNC_EXT_ABORT                   0x08   //sync/external
    278 #define FSR_TLB_CONFLICT_ABORT               0x10   //sync/external
    279 #define FSR_LOCKDOWN                         0x14   //internal
    280 #define FSR_COPROCESSOR_ABORT                0x1a   //internal
    281 #define FSR_SYNC_PARITY_ERROR                0x19   //sync/external
    282 #define FSR_ASYNC_EXTERNAL_ABORT             0x16   //DFSR only - async/external
    283 #define FSR_ASYNC_PARITY_ERROR               0x18   //DFSR only - async/external
    284 
    285 void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) {
    286     uint32_t FS = (DFSR & (1 << 10)) >> 6 | (DFSR & 0x0f); //Store Fault Status
    287 
    288     switch(FS) {
    289         //Synchronous parity errors - retry
    290         case FSR_SYNC_PARITY_ERROR:
    291         case FSR_SYNC_PARITY_TTB_WALK_FIRST:
    292         case FSR_SYNC_PARITY_TTB_WALK_SECOND:
    293             return;
    294 
    295         //Your code here. Value in DFAR is invalid for some fault statuses.
    296         case FSR_ALIGNMENT_FAULT:
    297         case FSR_INSTRUCTION_CACHE_MAINTENANCE:
    298         case FSR_SYNC_EXT_TTB_WALK_FIRST:
    299         case FSR_SYNC_EXT_TTB_WALK_SECOND:
    300         case FSR_TRANSLATION_FAULT_FIRST:
    301         case FSR_TRANSLATION_FAULT_SECOND:
    302         case FSR_ACCESS_FLAG_FAULT_FIRST:
    303         case FSR_ACCESS_FLAG_FAULT_SECOND:
    304         case FSR_DOMAIN_FAULT_FIRST:
    305         case FSR_DOMAIN_FAULT_SECOND:
    306         case FSR_PERMISION_FAULT_FIRST:
    307         case FSR_PERMISION_FAULT_SECOND:
    308         case FSR_DEBUG_EVENT:
    309         case FSR_SYNC_EXT_ABORT:
    310         case FSR_TLB_CONFLICT_ABORT:
    311         case FSR_LOCKDOWN:
    312         case FSR_COPROCESSOR_ABORT:
    313         case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid
    314         case FSR_ASYNC_PARITY_ERROR:   //DFAR invalid
    315         default:
    316                 _kernel_default_exc_handler();
    317     }
    318 }
    319 
    320 void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) {
    321     uint32_t FS = (IFSR & (1 << 10)) >> 6 | (IFSR & 0x0f); //Store Fault Status
    322 
    323     switch(FS) {
    324         //Synchronous parity errors - retry
    325         case FSR_SYNC_PARITY_ERROR:
    326         case FSR_SYNC_PARITY_TTB_WALK_FIRST:
    327         case FSR_SYNC_PARITY_TTB_WALK_SECOND:
    328             return;
    329 
    330         //Your code here. Value in IFAR is invalid for some fault statuses.
    331         case FSR_SYNC_EXT_TTB_WALK_FIRST:
    332         case FSR_SYNC_EXT_TTB_WALK_SECOND:
    333         case FSR_TRANSLATION_FAULT_FIRST:
    334         case FSR_TRANSLATION_FAULT_SECOND:
    335         case FSR_ACCESS_FLAG_FAULT_FIRST:
    336         case FSR_ACCESS_FLAG_FAULT_SECOND:
    337         case FSR_DOMAIN_FAULT_FIRST:
    338         case FSR_DOMAIN_FAULT_SECOND:
    339         case FSR_PERMISION_FAULT_FIRST:
    340         case FSR_PERMISION_FAULT_SECOND:
    341         case FSR_DEBUG_EVENT: //IFAR invalid
    342         case FSR_SYNC_EXT_ABORT:
    343         case FSR_TLB_CONFLICT_ABORT:
    344         case FSR_LOCKDOWN:
    345         case FSR_COPROCESSOR_ABORT:
    346         default:
    347             _kernel_default_exc_handler();
    348     }
    349 }
    350 
    351 //returns amount to decrement lr by
    352 //this will be 0 when we have emulated the instruction and want to execute the next instruction
    353 //this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2)
    354 //this will be 4 when we have performed some maintenance and want to retry the instruction in ARM (state == 4)
    355 uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {
    356     const unsigned int THUMB = 2;
    357     const unsigned int ARM = 4;
    358     //Lazy VFP/NEON initialisation and switching
    359 
    360     // (ARM ARM section A7.5) VFP data processing instruction?
    361     // (ARM ARM section A7.6) VFP/NEON register load/store instruction?
    362     // (ARM ARM section A7.8) VFP/NEON register data transfer instruction?
    363     // (ARM ARM section A7.9) VFP/NEON 64-bit register data transfer instruction?
    364     if ((state == ARM   && ((opcode & 0x0C000000) >> 26 == 0x03)) ||
    365         (state == THUMB && ((opcode & 0xEC000000) >> 26 == 0x3B))) {
    366         if (((opcode & 0x00000E00) >> 9) == 5) {
    367             FPUEnable();
    368             return state;
    369         }
    370     }
    371 
    372     // (ARM ARM section A7.4) NEON data processing instruction?
    373     if ((state == ARM   && ((opcode & 0xFE000000) >> 24 == 0xF2)) ||
    374         (state == THUMB && ((opcode & 0xEF000000) >> 24 == 0xEF)) ||
    375     // (ARM ARM section A7.7) NEON load/store instruction?
    376         (state == ARM   && ((opcode >> 24) == 0xF4)) ||
    377         (state == THUMB && ((opcode >> 24) == 0xF9))) {
    378         FPUEnable();
    379         return state;
    380     }
    381 
    382     //Add code here for other Undef cases
    383     _kernel_default_exc_handler();
    384     return 0;
    385 }
    386 
    387 #if defined(__ARMCC_VERSION)
    388 #pragma push
    389 #pragma arm
    390 //Critical section, called from undef handler, so systick is disabled
    391 __asm void FPUEnable(void) {
    392         ARM
    393 
    394         //Permit access to VFP/NEON, registers by modifying CPACR
    395         MRC     p15,0,R1,c1,c0,2
    396         ORR     R1,R1,#0x00F00000
    397         MCR     p15,0,R1,c1,c0,2
    398 
    399         //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
    400         ISB
    401 
    402         //Enable VFP/NEON
    403         VMRS    R1,FPEXC
    404         ORR     R1,R1,#0x40000000
    405         VMSR    FPEXC,R1
    406 
    407         //Initialise VFP/NEON registers to 0
    408         MOV     R2,#0
    409         //Initialise D16 registers to 0
    410         VMOV    D0, R2,R2
    411         VMOV    D1, R2,R2
    412         VMOV    D2, R2,R2
    413         VMOV    D3, R2,R2
    414         VMOV    D4, R2,R2
    415         VMOV    D5, R2,R2
    416         VMOV    D6, R2,R2
    417         VMOV    D7, R2,R2
    418         VMOV    D8, R2,R2
    419         VMOV    D9, R2,R2
    420         VMOV    D10,R2,R2
    421         VMOV    D11,R2,R2
    422         VMOV    D12,R2,R2
    423         VMOV    D13,R2,R2
    424         VMOV    D14,R2,R2
    425         VMOV    D15,R2,R2
    426         //Initialise D32 registers to 0
    427         VMOV    D16,R2,R2
    428         VMOV    D17,R2,R2
    429         VMOV    D18,R2,R2
    430         VMOV    D19,R2,R2
    431         VMOV    D20,R2,R2
    432         VMOV    D21,R2,R2
    433         VMOV    D22,R2,R2
    434         VMOV    D23,R2,R2
    435         VMOV    D24,R2,R2
    436         VMOV    D25,R2,R2
    437         VMOV    D26,R2,R2
    438         VMOV    D27,R2,R2
    439         VMOV    D28,R2,R2
    440         VMOV    D29,R2,R2
    441         VMOV    D30,R2,R2
    442         VMOV    D31,R2,R2
    443         //Initialise FPSCR to a known state
    444         VMRS    R2,FPSCR
    445         LDR     R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
    446         AND     R2,R2,R3
    447         VMSR    FPSCR,R2
    448 
    449         BX      LR
    450 }
    451 #pragma pop
    452 
    453 #elif defined(__GNUC__)
    454 void FPUEnable(void) {
    455     __asm__ (
    456         ".ARM;"
    457 
    458         //Permit access to VFP/NEON, registers by modifying CPACR
    459         "MRC     p15,0,R1,c1,c0,2;"
    460         "ORR     R1,R1,#0x00F00000;"
    461         "MCR     p15,0,R1,c1,c0,2;"
    462 
    463         //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
    464         "ISB;"
    465 
    466         //Enable VFP/NEON
    467         "VMRS    R1,FPEXC;"
    468         "ORR     R1,R1,#0x40000000;"
    469         "VMSR    FPEXC,R1;"
    470 
    471         //Initialise VFP/NEON registers to 0
    472         "MOV     R2,#0;"
    473         //Initialise D16 registers to 0
    474         "VMOV    D0, R2,R2;"
    475         "VMOV    D1, R2,R2;"
    476         "VMOV    D2, R2,R2;"
    477         "VMOV    D3, R2,R2;"
    478         "VMOV    D4, R2,R2;"
    479         "VMOV    D5, R2,R2;"
    480         "VMOV    D6, R2,R2;"
    481         "VMOV    D7, R2,R2;"
    482         "VMOV    D8, R2,R2;"
    483         "VMOV    D9, R2,R2;"
    484         "VMOV    D10,R2,R2;"
    485         "VMOV    D11,R2,R2;"
    486         "VMOV    D12,R2,R2;"
    487         "VMOV    D13,R2,R2;"
    488         "VMOV    D14,R2,R2;"
    489         "VMOV    D15,R2,R2;"
    490         //Initialise D32 registers to 0
    491         "VMOV    D16,R2,R2;"
    492         "VMOV    D17,R2,R2;"
    493         "VMOV    D18,R2,R2;"
    494         "VMOV    D19,R2,R2;"
    495         "VMOV    D20,R2,R2;"
    496         "VMOV    D21,R2,R2;"
    497         "VMOV    D22,R2,R2;"
    498         "VMOV    D23,R2,R2;"
    499         "VMOV    D24,R2,R2;"
    500         "VMOV    D25,R2,R2;"
    501         "VMOV    D26,R2,R2;"
    502         "VMOV    D27,R2,R2;"
    503         "VMOV    D28,R2,R2;"
    504         "VMOV    D29,R2,R2;"
    505         "VMOV    D30,R2,R2;"
    506         "VMOV    D31,R2,R2;"
    507 
    508         //Initialise FPSCR to a known state
    509         "VMRS    R2,FPSCR;"
    510         "LDR     R3,=0x00086060;" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
    511         "AND     R2,R2,R3;"
    512         "VMSR    FPSCR,R2;"
    513 
    514         //"BX      LR;"
    515              :
    516              :
    517              :"r1", "r2", "r3");
    518     return;
    519 }
    520 #else
    521 #endif
    522 

  • asp3_tinet_ecnl_arm/trunk/asp3_dcre/mbed/targets/TARGET_RENESAS/TARGET_RZA1XX/TARGET_RZ_A1H/device/system_RZ_A1H.h

    r373 r374  
    1 /**************************************************************************//**
    2  * @file     system_MBRZA1H.h
    3  * @brief    CMSIS Device System Header File for
    4  *           ARMCA9 Device Series
     1/******************************************************************************
     2 * @file     system_RZ_A1H.h
     3 * @brief    CMSIS Device System Header File for ARM Cortex-A Device Series
    54 * @version  V1.00
    6  * @date     11 June 2013
     5 * @date     10 Mar 2017
    76 *
    87 * @note
    98 *
    109 ******************************************************************************/
    11 /* Copyright (c) 2011 - 2013 ARM LIMITED
     10/*
     11 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
     12 *
     13 * SPDX-License-Identifier: Apache-2.0
     14 *
     15 * Licensed under the Apache License, Version 2.0 (the License); you may
     16 * not use this file except in compliance with the License.
     17 * You may obtain a copy of the License at
     18 *
     19 * www.apache.org/licenses/LICENSE-2.0
     20 *
     21 * Unless required by applicable law or agreed to in writing, software
     22 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
     23 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
     24 * See the License for the specific language governing permissions and
     25 * limitations under the License.
     26 */
    1227
    13    All rights reserved.
    14    Redistribution and use in source and binary forms, with or without
    15    modification, are permitted provided that the following conditions are met:
    16    - Redistributions of source code must retain the above copyright
    17      notice, this list of conditions and the following disclaimer.
    18    - Redistributions in binary form must reproduce the above copyright
    19      notice, this list of conditions and the following disclaimer in the
    20      documentation and/or other materials provided with the distribution.
    21    - Neither the name of ARM nor the names of its contributors may be used
    22      to endorse or promote products derived from this software without
    23      specific prior written permission.
    24    *
    25    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    26    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
    27    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
    28    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
    29    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
    30    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
    31    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
    32    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
    33    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
    34    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
    35    POSSIBILITY OF SUCH DAMAGE.
    36    ---------------------------------------------------------------------------*/
    37 
    38 
    39 #ifndef __SYSTEM_MBRZA1H
    40 #define __SYSTEM_MBRZA1H
     28#ifndef __SYSTEM_RZ_A1H_H
     29#define __SYSTEM_RZ_A1H_H
    4130
    4231#ifdef __cplusplus
    … …  
    4433#endif
    4534
     35#include <stdint.h>
     36
    4637extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
    4738
    48 typedef void(*IRQHandler)();
    49 uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler);
    50 uint32_t InterruptHandlerUnregister(IRQn_Type);
     39typedef void(*IRQHandler)();         /*!< Type Definition for Interrupt Handlers */
    5140
    5241/**
    53  * Initialize the system
    54  *
    55  * @param  none
    56  * @return none
    57  *
    58  * @brief  Setup the microcontroller system.
    59  *         Initialize the System and update the Systd short        int16_t;emCoreClock variable.
     42  \brief Setup the microcontroller system.
     43
     44   Initialize the System and update the SystemCoreClock variable.
    6045 */
    6146extern void SystemInit (void);
     47
     48
     49/**
     50  \brief  Update SystemCoreClock variable.
     51
     52   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
     53 */
     54extern void SystemCoreClockUpdate (void);
     55
     56/**
     57  \brief  Interrupt Handler Register.
     58
     59   Registers an Interrupt Handler into the IRQ Table.
     60 */
     61extern uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler);
     62
     63/**
     64  \brief  Interrupt Handler Unregister.
     65
     66   Unregisters an Interrupt Handler from the IRQ Table.
     67 */
     68extern uint32_t InterruptHandlerUnregister(IRQn_Type);
     69
     70/**
     71  \brief  Create Translation Table.
     72
     73   Creates Memory Management Unit Translation Table.
     74 */
     75extern void MMU_CreateTranslationTable(void);
    6276
    6377#ifdef __cplusplus
    … …  
    6579#endif
    6680
    67 #endif /* __SYSTEM_MBRZA1H */
     81#endif /* __SYSTEM_RZ_A1H_H */
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