- Timestamp:
- Apr 5, 2019, 9:26:53 PM (5 years ago)
- File:
-
- 1 edited
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asp3_tinet_ecnl_arm/trunk/asp3_dcre/arch/arm_gcc/common/arm.h
r352 r374 5 5 * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory 6 6 * Toyohashi Univ. of Technology, JAPAN 7 * Copyright (C) 2006-201 6by Embedded and Real-Time Systems Laboratory7 * Copyright (C) 2006-2018 by Embedded and Real-Time Systems Laboratory 8 8 * Graduate School of Information Science, Nagoya Univ., JAPAN 9 9 * … … 119 119 120 120 /* 121 * CP15のコプロセッサアクセス制御レジスタ(CPACR)の設定値 122 */ 123 #define CP15_CPACR_ASEDIS UINT_C(0x80000000) 124 #define CP15_CPACR_D32DIS UINT_C(0x40000000) 125 #define CP15_CPACR_CP11_FULLACCESS UINT_C(0x00c00000) 126 #define CP15_CPACR_CP10_FULLACCESS UINT_C(0x00300000) 127 128 /* 121 129 * CP15のフォールト状態レジスタの参照値 122 130 */ … … 444 452 445 453 #endif /* TOPPERS_MACRO_ONLY */ 454 455 /* 456 * 浮動小数点例外制御レジスタ(FPEXC)の設定値 457 */ 458 #define FPEXC_ENABLE UINT_C(0x40000000) 459 446 460 #endif /* TOPPERS_ARM_H */
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