Changeset 364 for asp3_tinet_ecnl_rx/trunk/ntshell/src
- Timestamp:
- Feb 1, 2019, 9:57:09 PM (5 years ago)
- Location:
- asp3_tinet_ecnl_rx/trunk/ntshell/src
- Files:
-
- 1 added
- 14 edited
Legend:
- Unmodified
- Added
- Removed
-
asp3_tinet_ecnl_rx/trunk/ntshell/src/echonet_app_config.h
r337 r364 40 40 41 41 #define ECHONET_TASK_STACK_SIZE 1024 /* ECNL UDPタスク用スタック領域のサイズ */ 42 43 #define ECHONET_API_DATAQUEUE_COUNT 5 /* ECHONET Lite API用データキュー */ 44 #define ECHONET_SVC_DATAQUEUE_COUNT 5 /* ECHONET Lite サービス処理タスク用データキュー */ 45 #define ECHONET_UDP_DATAQUEUE_COUNT 5 /* ECHONET Lite UDP通信処理用データキュー */ 42 46 43 47 /* -
asp3_tinet_ecnl_rx/trunk/ntshell/src/fdtable.c
r359 r364 45 45 #include "target_syssvc.h" 46 46 #ifndef NTSHELL_NO_SOCKET 47 #include <tinet_defs.h> 47 48 #include <tinet_config.h> 49 #include <net/net.h> 50 #include <net/net_endian.h> 48 51 #include <netinet/in.h> 49 52 #include <netinet/in_itron.h> … … 55 58 #include <net/net.h> 56 59 #include <net/if_var.h> 60 #include <netinet/udp.h> 57 61 #include <netinet/udp_var.h> 58 62 #include <netinet/tcp.h> 59 63 #include <netinet/tcp_var.h> 64 #include <net/net_buf.h> 60 65 #endif 61 66 #include "ff.h" … … 69 74 #define IO_TYPE_DIR 3 70 75 #define IO_TYPE_TCP 4 71 #define IO_TYPE_UDP 76 #define IO_TYPE_UDP 5 72 77 73 78 static struct _IO_FILE fd_table[8 * sizeof(FLGPTN)] = { … … 85 90 continue; 86 91 92 memset(fp, 0, sizeof(struct _IO_FILE)); 87 93 fp->fd = fd; 88 94 fp->type = type; … … 280 286 #endif 281 287 288 void memor(void *dst, void *src, size_t len) 289 { 290 uint8_t *d = (uint8_t *)dst; 291 uint8_t *s = (uint8_t *)src; 292 uint8_t *e = &s[len]; 293 294 while (s < e) { 295 *d++ |= *s++; 296 } 297 } 298 282 299 struct fd_events { 283 300 int count; … … 304 321 } 305 322 306 memcpy(&evts.readfds, rfds, sizeof(fd_set)); 307 memcpy(&evts.writefds, wfds, sizeof(fd_set)); 308 memcpy(&evts.errorfds, efds, sizeof(fd_set)); 323 if (rfds != NULL) 324 memcpy(&evts.readfds, rfds, sizeof(fd_set)); 325 else 326 memset(&evts.readfds, 0, sizeof(fd_set)); 327 if (wfds != NULL) 328 memcpy(&evts.writefds, wfds, sizeof(fd_set)); 329 else 330 memset(&evts.writefds, 0, sizeof(fd_set)); 331 if (efds != NULL) 332 memcpy(&evts.errorfds, efds, sizeof(fd_set)); 333 else 334 memset(&evts.errorfds, 0, sizeof(fd_set)); 309 335 evts.count = 0; 310 336 311 337 ret = shell_get_evts(&evts, tmout); 338 if (rfds != NULL) 339 memset(rfds, 0, sizeof(fd_set)); 340 if (wfds != NULL) 341 memset(wfds, 0, sizeof(fd_set)); 342 if (efds != NULL) 343 memset(efds, 0, sizeof(fd_set)); 312 344 if (ret == E_OK) { 313 memcpy(rfds, &evts.readfds, sizeof(fd_set)); 314 memcpy(wfds, &evts.writefds, sizeof(fd_set)); 315 memcpy(efds, &evts.errorfds, sizeof(fd_set)); 345 if (rfds != NULL) 346 memor(rfds, &evts.readfds, sizeof(fd_set)); 347 if (wfds != NULL) 348 memor(wfds, &evts.writefds, sizeof(fd_set)); 349 if (efds != NULL) 350 memor(efds, &evts.errorfds, sizeof(fd_set)); 316 351 return evts.count; 317 352 } 318 353 if (ret == E_TMOUT) { 319 memset(rfds, 0, sizeof(fd_set));320 memset(wfds, 0, sizeof(fd_set));321 memset(efds, 0, sizeof(fd_set));322 354 return 0; 323 355 } … … 441 473 struct _IO_FILE *fp = tcpid_to_fd(cepid); 442 474 FLGPTN flgptn = 0; 475 ER ret; 476 int len; 443 477 444 478 if (fp == NULL) … … 449 483 450 484 switch (fncd) { 485 case TFN_TCP_RCV_BUF: 486 len = *(int *)p_parblk; 487 if (len <= 0) 488 return E_OK; 489 490 ret = wai_sem(SEM_FILEDESC); 491 if (ret < 0) { 492 syslog(LOG_ERROR, "wai_sem => %d", ret); 493 } 494 fp->psock->len += len; 495 ret = sig_sem(SEM_FILEDESC); 496 if (ret < 0) { 497 syslog(LOG_ERROR, "sig_sem => %d", ret); 498 } 499 500 if (fp->readevt_w == fp->readevt_r) fp->readevt_w++; 501 502 set_flg(FLG_SELECT_WAIT, flgptn); 503 return E_OK; 504 451 505 case TFN_TCP_RCV_DAT: 506 len = *(int *)p_parblk; 507 if (len <= 0) 508 return E_OK; 509 510 ret = wai_sem(SEM_FILEDESC); 511 if (ret < 0) { 512 syslog(LOG_ERROR, "wai_sem => %d", ret); 513 } 514 fp->psock->len += len; 515 ret = sig_sem(SEM_FILEDESC); 516 if (ret < 0) { 517 syslog(LOG_ERROR, "sig_sem => %d", ret); 518 } 519 452 520 if (fp->readevt_w == fp->readevt_r) fp->readevt_w++; 453 521 … … 484 552 struct _IO_FILE *fp = udpid_to_fd(cepid); 485 553 FLGPTN flgptn = 0; 554 int len; 486 555 487 556 if (fp == NULL) … … 492 561 493 562 switch (fncd) { 563 case TEV_UDP_RCV_DAT: 564 { 565 T_UDP_RCV_DAT_PARA *udppara = (T_UDP_RCV_DAT_PARA *)p_parblk; 566 len = udppara->len; 567 if (len <= 0) 568 return E_OK; 569 570 ER ret = wai_sem(SEM_FILEDESC); 571 if (ret < 0) { 572 syslog(LOG_ERROR, "wai_sem => %d", ret); 573 } 574 fp->psock->len = len; 575 if (fp->psock->input != NULL) { 576 ret = rel_net_buf(fp->psock->input); 577 if (ret < 0) { 578 syslog(LOG_ERROR, "rel_net_buf => %d", ret); 579 } 580 } 581 fp->psock->input = udppara->input; 582 fp->psock->buf = GET_UDP_SDU(udppara->input, udppara->off); 583 memset(&fp->psock->raddr4, 0, sizeof(fp->psock->raddr4)); 584 fp->psock->raddr4.sin_family = AF_INET; 585 fp->psock->raddr4.sin_port = htons(udppara->rep4.portno); 586 fp->psock->raddr4.sin_addr.s_addr = htonl(udppara->rep4.ipaddr); 587 udppara->input->flags |= NB_FLG_NOREL_IFOUT; 588 ret = sig_sem(SEM_FILEDESC); 589 if (ret < 0) { 590 syslog(LOG_ERROR, "sig_sem => %d", ret); 591 } 592 593 if (fp->readevt_w == fp->readevt_r) fp->readevt_w++; 594 595 set_flg(FLG_SELECT_WAIT, flgptn); 596 return E_OK; 597 } 494 598 case TFN_UDP_CRE_CEP: 599 return E_OK; 600 495 601 case TFN_UDP_RCV_DAT: 602 len = *(int *)p_parblk; 603 if (len <= 0) 604 return E_OK; 605 496 606 if (fp->readevt_w == fp->readevt_r) fp->readevt_w++; 497 607 … … 524 634 ER shell_get_evts(struct fd_events *evts, TMO tmout) 525 635 { 526 ER ret;527 FLGPTN waitptn, flgptn = 0, readfds = 0, writefds = 0;528 struct _IO_FILE *fp = NULL;529 636 int count = 0; 530 531 stdio_update_evts(); 637 SYSTIM prev, now; 638 639 get_tim(&prev); 640 641 for (;;) { 642 ER ret; 643 FLGPTN waitptn, flgptn, readfds = 0, writefds = 0; 644 struct _IO_FILE *fp = NULL; 645 646 stdio_update_evts(); 532 647 533 648 #ifndef NTSHELL_NO_SOCKET 534 waitptn = *((FLGPTN *)&evts->errorfds);649 waitptn = *((FLGPTN *)&evts->errorfds); 535 650 #else 536 waitptn = *((FLGPTN *)&evts->readfds) | *((FLGPTN *)&evts->errorfds);651 waitptn = *((FLGPTN *)&evts->readfds) | *((FLGPTN *)&evts->errorfds); 537 652 #endif 538 for (int fd = 0; fd < fd_table_count; fd++) {539 fp = &fd_table[fd];653 for (int fd = 0; fd < fd_table_count; fd++) { 654 fp = &fd_table[fd]; 540 655 541 656 #ifndef NTSHELL_NO_SOCKET 542 if (FD_ISSET(fd, &evts->readfds)) { 543 if ((fp->type == IO_TYPE_TCP) 544 && (GET_TCP_CEP(fp->psock->cepid)->rwbuf_count > 0)) { 545 FD_SET(fd, (fd_set *)&readfds); 546 count++; 547 if (fp->readevt_w == fp->readevt_r) fp->readevt_r--; 657 if (FD_ISSET(fd, &evts->readfds)) { 658 if ((fp->type == IO_TYPE_TCP) && (fp->psock->cepid != 0)) { 659 if (fp->psock->len == 0) { 660 ret = tcp_rcv_buf(fp->psock->cepid, &fp->psock->input, TMO_NBLK); 661 if ((ret != E_WBLK) && (ret != E_OBJ) && (ret < 0)) { 662 syslog(LOG_ERROR, "tcp_rcv_buf => %d", ret); 663 //return ret; 664 } 665 if (ret > 0) { 666 ret = wai_sem(SEM_FILEDESC); 667 if (ret < 0) { 668 syslog(LOG_ERROR, "wai_sem => %d", ret); 669 } 670 fp->psock->len += ret; 671 ret = sig_sem(SEM_FILEDESC); 672 if (ret < 0) { 673 syslog(LOG_ERROR, "sig_sem => %d", ret); 674 } 675 } 676 } 677 else ret = 1; 678 if (ret > 0) { 679 FD_SET(fd, (fd_set *)&readfds); 680 count++; 681 if (fp->readevt_w == fp->readevt_r) fp->readevt_r--; 682 } 683 } 684 else if ((fp->type == IO_TYPE_UDP) && (fp->psock->cepid != 0)) { 685 if (fp->psock->input != NULL) { 686 FD_SET(fd, (fd_set *)&readfds); 687 count++; 688 if (fp->readevt_w == fp->readevt_r) fp->readevt_r--; 689 } 690 } 691 else { 692 FD_SET(fd, (fd_set *)&waitptn); 693 } 548 694 } 549 else { 550 FD_SET(fd, (fd_set *)&waitptn); 695 #endif 696 if (FD_ISSET(fd, &evts->writefds)) { 697 if (fp->writeevt_w == fp->writeevt_r) { 698 FD_SET(fd, (fd_set *)&writefds); 699 count++; 700 if (fp->writeevt_w == fp->writeevt_r) fp->writeevt_r--; 701 } 702 else { 703 FD_SET(fd, (fd_set *)&waitptn); 704 } 551 705 } 552 706 } 553 #endif 554 if (FD_ISSET(fd, &evts->writefds)) { 555 if (fp->writable) { 556 FD_SET(fd, (fd_set *)&writefds); 707 memset(evts, 0, sizeof(*evts)); 708 709 if (waitptn == 0) { 710 memcpy(&evts->readfds, &readfds, sizeof(evts->readfds)); 711 memcpy(&evts->writefds, &writefds, sizeof(evts->writefds)); 712 evts->count = count; 713 return E_OK; 714 } 715 else if ((readfds | writefds) != 0) { 716 set_flg(FLG_SELECT_WAIT, (readfds | writefds)); 717 } 718 719 /* イベント待ち */ 720 flgptn = 0; 721 ret = twai_flg(FLG_SELECT_WAIT, waitptn, TWF_ORW, &flgptn, tmout); 722 if (ret != E_OK) { 723 if (ret != E_TMOUT) { 724 syslog(LOG_ERROR, "twai_flg => %d", ret); 725 return ret; 726 } 727 728 stdio_flgptn(&flgptn); 729 730 if (flgptn == 0) 731 return E_TMOUT; 732 } 733 flgptn &= waitptn; 734 735 /* 受け取ったフラグのみクリア */ 736 ret = clr_flg(FLG_SELECT_WAIT, ~flgptn); 737 if (ret != E_OK) { 738 syslog(LOG_ERROR, "clr_flg => %d", ret); 739 } 740 741 count = 0; 742 for (int fd = 0; fd < fd_table_count; fd++) { 743 if (!FD_ISSET(fd, (fd_set *)&waitptn)) 744 continue; 745 746 fp = &fd_table[fd]; 747 748 if (fp->readevt_w != fp->readevt_r) { 749 fp->readevt_r++; 750 FD_SET(fd, &evts->readfds); 557 751 count++; 558 752 } 559 else { 560 FD_SET(fd, (fd_set *)&waitptn); 753 if (fp->writeevt_w != fp->writeevt_r) { 754 fp->writeevt_r++; 755 fp->writable = 1; 561 756 } 562 } 563 } 564 memset(evts, 0, sizeof(*evts)); 565 566 if (waitptn == 0) { 567 memcpy(&evts->readfds, &readfds, sizeof(evts->readfds)); 568 memcpy(&evts->writefds, &writefds, sizeof(evts->writefds)); 569 evts->count = count; 570 return E_OK; 571 } 572 else if ((readfds | writefds) != 0){ 573 set_flg(FLG_SELECT_WAIT, (readfds | writefds)); 574 } 575 576 /* イベント待ち */ 577 ret = twai_flg(FLG_SELECT_WAIT, waitptn, TWF_ORW, &flgptn, tmout); 578 if (ret != E_OK) { 579 if (ret != E_TMOUT) { 580 syslog(LOG_ERROR, "twai_flg => %d", ret); 581 return ret; 582 } 583 584 stdio_flgptn(&flgptn); 585 586 if (flgptn == 0) 757 if (fp->writable) { 758 FD_SET(fd, &evts->writefds); 759 count++; 760 } 761 if (fp->errorevt_w != fp->errorevt_r) { 762 fp->errorevt_r++; 763 FD_SET(fd, &evts->errorfds); 764 count++; 765 } 766 } 767 768 if (count > 0) 769 break; 770 771 get_tim(&now); 772 773 SYSTIM elapse = now - prev; 774 if (elapse > tmout) 587 775 return E_TMOUT; 588 } 589 flgptn &= waitptn; 590 591 /* 受け取ったフラグのみクリア */ 592 ret = clr_flg(FLG_SELECT_WAIT, ~flgptn); 593 if (ret != E_OK) { 594 syslog(LOG_ERROR, "clr_flg => %d", ret); 595 } 596 597 count = 0; 598 for (int fd = 0; fd < fd_table_count; fd++) { 599 if (!FD_ISSET(fd, (fd_set *)&waitptn)) 600 continue; 601 602 fp = &fd_table[fd]; 603 604 if (fp->readevt_w != fp->readevt_r) { 605 fp->readevt_r++; 606 FD_SET(fd, &evts->readfds); 607 count++; 608 } 609 if (fp->writeevt_w != fp->writeevt_r) { 610 fp->writeevt_r++; 611 fp->writable = 1; 612 } 613 if (fp->writable) { 614 FD_SET(fd, &evts->writefds); 615 count++; 616 } 617 if (fp->errorevt_w != fp->errorevt_r) { 618 fp->errorevt_r++; 619 FD_SET(fd, &evts->errorfds); 620 count++; 621 } 622 } 776 777 prev = now; 778 tmout -= elapse; 779 } 780 623 781 evts->count = count; 624 782 … … 676 834 } 677 835 678 ssize_t shell_send(int fd, const void *buf, size_t len, int flags)679 {680 return -ENOMEM;681 }682 683 836 ssize_t shell_sendto(int fd, const void *buf, size_t len, int flags, const struct sockaddr *addr, socklen_t alen) 684 837 { … … 691 844 } 692 845 693 ssize_t shell_recv(int fd, void *buf, size_t len, int flags) 694 { 695 return -ENOMEM; 696 } 697 698 ssize_t shell_recvfrom(int fd, void *buf, size_t len, int flags, struct sockaddr *__restrict addr, socklen_t *__restrict alen) 846 ssize_t shell_recvfrom(int fd, void *__restrict buf, size_t len, int flags, struct sockaddr *__restrict addr, socklen_t *__restrict alen) 699 847 { 700 848 return -ENOMEM; -
asp3_tinet_ecnl_rx/trunk/ntshell/src/mbed_api.c
r337 r364 1 1 /* 2 2 * TOPPERS ECHONET Lite Communication Middleware 3 * 4 * Copyright (C) 2014-201 7Cores Co., Ltd. Japan5 * 3 * 4 * Copyright (C) 2014-2018 Cores Co., Ltd. Japan 5 * 6 6 * 上記著作権者は,以下の(1)~(4)の条件を満たす場合に限り,本ソフトウェ 7 7 * ア(本ソフトウェアを改変したものを含む.以下同じ)を使用・複製・改 … … 26 26 * 由に基づく請求からも,上記著作権者およびTOPPERSプロジェクトを 27 27 * 免責すること. 28 * 28 * 29 29 * 本ソフトウェアは,無保証で提供されているものである.上記著作権者お 30 30 * よびTOPPERSプロジェクトは,本ソフトウェアに関して,特定の使用目的 … … 32 32 * アの利用により直接的または間接的に生じたいかなる損害に関しても,そ 33 33 * の責任を負わない. 34 * 34 * 35 35 * @(#) $Id$ 36 36 */ … … 42 42 #include "rx630.h" 43 43 #include "ff.h" 44 #include "target_stddef.h" 45 #include "target_kernel_impl.h" 46 #include "scif.h" 44 47 45 48 /* PWM出力(490Hz) */ … … 64 67 void gpio_init(gpio_t *obj, PinName pin) 65 68 { 69 obj->pin = pin; 70 obj->dir = PIN_INPUT; 71 obj->mode = PullDefault; 66 72 } 67 73 … … 83 89 /* 汎用入出力ポートに設定 */ 84 90 switch (pin) { 85 case 0:91 case D0: 86 92 /* P21 */ 87 93 sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) & ~PORT_PMR_B1_BIT); 88 94 break; 89 case 1:95 case D1: 90 96 /* P20 */ 91 97 sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) & ~PORT_PMR_B0_BIT); 92 98 break; 93 case 2:99 case D2: 94 100 /* P22 */ 95 101 sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) & ~PORT_PMR_B2_BIT); 96 102 break; 97 case 3:103 case D3: 98 104 /* P23 */ 99 105 sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) & ~PORT_PMR_B3_BIT); 100 106 break; 101 case 4:107 case D4: 102 108 /* P24 */ 103 109 sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) & ~PORT_PMR_B4_BIT); 104 110 break; 105 case 5:111 case D5: 106 112 /* P25 */ 107 113 sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) & ~PORT_PMR_B5_BIT); 108 114 break; 109 case 6:115 case D6: 110 116 /* P32 */ 111 117 sil_wrb_mem(PORT3_PMR_ADDR, sil_reb_mem(PORT3_PMR_ADDR) & ~PORT_PMR_B2_BIT); 112 118 break; 113 case 7:119 case D7: 114 120 /* P33 */ 115 121 sil_wrb_mem(PORT3_PMR_ADDR, sil_reb_mem(PORT3_PMR_ADDR) & ~PORT_PMR_B3_BIT); 122 break; 123 default: 116 124 break; 117 125 } … … 124 132 switch (pin) { 125 133 /* P21/TIOCA3 */ 126 case 0:134 case D0: 127 135 if (gpio) { 128 136 /* P21端子機能制御レジスタ P21とする */ … … 136 144 break; 137 145 /* P20/TIOCB3 */ 138 case 1:146 case D1: 139 147 if (gpio) { 140 148 /* P20端子機能制御レジスタ P20とする */ … … 148 156 break; 149 157 /* P22/TIOCC3 */ 150 case 2:158 case D2: 151 159 if (gpio) { 152 160 /* P22端子機能制御レジスタ P22とする */ … … 160 168 break; 161 169 /* P23/TIOCD3 */ 162 case 3:170 case D3: 163 171 if (gpio) { 164 172 /* P23端子機能制御レジスタ P23とする */ … … 172 180 break; 173 181 /* P24/TIOCB4 */ 174 case 4:182 case D4: 175 183 if (gpio) { 176 184 /* P24端子機能制御レジスタ P24とする */ … … 184 192 break; 185 193 /* P25/TIOCA4 */ 186 case 5:194 case D5: 187 195 if (gpio) { 188 196 /* P25端子機能制御レジスタ P25とする */ … … 196 204 break; 197 205 /* P32/TIOCC0 */ 198 case 6:206 case D6: 199 207 if (gpio) { 200 208 /* P32端子機能制御レジスタ P32とする */ … … 208 216 break; 209 217 /* P33/TIOCD0 */ 210 case 7:218 case D7: 211 219 if (gpio) { 212 220 /* P33端子機能制御レジスタ P33とする */ … … 218 226 } 219 227 result = E_OK; 228 break; 229 default: 220 230 break; 221 231 } … … 228 238 switch (pin) { 229 239 /* P21/TIOCA3 */ 230 case 0:240 case D0: 231 241 sil_wrb_mem(PORT2_PDR_ADDR, sil_reb_mem(PORT2_PDR_ADDR) | PORT_PDR_B1_BIT); 232 242 sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) | PORT_PMR_B1_BIT); 233 243 break; 234 244 /* P20/TIOCB3 */ 235 case 1:245 case D1: 236 246 sil_wrb_mem(PORT2_PDR_ADDR, sil_reb_mem(PORT2_PDR_ADDR) | PORT_PDR_B0_BIT); 237 247 sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) | PORT_PMR_B0_BIT); 238 248 break; 239 249 /* P22/TIOCC3 */ 240 case 2:250 case D2: 241 251 sil_wrb_mem(PORT2_PDR_ADDR, sil_reb_mem(PORT2_PDR_ADDR) | PORT_PDR_B2_BIT); 242 252 sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) | PORT_PMR_B2_BIT); 243 253 break; 244 254 /* P23/TIOCD3 */ 245 case 3:255 case D3: 246 256 sil_wrb_mem(PORT2_PDR_ADDR, sil_reb_mem(PORT2_PDR_ADDR) | PORT_PDR_B3_BIT); 247 257 sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) | PORT_PMR_B3_BIT); 248 258 break; 249 259 /* P24/TIOCB4 */ 250 case 4:260 case D4: 251 261 sil_wrb_mem(PORT2_PDR_ADDR, sil_reb_mem(PORT2_PDR_ADDR) | PORT_PDR_B4_BIT); 252 262 sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) | PORT_PMR_B4_BIT); 253 263 break; 254 264 /* P25/TIOCA4 */ 255 case 5:265 case D5: 256 266 sil_wrb_mem(PORT2_PDR_ADDR, sil_reb_mem(PORT2_PDR_ADDR) | PORT_PDR_B5_BIT); 257 267 sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) | PORT_PMR_B5_BIT); 258 268 break; 259 269 /* P32/TIOCC0 */ 260 case 6:270 case D6: 261 271 sil_wrb_mem(PORT3_PDR_ADDR, sil_reb_mem(PORT3_PDR_ADDR) | PORT_PDR_B2_BIT); 262 272 sil_wrb_mem(PORT3_PMR_ADDR, sil_reb_mem(PORT3_PMR_ADDR) | PORT_PMR_B2_BIT); 263 273 break; 264 274 /* P33/TIOCD0 */ 265 case 7:275 case D7: 266 276 sil_wrb_mem(PORT3_PDR_ADDR, sil_reb_mem(PORT3_PDR_ADDR) | PORT_PDR_B3_BIT); 267 277 sil_wrb_mem(PORT3_PMR_ADDR, sil_reb_mem(PORT3_PMR_ADDR) | PORT_PMR_B3_BIT); 268 278 break; 279 default: 280 break; 269 281 } 270 282 } … … 280 292 281 293 switch (obj->pin) { 282 case 0:294 case D0: 283 295 /* P21 */ 284 296 pdr = PORT2_PDR_ADDR; bit = PORT_PDR_B1_BIT; 285 297 break; 286 case 1:298 case D1: 287 299 /* P20 */ 288 300 pdr = PORT2_PDR_ADDR; bit = PORT_PDR_B0_BIT; 289 301 break; 290 case 2:302 case D2: 291 303 /* P22 */ 292 304 pdr = PORT2_PDR_ADDR; bit = PORT_PDR_B2_BIT; 293 305 break; 294 case 3:306 case D3: 295 307 /* P23 */ 296 308 pdr = PORT2_PDR_ADDR; bit = PORT_PDR_B3_BIT; 297 309 break; 298 case 4:310 case D4: 299 311 /* P24 */ 300 312 pdr = PORT2_PDR_ADDR; bit = PORT_PDR_B4_BIT; 301 313 break; 302 case 5:314 case D5: 303 315 /* P25 */ 304 316 pdr = PORT2_PDR_ADDR; bit = PORT_PDR_B5_BIT; 305 317 break; 306 case 6:318 case D6: 307 319 /* P32 */ 308 320 pdr = PORT3_PDR_ADDR; bit = PORT_PDR_B2_BIT; 309 321 break; 310 case 7:322 case D7: 311 323 /* P33 */ 312 324 pdr = PORT3_PDR_ADDR; bit = PORT_PDR_B3_BIT; 313 325 break; 314 case 8:326 case D8: 315 327 /* PC2 */ 316 328 pdr = PORTC_PDR_ADDR; bit = PORT_PDR_B2_BIT; 317 329 break; 318 case 9:330 case D9: 319 331 /* PC3 */ 320 332 pdr = PORTC_PDR_ADDR; bit = PORT_PDR_B3_BIT; 321 333 break; 322 case 10:334 case D10: 323 335 /* PC4 */ 324 336 pdr = PORTC_PDR_ADDR; bit = PORT_PDR_B4_BIT; 325 337 break; 326 case 11:338 case D11: 327 339 /* PC6 */ 328 340 pdr = PORTC_PDR_ADDR; bit = PORT_PDR_B6_BIT; 329 341 break; 330 case 12:342 case D12: 331 343 /* PC7 */ 332 344 pdr = PORTC_PDR_ADDR; bit = PORT_PDR_B7_BIT; 333 345 break; 334 case 13:346 case D13: 335 347 /* PC5 */ 336 348 pdr = PORTC_PDR_ADDR; bit = PORT_PDR_B5_BIT; … … 349 361 sil_wrb_mem(pdr, sil_reb_mem(pdr) | bit); 350 362 break; 363 default: 364 break; 351 365 } 352 366 … … 387 401 388 402 switch (obj->pin) { 389 case 0:403 case D0: 390 404 /* P21 */ 391 405 podr = PORT2_PODR_ADDR; bit = PORT_PODR_B1_BIT; 392 406 break; 393 case 1:407 case D1: 394 408 /* P20 */ 395 409 podr = PORT2_PODR_ADDR; bit = PORT_PODR_B0_BIT; 396 410 break; 397 case 2:411 case D2: 398 412 /* P22 */ 399 413 podr = PORT2_PODR_ADDR; bit = PORT_PODR_B2_BIT; 400 414 break; 401 case 3:415 case D3: 402 416 /* P23 */ 403 417 podr = PORT2_PODR_ADDR; bit = PORT_PODR_B3_BIT; 404 418 break; 405 case 4:419 case D4: 406 420 /* P24 */ 407 421 podr = PORT2_PODR_ADDR; bit = PORT_PODR_B4_BIT; 408 422 break; 409 case 5:423 case D5: 410 424 /* P25 */ 411 425 podr = PORT2_PODR_ADDR; bit = PORT_PODR_B5_BIT; 412 426 break; 413 case 6:427 case D6: 414 428 /* P32 */ 415 429 podr = PORT3_PODR_ADDR; bit = PORT_PODR_B2_BIT; 416 430 break; 417 case 7:431 case D7: 418 432 /* P33 */ 419 433 podr = PORT3_PODR_ADDR; bit = PORT_PODR_B3_BIT; 420 434 break; 421 case 8:435 case D8: 422 436 /* PC2 */ 423 437 podr = PORTC_PODR_ADDR; bit = PORT_PODR_B2_BIT; 424 438 break; 425 case 9:439 case D9: 426 440 /* PC3 */ 427 441 podr = PORTC_PODR_ADDR; bit = PORT_PODR_B3_BIT; 428 442 break; 429 case 10:443 case D10: 430 444 /* PC4 */ 431 445 podr = PORTC_PODR_ADDR; bit = PORT_PODR_B4_BIT; 432 446 break; 433 case 11:447 case D11: 434 448 /* PC6 */ 435 449 podr = PORTC_PODR_ADDR; bit = PORT_PODR_B6_BIT; 436 450 break; 437 case 12:451 case D12: 438 452 /* PC7 */ 439 453 podr = PORTC_PODR_ADDR; bit = PORT_PODR_B7_BIT; 440 454 break; 441 case 13:455 case D13: 442 456 /* PC5 */ 443 457 podr = PORTC_PODR_ADDR; bit = PORT_PODR_B5_BIT; … … 463 477 464 478 switch (obj->pin) { 465 case 0:479 case D0: 466 480 /* P21 */ 467 481 pidr = PORT2_PIDR_ADDR; bit = PORT_PIDR_B1_BIT; 468 482 break; 469 case 1:483 case D1: 470 484 /* P20 */ 471 485 pidr = PORT2_PIDR_ADDR; bit = PORT_PIDR_B0_BIT; 472 486 break; 473 case 2:487 case D2: 474 488 /* P22 */ 475 489 pidr = PORT2_PIDR_ADDR; bit = PORT_PIDR_B2_BIT; 476 490 break; 477 case 3:491 case D3: 478 492 /* P23 */ 479 493 pidr = PORT2_PIDR_ADDR; bit = PORT_PIDR_B3_BIT; 480 494 break; 481 case 4:495 case D4: 482 496 /* P24 */ 483 497 pidr = PORT2_PIDR_ADDR; bit = PORT_PIDR_B4_BIT; 484 498 break; 485 case 5:499 case D5: 486 500 /* P25 */ 487 501 pidr = PORT2_PIDR_ADDR; bit = PORT_PIDR_B5_BIT; 488 502 break; 489 case 6:503 case D6: 490 504 /* P32 */ 491 505 pidr = PORT3_PIDR_ADDR; bit = PORT_PIDR_B2_BIT; 492 506 break; 493 case 7:507 case D7: 494 508 /* P33 */ 495 509 pidr = PORT3_PIDR_ADDR; bit = PORT_PIDR_B3_BIT; 496 510 break; 497 case 8:511 case D8: 498 512 /* PC2 */ 499 513 pidr = PORTC_PIDR_ADDR; bit = PORT_PIDR_B2_BIT; 500 514 break; 501 case 9:515 case D9: 502 516 /* PC3 */ 503 517 pidr = PORTC_PIDR_ADDR; bit = PORT_PIDR_B3_BIT; 504 518 break; 505 case 10:519 case D10: 506 520 /* PC4 */ 507 521 pidr = PORTC_PIDR_ADDR; bit = PORT_PIDR_B4_BIT; 508 522 break; 509 case 11:523 case D11: 510 524 /* PC6 */ 511 525 pidr = PORTC_PIDR_ADDR; bit = PORT_PIDR_B6_BIT; 512 526 break; 513 case 12:527 case D12: 514 528 /* PC7 */ 515 529 pidr = PORTC_PIDR_ADDR; bit = PORT_PIDR_B7_BIT; 516 530 break; 517 case 13:531 case D13: 518 532 /* PC5 */ 519 533 pidr = PORTC_PIDR_ADDR; bit = PORT_PIDR_B5_BIT; … … 581 595 582 596 switch (obj->pin) { 583 case 14:597 case A0: 584 598 /* *value = sil_reh_mem(S12AD_ADDR0_ADDR); */ 585 599 result = (arduino_ad_avelage[0] / (arduino_ad_table_count)); 586 600 break; 587 case 15:601 case A1: 588 602 /* *value = sil_reh_mem(S12AD_ADDR1_ADDR); */ 589 603 result = (arduino_ad_avelage[1] / (arduino_ad_table_count)); 590 604 break; 591 case 16:605 case A2: 592 606 /* *value = sil_reh_mem(S12AD_ADDR2_ADDR); */ 593 607 result = (arduino_ad_avelage[2] / (arduino_ad_table_count)); 594 608 break; 595 case 17:609 case A3: 596 610 /* *value = sil_reh_mem(S12AD_ADDR3_ADDR); */ 597 611 result = (arduino_ad_avelage[3] / (arduino_ad_table_count)); 598 612 break; 599 case 18:613 case A4: 600 614 /* *value = sil_reh_mem(S12AD_ADDR4_ADDR); */ 601 615 result = (arduino_ad_avelage[4] / (arduino_ad_table_count)); 602 616 break; 603 case 19:617 case A5: 604 618 /* *value = sil_reh_mem(S12AD_ADDR5_ADDR); */ 605 619 result = (arduino_ad_avelage[5] / (arduino_ad_table_count)); 606 620 break; 607 case 20:621 case A6: 608 622 /* *value = sil_reh_mem(S12AD_ADDR6_ADDR); */ 609 623 result = (arduino_ad_avelage[6] / (arduino_ad_table_count)); 610 624 break; 611 case 21:625 case A7: 612 626 /* *value = sil_reh_mem(S12AD_ADDR7_ADDR); */ 613 627 result = (arduino_ad_avelage[7] / (arduino_ad_table_count)); 614 628 break; 629 default: 630 return 0; 615 631 } 616 632 … … 677 693 /* 波形出力レベルの選択 */ 678 694 sil_wrb_mem(TPU0_TIORL_ADDR, (5 << TPU_TIORL_IOC_OFFSET) | (5 << TPU_TIORL_IOD_OFFSET)); 679 sil_wrb_mem(TPU3_TIORH_ADDR, (5 << TPU_TIOR L_IOA_OFFSET) | (5 << TPU_TIORL_IOB_OFFSET));695 sil_wrb_mem(TPU3_TIORH_ADDR, (5 << TPU_TIORH_IOA_OFFSET) | (5 << TPU_TIORH_IOB_OFFSET)); 680 696 sil_wrb_mem(TPU3_TIORL_ADDR, (5 << TPU_TIORL_IOC_OFFSET) | (5 << TPU_TIORL_IOD_OFFSET)); 681 sil_wrb_mem(TPU4_TIOR_ADDR, (5 << TPU_TIOR L_IOA_OFFSET) | (5 << TPU_TIORL_IOB_OFFSET));697 sil_wrb_mem(TPU4_TIOR_ADDR, (5 << TPU_TIOR_IOA_OFFSET) | (5 << TPU_TIOR_IOB_OFFSET)); 682 698 /* TGRyの設定 */ 683 699 sil_wrh_mem(TPU0_TGRA_ADDR, TPU_BASE_COUNTER); … … 714 730 } 715 731 732 typedef enum { 733 sciSerial, 734 sciI2C, 735 sciSPIM, 736 sciSPIS, 737 } sci_mode_t; 738 739 void sci_enable(void *base_address, sci_mode_t mode) 740 { 741 /* 742 * モジュールストップ機能の設定 743 */ 744 sil_wrh_mem(SYSTEM_PRCR_ADDR, (uint16_t)0xA502); /* 書込み許可 */ 745 sil_wrw_mem(SYSTEM_MSTPCRB_ADDR, 746 sil_rew_mem(SYSTEM_MSTPCRB_ADDR) & ~SCI_MSTPCRB_BIT(base_address)); 747 sil_wrh_mem(SYSTEM_PRCR_ADDR, (uint16_t)0xA500); /* 書込み禁止 */ 748 749 /* 送受信禁止, SCKn端子は入出力ポートとして使用 */ 750 sil_wrb_mem(SCI_SCR(base_address), 0x00U); 751 752 switch ((uint32_t)base_address) { 753 /* TXD/SDA/MOSI:P20, RXD/SCL/MISO:P21, SCK:P22 */ 754 case SCI0_BASE: 755 switch (mode) { 756 case sciSerial: 757 /* HIGH状態に設定 */ 758 sil_wrb_mem(PORT2_PODR_ADDR, 759 sil_reb_mem(PORT2_PODR_ADDR) | PORT_PODR_B0_BIT | PORT_PODR_B1_BIT); 760 /* TX出力/RX入力ポート設定 */ 761 sil_wrb_mem(PORT2_PDR_ADDR, (sil_reb_mem(PORT2_PDR_ADDR) | PORT_PDR_B0_BIT) & ~PORT_PDR_B1_BIT); 762 /* プルアップ無効 */ 763 sil_wrb_mem(PORT2_PCR_ADDR, sil_reb_mem(PORT2_PCR_ADDR) & ~(PORT_PCR_B0_BIT | PORT_PCR_B1_BIT)); 764 /* RX CMOS */ 765 sil_wrb_mem(PORT2_ODR0_ADDR, 766 (sil_reb_mem(PORT2_ODR0_ADDR) & ~(PORT_ODR_Pm0_MASK | PORT_ODR_Pm1_MASK)) 767 | (PORT_ODR_CMOS << PORT_ODR_Pm0_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm1_OFFSET)); 768 /* 周辺機能として使用 */ 769 sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) | PORT_PMR_B0_BIT | PORT_PMR_B1_BIT); 770 break; 771 case sciI2C: 772 /* HIGH状態に設定 */ 773 sil_wrb_mem(PORT2_PODR_ADDR, 774 sil_reb_mem(PORT2_PODR_ADDR) | PORT_PODR_B0_BIT | PORT_PODR_B1_BIT); 775 /* SCL,SDA 出力ポート設定 */ 776 sil_wrb_mem(PORT2_PDR_ADDR, sil_reb_mem(PORT2_PDR_ADDR) | PORT_PDR_B0_BIT | PORT_PDR_B1_BIT); 777 /* プルアップ有効 */ 778 sil_wrb_mem(PORT2_PCR_ADDR, sil_reb_mem(PORT2_PCR_ADDR) | PORT_PCR_B0_BIT | PORT_PCR_B1_BIT); 779 /* Nチャネルオープンドレイン */ 780 sil_wrb_mem(PORT2_ODR0_ADDR, 781 (sil_reb_mem(PORT2_ODR0_ADDR) & ~(PORT_ODR_Pm0_MASK | PORT_ODR_Pm1_MASK)) 782 | (PORT_ODR_NCH_OPEN_DRAIN << PORT_ODR_Pm0_OFFSET) | (PORT_ODR_NCH_OPEN_DRAIN << PORT_ODR_Pm1_OFFSET)); 783 /* 周辺機能として使用 */ 784 sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) | PORT_PMR_B0_BIT | PORT_PMR_B1_BIT); 785 break; 786 case sciSPIM: 787 /* HIGH状態に設定 */ 788 sil_wrb_mem(PORT2_PODR_ADDR, 789 sil_reb_mem(PORT2_PODR_ADDR) | PORT_PODR_B0_BIT | PORT_PODR_B1_BIT | PORT_PODR_B2_BIT); 790 /* MOSI出力/MISO入力/SCK入出力ポート設定 */ 791 sil_wrb_mem(PORT2_PDR_ADDR, (sil_reb_mem(PORT2_PDR_ADDR) | PORT_PDR_B0_BIT | PORT_PDR_B2_BIT) & ~PORT_PDR_B1_BIT); 792 /* プルアップ無効 */ 793 sil_wrb_mem(PORT2_PCR_ADDR, sil_reb_mem(PORT2_PCR_ADDR) & ~(PORT_PCR_B0_BIT | PORT_PCR_B1_BIT | PORT_PCR_B2_BIT)); 794 /* MISO CMOS */ 795 sil_wrb_mem(PORT2_ODR0_ADDR, 796 (sil_reb_mem(PORT2_ODR0_ADDR) & ~(PORT_ODR_Pm0_MASK | PORT_ODR_Pm1_MASK | PORT_ODR_Pm2_MASK)) 797 | (PORT_ODR_CMOS << PORT_ODR_Pm0_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm1_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm2_OFFSET)); 798 /* 周辺機能として使用 */ 799 sil_wrb_mem(PORT2_PMR_ADDR, sil_reb_mem(PORT2_PMR_ADDR) | PORT_PMR_B0_BIT | PORT_PMR_B1_BIT | PORT_PMR_B2_BIT); 800 break; 801 } 802 /* 書き込みプロテクトレジスタの設定 PFSWEビットへの書き込みを許可 */ 803 sil_wrb_mem(MPC_PWPR_ADDR, 0x00); 804 /* 書き込みプロテクトレジスタの設定 PxxFSレジスタへの書き込みを許可 */ 805 sil_wrb_mem(MPC_PWPR_ADDR, 0x40); 806 807 /* P20端子機能制御レジスタ TXD0/SMOSI0/SSDA0とする */ 808 sil_wrb_mem(MPC_P20PFS_ADDR, 0x0A); 809 /* P21端子機能制御レジスタ RXD0/SMISO0/SSCL0とする */ 810 sil_wrb_mem(MPC_P21PFS_ADDR, 0x0A); 811 if (mode == sciSPIM) { 812 /* P22端子機能制御レジスタ SCK0とする */ 813 sil_wrb_mem(MPC_P22PFS_ADDR, 0x0A); 814 } 815 816 /* 書き込みプロテクトレジスタの設定 書き込みを禁止 */ 817 sil_wrb_mem(MPC_PWPR_ADDR, 0x80); 818 break; 819 /* TXD/SDA/MOSI:P50, RXD/SCL/MISO:P52, SCK:P51 */ 820 case SCI2_BASE: 821 switch (mode) { 822 case sciSerial: 823 /* HIGH状態に設定 */ 824 sil_wrb_mem(PORT5_PODR_ADDR, 825 sil_reb_mem(PORT5_PODR_ADDR) | PORT_PODR_B0_BIT | PORT_PODR_B2_BIT); 826 /* TX出力/RX入力ポート設定 */ 827 sil_wrb_mem(PORT5_PDR_ADDR, (sil_reb_mem(PORT5_PDR_ADDR) | PORT_PDR_B0_BIT) & ~PORT_PDR_B2_BIT); 828 /* プルアップ無効 */ 829 sil_wrb_mem(PORT5_PCR_ADDR, sil_reb_mem(PORT5_PCR_ADDR) & ~(PORT_PCR_B0_BIT | PORT_PCR_B2_BIT)); 830 /* RX CMOS */ 831 sil_wrb_mem(PORT5_ODR0_ADDR, 832 (sil_reb_mem(PORT5_ODR0_ADDR) & ~(PORT_ODR_Pm0_MASK | PORT_ODR_Pm2_MASK)) 833 | (PORT_ODR_CMOS << PORT_ODR_Pm0_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm2_OFFSET)); 834 /* 周辺機能として使用 */ 835 sil_wrb_mem(PORT5_PMR_ADDR, sil_reb_mem(PORT5_PMR_ADDR) | PORT_PMR_B0_BIT | PORT_PMR_B2_BIT); 836 break; 837 case sciI2C: 838 /* HIGH状態に設定 */ 839 sil_wrb_mem(PORT5_PODR_ADDR, 840 sil_reb_mem(PORT5_PODR_ADDR) | PORT_PODR_B0_BIT | PORT_PODR_B2_BIT); 841 /* SCL,SDA 出力ポート設定 */ 842 sil_wrb_mem(PORT5_PDR_ADDR, sil_reb_mem(PORT5_PDR_ADDR) | PORT_PDR_B0_BIT | PORT_PDR_B2_BIT); 843 /* プルアップ有効 */ 844 sil_wrb_mem(PORT5_PCR_ADDR, sil_reb_mem(PORT5_PCR_ADDR) | PORT_PCR_B0_BIT | PORT_PCR_B2_BIT); 845 /* Nチャネルオープンドレイン */ 846 sil_wrb_mem(PORT5_ODR0_ADDR, 847 (sil_reb_mem(PORT5_ODR0_ADDR) & ~(PORT_ODR_Pm0_MASK | PORT_ODR_Pm2_MASK)) 848 | (PORT_ODR_NCH_OPEN_DRAIN << PORT_ODR_Pm0_OFFSET) | (PORT_ODR_NCH_OPEN_DRAIN << PORT_ODR_Pm2_OFFSET)); 849 /* 周辺機能として使用 */ 850 sil_wrb_mem(PORT5_PMR_ADDR, sil_reb_mem(PORT5_PMR_ADDR) | PORT_PMR_B0_BIT | PORT_PMR_B2_BIT); 851 break; 852 case sciSPIM: 853 /* HIGH状態に設定 */ 854 sil_wrb_mem(PORT5_PODR_ADDR, 855 sil_reb_mem(PORT5_PODR_ADDR) | PORT_PODR_B0_BIT | PORT_PODR_B1_BIT | PORT_PODR_B2_BIT); 856 /* MOSI出力/MISO入力/SCK入出力ポート設定 */ 857 sil_wrb_mem(PORT5_PDR_ADDR, (sil_reb_mem(PORT5_PDR_ADDR) | PORT_PDR_B0_BIT | PORT_PDR_B1_BIT) & ~PORT_PDR_B2_BIT); 858 /* プルアップ無効 */ 859 sil_wrb_mem(PORT5_PCR_ADDR, sil_reb_mem(PORT5_PCR_ADDR) & ~(PORT_PCR_B0_BIT | PORT_PCR_B1_BIT | PORT_PCR_B2_BIT)); 860 /* MISO CMOS */ 861 sil_wrb_mem(PORT5_ODR0_ADDR, 862 (sil_reb_mem(PORT5_ODR0_ADDR) & ~(PORT_ODR_Pm0_MASK | PORT_ODR_Pm1_MASK | PORT_ODR_Pm2_MASK)) 863 | (PORT_ODR_CMOS << PORT_ODR_Pm0_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm1_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm2_OFFSET)); 864 /* 周辺機能として使用 */ 865 sil_wrb_mem(PORT5_PMR_ADDR, sil_reb_mem(PORT5_PMR_ADDR) | PORT_PMR_B0_BIT | PORT_PMR_B1_BIT | PORT_PMR_B1_BIT | PORT_PMR_B2_BIT); 866 break; 867 } 868 /* 書き込みプロテクトレジスタの設定 PFSWEビットへの書き込みを許可 */ 869 sil_wrb_mem(MPC_PWPR_ADDR, 0x00); 870 /* 書き込みプロテクトレジスタの設定 PxxFSレジスタへの書き込みを許可 */ 871 sil_wrb_mem(MPC_PWPR_ADDR, 0x40); 872 873 /* P50端子機能制御レジスタ SSDA2とする */ 874 sil_wrb_mem(MPC_P50PFS_ADDR, 0x0A); 875 /* P52端子機能制御レジスタ SSCL2とする */ 876 sil_wrb_mem(MPC_P52PFS_ADDR, 0x0A); 877 if (mode == sciSPIM) { 878 /* P51端子機能制御レジスタ SCK2とする */ 879 sil_wrb_mem(MPC_P51PFS_ADDR, 0x0A); 880 } 881 882 /* 書き込みプロテクトレジスタの設定 書き込みを禁止 */ 883 sil_wrb_mem(MPC_PWPR_ADDR, 0x80); 884 break; 885 /* TXD/SDA/MOSI:P32, RXD/SCL/MISO:P33, SCK:P34 */ 886 case SCI6_BASE: 887 switch (mode) { 888 case sciSerial: 889 /* HIGH状態に設定 */ 890 sil_wrb_mem(PORT3_PODR_ADDR, 891 sil_reb_mem(PORT3_PODR_ADDR) | PORT_PODR_B2_BIT | PORT_PODR_B3_BIT); 892 /* TX出力/RX入力ポート設定 */ 893 sil_wrb_mem(PORT3_PDR_ADDR, (sil_reb_mem(PORT3_PDR_ADDR) | PORT_PDR_B2_BIT) & ~PORT_PDR_B3_BIT); 894 /* プルアップ無効 */ 895 sil_wrb_mem(PORT3_PCR_ADDR, sil_reb_mem(PORT3_PCR_ADDR) & ~(PORT_PCR_B2_BIT | PORT_PCR_B3_BIT)); 896 /* RX CMOS */ 897 sil_wrb_mem(PORT3_ODR0_ADDR, 898 (sil_reb_mem(PORT3_ODR0_ADDR) & ~(PORT_ODR_Pm2_MASK | PORT_ODR_Pm3_MASK)) 899 | (PORT_ODR_CMOS << PORT_ODR_Pm2_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm3_OFFSET)); 900 /* 周辺機能として使用 */ 901 sil_wrb_mem(PORT3_PMR_ADDR, sil_reb_mem(PORT3_PMR_ADDR) | PORT_PMR_B2_BIT | PORT_PMR_B3_BIT); 902 break; 903 case sciI2C: 904 /* HIGH状態に設定 */ 905 sil_wrb_mem(PORT3_PODR_ADDR, 906 sil_reb_mem(PORT3_PODR_ADDR) | PORT_PODR_B2_BIT | PORT_PODR_B3_BIT); 907 /* SCL,SDA 出力ポート設定 */ 908 sil_wrb_mem(PORT3_PDR_ADDR, sil_reb_mem(PORT3_PDR_ADDR) | PORT_PDR_B2_BIT | PORT_PDR_B3_BIT); 909 /* プルアップ有効 */ 910 sil_wrb_mem(PORT3_PCR_ADDR, sil_reb_mem(PORT3_PCR_ADDR) | PORT_PCR_B2_BIT | PORT_PCR_B3_BIT); 911 /* Nチャネルオープンドレイン */ 912 sil_wrb_mem(PORT3_ODR0_ADDR, 913 (sil_reb_mem(PORT3_ODR0_ADDR) & ~(PORT_ODR_Pm2_MASK | PORT_ODR_Pm3_MASK)) 914 | (PORT_ODR_NCH_OPEN_DRAIN << PORT_ODR_Pm2_OFFSET) | (PORT_ODR_NCH_OPEN_DRAIN << PORT_ODR_Pm3_OFFSET)); 915 /* 周辺機能として使用 */ 916 sil_wrb_mem(PORT3_PMR_ADDR, sil_reb_mem(PORT3_PMR_ADDR) | PORT_PMR_B2_BIT | PORT_PMR_B3_BIT); 917 break; 918 case sciSPIM: 919 /* HIGH状態に設定 */ 920 sil_wrb_mem(PORT3_PODR_ADDR, 921 sil_reb_mem(PORT3_PODR_ADDR) | PORT_PODR_B2_BIT | PORT_PODR_B3_BIT | PORT_PODR_B4_BIT); 922 /* MOSI出力/MISO入力/SCK入出力ポート設定 */ 923 sil_wrb_mem(PORT3_PDR_ADDR, (sil_reb_mem(PORT3_PDR_ADDR) | PORT_PDR_B2_BIT | PORT_PDR_B4_BIT) & ~PORT_PDR_B3_BIT); 924 /* プルアップ無効 */ 925 sil_wrb_mem(PORT3_PCR_ADDR, sil_reb_mem(PORT3_PCR_ADDR) & ~(PORT_PCR_B2_BIT | PORT_PCR_B3_BIT | PORT_PCR_B4_BIT)); 926 /* MISO CMOS */ 927 sil_wrb_mem(PORT3_ODR0_ADDR, 928 (sil_reb_mem(PORT3_ODR0_ADDR) & ~(PORT_ODR_Pm2_MASK | PORT_ODR_Pm3_MASK | PORT_ODR_Pm4_MASK)) 929 | (PORT_ODR_CMOS << PORT_ODR_Pm2_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm3_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm4_OFFSET)); 930 /* 周辺機能として使用 */ 931 sil_wrb_mem(PORT3_PMR_ADDR, sil_reb_mem(PORT3_PMR_ADDR) | PORT_PMR_B2_BIT | PORT_PMR_B3_BIT | PORT_PMR_B4_BIT); 932 break; 933 } 934 935 /* 書き込みプロテクトレジスタの設定 PFSWEビットへの書き込みを許可 */ 936 sil_wrb_mem(MPC_PWPR_ADDR, 0x00); 937 /* 書き込みプロテクトレジスタの設定 PxxFSレジスタへの書き込みを許可 */ 938 sil_wrb_mem(MPC_PWPR_ADDR, 0x40); 939 940 /* P32端子機能制御レジスタ TXD6/SMOSI6/SSDA6とする */ 941 sil_wrb_mem(MPC_P32PFS_ADDR, 0x0A); 942 /* P33端子機能制御レジスタ RXD6/SMISO6/SSCL6とする */ 943 sil_wrb_mem(MPC_P33PFS_ADDR, 0x0A); 944 if (mode == sciSPIM) { 945 /* P34端子機能制御レジスタ SCK6とする */ 946 sil_wrb_mem(MPC_P34PFS_ADDR, 0x0A); 947 } 948 949 /* 書き込みプロテクトレジスタの設定 書き込みを禁止 */ 950 sil_wrb_mem(MPC_PWPR_ADDR, 0x80); 951 break; 952 /* TXD/SDA/MOSI:PC7, RXD/SCL/MISO:PC6, SCK:PC5 */ 953 case SCI8_BASE: 954 switch (mode) { 955 case sciSerial: 956 /* HIGH状態に設定 */ 957 sil_wrb_mem(PORTC_PODR_ADDR, 958 sil_reb_mem(PORTC_PODR_ADDR) | PORT_PODR_B6_BIT | PORT_PODR_B7_BIT); 959 /* TX出力/RX入力ポート設定 */ 960 sil_wrb_mem(PORTC_PDR_ADDR, (sil_reb_mem(PORTC_PDR_ADDR) | PORT_PDR_B6_BIT) & ~PORT_PDR_B7_BIT); 961 /* プルアップ無効 */ 962 sil_wrb_mem(PORTC_PCR_ADDR, sil_reb_mem(PORTC_PCR_ADDR) & ~(PORT_PCR_B6_BIT | PORT_PCR_B7_BIT)); 963 /* RX CMOS */ 964 sil_wrb_mem(PORTC_ODR0_ADDR, 965 (sil_reb_mem(PORTC_ODR0_ADDR) & ~(PORT_ODR_Pm6_MASK | PORT_ODR_Pm7_MASK)) 966 | (PORT_ODR_CMOS << PORT_ODR_Pm6_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm7_OFFSET)); 967 /* 周辺機能として使用 */ 968 sil_wrb_mem(PORTC_PMR_ADDR, sil_reb_mem(PORTC_PMR_ADDR) | PORT_PMR_B6_BIT | PORT_PMR_B7_BIT); 969 break; 970 case sciI2C: 971 /* HIGH状態に設定 */ 972 sil_wrb_mem(PORTC_PODR_ADDR, 973 sil_reb_mem(PORTC_PODR_ADDR) | PORT_PODR_B6_BIT | PORT_PODR_B7_BIT); 974 /* SCL,SDA 出力ポート設定 */ 975 sil_wrb_mem(PORTC_PDR_ADDR, sil_reb_mem(PORTC_PDR_ADDR) | PORT_PDR_B6_BIT | PORT_PDR_B7_BIT); 976 /* プルアップ有効 */ 977 sil_wrb_mem(PORTC_PCR_ADDR, sil_reb_mem(PORTC_PCR_ADDR) | PORT_PCR_B6_BIT | PORT_PCR_B7_BIT); 978 /* Nチャネルオープンドレイン */ 979 sil_wrb_mem(PORTC_ODR0_ADDR, 980 (sil_reb_mem(PORTC_ODR0_ADDR) & ~(PORT_ODR_Pm6_MASK | PORT_ODR_Pm7_MASK)) 981 | (PORT_ODR_NCH_OPEN_DRAIN << PORT_ODR_Pm6_OFFSET) | (PORT_ODR_NCH_OPEN_DRAIN << PORT_ODR_Pm7_OFFSET)); 982 /* 周辺機能として使用 */ 983 sil_wrb_mem(PORTC_PMR_ADDR, sil_reb_mem(PORTC_PMR_ADDR) | PORT_PMR_B6_BIT | PORT_PMR_B7_BIT); 984 break; 985 case sciSPIM: 986 /* HIGH状態に設定 */ 987 sil_wrb_mem(PORTC_PODR_ADDR, 988 sil_reb_mem(PORTC_PODR_ADDR) | PORT_PODR_B7_BIT | PORT_PODR_B6_BIT | PORT_PODR_B5_BIT); 989 /* MOSI出力/MISO入力/SCK入出力ポート設定 */ 990 sil_wrb_mem(PORTC_PDR_ADDR, (sil_reb_mem(PORTC_PDR_ADDR) | PORT_PDR_B5_BIT | PORT_PDR_B7_BIT) & ~PORT_PDR_B6_BIT); 991 /* プルアップ無効 */ 992 sil_wrb_mem(PORTC_PCR_ADDR, sil_reb_mem(PORTC_PCR_ADDR) & ~(PORT_PCR_B5_BIT | PORT_PCR_B7_BIT | PORT_PCR_B6_BIT)); 993 /* MISO CMOS */ 994 sil_wrb_mem(PORTC_ODR0_ADDR, 995 (sil_reb_mem(PORTC_ODR0_ADDR) & ~(PORT_ODR_Pm5_MASK | PORT_ODR_Pm6_MASK | PORT_ODR_Pm7_MASK)) 996 | (PORT_ODR_CMOS << PORT_ODR_Pm5_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm6_OFFSET) | (PORT_ODR_CMOS << PORT_ODR_Pm7_OFFSET)); 997 /* 周辺機能として使用 */ 998 sil_wrb_mem(PORTC_PMR_ADDR, sil_reb_mem(PORTC_PMR_ADDR) | PORT_PMR_B5_BIT | PORT_PMR_B6_BIT | PORT_PMR_B7_BIT); 999 break; 1000 } 1001 1002 /* 書き込みプロテクトレジスタの設定 PFSWEビットへの書き込みを許可 */ 1003 sil_wrb_mem(MPC_PWPR_ADDR, 0x00); 1004 /* 書き込みプロテクトレジスタの設定 PxxFSレジスタへの書き込みを許可 */ 1005 sil_wrb_mem(MPC_PWPR_ADDR, 0x40); 1006 1007 /* PC7端子機能制御レジスタ TXD8/SMOSI8/SSDA8とする */ 1008 sil_wrb_mem(MPC_PC7PFS_ADDR, 0x0A); 1009 /* PC6端子機能制御レジスタ RXD8/SMISO8/SSCL8とする */ 1010 sil_wrb_mem(MPC_PC6PFS_ADDR, 0x0A); 1011 if (mode == sciSPIM) { 1012 /* PC5端子機能制御レジスタ SCK8とする */ 1013 sil_wrb_mem(MPC_PC5PFS_ADDR, 0x0A); 1014 } 1015 1016 /* 書き込みプロテクトレジスタの設定 書き込みを禁止 */ 1017 sil_wrb_mem(MPC_PWPR_ADDR, 0x80); 1018 break; 1019 } 1020 } 1021 1022 void sci_disable(void *base_address) 1023 { 1024 /* 送受信禁止, SCKn端子は入出力ポートとして使用 */ 1025 sil_wrb_mem(SCI_SCR(base_address), 0x00U); 1026 1027 /* 1028 * モジュールストップ機能の設定 1029 */ 1030 sil_wrh_mem(SYSTEM_PRCR_ADDR, (uint16_t)0xA502); /* 書込み許可 */ 1031 sil_wrw_mem(SYSTEM_MSTPCRB_ADDR, 1032 sil_rew_mem(SYSTEM_MSTPCRB_ADDR) | SCI_MSTPCRB_BIT(base_address)); 1033 sil_wrh_mem(SYSTEM_PRCR_ADDR, (uint16_t)0xA500); /* 書込み禁止 */ 1034 } 1035 1036 void sci_set_frequency(void *base_address, int hz) 1037 { 1038 uint_t cnt, brr, clk; 1039 1040 cnt = (FREQ_PCLK * 1000) / (16 * hz); 1041 if (cnt < 512) 1042 clk = 0; 1043 else if (cnt < 4 * 512) 1044 clk = 1; 1045 else if (cnt < 16 * 512) 1046 clk = 2; 1047 else if (cnt < 64 * 512) 1048 clk = 3; 1049 else 1050 return; 1051 1052 brr = cnt / (1 << (2 * clk)); 1053 brr = (brr / 2) + (brr % 2) - 1; 1054 1055 /* SMRに送信/ 受信フォーマットを設定 */ 1056 /* クロック選択ビット(SMR.CKS[1:0]ビットを設定)、それ以外のビットを“0”に設定します。 */ 1057 sil_wrb_mem(SCI_SMR(base_address), clk); 1058 1059 /* SCMRレジスタはSDIRビットを“1”、SINVビットを“0”、SMIFビットを“0”に設定します。 */ 1060 sil_wrb_mem(SCI_SCMR(base_address), 1061 (sil_reb_mem(SCI_SCMR(base_address)) & ~(SINV | SMIF)) | SDIR); 1062 1063 /* ビットレートを設定 */ 1064 sil_wrb_mem(SCI_BRR(base_address), brr); 1065 } 1066 716 1067 void serial_init(serial_t *obj, PinName tx, PinName rx) 717 1068 { 1069 #ifdef TOPPERS_GRCITRUS 1070 if ((rx == D0) && (tx == D1)) { 1071 obj->base_address = (void *)SCI0_BASE; 1072 obj->rxi_intno = INT_SCI0_RXI; 1073 obj->tei_intno = INT_SCI0_TEI; 1074 } 1075 else if ((rx == D5) && (tx == D6)) { 1076 obj->base_address = (void *)SCI2_BASE; 1077 obj->rxi_intno = INT_SCI2_RXI; 1078 obj->tei_intno = INT_SCI2_TEI; 1079 } 1080 else if ((rx == D7) && (tx == D8)) { 1081 obj->base_address = (void *)SCI6_BASE; 1082 obj->rxi_intno = INT_SCI6_RXI; 1083 obj->tei_intno = INT_SCI6_TEI; 1084 } 1085 else if ((rx == D11) && (tx == D12)) { 1086 obj->base_address = (void *)SCI8_BASE; 1087 obj->rxi_intno = INT_SCI8_RXI; 1088 obj->tei_intno = INT_SCI8_TEI; 1089 } 1090 else { 1091 obj->base_address = NULL; 1092 return; 1093 } 1094 #else 1095 if ((rx == D0) && (tx == D1)) { 1096 obj->base_address = (void *)SCI0_BASE; 1097 obj->rxi_intno = INT_SCI0_RXI; 1098 obj->tei_intno = INT_SCI0_TEI; 1099 } 1100 else if ((rx == D6) && (tx == D7)) { 1101 obj->base_address = (void *)SCI6_BASE; 1102 obj->rxi_intno = INT_SCI6_RXI; 1103 obj->tei_intno = INT_SCI6_TEI; 1104 } 1105 else if ((rx == D11) && (tx == D12)) { 1106 obj->base_address = (void *)SCI8_BASE; 1107 obj->rxi_intno = INT_SCI8_RXI; 1108 obj->tei_intno = INT_SCI8_TEI; 1109 } 1110 else { 1111 obj->base_address = NULL; 1112 return; 1113 } 1114 #endif // TOPPERS_GRCITRUS 1115 /* SCI有効 */ 1116 sci_enable(obj->base_address, sciSerial); 1117 1118 /* SIMR1.IICMビットを“0”に設定 */ 1119 sil_wrb_mem(SCI_SIMR1(obj->base_address), 1120 sil_reb_mem(SCI_SIMR1(obj->base_address)) & ~IICM); 1121 1122 /* SPMR.CKPH, CKPOLビットを“0”に設定 */ 1123 sil_wrb_mem(SCI_SPMR(obj->base_address), 1124 sil_reb_mem(SCI_SPMR(obj->base_address)) & ~(CKPH | CKPOL)); 1125 1126 sci_set_frequency(obj->base_address, 9600); 1127 1128 /* SMRに送信/ 受信フォーマットを設定 */ 1129 serial_format(obj, 8, ParityNone, 1); 1130 1131 /* 送受信許可 */ 1132 sil_wrb_mem(SCI_SCR(obj->base_address), 1133 (sil_reb_mem(SCI_SCR(obj->base_address)) | RE | TE)); 718 1134 } 719 1135 720 1136 void serial_free(serial_t *obj) 721 1137 { 1138 /* SCI無効 */ 1139 sci_disable(obj->base_address); 1140 1141 obj->base_address = NULL; 722 1142 } 723 1143 724 1144 void serial_baud(serial_t *obj, int baudrate) 725 1145 { 1146 uint8_t scr = sil_reb_mem(SCI_SCR(obj->base_address)); 1147 1148 /* 送受信禁止, SCKn端子は入出力ポートとして使用 */ 1149 sil_wrb_mem(SCI_SCR(obj->base_address), 0x00U); 1150 1151 sci_set_frequency(obj->base_address, baudrate); 1152 1153 /* 送受信許可 */ 1154 sil_wrb_mem(SCI_SCR(obj->base_address), scr); 726 1155 } 727 1156 728 1157 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) 729 1158 { 1159 uint8_t smr = sil_reb_mem(SCI_SMR(obj->base_address)); 1160 1161 smr &= ~(PE | PM | CHR | STOP); 1162 1163 switch (parity) { 1164 case ParityNone: 1165 break; 1166 case ParityOdd: 1167 smr |= PE | PM; 1168 break; 1169 case ParityEven: 1170 smr |= PE; 1171 break; 1172 default: 1173 break; 1174 } 1175 1176 switch (data_bits) { 1177 case 7: 1178 smr |= CHR; 1179 break; 1180 case 8: 1181 break; 1182 default: 1183 break; 1184 } 1185 1186 switch (stop_bits) { 1187 case 1: 1188 break; 1189 case 2: 1190 smr |= STOP; 1191 break; 1192 default: 1193 break; 1194 } 1195 1196 sil_wrb_mem(SCI_SMR(obj->base_address), smr); 730 1197 } 731 1198 732 1199 int serial_getc(serial_t *obj) 733 1200 { 1201 uint8_t ssr; 1202 int c; 1203 1204 for (;;) { 1205 /* SSR.ORER, PER, FERフラグをリード */ 1206 ssr = sil_reb_mem(SCI_SSR(obj->base_address)); 1207 1208 /* 受信エラーが発生したとき */ 1209 if ((ssr & (ORER | PER | FER)) != 0) { 1210 /* オーバランエラー */ 1211 if ((ssr & ORER) != 0) { 1212 /* RDRレジスタをリード */ 1213 c = (int)sil_reb_mem(SCI_RDR(obj->base_address)); 1214 } 1215 /* フレーミングエラー */ 1216 if ((ssr & FER) != 0) { 1217 } 1218 /* パリティエラー */ 1219 if ((ssr & PER) != 0) { 1220 } 1221 } 1222 1223 /* SSR.ORER, PER, FERフラグを“0”に設定 */ 1224 sil_wrb_mem(SCI_SSR(obj->base_address), ssr & ~(ORER | PER | FER)); 1225 1226 /* SSR.ORER, PER, FERフラグをリード */ 1227 ssr = sil_reb_mem(SCI_SSR(obj->base_address)); 1228 1229 /* RXI割り込み */ 1230 if (serial_readable(obj)) { 1231 clear_int(obj->rxi_intno); 1232 break; 1233 } 1234 1235 dly_tsk(10); 1236 } 1237 1238 /* RDRレジスタをリード */ 1239 c = (int)sil_reb_mem(SCI_RDR(obj->base_address)); 1240 1241 return c; 1242 } 1243 1244 void serial_putc(serial_t *obj, int c) 1245 { 1246 while (serial_writable(obj)) 1247 dly_tsk(10); 1248 1249 clear_int(obj->tei_intno); 1250 1251 sil_wrb_mem(SCI_TDR(obj->base_address), (char)c); 1252 } 1253 1254 int serial_readable(serial_t *obj) 1255 { 1256 return probe_int(obj->rxi_intno); 1257 } 1258 1259 int serial_writable(serial_t *obj) 1260 { 1261 return probe_int(obj->tei_intno); 1262 } 1263 1264 uart_irq_handler sci_irq_handler[7]; 1265 1266 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) 1267 { 1268 int no = SCI_NUM(obj->base_address); 1269 1270 sci_irq_handler[no] = handler; 1271 } 1272 1273 void i2c_init(i2c_t *obj, PinName sda, PinName scl) 1274 { 1275 if ((sda == I2C_SDA) && (scl == I2C_SCL)) { 1276 #ifdef TOPPERS_GRCITRUS 1277 obj->base_address = (void *)SCI6_BASE; 1278 obj->rxi_intno = INT_SCI6_RXI; 1279 obj->txi_intno = INT_SCI6_TXI; 1280 obj->tei_intno = INT_SCI6_TEI; 1281 #else 1282 obj->base_address = (void *)SCI2_BASE; 1283 obj->rxi_intno = INT_SCI2_RXI; 1284 obj->txi_intno = INT_SCI2_TXI; 1285 obj->tei_intno = INT_SCI2_TEI; 1286 #endif 1287 } 1288 else { 1289 obj->base_address = NULL; 1290 return; 1291 } 1292 1293 /* SCI有効 */ 1294 sci_enable(obj->base_address, sciI2C); 1295 1296 /* SIMR3.IICSDAS[1:0](b5-b4), IICSCLS[1:0](b7-b6)ビットを“11b”に設定 */ 1297 sil_wrb_mem(SCI_SIMR3(obj->base_address), 0xF0U); 1298 1299 sci_set_frequency(obj->base_address, 100000); 1300 1301 /* SEMR、SNFR、SIMR1、SIMR2、SPMRレジスタに値を設定します。 */ 1302 /* SEMRレジスタは、NFENビットを設定します。 */ 1303 sil_wrb_mem(SCI_SEMR(obj->base_address), NFEN); 1304 1305 /* SNFRレジスタは、NFCS[2:0]ビットを設定します。*/ 1306 sil_wrb_mem(SCI_SNFR(obj->base_address), 1); 1307 1308 /* SIMR1レジスタは、IICMビットを“1”に設定し、IICDL[4:0]ビ ットを設定します。 */ 1309 sil_wrb_mem(SCI_SIMR1(obj->base_address), IICM | (3 << 3)); 1310 1311 /* SIMR2レジスタは、IICACKT、IICCSCビットを“1”に設定し、IICINTMビットを設定します。 */ 1312 sil_wrb_mem(SCI_SIMR2(obj->base_address), IICACKT | IICCSC | IICINTM); 1313 1314 /* SPMRレジスタは、全ビット“0”に設定します。 */ 1315 sil_wrb_mem(SCI_SPMR(obj->base_address), 0); 1316 1317 /* 送受信許可 */ 1318 sil_wrb_mem(SCI_SCR(obj->base_address), 1319 (sil_reb_mem(SCI_SCR(obj->base_address)) | RE | TE)); 1320 } 1321 1322 void i2c_frequency(i2c_t *obj, int hz) 1323 { 1324 uint8_t scr = sil_reb_mem(SCI_SCR(obj->base_address)); 1325 1326 /* 送受信禁止, SCKn端子は入出力ポートとして使用 */ 1327 sil_wrb_mem(SCI_SCR(obj->base_address), 0x00U); 1328 1329 sci_set_frequency(obj->base_address, hz); 1330 1331 /* 送受信許可 */ 1332 sil_wrb_mem(SCI_SCR(obj->base_address), scr); 1333 } 1334 1335 int i2c_start(i2c_t *obj) 1336 { 1337 if (obj->base_address == NULL) 1338 return 0; 1339 1340 /* SIMR3.IICSTAREQビットを“1”に設定すると同時に、 1341 * SIMR3.IICSCLS[1:0],IICSDAS[1:0]ビットを“01b”に設定 */ 1342 sil_wrb_mem(SCI_SIMR3(obj->base_address), IICSTAREQ | (1 << 4) | (1 << 6)); 1343 734 1344 return 0; 735 1345 } 736 1346 737 void serial_putc(serial_t *obj, int c) 738 { 739 } 740 741 int serial_readable(serial_t *obj) 742 { 1347 int i2c_restart(i2c_t *obj) 1348 { 1349 if (obj->base_address == NULL) 1350 return 0; 1351 1352 sil_wrb_mem(SCI_SIMR3(obj->base_address), IICRSTAREQ | (1 << 4) | (1 << 6)); 1353 743 1354 return 0; 744 1355 } 745 1356 746 int serial_writable(serial_t *obj) 747 { 1357 int i2c_stop(i2c_t *obj) 1358 { 1359 if (obj->base_address == NULL) 1360 return 0; 1361 1362 /* SIMR3.IICSTPREQビットを“1”に設定すると同時に、 1363 * SIMR3.IICSCLS[1:0],IICSDAS[1:0]ビットを“01b”に設定 */ 1364 sil_wrb_mem(SCI_SIMR3(obj->base_address), IICSTPREQ | (1 << 4) | (1 << 6)); 1365 748 1366 return 0; 749 1367 } 750 1368 751 void i2c_init(i2c_t *obj, PinName sda, PinName scl) 752 { 753 } 754 755 void i2c_frequency(i2c_t *obj, int hz) 756 { 757 } 758 759 int i2c_start(i2c_t *obj) 760 { 1369 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) 1370 { 1371 if (obj->base_address == NULL) 1372 return 0; 1373 1374 /* 送信割り込み要求を禁止 */ 1375 sil_wrb_mem(SCI_SCR(obj->base_address), 1376 (sil_reb_mem(SCI_SCR(obj->base_address)) & ~(RIE)) | TEIE | TIE); 1377 1378 /* 開始条件の生成 */ 1379 i2c_start(obj); 1380 1381 /* STI(TEI)割り込み発生確認 */ 1382 while (!probe_int(obj->tei_intno)) 1383 dly_tsk(2); 1384 clear_int(obj->tei_intno); 1385 1386 /* SIMR3.IICSTIFフラグを“0”に設定し、 */ 1387 sil_wrb_mem(SCI_SIMR3(obj->base_address), 1388 sil_reb_mem(SCI_SIMR3(obj->base_address)) & ~IICSTIF); 1389 /* SIMR3.IICSCLS[1:0], IICSDAS[1:0]ビットを“00b”に設定 */ 1390 sil_wrb_mem(SCI_SIMR3(obj->base_address), 1391 sil_reb_mem(SCI_SIMR3(obj->base_address)) & ~((3 << 4) | (3 << 6))); 1392 1393 /* TDRレジスタにスレーブアドレス、R/Wビットをライト */ 1394 sil_wrb_mem(SCI_TDR(obj->base_address), address | 1); 1395 1396 /* TXI割り込み発生確認 */ 1397 while (!probe_int(obj->txi_intno)) 1398 dly_tsk(10); 1399 clear_int(obj->txi_intno); 1400 1401 /* スレーブデバイスからのACKを確認 */ 1402 if ((sil_reb_mem(SCI_SISR(obj->base_address)) & IICACKR) == 0) { 1403 /* SIMR2.IICACKTビットを“0”に設定 */ 1404 sil_wrb_mem(SCI_SIMR2(obj->base_address), sil_reb_mem(SCI_SIMR2(obj->base_address)) & ~IICACKT); 1405 /* SCR.RIEビットを“1”に設定 */ 1406 sil_wrb_mem(SCI_SCR(obj->base_address), sil_reb_mem(SCI_SCR(obj->base_address)) | RIE); 1407 1408 for (int i = 0; i < length; i++) { 1409 /* 次データが最終 */ 1410 if (i == length - 1) { 1411 /* SIMR2.IICACKTビットを“1”に設定 */ 1412 sil_wrb_mem(SCI_SIMR2(obj->base_address), sil_reb_mem(SCI_SIMR2(obj->base_address)) | IICACKT); 1413 } 1414 1415 /* TDRレジスタにダミーデータ“FFh”をライト */ 1416 sil_wrb_mem(SCI_TDR(obj->base_address), 0xFF); 1417 1418 /* RXI割り込み発生確認 */ 1419 while (!probe_int(obj->rxi_intno)) 1420 dly_tsk(10); 1421 clear_int(obj->rxi_intno); 1422 1423 /* RDRレジスタの受信データをリード */ 1424 *data = sil_reb_mem(SCI_RDR(obj->base_address)); 1425 data++; 1426 1427 /* TXI割り込み発生確認 */ 1428 while (!probe_int(obj->txi_intno)) 1429 dly_tsk(10); 1430 clear_int(obj->txi_intno); 1431 } 1432 } 1433 1434 if (stop) { 1435 /* 停止条件の生成 */ 1436 i2c_stop(obj); 1437 1438 /* STI(TEI)割り込み発生確認 */ 1439 while (!probe_int(obj->tei_intno)) 1440 dly_tsk(2); 1441 clear_int(obj->tei_intno); 1442 1443 /* SIMR3.IICSTIFフラグを“0”に設定し、*/ 1444 sil_wrb_mem(SCI_SIMR3(obj->base_address), 1445 sil_reb_mem(SCI_SIMR3(obj->base_address)) & ~IICSTIF); 1446 /* SIMR3.IICSCLS[1:0], IICSDAS[1:0]ビットを“11b”に設定 */ 1447 sil_wrb_mem(SCI_SIMR3(obj->base_address), 1448 sil_reb_mem(SCI_SIMR3(obj->base_address)) | ((3 << 4) | (3 << 6))); 1449 } 1450 1451 return length; 1452 } 1453 1454 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) 1455 { 1456 if (obj->base_address == NULL) 1457 return 0; 1458 1459 /* 受信割り込み要求を禁止 */ 1460 sil_wrb_mem(SCI_SCR(obj->base_address), 1461 (sil_reb_mem(SCI_SCR(obj->base_address)) & ~(RIE)) | TEIE | TIE); 1462 1463 /* 開始条件の生成 */ 1464 i2c_start(obj); 1465 1466 /* STI(TEI)割り込み発生確認 */ 1467 while (!probe_int(obj->tei_intno)) 1468 dly_tsk(2); 1469 clear_int(obj->tei_intno); 1470 1471 /* SIMR3.IICSTIFフラグを“0”に設定し、 */ 1472 sil_wrb_mem(SCI_SIMR3(obj->base_address), 1473 sil_reb_mem(SCI_SIMR3(obj->base_address)) & ~IICSTIF); 1474 /* SIMR3.IICSCLS[1:0], IICSDAS[1:0]ビットを“00b”に設定 */ 1475 sil_wrb_mem(SCI_SIMR3(obj->base_address), 1476 sil_reb_mem(SCI_SIMR3(obj->base_address)) & ~((3 << 4) | (3 << 6))); 1477 1478 /* TDRレジスタにスレーブアドレス、R/Wビットをライト */ 1479 sil_wrb_mem(SCI_TDR(obj->base_address), address); 1480 1481 /* TXI割り込み発生確認 */ 1482 while (!probe_int(obj->txi_intno)) 1483 dly_tsk(10); 1484 clear_int(obj->txi_intno); 1485 1486 /* スレーブデバイスからのACKを確認 */ 1487 if ((sil_reb_mem(SCI_SISR(obj->base_address)) & IICACKR) == 0) { 1488 1489 for (int i = 0; i < length; i++) { 1490 /* TDRレジスタにスレーブアドレス、R/Wビットをライト */ 1491 sil_wrb_mem(SCI_TDR(obj->base_address), *data); 1492 data++; 1493 1494 /* TXI割り込み発生確認 */ 1495 while (!probe_int(obj->txi_intno)) 1496 dly_tsk(10); 1497 clear_int(obj->txi_intno); 1498 } 1499 } 1500 1501 if (stop) { 1502 /* 停止条件の生成 */ 1503 i2c_stop(obj); 1504 1505 /* STI(TEI)割り込み発生確認 */ 1506 while (!probe_int(obj->tei_intno)) 1507 dly_tsk(2); 1508 clear_int(obj->tei_intno); 1509 1510 /* SIMR3.IICSTIFフラグを“0”に設定し、*/ 1511 sil_wrb_mem(SCI_SIMR3(obj->base_address), 1512 sil_reb_mem(SCI_SIMR3(obj->base_address)) & ~IICSTIF); 1513 /* SIMR3.IICSCLS[1:0], IICSDAS[1:0]ビットを“11b”に設定 */ 1514 sil_wrb_mem(SCI_SIMR3(obj->base_address), 1515 sil_reb_mem(SCI_SIMR3(obj->base_address)) | ((3 << 4) | (3 << 6))); 1516 } 1517 1518 return length; 1519 } 1520 1521 int i2c_byte_read(i2c_t *obj, int last) 1522 { 1523 if (obj->base_address == NULL) 1524 return 0; 1525 761 1526 return 0; 762 1527 } 763 1528 764 int i2c_stop(i2c_t *obj) 765 { 1529 int i2c_byte_write(i2c_t *obj, int data) 1530 { 1531 if (obj->base_address == NULL) 1532 return 0; 1533 766 1534 return 0; 767 1535 } 768 1536 769 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)770 {771 return 0;772 }773 774 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)775 {776 return 0;777 }778 779 int i2c_byte_read(i2c_t *obj, int last)780 {781 return 0;782 }783 784 int i2c_byte_write(i2c_t *obj, int data)785 {786 return 0;787 }788 789 1537 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) 790 1538 { 1539 if ((mosi == D11) && (miso == D12) && (sclk == D13) && ((ssel == D10) || (ssel == NC))) { 1540 obj->base_address = (void *)SCI8_BASE; 1541 obj->txi_intno = INT_SCI8_TXI; 1542 obj->rxi_intno = INT_SCI8_RXI; 1543 obj->tei_intno = INT_SCI8_TEI; 1544 } 1545 else { 1546 obj->base_address = NULL; 1547 return; 1548 } 1549 1550 /* SCI有効 */ 1551 sci_enable(obj->base_address, (ssel == D10) ? sciSPIS : sciSPIM); 1552 1553 /* SIMR1.IICMビットを“0”に設定 */ 1554 sil_wrb_mem(SCI_SIMR1(obj->base_address), 1555 sil_reb_mem(SCI_SIMR1(obj->base_address)) & ~IICM); 1556 1557 if (ssel == NC) { 1558 /* SPMR.SSE, CTSE, MSS, MFF, CKPH, CKPOLビットを“0”に設定 */ 1559 sil_wrb_mem(SCI_SPMR(obj->base_address), 0); 1560 } 1561 else { 1562 /* SPMR, CTSE, MSS, MFF, CKPH, CKPOLビットを“0”に設定 */ 1563 /* SPMR.SSEビットを“1”に設定 */ 1564 sil_wrb_mem(SCI_SPMR(obj->base_address), SSE); 1565 } 1566 1567 /* SCMR.SMIF ビットを“0”に設定 */ 1568 sil_wrb_mem(SCI_SCMR(obj->base_address), 1569 sil_reb_mem(SCI_SCMR(obj->base_address)) & ~SMIF); 1570 1571 /* SMRに送信/ 受信フォーマットをクロック同期式モードで動作で設定 */ 1572 sil_wrb_mem(SCI_SMR(obj->base_address), CM); 1573 1574 sci_set_frequency(obj->base_address, 1000000); 1575 1576 /* 送受信許可 */ 1577 sil_wrb_mem(SCI_SCR(obj->base_address), 1578 (sil_reb_mem(SCI_SCR(obj->base_address)) | RE | TE)); 791 1579 } 792 1580 793 1581 void spi_free(spi_t *obj) 794 1582 { 1583 /* SCI無効 */ 1584 sci_disable(obj->base_address); 1585 1586 obj->base_address = NULL; 795 1587 } 796 1588 797 1589 void spi_format(spi_t *obj, int bits, int mode, int slave) 798 1590 { 1591 int polarity = (mode & 0x2) ? 1 : 0; 1592 int phase = (mode & 0x1) ? 1 : 0; 1593 uint8_t spmr; 1594 1595 if ((bits != 8) || (mode < 0) || (mode > 3)) { 1596 return; 1597 } 1598 1599 /* 送受信禁止, SCKn端子は入出力ポートとして使用 */ 1600 sil_wrb_mem(SCI_SCR(obj->base_address), 0x00U); 1601 1602 spmr = sil_reb_mem(SCI_SPMR(obj->base_address)); 1603 1604 /* クロック極性反転あり/なし */ 1605 if (polarity) 1606 spmr |= CKPOL; 1607 else 1608 spmr &= ~CKPOL; 1609 1610 /* クロック位相反転あり/なし */ 1611 if (phase) 1612 spmr |= CKPH; 1613 else 1614 spmr &= ~CKPH; 1615 1616 if (slave) { 1617 /* SCKn端子はクロック入力として使用 */ 1618 sil_wrb_mem(SCI_SCR(obj->base_address), 1619 (sil_reb_mem(SCI_SCR(obj->base_address)) & ~CKE) | 2); 1620 1621 /* SPMR.MSSビットを“1”に設定 */ 1622 sil_wrb_mem(SCI_SPMR(obj->base_address), spmr | MSS); 1623 } 1624 else { 1625 /* SCKn端子はクロック出力として使用 */ 1626 sil_wrb_mem(SCI_SCR(obj->base_address), 1627 sil_reb_mem(SCI_SCR(obj->base_address)) & ~CKE); 1628 1629 /* SPMR.MSSビットを“0”に設定 */ 1630 sil_wrb_mem(SCI_SPMR(obj->base_address), spmr & ~MSS); 1631 } 1632 1633 /* 送受信許可 */ 1634 sil_wrb_mem(SCI_SCR(obj->base_address), 1635 (sil_reb_mem(SCI_SCR(obj->base_address)) | RE | TE)); 799 1636 } 800 1637 801 1638 void spi_frequency(spi_t *obj, int hz) 802 1639 { 1640 uint8_t scr = sil_reb_mem(SCI_SCR(obj->base_address)); 1641 1642 /* 送受信禁止, SCKn端子は入出力ポートとして使用 */ 1643 sil_wrb_mem(SCI_SCR(obj->base_address), 0x00U); 1644 1645 sci_set_frequency(obj->base_address, hz); 1646 1647 /* 送受信許可 */ 1648 sil_wrb_mem(SCI_SCR(obj->base_address), scr); 803 1649 } 804 1650 805 1651 int spi_master_write(spi_t *obj, int value) 806 1652 { 807 return 0; 1653 /* TXI割り込み発生確認 */ 1654 while (!probe_int(obj->txi_intno)) 1655 ; 1656 1657 /* 送信データをライト */ 1658 sil_wrb_mem(SCI_TDR(obj->base_address), (char)value); 1659 1660 do { 1661 uint8_t ssr = sil_reb_mem(SCI_SSR(obj->base_address)); 1662 if ((ssr & ORER) != 0) { 1663 ssr &= ~ORER; 1664 sil_wrb_mem(SCI_SSR(obj->base_address), ssr); 1665 return -1; 1666 } 1667 } 1668 /* RXI割り込み発生確認 */ 1669 while (!probe_int(obj->rxi_intno)); 1670 1671 /* 受信データをリード */ 1672 return sil_reb_mem(SCI_RDR(obj->base_address)); 1673 } 1674 1675 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, 1676 char *rx_buffer, int rx_length, char write_fill) 1677 { 1678 int total = (tx_length > rx_length) ? tx_length : rx_length; 1679 1680 for (int i = 0; i < total; i++) { 1681 char out = (i < tx_length) ? tx_buffer[i] : write_fill; 1682 char in = spi_master_write(obj, out); 1683 if (i < rx_length) { 1684 rx_buffer[i] = in; 1685 } 1686 } 1687 1688 return total; 808 1689 } 809 1690 … … 858 1739 sil_wrb_mem((uint8_t *)RTC_RSECCNT_ADDR, DecToBcd(tm.tm_sec)); 859 1740 } 1741 1742 void sci_rxi_handler(uint32_t id) 1743 { 1744 uart_irq_handler hdr = sci_irq_handler[id]; 1745 if (hdr == NULL) 1746 return; 1747 1748 hdr(id, RxIrq); 1749 } 1750 1751 void sci_txi_handler(uint32_t id) 1752 { 1753 uart_irq_handler hdr = sci_irq_handler[id]; 1754 if (hdr == NULL) 1755 return; 1756 1757 hdr(id, TxIrq); 1758 } 1759 1760 void sci_tei_handler(int no) 1761 { 1762 } 1763 1764 void sci0_rxi_handler(void) 1765 { 1766 sci_rxi_handler(0); 1767 } 1768 1769 void sci0_txi_handler(void) 1770 { 1771 sci_txi_handler(0); 1772 } 1773 1774 void sci0_tei_handler(void) 1775 { 1776 sci_tei_handler(0); 1777 } 1778 1779 void sci1_rxi_handler(void) 1780 { 1781 sci_rxi_handler(1); 1782 } 1783 1784 void sci1_txi_handler(void) 1785 { 1786 sci_txi_handler(1); 1787 } 1788 1789 void sci1_tei_handler(void) 1790 { 1791 sci_tei_handler(1); 1792 } 1793 1794 void sci2_rxi_handler(void) 1795 { 1796 sci_rxi_handler(2); 1797 } 1798 1799 void sci2_txi_handler(void) 1800 { 1801 sci_txi_handler(2); 1802 } 1803 1804 void sci2_tei_handler(void) 1805 { 1806 sci_tei_handler(2); 1807 } 1808 1809 void sci3_rxi_handler(void) 1810 { 1811 sci_rxi_handler(3); 1812 } 1813 1814 void sci3_txi_handler(void) 1815 { 1816 sci_txi_handler(3); 1817 } 1818 1819 void sci3_tei_handler(void) 1820 { 1821 sci_tei_handler(3); 1822 } 1823 1824 void sci4_rxi_handler(void) 1825 { 1826 sci_rxi_handler(4); 1827 } 1828 1829 void sci4_txi_handler(void) 1830 { 1831 sci_txi_handler(4); 1832 } 1833 1834 void sci4_tei_handler(void) 1835 { 1836 sci_tei_handler(4); 1837 } 1838 1839 void sci5_rxi_handler(void) 1840 { 1841 sci_rxi_handler(5); 1842 } 1843 1844 void sci5_txi_handler(void) 1845 { 1846 sci_txi_handler(5); 1847 } 1848 1849 void sci5_tei_handler(void) 1850 { 1851 sci_tei_handler(5); 1852 } 1853 1854 void sci6_rxi_handler(void) 1855 { 1856 sci_rxi_handler(6); 1857 } 1858 1859 void sci6_txi_handler(void) 1860 { 1861 sci_txi_handler(6); 1862 } 1863 1864 void sci6_tei_handler(void) 1865 { 1866 sci_tei_handler(6); 1867 } -
asp3_tinet_ecnl_rx/trunk/ntshell/src/mbed_api.h
r337 r364 2 2 * TOPPERS ECHONET Lite Communication Middleware 3 3 * 4 * Copyright (C) 2014-201 7Cores Co., Ltd. Japan4 * Copyright (C) 2014-2018 Cores Co., Ltd. Japan 5 5 * 6 6 * 上記著作権者は,以下の(1)~(4)の条件を満たす場合に限り,本ソフトウェ … … 38 38 #define _MBED_API_H_ 39 39 40 #define DEVICE_SPI 41 #define DEVICE_I2C 42 40 43 void mbed_api_init(void); 41 44 … … 44 47 45 48 typedef enum { 49 D0, /* P21 */ 50 D1, /* P20 */ 51 D2, /* P22 */ 52 D3, /* P23 */ 53 D4, /* P24 */ 54 D5, /* P25 */ 55 D6, /* P32 */ 56 D7, /* P33 */ 57 D8, /* PC2 */ 58 D9, /* PC3 */ 59 D10, /* PC4 */ 60 D11, /* PC6 */ 61 D12, /* PC7 */ 62 D13, /* PC5 */ 63 64 A0, /* AN0 */ 65 A1, /* AN1 */ 66 A2, /* AN2 */ 67 A3, /* AN3 */ 68 A4, /* AN4 */ 69 A5, /* AN5 */ 70 A6, /* AN6 */ 71 A7, /* AN7 */ 72 73 I2C_SCL, /* P52 */ 74 I2C_SDA, /* P50 */ 75 46 76 PIN_LED0, 47 77 PIN_LED1, 48 78 PIN_LED2, 49 79 PIN_LED3, 50 PIN_BUTTON0, 80 PIN_SW, 81 51 82 NC = (int)0xFFFFFFFF 52 83 } PinName; … … 56 87 #define LED_BLUE PIN_LED2 57 88 #define LED_USER PIN_LED3 58 #define USER_BUTTON0 PIN_ BUTTON089 #define USER_BUTTON0 PIN_SW 59 90 60 91 typedef enum { … … 64 95 65 96 typedef enum { 66 PullUp = 0,97 PullUp = 2, 67 98 PullDown = 3, 68 PullNone = 2,99 PullNone = 0, 69 100 OpenDrain = 4, 70 PullDefault = Pull Down101 PullDefault = PullNone 71 102 } PinMode; 72 103 … … 114 145 115 146 typedef enum { 116 117 118 119 120 147 ParityNone = 0, 148 ParityOdd = 1, 149 ParityEven = 2, 150 ParityForced1 = 3, 151 ParityForced0 = 4 121 152 } SerialParity; 122 153 123 154 typedef enum { 124 FlowControlNone, 125 FlowControlRTS, 126 FlowControlCTS, 127 FlowControlRTSCTS 155 RxIrq, 156 TxIrq 157 } SerialIrq; 158 159 typedef enum { 160 FlowControlNone, 161 FlowControlRTS, 162 FlowControlCTS, 163 FlowControlRTSCTS 128 164 } FlowControl; 129 165 130 166 typedef struct serial_s { 131 int dummy; 167 void *base_address; 168 int rxi_intno; 169 int tei_intno; 132 170 } serial_t; 133 171 134 typedef struct spi_s { 135 int dummy; 136 } spi_t; 172 typedef void (*uart_irq_handler)(uint32_t id, SerialIrq event); 137 173 138 174 void serial_init(serial_t *obj, PinName tx, PinName rx); … … 144 180 int serial_readable(serial_t *obj); 145 181 int serial_writable(serial_t *obj); 182 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id); 146 183 147 184 typedef struct i2c_s { 185 void *base_address; 186 int rxi_intno; 187 int txi_intno; 188 int tei_intno; 148 189 unsigned char rxdata[16]; 149 190 } i2c_t; … … 158 199 int i2c_byte_write(i2c_t *obj, int data); 159 200 201 #define SPI_FILL_CHAR (0xFF) 202 203 typedef struct spi_s { 204 void *base_address; 205 int rxi_intno; 206 int txi_intno; 207 int tei_intno; 208 } spi_t; 209 160 210 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel); 161 211 void spi_free(spi_t *obj); … … 163 213 void spi_frequency(spi_t *obj, int hz); 164 214 int spi_master_write(spi_t *obj, int value); 215 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, 216 char *rx_buffer, int rx_length, char write_fill); 165 217 166 218 void rtc_init(void); … … 170 222 void rtc_write(time_t t); 171 223 224 void sci0_rxi_handler(void); 225 void sci0_txi_handler(void); 226 void sci0_tei_handler(void); 227 228 void sci1_rxi_handler(void); 229 void sci1_txi_handler(void); 230 void sci1_tei_handler(void); 231 232 void sci2_rxi_handler(void); 233 void sci2_txi_handler(void); 234 void sci2_tei_handler(void); 235 236 void sci3_rxi_handler(void); 237 void sci3_txi_handler(void); 238 void sci3_tei_handler(void); 239 240 void sci4_rxi_handler(void); 241 void sci4_txi_handler(void); 242 void sci4_tei_handler(void); 243 244 void sci5_rxi_handler(void); 245 void sci5_txi_handler(void); 246 void sci5_tei_handler(void); 247 248 void sci6_rxi_handler(void); 249 void sci6_txi_handler(void); 250 void sci6_tei_handler(void); 251 172 252 #endif /* _MBED_API_H_ */ -
asp3_tinet_ecnl_rx/trunk/ntshell/src/net_misc.h
r359 r364 41 41 /* スタックサイズ */ 42 42 43 #define NET_MISC_STACK_SIZE 1024/* NTP クライアントタスク(IPv4)のスタックサイズ */43 #define NET_MISC_STACK_SIZE 2048 /* NTP クライアントタスク(IPv4)のスタックサイズ */ 44 44 45 45 /* 優先度 */ -
asp3_tinet_ecnl_rx/trunk/ntshell/src/netcmd.c
r342 r364 239 239 int usrcmd_ping(int argc, char **argv) 240 240 { 241 int tmo, size;242 char 241 int tmo = 3, size = 64; 242 char apip = DEFAULT_API_PROTO; 243 243 char *line = argv[1]; 244 244 #if defined(SUPPORT_INET6) … … 262 262 263 263 #if defined(SUPPORT_INET6) && defined(SUPPORT_INET4) 264 if (argc <= 2) 265 return 0; 266 264 267 if ('0' <= *line && *line <= '9') { 265 268 if (*line == '6') … … 269 272 line++; 270 273 } 274 275 line = argv[2]; 276 #else 277 if (argc <= 1) 278 return 0; 271 279 #endif /* of #if defined(SUPPORT_INET6) && defined(SUPPORT_INET4) */ 272 280 … … 276 284 } 277 285 278 line = argv[2];279 if ('0' <= *line && *line <= '9')280 line = get_int(&tmo, line);281 else282 tmo = 3; 283 284 line = argv[3];285 if ('0' <= *line && *line <= '9')286 line = get_int(&size, line);287 else288 size = 64;286 if (argc > 2) { 287 line = argv[2]; 288 if ('0' <= *line && *line <= '9') 289 line = get_int(&tmo, line); 290 291 if (argc > 3) { 292 line = argv[3]; 293 if ('0' <= *line && *line <= '9') 294 line = get_int(&size, line); 295 } 296 } 289 297 290 298 #if defined(SUPPORT_INET6) … … 337 345 { 338 346 ER ret; 347 348 if (argc < 2) 349 return 0; 350 339 351 if (ntlibc_strcmp(argv[1], "rel") == 0) { 340 352 ret = dhcp4c_rel_info(); … … 348 360 dhcp4c_info(); 349 361 } 362 350 363 return 0; 351 364 } -
asp3_tinet_ecnl_rx/trunk/ntshell/src/ntp_cli.c
r359 r364 265 265 266 266 nc->buf[0] = '\0'; 267 #if ndef _MSC_VER267 #ifdef __NEED_struct_timespec 268 268 if (ctime_r(&tp.tv_sec, nc->buf) != NULL) 269 269 #else -
asp3_tinet_ecnl_rx/trunk/ntshell/src/ntshell_main.c
r342 r364 60 60 #include "socket_stub.h" 61 61 #include "usb_hbth.h" 62 #include "mbed_api.h" 62 63 63 64 extern int bt_bnep_mode; … … 69 70 const struct utsname host_name = { 70 71 "TOPPERS/ASP3", 71 72 73 74 75 72 TARGET_NAME, 73 "3.2.0", 74 "3.2.0", 75 TARGET_NAME, 76 "toppers.jp" 76 77 }; 77 78 … … 88 89 jmp_buf process_exit; 89 90 void sys_init(void); 90 91 void ntshell_task_init() 92 { 91 NTSHELL_SERIAL_READ ntshell_serial_read = 0; 92 NTSHELL_SERIAL_WRITE ntshell_serial_write = 0; 93 void *ntshell_serial_extobj; 94 95 unsigned char ntstdio_xi(struct ntstdio_t *handle) 96 { 97 unsigned char buf[1]; 98 ntshell_serial_read((char *)buf, 1, ntshell_serial_extobj); 99 return buf[0]; 100 } 101 102 void ntstdio_xo(struct ntstdio_t *handle, unsigned char c) 103 { 104 char buf[1]; 105 buf[0] = c; 106 ntshell_serial_write(buf, 1, ntshell_serial_extobj); 107 } 108 109 void ntshell_task_init(NTSHELL_SERIAL_READ func_read, 110 NTSHELL_SERIAL_WRITE func_write, void *extobj) 111 { 112 ntshell_serial_read = func_read; 113 ntshell_serial_write = func_write; 114 ntshell_serial_extobj = extobj; 115 93 116 sys_init(); 94 117 … … 126 149 int result = 0; 127 150 int found = 0; 151 152 if (*args == 0) 153 return result; 128 154 129 155 if (strcmp((const char *)args[1], "help") == 0) { … … 295 321 int shell_clock_getres(clockid_t clk_id, struct timespec *res) 296 322 { 297 if ( clk_id != CLOCK_REALTIME)323 if ((clk_id != CLOCK_REALTIME) && (clk_id != CLOCK_MONOTONIC)) 298 324 return -EINVAL; 299 325 … … 308 334 SYSTIM now = 0; 309 335 310 if ( clk_id != CLOCK_REALTIME)336 if ((clk_id != CLOCK_REALTIME) && (clk_id != CLOCK_MONOTONIC)) 311 337 return -EINVAL; 312 338 … … 320 346 int shell_clock_settime(clockid_t clk_id, const struct timespec *tp) 321 347 { 322 if ( clk_id != CLOCK_REALTIME)348 if ((clk_id != CLOCK_REALTIME) && (clk_id != CLOCK_MONOTONIC)) 323 349 return -EINVAL; 324 350 325 rtc_write(tp->tv_sec); 351 SYSTIM time; 352 ER ret; 353 354 time = (tp->tv_sec * 1000000ll) + (tp->tv_nsec / 1000ll); 355 356 ret = set_tim(time); 357 if (ret != E_OK) { 358 return -EPERM; 359 } 326 360 327 361 return 0; … … 356 390 } 357 391 358 struct sigaction sigtable[ 6];392 struct sigaction sigtable[7]; 359 393 360 394 int shell_sigaction(int sig, const struct sigaction *restrict sa, struct sigaction *restrict old) … … 381 415 sat = &sigtable[5]; 382 416 break; 417 case SIGPIPE: 418 sat = &sigtable[6]; 419 break; 383 420 default: 384 421 return -EINVAL; -
asp3_tinet_ecnl_rx/trunk/ntshell/src/ntshell_main.cfg
r337 r364 43 43 CRE_TSK(NTSHELL_TASK, { TA_NULL, 0, ntshell_task, NTSHELL_PRIORITY, NTSHELL_STACK_SIZE, NULL }); 44 44 CRE_FLG(FLG_SELECT_WAIT, { TA_WMUL, 0x00 }); 45 CRE_SEM(SEM_FILEDESC, { TA_TPRI, 1, 1 }); 45 46 CRE_SEM(SEM_MALLOC, { TA_TPRI, 1, 1 }); -
asp3_tinet_ecnl_rx/trunk/ntshell/src/ntshell_main.h
r337 r364 49 49 50 50 #include "usrcmd.h" 51 #include "core/ntshell.h" 51 52 52 53 /* … … 54 55 */ 55 56 56 #define NTSHELL_PRIORITY 4/* ntshellタスクの優先度 */57 #define NTSHELL_PRIORITY 8 /* ntshellタスクの優先度 */ 57 58 58 59 #define NTSHELL_STACK_SIZE 8192 /* ntshellタスクのスタック領域のサイズ */ … … 75 76 extern PRI main_task_priority; 76 77 77 struct ntstdio_t;78 unsigned char ntstdio_xi(struct ntstdio_t *handle);79 void ntstdio_xo(struct ntstdio_t *handle, unsigned char c);80 81 78 /* ntshellタスク初期化 */ 82 void ntshell_task_init(); 79 void ntshell_task_init(NTSHELL_SERIAL_READ func_read, 80 NTSHELL_SERIAL_WRITE func_write, void *extobj); 83 81 84 82 /* ntshellタスク */ -
asp3_tinet_ecnl_rx/trunk/ntshell/src/shellif.h
r342 r364 39 39 40 40 #ifdef _MSC_VER 41 #define _CRT_NO_TIME_T42 #define tm msc_tm43 #include <time.h>44 #include <errno.h>45 #include <limits.h>46 #include <stdlib.h>47 #undef tm48 41 #undef NULL 49 42 #endif … … 133 126 #endif 134 127 128 #ifdef __cplusplus 129 extern "C" { 130 #endif 131 135 132 // time.h 136 133 #define CLOCK_REALTIME 0 … … 179 176 int shell_access(const char *path, int mode); 180 177 // signal.h 181 int shell_sigprocmask(int how, const sigset_t * restrict set, sigset_t *restrict old);182 int shell_sigaction(int sig, const struct sigaction * restrict sa, struct sigaction *restrict old);178 int shell_sigprocmask(int how, const sigset_t *__restrict set, sigset_t *__restrict old); 179 int shell_sigaction(int sig, const struct sigaction *__restrict sa, struct sigaction *__restrict old); 183 180 // socket.h 184 181 int shell_socket(int, int, int); 185 182 int shell_connect(int, const struct sockaddr *, socklen_t); 186 ssize_t shell_send(int, const void *, size_t, int);187 183 ssize_t shell_sendto(int, const void *, size_t, int, const struct sockaddr *, socklen_t); 188 184 ssize_t shell_sendmsg(int, const struct msghdr *, int); … … 190 186 int shell_listen(int, int); 191 187 int shell_accept(int, struct sockaddr *__restrict, socklen_t *__restrict); 192 ssize_t shell_recv(int, void *, size_t, int);193 188 ssize_t shell_recvfrom(int, void *__restrict, size_t, int, struct sockaddr *__restrict, socklen_t *__restrict); 194 189 ssize_t shell_recvmsg(int, struct msghdr *, int); … … 263 258 int shell_pipe2(int [2], int); 264 259 int shell_ppoll(struct pollfd *, nfds_t, const struct timespec *,const sigset_t *); 265 int shell_pselect6(int, fd_set * restrict, fd_set *restrict,266 fd_set * restrict, const struct timespec *restrict, const sigset_t *restrict);260 int shell_pselect6(int, fd_set *__restrict, fd_set *__restrict, 261 fd_set *__restrict, const struct timespec *__restrict, const sigset_t *__restrict); 267 262 int shell_setpgid(pid_t, pid_t); 268 263 int shell_setsid(); … … 308 303 #endif 309 304 310 struct tm *gmtime_r(const time_t *t, struct tm *tm);311 305 void *malloc(size_t size); 312 306 void *calloc(size_t size, size_t count); … … 314 308 void free(void *ptr); 315 309 310 #ifdef __cplusplus 311 } 312 #endif 313 316 314 #endif /* SHELLIF_H */ -
asp3_tinet_ecnl_rx/trunk/ntshell/src/socket_stub.c
r337 r364 42 42 #include <sil.h> 43 43 #include "syssvc/syslog.h" 44 #include <tinet_defs.h> 44 45 #include <tinet_config.h> 46 #include <net/net.h> 47 #include <net/net_endian.h> 45 48 #include <netinet/in.h> 46 49 #include <netinet/in_itron.h> … … 53 56 #include <net/if_var.h> 54 57 #include <netinet/udp_var.h> 58 #include <net/net_buf.h> 55 59 //#include <netinet/tcp_var.h> 56 60 #include <netapp/resolver.h> … … 58 62 #include "ff.h" 59 63 #include "socket_stub.h" 64 #include "kernel_cfg.h" 60 65 61 66 #define SOCKET_TIMEOUT 2000000 … … 181 186 fp->psock->buf_size = 512 + 512; 182 187 fp->psock->buf = malloc(fp->psock->buf_size); 188 #ifdef _DEBUG 189 memset(fp->psock->buf, 0, fp->psock->buf_size); 190 #endif 183 191 T_TCP_CCEP ccep = { 0, fp->psock->buf, 512, &fp->psock->buf[512], 512, (FP)socket_tcp_callback }; 184 192 ret = tcp_cre_cep(cepid, &ccep); … … 279 287 fp->psock->buf_size = 512 + 512; 280 288 fp->psock->buf = malloc(fp->psock->buf_size); 289 #ifdef _DEBUG 290 memset(fp->psock->buf, 0, fp->psock->buf_size); 291 #endif 281 292 T_TCP_CCEP ccep = { 0, fp->psock->buf, 512, &fp->psock->buf[512], 512, (FP)socket_tcp_callback }; 282 293 ret = tcp_cre_cep(cepid, &ccep); … … 298 309 return -EHOSTUNREACH; 299 310 } 300 fp->writable = 1;301 311 break; 302 312 } … … 322 332 } 323 333 324 memcpy( &fp->psock, &lfp->psock, sizeof(fp->psock));334 memcpy(fp->psock, lfp->psock, offsetof(socket_t, buf_size)); 325 335 326 336 ER ret; … … 335 345 fp->psock->buf_size = 512 + 512; 336 346 fp->psock->buf = malloc(fp->psock->buf_size); 347 #ifdef _DEBUG 348 memset(fp->psock->buf, 0, fp->psock->buf_size); 349 #endif 337 350 T_TCP_CCEP ccep = { 0, fp->psock->buf, 512, &fp->psock->buf[512], 512, (FP)socket_tcp_callback }; 338 351 ret = tcp_cre_cep(cepid, &ccep); … … 346 359 else { 347 360 cepid = lfp->psock->cepid; 361 fp->handle = cepid; 348 362 lfp->handle = tmax_tcp_cepid + lfp->psock->repid; 349 363 lfp->psock->cepid = 0; … … 356 370 return -ENOMEM; 357 371 } 358 fp->writable = 1;359 372 struct sockaddr_in *raddr = &fp->psock->raddr4; 360 373 memset(raddr, 0, sizeof(*raddr)); … … 384 397 } 385 398 386 ssize_t shell_send (int fd, const void *buf, size_t len, int flags)399 ssize_t shell_sendto(int fd, const void *buf, size_t len, int flags, const struct sockaddr *addr, socklen_t alen) 387 400 { 388 401 SOCKET *fp = fd_to_fp(fd); … … 396 409 switch (fp->psock->type) { 397 410 case SOCK_STREAM: { 398 fp->writable = 0; 411 if ((addr != NULL) || (alen != 0)) { 412 return -EISCONN; 413 } 414 399 415 if (flags & MSG_OOB) { 400 416 ret = tcp_snd_oob(fp->psock->cepid, (void *)buf, len, SOCKET_TIMEOUT); … … 404 420 } 405 421 else { 406 ret = tcp_snd_dat(fp->psock->cepid, (void *)buf, len, SOCKET_TIMEOUT); 407 if (ret < 0) { 408 return -ECOMM; 409 } 410 } 411 break; 412 } 413 case SOCK_DGRAM: { 414 return -EINVAL; 415 } 416 } 417 break; 418 } 419 case AF_INET6: { 420 return -EAFNOSUPPORT; 421 } 422 } 423 424 return ret; 425 } 426 427 ssize_t shell_sendto(int fd, const void *buf, size_t len, int flags, const struct sockaddr *addr, socklen_t alen) 428 { 429 SOCKET *fp = fd_to_fp(fd); 430 if (fp == NULL) { 431 return -EBADF; 432 } 433 434 int ret = 0; 435 switch (fp->psock->family) { 436 case AF_INET: { 437 switch (fp->psock->type) { 438 case SOCK_STREAM: { 439 if ((addr != NULL) && (alen != 0)) { 440 return -EINVAL; 441 } 442 443 fp->writable = 0; 444 if (flags & MSG_OOB) { 445 ret = tcp_snd_oob(fp->psock->cepid, (void *)buf, len, SOCKET_TIMEOUT); 446 if (ret < 0) { 447 return -ECOMM; 448 } 449 } 450 else { 451 ret = tcp_snd_dat(fp->psock->cepid, (void *)buf, len, SOCKET_TIMEOUT); 452 if (ret < 0) { 453 return -ECOMM; 454 } 422 for (;;) { 423 ret = tcp_snd_dat(fp->psock->cepid, (void *)buf, len, SOCKET_TIMEOUT); 424 if (ret < 0) { 425 if (ret == E_TMOUT) 426 return -ETIME; 427 return -ECOMM; 428 } 429 len -= ret; 430 if (len <= 0) 431 break; 432 buf = (const void *)&((uint8_t *)buf)[ret]; 433 } 455 434 } 456 435 break; … … 458 437 case SOCK_DGRAM: { 459 438 int sz = alen; 460 if ( sz < 8) {439 if ((addr == NULL) || (sz < 8)) { 461 440 return -EINVAL; 462 441 } … … 465 444 memcpy(raddr, addr, sz); 466 445 T_IPV4EP rep = { ntohl(raddr->sin_addr.s_addr), ntohs(raddr->sin_port) }; 467 fp->writable = 0;468 446 ret = udp_snd_dat(fp->psock->cepid, &rep, (void *)buf, len, 469 (fp->psock->flags & O_NONBLOCK) ? 0: SOCKET_TIMEOUT);447 (fp->psock->flags & O_NONBLOCK) ? TMO_POL : SOCKET_TIMEOUT); 470 448 if (ret < 0) { 471 return -ECOMM;449 return (ret == E_TMOUT) ? -ETIME : -ECOMM; 472 450 } 473 451 break; … … 490 468 } 491 469 492 ssize_t shell_recv (int fd, void *buf, size_t len, int flags)470 ssize_t shell_recvfrom(int fd, void *__restrict buf, size_t len, int flags, struct sockaddr *__restrict addr, socklen_t *__restrict alen) 493 471 { 494 472 SOCKET *fp = fd_to_fp(fd); … … 505 483 ret = tcp_rcv_oob(fp->psock->cepid, buf, len); 506 484 if (ret < 0) { 485 syslog(LOG_ERROR, "tcp_rcv_oob => %d", ret); 507 486 return -ECOMM; 508 487 } 509 488 } 510 489 else { 511 ret = tcp_rcv_dat(fp->psock->cepid, buf, len, TMO_FEVR); 490 int rsz, tmp; 491 if (fp->psock->input == NULL) { 492 ret = wai_sem(SEM_FILEDESC); 493 if (ret < 0) { 494 syslog(LOG_ERROR, "wai_sem => %d", ret); 495 } 496 fp->psock->len = 0; 497 ret = sig_sem(SEM_FILEDESC); 498 if (ret < 0) { 499 syslog(LOG_ERROR, "sig_sem => %d", ret); 500 } 501 ret = tcp_rcv_buf(fp->psock->cepid, &fp->psock->input, TMO_FEVR); 502 if (ret < 0) { 503 syslog(LOG_ERROR, "tcp_rcv_buf => %d", ret); 504 return -ECOMM; 505 } 506 rsz = ret; 507 } 508 else 509 rsz = fp->psock->len; 510 tmp = rsz; 511 if (rsz > len) 512 rsz = len; 513 if (rsz >= 0) { 514 memcpy(buf, fp->psock->input, rsz); 515 ret = wai_sem(SEM_FILEDESC); 516 if (ret < 0) { 517 syslog(LOG_ERROR, "wai_sem => %d", ret); 518 } 519 fp->psock->len = tmp - rsz; 520 ret = sig_sem(SEM_FILEDESC); 521 if (ret < 0) { 522 syslog(LOG_ERROR, "sig_sem => %d", ret); 523 } 524 if (tmp - rsz == 0) { 525 fp->psock->input = NULL; 526 } 527 else 528 fp->psock->input = (void *)&((uint8_t *)fp->psock->input)[rsz]; 529 ret = tcp_rel_buf(fp->psock->cepid, rsz); 530 if ((ret != E_OBJ) && (ret < 0)) { 531 syslog(LOG_ERROR, "tcp_rel_buf => %d", ret); 532 //return -ECOMM; 533 } 534 } 535 ret = rsz; 536 } 537 break; 538 } 539 case SOCK_DGRAM: { 540 struct sockaddr_in *raddr = &fp->psock->raddr4; 541 int rsz; 542 ret = wai_sem(SEM_FILEDESC); 543 if (ret < 0) { 544 syslog(LOG_ERROR, "wai_sem => %d", ret); 545 } 546 T_NET_BUF *input = fp->psock->input; 547 if (input == NULL) { 548 ret = sig_sem(SEM_FILEDESC); 512 549 if (ret < 0) { 513 return -ECOMM; 514 } 515 } 516 break; 517 } 518 case SOCK_DGRAM: { 519 T_IPV4EP rep = { 0, 0 }; 520 ret = udp_rcv_dat(fp->psock->cepid, &rep, buf, len, (fp->psock->flags & O_NONBLOCK) ? 0 : TMO_FEVR); 521 if (ret < 0) { 522 return -ECOMM; 523 } 524 } 525 } 526 break; 527 } 528 case AF_INET6: { 529 return -EAFNOSUPPORT; 530 } 531 } 532 533 return ret; 534 } 535 536 ssize_t shell_recvfrom(int fd, void *buf, size_t len, int flags, struct sockaddr *__restrict addr, socklen_t *__restrict alen) 537 { 538 SOCKET *fp = fd_to_fp(fd); 539 if (fp == NULL) { 540 return -EBADF; 541 } 542 543 int ret = 0; 544 switch (fp->psock->family) { 545 case AF_INET: { 546 switch (fp->psock->type) { 547 case SOCK_STREAM: { 548 if (flags & MSG_OOB) { 549 ret = tcp_rcv_oob(fp->psock->cepid, buf, len); 550 syslog(LOG_ERROR, "sig_sem => %d", ret); 551 } 552 553 T_IPV4EP rep = { 0, 0 }; 554 ret = udp_rcv_dat(fp->psock->cepid, &rep, buf, len, 555 (fp->psock->flags & O_NONBLOCK) ? TMO_POL : SOCKET_TIMEOUT); 550 556 if (ret < 0) { 551 return -ECOMM; 557 syslog(LOG_ERROR, "udp_rcv_buf => %d", ret); 558 return (ret == E_TMOUT) ? -ETIME : -ECOMM; 559 } 560 rsz = ret; 561 if ((addr != NULL) && (alen != NULL)) { 562 ret = wai_sem(SEM_FILEDESC); 563 if (ret < 0) { 564 syslog(LOG_ERROR, "wai_sem => %d", ret); 565 } 566 int sz = *alen; 567 memset(raddr, 0, sizeof(fp->psock->raddr4)); 568 raddr->sin_family = AF_INET; 569 raddr->sin_port = htons(rep.portno); 570 raddr->sin_addr.s_addr = htonl(rep.ipaddr); 571 if (sz > sizeof(fp->psock->raddr4)) 572 sz = sizeof(fp->psock->raddr4); 573 memcpy(addr, raddr, sz); 574 *alen = sz; 575 ret = sig_sem(SEM_FILEDESC); 576 if (ret < 0) { 577 syslog(LOG_ERROR, "sig_sem => %d", ret); 578 } 552 579 } 553 580 } 554 581 else { 555 ret = tcp_rcv_dat(fp->psock->cepid, buf, len, TMO_FEVR); 582 rsz = fp->psock->len; 583 void *pbuf = fp->psock->buf; 584 fp->psock->input = NULL; 585 fp->psock->len = 0; 586 fp->psock->buf = NULL; 587 if ((addr != NULL) && (alen != NULL)) { 588 int sz = *alen; 589 if (sz > sizeof(fp->psock->raddr4)) 590 sz = sizeof(fp->psock->raddr4); 591 memcpy(addr, raddr, sz); 592 *alen = sz; 593 } 594 ret = sig_sem(SEM_FILEDESC); 556 595 if (ret < 0) { 557 return -ECOMM; 558 } 559 } 560 break; 561 } 562 case SOCK_DGRAM: { 563 T_IPV4EP rep = { 0, 0 }; 564 ret = udp_rcv_dat(fp->psock->cepid, &rep, buf, len, TMO_FEVR); 565 if (ret < 0) { 566 return -ECOMM; 567 } 568 int sz = *alen; 569 struct sockaddr_in raddr; 570 memset(&raddr, 0, sizeof(raddr)); 571 raddr.sin_family = AF_INET; 572 raddr.sin_port = htons(rep.portno); 573 raddr.sin_addr.s_addr = htonl(rep.ipaddr); 574 if (sz > sizeof(raddr)) 575 sz = sizeof(raddr); 576 memcpy(addr, &raddr, sz); 596 syslog(LOG_ERROR, "sig_sem => %d", ret); 597 } 598 if (rsz > len) 599 rsz = len; 600 memcpy(buf, pbuf, rsz); 601 ret = rel_net_buf(input); 602 if (ret < 0) { 603 syslog(LOG_ERROR, "rel_net_buf => %d", ret); 604 //return -ECOMM; 605 } 606 } 607 ret = rsz; 577 608 } 578 609 } … … 830 861 int tcp_fd_close(struct _IO_FILE *fp) 831 862 { 832 ER ret; 833 834 free(fp->psock->buf); 835 fp->psock->buf = NULL; 863 ER ret, ret2; 836 864 837 865 switch (fp->psock->family) { … … 844 872 } 845 873 ret = tcp_cls_cep(cepid, (fp->psock->repid != 0) ? 0 : SOCKET_TIMEOUT); 846 if (ret < 0) { 847 //return -1; 848 } 849 ret = tcp_del_cep(cepid); 874 ret2 = tcp_del_cep(cepid); 875 free(fp->psock->buf); 876 fp->psock->buf = NULL; 850 877 delete_tcp_fd(cepid); 851 878 delete_id(tcp_cepid_table, tcp_cepid_table_count, cepid); 852 if ( ret < 0) {853 return -EINVAL;879 if ((ret < 0) || (ret2 < 0)) { 880 return (ret == E_TMOUT) ? -ETIME : -EINVAL; 854 881 } 855 882 } … … 857 884 ID repid = fp->psock->repid; 858 885 ret = tcp_del_rep(repid); 886 free(fp->psock->buf); 887 fp->psock->buf = NULL; 859 888 delete_tcp_fd(tmax_tcp_cepid + repid); 860 889 delete_id(tcp_repid_table, tcp_repid_table_count, repid); … … 864 893 } 865 894 else { 895 free(fp->psock->buf); 896 fp->psock->buf = NULL; 866 897 return -EINVAL; 867 898 } … … 878 909 size_t tcp_fd_read(struct _IO_FILE *fp, unsigned char *dst, size_t dstsz) 879 910 { 880 return shell_recv (fp->fd, dst, dstsz, 0);911 return shell_recvfrom(fp->fd, dst, dstsz, 0, NULL, NULL); 881 912 } 882 913 883 914 size_t tcp_fd_write(struct _IO_FILE *fp, const unsigned char *src, size_t srcsz) 884 915 { 885 return shell_send (fp->fd, src, srcsz, 0);916 return shell_sendto(fp->fd, src, srcsz, 0, NULL, 0); 886 917 } 887 918 … … 901 932 ID cepid; 902 933 903 free(fp->psock->buf);904 fp->psock->buf = NULL;905 906 934 switch (fp->psock->family) { 907 935 case AF_INET: { 908 936 cepid = fp->psock->cepid; 909 937 ret = udp_del_cep(cepid); 938 //free(fp->psock->buf); 939 //fp->psock->buf = NULL; 910 940 delete_udp_fd(cepid); 911 941 delete_id(udp_cepid_table, udp_cepid_table_count, cepid); … … 925 955 size_t udp_fd_read(struct _IO_FILE *fp, unsigned char *dst, size_t dstsz) 926 956 { 927 return shell_recv (fp->fd, dst, dstsz, 0);957 return shell_recvfrom(fp->fd, dst, dstsz, 0, NULL, NULL); 928 958 } 929 959 930 960 size_t udp_fd_write(struct _IO_FILE *fp, const unsigned char *src, size_t srcsz) 931 961 { 932 return shell_send (fp->fd, src, srcsz, 0);962 return shell_sendto(fp->fd, src, srcsz, 0, NULL, 0); 933 963 } 934 964 -
asp3_tinet_ecnl_rx/trunk/ntshell/src/socket_stub.h
r337 r364 99 99 int buf_size; 100 100 unsigned char *buf; 101 void *input; 102 int len; 101 103 } socket_t; 102 104 -
asp3_tinet_ecnl_rx/trunk/ntshell/src/syscall.c
r359 r364 172 172 173 173 long SYS_futex() { 174 int futex(int *uaddr, int op, int val, const struct timespec *timeout, int *uaddr2, int val3); 174 175 return no_implement("futex\n"); 175 176 } … … 280 281 281 282 long SYS_recv(long a, long b, long c, long d) { 282 return shell_recv ((int)a, (void *)b, (size_t)c, (int)d);283 return shell_recvfrom((int)a, (void *)b, (size_t)c, (int)d, NULL, NULL); 283 284 } 284 285 285 286 long SYS_recvfrom(long a, long b, long c, long d, long e, long f) { 286 if (a == 0) 287 return shell_recv(a, (void *)b, (size_t)c, (int)d); 288 else 289 return shell_recvfrom(a, (void *)b, (size_t)c, (int)d, (struct sockaddr *)e, (socklen_t *)f); 287 return shell_recvfrom(a, (void *)b, (size_t)c, (int)d, (struct sockaddr *)e, (socklen_t *)f); 290 288 } 291 289 … … 315 313 316 314 long SYS_send(long a, long b, long c, long d) { 317 return shell_send ((int)a, (const void *)b, (size_t)c, (int)d);315 return shell_sendto((int)a, (const void *)b, (size_t)c, (int)d, NULL, 0); 318 316 } 319 317 … … 323 321 324 322 long SYS_sendto(long a, long b, long c, long d, long e, long f) { 325 if (a == 0) 326 return shell_send(a, (const void *)b, (size_t)c, (int)d); 327 else 328 return shell_sendto(a, (const void *)b, (size_t)c, (int)d, (const struct sockaddr *)e, (socklen_t)f); 323 return shell_sendto(a, (const void *)b, (size_t)c, (int)d, (const struct sockaddr *)e, (socklen_t)f); 329 324 } 330 325 … … 392 387 return shell_writev((int)a, (const struct iovec *)b, (size_t)c); 393 388 } 389 390 long SYS_dup() 391 { 392 return no_implement("dup\n"); 393 } 394 395 long SYS_dup2() 396 { 397 return no_implement("dup2\n"); 398 } 399 400 long SYS_pipe() 401 { 402 return no_implement("pipe\n"); 403 } 404 405 long SYS_readlink() 406 { 407 return no_implement("readlink\n"); 408 } 409 410 long SYS_symlink() 411 { 412 return no_implement("symlink\n"); 413 } 414 415 long SYS_umask() 416 { 417 return no_implement("umask\n"); 418 } 419 420 long SYS_execve() 421 { 422 return no_implement("execve\n"); 423 } 424 425 long SYS_fork() 426 { 427 return no_implement("fork\n"); 428 } 429 430 long SYS_wait4() 431 { 432 return no_implement("wait4\n"); 433 } 434 435 long SYS_socketpair() 436 { 437 return no_implement("socketpair\n"); 438 } 439 440 long SYS_flock() 441 { 442 return no_implement("flock\n"); 443 }
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