Index: asp3_tinet_ecnl_rx/trunk/asp3_dcre/arch/rx630_gcc/prc_kernel_impl.c
===================================================================
--- asp3_tinet_ecnl_rx/trunk/asp3_dcre/arch/rx630_gcc/prc_kernel_impl.c	(revision 359)
+++ asp3_tinet_ecnl_rx/trunk/asp3_dcre/arch/rx630_gcc/prc_kernel_impl.c	(revision 364)
@@ -237,5 +237,5 @@
 #endif /* OMIT_DEFAULT_EXC_HANDLER */
 
-void _start_c(char **args);
+void _start_c(char * const*args);
 
 void
@@ -243,5 +243,5 @@
 {
 	const char *const args[] = {
-		1,
+		(char *)1,
 		"asp3",
 		0,
@@ -268,11 +268,29 @@
 
 __attribute__((weak))
-void SYS_set_tid_address()
-{
-	return 0;//-ENOSYS;
-}
-
-__attribute__((weak))
-void SYS_mmap2()
+long SYS_set_tid_address()
+{
+	return 0;//-ENOSYS;
+}
+
+__attribute__((weak))
+long SYS_gettid()
+{
+	return 0;//-ENOSYS;
+}
+
+__attribute__((weak))
+long SYS_rt_sigprocmask()
+{
+	return 0;//-ENOSYS;
+}
+
+__attribute__((weak))
+long SYS_mmap2()
+{
+	return 0;//-ENOSYS;
+}
+
+__attribute__((weak))
+long SYS_tkill()
 {
 	return 0;//-ENOSYS;
Index: asp3_tinet_ecnl_rx/trunk/asp3_dcre/arch/rx630_gcc/prc_rename.def
===================================================================
--- asp3_tinet_ecnl_rx/trunk/asp3_dcre/arch/rx630_gcc/prc_rename.def	(revision 359)
+++ asp3_tinet_ecnl_rx/trunk/asp3_dcre/arch/rx630_gcc/prc_rename.def	(revision 364)
@@ -18,5 +18,5 @@
 exception
 
-# rx610_kernel_impl.c
+# rx630_kernel_impl.c
 ipr_reg_addr
 ier_reg_addr
Index: asp3_tinet_ecnl_rx/trunk/asp3_dcre/arch/rx630_gcc/prc_support.S
===================================================================
--- asp3_tinet_ecnl_rx/trunk/asp3_dcre/arch/rx630_gcc/prc_support.S	(revision 359)
+++ asp3_tinet_ecnl_rx/trunk/asp3_dcre/arch/rx630_gcc/prc_support.S	(revision 364)
@@ -410,4 +410,5 @@
 dispatcher_idle_loop:
 	setpsw	i							; 全割込み許可
+	wait
 	clrpsw	i							; 全割込み禁止
 
Index: asp3_tinet_ecnl_rx/trunk/asp3_dcre/arch/rx630_gcc/rx630.h
===================================================================
--- asp3_tinet_ecnl_rx/trunk/asp3_dcre/arch/rx630_gcc/rx630.h	(revision 359)
+++ asp3_tinet_ecnl_rx/trunk/asp3_dcre/arch/rx630_gcc/rx630.h	(revision 364)
@@ -1212,6 +1212,6 @@
 #define ICU_IPR254_ADDR			( ( volatile uint8_t __evenaccess * )0x000873FE )
 #define ICU_IPR255_ADDR			( ( volatile uint8_t __evenaccess * )0x000873FF )
-#define ICU_IPR_BIT				( 7U << 0U )
-
+#define ICU_IPR_OFFSET			( 0U )
+#define ICU_IPR_MASK			( 0xFU << ICU_IPR_OFFSET )
 
 /*
@@ -1323,4 +1323,52 @@
 #define SCI6_SCMR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A0C6 )
 #define SCI6_SEMR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A0C7 )
+#define SCI7_SMR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A0E0 )
+#define SCI7_BRR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A0E1 )
+#define SCI7_SCR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A0E2 )
+#define SCI7_TDR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A0E3 )
+#define SCI7_SSR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A0E4 )
+#define SCI7_RDR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A0E5 )
+#define SCI7_SCMR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A0E6 )
+#define SCI7_SEMR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A0E7 )
+#define SCI8_SMR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A100 )
+#define SCI8_BRR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A101 )
+#define SCI8_SCR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A102 )
+#define SCI8_TDR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A103 )
+#define SCI8_SSR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A104 )
+#define SCI8_RDR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A105 )
+#define SCI8_SCMR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A106 )
+#define SCI8_SEMR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A107 )
+#define SCI9_SMR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A120 )
+#define SCI9_BRR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A121 )
+#define SCI9_SCR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A122 )
+#define SCI9_TDR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A123 )
+#define SCI9_SSR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A124 )
+#define SCI9_RDR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A125 )
+#define SCI9_SCMR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A126 )
+#define SCI9_SEMR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A127 )
+#define SCI10_SMR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A140 )
+#define SCI10_BRR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A141 )
+#define SCI10_SCR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A142 )
+#define SCI10_TDR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A143 )
+#define SCI10_SSR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A144 )
+#define SCI10_RDR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A145 )
+#define SCI10_SCMR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A146 )
+#define SCI10_SEMR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A147 )
+#define SCI11_SMR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A160 )
+#define SCI11_BRR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A161 )
+#define SCI11_SCR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A162 )
+#define SCI11_TDR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A163 )
+#define SCI11_SSR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A164 )
+#define SCI11_RDR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A165 )
+#define SCI11_SCMR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A166 )
+#define SCI11_SEMR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A167 )
+#define SCI12_SMR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A300 )
+#define SCI12_BRR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A301 )
+#define SCI12_SCR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A302 )
+#define SCI12_TDR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A303 )
+#define SCI12_SSR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A304 )
+#define SCI12_RDR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A305 )
+#define SCI12_SCMR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A306 )
+#define SCI12_SEMR_ADDR			( ( volatile uint8_t __evenaccess * )0x0008A307 )
 #define SCI_SMR_CKS_BIT			( 3U << 0U )
 #define SCI_SMR_STOP_BIT		( 1U << 3U )
@@ -1515,4 +1563,23 @@
 #define PORTG_ODR1_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C0A1 )
 #define PORTJ_ODR1_ADDR			( ( volatile uint8_t __evenaccess * )0x0008C0A5 )
+#define PORT_ODR_Pm0_OFFSET		( 0U )
+#define PORT_ODR_Pm0_MASK		( 0x3U << PORT_ODR_Pm0_OFFSET )
+#define PORT_ODR_Pm1_OFFSET		( 2U )
+#define PORT_ODR_Pm1_MASK		( 0x3U << PORT_ODR_Pm1_OFFSET )
+#define PORT_ODR_Pm2_OFFSET		( 4U )
+#define PORT_ODR_Pm2_MASK		( 0x3U << PORT_ODR_Pm2_OFFSET )
+#define PORT_ODR_Pm3_OFFSET		( 6U )
+#define PORT_ODR_Pm3_MASK		( 0x3U << PORT_ODR_Pm3_OFFSET )
+#define PORT_ODR_Pm4_OFFSET		( 0U )
+#define PORT_ODR_Pm4_MASK		( 0x3U << PORT_ODR_Pm4_OFFSET )
+#define PORT_ODR_Pm5_OFFSET		( 2U )
+#define PORT_ODR_Pm5_MASK		( 0x3U << PORT_ODR_Pm5_OFFSET )
+#define PORT_ODR_Pm6_OFFSET		( 4U )
+#define PORT_ODR_Pm6_MASK		( 0x3U << PORT_ODR_Pm6_OFFSET )
+#define PORT_ODR_Pm7_OFFSET		( 6U )
+#define PORT_ODR_Pm7_MASK		( 0x3U << PORT_ODR_Pm7_OFFSET )
+#define PORT_ODR_CMOS			( 0U )
+#define PORT_ODR_NCH_OPEN_DRAIN	( 1U )
+#define PORT_ODR_PCH_OPEN_DRAIN	( 2U )
 
 /*
@@ -1728,4 +1795,10 @@
 #define TPU10_TMDR_ADDR			( ( volatile uint8_t __evenaccess * )0x000881C1 )
 #define TPU11_TMDR_ADDR			( ( volatile uint8_t __evenaccess * )0x000881D1 )
+#define TPU_TMDR_MD_OFFSET		( 0U )
+#define TPU_TMDR_MD_MASK		( 0xFU << TPU_TMDR_MD_OFFSET )
+#define TPU_TMDR_BFA_BIT		( 0x10 )
+#define TPU_TMDR_BFB_BIT		( 0x20 )
+#define TPU_TMDR_ICSELB_BIT		( 0x40 )
+#define TPU_TMDR_ICSELD_BIT		( 0x80 )
 
 #define TPU0_TIOR_ADDR			( ( volatile uint8_t __evenaccess * )0x000881C0 )
@@ -1746,8 +1819,12 @@
 #define TPU10_TIOR_ADDR			( ( volatile uint8_t __evenaccess * )0x000881C2 )
 #define TPU11_TIOR_ADDR			( ( volatile uint8_t __evenaccess * )0x000881D2 )
-#define TPU_TIORL_IOA_OFFSET	( 0U )
-#define TPU_TIORL_IOA_MASK		( 0xFU << TPU_TIORL_IOA_OFFSET )
-#define TPU_TIORL_IOB_OFFSET	( 4U )
-#define TPU_TIORL_IOB_MASK		( 0xFU << TPU_TIORL_IOB_OFFSET )
+#define TPU_TIOR_IOA_OFFSET	( 0U )
+#define TPU_TIOR_IOA_MASK		( 0xFU << TPU_TIOR_IOA_OFFSET )
+#define TPU_TIOR_IOB_OFFSET	( 4U )
+#define TPU_TIOR_IOB_MASK		( 0xFU << TPU_TIOR_IOB_OFFSET )
+#define TPU_TIORH_IOA_OFFSET	( 0U )
+#define TPU_TIORH_IOA_MASK		( 0xFU << TPU_TIORH_IOA_OFFSET )
+#define TPU_TIORH_IOB_OFFSET	( 4U )
+#define TPU_TIORH_IOB_MASK		( 0xFU << TPU_TIORH_IOB_OFFSET )
 #define TPU_TIORL_IOC_OFFSET	( 0U )
 #define TPU_TIORL_IOC_MASK		( 0xFU << TPU_TIORL_IOC_OFFSET )
@@ -1806,4 +1883,30 @@
 #define TPU_TSYR_SYNC5_BIT		( 0x01U << 5U )
 
+#define TPU0_TIER_ADDR			( ( volatile uint8_t __evenaccess *)0x00088114 )
+#define TPU1_TIER_ADDR			( ( volatile uint8_t __evenaccess *)0x00088124 )
+#define TPU2_TIER_ADDR			( ( volatile uint8_t __evenaccess *)0x00088134 )
+#define TPU3_TIER_ADDR			( ( volatile uint8_t __evenaccess *)0x00088144 )
+#define TPU4_TIER_ADDR			( ( volatile uint8_t __evenaccess *)0x00088154 )
+#define TPU5_TIER_ADDR			( ( volatile uint8_t __evenaccess *)0x00088164 )
+#define TPU6_TIER_ADDR			( ( volatile uint8_t __evenaccess *)0x00088184 )
+#define TPU7_TIER_ADDR			( ( volatile uint8_t __evenaccess *)0x00088194 )
+#define TPU8_TIER_ADDR			( ( volatile uint8_t __evenaccess *)0x000881A4 )
+#define TPU9_TIER_ADDR			( ( volatile uint8_t __evenaccess *)0x000881B4 )
+#define TPU10_TIER_ADDR			( ( volatile uint8_t __evenaccess *)0x000881C4 )
+#define TPU11_TIER_ADDR			( ( volatile uint8_t __evenaccess *)0x000881D4 )
+
+#define TPU0_TCNT_ADDR			( ( volatile uint16_t __evenaccess *)0x00088116 )
+#define TPU1_TCNT_ADDR			( ( volatile uint16_t __evenaccess *)0x00088126 )
+#define TPU2_TCNT_ADDR			( ( volatile uint16_t __evenaccess *)0x00088136 )
+#define TPU3_TCNT_ADDR			( ( volatile uint16_t __evenaccess *)0x00088146 )
+#define TPU4_TCNT_ADDR			( ( volatile uint16_t __evenaccess *)0x00088156 )
+#define TPU5_TCNT_ADDR			( ( volatile uint16_t __evenaccess *)0x00088166 )
+#define TPU6_TCNT_ADDR			( ( volatile uint16_t __evenaccess *)0x00088186 )
+#define TPU7_TCNT_ADDR			( ( volatile uint16_t __evenaccess *)0x00088196 )
+#define TPU8_TCNT_ADDR			( ( volatile uint16_t __evenaccess *)0x000881A6 )
+#define TPU9_TCNT_ADDR			( ( volatile uint16_t __evenaccess *)0x000881B6 )
+#define TPU10_TCNT_ADDR			( ( volatile uint16_t __evenaccess *)0x000881C6 )
+#define TPU11_TCNT_ADDR			( ( volatile uint16_t __evenaccess *)0x000881D6 )
+
 /*
  * RSPI
Index: asp3_tinet_ecnl_rx/trunk/asp3_dcre/arch/rx630_gcc/scif.h
===================================================================
--- asp3_tinet_ecnl_rx/trunk/asp3_dcre/arch/rx630_gcc/scif.h	(revision 359)
+++ asp3_tinet_ecnl_rx/trunk/asp3_dcre/arch/rx630_gcc/scif.h	(revision 364)
@@ -59,7 +59,13 @@
 #define SCI5_BASE	((uint32_t)(SCI5_SMR_ADDR))
 #define SCI6_BASE	((uint32_t)(SCI6_SMR_ADDR))
+#define SCI7_BASE	((uint32_t)(SCI7_SMR_ADDR))
+#define SCI8_BASE	((uint32_t)(SCI8_SMR_ADDR))
+#define SCI9_BASE	((uint32_t)(SCI9_SMR_ADDR))
+#define SCI10_BASE	((uint32_t)(SCI10_SMR_ADDR))
+#define SCI11_BASE	((uint32_t)(SCI11_SMR_ADDR))
+/* SCI12は下記のSCI_NUMが使用できない */
 
 /* モジュールストップコントロールレジスタB bit */
-#define SCI_NUM(base)	((base - SCI0_BASE) / 0x20)
+#define SCI_NUM(base)	(((intptr_t)base - SCI0_BASE) / 0x20)
 #define SCI_MSTPCRB_BIT(base)	(1 << (31 - SCI_NUM(base)))
 
@@ -70,6 +76,7 @@
 #define CLK_F64	UINT_C(0x03)
 
-/* シリアルモードレジスタ（SMR) */
+/* シリアルモードレジスタ（SMR） */
 #define CKS			UINT_C(0x03)
+#define MP			UINT_C(0x04)
 #define STOP		UINT_C(0x08)
 #define PM			UINT_C(0x10)
@@ -80,5 +87,5 @@
 #define ASYNC_8BIT	UINT_C(0x40)
 
-/* シリアルコントロールレジスタ（SCR) */
+/* シリアルコントロールレジスタ（SCR） */
 #define CKE			UINT_C(0x03)
 #define TEIE		UINT_C(0x04)
@@ -94,7 +101,38 @@
 #define ORER		UINT_C(0x20)
 
-/* シリアル拡張モードレジスタ（SEMR) */
+/* スマートカードモードレジスタ（SCMR） */
+#define SMIF		UINT_C(0x01)
+#define SINV		UINT_C(0x04)
+#define SDIR		UINT_C(0x08)
+#define BCP2		UINT_C(0x80)
+
+/* シリアル拡張モードレジスタ（SEMR） */
 #define ACS0		UINT_C(0x01)
 #define ABCS		UINT_C(0x10)
+#define NFEN		UINT_C(0x20)
+
+/* I2C モードレジスタ1（SIMR1） */
+#define IICM		UINT_C(0x01)
+
+/* I2C モードレジスタ2（SIMR2） */
+#define IICINTM		UINT_C(0x01)
+#define IICCSC		UINT_C(0x02)
+#define IICACKT		UINT_C(0x20)
+
+/* I2C モードレジスタ3（SIMR2） */
+#define IICSTAREQ	UINT_C(0x01)
+#define IICRSTAREQ	UINT_C(0x02)
+#define IICSTPREQ	UINT_C(0x04)
+#define IICSTIF		UINT_C(0x08)
+
+/* I2C ステータスレジスタ（SISR） */
+#define IICACKR		UINT_C(0x01)
+
+/* SPI モードレジスタ（SPMR） */
+#define SSE			UINT_C(0x01)
+#define CTSE		UINT_C(0x02)
+#define MSS			UINT_C(0x04)
+#define CKPOL		UINT_C(0x40)
+#define CKPH 		UINT_C(0x80)
 
 #define SCI_SCR_FLG_ENABLE	(RE | TE)
@@ -104,13 +142,18 @@
  *  SCIレジスタの番地の定義
  */
-#define SCI_SMR(base)		((uint8_t *)(base + 0x00U))
-#define SCI_BRR(base)		((uint8_t *)(base + 0x01U))
-#define SCI_SCR(base)		((uint8_t *)(base + 0x02U))
-#define SCI_TDR(base)		((uint8_t *)(base + 0x03U))
-#define SCI_SSR(base)		((uint8_t *)(base + 0x04U))
-#define SCI_RDR(base)		((uint8_t *)(base + 0x05U))
-#define SCI_SCMR(base)		((uint8_t *)(base + 0x06U))
-#define SCI_SEMR(base)		((uint8_t *)(base + 0x07U))
-#define SCI_SNFR(base)		((uint8_t *)(base + 0x08U))
+#define SCI_SMR(base)		((uint8_t *)((intptr_t)base + 0x00U))
+#define SCI_BRR(base)		((uint8_t *)((intptr_t)base + 0x01U))
+#define SCI_SCR(base)		((uint8_t *)((intptr_t)base + 0x02U))
+#define SCI_TDR(base)		((uint8_t *)((intptr_t)base + 0x03U))
+#define SCI_SSR(base)		((uint8_t *)((intptr_t)base + 0x04U))
+#define SCI_RDR(base)		((uint8_t *)((intptr_t)base + 0x05U))
+#define SCI_SCMR(base)		((uint8_t *)((intptr_t)base + 0x06U))
+#define SCI_SEMR(base)		((uint8_t *)((intptr_t)base + 0x07U))
+#define SCI_SNFR(base)		((uint8_t *)((intptr_t)base + 0x08U))
+#define SCI_SIMR1(base)		((uint8_t *)((intptr_t)base + 0x09U))
+#define SCI_SIMR2(base)		((uint8_t *)((intptr_t)base + 0x0AU))
+#define SCI_SIMR3(base)		((uint8_t *)((intptr_t)base + 0x0BU))
+#define SCI_SISR(base)		((uint8_t *)((intptr_t)base + 0x0CU))
+#define SCI_SPMR(base)		((uint8_t *)((intptr_t)base + 0x0DU))
 
 #ifndef TOPPERS_MACRO_ONLY
