Changeset 364 for asp3_tinet_ecnl_rx/trunk/asp3_dcre/arch/rx630_gcc/scif.h
- Timestamp:
- Feb 1, 2019, 9:57:09 PM (5 years ago)
- File:
-
- 1 edited
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asp3_tinet_ecnl_rx/trunk/asp3_dcre/arch/rx630_gcc/scif.h
r337 r364 59 59 #define SCI5_BASE ((uint32_t)(SCI5_SMR_ADDR)) 60 60 #define SCI6_BASE ((uint32_t)(SCI6_SMR_ADDR)) 61 #define SCI7_BASE ((uint32_t)(SCI7_SMR_ADDR)) 62 #define SCI8_BASE ((uint32_t)(SCI8_SMR_ADDR)) 63 #define SCI9_BASE ((uint32_t)(SCI9_SMR_ADDR)) 64 #define SCI10_BASE ((uint32_t)(SCI10_SMR_ADDR)) 65 #define SCI11_BASE ((uint32_t)(SCI11_SMR_ADDR)) 66 /* SCI12は下記のSCI_NUMが使用できない */ 61 67 62 68 /* モジュールストップコントロールレジスタB bit */ 63 #define SCI_NUM(base) (( base - SCI0_BASE) / 0x20)69 #define SCI_NUM(base) (((intptr_t)base - SCI0_BASE) / 0x20) 64 70 #define SCI_MSTPCRB_BIT(base) (1 << (31 - SCI_NUM(base))) 65 71 … … 70 76 #define CLK_F64 UINT_C(0x03) 71 77 72 /* シリアルモードレジスタ(SMR )*/78 /* シリアルモードレジスタ(SMR) */ 73 79 #define CKS UINT_C(0x03) 80 #define MP UINT_C(0x04) 74 81 #define STOP UINT_C(0x08) 75 82 #define PM UINT_C(0x10) … … 80 87 #define ASYNC_8BIT UINT_C(0x40) 81 88 82 /* シリアルコントロールレジスタ(SCR )*/89 /* シリアルコントロールレジスタ(SCR) */ 83 90 #define CKE UINT_C(0x03) 84 91 #define TEIE UINT_C(0x04) … … 94 101 #define ORER UINT_C(0x20) 95 102 96 /* シリアル拡張モードレジスタ(SEMR) */ 103 /* スマートカードモードレジスタ(SCMR) */ 104 #define SMIF UINT_C(0x01) 105 #define SINV UINT_C(0x04) 106 #define SDIR UINT_C(0x08) 107 #define BCP2 UINT_C(0x80) 108 109 /* シリアル拡張モードレジスタ(SEMR) */ 97 110 #define ACS0 UINT_C(0x01) 98 111 #define ABCS UINT_C(0x10) 112 #define NFEN UINT_C(0x20) 113 114 /* I2C モードレジスタ1(SIMR1) */ 115 #define IICM UINT_C(0x01) 116 117 /* I2C モードレジスタ2(SIMR2) */ 118 #define IICINTM UINT_C(0x01) 119 #define IICCSC UINT_C(0x02) 120 #define IICACKT UINT_C(0x20) 121 122 /* I2C モードレジスタ3(SIMR2) */ 123 #define IICSTAREQ UINT_C(0x01) 124 #define IICRSTAREQ UINT_C(0x02) 125 #define IICSTPREQ UINT_C(0x04) 126 #define IICSTIF UINT_C(0x08) 127 128 /* I2C ステータスレジスタ(SISR) */ 129 #define IICACKR UINT_C(0x01) 130 131 /* SPI モードレジスタ(SPMR) */ 132 #define SSE UINT_C(0x01) 133 #define CTSE UINT_C(0x02) 134 #define MSS UINT_C(0x04) 135 #define CKPOL UINT_C(0x40) 136 #define CKPH UINT_C(0x80) 99 137 100 138 #define SCI_SCR_FLG_ENABLE (RE | TE) … … 104 142 * SCIレジスタの番地の定義 105 143 */ 106 #define SCI_SMR(base) ((uint8_t *)(base + 0x00U)) 107 #define SCI_BRR(base) ((uint8_t *)(base + 0x01U)) 108 #define SCI_SCR(base) ((uint8_t *)(base + 0x02U)) 109 #define SCI_TDR(base) ((uint8_t *)(base + 0x03U)) 110 #define SCI_SSR(base) ((uint8_t *)(base + 0x04U)) 111 #define SCI_RDR(base) ((uint8_t *)(base + 0x05U)) 112 #define SCI_SCMR(base) ((uint8_t *)(base + 0x06U)) 113 #define SCI_SEMR(base) ((uint8_t *)(base + 0x07U)) 114 #define SCI_SNFR(base) ((uint8_t *)(base + 0x08U)) 144 #define SCI_SMR(base) ((uint8_t *)((intptr_t)base + 0x00U)) 145 #define SCI_BRR(base) ((uint8_t *)((intptr_t)base + 0x01U)) 146 #define SCI_SCR(base) ((uint8_t *)((intptr_t)base + 0x02U)) 147 #define SCI_TDR(base) ((uint8_t *)((intptr_t)base + 0x03U)) 148 #define SCI_SSR(base) ((uint8_t *)((intptr_t)base + 0x04U)) 149 #define SCI_RDR(base) ((uint8_t *)((intptr_t)base + 0x05U)) 150 #define SCI_SCMR(base) ((uint8_t *)((intptr_t)base + 0x06U)) 151 #define SCI_SEMR(base) ((uint8_t *)((intptr_t)base + 0x07U)) 152 #define SCI_SNFR(base) ((uint8_t *)((intptr_t)base + 0x08U)) 153 #define SCI_SIMR1(base) ((uint8_t *)((intptr_t)base + 0x09U)) 154 #define SCI_SIMR2(base) ((uint8_t *)((intptr_t)base + 0x0AU)) 155 #define SCI_SIMR3(base) ((uint8_t *)((intptr_t)base + 0x0BU)) 156 #define SCI_SISR(base) ((uint8_t *)((intptr_t)base + 0x0CU)) 157 #define SCI_SPMR(base) ((uint8_t *)((intptr_t)base + 0x0DU)) 115 158 116 159 #ifndef TOPPERS_MACRO_ONLY
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