Index: /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/MANIFEST
===================================================================
--- /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/MANIFEST	(revision 307)
+++ /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/MANIFEST	(revision 307)
@@ -0,0 +1,20 @@
+PACKAGE asp3_arch_arm_gcc
+
+MANIFEST
+Makefile.chip
+chip_kernel.h
+chip_kernel.trb
+chip_kernel_impl.c
+chip_kernel_impl.h
+chip_rename.def
+chip_rename.h
+chip_stddef.h
+chip_sym.def
+chip_timer.c
+chip_timer.cfg
+chip_timer.h
+chip_unrename.h
+rza1.h
+scif.h
+tSCIF.c
+tSCIF.cdl
Index: /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/Makefile.chip
===================================================================
--- /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/Makefile.chip	(revision 307)
+++ /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/Makefile.chip	(revision 307)
@@ -0,0 +1,36 @@
+#
+#		Makefile ã®ãããä¾å­é¨ï¼RZ/A1ç¨ï¼
+#
+#  $Id: Makefile.chip 720 2016-04-01 22:16:17Z ertl-hiro $
+# 
+
+#
+#  ãããä¾å­é¨ãã£ã¬ã¯ããªåã®å®ç¾©
+#
+CHIPDIR = $(SRCDIR)/arch/$(CORE)_$(TOOL)/$(CHIP)
+
+#
+#  ã³ã³ãã¤ã«ãªãã·ã§ã³
+#
+INCLUDES := $(INCLUDES) -I$(CHIPDIR)
+COPTS := $(COPTS) -mcpu=cortex-a9
+LDFLAGS := $(LDFLAGS) -mcpu=cortex-a9
+CDEFS := $(CDEFS) -D__TARGET_ARCH_ARM=7
+
+#
+#  ã«ã¼ãã«ã«é¢ããå®ç¾©
+#
+KERNEL_DIRS := $(KERNEL_DIRS) $(CHIPDIR)
+KERNEL_ASMOBJS := $(KERNEL_ASMOBJS) gic_support.o
+KERNEL_COBJS := $(KERNEL_COBJS) chip_kernel_impl.o gic_kernel_impl.o \
+															chip_timer.o
+
+#
+#  ã³ã³ãã£ã®ã¥ã¬ã¼ã¿é¢ä¿ã®å¤æ°ã®å®ç¾©
+#
+CFG_TABS := $(CFG_TABS) --symval-table $(CHIPDIR)/chip_sym.def
+
+#
+#  ã³ã¢ä¾å­é¨
+#
+include $(SRCDIR)/arch/$(CORE)_$(TOOL)/common/Makefile.core
Index: /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_kernel.h
===================================================================
--- /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_kernel.h	(revision 307)
+++ /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_kernel.h	(revision 307)
@@ -0,0 +1,122 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  $Id: chip_kernel.h 727 2016-04-03 00:47:42Z ertl-hiro $
+ */
+
+/*
+ *		kernel.hã®ã¿ã¼ã²ããä¾å­é¨ï¼RZ/A1ç¨ï¼
+ *
+ *  ãã®ããããã¡ã¤ã«ã¯ï¼kernel.hããã¤ã³ã¯ã«ã¼ããããï¼ä»ã®ãã¡ã¤ã«
+ *  ããç´æ¥ã¤ã³ã¯ã«ã¼ããããã¨ã¯ãªãï¼ãã®ãã¡ã¤ã«ãã¤ã³ã¯ã«ã¼ããã
+ *  åã«ï¼t_stddef.hãã¤ã³ã¯ã«ã¼ããããã®ã§ï¼ããã«ä¾å­ãã¦ãããï¼
+ */
+
+#ifndef TOPPERS_CHIP_KERNEL_H
+#define TOPPERS_CHIP_KERNEL_H
+
+/*
+ *  å²è¾¼ã¿åªå
+åº¦ã®ç¯å²
+ */
+#define TMIN_INTPRI		(-31)		/* å²è¾¼ã¿åªå
+åº¦ã®æå°å¤ï¼æé«å¤ï¼*/
+#define TMAX_INTPRI		(-1)		/* å²è¾¼ã¿åªå
+åº¦ã®æå¤§å¤ï¼æä½å¤ï¼*/
+
+/*
+ *  ã¿ã¼ã²ããå®ç¾©ã®å²è¾¼ã¿è¦æ±ã©ã¤ã³å±æ§
+ */
+#define TA_NEGEDGE		0x04U		/* ãã¬ãã£ãã¨ãã¸ããªã¬ */
+#define TA_POSEDGE		0x08U		/* ãã¸ãã£ãã¨ãã¸ããªã¬ */
+#define TA_BOTHEDGE		0x0cU		/* ä¸¡ã¨ãã¸ããªã¬ */
+
+/*
+ *  ãµãã¼ãã§ããæ©è½ã®å®ç¾©
+ *
+ *  ena_intï¼dis_intã¨ãªã¼ãã©ã³ãã³ãã©ããµãã¼ããããã¨ãã§ããï¼
+ */
+#define TOPPERS_TARGET_SUPPORT_ENA_INT		/* ena_int */
+#define TOPPERS_TARGET_SUPPORT_DIS_INT		/* dis_int */
+#define TOPPERS_TARGET_SUPPORT_OVRHDR
+
+/*
+ *  é«åè§£è½ã¿ã¤ãã®ã¿ã¤ãå¨æ
+ *
+ *  2^32 / 33.33â¦ãä¸¸ããå¤ã¨ããï¼
+ */
+#define TCYC_HRTCNT		128849019U
+
+/*
+ *  é«åè§£è½ã¿ã¤ãã®ã«ã¦ã³ãå¤ã®é²ã¿å¹
+
+ */
+#define TSTEP_HRTCNT	1U
+
+/*
+ *  ãªã¼ãã©ã³ãã³ãã©ã®æ®ããã­ã»ããµæéã«æå®ã§ããæå¤§å¤
+ *
+ *  ãã®å¤ãOSã¿ã¤ãã¸ã®è¨­å®å¤ã«å¤æãã¦ã¿ã¤ãã«è¨­å®ããå¾ï¼ã¿ã¤ãã®ç¾
+ *  å¨å¤ãèª­ã¿åºãã¦Î¼ç§åä½ã«å¤æã§ããå¤ã¨ãã¦ããï¼ã¿ã¤ãã®ç¾å¨å¤ã
+ *  Î¼ç§åä½ã«å¤æããæã«34ãå ããããï¼ä»¥ä¸ã®æ¡ä»¶ãæºããæå¤§ã®å¤ã¨
+ *  ããï¼
+ *		(TMAX_OVRTIM * 33 + TMAX_OVRTIM / 3 + 1) + 34 < 2^32
+ */
+#define TMAX_OVRTIM		128849017U
+
+/*
+ *  ã³ã¢ã§å
+±éãªå®ç¾©
+ */
+#include "core_kernel.h"
+
+#endif /* TOPPERS_CHIP_KERNEL_H */
Index: /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_kernel.trb
===================================================================
--- /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_kernel.trb	(revision 307)
+++ /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_kernel.trb	(revision 307)
@@ -0,0 +1,43 @@
+# -*- coding: utf-8 -*-
+# 
+#		ãã¹2ã®çæã¹ã¯ãªããã®ãããä¾å­é¨ï¼RZ/A1ç¨ï¼
+# 
+
+# 
+#  ä½¿ç¨ã§ããå²è¾¼ã¿çªå·ã¨ããã«å¯¾å¿ããå²è¾¼ã¿ãã³ãã©çªå·
+# 
+if $TOPPERS_RZA1H
+  $INTNO_VALID = [ *(0..586) ]
+else
+  $INTNO_VALID = [ *(0..537) ]
+end
+$INHNO_VALID = $INTNO_VALID
+
+#
+#  ã¿ã¼ã²ããå®ç¾©ã®å²è¾¼ã¿è¦æ±ã©ã¤ã³å±æ§
+#
+$TARGET_INTATR = $TA_NEGEDGE|$TA_POSEDGE|$TA_BOTHEDGE
+
+# 
+#  çæã¹ã¯ãªããã®ã³ã¢ä¾å­é¨
+# 
+IncludeTrb("core_kernel.trb")
+
+#
+#  å²è¾¼ã¿è¦æ±ã©ã¤ã³å±æ§ã«é¢ããã¿ã¼ã²ããä¾å­ã®ã¨ã©ã¼ãã§ãã¯
+#
+$cfgData[:CFG_INT].each do |key, params|
+  if $INTNO_IRQ0 <= key && key <= $INTNO_IRQ7
+    # IRQå²è¾¼ã¿ã®å ´å
+    #ï¼TA_EDGEãã»ããããã¦ããå ´åï¼
+    if (params[:intatr] & $TA_EDGE) != 0
+      error_illegal_sym("E_RSATR", params, :intatr, :intno)
+    end
+  else
+    # ãã®ä»ã®å²è¾¼ã¿ã®å ´å
+    #ï¼TA_NEGEDGEï¼TA_POSEDGEï¼TARGET_BOTHEDGEãã»ããããã¦ããå ´åï¼
+    if (params[:intatr] & $TARGET_INTATR) != 0
+      error_illegal_sym("E_RSATR", params, :intatr, :intno)
+    end
+  end
+end
Index: /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_kernel_impl.c
===================================================================
--- /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_kernel_impl.c	(revision 307)
+++ /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_kernel_impl.c	(revision 307)
@@ -0,0 +1,220 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
+ *                              Toyohashi Univ. of Technology, JAPAN
+ *  Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  $Id: chip_kernel_impl.c 720 2016-04-01 22:16:17Z ertl-hiro $
+ */
+
+/*
+ *		ã«ã¼ãã«ã®ãããä¾å­é¨ï¼RZ/A1ç¨ï¼
+ */
+
+#include "kernel_impl.h"
+#include "interrupt.h"
+
+/*
+ *  ãããä¾å­ã®åæå
+ */
+void
+chip_initialize(void)
+{
+	/*
+	 *  ã­ã£ãã·ã¥ããã£ã¹ã¨ã¼ãã«
+	 */
+	arm_disable_cache();
+
+	/*
+	 *  ã³ã¢ä¾å­ã®åæå
+	 */
+	core_initialize();
+
+	/*
+	 *  ã­ã£ãã·ã¥ãã¤ãã¼ãã«
+	 */
+	arm_enable_cache();
+
+	/*
+	 *  GICã®ãã£ã¹ããªãã¥ã¼ã¿ã®åæå
+	 */
+	gicd_initialize();
+
+	/*
+	 *  GICã®CPUã¤ã³ã¿ãã§ã¼ã¹ã®åæå
+	 */
+	gicc_initialize();
+
+	/*
+	 *  åå²äºæ¸¬ã®ç¡å¹åã¨ã¤ãã¼ãã«
+	 */
+	arm_invalidate_bp();
+	arm_enable_bp();
+}
+
+/*
+ *  ãããä¾å­é¨ã®çµäºå¦ç
+ */
+void
+chip_terminate(void)
+{
+	extern void    software_term_hook(void);
+	void (*volatile fp)(void) = software_term_hook;
+
+	/*
+	 *  software_term_hookã¸ã®ãã¤ã³ã¿ãï¼ä¸æ¦volatileæå®ã®ããfpã«ä»£
+	 *  å
+¥ãã¦ããä½¿ãã®ã¯ï¼0ã¨ã®æ¯è¼ãæé©åã§åé¤ãããªãããã«ããã
+	 *  ãã§ããï¼
+	 */
+	if (fp != 0) {
+		(*fp)();
+	}
+
+	/*
+	 *  GICã®CPUã¤ã³ã¿ãã§ã¼ã¹ã®çµäºå¦ç
+	 */
+	gicc_terminate();
+
+	/*
+	 *  GICã®ãã£ã¹ããªãã¥ã¼ã¿ã®çµäºå¦ç
+	 */
+	gicd_terminate();
+
+	/*
+	 *  ã³ã¢ä¾å­ã®çµäºå¦ç
+	 */
+	core_terminate();
+}
+
+/*
+ *  å²è¾¼ã¿è¦æ±ã©ã¤ã³ã®å±æ§ã®è¨­å®
+ *
+ *  ASPã«ã¼ãã«ã§ã®å©ç¨ãæ³å®ãã¦ï¼ãã©ã¡ã¼ã¿ã¨ã©ã¼ã¯ã¢ãµã¼ã·ã§ã³ã§ãã§ã
+ *  ã¯ãã¦ããï¼
+ */
+Inline void
+config_int(INTNO intno, ATR intatr, PRI intpri)
+{
+	assert(VALID_INTNO(intno));
+	assert(TMIN_INTPRI <= intpri && intpri <= TMAX_INTPRI);
+
+	/*
+	 *  å²è¾¼ã¿ãç¦æ­¢
+	 *
+	 *  å²è¾¼ã¿ãåãä»ããã¾ã¾ï¼ã¬ãã«ããªã¬ï¼ã¨ãã¸ããªã¬ã®è¨­å®ãï¼å²
+	 *  è¾¼ã¿åªå
+åº¦ã®è¨­å®ãè¡ãã®ã¯å±éºãªããï¼å²è¾¼ã¿å±æ§ã«ãããããï¼
+	 *  ä¸æ¦ãã¹ã¯ããï¼
+	 */
+	disable_int(intno);
+
+	/*
+	 *  å²è¾¼ã¿ãã³ã³ãã£ã®ã¥ã¬ã¼ã·ã§ã³
+	 */
+#ifdef TOPPERS_SAFEG_SECURE
+	gicd_config_group(intno, 1U);
+#endif /* TOPPERS_SAFEG_SECURE */
+
+	if (INTNO_IRQ0 <= intno && intno <= INTNO_IRQ7) {
+		uint16_t	reg;
+
+		reg = sil_reh_mem(RZA1_ICR1);
+		reg &= ~(0x03U << ((intno - INTNO_IRQ0) * 2));
+		reg |= ((intatr >> 2) << ((intno - INTNO_IRQ0) * 2));
+		sil_wrh_mem(RZA1_ICR1, reg);
+	}
+
+	if ((intatr & TA_EDGE) != 0U) {
+#ifdef GIC_ARM11MPCORE
+		gicd_config(intno, GICD_ICFGRn_EDGE|GICD_ICFGRn_1_N);
+#else /* GIC_ARM11MPCORE */
+		gicd_config(intno, GICD_ICFGRn_EDGE);
+#endif /* GIC_ARM11MPCORE */
+		clear_int(intno);
+	}
+	else {
+#ifdef GIC_ARM11MPCORE
+		gicd_config(intno, GICD_ICFGRn_LEVEL|GICD_ICFGRn_1_N);
+#else /* GIC_ARM11MPCORE */
+		gicd_config(intno, GICD_ICFGRn_LEVEL);
+#endif /* GIC_ARM11MPCORE */
+	}
+
+	/*
+	 *  å²è¾¼ã¿åªå
+åº¦ã¨ã¿ã¼ã²ãããã­ã»ããµãè¨­å®
+	 */
+	gicd_set_priority(intno, INT_IPM(intpri));
+	gicd_set_target(intno, 1U << arm_prc_index());
+
+	/*
+	 * å²è¾¼ã¿ãè¨±å¯
+	 */
+	if ((intatr & TA_ENAINT) != 0U) {
+		enable_int(intno);
+	}
+}
+
+/*
+ *  å²è¾¼ã¿ç®¡çæ©è½ã®åæå
+ */
+void
+initialize_interrupt(void)
+{
+	uint_t			i;
+	const INTINIB	*p_intinib;
+
+	for (i = 0; i < tnum_cfg_intno; i++) {
+		p_intinib = &(intinib_table[i]);
+		config_int(p_intinib->intno, p_intinib->intatr, p_intinib->intpri);
+	}
+}
Index: /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_kernel_impl.h
===================================================================
--- /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_kernel_impl.h	(revision 307)
+++ /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_kernel_impl.h	(revision 307)
@@ -0,0 +1,112 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
+ *                              Toyohashi Univ. of Technology, JAPAN
+ *  Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  $Id: chip_kernel_impl.h 720 2016-04-01 22:16:17Z ertl-hiro $
+ */
+
+/*
+ *		kernel_impl.hã®ãããä¾å­é¨ï¼RZ/A1ç¨ï¼
+ *
+ *  ãã®ããããã¡ã¤ã«ã¯ï¼target_kernel_impl.hï¼ã¾ãã¯ï¼ããããã¤ã³ã¯
+ *  ã«ã¼ãããããã¡ã¤ã«ï¼ã®ã¿ããã¤ã³ã¯ã«ã¼ããããï¼ä»ã®ãã¡ã¤ã«ãã
+ *  ç´æ¥ã¤ã³ã¯ã«ã¼ããã¦ã¯ãªããªãï¼
+ */
+
+#ifndef TOPPERS_CHIP_KERNEL_IMPL_H
+#define TOPPERS_CHIP_KERNEL_IMPL_H
+
+/*
+ *  RZ/A1ã®ãã¼ãã¦ã§ã¢è³æºã®å®ç¾©
+ */
+#include "rza1.h"
+
+/*
+ *  MMUã®ä½¿ç¨ã«é¢ããè¨­å®
+ */
+#define USE_ARM_MMU
+#define USE_ARM_SSECTION
+
+/*
+ *  GICã®ãã£ã¹ããªãã¥ã¼ã¿ã®å²è¾¼ã¿ã³ã³ãã£ã®ã¥ã¬ã¼ã·ã§ã³ã¬ã¸ã¹ã¿ã«è¨­å®
+ *  ããå¤ã«é¢ããå®ç¾©
+ */
+#define GIC_ARM11MPCORE
+
+/*
+ *  GICä¾å­é¨ã®å²è¾¼ã¿ç®¡çæ©è½ã®åæåã¯ä½¿ç¨ããªãï¼
+ */
+#define OMIT_GIC_INITIALIZE_INTERRUPT
+
+/*
+ *  GICã«é¢ããå®ç¾©ï¼ã³ã¢ã§å
+±éãªå®ç¾©
+ *
+ *  core_kernel_impl.hã¯ï¼gic_kernel_impl.hããã¤ã³ã¯ã«ã¼ããããï¼
+ */
+#include "gic_kernel_impl.h"
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ *  ãããä¾å­ã®åæå
+ */
+extern void chip_initialize(void);
+
+/*
+ *  ãããä¾å­ã®çµäºå¦ç
+ */
+extern void chip_terminate(void);
+
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_CHIP_KERNEL_IMPL_H */
Index: /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_rename.def
===================================================================
--- /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_rename.def	(revision 307)
+++ /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_rename.def	(revision 307)
@@ -0,0 +1,17 @@
+# chip_kernel_impl.c
+chip_initialize
+chip_terminate
+
+# chip_timer.c
+target_hrt_initialize
+target_hrt_terminate
+target_hrt_set_event
+target_hrt_raise_event
+target_hrt_handler
+target_ovrtimer_initialize
+target_ovrtimer_terminate
+target_ovrtimer_stop
+target_ovrtimer_get_current
+target_ovrtimer_handler
+
+INCLUDE "core"
Index: /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_rename.h
===================================================================
--- /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_rename.h	(revision 307)
+++ /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_rename.h	(revision 307)
@@ -0,0 +1,29 @@
+/* This file is generated from chip_rename.def by genrename. */
+
+#ifndef TOPPERS_CHIP_RENAME_H
+#define TOPPERS_CHIP_RENAME_H
+
+/*
+ *  chip_kernel_impl.c
+ */
+#define chip_initialize				_kernel_chip_initialize
+#define chip_terminate				_kernel_chip_terminate
+
+/*
+ *  chip_timer.c
+ */
+#define target_hrt_initialize		_kernel_target_hrt_initialize
+#define target_hrt_terminate		_kernel_target_hrt_terminate
+#define target_hrt_set_event		_kernel_target_hrt_set_event
+#define target_hrt_raise_event		_kernel_target_hrt_raise_event
+#define target_hrt_handler			_kernel_target_hrt_handler
+#define target_ovrtimer_initialize	_kernel_target_ovrtimer_initialize
+#define target_ovrtimer_terminate	_kernel_target_ovrtimer_terminate
+#define target_ovrtimer_stop		_kernel_target_ovrtimer_stop
+#define target_ovrtimer_get_current	_kernel_target_ovrtimer_get_current
+#define target_ovrtimer_handler		_kernel_target_ovrtimer_handler
+
+
+#include "core_rename.h"
+
+#endif /* TOPPERS_CHIP_RENAME_H */
Index: /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_serial.c
===================================================================
--- /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_serial.c	(revision 307)
+++ /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_serial.c	(revision 307)
@@ -0,0 +1,254 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2007-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  @(#) $Id: chip_serial.c 2758 2016-03-10 15:15:26Z ertl-honda $
+ */
+
+/*
+ *  ã·ãªã¢ã«I/Oããã¤ã¹ï¼SCIFï¼ãã©ã¤ãï¼RZ/A1ç¨ï¼
+ */
+
+#include <kernel.h>
+#include <t_syslog.h>
+#include "chip_serial.h"
+#include "rza1.h"
+
+static INTNO const intno_sio_bri[TNUM_SIOP] = {
+	INTNO_SCIF_BRI_1,
+	INTNO_SCIF_BRI_2,
+	INTNO_SCIF_BRI_3,
+	INTNO_SCIF_BRI_4,
+	INTNO_SCIF_BRI_5,
+#if TNUM_SIOP > 5
+	INTNO_SCIF_BRI_6,
+	INTNO_SCIF_BRI_7,
+	INTNO_SCIF_BRI_8,
+#endif /* TNUM_SIOP > 5 */
+};
+
+static INTNO const intno_sio_eri[TNUM_SIOP] = {
+	INTNO_SCIF_ERI_1,
+	INTNO_SCIF_ERI_2,
+	INTNO_SCIF_ERI_3,
+	INTNO_SCIF_ERI_4,
+	INTNO_SCIF_ERI_5,
+#if TNUM_SIOP > 5
+	INTNO_SCIF_ERI_6,
+	INTNO_SCIF_ERI_7,
+	INTNO_SCIF_ERI_8,
+#endif /* TNUM_SIOP > 5 */
+};
+
+static INTNO const intno_sio_rxi[TNUM_SIOP] = {
+	INTNO_SCIF_RXI_1,
+	INTNO_SCIF_RXI_2,
+	INTNO_SCIF_RXI_3,
+	INTNO_SCIF_RXI_4,
+	INTNO_SCIF_RXI_5,
+#if TNUM_SIOP > 5
+	INTNO_SCIF_RXI_6,
+	INTNO_SCIF_RXI_7,
+	INTNO_SCIF_RXI_8,
+#endif /* TNUM_SIOP > 5 */
+};
+
+static INTNO const intno_sio_txi[TNUM_SIOP] = {
+	INTNO_SCIF_TXI_1,
+	INTNO_SCIF_TXI_2,
+	INTNO_SCIF_TXI_3,
+	INTNO_SCIF_TXI_4,
+#if TNUM_SIOP > 5
+	INTNO_SCIF_TXI_5,
+	INTNO_SCIF_TXI_6,
+	INTNO_SCIF_TXI_7,
+	INTNO_SCIF_TXI_8,
+#endif /* TNUM_SIOP > 5 */
+};
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãIDããå²è¾¼ã¿çªå·ãåãåºãããã®ãã¯ã­
+ */
+#define INDEX_SIOP(siopid)           ((uint_t)((siopid) - 1))
+#define get_intno_sio_bri(siopid)    (intno_sio_bri[INDEX_SIOP(siopid)])
+#define get_intno_sio_eri(siopid)    (intno_sio_eri[INDEX_SIOP(siopid)])
+#define get_intno_sio_rxi(siopid)    (intno_sio_rxi[INDEX_SIOP(siopid)])
+#define get_intno_sio_txi(siopid)    (intno_sio_txi[INDEX_SIOP(siopid)])
+
+/*
+ *  SIOãã©ã¤ãã®åæå
+ */
+void
+sio_initialize(intptr_t exinf)
+{
+	scif_initialize();
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã®ãªã¼ãã³
+ */
+SIOPCB *
+sio_opn_por(ID siopid, intptr_t exinf)
+{
+	SIOPCB    *p_siopcb;
+	ER        ercd;
+
+	/*
+	 *  ã·ãªã¢ã«I/Oå²è¾¼ã¿ããã¹ã¯ããï¼
+	 */
+	ercd = dis_int(get_intno_sio_rxi(siopid));
+	assert(ercd == E_OK);
+	ercd = dis_int(get_intno_sio_txi(siopid));
+	assert(ercd == E_OK);
+
+	/*
+	 *  ããã¤ã¹ä¾å­ã®ãªã¼ãã³å¦çï¼
+	 */
+	p_siopcb = scif_opn_por(siopid, exinf);
+
+	/*
+	 *  ã·ãªã¢ã«I/Oå²è¾¼ã¿ã®ãã¹ã¯ãè§£é¤ããï¼
+	 */
+	ercd = ena_int(get_intno_sio_rxi(siopid));
+	assert(ercd == E_OK);
+	ercd = ena_int(get_intno_sio_txi(siopid));
+	assert(ercd == E_OK);
+
+	return(p_siopcb);
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã®ã¯ã­ã¼ãº
+ */
+void
+sio_cls_por(SIOPCB *p_siopcb)
+{
+	ER ercd;
+	ID siopid;
+
+	/*
+	 *  ã·ãªã¢ã«I/Oãã¼ãIDã®åå¾
+	 */
+	siopid = scif_get_siopid(p_siopcb);
+
+	/*
+	 *  ããã¤ã¹ä¾å­ã®ã¯ã­ã¼ãºå¦çï¼
+	 */
+	scif_cls_por(p_siopcb);
+
+	/*
+	 *  ã·ãªã¢ã«I/Oå²è¾¼ã¿ããã¹ã¯ããï¼
+	 */
+	ercd = dis_int(intno_sio_rxi[siopid]);
+	assert(ercd == E_OK);
+	ercd = dis_int(intno_sio_txi[siopid]);
+	assert(ercd == E_OK);
+}
+
+/*
+ *  SIOã®å²è¾¼ã¿ãã³ãã©
+ */
+void sio_isr_rxi(intptr_t exinf)
+{
+    scif_rx_isr(exinf);
+}
+void sio_isr_txi(intptr_t exinf)
+{
+    scif_tx_isr(exinf);
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã¸ã®æå­éä¿¡
+ */
+bool_t sio_snd_chr(SIOPCB *siopcb, char c)
+{
+	return(scif_snd_chr(siopcb, c));
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®æå­åä¿¡
+ */
+int_t sio_rcv_chr(SIOPCB *siopcb)
+{
+	return(scif_rcv_chr(siopcb));
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®è¨±å¯
+ */
+void sio_ena_cbr(SIOPCB *siopcb, uint_t cbrtn)
+{
+	scif_ena_cbr(siopcb, cbrtn);
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®ç¦æ­¢
+ */
+void sio_dis_cbr(SIOPCB *siopcb, uint_t cbrtn)
+{
+	scif_dis_cbr(siopcb, cbrtn);
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®éä¿¡å¯è½ã³ã¼ã«ããã¯
+ */
+void scif_irdy_snd(intptr_t exinf)
+{
+	sio_irdy_snd(exinf);
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®åä¿¡éç¥ã³ã¼ã«ããã¯
+ */
+void scif_irdy_rcv(intptr_t exinf)
+{
+	sio_irdy_rcv(exinf);
+}
Index: /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_serial.h
===================================================================
--- /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_serial.h	(revision 307)
+++ /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_serial.h	(revision 307)
@@ -0,0 +1,202 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2007-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  @(#) $Id: chip_serial.h 2758 2016-03-10 15:15:26Z ertl-honda $
+ */
+
+/*
+ *  ã·ãªã¢ã«I/Oããã¤ã¹ï¼SIOï¼ãã©ã¤ãï¼RZ/A1ç¨ï¼
+ */
+
+#ifndef TOPPERS_CHIP_SERIAL_H
+#define TOPPERS_CHIP_SERIAL_H
+
+#include "scif.h"
+
+/*
+ *  SIOã®å²è¾¼ã¿ãã³ãã©ã®ãã¯ã¿çªå·
+ */
+#define INTNO_SCIF_BRI_1        INTNO_SCIF0_BRI    /* å²è¾¼ã¿ãã³ãã©çªå·(BRI) */
+#define INTNO_SCIF_ERI_1        INTNO_SCIF0_ERI    /* å²è¾¼ã¿ãã³ãã©çªå·(ERI) */
+#define INTNO_SCIF_RXI_1        INTNO_SCIF0_RXI    /* å²è¾¼ã¿ãã³ãã©çªå·(RXI) */
+#define INTNO_SCIF_TXI_1        INTNO_SCIF0_TXI    /* å²è¾¼ã¿ãã³ãã©çªå·(TXI) */
+#ifndef INTPRI_SIO_1
+#define INTPRI_SIO_1            (-4)      /* å²è¾¼ã¿åªå
+åº¦ */
+#endif  /* INTPRI_SIO_1 */
+#define INTATR_SIO_1            0U        /* å²è¾¼ã¿å±æ§ */
+
+#define INTNO_SCIF_BRI_2        INTNO_SCIF1_BRI    /* å²è¾¼ã¿ãã³ãã©çªå·(BRI) */
+#define INTNO_SCIF_ERI_2        INTNO_SCIF1_ERI    /* å²è¾¼ã¿ãã³ãã©çªå·(ERI) */
+#define INTNO_SCIF_RXI_2        INTNO_SCIF1_RXI    /* å²è¾¼ã¿ãã³ãã©çªå·(RXI) */
+#define INTNO_SCIF_TXI_2        INTNO_SCIF1_TXI    /* å²è¾¼ã¿ãã³ãã©çªå·(TXI) */
+#ifndef INTPRI_SIO_2
+#define INTPRI_SIO_2            (-4)      /* å²è¾¼ã¿åªå
+åº¦ */
+#endif  /* INTPRI_SIO_2 */
+#define INTATR_SIO_2            0U        /* å²è¾¼ã¿å±æ§ */
+
+#define INTNO_SCIF_BRI_3        INTNO_SCIF2_BRI    /* å²è¾¼ã¿ãã³ãã©çªå·(BRI) */
+#define INTNO_SCIF_ERI_3        INTNO_SCIF2_ERI    /* å²è¾¼ã¿ãã³ãã©çªå·(ERI) */
+#define INTNO_SCIF_RXI_3        INTNO_SCIF2_RXI    /* å²è¾¼ã¿ãã³ãã©çªå·(RXI) */
+#define INTNO_SCIF_TXI_3        INTNO_SCIF2_TXI    /* å²è¾¼ã¿ãã³ãã©çªå·(TXI) */
+#ifndef INTPRI_SIO_3
+#define INTPRI_SIO_3            (-4)      /* å²è¾¼ã¿åªå
+åº¦ */
+#endif  /* INTPRI_SIO_3 */
+#define INTATR_SIO_3            0U        /* å²è¾¼ã¿å±æ§ */
+
+#define INTNO_SCIF_BRI_4        INTNO_SCIF3_BRI    /* å²è¾¼ã¿ãã³ãã©çªå·(BRI) */
+#define INTNO_SCIF_ERI_4        INTNO_SCIF3_ERI    /* å²è¾¼ã¿ãã³ãã©çªå·(ERI) */
+#define INTNO_SCIF_RXI_4        INTNO_SCIF3_RXI    /* å²è¾¼ã¿ãã³ãã©çªå·(RXI) */
+#define INTNO_SCIF_TXI_4        INTNO_SCIF3_TXI    /* å²è¾¼ã¿ãã³ãã©çªå·(TXI) */
+#ifndef INTPRI_SIO_4
+#define INTPRI_SIO_4            (-4)      /* å²è¾¼ã¿åªå
+åº¦ */
+#endif  /* INTPRI_SIO_4 */
+#define INTATR_SIO_4            0U        /* å²è¾¼ã¿å±æ§ */
+
+#define INTNO_SCIF_BRI_5        INTNO_SCIF4_BRI    /* å²è¾¼ã¿ãã³ãã©çªå·(BRI) */
+#define INTNO_SCIF_ERI_5        INTNO_SCIF4_ERI    /* å²è¾¼ã¿ãã³ãã©çªå·(ERI) */
+#define INTNO_SCIF_RXI_5        INTNO_SCIF4_RXI    /* å²è¾¼ã¿ãã³ãã©çªå·(RXI) */
+#define INTNO_SCIF_TXI_5        INTNO_SCIF4_TXI    /* å²è¾¼ã¿ãã³ãã©çªå·(TXI) */
+#ifndef INTPRI_SIO_5
+#define INTPRI_SIO_5            (-4)      /* å²è¾¼ã¿åªå
+åº¦ */
+#endif  /* INTPRI_SIO_5 */
+#define INTATR_SIO_5            0U        /* å²è¾¼ã¿å±æ§ */
+
+#define INTNO_SCIF_BRI_6        INTNO_SCIF5_BRI    /* å²è¾¼ã¿ãã³ãã©çªå·(BRI) */
+#define INTNO_SCIF_ERI_6        INTNO_SCIF5_ERI    /* å²è¾¼ã¿ãã³ãã©çªå·(ERI) */
+#define INTNO_SCIF_RXI_6        INTNO_SCIF5_RXI    /* å²è¾¼ã¿ãã³ãã©çªå·(RXI) */
+#define INTNO_SCIF_TXI_6        INTNO_SCIF5_TXI    /* å²è¾¼ã¿ãã³ãã©çªå·(TXI) */
+#ifndef INTPRI_SIO_6
+#define INTPRI_SIO_6            (-4)      /* å²è¾¼ã¿åªå
+åº¦ */
+#endif  /* INTPRI_SIO_6 */
+#define INTATR_SIO_6            0U        /* å²è¾¼ã¿å±æ§ */
+
+#define INTNO_SCIF_BRI_7        INTNO_SCIF6_BRI    /* å²è¾¼ã¿ãã³ãã©çªå·(BRI) */
+#define INTNO_SCIF_ERI_7        INTNO_SCIF6_ERI    /* å²è¾¼ã¿ãã³ãã©çªå·(ERI) */
+#define INTNO_SCIF_RXI_7        INTNO_SCIF6_RXI    /* å²è¾¼ã¿ãã³ãã©çªå·(RXI) */
+#define INTNO_SCIF_TXI_7        INTNO_SCIF6_TXI    /* å²è¾¼ã¿ãã³ãã©çªå·(TXI) */
+#ifndef INTPRI_SIO_7
+#define INTPRI_SIO_7            (-4)      /* å²è¾¼ã¿åªå
+åº¦ */
+#endif  /* INTPRI_SIO_7 */
+#define INTATR_SIO_7            0U        /* å²è¾¼ã¿å±æ§ */
+
+#define INTNO_SCIF_BRI_8        INTNO_SCIF7_BRI    /* å²è¾¼ã¿ãã³ãã©çªå·(BRI) */
+#define INTNO_SCIF_ERI_8        INTNO_SCIF7_ERI    /* å²è¾¼ã¿ãã³ãã©çªå·(ERI) */
+#define INTNO_SCIF_RXI_8        INTNO_SCIF7_RXI    /* å²è¾¼ã¿ãã³ãã©çªå·(RXI) */
+#define INTNO_SCIF_TXI_8        INTNO_SCIF7_TXI    /* å²è¾¼ã¿ãã³ãã©çªå·(TXI) */
+#ifndef INTPRI_SIO_8
+#define INTPRI_SIO_8            (-4)      /* å²è¾¼ã¿åªå
+åº¦ */
+#endif  /* INTPRI_SIO_8 */
+#define INTATR_SIO_8            0U        /* å²è¾¼ã¿å±æ§ */
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ *  SIOãã©ã¤ãã®åæå
+ */
+extern void sio_initialize(intptr_t exinf);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã®ãªã¼ãã³
+ */
+extern SIOPCB *sio_opn_por(ID siopid, intptr_t exinf);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã®ã¯ã­ã¼ãº
+ */
+extern void sio_cls_por(SIOPCB *p_siopcb);
+
+/*
+ *  SIOã®å²è¾¼ã¿ãã³ãã©
+ */
+extern void sio_isr_rxi(intptr_t exinf);
+extern void sio_isr_txi(intptr_t exinf);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã¸ã®æå­éä¿¡
+ */
+extern bool_t sio_snd_chr(SIOPCB *siopcb, char c);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®æå­åä¿¡
+ */
+extern int_t sio_rcv_chr(SIOPCB *siopcb);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®è¨±å¯
+ */
+extern void sio_ena_cbr(SIOPCB *siopcb, uint_t cbrtn);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®ç¦æ­¢
+ */
+extern void sio_dis_cbr(SIOPCB *siopcb, uint_t cbrtn);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®éä¿¡å¯è½ã³ã¼ã«ããã¯
+ */
+extern void sio_irdy_snd(intptr_t exinf);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®åä¿¡éç¥ã³ã¼ã«ããã¯
+ */
+extern void sio_irdy_rcv(intptr_t exinf);
+
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_CHIP_SERIAL_H */
Index: /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_stddef.h
===================================================================
--- /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_stddef.h	(revision 307)
+++ /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_stddef.h	(revision 307)
@@ -0,0 +1,86 @@
+/*
+ *  TOPPERS Software
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *
+ *  Copyright (C) 2007 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2011-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  $Id: chip_stddef.h 720 2016-04-01 22:16:17Z ertl-hiro $
+ */
+
+/*
+ *		t_stddef.hã®ãããä¾å­é¨ï¼RZ/A1ç¨ï¼
+ *
+ *  ãã®ããããã¡ã¤ã«ã¯ï¼target_stddef.hï¼ã¾ãã¯ï¼ããããã¤ã³ã¯ã«ã¼ã
+ *  ããããã¡ã¤ã«ï¼ã®ã¿ããã¤ã³ã¯ã«ã¼ããããï¼ä»ã®ãã¡ã¤ã«ããç´æ¥ã¤
+ *  ã³ã¯ã«ã¼ããã¦ã¯ãªããªãï¼
+ */
+
+#ifndef TOPPERS_CHIP_STDDEF_H
+#define TOPPERS_CHIP_STDDEF_H
+
+/*
+ *  ã¿ã¼ã²ãããè­å¥ããããã®ãã¯ã­ã®å®ç¾©
+ */
+#define TOPPERS_RZA1					/* ãããç¥ç§° */
+
+/*
+ *  ããããéå®ãããã¯ã­ãå®ç¾©ããã¦ãããã®ãã§ãã¯
+ */
+#if !defined(TOPPERS_RZA1H) && !defined(TOPPERS_RZA1L)
+#error Either TOPPERS_RZA1H or TOPPERS_RZA1L must be defined.
+#endif
+
+/*
+ *  ã³ã¢ã§å
+±éãªå®ç¾©
+ */
+#include "core_stddef.h"
+
+#endif /* TOPPERS_CHIP_STDDEF_H */
Index: /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_sym.def
===================================================================
--- /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_sym.def	(revision 307)
+++ /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_sym.def	(revision 307)
@@ -0,0 +1,7 @@
+TARGET_RZA1H,true,bool,defined(TARGET_RZA1H)
+TARGET_RZA1L,true,bool,defined(TARGET_RZA1L)
+TA_NEGEDGE
+TA_POSEDGE
+TA_BOTHEDGE
+INTNO_IRQ0
+INTNO_IRQ7
Index: /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_timer.c
===================================================================
--- /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_timer.c	(revision 307)
+++ /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_timer.c	(revision 307)
@@ -0,0 +1,282 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  $Id: chip_timer.c 731 2016-04-03 03:07:35Z ertl-hiro $
+ */
+
+/*
+ *		ã¿ã¤ããã©ã¤ãï¼RZ/A1 OSã¿ã¤ãç¨ï¼
+ *
+ *  RZ/A1ã¯2ãã£ã³ãã«ã®OSã¿ã¤ããæã¤ãï¼ãã®å
+ã®1ã¤ãç¨ãã¦é«åè§£è½ã¿
+ *  ã¤ããï¼ãã1ã¤ãç¨ãã¦ãªã¼ãã©ã³ã¿ã¤ããå®ç¾ããï¼
+ */
+
+#include "kernel_impl.h"
+#include "time_event.h"
+#ifdef TOPPERS_SUPPORT_OVRHDR
+#include "overrun.h"
+#endif /* TOPPERS_SUPPORT_OVRHDR */
+#include "target_timer.h"
+#include <sil.h>
+#include "rza1.h"
+
+/*
+ *  ã¿ã¤ãå²è¾¼ã¿è¦æ±ã®ã¯ãªã¢
+ */
+Inline void
+target_hrt_int_clear()
+{
+	gicd_clear_pending(INTNO_OSTM0);
+}
+
+/*
+ *  ã¿ã¤ãã®èµ·åå¦ç
+ */
+void
+target_hrt_initialize(intptr_t exinf)
+{
+	/*
+	 *  OSã¿ã¤ããããªã¼ã©ã³ãã³ã°ã³ã³ãã¢ã¢ã¼ãã«è¨­å®ããï¼
+	 */
+	sil_wrb_mem(OSTM_CTL(OSTM0_BASE), OSTM_CTL_FRCMP);
+
+	/*
+	 *  OSã¿ã¤ãã®è¨­å®å¤ãæå¤§å¤ã«ãã¦ããï¼
+	 */
+	sil_wrw_mem(OSTM_CMP(OSTM0_BASE), 0xffffffff);
+
+	/*
+	 *  OSã¿ã¤ããåä½éå§ããï¼
+	 */
+	sil_wrb_mem(OSTM_TS(OSTM0_BASE), OSTM_TS_START);
+
+	/*
+	 *  ã¿ã¤ãå²è¾¼ã¿è¦æ±ãã¯ãªã¢ããï¼
+	 */
+	target_hrt_int_clear();
+}
+
+/*
+ *  ã¿ã¤ãã®åæ­¢å¦ç
+ */
+void
+target_hrt_terminate(intptr_t exinf)
+{
+	/*
+	 *  OSã¿ã¤ããåæ­¢ããï¼
+	 */
+	sil_wrb_mem(OSTM_TT(OSTM0_BASE), OSTM_TT_STOP);
+
+	/*
+	 *  ã¿ã¤ãå²è¾¼ã¿è¦æ±ãã¯ãªã¢ããï¼
+	 */
+	target_hrt_int_clear();
+}
+
+/*
+ *  é«åè§£è½ã¿ã¤ãã¸ã®å²è¾¼ã¿ã¿ã¤ãã³ã°ã®è¨­å®
+ */
+void
+target_hrt_set_event(HRTCNT hrtcnt)
+{
+	uint32_t	cnt = hrtcnt * 33 + hrtcnt / 3 + 1;
+	uint32_t	current;
+
+	/*
+	 *  ç¾å¨ã®ã«ã¦ã³ãå¤ãèª­ã¿ï¼hrtcntå¾ã«å²è¾¼ã¿ãçºçããããã«è¨­å®ããï¼
+	 */
+	current = sil_rew_mem(OSTM_CNT(OSTM0_BASE));
+	sil_wrw_mem(OSTM_CMP(OSTM0_BASE), current + cnt);
+
+	/*
+	 *  ä¸ã§ç¾å¨ã®ã«ã¦ã³ãå¤ãèª­ãã§ä»¥éã«ï¼cntä»¥ä¸ã«ã¦ã³ãã¢ãããã¦ã
+	 *  ãå ´åã«ã¯ï¼å²è¾¼ã¿ãçºçãããï¼
+	 */
+	if (sil_rew_mem(OSTM_CNT(OSTM0_BASE)) - current >= cnt) {
+		gicd_set_pending(INTNO_OSTM0);
+	}
+}
+
+/*
+ *  é«åè§£è½ã¿ã¤ãå²è¾¼ã¿ã®è¦æ±
+ */
+void
+target_hrt_raise_event(void)
+{
+	gicd_set_pending(INTNO_OSTM0);
+}
+
+/*
+ *  ã¿ã¤ãå²è¾¼ã¿ãã³ãã©
+ */
+void
+target_hrt_handler(void)
+{
+	/*
+	 *  ã¿ã¤ãå²è¾¼ã¿è¦æ±ãã¯ãªã¢ããï¼
+	 */
+	target_hrt_int_clear();
+
+	/*
+	 *  é«åè§£è½ã¿ã¤ãå²è¾¼ã¿ãå¦çããï¼
+	 */
+	signal_time();
+}
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ããã©ã¤ã
+ */
+#ifdef TOPPERS_SUPPORT_OVRHDR
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ãå²è¾¼ã¿è¦æ±ã®ã¯ãªã¢
+ */
+Inline void
+target_ovrtimer_int_clear()
+{
+	gicd_clear_pending(INTNO_OSTM1);
+}
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ãã®åæåå¦ç
+ */
+void
+target_ovrtimer_initialize(intptr_t exinf)
+{
+	/*
+	 *  OSã¿ã¤ããã¤ã³ã¿ã¼ãã«ã¿ã¤ãã¢ã¼ãã«è¨­å®ããï¼
+	 */
+	sil_wrb_mem(OSTM_CTL(OSTM1_BASE), OSTM_CTL_INTERVAL);
+
+	/*
+	 *  ãªã¼ãã©ã³ã¿ã¤ãå²è¾¼ã¿è¦æ±ãã¯ãªã¢ããï¼
+	 */
+	target_ovrtimer_int_clear();
+}
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ãã®åæ­¢å¦ç
+ */
+void
+target_ovrtimer_terminate(intptr_t exinf)
+{
+	/*
+	 *  OSã¿ã¤ããåæ­¢ããï¼
+	 */
+	sil_wrb_mem(OSTM_TT(OSTM1_BASE), OSTM_TT_STOP);
+
+	/*
+	 *  ãªã¼ãã©ã³ã¿ã¤ãå²è¾¼ã¿è¦æ±ãã¯ãªã¢ããï¼
+	 */
+	target_ovrtimer_int_clear();
+}
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ãã®åæ­¢
+ */
+PRCTIM
+target_ovrtimer_stop(void)
+{
+	uint32_t	cnt;
+
+	/*
+	 *  OSã¿ã¤ããåæ­¢ããï¼
+	 */
+	sil_wrb_mem(OSTM_TT(OSTM1_BASE), OSTM_TT_STOP);
+
+	if (gicd_probe_pending(INTNO_OSTM1)) {
+		/*
+		 *  å²è¾¼ã¿è¦æ±ãçºçãã¦ããå ´å
+		 */
+		target_ovrtimer_int_clear();
+		return(0U);
+	}
+	else {
+		cnt = sil_rew_mem(OSTM_CNT(OSTM1_BASE));
+		return((PRCTIM)((cnt + 34) / 5 * 3 / 20));
+	}
+}
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ãã®ç¾å¨å¤ã®èª­åºã
+ */
+PRCTIM
+target_ovrtimer_get_current(void)
+{
+	uint32_t	cnt;
+
+	if (gicd_probe_pending(INTNO_OSTM1)) {
+		/*
+		 *  å²è¾¼ã¿è¦æ±ãçºçãã¦ããå ´å
+		 */
+		return(0U);
+	}
+	else {
+		cnt = sil_rew_mem(OSTM_CNT(OSTM1_BASE));
+		return((PRCTIM)((cnt + 34) / 5 * 3 / 20));
+	}
+}
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ãå²è¾¼ã¿ãã³ãã©
+ *
+ *  ãã®ã«ã¼ãã³ã«æ¥ãã¾ã§ã«ï¼target_ovrtimer_stopãå¼ã°ãã¦ããããï¼
+ *  OSã¿ã¤ããåæ­¢ããå¿
+è¦ã¯ãªãï¼
+ */
+void
+target_ovrtimer_handler(void)
+{
+	call_ovrhdr();					/* ãªã¼ãã©ã³ãã³ãã©ã®èµ·åå¦ç */
+}
+
+#endif /* TOPPERS_SUPPORT_OVRHDR */
Index: /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_timer.cfg
===================================================================
--- /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_timer.cfg	(revision 307)
+++ /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_timer.cfg	(revision 307)
@@ -0,0 +1,23 @@
+/*
+ *		ã¿ã¤ããã©ã¤ãã®ã³ã³ãã£ã®ã¥ã¬ã¼ã·ã§ã³ãã¡ã¤ã«
+ *
+ *  $Id: chip_timer.cfg 727 2016-04-03 00:47:42Z ertl-hiro $
+ */
+
+/*
+ *  é«åè§£è½ã¿ã¤ããã©ã¤ã
+ */
+ATT_INI({ TA_NULL, 0, _kernel_target_hrt_initialize });
+ATT_TER({ TA_NULL, 0, _kernel_target_hrt_terminate });
+CFG_INT(INTNO_TIMER, { TA_ENAINT|INTATR_TIMER, INTPRI_TIMER });
+DEF_INH(INHNO_TIMER, { TA_NULL, _kernel_target_hrt_handler });
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ããã©ã¤ã
+ */
+#ifdef TOPPERS_SUPPORT_OVRHDR
+ATT_INI({ TA_NULL, 0, _kernel_target_ovrtimer_initialize });
+ATT_TER({ TA_NULL, 0, _kernel_target_ovrtimer_terminate });
+CFG_INT(INTNO_OVRTIMER, { TA_ENAINT|INTATR_OVRTIMER, INTPRI_OVRTIMER });
+DEF_INH(INHNO_OVRTIMER, { TA_NULL, _kernel_target_ovrtimer_handler });
+#endif /* TOPPERS_SUPPORT_OVRHDR */
Index: /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_timer.h
===================================================================
--- /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_timer.h	(revision 307)
+++ /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_timer.h	(revision 307)
@@ -0,0 +1,219 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
+ *                              Toyohashi Univ. of Technology, JAPAN
+ *  Copyright (C) 2005-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  $Id: chip_timer.h 742 2016-04-07 13:11:22Z ertl-hiro $
+ */
+
+/*
+ *		ã¿ã¤ããã©ã¤ãï¼RZ/A1 OSã¿ã¤ãç¨ï¼
+ *
+ *  RZ/A1ã¯2ãã£ã³ãã«ã®OSã¿ã¤ããæã¤ãï¼ãã®å
+ã®1ã¤ãç¨ãã¦é«åè§£è½ã¿
+ *  ã¤ããï¼ãã1ã¤ãç¨ãã¦ãªã¼ãã©ã³ã¿ã¤ããå®ç¾ããï¼
+ */
+
+#ifndef TOPPERS_CHIP_TIMER_H
+#define TOPPERS_CHIP_TIMER_H
+
+#include <sil.h>
+#include "rza1.h"
+
+/*
+ *  ã¿ã¤ãå²è¾¼ã¿ãã³ãã©ç»é²ã®ããã®å®æ°
+ */
+#define INHNO_TIMER		INTNO_OSTM0			/* å²è¾¼ã¿ãã³ãã©çªå· */
+#define INTNO_TIMER		INTNO_OSTM0			/* å²è¾¼ã¿çªå· */
+#define INTPRI_TIMER	(TMAX_INTPRI - 1)	/* å²è¾¼ã¿åªå
+åº¦ */
+#define INTATR_TIMER	TA_EDGE				/* å²è¾¼ã¿å±æ§ */
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ãå²è¾¼ã¿ãã³ãã©ç»é²ã®ããã®å®æ°
+ */
+#ifdef TOPPERS_SUPPORT_OVRHDR
+#define INHNO_OVRTIMER		INTNO_OSTM1			/* å²è¾¼ã¿ãã³ãã©çªå· */
+#define INTNO_OVRTIMER		INTNO_OSTM1			/* å²è¾¼ã¿çªå· */
+#define INTPRI_OVRTIMER		TMAX_INTPRI			/* å²è¾¼ã¿åªå
+åº¦ */
+#define INTATR_OVRTIMER		TA_EDGE				/* å²è¾¼ã¿å±æ§ */
+#endif /* TOPPERS_SUPPORT_OVRHDR */
+
+/*
+ *  OSã¿ã¤ãã®å¨æ³¢æ°ã®æ³å®å¤ã®ãã§ãã¯
+ *
+ *  ç¾å¨ã®å®è£
+ã¯ï¼ã¯ã­ãã¯ã33.33â¦MHzã®å ´åã®ã¿ã«å¯¾å¿ãã¦ããï¼
+ */
+#if OSTM_CLK != 33333333UL
+#error Unsupported OS time clock.
+#endif /* OSTM_CLK != 33333333UL */
+
+/*
+ *  OSã¿ã¤ãã¬ã¸ã¹ã¿ã®çªå°ã®å®ç¾©
+ */
+#define OSTM_CMP(base)		((uint32_t *)(base + 0x00U))
+#define OSTM_CNT(base)		((uint32_t *)(base + 0x04U))
+#define OSTM_TE(base)		((uint8_t *)(base + 0x10U))
+#define OSTM_TS(base)		((uint8_t *)(base + 0x14U))
+#define OSTM_TT(base)		((uint8_t *)(base + 0x18U))
+#define OSTM_CTL(base)		((uint8_t *)(base + 0x20U))
+
+/*
+ *  OSã¿ã¤ã ã«ã¦ã³ãéå§ããªã¬ã¬ã¸ã¹ã¿ã®è¨­å®å¤ã®å®ç¾©
+ */
+#define OSTM_TS_START		0x01U
+
+/*
+ *  OSã¿ã¤ã ã«ã¦ã³ãåæ­¢ããªã¬ã¬ã¸ã¹ã¿ã®è¨­å®å¤ã®å®ç¾©
+ */
+#define OSTM_TT_STOP		0x01U
+
+/*
+ *  OSã¿ã¤ã å¶å¾¡ã¬ã¸ã¹ã¿ã®è¨­å®å¤ã®å®ç¾©
+ */
+#define OSTM_CTL_INTERVAL	0x00U		/* ã¤ã³ã¿ã¼ãã«ã¿ã¤ãã¢ã¼ã */
+#define OSTM_CTL_FRCMP		0x02U		/* ããªã¼ã©ã³ãã³ã°ã³ã³ãã¢ã¢ã¼ã */
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ *  é«åè§£è½ã¿ã¤ãã®èµ·åå¦ç
+ */
+extern void	target_hrt_initialize(intptr_t exinf);
+
+/*
+ *  é«åè§£è½ã¿ã¤ãã®åæ­¢å¦ç
+ */
+extern void	target_hrt_terminate(intptr_t exinf);
+
+/*
+ *  é«åè§£è½ã¿ã¤ãã®ç¾å¨ã®ã«ã¦ã³ãå¤ã®èª­åºã
+ */
+Inline HRTCNT
+target_hrt_get_current(void)
+{
+	uint32_t	cnt, cnt1;
+
+	cnt = sil_rew_mem(OSTM_CNT(OSTM0_BASE));
+
+	/* Î¼ç§åä½ã«å¤æï¼ã¯ã­ãã¯ã33.33â¦MHzã§ããåæï¼*/
+	cnt1 = cnt / 1000000000;
+	return((HRTCNT)((cnt - cnt1 * 999999999) * 3 / 100 + cnt1 * 30000000));
+}
+
+/*
+ *  é«åè§£è½ã¿ã¤ãã¸ã®å²è¾¼ã¿ã¿ã¤ãã³ã°ã®è¨­å®
+ *
+ *  é«åè§£è½ã¿ã¤ããï¼hrtcntã§æå®ããå¤ã«ã¦ã³ãã¢ãããããå²è¾¼ã¿ãçº
+ *  çãããããã«è¨­å®ããï¼
+ */
+extern void target_hrt_set_event(HRTCNT hrtcnt);
+
+/*
+ *  é«åè§£è½ã¿ã¤ãå²è¾¼ã¿ã®è¦æ±
+ */
+extern  void target_hrt_raise_event(void);
+
+/*
+ *  å²è¾¼ã¿ã¿ã¤ãã³ã°ã«æå®ããæå¤§å¤
+ */
+#define HRTCNT_BOUND	100000002U
+
+/*
+ *  é«åè§£è½ã¿ã¤ãå²è¾¼ã¿ãã³ãã©
+ */
+extern void	target_hrt_handler(void);
+
+#ifdef TOPPERS_SUPPORT_OVRHDR
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ãã®åæåå¦ç
+ */
+extern void target_ovrtimer_initialize(intptr_t exinf);
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ãã®åæ­¢å¦ç
+ */
+extern void target_ovrtimer_terminate(intptr_t exinf);
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ãã®åä½éå§
+ */
+Inline void
+target_ovrtimer_start(PRCTIM ovrtim)
+{
+	uint32_t	cnt = ovrtim * 33 + ovrtim / 3 + 1;
+
+	sil_wrw_mem(OSTM_CMP(OSTM1_BASE), cnt);
+	sil_wrb_mem(OSTM_TS(OSTM1_BASE), OSTM_TS_START);
+}
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ãã®åæ­¢
+ */
+extern PRCTIM target_ovrtimer_stop(void);
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ãã®ç¾å¨å¤ã®èª­åºã
+ */
+extern PRCTIM target_ovrtimer_get_current(void);
+
+/*
+ *  ãªã¼ãã©ã³ã¿ã¤ãå²è¾¼ã¿ãã³ãã©
+ */
+extern void	target_ovrtimer_handler(void);
+
+#endif /* TOPPERS_SUPPORT_OVRHDR */
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_CHIP_TIMER_H */
Index: /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_unrename.h
===================================================================
--- /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_unrename.h	(revision 307)
+++ /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/chip_unrename.h	(revision 307)
@@ -0,0 +1,30 @@
+/* This file is generated from chip_rename.def by genrename. */
+
+/* This file is included only when chip_rename.h has been included. */
+#ifdef TOPPERS_CHIP_RENAME_H
+#undef TOPPERS_CHIP_RENAME_H
+
+/*
+ *  chip_kernel_impl.c
+ */
+#undef chip_initialize
+#undef chip_terminate
+
+/*
+ *  chip_timer.c
+ */
+#undef target_hrt_initialize
+#undef target_hrt_terminate
+#undef target_hrt_set_event
+#undef target_hrt_raise_event
+#undef target_hrt_handler
+#undef target_ovrtimer_initialize
+#undef target_ovrtimer_terminate
+#undef target_ovrtimer_stop
+#undef target_ovrtimer_get_current
+#undef target_ovrtimer_handler
+
+
+#include "core_unrename.h"
+
+#endif /* TOPPERS_CHIP_RENAME_H */
Index: /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/rza1.h
===================================================================
--- /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/rza1.h	(revision 307)
+++ /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/rza1.h	(revision 307)
@@ -0,0 +1,317 @@
+/*
+ *  TOPPERS Software
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *
+ *  Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  $Id: rza1.h 720 2016-04-01 22:16:17Z ertl-hiro $
+ */
+
+/*
+ *		RZ/A1ã®ãã¼ãã¦ã§ã¢è³æºã®å®ç¾©
+ */
+
+#ifndef TOPPERS_RZA1_H
+#define TOPPERS_RZA1_H
+
+#include <sil.h>
+
+/*
+ *  åã­ã£ã¹ããè¡ããã¯ã­ã®å®ç¾©
+ */
+#ifndef CAST
+#define CAST(type, val)		((type)(val))
+#endif /* CAST */
+
+/*
+ *  ã¡ã¢ãªãããã®å®ç¾©ï¼MMUã«è¨­å®ããããã«å¿
+è¦ï¼
+ */
+#define SPI_ADDR		0x18000000		/* ã·ãªã¢ã«ãã©ãã·ã¥ã¡ã¢ãª */
+#define SPI_SIZE		0x08000000		/* 128MB */
+
+#define SRAM_ADDR		0x20000000		/* å
+èµRAM */
+#ifdef TOPPERS_RZA1H
+#define SRAM_SIZE		0x00a00000		/* 10MB */
+#else /* TOPPERS_RZA1H */
+#define SRAM_SIZE		0x00300000		/* 3MB */
+#endif /* TOPPERS_RZA1H */
+
+#define IO1_ADDR		0x3fe00000		/* I/Oé åï¼äºç´é åãå«ãï¼*/
+#define IO1_SIZE		0x00200000		/* 2MB */
+#define IO2_ADDR		0xe8000000		/* I/Oé åï¼äºç´é åãå«ãï¼*/
+#define IO2_SIZE		0x18000000		/* 384MB */
+
+/*
+ *  åã¯ã­ãã¯å¨æ³¢æ°ã®å®ç¾©
+ */
+#define OSTM_CLK		RZA1_CLK_P0
+#define SCIF_CLK		RZA1_CLK_P1
+
+/*
+ *  MPCore Private Memory Regionã®å
+é ­çªå°
+ */
+#define MPCORE_PMR_BASE		0xf0000000
+
+/*
+ *  GICä¾å­é¨ãä½¿ç¨ããããã®å®ç¾©
+ */
+#ifndef GIC_TNUM_INTNO
+#ifdef TOPPERS_RZA1H
+#define GIC_TNUM_INTNO		UINT_C(587)
+#else /* TOPPERS_RZA1H */
+#define GIC_TNUM_INTNO		UINT_C(538)
+#endif /* TOPPERS_RZA1H */
+#endif /* GIC_TNUM_INT */
+
+/*
+ *  å²è¾¼ã¿ã³ã³ãã­ã¼ã©ã®ãã¼ã¹ã¢ãã¬ã¹ã¨ã¬ã¸ã¹ã¿ï¼RZ/A1åºæã®ãã®ï¼
+ */
+#define GICC_BASE			0xe8202000
+#define GICD_BASE			0xe8201000
+
+#define RZA1_ICR0			CAST(uint16_t *, 0xfcfef800)
+#define RZA1_ICR1			CAST(uint16_t *, 0xfcfef802)
+#define RZA1_IRQRR			CAST(uint16_t *, 0xfcfef804)
+
+/*
+ *  OSã¿ã¤ãã®ãã¼ã¹ã¢ãã¬ã¹
+ */
+#define OSTM0_BASE			0xfcfec000
+#define OSTM1_BASE			0xfcfec400
+
+/*
+ *  L2ã­ã£ãã·ã¥ã³ã³ãã­ã¼ã©ï¼PL310ï¼ã®ãã¼ã¹ã¢ãã¬ã¹
+ */
+#define PL310_BASE			0x3ffff000
+
+/*
+ *  ã¯ã­ãã¯ãã«ã¹ã¸ã§ãã¬ã¼ã¿ã®ãã¼ã¹ã¢ãã¬ã¹ã¨ã¬ã¸ã¹ã¿
+ */
+#define RZA1_CPG_BASE		0xfcfe0000
+#define RZA1_FRQCR			CAST(uint16_t *, RZA1_CPG_BASE + 0x010)
+#define RZA1_FRQCR2			CAST(uint16_t *, RZA1_CPG_BASE + 0x014)
+
+/*
+ *  ãã¹ã¹ãã¼ãã³ã³ãã­ã¼ã©ã®ãã¼ã¹ã¢ãã¬ã¹ã¨ã¬ã¸ã¹ã¿
+ */
+#define RZA1_BSC_BASE		0x3FFFC000
+#define RZA1_CMNCR			CAST(uint32_t *, RZA1_BSC_BASE)
+#define RZA1_CS0BCR			CAST(uint32_t *, RZA1_BSC_BASE + 0x0004)
+#define RZA1_CS1BCR			CAST(uint32_t *, RZA1_BSC_BASE + 0x0008)
+#define RZA1_CS2BCR			CAST(uint32_t *, RZA1_BSC_BASE + 0x000C)
+#define RZA1_CS3BCR			CAST(uint32_t *, RZA1_BSC_BASE + 0x0010)
+#define RZA1_CS4BCR			CAST(uint32_t *, RZA1_BSC_BASE + 0x0014)
+#define RZA1_CS5BCR			CAST(uint32_t *, RZA1_BSC_BASE + 0x0018)
+#define RZA1_CS0WCR			CAST(uint32_t *, RZA1_BSC_BASE + 0x0028)
+#define RZA1_CS1WCR			CAST(uint32_t *, RZA1_BSC_BASE + 0x002C)
+#define RZA1_CS2WCR			CAST(uint32_t *, RZA1_BSC_BASE + 0x0030)
+#define RZA1_CS3WCR			CAST(uint32_t *, RZA1_BSC_BASE + 0x0034)
+#define RZA1_CS4WCR			CAST(uint32_t *, RZA1_BSC_BASE + 0x0038)
+#define RZA1_CS5WCR			CAST(uint32_t *, RZA1_BSC_BASE + 0x003C)
+#define RZA1_SDCR			CAST(uint32_t *, RZA1_BSC_BASE + 0x004C)
+#define RZA1_RTCSR			CAST(uint32_t *, RZA1_BSC_BASE + 0x0050)
+#define RZA1_RTCNT			CAST(uint32_t *, RZA1_BSC_BASE + 0x0054)
+#define RZA1_RTCOR			CAST(uint32_t *, RZA1_BSC_BASE + 0x0058)
+
+/*
+ *  ã·ãªã¢ã«ã³ãã¥ãã±ã¼ã·ã§ã³ã¤ã³ã¿ãã§ã¼ã¹ã®ãã¼ã¹ã¢ãã¬ã¹
+ */
+#define SCIF0_BASE			0xe8007000
+#define SCIF1_BASE			0xe8007800
+#define SCIF2_BASE			0xe8008000
+#define SCIF3_BASE			0xe8008800
+#define SCIF4_BASE			0xe8009000
+#ifdef TOPPERS_RZA1H
+#define SCIF5_BASE			0xe8009800
+#define SCIF6_BASE			0xe800a000
+#define SCIF7_BASE			0xe800a800
+#endif /* TOPPERS_RZA1H */
+
+/*
+ *  ãµãã¼ãããã·ãªã¢ã«ãã¼ãã®åæ°
+ */
+#ifdef TOPPERS_RZA1H
+#define TNUM_SIOP  8
+#elif defined(TOPPERS_RZ_A1L)
+#define TNUM_SIOP  5
+#endif /* TOPPERS_RZA1H */
+
+/*
+ *  ä½æ¶è²»é»åã¢ã¼ãé¢é£ã®ãã¼ã¹ã¢ãã¬ã¹ã¨ã¬ã¸ã¹ã¿
+ */
+#define RZA1_LOWPWR_BASE	0xfcfe0000
+#define RZA1_STBCR1			CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x020)
+#define RZA1_STBCR2			CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x024)
+#define RZA1_STBCR3			CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x420)
+#define RZA1_STBCR4			CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x424)
+#define RZA1_STBCR5			CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x428)
+#define RZA1_STBCR6			CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x42C)
+#define RZA1_STBCR7			CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x430)
+#define RZA1_STBCR8			CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x434)
+#define RZA1_STBCR9			CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x438)
+#define RZA1_STBCR10		CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x43C)
+#define RZA1_STBCR11		CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x440)
+#define RZA1_STBCR12		CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x444)
+#define RZA1_STBCR13		CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x470)
+#define RZA1_SYSCR1			CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x400)
+#define RZA1_SYSCR2			CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x404)
+#define RZA1_SYSCR3			CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x408)
+#define RZA1_CPUSTS			CAST(uint8_t *, RZA1_LOWPWR_BASE + 0x018)
+
+/*
+ *  æ±ç¨å
+¥åºåãã¼ãã®ãã¼ã¹ã¢ãã¬ã¹ã¨ã¬ã¸ã¹ã¿
+ */
+#define RZA1_PORT_BASE		0xfcfe3000
+#define RZA1_PORT_P(n)		CAST(uint16_t *, (RZA1_PORT_BASE + 0x0000 + (n)*4))
+#define RZA1_PORT_PSR(n)	CAST(uint32_t *, (RZA1_PORT_BASE + 0x0100 + (n)*4))
+#define RZA1_PORT_PPR(n)	CAST(uint16_t *, (RZA1_PORT_BASE + 0x0200 + (n)*4))
+#define RZA1_PORT_PM(n)		CAST(uint16_t *, (RZA1_PORT_BASE + 0x0300 + (n)*4))
+#define RZA1_PORT_PMC(n)	CAST(uint16_t *, (RZA1_PORT_BASE + 0x0400 + (n)*4))
+#define RZA1_PORT_PFC(n)	CAST(uint16_t *, (RZA1_PORT_BASE + 0x0500 + (n)*4))
+#define RZA1_PORT_PFCE(n)	CAST(uint16_t *, (RZA1_PORT_BASE + 0x0600 + (n)*4))
+#define RZA1_PORT_PFCAE(n)	CAST(uint16_t *, (RZA1_PORT_BASE + 0x0a00 + (n)*4))
+#define RZA1_PORT_PIBC(n)	CAST(uint16_t *, (RZA1_PORT_BASE + 0x4000 + (n)*4))
+#define RZA1_PORT_PBDC(n)	CAST(uint16_t *, (RZA1_PORT_BASE + 0x4100 + (n)*4))
+#define RZA1_PORT_PIPC(n)	CAST(uint16_t *, (RZA1_PORT_BASE + 0x4200 + (n)*4))
+
+/*
+ *	å²è¾¼ã¿çªå·
+ */
+#define INTNO_IRQ0			32		/* IRQ0 */
+#define INTNO_IRQ1			33		/* IRQ1 */
+#define INTNO_IRQ2			34		/* IRQ2 */
+#define INTNO_IRQ3			35		/* IRQ3 */
+#define INTNO_IRQ4			36		/* IRQ4 */
+#define INTNO_IRQ5			37		/* IRQ5 */
+#define INTNO_IRQ6			38		/* IRQ6 */
+#define INTNO_IRQ7			39		/* IRQ7 */
+#define INTNO_OSTM0			134		/* OSã¿ã¤ã0 */
+#define INTNO_OSTM1			135		/* OSã¿ã¤ã1 */
+#define INTNO_SCIF0_BRI		221		/* SCIF0 ãã¬ã¼ã¯å²è¾¼ã¿ */
+#define INTNO_SCIF0_ERI		222		/* SCIF0 ã¨ã©ã¼å²è¾¼ã¿ */
+#define INTNO_SCIF0_RXI		223		/* SCIF0 åä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF0_TXI		224		/* SCIF0 éä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF1_BRI		225		/* SCIF1 ãã¬ã¼ã¯å²è¾¼ã¿ */
+#define INTNO_SCIF1_ERI		226		/* SCIF1 ã¨ã©ã¼å²è¾¼ã¿ */
+#define INTNO_SCIF1_RXI		227		/* SCIF1 åä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF1_TXI		228		/* SCIF1 éä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF2_BRI		229		/* SCIF2 ãã¬ã¼ã¯å²è¾¼ã¿ */
+#define INTNO_SCIF2_ERI		230		/* SCIF2 ã¨ã©ã¼å²è¾¼ã¿ */
+#define INTNO_SCIF2_RXI		231		/* SCIF2 åä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF2_TXI		232		/* SCIF2 éä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF3_BRI		233		/* SCIF3 ãã¬ã¼ã¯å²è¾¼ã¿ */
+#define INTNO_SCIF3_ERI		234		/* SCIF3 ã¨ã©ã¼å²è¾¼ã¿ */
+#define INTNO_SCIF3_RXI		235		/* SCIF3 åä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF3_TXI		236		/* SCIF3 éä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF4_BRI		237		/* SCIF4 ãã¬ã¼ã¯å²è¾¼ã¿ */
+#define INTNO_SCIF4_ERI		238		/* SCIF4 ã¨ã©ã¼å²è¾¼ã¿ */
+#define INTNO_SCIF4_RXI		239		/* SCIF4 åä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF4_TXI		240		/* SCIF4 éä¿¡å²è¾¼ã¿ */
+#ifdef TOPPERS_RZA1H
+#define INTNO_SCIF5_BRI		241		/* SCIF5 ãã¬ã¼ã¯å²è¾¼ã¿ */
+#define INTNO_SCIF5_ERI		242		/* SCIF5 ã¨ã©ã¼å²è¾¼ã¿ */
+#define INTNO_SCIF5_RXI		243		/* SCIF5 åä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF5_TXI		244		/* SCIF5 éä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF6_BRI		245		/* SCIF6 ãã¬ã¼ã¯å²è¾¼ã¿ */
+#define INTNO_SCIF6_ERI		246		/* SCIF6 ã¨ã©ã¼å²è¾¼ã¿ */
+#define INTNO_SCIF6_RXI		247		/* SCIF6 åä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF6_TXI		248		/* SCIF6 éä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF7_BRI		249		/* SCIF7 ãã¬ã¼ã¯å²è¾¼ã¿ */
+#define INTNO_SCIF7_ERI		250		/* SCIF7 ã¨ã©ã¼å²è¾¼ã¿ */
+#define INTNO_SCIF7_RXI		251		/* SCIF7 åä¿¡å²è¾¼ã¿ */
+#define INTNO_SCIF7_TXI		252		/* SCIF7 éä¿¡å²è¾¼ã¿ */
+#endif /* TOPPERS_RZA1H */
+
+#ifndef TOPPERS_MACRO_ONLY
+
+#include "kernel.h"
+
+/*
+ *  IRQå²è¾¼ã¿è¦æ±ã®ã¯ãªã¢
+ */
+Inline void
+rza1_clear_irq(INTNO intno)
+{
+	uint16_t	reg;
+
+	reg = sil_reh_mem(RZA1_IRQRR);
+	reg &= ~(0x01U << (intno - INTNO_IRQ0));
+	sil_wrh_mem(RZA1_IRQRR, reg);
+}
+
+/*
+ *  æ±ç¨å
+¥åºåãã¼ãã®è¨­å®
+ *
+ *  æ±ç¨å
+¥åºåãã¼ãã®å¶å¾¡ã¬ã¸ã¹ã¿ã®ç¹å®ã®ããããï¼ã»ããï¼setã0ã§ãª
+ *  ãæï¼ã¾ãã¯ã¯ãªã¢ï¼setã0ã®æï¼ããï¼
+ */
+Inline void
+rza1_config_port(uint16_t *reg, uint_t bit, uint_t set)
+{
+	uint16_t	val;
+	uint16_t	mask;
+
+	mask = 0x01U << bit;
+	val = sil_reh_mem(reg);
+	if (set == 0) {
+		val &= ~mask;
+	}
+	else {
+		val |= mask;
+	}
+	sil_wrh_mem(reg, val);
+}
+
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_RZA1_H */
Index: /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/scif.c
===================================================================
--- /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/scif.c	(revision 307)
+++ /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/scif.c	(revision 307)
@@ -0,0 +1,628 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2001-2011 by Industrial Technology Institute,
+ *                              Miyagi Prefectural Government, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  @(#) $Id: scif.c 2758 2016-03-10 15:15:26Z ertl-honda $
+ */
+
+/*
+ *   RZ/A1ç¨ ç°¡æSIOãã©ã¤ã
+ */
+#include <sil.h>
+#include "target_syssvc.h"
+#include "rza1.h"
+#include "scif.h"
+
+/*
+ * åã¬ã¸ã¹ã¿ã®ãªãã»ãã
+ */
+#define REG_SCSMR       0x00    /* ã·ãªã¢ã«ã¢ã¼ãã¬ã¸ã¹ã¿, 16bit */
+#define REG_SCBRR       0x04    /* ãããã¬ã¼ãã¬ã¸ã¹ã¿, 8bit */
+#define REG_SCSCR       0x08    /* ã·ãªã¢ã«ã³ã³ãã­ã¼ã«ã¬ã¸ã¹ã¿, 16bit */
+#define REG_SCFTDR      0x0C    /* éä¿¡FIFOãã¼ã¿ã¬ã¸ã¹ã¿, 8bit */
+#define REG_SCFSR       0x10    /* ã·ãªã¢ã«ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿, 16bit */
+#define REG_SCFRDR      0x14    /* åä¿¡FIFOãã¼ã¿ã¬ã¸ã¹ã¿, 8bit */
+#define REG_SCFCR       0x18    /* FIFOã³ã³ãã­ã¼ã«ã¬ã¸ã¹ã¿, 16bit */
+#define REG_SCFDR       0x1C    /* FIFOãã¼ã¿ã«ã¦ã³ãã¬ã¸ã¹ã¿, 16bit */
+#define REG_SCSPTR      0x20    /* ã·ãªã¢ã«ãã¼ãã¬ã¸ã¹ã¿, 16bit */
+#define REG_SCLSR       0x24    /* ã©ã¤ã³ã¹ãã¼ã¿ã¹ã¬ã¸ã¹ã¿, 16bit */
+#define REG_SCEMR       0x28    /* ã·ãªã¢ã«æ¡å¼µã¢ã¼ãã¬ã¸ã¹ã¿, 16bit */
+
+/*
+ * åã¬ã¸ã¹ã¿ã®è¨­å®å¤
+ */
+#define SCSMR_SYNC      0x0080          /* 1:ã¯ã­ãã¯åæå¼ã¢ã¼ã */
+#define SCSMR_7BIT      0x0040          /* 1:ï¼ããããã¼ã¿ */
+#define SCSMR_PARITY    0x0020          /* 1:ããªãã£ä»å  */
+#define SCSMR_ODD       0x0010          /* 1:å¥æ°ããªãã£ */
+#define SCSMR_2STOP     0x0008          /* 1:ï¼ã¹ãããããã */
+#define SCSMR_CKS1      0x0000          /* 00:P1clock / 1 */
+#define SCSMR_CKS4      0x0001          /* 01:P1clock / 4 */
+#define SCSMR_CKS16     0x0002          /* 10:P1clock / 16 */
+#define SCSMR_CKS64     0x0003          /* 11:P1clock / 64 */
+
+#define SCSCR_TIE       0x0080          /* 1:éä¿¡å²ãè¾¼ã¿è¨±å¯ */
+#define SCSCR_RIE       0x0040          /* 1:åä¿¡å²ãè¾¼ã¿,åä¿¡ã¨ã©ã¼å²ãè¾¼ã¿,ãã¬ã¼ã¯å²ãè¾¼ã¿è¨±å¯ */
+#define SCSCR_TE        0x0020          /* 1:éä¿¡è¨±å¯ */
+#define SCSCR_RE        0x0010          /* 1:åä¿¡è¨±å¯ */
+#define SCSCR_REIE      0x0008          /* 1:åä¿¡ã¨ã©ã¼å²ãè¾¼ã¿,ãã¬ã¼ã¯å²ãè¾¼ã¿è¨±å¯ */
+#define SCSCR_INTCLK    0x0000          /* 00:å
+é¨ã¯ã­ãã¯,CKSç«¯å­ã¯ç¡è¦ï¼èª¿æ­©åæå¼ã®å ´åï¼ */
+
+#define SCFSR_PER_MASK  0xF000          /* ããªãã£ã¨ã©ã¼æ°æ½åºãã¹ã¯ */
+#define SCFSR_PER_SHIFT 12              /* ããªãã£ã¨ã©ã¼æ°æ½åºå³ã·ããæ° */
+#define SCFSR_FER_MASK  0x0F00          /* ãã¬ã¼ãã³ã°ã¨ã©ã¼æ°æ½åºãã¹ã¯ */
+#define SCFSR_FER_SHIFT 8               /* ãã¬ã¼ãã³ã°ã¨ã©ã¼æ°æ½åºå³ã·ããæ° */
+#define SCFSR_ER        0x0080          /* 1:åä¿¡ã¨ã©ã¼ */
+#define SCFSR_TEND      0x0040          /* 1:éä¿¡å®äº */
+#define SCFSR_TDFE      0x0020          /* 1:éä¿¡FIFOãã¼ã¿ã¨ã³ããã£ */
+#define SCFSR_BRK       0x0010          /* 1:ãã¬ã¼ã¯æ¤åº */
+#define SCFSR_FER       0x0008          /* 1:ãã¬ã¼ãã³ã°ã¨ã©ã¼æ¤åº */
+#define SCFSR_PER       0x0004          /* 1:ããªãã£ã¨ã©ã¼æ¤åº */
+#define SCFSR_RDF       0x0002          /* 1:åä¿¡FIFOãã¼ã¿ãã« */
+#define SCFSR_DR        0x0001          /* 1:åä¿¡ãã¼ã¿ã¬ãã£ */
+
+#define SCFCR_RSTRG_15  0x0000          /* RTS#åºåã¢ã¯ãã£ãããªã¬:15 */
+#define SCFCR_RSTRG_1   0x0100          /* RTS#åºåã¢ã¯ãã£ãããªã¬:1 */
+#define SCFCR_RSTRG_4   0x0200          /* RTS#åºåã¢ã¯ãã£ãããªã¬:4 */
+#define SCFCR_RSTRG_6   0x0300          /* RTS#åºåã¢ã¯ãã£ãããªã¬:6 */
+#define SCFCR_RSTRG_8   0x0400          /* RTS#åºåã¢ã¯ãã£ãããªã¬:8 */
+#define SCFCR_RSTRG_10  0x0500          /* RTS#åºåã¢ã¯ãã£ãããªã¬:10 */
+#define SCFCR_RSTRG_12  0x0600          /* RTS#åºåã¢ã¯ãã£ãããªã¬:12 */
+#define SCFCR_RSTRG_14  0x0700          /* RTS#åºåã¢ã¯ãã£ãããªã¬:14 */
+#define SCFCR_RTRG_1    0x0000          /* åä¿¡FIFOãã¼ã¿æ°ããªã¬:1ï¼èª¿æ­©åæå¼ã®å ´åï¼ */
+#define SCFCR_RTRG_4    0x0040          /* åä¿¡FIFOãã¼ã¿æ°ããªã¬:4ï¼èª¿æ­©åæå¼ã®å ´åï¼ */
+#define SCFCR_RTRG_8    0x0080          /* åä¿¡FIFOãã¼ã¿æ°ããªã¬:8ï¼èª¿æ­©åæå¼ã®å ´åï¼ */
+#define SCFCR_RTRG_14   0x00C0          /* åä¿¡FIFOãã¼ã¿æ°ããªã¬:14ï¼èª¿æ­©åæå¼ã®å ´åï¼ */
+#define SCFCR_TTRG_8    0x0000          /* éä¿¡FIFOãã¼ã¿æ°ããªã¬:8ï¼èª¿æ­©åæå¼ã®å ´åï¼ */
+#define SCFCR_TTRG_4    0x0010          /* éä¿¡FIFOãã¼ã¿æ°ããªã¬:4ï¼èª¿æ­©åæå¼ã®å ´åï¼ */
+#define SCFCR_TTRG_2    0x0020          /* éä¿¡FIFOãã¼ã¿æ°ããªã¬:2ï¼èª¿æ­©åæå¼ã®å ´åï¼ */
+#define SCFCR_TTRG_0    0x0030          /* éä¿¡FIFOãã¼ã¿æ°ããªã¬:0ï¼èª¿æ­©åæå¼ã®å ´åï¼ */
+#define SCFCR_MCE       0x0008          /* CTS#,RTS#è¨±å¯ */
+#define SCFCR_TFRST     0x0004          /* 1:éä¿¡FIFOãã¼ã¿ã¬ã¸ã¹ã¿ãªã»ãã */
+#define SCFCR_RFRST     0x0002          /* 1:åä¿¡FIFOãã¼ã¿ã¬ã¸ã¹ã¿ãªã»ãã */
+#define SCFCR_LOOP      0x0001          /* 1:ã«ã¼ãããã¯ãã¹ã */
+
+#define SCFDR_T_MASK    0x1F00          /* æªéä¿¡ãã¼ã¿æ°æ½åºãã¹ã¯ */
+#define SCFDR_T_SHIFT   8               /* æªéä¿¡ãã¼ã¿æ°æ½åºå³ã·ããæ° */
+#define SCFDR_R_MASK    0x001F          /* åä¿¡ãã¼ã¿æ°æ½åºãã¹ã¯ */
+#define SCFDR_R_SHIFT   0               /* åä¿¡ãã¼ã¿æ°æ½åºå³ã·ããæ° */
+
+#define SCLSR_ORER      0x0001          /* 1:ãªã¼ãã¼ã©ã³ã¨ã©ã¼ */
+
+#define SCEMR_BGDM      0x0080          /* 1:ãã¼ã¬ã¼ãã¸ã§ãã¬ã¼ã¿åéã¢ã¼ã */
+#define SCEMR_ABCS16    0x0000          /* ãããã¬ã¼ãã®16åã®åºæ¬ã¯ã­ãã¯ã§åä½ */
+#define SCEMR_ABCS8     0x0001          /* ãããã¬ã¼ãã®8åã®åºæ¬ã¯ã­ãã¯ã§åä½ */
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãåæåãã­ãã¯ã®å®ç¾©
+ */
+typedef struct sio_port_initialization_block {
+	uint16_t *port;   			/* ã·ãªã¢ã«ãã¼ãã®ãã¼ã¹ã¬ã¸ã¹ã¿ */
+	uint32_t bps_setting; 		/* ãã¼ã¬ã¼ãã®è¨­å®å¤ */
+} SIOPINIB;
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãç®¡çãã­ãã¯ã®å®ç¾©
+ */
+struct sio_port_control_block {
+	const SIOPINIB  *p_siopinib;  /* ã·ãªã¢ã«I/Oãã¼ãåæåãã­ãã¯ */
+	intptr_t  exinf;              /* æ¡å¼µæ
+å ± */
+	bool_t    openflag;           /* ãªã¼ãã³æ¸ã¿ãã©ã° */
+	bool_t    sendflag;           /* éä¿¡å²è¾¼ã¿ã¤ãã¼ãã«ãã©ã° */
+	bool_t    getready;           /* æå­ãåä¿¡ããç¶æ
+ */
+	bool_t    putready;           /* æå­ãéä¿¡ã§ããç¶æ
+ */
+	bool_t    is_initialized;     /* ããã¤ã¹åæåæ¸ã¿ãã©ã° */
+};
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãåæåãã­ãã¯
+ */
+static const SIOPINIB siopinib_table[TNUM_SIOP] = {
+	{
+		(uint16_t *)(SCIF0_BASE),
+		UART1_BPS_SETTING,
+	},
+#if TNUM_SIOP > 1
+	{
+		(uint16_t *)(SCIF1_BASE),
+		UART2_BPS_SETTING,
+	},
+#endif /* TNUM_SIOP > 1 */
+#if TNUM_SIOP > 2
+	{
+		(uint16_t *)(SCIF2_BASE),
+		UART3_BPS_SETTING,
+	},
+#endif /* TNUM_SIOP > 2 */
+#if TNUM_SIOP > 3
+	{
+		(uint16_t *)(SCIF3_BASE),
+		UART4_BPS_SETTING,
+	},
+#endif /* TNUM_SIOP >  3*/
+#if TNUM_SIOP > 4
+	{
+		(uint16_t *)(SCIF4_BASE),
+		UART5_BPS_SETTING,
+	},
+#endif /* TNUM_SIOP >  4*/
+#if TNUM_SIOP > 5
+	{
+		(uint16_t *)(SCIF5_BASE),
+		UART6_BPS_SETTING,
+	},
+#endif /* TNUM_SIOP >  5*/
+#if TNUM_SIOP > 6
+	{
+		(uint16_t *)(SCIF6_BASE),
+		UART7_BPS_SETTING,
+	},
+#endif /* TNUM_SIOP >  6*/
+#if TNUM_SIOP > 7
+	{
+		(uint16_t *)(SCIF7_BASE),
+		UART8_BPS_SETTING,
+	},
+#endif /* TNUM_SIOP >  7*/
+};
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãç®¡çãã­ãã¯ã®ã¨ãªã¢
+ */
+static SIOPCB	siopcb_table[TNUM_SIOP];
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãIDããç®¡çãã­ãã¯ãåãåºãããã®ãã¯ã­
+ */
+#define INDEX_SIOP(siopid)	 ((uint_t)((siopid) - 1))
+#define get_siopcb(siopid)	 (&(siopcb_table[INDEX_SIOP(siopid)]))
+#define get_siopinib(siopid) (&(siopinib_table[INDEX_SIOP(siopid)]))
+
+/*
+ *  ç®¡çãã­ãã¯ã¸ã®ãã¤ã³ã¿ããã·ãªã¢ã«I/Oãã¼ãIDãåãåºãããã®ãã¯ã­
+ */
+#define SIOPID(p_siopcb)    ((ID)((p_siopcb) - siopcb_table))
+
+/*
+ *  æå­ãåä¿¡ãããï¼
+ */
+Inline bool_t scif_getready(SIOPCB *p_siopcb)
+{
+	uint16_t fsrval;
+	uint16_t lsrval;
+
+	fsrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFSR));
+	lsrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCLSR));
+	if (fsrval & (SCFSR_ER | SCFSR_BRK)) {
+		fsrval = fsrval & ~(SCFSR_ER | SCFSR_BRK);
+		sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFSR), fsrval);
+	}
+	if (lsrval & SCLSR_ORER) {
+		lsrval = lsrval & ~SCLSR_ORER;
+		sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCLSR), lsrval);
+	}
+	if (fsrval & SCFSR_RDF) {
+		return true;
+	}
+	return false;
+}
+
+/*
+ *  æå­ãéä¿¡ã§ãããï¼
+ */
+Inline bool_t scif_putready(SIOPCB *p_siopcb)
+{
+	uint16_t fsrval;
+
+	fsrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFSR));
+	if (fsrval & SCFSR_TDFE) {
+		return true;
+	}
+	return false;
+}
+
+/*
+ *  åä¿¡ããæå­ã®ååºã
+ */
+Inline bool_t scif_getchar(SIOPCB *p_siopcb, char *rxdata)
+{
+	uint16_t fsrval;
+	uint16_t lsrval;
+	uint8_t read_data;
+
+	fsrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFSR));
+	lsrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCLSR));
+	if (fsrval & (SCFSR_ER | SCFSR_BRK)) {
+		fsrval = fsrval & ~(SCFSR_ER | SCFSR_BRK);
+		sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFSR), fsrval);
+	}
+	if (lsrval & SCLSR_ORER) {
+		lsrval = lsrval & ~SCLSR_ORER;
+		sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCLSR), lsrval);
+	}
+	if (fsrval & SCFSR_RDF) {
+		read_data = sil_reb_mem((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFRDR);
+		fsrval = fsrval & ~SCFSR_RDF;
+		sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFSR), fsrval);
+		*rxdata = (char)read_data;
+		return true;
+	}
+	return false;
+}
+
+/*
+ *  éä¿¡ããæå­ã®æ¸è¾¼ã¿
+ */
+Inline void scif_putchar(SIOPCB *p_siopcb, char c)
+{
+	sil_wrb_mem((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFTDR, c);
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCFSR), ~(SCFSR_TEND | SCFSR_TDFE));
+}
+
+/*
+ *  éä¿¡å²è¾¼ã¿è¨±å¯
+ */
+Inline void scif_enable_send(SIOPCB *p_siopcb)
+{
+	uint16_t scrval;
+
+	scrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCSCR));
+	scrval |= SCSCR_TIE;
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCSCR), scrval);
+}
+
+/*
+ *  éä¿¡å²è¾¼ã¿ç¦æ­¢
+ */
+Inline void scif_disable_send(SIOPCB *p_siopcb)
+{
+	uint16_t scrval;
+
+	scrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCSCR));
+	scrval = scrval & ~SCSCR_TIE;
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCSCR), scrval);
+}
+
+
+/*
+ *  åä¿¡å²è¾¼ã¿è¨±å¯
+ */
+Inline void scif_enable_rcv(SIOPCB *p_siopcb)
+{
+	uint16_t scrval;
+
+	scrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCSCR));
+	scrval |= SCSCR_RIE;
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCSCR), scrval);
+}
+
+/*
+ *  åä¿¡å²è¾¼ã¿ç¦æ­¢
+ */
+Inline void
+scif_disable_rcv(SIOPCB *p_siopcb)
+{
+	uint16_t scrval;
+
+	scrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCSCR));
+	scrval = scrval & ~SCSCR_RIE;
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopcb->p_siopinib->port + REG_SCSCR), scrval);
+}
+
+/*
+ *  SIOãã©ã¤ãã®åæå
+ */
+void scif_initialize(void)
+{
+	SIOPCB	*p_siopcb;
+	uint_t	i;
+
+	/*
+	 *  ã·ãªã¢ã«I/Oãã¼ãç®¡çãã­ãã¯ã®åæå
+	 */
+	for (p_siopcb = siopcb_table, i = 0; i < TNUM_SIOP; p_siopcb++, i++) {
+		p_siopcb->p_siopinib = &(siopinib_table[i]);
+		p_siopcb->openflag = false;
+		p_siopcb->sendflag = false;
+	}
+}
+
+
+/*
+ * ãã¼ãã¦ã§ã¢ã®åæåå¦ç
+ */
+static int scif_init_siopinib(const SIOPINIB *p_siopinib)
+{
+	uint16_t fsrval;
+	uint8_t brrval;
+
+	fsrval = RZA1_CLK_P1 / (32 * p_siopinib->bps_setting) - 1;
+	if (fsrval > 255) return 1;
+	brrval = (uint8_t)fsrval;
+
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCSCR), 0);
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFCR), SCFCR_TFRST | SCFCR_RFRST);
+	(void)sil_reh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFSR));
+	(void)sil_reh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCLSR));
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFSR), 0);
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCLSR), 0);
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCSCR), SCSCR_INTCLK);
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCSMR), SCSMR_CKS1);	/* 8N1, P1clock/1 */
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCEMR), 0);
+	sil_wrb_mem((uint8_t *)p_siopinib->port + REG_SCBRR, brrval);
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFCR), SCFCR_RSTRG_15 | SCFCR_RTRG_1 | SCFCR_TTRG_8);
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCSCR), SCSCR_TE | SCSCR_RE | SCSCR_INTCLK);
+	while (sil_reh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFSR)) & SCFSR_RDF) {
+		(void)sil_reb_mem((uint8_t *)p_siopinib->port + REG_SCFRDR);
+		sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFSR), ~SCFSR_RDF);
+	}
+	sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFSR), 0);
+	return 0;
+}
+
+
+/*
+ * ã«ã¼ãã«èµ·åæã®ãã¼ãåºåç¨ã®åæå
+ */
+void
+scif_init(ID siopid)
+{
+	SIOPCB		  *p_siopcb   = get_siopcb(siopid);
+	const SIOPINIB  *p_siopinib = get_siopinib(siopid);
+	/*  ãã®æç¹ã§ã¯ãp_siopcb->p_siopinibã¯åæåããã¦ããªã  */
+
+	if (!(p_siopcb->is_initialized)) {
+		scif_init_siopinib(p_siopinib);
+		p_siopcb->is_initialized = true;
+	}
+}
+
+/*
+ *  ãã¼ãnããªã¼ãã³æ¸ã¿ãï¼ï¼ãã¼ãIDãå¼æ°ï¼
+ */
+bool_t
+scif_openflag_id(ID siopid)
+{
+	return(get_siopcb(siopid)->openflag);
+}
+
+/*
+ *  ãã¼ãnããªã¼ãã³æ¸ã¿ãï¼
+ *  ï¼ãã·ãªã¢ã«I/Oãã¼ãç®¡çãã­ãã¯ãã®å
+é ­çªå°ãå¼æ°ï¼
+ */
+bool_t
+scif_openflag_cb(SIOPCB *p_siopcb)
+{
+	return(p_siopcb->openflag);
+}
+
+/*
+ *  ãã¼ãIDã®åå¾
+ */
+ID
+scif_get_siopid(SIOPCB *p_siopcb)
+{
+	return(SIOPID(p_siopcb));
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã®ãªã¼ãã³
+ */
+SIOPCB *
+scif_opn_por(ID siopid, intptr_t exinf)
+{
+	SIOPCB		  *p_siopcb;
+	const SIOPINIB  *p_siopinib;
+
+	p_siopcb = get_siopcb(siopid);
+	p_siopinib = p_siopcb->p_siopinib;
+
+	/*
+	 * ãã¼ãã¦ã§ã¢ã®åæå
+	 * ãæ¢ã«åæåãã¦ããå ´åã¯ãäºéã«åæåããªãã
+	 */
+	if (!(p_siopcb->is_initialized)) {
+		scif_init_siopinib(p_siopinib);
+		p_siopcb->is_initialized = true;
+	}
+
+	p_siopcb->exinf = exinf;
+	p_siopcb->getready = p_siopcb->putready = false;
+	p_siopcb->openflag = true;
+
+	return(p_siopcb);
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã®ã¯ã­ã¼ãº
+ */
+void
+scif_cls_por(SIOPCB *p_siopcb)
+{
+	sil_wrh_mem(p_siopcb->p_siopinib->port + REG_SCSCR, 0);
+}
+
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã¸ã®ãã¼ãªã³ã°ã§ã®åºå
+ */
+void
+scif_pol_putc(char c, ID siopid)
+{
+	const SIOPINIB *p_siopinib;
+	uint16_t fsrval;
+	SIL_PRE_LOC;
+
+	p_siopinib = get_siopinib(siopid);
+
+	while(1) {
+		/*
+		 *  ãªã¨ã³ãã©ã³ãã«ãããããå
+¨å²è¾¼ã¿ã­ãã¯ç¶æ
+ã«ããã
+		 */
+		SIL_LOC_INT();
+
+		fsrval = sil_reh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFSR));
+		if (fsrval & SCFSR_TDFE) {
+			sil_wrb_mem((uint8_t *)p_siopinib->port + REG_SCFTDR, c);
+			sil_wrh_mem((uint16_t *)((uint8_t *)p_siopinib->port + REG_SCFSR), ~(SCFSR_TEND | SCFSR_TDFE));
+			/*
+			 *  ãªã¿ã¼ã³ããåã«å
+¨å²è¾¼ã¿ã­ãã¯ãã©ã°ãå
+ã®ç¶æ
+ã«æ»ãã
+			 */
+			SIL_UNL_INT();
+			return;
+		} else {
+			/*
+			 *  ããã§å
+¨å²è¾¼ã¿ã­ãã¯ãè§£é¤ãã¦ãå²è¾¼ã¿ãåãä»ããã
+			 */
+			SIL_UNL_INT();
+		}
+	}
+}
+
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã¸ã®æå­éä¿¡
+ */
+bool_t
+scif_snd_chr(SIOPCB *p_siopcb, char c)
+{
+	if (scif_putready(p_siopcb)){
+		scif_putchar(p_siopcb, c);
+		return(true);
+	}
+	return(false);
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®æå­åä¿¡
+ */
+int_t
+scif_rcv_chr(SIOPCB *p_siopcb)
+{
+	char rxdata;
+	if (scif_getready(p_siopcb)) {
+		if (scif_getchar(p_siopcb, &rxdata)) {
+			return((int_t)rxdata);
+		}
+	}
+	return(-1);
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®è¨±å¯
+ */
+void
+scif_ena_cbr(SIOPCB *p_siopcb, uint_t cbrtn)
+{
+	switch (cbrtn) {
+	  case SIO_RDY_SND:
+		scif_enable_send(p_siopcb);
+		break;
+	  case SIO_RDY_RCV:
+		scif_enable_rcv(p_siopcb);
+		break;
+	}
+}
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®ç¦æ­¢
+ */
+void
+scif_dis_cbr(SIOPCB *p_siopcb, uint_t cbrtn)
+{
+	switch (cbrtn) {
+	  case SIO_RDY_SND:
+		scif_disable_send(p_siopcb);
+		break;
+	  case SIO_RDY_RCV:
+		scif_disable_rcv(p_siopcb);
+		break;
+	}
+}
+
+/*
+ *  SIOã®å²è¾¼ã¿ãµã¼ãã¹ã«ã¼ãã³
+ */
+void
+scif_tx_isr(ID siopid)
+{
+	SIOPCB *p_siopcb = get_siopcb(siopid);
+
+	if (scif_putready(p_siopcb)) {
+		scif_irdy_snd(p_siopcb->exinf);
+	}
+}
+
+
+/*
+ *  SIOã®å²è¾¼ã¿ãµã¼ãã¹ã«ã¼ãã³
+ */
+void
+scif_rx_isr(ID siopid)
+{
+	SIOPCB *p_siopcb = get_siopcb(siopid);
+	while (scif_getready(p_siopcb)) {
+		scif_irdy_rcv(p_siopcb->exinf);
+	}
+}
Index: /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/scif.h
===================================================================
--- /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/scif.h	(revision 307)
+++ /asp3_wo_tecs/trunk/arch/arm_gcc/rza1/scif.h	(revision 307)
@@ -0,0 +1,157 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2007-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2001-2011 by Industrial Technology Institute,
+ *                              Miyagi Prefectural Government, JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  @(#) $Id: scif.h 2758 2016-03-10 15:15:26Z ertl-honda $
+ */
+
+
+#ifndef TOPPERS_SCIF_H
+#define TOPPERS_SCIF_H
+
+#ifndef TOPPERS_MACRO_ONLY
+
+#include <kernel.h>
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãç®¡çãã­ãã¯ã®å®ç¾©
+ */
+typedef struct sio_port_control_block	SIOPCB;
+
+/*
+ *  ã³ã¼ã«ããã¯ã«ã¼ãã³ã®è­å¥çªå·
+ */
+#define SIO_RDY_SND    1U        /* éä¿¡å¯è½ã³ã¼ã«ããã¯ */
+#define SIO_RDY_RCV    2U        /* åä¿¡éç¥ã³ã¼ã«ããã¯ */
+
+/*
+ *  SIOãã©ã¤ãã®åæåã«ã¼ãã³
+ */
+extern void scif_initialize(void);
+
+/*
+ * ã«ã¼ãã«èµ·åæã®ãã¼ãåºåç¨ã®åæå
+ */
+extern void scif_init(ID siopid);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã¸ã®ãã¼ãªã³ã°ã§ã®åºå
+ */
+extern void scif_pol_putc(char c, ID siopid);
+
+/*
+ *  ãªã¼ãã³ãã¦ãããã¼ãããããï¼
+ */
+extern bool_t scif_openflag_id(ID siopid);			/*  ãã¼ãID  */
+extern bool_t scif_openflag_cb(SIOPCB *p_siopcb);	/*  ç®¡çãã­ãã¯ã®å
+é ­çªå°  */
+
+/*
+ *  ãã¼ãIDã®åå¾
+ */
+extern ID scif_get_siopid(SIOPCB *p_siopcb);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã®ãªã¼ãã³
+ */
+extern SIOPCB *scif_opn_por(ID siopid, intptr_t exinf);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã®ã¯ã­ã¼ãº
+ */
+extern void scif_cls_por(SIOPCB *p_siopcb);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãã¸ã®æå­éä¿¡
+ */
+extern bool_t scif_snd_chr(SIOPCB *p_siopcb, char c);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®æå­åä¿¡
+ */
+extern int_t scif_rcv_chr(SIOPCB *p_siopcb);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®è¨±å¯
+ */
+extern void  scif_ena_cbr(SIOPCB *p_siopcb, uint_t cbrtn);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®ã³ã¼ã«ããã¯ã®ç¦æ­¢
+ */
+extern void scif_dis_cbr(SIOPCB *p_siopcb, uint_t cbrtn);
+
+/*
+ *  SIOã®å²è¾¼ã¿ãµã¼ãã¹ã«ã¼ãã³
+ */
+extern void scif_tx_isr(ID siopid);
+extern void scif_rx_isr(ID siopid);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®éä¿¡å¯è½ã³ã¼ã«ããã¯
+ */
+extern void scif_irdy_snd(intptr_t exinf);
+
+/*
+ *  ã·ãªã¢ã«I/Oãã¼ãããã®åä¿¡éç¥ã³ã¼ã«ããã¯
+ */
+extern void scif_irdy_rcv(intptr_t exinf);
+
+/*
+ *  ãã¼ãçªå·ããç®¡çãã­ãã¯ã®å
+é ­çªå°ã¸ã®å¤æ
+ */
+extern SIOPCB *scif_get_siopcb(ID siopid);
+
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_SCIF_H */
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/E_PACKAGE
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/E_PACKAGE	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/E_PACKAGE	(revision 307)
@@ -0,0 +1,6 @@
+E_PACKAGE asp3_gr_peach_gcc
+VERSION %date
+
+INCLUDE ../../MANIFEST
+INCLUDE ../../arch/arm_gcc/MANIFEST
+INCLUDE ../../tecsgen/MANIFEST_for_asp3
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/MANIFEST
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/MANIFEST	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/MANIFEST	(revision 307)
@@ -0,0 +1,35 @@
+PACKAGE asp3_arch_arm_gcc
+
+E_PACKAGE
+MANIFEST
+Makefile.target
+gdb_ram.ini
+gdb_rom.ini
+gr_peach.h
+gr_peach_ram.ld
+gr_peach_rom.ld
+renesas_rza1h_swd.cfg
+sf_boot.c
+tPutLogGRPeach.c
+tPutLogGRPeach.cdl
+tSIOPortGRPeach.cdl
+tSIOPortGRPeachMain_inline.h
+target.cdl
+target_cfg1_out.h
+target_check.trb
+target_kernel.cfg
+target_kernel.h
+target_kernel.trb
+target_kernel_impl.c
+target_kernel_impl.h
+target_rename.def
+target_rename.h
+target_sil.h
+target_stddef.h
+target_support.S
+target_syssvc.h
+target_test.h
+target_timer.cfg
+target_timer.h
+target_unrename.h
+target_user.txt
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/Makefile.target
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/Makefile.target	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/Makefile.target	(revision 307)
@@ -0,0 +1,108 @@
+#
+#		Makefile ã®ã¿ã¼ã²ããä¾å­é¨ï¼GR-PEACHç¨ï¼
+#
+#  $Id: Makefile.target 732 2016-04-03 03:08:05Z ertl-hiro $
+# 
+
+#
+#  ã·ã¹ãã åï¼ãããåï¼ã³ã¢åï¼éçºç°å¢åã®å®ç¾©
+#
+SYS = gr_peach
+CHIP = rza1
+CORE = arm
+TOOL = gcc
+
+#
+#  å®è¡å½¢æ
+
+#
+#  ãã©ãã·ã¥ã¡ã¢ãªï¼ROMï¼ã«æ¸ãè¾¼ããï¼RAMã«ã­ã¼ããã¦å®è¡ããããé¸æ
+#  ããï¼
+#
+#EXECUTE_ON = ROM
+EXECUTE_ON = RAM
+
+#
+#  ãã¼ãã­ã¼ãã®çµè¾¼ã¿
+#
+ifeq ($(EXECUTE_ON),ROM)
+	SYSSVC_COBJS := $(SYSSVC_COBJS) sf_boot.o
+endif
+
+#
+#  MPCoreã®ç¨®é¡ã®å®ç¾©
+#
+MPCORE_TYPE = CA9
+
+#
+#  ã³ã³ãã¤ã«ãªãã·ã§ã³
+#
+INCLUDES := $(INCLUDES) -I$(TARGETDIR)
+COPTS := $(COPTS) -mlittle-endian
+LDFLAGS := $(LDFLAGS) -mlittle-endian
+
+#
+#  ã«ã¼ãã«ã«é¢ããå®ç¾©
+#
+KERNEL_DIRS := $(KERNEL_DIRS) $(TARGETDIR)
+KERNEL_COBJS := $(KERNEL_COBJS) target_kernel_impl.o pl310.o
+KERNEL_ASMOBJS := $(KERNEL_ASMOBJS) target_support.o
+
+#
+#  ã·ã¹ãã ãµã¼ãã¹ã«é¢ããå®ç¾©
+#
+SYSSVC_DIRS := $(SYSSVC_DIRS)
+SYSSVC_COBJS := $(SYSSVC_COBJS) scif.o chip_serial.o
+
+#
+#  ã³ã³ãã¤ã«ãªãã·ã§ã³ã¨ãªã³ã«ã¹ã¯ãªããã®å®ç¾©
+#
+ifeq ($(EXECUTE_ON),ROM)
+	CDEFS := $(CDEFS) -DTOPPERS_EXECUTE_ON_ROM
+	LDSCRIPT = $(TARGETDIR)/gr_peach_rom.ld
+else
+	CDEFS := $(CDEFS) -DTOPPERS_EXECUTE_ON_RAM
+	LDSCRIPT = $(TARGETDIR)/gr_peach_ram.ld
+endif
+
+#
+#  GNUéçºç°å¢ã®ã¿ã¼ã²ããã¢ã¼ã­ãã¯ãã£ã®å®ç¾©
+#
+GCC_TARGET = arm-none-eabi
+#GCC_TARGET = arm-atollic-eabi
+
+#
+#  ãã¬ã¼ã¹ã­ã°è¨é²ã®ãµã³ãã«ã³ã¼ãã«é¢ããå®ç¾©
+#
+ifeq ($(ENABLE_TRACE),true)
+	COPTS := $(COPTS) -DTOPPERS_ENABLE_TRACE
+	SYSSVC_DIRS := $(SYSSVC_DIRS) $(SRCDIR)/arch/tracelog
+endif
+
+#
+#  ãããä¾å­é¨ã®ã¤ã³ã¯ã«ã¼ã
+#
+include $(SRCDIR)/arch/arm_gcc/rza1/Makefile.chip
+
+
+#
+#  ãã©ãã·ã¥ã¸ã®æ¸ãè¾¼ã¿
+#
+OPENOCD_DIR  = c:/arm/OpenOCD/0.10.0-201601101000-dev
+OPENOCD_PATH = ${OPENOCD_DIR}/bin/openocd.exe
+OPENOCD_SCRIPT_PATH = ${OPENOCD_DIR}/scripts
+OPENOCD_SCRIPT1  = ${OPENOCD_DIR}/scripts/interface/cmsis-dap.cfg
+OPENOCD_SCRIPT2  = ${OPENOCD_DIR}/scripts/target/renesas_rza1h_swd.cfg 
+GDB = arm-gdb_m0.exe
+
+ifeq ($(EXECUTE_ON),RAM)
+	GDBINI = gdb_ram.ini
+else
+	GDBINI = gdb_rom.ini
+endif
+
+ocd: $(OBJNAME).bin
+	cygstart `cygpath -u "$(OPENOCD_PATH)"` '-s "$(OPENOCD_SCRIPT_PATH)"' '-f "$(OPENOCD_SCRIPT1)"' '-f "$(OPENOCD_SCRIPT2)"'
+
+db: $(OBJNAME).bin
+	$(GDB) $(OBJFILE) -x $(TARGETDIR)/${GDBINI}
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/gdb_ram.ini
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/gdb_ram.ini	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/gdb_ram.ini	(revision 307)
@@ -0,0 +1,17 @@
+target remote :3333
+monitor init
+monitor reset
+monitor halt
+
+# Release L2 cache standby
+set {unsigned int}0x3fffff80=0x00000001
+
+# Allow write access for RAM     
+set {unsigned char}0xfcfe0400=0x3f
+x/b 0xfcfe0400
+set {unsigned char}0xfcfe0404=0x3f
+x/b 0xfcfe0404
+set {unsigned char}0xfcfe0408=0x0f
+x/b 0xfcfe0408
+
+load
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/gdb_rom.ini
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/gdb_rom.ini	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/gdb_rom.ini	(revision 307)
@@ -0,0 +1,4 @@
+target remote :3333
+monitor init
+monitor reset
+monitor halt
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/gr_peach.h
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/gr_peach.h	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/gr_peach.h	(revision 307)
@@ -0,0 +1,86 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2011-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ */
+
+/*
+ *		GR-PEACHã®ãã¼ãã¦ã§ã¢è³æºã®å®ç¾©
+ */
+
+#ifndef TOPPERS_GR_PEACH_H
+#define TOPPERS_GR_PEACH_H
+
+#include <t_stddef.h>
+
+/*
+ *  åã¯ã­ãã¯å¨æ³¢æ°ã®å®ç¾©
+ */
+#define RZA1_CLK_I			400000000UL		/* 400MHz */
+#define RZA1_CLK_I_MHZ		400				/* 400MHz */
+#define RZA1_CLK_G			266666667UL		/* 266.66â¦MHz */
+#define RZA1_CLK_B			133333333UL		/* 133.33â¦MHz */
+#define RZA1_CLK_P1			66666667UL		/* 66.66â¦MHz */
+#define RZA1_CLK_P0			33333333UL		/* 33.33â¦MHz */
+
+/*
+ *  LEDã®ç¹ç¯ï¼æ¶ç¯
+ */
+#define GR_PEACH_LED_RED	13
+#define GR_PEACH_LED_GREEN	14
+#define GR_PEACH_LED_BLUE	15
+#define GR_PEACH_LED_USER	12
+
+#ifndef TOPPERS_MACRO_ONLY
+extern void gr_peach_set_led(uint_t led, uint_t set);
+#endif /* TOPPERS_MACRO_ONLY */
+
+#endif /* TOPPERS_GR_PEACH_H */
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/gr_peach_ram.ld
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/gr_peach_ram.ld	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/gr_peach_ram.ld	(revision 307)
@@ -0,0 +1,111 @@
+/*
+ *  $Id: gr_peach_ram.ld 720 2016-04-01 22:16:17Z ertl-hiro $
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm","elf32-littlearm") 
+OUTPUT_ARCH(arm)
+ENTRY(start);
+
+MEMORY {
+	ROM (rx)  : ORIGIN = 0x20000000, LENGTH = 1M
+	RAM (xrw) : ORIGIN = 0x20100000, LENGTH = 9M
+}
+
+PROVIDE(hardware_init_hook = 0);
+PROVIDE(software_init_hook = 0);
+PROVIDE(software_term_hook = 0);
+
+SECTIONS {
+	.text : {
+		__start_text = .;
+		*(.vector)
+		*(.text)
+		*(.glue_7t)
+		*(.glue_7)
+		__end_kernel = .;
+	} > ROM
+	_etext = .;
+	PROVIDE(etext = .);
+
+	.rodata ALIGN(4) : {
+		__start_rodata = .;
+		*(.rodata)
+		__end_rodata = .;
+	} > ROM
+	.preinit_array ALIGN(4) : {
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP (*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+	} > ROM
+	.init_array ALIGN(4) : {
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP (*(SORT(.init_array.*)))
+		KEEP (*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+	} > ROM
+	.fini_array ALIGN(4) : {
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP (*(SORT(.fini_array.*)))
+		KEEP (*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+	} > ROM
+	.ARM.exidx ALIGN(4) : {
+		__exidx_start = .;
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+		__exidx_end = .;
+	} > ROM
+
+	.data : ALIGN(4) {
+		__start_data = .;
+		*(.data)
+		__end_data = .;
+	} > RAM AT > ROM
+	__start_idata = LOADADDR(.data);
+	. = ALIGN(4);
+	_edata = .;
+	PROVIDE(edata = .);
+
+	.bss ALIGN(4) : {
+		__start_bss = .;
+		*(.bss)
+		*(COMMON)
+		__end_bss = .;
+	} > RAM
+	. = ALIGN(4);
+	_end = .;
+	PROVIDE(end = .);
+	.comment 0 : { *(.comment) }	
+
+	/*
+	 *  DWARF debug sections.
+	 *  Symbols in the DWARF debugging sections are relative to
+	 *  the beginning of the section so we begin them at 0.
+	 */
+
+	/* DWARF 1 */
+	.debug			0 : { *(.debug) }
+	.line			0 : { *(.line) }
+
+	/* GNU DWARF 1 extensions */
+	.debug_srcinfo	0 : { *(.debug_srcinfo) }
+	.debug_sfnames	0 : { *(.debug_sfnames) }
+
+	/* DWARF 1.1 and DWARF 2 */
+	.debug_aranges	0 : { *(.debug_aranges) }
+	.debug_pubnames	0 : { *(.debug_pubnames) }
+
+	/* DWARF 2 */
+	.debug_info		0 : { *(.debug_info) }
+	.debug_abbrev	0 : { *(.debug_abbrev) }
+	.debug_line		0 : { *(.debug_line) }
+	.debug_frame	0 : { *(.debug_frame) }
+	.debug_str		0 : { *(.debug_str) }
+	.debug_loc		0 : { *(.debug_loc) }
+	.debug_macinfo	0 : { *(.debug_macinfo) }
+
+	/* SGI/MIPS DWARF 2 extensions */
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames  0 : { *(.debug_varnames) }
+}	
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/gr_peach_rom.ld
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/gr_peach_rom.ld	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/gr_peach_rom.ld	(revision 307)
@@ -0,0 +1,116 @@
+/*
+ *  $Id: gr_peach_rom.ld 720 2016-04-01 22:16:17Z ertl-hiro $
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm","elf32-littlearm") 
+OUTPUT_ARCH(arm)
+ENTRY(start);
+
+MEMORY {
+	BOOT_LOADER (rx) : ORIGIN = 0x18000000, LENGTH = 0x00004000
+	ROM (rx)         : ORIGIN = 0x18004000, LENGTH = 0x07FFC000
+	RAM (xrw)        : ORIGIN = 0x20000000, LENGTH = 10M
+}
+
+PROVIDE(hardware_init_hook = 0);
+PROVIDE(software_init_hook = 0);
+PROVIDE(software_term_hook = 0);
+
+SECTIONS {
+	.boot : {
+		KEEP(*(.boot_loader)) 
+	} > BOOT_LOADER 
+
+	.text : {
+		__start_text = .;
+		*(.vector)
+		*(.text)
+		*(.glue_7t)
+		*(.glue_7)
+		__end_kernel = .;
+	} > ROM
+	_etext = .;
+	PROVIDE(etext = .);
+
+	.rodata ALIGN(4) : {
+		__start_rodata = .;
+		*(.rodata)
+		__end_rodata = .;
+	} > ROM
+	.preinit_array ALIGN(4) : {
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP (*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+	} > ROM
+	.init_array ALIGN(4) : {
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP (*(SORT(.init_array.*)))
+		KEEP (*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+	} > ROM
+	.fini_array ALIGN(4) : {
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP (*(SORT(.fini_array.*)))
+		KEEP (*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+	} > ROM
+	.ARM.exidx ALIGN(4) : {
+		__exidx_start = .;
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+		__exidx_end = .;
+	} > ROM
+
+	.data : ALIGN(4) {
+		__start_data = .;
+		*(.data)
+		__end_data = .;
+	} > RAM AT > ROM
+	__start_idata = LOADADDR(.data);
+	. = ALIGN(4);
+	_edata = .;
+	PROVIDE(edata = .);
+
+	.bss ALIGN(4) : {
+		__start_bss = .;
+		*(.bss)
+		*(COMMON)
+		__end_bss = .;
+	} > RAM
+	. = ALIGN(4);
+	_end = .;
+	PROVIDE(end = .);
+	.comment 0 : { *(.comment) }	
+
+	/*
+	 *  DWARF debug sections.
+	 *  Symbols in the DWARF debugging sections are relative to
+	 *  the beginning of the section so we begin them at 0.
+	 */
+
+	/* DWARF 1 */
+	.debug			0 : { *(.debug) }
+	.line			0 : { *(.line) }
+
+	/* GNU DWARF 1 extensions */
+	.debug_srcinfo	0 : { *(.debug_srcinfo) }
+	.debug_sfnames	0 : { *(.debug_sfnames) }
+
+	/* DWARF 1.1 and DWARF 2 */
+	.debug_aranges	0 : { *(.debug_aranges) }
+	.debug_pubnames	0 : { *(.debug_pubnames) }
+
+	/* DWARF 2 */
+	.debug_info		0 : { *(.debug_info) }
+	.debug_abbrev	0 : { *(.debug_abbrev) }
+	.debug_line		0 : { *(.debug_line) }
+	.debug_frame	0 : { *(.debug_frame) }
+	.debug_str		0 : { *(.debug_str) }
+	.debug_loc		0 : { *(.debug_loc) }
+	.debug_macinfo	0 : { *(.debug_macinfo) }
+
+	/* SGI/MIPS DWARF 2 extensions */
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames  0 : { *(.debug_varnames) }
+}	
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/renesas_rza1h_swd.cfg
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/renesas_rza1h_swd.cfg	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/renesas_rza1h_swd.cfg	(revision 307)
@@ -0,0 +1,28 @@
+# Renesas RZ/A1H
+
+source [find target/swj-dp.tcl]
+
+set _CHIPNAME rza1h
+swj_newdap $_CHIPNAME cpu -expected-id 0x00000000
+
+set ENDIAN little
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -chain-position $_TARGETNAME
+
+#debug_level 3
+adapter_khz 1000
+adapter_nsrst_delay 400
+reset_config  srst_only
+
+gdb_target_description disable
+gdb_breakpoint_override hard
+
+init
+cortex_a dbginit
+cortex_a maskisr on
+
+${_TARGETNAME} configure -event reset-assert-post "cortex_a dbginit"
+
+reset
+halt
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/sf_boot.c
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/sf_boot.c	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/sf_boot.c	(revision 307)
@@ -0,0 +1,809 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+const char boot_loader[]  __attribute__ ((section(".boot_loader"), used)) =
+{
+    0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,
+    0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,
+    0x00,0x30,0x00,0x18,0x74,0x30,0x00,0x18,0x78,0x30,0x00,0x18,0x7C,0x30,0x00,0x18,
+    0x80,0x30,0x00,0x18,0x84,0x30,0x00,0x18,0x88,0x30,0x00,0x18,0x8C,0x30,0x00,0x18,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0x2C,0x30,0x9F,0xE5,0x00,0x20,0xA0,0xE3,0x28,0x10,0x9F,0xE5,0x28,0x00,0x9F,0xE5,
+    0x10,0x40,0x2D,0xE9,0x23,0x31,0xA0,0xE1,0x02,0x00,0x00,0xEA,0x04,0x40,0x91,0xE4,
+    0x01,0x20,0x82,0xE2,0x04,0x40,0x80,0xE4,0x03,0x00,0x52,0xE1,0xFA,0xFF,0xFF,0xBA,
+    0x10,0x80,0xBD,0xE8,0x97,0x28,0x00,0x00,0x00,0x04,0x00,0x18,0x00,0x02,0x02,0x20,
+    0x70,0x40,0x2D,0xE9,0x02,0x29,0xA0,0xE3,0xC8,0x40,0x9F,0xE5,0x0F,0x10,0xA0,0xE3,
+    0x04,0x00,0xA0,0xE1,0x4C,0x00,0x00,0xEB,0x01,0x00,0x50,0xE3,0x06,0x00,0x00,0x1A,
+    0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,
+    0x33,0x00,0x00,0xEB,0x08,0x00,0x44,0xE2,0xB8,0x00,0xD0,0xE1,0x01,0x34,0xA0,0xE3,
+    0x94,0x50,0x9F,0xE5,0x18,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,
+    0x32,0x00,0x00,0xEB,0x3C,0x40,0x85,0xE2,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x04,0x00,0xA0,0xE1,0x3C,0x00,0x00,0xEB,0x00,0x00,0x50,0xE3,0xF9,0xFF,0xFF,0x1A,
+    0x01,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,0x36,0x00,0x00,0xEB,
+    0x01,0x00,0x50,0xE3,0xF9,0xFF,0xFF,0x1A,0x00,0x00,0xA0,0xE3,0x4C,0x10,0x9F,0xE5,
+    0x04,0x00,0x81,0xE5,0x00,0x20,0xA0,0xE1,0x44,0x40,0x9F,0xE5,0x00,0x10,0xA0,0xE1,
+    0x03,0x30,0xA0,0xE3,0x04,0x00,0xA0,0xE1,0x1C,0x00,0x00,0xEB,0xFF,0x3C,0xA0,0xE3,
+    0x08,0x20,0xA0,0xE3,0x02,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,0x17,0x00,0x00,0xEB,
+    0x05,0x00,0xA0,0xE1,0x01,0x3C,0xA0,0xE3,0x70,0x40,0xBD,0xE8,0x08,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x11,0x00,0x00,0xEA,0x08,0x18,0xFF,0xFC,0x0C,0xA0,0xEF,0x3F,
+    0x00,0xA0,0xEF,0x3F,0x08,0xA0,0xEF,0x3F,0x10,0x40,0x2D,0xE9,0x00,0x40,0xD0,0xE5,
+    0x11,0x12,0xA0,0xE1,0x03,0x20,0xC4,0xE1,0x02,0x10,0x81,0xE1,0x00,0x10,0xC0,0xE5,
+    0x10,0x80,0xBD,0xE8,0x10,0x40,0x2D,0xE9,0xB0,0x40,0xD0,0xE1,0x11,0x12,0xA0,0xE1,
+    0x03,0x20,0xC4,0xE1,0x02,0x10,0x81,0xE1,0xB0,0x10,0xC0,0xE1,0x10,0x80,0xBD,0xE8,
+    0x10,0x40,0x2D,0xE9,0x00,0x40,0x90,0xE5,0x11,0x12,0xA0,0xE1,0x03,0x20,0xC4,0xE1,
+    0x02,0x10,0x81,0xE1,0x00,0x10,0x80,0xE5,0x10,0x80,0xBD,0xE8,0x00,0x00,0xD0,0xE5,
+    0x02,0x00,0x00,0xE0,0x30,0x01,0xA0,0xE1,0x1E,0xFF,0x2F,0xE1,0xB0,0x00,0xD0,0xE1,
+    0x02,0x00,0x00,0xE0,0x30,0x01,0xA0,0xE1,0x1E,0xFF,0x2F,0xE1,0x00,0x00,0x90,0xE5,
+    0x02,0x00,0x00,0xE0,0x30,0x01,0xA0,0xE1,0x1E,0xFF,0x2F,0xE1,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0x10,0xFF,0x2F,0xE1,0x10,0x40,0x2D,0xE9,0x00,0x00,0xA0,0xE3,0x7D,0x03,0x00,0xEB,
+    0x2C,0x10,0x9F,0xE5,0x00,0x00,0xA0,0xE3,0x7B,0x03,0x00,0xEB,0x20,0x20,0x9F,0xE5,
+    0x00,0x10,0xA0,0xE3,0x01,0x00,0xA0,0xE1,0x51,0x03,0x00,0xEB,0x00,0x00,0x50,0xE3,
+    0x00,0x00,0x00,0x0A,0xFE,0xFF,0xFF,0xEA,0x10,0x40,0xBD,0xE8,0x04,0x00,0x9F,0xE5,
+    0xEE,0xFF,0xFF,0xEA,0x94,0x2A,0x02,0x20,0x00,0x40,0x00,0x18,0xF0,0x41,0x2D,0xE9,
+    0x00,0x40,0xA0,0xE1,0x03,0x70,0xA0,0xE1,0x02,0x50,0xA0,0xE1,0x18,0x60,0x9D,0xE5,
+    0x01,0x80,0xA0,0xE1,0x01,0x00,0xA0,0xE1,0xD9,0x01,0x00,0xEB,0x00,0x00,0x50,0xE3,
+    0xF0,0x81,0xBD,0x18,0x00,0x00,0xA0,0xE3,0x01,0x20,0xA0,0xE3,0x0F,0x00,0x56,0xE3,
+    0x54,0x16,0x9F,0xE5,0x18,0x30,0x81,0xE2,0x00,0x00,0x81,0xE5,0x08,0x00,0x81,0xE5,
+    0x14,0x20,0x81,0xE5,0xD8,0x20,0xA0,0x13,0x41,0x00,0x83,0xE8,0xDC,0x20,0xA0,0x03,
+    0x20,0x00,0x81,0xE5,0x01,0x00,0x55,0xE3,0x24,0x00,0x81,0xE5,0x28,0x00,0x81,0xE5,
+    0x2C,0x00,0x81,0xE5,0x30,0x00,0x81,0xE5,0x46,0x20,0xC1,0xE5,0xA4,0x20,0xA0,0x01,
+    0x48,0x20,0x81,0x05,0x48,0x40,0x81,0x15,0x34,0x00,0x81,0xE5,0x38,0x00,0x81,0xE5,
+    0x3C,0x00,0x81,0xE5,0x40,0x00,0x81,0xE5,0x08,0x00,0xA0,0xE1,0xF8,0x15,0x9F,0xE5,
+    0x91,0x08,0x00,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18,0x07,0x20,0xA0,0xE1,
+    0x05,0x10,0xA0,0xE1,0x08,0x00,0xA0,0xE1,0xF0,0x41,0xBD,0xE8,0x9E,0x01,0x00,0xEA,
+    0xFF,0x5F,0x2D,0xE9,0x00,0xB0,0xA0,0xE1,0x02,0x70,0xA0,0xE1,0x01,0x60,0xA0,0xE1,
+    0x0C,0x00,0x9D,0xE5,0x40,0x80,0x9D,0xE5,0x3C,0x90,0x9D,0xE5,0x38,0xA0,0x9D,0xE5,
+    0xAB,0x01,0x00,0xEB,0x00,0x00,0x50,0xE3,0x7A,0x00,0x00,0x1A,0x00,0x50,0xA0,0xE3,
+    0xA4,0x45,0x9F,0xE5,0x01,0x00,0xA0,0xE3,0x00,0x00,0x59,0xE3,0x14,0x10,0x84,0xE2,
+    0x00,0x50,0x84,0xE5,0x08,0x50,0x84,0xE5,0x21,0x01,0x81,0xE8,0x28,0x10,0x84,0xE2,
+    0x20,0x50,0x84,0xE5,0x24,0x50,0x84,0xE5,0x21,0x00,0x81,0xE8,0x30,0x50,0x84,0xE5,
+    0x34,0x50,0x84,0xE5,0x38,0x50,0x84,0xE5,0x3C,0x50,0x84,0xE5,0x40,0x50,0x84,0xE5,
+    0x22,0x00,0x00,0x0A,0x0F,0x00,0x58,0xE3,0x34,0x00,0xA0,0x03,0x32,0x00,0xA0,0x13,
+    0x01,0x00,0x5A,0xE3,0x50,0x15,0x9F,0xE5,0x46,0x00,0xC4,0xE5,0xAB,0x00,0xA0,0x01,
+    0x48,0x00,0x84,0x05,0x48,0xB0,0x84,0x15,0x0C,0x00,0x9D,0xE5,0x62,0x08,0x00,0xEB,
+    0x00,0x00,0x50,0xE3,0x5B,0x00,0x00,0x1A,0x14,0x50,0x84,0xE5,0x10,0x90,0x84,0xE5,
+    0x01,0x30,0xA0,0xE3,0x18,0x50,0x84,0xE5,0x01,0x00,0x5A,0xE3,0x1C,0x50,0x84,0xE5,
+    0x0F,0x00,0xA0,0xE3,0x20,0x50,0x84,0xE5,0x08,0x10,0xA0,0xE3,0x30,0x30,0x84,0xE5,
+    0x0C,0x20,0xA0,0xE3,0x2C,0x50,0x84,0xE5,0x0C,0x00,0x00,0x0A,0x03,0x00,0x17,0xE3,
+    0x20,0x00,0x00,0x0A,0x01,0x00,0x17,0xE3,0x23,0x00,0x00,0x0A,0x00,0x00,0x57,0xE3,
+    0x01,0x80,0xA0,0xE3,0x24,0x10,0x84,0xE5,0x42,0x00,0x00,0xDA,0x2C,0x00,0x00,0xEA,
+    0x0F,0x00,0x58,0xE3,0x02,0x00,0xA0,0x13,0x12,0x00,0xA0,0x03,0xDB,0xFF,0xFF,0xEA,
+    0x07,0x00,0x17,0xE3,0x09,0x00,0x00,0x0A,0x03,0x00,0x17,0xE3,0x0C,0x00,0x00,0x0A,
+    0x01,0x00,0x17,0xE3,0x00,0x00,0xE0,0x13,0x3A,0x00,0x00,0x1A,0x00,0x00,0x57,0xE3,
+    0x02,0x80,0xA0,0xE3,0x24,0x10,0x84,0xE5,0x1F,0x00,0x00,0xCA,0x31,0x00,0x00,0xEA,
+    0x00,0x00,0x57,0xE3,0x08,0x80,0xA0,0xE3,0x24,0x00,0x84,0xE5,0x1E,0x00,0x00,0xCA,
+    0x2C,0x00,0x00,0xEA,0x00,0x00,0x57,0xE3,0x04,0x80,0xA0,0xE3,0x24,0x20,0x84,0xE5,
+    0x17,0x00,0x00,0xCA,0x27,0x00,0x00,0xEA,0x00,0x00,0x57,0xE3,0x04,0x80,0xA0,0xE3,
+    0x24,0x00,0x84,0xE5,0x12,0x00,0x00,0xCA,0x22,0x00,0x00,0xEA,0x00,0x00,0x57,0xE3,
+    0x02,0x80,0xA0,0xE3,0x24,0x20,0x84,0xE5,0x0B,0x00,0x00,0xCA,0x1D,0x00,0x00,0xEA,
+    0x01,0x00,0x58,0xE3,0x06,0x00,0x00,0x0A,0x02,0x00,0x58,0xE3,0x06,0x00,0x00,0x0A,
+    0x04,0x00,0x58,0xE3,0x06,0x00,0x00,0x0A,0x08,0x00,0x58,0xE3,0x0A,0x00,0x00,0x1A,
+    0x05,0x00,0x00,0xEA,0x00,0x00,0xD6,0xE5,0x06,0x00,0x00,0xEA,0xB0,0x00,0xD6,0xE1,
+    0x04,0x00,0x00,0xEA,0x00,0x00,0x96,0xE5,0x02,0x00,0x00,0xEA,0x00,0x10,0x96,0xE5,
+    0x5C,0x10,0x84,0xE5,0x04,0x00,0x96,0xE5,0x58,0x00,0x84,0xE5,0x08,0x70,0x47,0xE0,
+    0x00,0x00,0x57,0xE3,0xF0,0x13,0x9F,0xE5,0x28,0x50,0x84,0xD5,0x08,0x60,0x86,0xE0,
+    0x0C,0x00,0x9D,0xE5,0x0C,0x08,0x00,0xEB,0x00,0x00,0x50,0xE3,0x05,0x00,0x00,0x1A,
+    0x00,0x00,0x57,0xE3,0xE1,0xFF,0xFF,0xCA,0x0C,0x00,0x9D,0xE5,0x09,0x20,0xA0,0xE1,
+    0x0A,0x10,0xA0,0xE1,0x18,0x01,0x00,0xEB,0x10,0xD0,0x8D,0xE2,0xF0,0x9F,0xBD,0xE8,
+    0xF0,0x47,0x2D,0xE9,0x01,0x50,0xA0,0xE1,0xAC,0x43,0x9F,0xE5,0x00,0x70,0xA0,0xE3,
+    0x24,0x10,0x9D,0xE5,0x01,0x80,0xA0,0xE3,0x20,0x90,0x9D,0xE5,0x02,0x60,0xA0,0xE1,
+    0x1C,0x20,0x84,0xE2,0x03,0xA0,0xA0,0xE1,0x00,0x70,0x84,0xE5,0x0F,0x00,0x51,0xE3,
+    0x08,0x70,0x84,0xE5,0x14,0x80,0x84,0xE5,0x18,0x70,0x84,0xE5,0x82,0x00,0x82,0xE8,
+    0x24,0x20,0x84,0xE2,0x6C,0x10,0xA0,0x03,0x6B,0x10,0xA0,0x13,0x80,0x01,0x82,0xE8,
+    0x01,0x00,0x59,0xE3,0x2C,0x70,0x84,0xE5,0xA0,0x00,0xA0,0x01,0x30,0x70,0x84,0xE5,
+    0x46,0x10,0xC4,0xE5,0x07,0x10,0xA0,0xE3,0x34,0x80,0x84,0xE5,0x44,0x70,0xC4,0xE5,
+    0x45,0x10,0xC4,0xE5,0x38,0x70,0x84,0xE5,0x3C,0x70,0x84,0xE5,0x38,0x13,0x9F,0xE5,
+    0x40,0x70,0x84,0xE5,0x48,0x00,0x84,0xE5,0x03,0x00,0xA0,0xE1,0xDE,0x07,0x00,0xEB,
+    0x00,0x00,0x50,0xE3,0xF0,0x87,0xBD,0x18,0x02,0x30,0xA0,0xE3,0x10,0xC0,0x84,0xE2,
+    0x01,0x00,0x59,0xE3,0x0F,0x00,0xA0,0xE3,0x08,0x10,0xA0,0xE3,0x88,0x00,0x8C,0xE8,
+    0x0C,0x20,0xA0,0xE3,0x18,0x70,0x84,0xE5,0x1C,0x70,0x84,0xE5,0x20,0x70,0x84,0xE5,
+    0x2C,0x80,0x84,0xE5,0x30,0x70,0x84,0xE5,0x34,0x70,0x84,0xE5,0x04,0x00,0x00,0x0A,
+    0x04,0x00,0x56,0xE3,0x1F,0x00,0x00,0x0A,0x02,0x00,0x56,0xE3,0x1F,0x00,0x00,0x0A,
+    0x06,0x00,0x00,0xEA,0x08,0x00,0x56,0xE3,0x1A,0x00,0x00,0x0A,0x04,0x00,0x56,0xE3,
+    0x1A,0x00,0x00,0x0A,0x02,0x00,0x56,0xE3,0x00,0x00,0xE0,0x13,0xF0,0x87,0xBD,0x18,
+    0x24,0x10,0x84,0xE5,0x0A,0x00,0xA0,0xE1,0x28,0x70,0x84,0xE5,0xA8,0x12,0x9F,0xE5,
+    0xBD,0x07,0x00,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x87,0xBD,0x18,0x01,0x00,0x56,0xE3,
+    0x50,0x00,0xD4,0x05,0x00,0x00,0xC5,0x05,0x12,0x00,0x00,0x0A,0x02,0x00,0x56,0xE3,
+    0xB0,0x05,0xD4,0x01,0xB0,0x00,0xC5,0x01,0x0E,0x00,0x00,0x0A,0x04,0x00,0x56,0xE3,
+    0x50,0x00,0x94,0x05,0x00,0x00,0x85,0x05,0x0A,0x00,0x00,0x0A,0x08,0x00,0x56,0xE3,
+    0x04,0x00,0x00,0x0A,0x07,0x00,0x00,0xEA,0x24,0x00,0x84,0xE5,0xE8,0xFF,0xFF,0xEA,
+    0x24,0x20,0x84,0xE5,0xE6,0xFF,0xFF,0xEA,0x54,0x00,0x94,0xE5,0x00,0x00,0x85,0xE5,
+    0x50,0x00,0x94,0xE5,0x04,0x00,0x85,0xE5,0x00,0x00,0xA0,0xE3,0xF0,0x87,0xBD,0xE8,
+    0xF0,0x5F,0x2D,0xE9,0x01,0x60,0xA0,0xE1,0x2C,0x42,0x9F,0xE5,0x00,0x50,0xA0,0xE3,
+    0x2C,0x10,0x9D,0xE5,0x01,0x80,0xA0,0xE3,0x28,0xA0,0x9D,0xE5,0x02,0x70,0xA0,0xE1,
+    0x1C,0x20,0x84,0xE2,0x0C,0x90,0xA0,0xE3,0x00,0x50,0x84,0xE5,0x0F,0x00,0x51,0xE3,
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+    0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,
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+    0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0xC3,0x01,0x8B,0xE0,
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+    0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
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+    0x07,0x00,0xA0,0xE1,0xBA,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,
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+    0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
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+    0x0A,0x00,0xA0,0xE1,0xA6,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0xA1,0xFB,0xFF,0xEB,0x0E,0x20,0xA0,0xE3,
+    0x01,0x39,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x82,0x03,0x87,0xE0,0x9C,0xFB,0xFF,0xEB,
+    0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,
+    0x97,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
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+    0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,
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+    0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,
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+    0x0B,0x00,0xA0,0xE1,0x6A,0xFB,0xFF,0xEB,0x0F,0x20,0xA0,0xE3,0x02,0x39,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x02,0x04,0x2A,0xE0,0x65,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3,
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+    0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+    0x5B,0xFB,0xFF,0xEB,0x02,0x00,0x54,0xE3,0x3B,0x02,0x00,0x0A,0xA9,0x02,0x00,0xEA,
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+    0x05,0x00,0xA0,0xE1,0x52,0xFB,0xFF,0xEB,0x02,0x20,0xA0,0xE3,0x04,0x30,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x82,0x63,0x85,0xE1,0x06,0x00,0xA0,0xE1,0x4C,0xFB,0xFF,0xEB,
+    0x3D,0x7C,0x45,0xE2,0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x07,0x00,0xA0,0xE1,0x46,0xFB,0xFF,0xEB,0x02,0x20,0xA0,0xE3,0x04,0x30,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x82,0x83,0x87,0xE0,0x08,0x00,0xA0,0xE1,0x40,0xFB,0xFF,0xEB,
+    0x02,0x20,0xA0,0xE3,0x04,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x82,0x93,0x86,0xE0,
+    0x09,0x00,0xA0,0xE1,0x3A,0xFB,0xFF,0xEB,0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x35,0xFB,0xFF,0xEB,0x01,0x10,0xA0,0xE3,
+    0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x01,0xA4,0x88,0xE1,0x0A,0x00,0xA0,0xE1,
+    0x2F,0xFB,0xFF,0xEB,0x02,0x20,0xA0,0xE3,0x04,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x82,0xB3,0x8A,0xE0,0x0B,0x00,0xA0,0xE1,0x29,0xFB,0xFF,0xEB,0x02,0x20,0xA0,0xE3,
+    0x04,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x82,0x04,0x8B,0xE0,0x24,0xFB,0xFF,0xEB,
+    0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,
+    0x1F,0xFB,0xFF,0xEB,0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x08,0x00,0xA0,0xE1,0x1A,0xFB,0xFF,0xEB,0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x15,0xFB,0xFF,0xEB,0x08,0x30,0xA0,0xE3,
+    0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x10,0xFB,0xFF,0xEB,
+    0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,
+    0x0B,0xFB,0xFF,0xEB,0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x08,0x00,0xA0,0xE1,0x06,0xFB,0xFF,0xEB,0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,
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+    0x03,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0xFC,0xFA,0xFF,0xEB,
+    0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,
+    0xF7,0xFA,0xFF,0xEB,0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x0B,0x00,0xA0,0xE1,0xF2,0xFA,0xFF,0xEB,0x03,0x20,0xA0,0xE3,0x08,0x30,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x82,0x04,0x88,0xE0,0xED,0xFA,0xFF,0xEB,0x08,0x30,0xA0,0xE3,
+    0x03,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0xE8,0xFA,0xFF,0xEB,
+    0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+    0xE3,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x05,0x00,0xA0,0xE1,0xDE,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0xD9,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,
+    0x04,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0xD4,0xFA,0xFF,0xEB,
+    0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+    0xCF,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x09,0x00,0xA0,0xE1,0xCA,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0xC5,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,
+    0x04,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0xC0,0xFA,0xFF,0xEB,
+    0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,
+    0xBB,0xFA,0xFF,0xEB,0x04,0x20,0xA0,0xE3,0x10,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x02,0x04,0x8B,0xE0,0xB6,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0xB1,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,
+    0x04,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xAC,0xFA,0xFF,0xEB,
+    0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,
+    0xA7,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x06,0x00,0xA0,0xE1,0xA2,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x9D,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,
+    0x05,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x98,0xFA,0xFF,0xEB,
+    0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,
+    0x93,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x06,0x00,0xA0,0xE1,0x8E,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0x89,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,
+    0x05,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0x84,0xFA,0xFF,0xEB,
+    0x05,0x20,0xA0,0xE3,0x20,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x02,0x04,0x8A,0xE0,
+    0x7F,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x09,0x00,0xA0,0xE1,0x7A,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x75,0xFA,0xFF,0xEB,0x02,0x00,0x54,0xE3,
+    0xC4,0x01,0x00,0x1A,0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x05,0x00,0xA0,0xE1,0x6E,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x69,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,
+    0x06,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x64,0xFA,0xFF,0xEB,
+    0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+    0x5F,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x09,0x00,0xA0,0xE1,0x5A,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x55,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,
+    0x06,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0x50,0xFA,0xFF,0xEB,
+    0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,
+    0x4B,0xFA,0xFF,0xEB,0x06,0x20,0xA0,0xE3,0x40,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x02,0x44,0x88,0xE0,0x04,0x00,0xA0,0xE1,0x45,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,
+    0x06,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x40,0xFA,0xFF,0xEB,
+    0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+    0x3B,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x05,0x00,0xA0,0xE1,0x36,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x31,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,
+    0x07,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x2C,0xFA,0xFF,0xEB,
+    0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+    0x27,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x09,0x00,0xA0,0xE1,0x22,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x1D,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,
+    0x07,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0x18,0xFA,0xFF,0xEB,
+    0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,
+    0x13,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x04,0x00,0xA0,0xE1,0x0E,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x09,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,
+    0x07,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x04,0xFA,0xFF,0xEB,
+    0x08,0x00,0x9D,0xE5,0x01,0x00,0x50,0xE3,0x52,0x01,0x00,0x1A,0x1C,0x40,0x45,0xE2,
+    0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,
+    0xFB,0xF9,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x43,0x52,0x84,0xE1,0x05,0x00,0xA0,0xE1,0xF5,0xF9,0xFF,0xEB,0x3D,0x6C,0x44,0xE2,
+    0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+    0xEF,0xF9,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x43,0x72,0x86,0xE0,0x07,0x00,0xA0,0xE1,0xE9,0xF9,0xFF,0xEB,0x0C,0x20,0xA0,0xE3,
+    0x01,0x3A,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x02,0x83,0x25,0xE0,0x08,0x00,0xA0,0xE1,
+    0xE3,0xF9,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x05,0x00,0xA0,0xE1,0xDE,0xF9,0xFF,0xEB,0x01,0x10,0xA0,0xE3,0x01,0x3A,0xA0,0xE3,
+    0x0C,0x20,0xA0,0xE3,0x01,0x94,0x87,0xE1,0x09,0x00,0xA0,0xE1,0xD8,0xF9,0xFF,0xEB,
+    0x01,0x10,0xA0,0xE3,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0xA4,0x89,0xE0,
+    0x0A,0x00,0xA0,0xE1,0xD2,0xF9,0xFF,0xEB,0x0C,0x20,0xA0,0xE3,0x01,0x3A,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x82,0xB3,0x87,0xE0,0x0B,0x00,0xA0,0xE1,0xCC,0xF9,0xFF,0xEB,
+    0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+    0xC7,0xF9,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x07,0x00,0xA0,0xE1,0xC2,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,0xBD,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,
+    0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0xB8,0xF9,0xFF,0xEB,
+    0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+    0xB3,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x07,0x00,0xA0,0xE1,0xAE,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xA9,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,
+    0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0xA4,0xF9,0xFF,0xEB,
+    0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,
+    0x9F,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x0A,0x00,0xA0,0xE1,0x9A,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0x95,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,
+    0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x90,0xF9,0xFF,0xEB,
+    0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,
+    0x8B,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x04,0x00,0xA0,0xE1,0x86,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x81,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,
+    0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x7C,0xF9,0xFF,0xEB,
+    0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,
+    0x77,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x08,0x00,0xA0,0xE1,0x72,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x6D,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,
+    0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x68,0xF9,0xFF,0xEB,
+    0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,
+    0x63,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x0B,0x00,0xA0,0xE1,0x5E,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x59,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,
+    0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x54,0xF9,0xFF,0xEB,
+    0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,
+    0x4F,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x05,0x00,0xA0,0xE1,0x4A,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x45,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,
+    0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x40,0xF9,0xFF,0xEB,
+    0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,
+    0x3B,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x05,0x00,0xA0,0xE1,0x36,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x31,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,
+    0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0x2C,0xF9,0xFF,0xEB,
+    0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,
+    0x27,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x08,0x00,0xA0,0xE1,0x22,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x6D,0x00,0x00,0xEA,0x01,0x3B,0xA0,0xE3,
+    0x0A,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x18,0xF9,0xFF,0xEB,
+    0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+    0x13,0xF9,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x07,0x00,0xA0,0xE1,0x0E,0xF9,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x09,0xF9,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,
+    0x0A,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x04,0xF9,0xFF,0xEB,
+    0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+    0xFF,0xF8,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x0A,0x00,0xA0,0xE1,0xFA,0xF8,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0xF5,0xF8,0xFF,0xEB,0x24,0x41,0x9F,0xE5,
+    0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,
+    0xEF,0xF8,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x09,0x00,0xA0,0xE1,0xEA,0xF8,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xE5,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,
+    0x0B,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0xE0,0xF8,0xFF,0xEB,
+    0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+    0xDB,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x07,0x00,0xA0,0xE1,0xD6,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xD1,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,
+    0x0B,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0xCC,0xF8,0xFF,0xEB,
+    0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,
+    0xC7,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x0A,0x00,0xA0,0xE1,0xC2,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0xBD,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,
+    0x0B,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,0xB8,0xF8,0xFF,0xEB,
+    0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,
+    0xB3,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x08,0x00,0xA0,0xE1,0xAE,0xF8,0xFF,0xEB,0x00,0x00,0xA0,0xE3,0xFE,0x8F,0xBD,0xE8,
+    0x20,0x70,0xFE,0xFC,0x24,0x70,0xFE,0xFC,0x20,0x3A,0xFE,0xFC,0xF0,0x41,0x2D,0xE9,
+    0x01,0x00,0x50,0xE3,0x02,0x70,0xA0,0xE1,0x01,0x50,0xA0,0xE1,0x00,0x40,0xA0,0xE1,
+    0x15,0x00,0x00,0x8A,0x54,0x6B,0x9F,0xE5,0x01,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x04,0x01,0x96,0xE7,0x48,0x00,0x80,0xE2,0xB3,0xF8,0xFF,0xEB,0x01,0x00,0x50,0xE3,
+    0x0D,0x00,0x00,0x1A,0x04,0x01,0x96,0xE7,0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0xAD,0xF8,0xFF,0xEB,0x05,0x00,0x50,0xE1,0x14,0x00,0x00,0x0A,0x01,0x00,0x55,0xE3,
+    0x07,0x00,0x00,0x1A,0x05,0x20,0xA0,0xE1,0x07,0x10,0xA0,0xE1,0x04,0x00,0xA0,0xE1,
+    0x49,0xFC,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x01,0x00,0x00,0xAA,0x00,0x00,0xE0,0xE3,
+    0xF0,0x81,0xBD,0xE8,0x04,0x01,0x96,0xE7,0x03,0x30,0xA0,0xE3,0x00,0x20,0xA0,0xE3,
+    0x05,0x10,0xA0,0xE1,0x8D,0xF8,0xFF,0xEB,0x04,0x01,0x96,0xE7,0x02,0x3C,0xA0,0xE3,
+    0x09,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0C,0x00,0x80,0xE2,0x87,0xF8,0xFF,0xEB,
+    0x00,0x00,0xA0,0xE3,0xF0,0x81,0xBD,0xE8,0xF0,0x47,0x2D,0xE9,0x01,0x00,0x50,0xE3,
+    0x03,0x70,0xA0,0xE1,0x02,0x80,0xA0,0xE1,0x20,0x60,0x9D,0xE5,0x01,0x90,0xA0,0xE1,
+    0x00,0x40,0xA0,0xE1,0x71,0x00,0x00,0x8A,0x01,0x20,0xA0,0xE1,0x06,0x10,0xA0,0xE1,
+    0x2D,0xFC,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x6C,0x00,0x00,0xBA,0x01,0x20,0xA0,0xE3,
+    0x88,0x5A,0x9F,0xE5,0x00,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x48,0x00,0x80,0xE2,
+    0x81,0xF8,0xFF,0xEB,0x01,0x00,0x50,0xE3,0x64,0x00,0x00,0x1A,0x04,0x01,0x95,0xE7,
+    0x03,0x35,0xA0,0xE3,0x16,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE3,0x6B,0xF8,0xFF,0xEB,
+    0x04,0x01,0x95,0xE7,0x03,0x36,0xA0,0xE3,0x14,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE3,
+    0x66,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x03,0x37,0xA0,0xE3,0x12,0x20,0xA0,0xE3,
+    0x03,0x10,0xA0,0xE3,0x61,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x03,0x38,0xA0,0xE3,
+    0x10,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE3,0x5C,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+    0x03,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE3,0x57,0xF8,0xFF,0xEB,
+    0x04,0x01,0x95,0xE7,0x03,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE3,
+    0x52,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x03,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3,
+    0x03,0x10,0xA0,0xE3,0x4D,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x01,0x34,0xA0,0xE3,
+    0x18,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x48,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+    0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x43,0xF8,0xFF,0xEB,
+    0x04,0x01,0x95,0xE7,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x3E,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x39,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x08,0x30,0xA0,0xE3,
+    0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x34,0xF8,0xFF,0xEB,0x06,0x20,0xA0,0xE1,
+    0x09,0x10,0xA0,0xE1,0x04,0x00,0xA0,0xE1,0x7F,0xFF,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+    0x07,0x38,0xA0,0xE3,0x10,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0x80,0xE2,
+    0x2A,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x07,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x04,0x00,0x80,0xE2,0x24,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+    0x00,0x20,0xA0,0xE3,0x07,0x30,0xA0,0xE3,0x02,0x10,0xA0,0xE1,0x04,0x00,0x80,0xE2,
+    0x1E,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0xFF,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3,
+    0x08,0x10,0xA0,0xE1,0x08,0x00,0x80,0xE2,0x18,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+    0x03,0x30,0xA0,0xE3,0x00,0x20,0xA0,0xE3,0x07,0x10,0xA0,0xE1,0x08,0x00,0x80,0xE2,
+    0x12,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x48,0x00,0x80,0xE2,0x1C,0xF8,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x01,0x00,0x00,0x0A,
+    0x00,0x00,0xE0,0xE3,0xF0,0x87,0xBD,0xE8,0x04,0x11,0x95,0xE7,0x08,0x05,0x0A,0xE3,
+    0x50,0x00,0x81,0xE5,0x04,0x11,0x95,0xE7,0xC4,0x08,0x9F,0xE5,0x68,0x00,0x81,0xE5,
+    0x00,0x00,0xA0,0xE3,0xF0,0x87,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x00,0x40,0xA0,0xE1,
+    0xA8,0x58,0x9F,0xE5,0x01,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+    0x48,0x00,0x80,0xE2,0x08,0xF8,0xFF,0xEB,0x01,0x00,0x50,0xE3,0xF8,0xFF,0xFF,0x1A,
+    0x70,0x80,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x01,0x00,0x50,0xE3,0x01,0x60,0xA0,0xE1,
+    0x00,0x40,0xA0,0xE1,0x07,0x00,0x00,0x8A,0x01,0x20,0xA0,0xE3,0x6C,0x58,0x9F,0xE5,
+    0x00,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x48,0x00,0x80,0xE2,0xFA,0xF7,0xFF,0xEB,
+    0x01,0x00,0x50,0xE3,0x01,0x00,0x00,0x0A,0x00,0x00,0xE0,0xE3,0x70,0x80,0xBD,0xE8,
+    0x04,0x01,0x95,0xE7,0x02,0x31,0xA0,0xE3,0x1F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0xE2,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x0F,0x38,0xA0,0xE3,0x10,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0x0C,0x00,0x80,0xE2,0xDC,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+    0x01,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0C,0x00,0x80,0xE2,
+    0xD6,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x01,0x30,0xA0,0xE3,0x00,0x20,0xA0,0xE3,
+    0x03,0x10,0xA0,0xE1,0x0C,0x00,0x80,0xE2,0xD0,0xF7,0xFF,0xEB,0x00,0x10,0xD6,0xE5,
+    0xFF,0x38,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x10,0x20,0xA0,0xE3,0x10,0x00,0x80,0xE2,
+    0xCA,0xF7,0xFF,0xEB,0x01,0x10,0xD6,0xE5,0x03,0x31,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+    0x1E,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,0xC4,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+    0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x1C,0x00,0x80,0xE2,
+    0xBE,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x00,0x20,0xA0,0xE3,0xFF,0x30,0xA0,0xE3,
+    0x02,0x10,0xA0,0xE1,0x10,0x00,0x80,0xE2,0xB8,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+    0x03,0x32,0xA0,0xE3,0x1C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x1C,0x00,0x80,0xE2,
+    0xB2,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x1C,0x00,0x80,0xE2,0xAC,0xF7,0xFF,0xEB,0x0E,0x10,0xD6,0xE5,
+    0x03,0x34,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x18,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,
+    0xA6,0xF7,0xFF,0xEB,0x0F,0x10,0xD6,0xE5,0x0F,0x3C,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+    0x08,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,0xA0,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+    0xFF,0x38,0xA0,0xE3,0x10,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x14,0x00,0x80,0xE2,
+    0x9A,0xF7,0xFF,0xEB,0x02,0x10,0xD6,0xE5,0xFF,0x34,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+    0x18,0x20,0xA0,0xE3,0x18,0x00,0x80,0xE2,0x94,0xF7,0xFF,0xEB,0x03,0x10,0xD6,0xE5,
+    0xFF,0x38,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x10,0x20,0xA0,0xE3,0x18,0x00,0x80,0xE2,
+    0x8E,0xF7,0xFF,0xEB,0x04,0x10,0xD6,0xE5,0xFF,0x3C,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+    0x08,0x20,0xA0,0xE3,0x18,0x00,0x80,0xE2,0x88,0xF7,0xFF,0xEB,0x05,0x10,0xD6,0xE5,
+    0xFF,0x30,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x00,0x20,0xA0,0xE3,0x18,0x00,0x80,0xE2,
+    0x82,0xF7,0xFF,0xEB,0x07,0x10,0xD6,0xE5,0x03,0x36,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+    0x14,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,0x7C,0xF7,0xFF,0xEB,0x06,0x10,0xD6,0xE5,
+    0xF0,0x30,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x04,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,
+    0x76,0xF7,0xFF,0xEB,0x0B,0x10,0xD6,0xE5,0x03,0x38,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+    0x10,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,0x70,0xF7,0xFF,0xEB,0x09,0x10,0xD6,0xE5,
+    0x02,0x39,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x0F,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,
+    0x6A,0xF7,0xFF,0xEB,0x0A,0x10,0xD6,0xE5,0x03,0x38,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+    0x10,0x20,0xA0,0xE3,0x58,0x00,0x80,0xE2,0x64,0xF7,0xFF,0xEB,0x08,0x10,0xD6,0xE5,
+    0x07,0x30,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x00,0x20,0xA0,0xE3,0x58,0x00,0x80,0xE2,
+    0x5E,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x01,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x5C,0x00,0x80,0xE2,0x58,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,
+    0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x5C,0x00,0x80,0xE2,
+    0x52,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x00,0x20,0xA0,0xE3,0x01,0x30,0xA0,0xE3,
+    0x02,0x10,0xA0,0xE1,0x5C,0x00,0x80,0xE2,0x4C,0xF7,0xFF,0xEB,0x00,0x00,0xA0,0xE3,
+    0x70,0x80,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x01,0x00,0x50,0xE3,0x00,0x40,0xA0,0xE1,
+    0x00,0x00,0xE0,0x83,0x70,0x80,0xBD,0x88,0x01,0x34,0xA0,0xE3,0x18,0x20,0xA0,0xE3,
+    0x01,0x10,0xA0,0xE3,0xB4,0x55,0x9F,0xE5,0x04,0x01,0x95,0xE7,0x0C,0x00,0x80,0xE2,
+    0x3E,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,
+    0x48,0x00,0x80,0xE2,0x48,0xF7,0xFF,0xEB,0x00,0x00,0x50,0xE3,0xF8,0xFF,0xFF,0x1A,
+    0x70,0x80,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x00,0x40,0xA0,0xE1,0x7C,0x55,0x9F,0xE5,
+    0x02,0x21,0xA0,0xE3,0x1F,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x3E,0xF7,0xFF,0xEB,
+    0x00,0x00,0x50,0xE3,0x09,0x00,0x00,0x0A,0x04,0x00,0xA0,0xE1,0xE0,0xFF,0xFF,0xEB,
+    0x00,0x00,0x50,0xE3,0x00,0x00,0xE0,0xB3,0x70,0x80,0xBD,0xB8,0x02,0x31,0xA0,0xE3,
+    0x1F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x23,0xF7,0xFF,0xEB,
+    0x00,0x00,0xA0,0xE3,0x70,0x80,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x00,0x40,0xA0,0xE1,
+    0x28,0x55,0x9F,0xE5,0x02,0x21,0xA0,0xE3,0x1F,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+    0x29,0xF7,0xFF,0xEB,0x01,0x00,0x50,0xE3,0x09,0x00,0x00,0x0A,0x04,0x00,0xA0,0xE1,
+    0xCB,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x00,0x00,0xE0,0xB3,0x70,0x80,0xBD,0xB8,
+    0x02,0x31,0xA0,0xE3,0x1F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,
+    0x0E,0xF7,0xFF,0xEB,0x00,0x00,0xA0,0xE3,0x70,0x80,0xBD,0xE8,0xF0,0x41,0x2D,0xE9,
+    0x01,0x00,0x50,0xE3,0x01,0x40,0xA0,0xE1,0x00,0x50,0xA0,0xE1,0x19,0x00,0x00,0x8A,
+    0x02,0x21,0xA0,0xE3,0xC4,0x64,0x9F,0xE5,0x1F,0x10,0xA0,0xE3,0x05,0x01,0x96,0xE7,
+    0x11,0xF7,0xFF,0xEB,0x01,0x00,0x50,0xE3,0x0B,0x00,0x00,0x0A,0x05,0x01,0x96,0xE7,
+    0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x48,0x00,0x80,0xE2,0x0A,0xF7,0xFF,0xEB,
+    0x00,0x00,0x50,0xE3,0x0B,0x00,0x00,0x1A,0x05,0x01,0x96,0xE7,0x02,0x31,0xA0,0xE3,
+    0x1F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0xF4,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,
+    0x01,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x48,0x00,0x80,0xE2,0xFE,0xF6,0xFF,0xEB,
+    0x01,0x00,0x50,0xE3,0x01,0x00,0x00,0x0A,0x00,0x00,0xE0,0xE3,0xF0,0x81,0xBD,0xE8,
+    0x05,0x01,0x96,0xE7,0x01,0x39,0xA0,0xE3,0x14,0x10,0x94,0xE5,0x0E,0x20,0xA0,0xE3,
+    0x30,0x00,0x80,0xE2,0xE5,0xF6,0xFF,0xEB,0x14,0x00,0x94,0xE5,0x00,0x00,0x50,0xE3,
+    0x0B,0x00,0x00,0x0A,0x05,0x01,0x96,0xE7,0x46,0x10,0xD4,0xE5,0xFF,0x38,0xA0,0xE3,
+    0x24,0x00,0x80,0xE2,0x10,0x20,0xA0,0xE3,0xDC,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,
+    0x03,0x31,0xA0,0xE3,0x00,0x10,0x94,0xE5,0x1E,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,
+    0xD6,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x01,0x3A,0xA0,0xE3,0x18,0x10,0x94,0xE5,
+    0x0C,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,0xD0,0xF6,0xFF,0xEB,0x18,0x00,0x94,0xE5,
+    0x00,0x00,0x50,0xE3,0x0B,0x00,0x00,0x0A,0x05,0x01,0x96,0xE7,0x47,0x10,0xD4,0xE5,
+    0xFF,0x30,0xA0,0xE3,0x24,0x00,0x80,0xE2,0x00,0x20,0xA0,0xE3,0xC7,0xF6,0xFF,0xEB,
+    0x05,0x01,0x96,0xE7,0x03,0x32,0xA0,0xE3,0x04,0x10,0x94,0xE5,0x1C,0x20,0xA0,0xE3,
+    0x30,0x00,0x80,0xE2,0xC1,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x0F,0x3C,0xA0,0xE3,
+    0x1C,0x10,0x94,0xE5,0x08,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,0xBB,0xF6,0xFF,0xEB,
+    0x1C,0x00,0x94,0xE5,0x00,0x00,0x50,0xE3,0x0B,0x00,0x00,0x0A,0x05,0x01,0x96,0xE7,
+    0x48,0x10,0x94,0xE5,0x00,0x30,0xE0,0xE3,0x00,0x20,0xA0,0xE3,0x28,0x00,0x80,0xE2,
+    0xB2,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x03,0x34,0xA0,0xE3,0x08,0x10,0x94,0xE5,
+    0x18,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,0xAC,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,
+    0xF0,0x30,0xA0,0xE3,0x20,0x10,0x94,0xE5,0x04,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,
+    0xA6,0xF6,0xFF,0xEB,0x20,0x00,0x94,0xE5,0x00,0x00,0x50,0xE3,0x1D,0x00,0x00,0x0A,
+    0x05,0x01,0x96,0xE7,0x4C,0x10,0xD4,0xE5,0xFF,0x34,0xA0,0xE3,0x2C,0x00,0x80,0xE2,
+    0x18,0x20,0xA0,0xE3,0x9D,0xF6,0xFF,0xEB,0x4D,0x10,0xD4,0xE5,0xFF,0x38,0xA0,0xE3,
+    0x05,0x01,0x96,0xE7,0x10,0x20,0xA0,0xE3,0x2C,0x00,0x80,0xE2,0x97,0xF6,0xFF,0xEB,
+    0x4E,0x10,0xD4,0xE5,0xFF,0x3C,0xA0,0xE3,0x05,0x01,0x96,0xE7,0x08,0x20,0xA0,0xE3,
+    0x2C,0x00,0x80,0xE2,0x91,0xF6,0xFF,0xEB,0x4F,0x10,0xD4,0xE5,0xFF,0x30,0xA0,0xE3,
+    0x05,0x01,0x96,0xE7,0x00,0x20,0xA0,0xE3,0x2C,0x00,0x80,0xE2,0x8B,0xF6,0xFF,0xEB,
+    0x05,0x01,0x96,0xE7,0x03,0x36,0xA0,0xE3,0x0C,0x10,0x94,0xE5,0x14,0x20,0xA0,0xE3,
+    0x30,0x00,0x80,0xE2,0x85,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x02,0x39,0xA0,0xE3,
+    0x34,0x10,0x94,0xE5,0x0F,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,0x7F,0xF6,0xFF,0xEB,
+    0x34,0x00,0x94,0xE5,0x00,0x00,0x50,0xE3,0x0B,0x00,0x00,0x0A,0x05,0x01,0x96,0xE7,
+    0x44,0x10,0xD4,0xE5,0x03,0x38,0xA0,0xE3,0x60,0x00,0x80,0xE2,0x10,0x20,0xA0,0xE3,
+    0x76,0xF6,0xFF,0xEB,0x45,0x10,0xD4,0xE5,0x07,0x30,0xA0,0xE3,0x05,0x01,0x96,0xE7,
+    0x00,0x20,0xA0,0xE3,0x60,0x00,0x80,0xE2,0x70,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,
+    0x0F,0x30,0xA0,0xE3,0x24,0x10,0x94,0xE5,0x00,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,
+    0x6A,0xF6,0xFF,0xEB,0x24,0x00,0x94,0xE5,0x58,0x72,0x9F,0xE5,0x00,0x00,0x50,0xE3,
+    0x2C,0x00,0x00,0x0A,0x08,0x00,0x50,0xE3,0x04,0x00,0x00,0x0A,0x0C,0x00,0x50,0xE3,
+    0x0C,0x00,0x00,0x0A,0x0F,0x00,0x50,0xE3,0x14,0x00,0x00,0x0A,0x1F,0x00,0x00,0xEA,
+    0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x6A,0xF6,0xFF,0xEB,
+    0x00,0x00,0x50,0xE3,0x58,0x00,0xD4,0x05,0x05,0x11,0x96,0x07,0x40,0x00,0xC1,0x05,
+    0x06,0x00,0x00,0x1A,0x15,0x00,0x00,0xEA,0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x07,0x00,0xA0,0xE1,0x60,0xF6,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x53,0x00,0x00,0x1A,
+    0x05,0x11,0x96,0xE7,0xB8,0x05,0xD4,0xE1,0xB0,0x04,0xC1,0xE1,0x0B,0x00,0x00,0xEA,
+    0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x56,0xF6,0xFF,0xEB,
+    0x00,0x00,0x50,0xE3,0x49,0x00,0x00,0x0A,0x05,0x11,0x96,0xE7,0x58,0x00,0x94,0xE5,
+    0x40,0x00,0x81,0xE5,0x05,0x01,0x96,0xE7,0x5C,0x10,0x94,0xE5,0x44,0x10,0x80,0xE5,
+    0x03,0x38,0xA0,0xE3,0x05,0x01,0x96,0xE7,0x10,0x20,0xA0,0xE3,0x10,0x10,0x94,0xE5,
+    0x30,0x00,0x80,0xE2,0x39,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x01,0x3C,0xA0,0xE3,
+    0x28,0x10,0x94,0xE5,0x08,0x20,0xA0,0xE3,0x20,0x00,0x80,0xE2,0x33,0xF6,0xFF,0xEB,
+    0x10,0x00,0x94,0xE5,0x00,0x00,0x50,0xE3,0x24,0x00,0x94,0x15,0x00,0x00,0x50,0x13,
+    0x04,0x00,0x00,0x0A,0x2C,0x00,0x94,0xE5,0x01,0x00,0x50,0xE3,0x30,0x00,0x94,0x05,
+    0x01,0x00,0x50,0x03,0x3B,0xFF,0xFF,0x0A,0x05,0x01,0x96,0xE7,0x2C,0x10,0x94,0xE5,
+    0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x20,0x00,0x80,0xE2,0x23,0xF6,0xFF,0xEB,
+    0x05,0x01,0x96,0xE7,0x02,0x30,0xA0,0xE3,0x30,0x10,0x94,0xE5,0x01,0x20,0xA0,0xE3,
+    0x20,0x00,0x80,0xE2,0x1D,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x01,0x3C,0xA0,0xE3,
+    0x38,0x10,0x94,0xE5,0x08,0x20,0xA0,0xE3,0x64,0x00,0x80,0xE2,0x17,0xF6,0xFF,0xEB,
+    0x05,0x01,0x96,0xE7,0x10,0x30,0xA0,0xE3,0x3C,0x10,0x94,0xE5,0x04,0x20,0xA0,0xE3,
+    0x64,0x00,0x80,0xE2,0x11,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x01,0x30,0xA0,0xE3,
+    0x40,0x10,0x94,0xE5,0x00,0x20,0xA0,0xE3,0x64,0x00,0x80,0xE2,0x0B,0xF6,0xFF,0xEB,
+    0x05,0x01,0x96,0xE7,0x01,0x30,0xA0,0xE3,0x00,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE1,
+    0x20,0x00,0x80,0xE2,0x05,0xF6,0xFF,0xEB,0x05,0x00,0xA0,0xE1,0xAD,0xF9,0xFF,0xEB,
+    0x24,0x00,0x94,0xE5,0x08,0x00,0x50,0xE3,0x08,0x00,0x00,0x0A,0x0C,0x00,0x50,0xE3,
+    0x11,0x00,0x00,0x0A,0x0F,0x00,0x50,0xE3,0x16,0x00,0x00,0x0A,0x21,0x00,0x00,0xEA,
+    0x05,0x11,0x96,0xE7,0x58,0x00,0x94,0xE5,0x40,0x00,0x81,0xE5,0xB7,0xFF,0xFF,0xEA,
+    0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x02,0xF6,0xFF,0xEB,
+    0x00,0x00,0x50,0xE3,0x05,0x01,0x96,0x07,0x38,0x00,0xD0,0x05,0x19,0x00,0x00,0x0A,
+    0x05,0x01,0x96,0xE7,0xB8,0x03,0xD0,0xE1,0x16,0x00,0x00,0xEA,0x03,0x20,0xA0,0xE3,
+    0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0xF7,0xF5,0xFF,0xEB,0x00,0x00,0x50,0xE3,
+    0x0E,0x00,0x00,0x1A,0xF5,0xFF,0xFF,0xEA,0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
+    0x07,0x00,0xA0,0xE1,0xF0,0xF5,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x07,0x00,0x00,0x0A,
+    0x05,0x01,0x96,0xE7,0x38,0x00,0x90,0xE5,0x50,0x00,0x84,0xE5,0x05,0x01,0x96,0xE7,
+    0x3C,0x00,0x90,0xE5,0x54,0x00,0x84,0xE5,0x00,0x00,0xA0,0xE3,0xF0,0x81,0xBD,0xE8,
+    0x05,0x01,0x96,0xE7,0x38,0x00,0x90,0xE5,0x50,0x00,0x84,0xE5,0xF9,0xFF,0xFF,0xEA,
+    0x8C,0x2A,0x02,0x20,0x63,0x63,0x00,0xA5,0x00,0xA0,0xEF,0x3F,0xF0,0x40,0x2D,0xE9,
+    0xEB,0xC0,0xA0,0xE3,0x00,0xC0,0xC1,0xE5,0x08,0x70,0xA0,0xE3,0x06,0x70,0xC1,0xE5,
+    0x03,0x60,0xA0,0xE3,0x08,0x60,0xC1,0xE5,0x55,0x50,0xA0,0xE3,0x02,0x50,0xC1,0xE5,
+    0x01,0x40,0xA0,0xE3,0x09,0x40,0xC1,0xE5,0x02,0x30,0xA0,0xE3,0x0E,0x30,0xC1,0xE5,
+    0x00,0x20,0xA0,0xE3,0x07,0x30,0xC1,0xE5,0x00,0x00,0x50,0xE3,0x0B,0x30,0xC1,0xE5,
+    0x07,0x00,0xA0,0xE3,0x01,0x20,0xC1,0xE5,0x03,0x20,0xC1,0xE5,0x04,0x20,0xC1,0xE5,
+    0x05,0x20,0xC1,0xE5,0x0A,0x20,0xC1,0xE5,0x0C,0x40,0xC1,0x05,0x0C,0x30,0xC1,0x15,
+    0x0D,0x20,0xC1,0xE5,0x0F,0x00,0xC1,0xE5,0xF0,0x80,0xBD,0xE8,0x00,0xA0,0xEF,0x3F,
+    0x00,0xB0,0xEF,0x3F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+    0x5C,0x00,0x9F,0xE5,0x01,0x10,0xA0,0xE3,0x00,0x10,0x80,0xE5,0x00,0x00,0x90,0xE5,
+    0x50,0x00,0x9F,0xE5,0x35,0x10,0x01,0xE3,0xB0,0x10,0xC0,0xE1,0x00,0x00,0x90,0xE5,
+    0x44,0x00,0x9F,0xE5,0x01,0x10,0xA0,0xE3,0xB0,0x10,0xC0,0xE1,0x00,0x00,0x90,0xE5,
+    0x10,0x0F,0x11,0xEE,0x02,0x0A,0xC0,0xE3,0x01,0x0A,0xC0,0xE3,0x04,0x00,0xC0,0xE3,
+    0x01,0x00,0xC0,0xE3,0x10,0x0F,0x01,0xEE,0x26,0x00,0x00,0xEB,0x1C,0xD0,0x9F,0xE5,
+    0x14,0x00,0x00,0xEB,0x0D,0x00,0x00,0xEB,0x0E,0x00,0x00,0xEB,0x0F,0x00,0x00,0xEB,
+    0xFE,0xFF,0xFF,0xEA,0x80,0xFF,0xFF,0x3F,0x10,0x00,0xFE,0xFC,0x14,0x00,0xFE,0xFC,
+    0x00,0x00,0x03,0x20,0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,
+    0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,
+    0x04,0xF0,0x1F,0xE5,0x40,0x00,0x02,0x20,0x04,0xF0,0x1F,0xE5,0x00,0x00,0x02,0x20,
+    0x04,0xF0,0x1F,0xE5,0x04,0x02,0x02,0x20,0x2C,0x30,0x9F,0xE5,0x00,0x20,0xA0,0xE3,
+    0x28,0x10,0x9F,0xE5,0x28,0x00,0x9F,0xE5,0x10,0x40,0x2D,0xE9,0x23,0x31,0xA0,0xE1,
+    0x02,0x00,0x00,0xEA,0x04,0x40,0x91,0xE4,0x01,0x20,0x82,0xE2,0x04,0x40,0x80,0xE4,
+    0x03,0x00,0x52,0xE1,0xFA,0xFF,0xFF,0xBA,0x10,0x80,0xBD,0xE8,0xAF,0x01,0x00,0x00,
+    0x00,0x02,0x00,0x18,0x00,0x00,0x02,0x20,0x04,0x00,0x9F,0xE5,0x10,0x0F,0x0C,0xEE,
+    0x1E,0xFF,0x2F,0xE1,0x00,0x00,0x00,0x18,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,
+};
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_cfg1_out.h
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_cfg1_out.h	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_cfg1_out.h	(revision 307)
@@ -0,0 +1,11 @@
+/*
+ *		cfg1_out.cããªã³ã¯ããããã«å¿
+è¦ãªã¹ã¿ãã®å®ç¾©
+ *
+ *  $Id: target_cfg1_out.h 720 2016-04-01 22:16:17Z ertl-hiro $
+ */
+
+/*
+ *  ã³ã¢ä¾å­ã®ã¹ã¿ãã®å®ç¾©ï¼ãããä¾å­é¨ã¯é£ã°ãï¼
+ */
+#include "core_cfg1_out.h"
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_check.trb
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_check.trb	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_check.trb	(revision 307)
@@ -0,0 +1,9 @@
+# -*- coding: utf-8 -*-
+#
+#		ãã¹3ã®çæã¹ã¯ãªããã®ã¿ã¼ã²ããä¾å­é¨ï¼GR-PEACHç¨ï¼
+#
+
+#
+#  çæã¹ã¯ãªããã®ã³ã¢ä¾å­é¨ï¼ãããä¾å­é¨ã¯é£ã°ãï¼
+#
+IncludeTrb("core_check.trb")
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_kernel.cfg
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_kernel.cfg	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_kernel.cfg	(revision 307)
@@ -0,0 +1,7 @@
+/*
+ *		ã«ã¼ãã«å®è£
+ã®ã³ã³ãã£ã®ã¥ã¬ã¼ã·ã§ã³ãã¡ã¤ã«
+ *
+ *  $Id: target_kernel.cfg 720 2016-04-01 22:16:17Z ertl-hiro $
+ */
+INCLUDE("target_timer.cfg")
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_kernel.h
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_kernel.h	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_kernel.h	(revision 307)
@@ -0,0 +1,84 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  $Id: target_kernel.h 720 2016-04-01 22:16:17Z ertl-hiro $
+ */
+
+/*
+ *		kernel.hã®ã¿ã¼ã²ããä¾å­é¨ï¼GR-PEACHç¨ï¼
+ *
+ *  ãã®ããããã¡ã¤ã«ã¯ï¼kernel.hããã¤ã³ã¯ã«ã¼ããããï¼ä»ã®ãã¡ã¤ã«
+ *  ããç´æ¥ã¤ã³ã¯ã«ã¼ããããã¨ã¯ãªãï¼ãã®ãã¡ã¤ã«ãã¤ã³ã¯ã«ã¼ããã
+ *  åã«ï¼t_stddef.hãã¤ã³ã¯ã«ã¼ããããã®ã§ï¼ããã«ä¾å­ãã¦ãããï¼
+ */
+
+#ifndef TOPPERS_TARGET_KERNEL_H
+#define TOPPERS_TARGET_KERNEL_H
+
+/*
+ *  ä½¿ç¨ããSCIF(0 to 7)
+ */
+#define USE_SCIF_PORTID   2
+
+/*
+ *  ä½¿ç¨ããSIOã®ãã¼ãID
+ *  SCIF ã¨éã 1 ãªãªã¸ã³ã¨ãªã£ã¦ããï¼
+ */
+#define USE_SIO_PORTID  (USE_SCIF_PORTID + 1)
+
+/*
+ *  ãããã§å
+±éãªå®ç¾©
+ */
+#include "chip_kernel.h"
+
+#endif /* TOPPERS_TARGET_KERNEL_H */
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_kernel.trb
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_kernel.trb	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_kernel.trb	(revision 307)
@@ -0,0 +1,9 @@
+# -*- coding: utf-8 -*-
+#
+#		ãã¹2ã®çæã¹ã¯ãªããã®ã¿ã¼ã²ããä¾å­é¨ï¼GR-PEACHç¨ï¼
+#
+
+#
+#  çæã¹ã¯ãªããã®ãããä¾å­é¨
+#
+IncludeTrb("chip_kernel.trb")
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_kernel_impl.c
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_kernel_impl.c	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_kernel_impl.c	(revision 307)
@@ -0,0 +1,329 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2007-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  $Id: target_kernel_impl.c 734 2016-04-03 09:12:48Z ertl-hiro $
+ */
+
+/*
+ *		ã«ã¼ãã«ã®ã¿ã¼ã²ããä¾å­é¨ï¼GR-PEACHç¨ï¼
+ */
+
+#include "kernel_impl.h"
+#include <sil.h>
+#include "arm.h"
+#include "rza1.h"
+#include "scif.h"
+#include "pl310.h"
+
+/*
+ *  ã«ã¼ãã«åä½æã®ã¡ã¢ãªãããã¨é¢é£ããå®ç¾©
+ *
+ *  0x18000000 - 0x1fffffffï¼ã·ãªã¢ã«ãã©ãã·ã¥ã¡ã¢ãªï¼128MBï¼
+ *  0x20000000 - 0x209fffffï¼å
+èµSRAMï¼10MBï¼
+ *  0x3fe00000 - 0x3fffffffï¼I/Oé åï¼2MBï¼ï¼äºç´é åãå«ã
+ *  0xe8000000 - 0xffffffffï¼I/Oé åï¼384MBï¼ï¼äºç´é åãå«ã
+ */
+
+/*
+ *  MMUã¸ã®è¨­å®å±æ§ï¼ç¬¬1ã¬ãã«ãã£ã¹ã¯ãªãã¿ï¼
+ */
+#define MMU_ATTR_RAM	(ARM_MMU_DSCR1_SHARED|ARMV6_MMU_DSCR1_APX0 \
+							|ARM_MMU_DSCR1_TEX001|ARM_MMU_DSCR1_AP11 \
+							|ARM_MMU_DSCR1_CB11)
+#define MMU_ATTR_IODEV	(ARM_MMU_DSCR1_SHARED|ARMV6_MMU_DSCR1_APX0 \
+							|ARM_MMU_DSCR1_TEX000|ARM_MMU_DSCR1_AP11 \
+							|ARM_MMU_DSCR1_CB01|ARMV6_MMU_DSCR1_NOEXEC)
+/*
+ *  MMUã®è¨­å®æ
+å ±ï¼ã¡ã¢ãªã¨ãªã¢ã®æ
+å ±ï¼
+ */
+ARM_MMU_CONFIG arm_memory_area[] = {
+	{ SPI_ADDR, SPI_ADDR, SPI_SIZE, MMU_ATTR_RAM },
+	{ SRAM_ADDR, SRAM_ADDR, SRAM_SIZE, MMU_ATTR_RAM },
+	{ IO1_ADDR, IO1_ADDR, IO1_SIZE, MMU_ATTR_IODEV },
+	{ IO2_ADDR, IO2_ADDR, IO2_SIZE, MMU_ATTR_IODEV }
+};
+
+/*
+ *  MMUã®è¨­å®æ
+å ±ã®æ°ï¼ã¡ã¢ãªã¨ãªã¢ã®æ°ï¼
+ */
+const uint_t arm_tnum_memory_area
+					= sizeof(arm_memory_area) / sizeof(ARM_MMU_CONFIG);
+
+/*
+ *  ä½æ¶è²»é»åã¢ã¼ãã®åæå
+ */
+static void
+lowpower_initialize(void)
+{
+	/* ã¹ã¿ã³ãã¤ã¢ã¼ãæã«ç«¯å­ç¶æ
+ãç¶­æããï¼CoreSightåä½ */
+	sil_wrb_mem(RZA1_STBCR2, 0x6a);
+	(void) sil_reb_mem(RZA1_STBCR2);		/* ããã¼ãªã¼ã */
+
+	/* IEBus, irDA, LIN0, LIN1, MTU2, RSCAN2, ASC, PWMåä½ */
+	sil_wrb_mem(RZA1_STBCR3, 0x00);
+	(void) sil_reb_mem(RZA1_STBCR3);		/* ããã¼ãªã¼ã */
+
+	/* SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7åä½ */
+	sil_wrb_mem(RZA1_STBCR4, 0x00);
+	(void) sil_reb_mem(RZA1_STBCR4);		/* ããã¼ãªã¼ã */
+
+	/* SCIM0, SCIM1, SDG0, SDG1, SDG2, SDG3, OSTM0, OSTM1åä½ */
+	sil_wrb_mem(RZA1_STBCR5, 0x00);
+	(void) sil_reb_mem(RZA1_STBCR5);		/* ããã¼ãªã¼ã */
+
+	/* A/D, CEU, DISCOM0, DISCOM1, DRC0, DRC1, JCU, RTClockåä½ */
+	sil_wrb_mem(RZA1_STBCR6, 0x00);
+	(void) sil_reb_mem(RZA1_STBCR6);		/* ããã¼ãªã¼ã */
+
+	/* DVDEC0, DVDEC1, ETHER, FLCTL, USB0, USB1åä½ */
+	sil_wrb_mem(RZA1_STBCR7, 0x24);
+	(void) sil_reb_mem(RZA1_STBCR7);		/* ããã¼ãªã¼ã */
+
+	/* IMR-LS20, IMR-LS21, IMR-LSD, MMCIF, MOST50, SCUXåä½ */
+	sil_wrb_mem(RZA1_STBCR8, 0x05);
+	(void) sil_reb_mem(RZA1_STBCR8);		/* ããã¼ãªã¼ã */
+
+	/* I2C0, I2C1, I2C2, I2C3, SPIBSC0, SPIBSC1, VDC50, VDC51åä½ */
+	sil_wrb_mem(RZA1_STBCR9, 0x00);
+	(void) sil_reb_mem(RZA1_STBCR9);		/* ããã¼ãªã¼ã */
+
+	/* RSPI0, RSPI1, RSPI2, RSPI3, RSPI4, CD-ROMDEC, RSPDIF, RGPVGåä½ */
+	sil_wrb_mem(RZA1_STBCR10, 0x00);
+	(void) sil_reb_mem(RZA1_STBCR10);		/* ããã¼ãªã¼ã */
+
+	/* SSIF0, SSIF1, SSIF2, SSIF3, SSIF4, SSIF5åä½ */
+	sil_wrb_mem(RZA1_STBCR11, 0xc0);
+	(void) sil_reb_mem(RZA1_STBCR11);		/* ããã¼ãªã¼ã */
+
+	/* SDHI00, SDHI01, SDHI10, SDHI11åä½ */
+	sil_wrb_mem(RZA1_STBCR12, 0xf0);
+	(void) sil_reb_mem(RZA1_STBCR12);		/* ããã¼ãªã¼ã */
+}
+
+/*
+ *  æ±ç¨å
+¥åºåãã¼ãã®åæåï¼ãã¼ãï¼ããªãã§ã©ã«å
+¼ç¨ãã³ã®ã¢ãµã¤ã³ã®è¨­å®ï¼
+ */
+static void
+port_initialize(void)
+{
+	/* ãã¼ã6:ããã3ï¼TxD2ï¼ã®è¨­å® */
+	rza1_config_port(RZA1_PORT_PIBC(6),  3, 0);
+	rza1_config_port(RZA1_PORT_PBDC(6),  3, 0);
+	rza1_config_port(RZA1_PORT_PIPC(6),  3, 1);
+	/* ç¬¬7å
+¼ç¨æ©è½ï¼TxD2ï¼ï¼åºå */
+	rza1_config_port(RZA1_PORT_PMC(6),   3, 1);
+	rza1_config_port(RZA1_PORT_PFCAE(6), 3, 1);
+	rza1_config_port(RZA1_PORT_PFCE(6),  3, 1);
+	rza1_config_port(RZA1_PORT_PFC(6),   3, 0);
+	rza1_config_port(RZA1_PORT_PM(6),    3, 0);
+
+	/* ãã¼ã6:ããã2ï¼RxD2ï¼ã®è¨­å® */
+	rza1_config_port(RZA1_PORT_PIBC(6),  2, 0);
+	rza1_config_port(RZA1_PORT_PBDC(6),  2, 0);
+	rza1_config_port(RZA1_PORT_PIPC(6),  2, 1);
+	/* ç¬¬7å
+¼ç¨æ©è½ï¼RxD2ï¼ï¼å
+¥å */
+	rza1_config_port(RZA1_PORT_PMC(6),   2, 1);
+	rza1_config_port(RZA1_PORT_PFCAE(6), 2, 1);
+	rza1_config_port(RZA1_PORT_PFCE(6),  2, 1);
+	rza1_config_port(RZA1_PORT_PFC(6),   2, 0);
+	rza1_config_port(RZA1_PORT_PM(6),    2, 1);
+
+	/* ãã¼ã6:ããã13ï¼LED1ï¼èµ¤ï¼ã®è¨­å® */
+	rza1_config_port(RZA1_PORT_PIBC(6),  13, 0);
+	rza1_config_port(RZA1_PORT_PBDC(6),  13, 0);
+	/* ãã¼ãã¢ã¼ãï¼åºå */
+	rza1_config_port(RZA1_PORT_PMC(6),   13, 0);
+	rza1_config_port(RZA1_PORT_PM(6),    13, 0);
+
+	/* ãã¼ã6:ããã14ï¼LED2ï¼ç·ï¼ã®è¨­å® */
+	rza1_config_port(RZA1_PORT_PIBC(6),  14, 0);
+	rza1_config_port(RZA1_PORT_PBDC(6),  14, 0);
+	/* ãã¼ãã¢ã¼ãï¼åºå */
+	rza1_config_port(RZA1_PORT_PMC(6),   14, 0);
+	rza1_config_port(RZA1_PORT_PM(6),    14, 0);
+
+	/* ãã¼ã6:ããã15ï¼LED3ï¼éï¼ã®è¨­å® */
+	rza1_config_port(RZA1_PORT_PIBC(6),  15, 0);
+	rza1_config_port(RZA1_PORT_PBDC(6),  15, 0);
+	/* ãã¼ãã¢ã¼ãï¼åºå */
+	rza1_config_port(RZA1_PORT_PMC(6),   15, 0);
+	rza1_config_port(RZA1_PORT_PM(6),    15, 0);
+
+	/* ãã¼ã6:ããã12ï¼LED4ï¼ã¦ã¼ã¶ï¼ã®è¨­å® */
+	rza1_config_port(RZA1_PORT_PIBC(6),  12, 0);
+	rza1_config_port(RZA1_PORT_PBDC(6),  12, 0);
+	/* ãã¼ãã¢ã¼ãï¼åºå */
+	rza1_config_port(RZA1_PORT_PMC(6),   12, 0);
+	rza1_config_port(RZA1_PORT_PM(6),    12, 0);
+
+	/* ãã¼ã6:ããã0ï¼ã¦ã¼ã¶ãã¿ã³ï¼ã®è¨­å® */
+	rza1_config_port(RZA1_PORT_PIBC(6),  0, 1);
+	rza1_config_port(RZA1_PORT_PBDC(6),  0, 0);
+	/* ç¬¬6å
+¼ç¨æ©è½ï¼IRQ5ï¼ï¼å
+¥å */
+	rza1_config_port(RZA1_PORT_PMC(6),   0, 1);
+	rza1_config_port(RZA1_PORT_PFCAE(6), 0, 1);
+	rza1_config_port(RZA1_PORT_PFCE(6),  0, 0);
+	rza1_config_port(RZA1_PORT_PFC(6),   0, 1);
+	rza1_config_port(RZA1_PORT_PM(6),    0, 1);
+}
+
+/*
+ *  ã·ã¹ãã ã­ã°ã®ä½ã¬ãã«åºåã®ããã®åæå
+ *
+ *  ã»ã«ã¿ã¤ãtPutLogGRPeachå
+ã«å®è£
+ããã¦ããé¢æ°ãç´æ¥å¼ã³åºãï¼
+ */
+extern void	tPutLogGRPeach_initialize(void);
+
+/*
+ *  ã¿ã¼ã²ããä¾å­ã®åæå
+ */
+void
+target_initialize(void)
+{
+	extern void	*vector_table;		/* ãã¯ã¿ãã¼ãã« */
+
+	/*
+	 *  Low exception vectorsãä½¿ç¨
+	 */
+	arm_set_low_vectors();
+
+	/*
+	 *  ãããä¾å­ã®åæå
+	 */
+	chip_initialize();
+
+	/*
+	 *  ä½æ¶è²»é»åã¢ã¼ãã®åæå
+	 */
+	lowpower_initialize();
+
+	/*
+	 *  æ±ç¨å
+¥åºåãã¼ãã®åæåï¼ãã¼ãï¼ããªãã§ã©ã«å
+¼ç¨ãã³ã®ã¢ãµã¤ã³ã®è¨­å®ï¼
+	 */
+	port_initialize();
+
+	/*
+	 *  ãã¯ã¿ãã¼ãã«ã®è¨­å®
+	 */
+	CP15_WRITE_VBAR((uint32_t) &vector_table);
+
+	/*
+	 *  L2ã­ã£ãã·ã¥ã³ã³ãã­ã¼ã©ï¼PL310ï¼ã®åæå
+	 */
+	pl310_initialize(0x0U, ~0x0U);
+
+	/*
+	 *  LEDãéè²ã«ç¹ç¯ããã
+	 */
+	gr_peach_set_led(GR_PEACH_LED_BLUE, 1);
+
+	/*
+	 *  ä½ã¬ãã«åºåç¨ã«SIOãåæå
+	 */
+	scif_init(USE_SIO_PORTID);
+}
+
+/*
+ *  ã¿ã¼ã²ããä¾å­ã®çµäºå¦ç
+ */
+void
+target_exit(void)
+{
+	/*
+	 *  ãããä¾å­ã®çµäºå¦ç
+	 */
+	chip_terminate();
+
+	/*
+	 *  bkptå½ä»¤ã«ãããããã¬ã«å¶å¾¡ãç§»ãï¼ãã©ã¡ã¼ã¿ãä½ãè¯ããæªæ¤è¨ï¼
+	 */
+	Asm("bkpt #0");
+
+	while (true) ;
+}
+
+/*
+ *  ã·ã¹ãã ã­ã°ã®ä½ã¬ãã«åºåã®ããã®æå­åºå
+ */
+void
+target_fput_log(char c)
+{
+	if (c == '\n') {
+		scif_pol_putc('\r', USE_SIO_PORTID);
+	}
+	scif_pol_putc(c, USE_SIO_PORTID);
+}
+
+/*
+ *  LEDã®ç¹ç¯ï¼æ¶ç¯
+ */
+void
+gr_peach_set_led(uint_t led, uint_t set)
+{
+	rza1_config_port(RZA1_PORT_P(6), led, set);
+}
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_kernel_impl.h
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_kernel_impl.h	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_kernel_impl.h	(revision 307)
@@ -0,0 +1,112 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
+ *                              Toyohashi Univ. of Technology, JAPAN
+ *  Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  $Id: target_kernel_impl.h 720 2016-04-01 22:16:17Z ertl-hiro $
+ */
+
+/*
+ *		ã«ã¼ãã«ã®ã¿ã¼ã²ããä¾å­é¨ã«é¢ããå®ç¾©ï¼GR-PEACHç¨ï¼
+ *
+ *  ã«ã¼ãã«ã®ã¿ã¼ã²ããä¾å­é¨ã®ããããã¡ã¤ã«ï¼kernel_impl.hã®ã¿ã¼ã²ã
+ *  ãä¾å­é¨ã®ä½ç½®ä»ãã¨ãªãï¼
+ */
+
+#ifndef TOPPERS_TARGET_KERNEL_IMPL_H
+#define TOPPERS_TARGET_KERNEL_IMPL_H
+
+/*
+ *  ã¿ã¼ã²ããã®ãã¼ãã¦ã§ã¢è³æºã®å®ç¾©
+ */
+#include "gr_peach.h"
+
+/*
+ *  ãã¬ã¼ã¹ã­ã°ã«é¢ããè¨­å®
+ */
+#ifdef TOPPERS_ENABLE_TRACE
+#include "arch/tracelog/trace_log.h"
+#endif /* TOPPERS_ENABLE_TRACE */
+
+/*
+ *  ããã©ã«ãã®éã¿ã¹ã¯ã³ã³ãã­ã¹ãç¨ã®ã¹ã¿ãã¯é åã®å®ç¾©
+ */
+#define DEFAULT_ISTKSZ  0x2000U		/* 8KB */
+
+/*
+ *  å¾®å°æéå¾
+ã¡ã®ããã®å®ç¾©ï¼æ¬æ¥ã¯SILã®ã¿ã¼ã²ããä¾å­é¨ï¼
+ */
+#define SIL_DLY_TIM1    352
+#define SIL_DLY_TIM2    200
+
+/*
+ *  ãããä¾å­é¨ï¼RZ/A1ç¨ï¼
+ */
+#include "chip_kernel_impl.h"
+
+#ifndef TOPPERS_MACRO_ONLY
+
+/*
+ *  ã¿ã¼ã²ããã·ã¹ãã ä¾å­ã®åæå
+ */
+extern void target_initialize(void);
+
+/*
+ *  ã¿ã¼ã²ããã·ã¹ãã ã®çµäº
+ *
+ *  ã·ã¹ãã ãçµäºããæã«ä½¿ãï¼
+ */
+extern void target_exit(void) NoReturn;
+
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_TARGET_KERNEL_IMPL_H */
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_rename.def
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_rename.def	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_rename.def	(revision 307)
@@ -0,0 +1,13 @@
+# target_kernel_impl.c
+target_initialize
+target_exit
+
+# tTraceLog.c
+log_dsp_enter
+log_dsp_leave
+log_inh_enter
+log_inh_leave
+log_exc_enter
+log_exc_leave
+
+INCLUDE "chip"
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_rename.h
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_rename.h	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_rename.h	(revision 307)
@@ -0,0 +1,25 @@
+/* This file is generated from target_rename.def by genrename. */
+
+#ifndef TOPPERS_TARGET_RENAME_H
+#define TOPPERS_TARGET_RENAME_H
+
+/*
+ *  target_kernel_impl.c
+ */
+#define target_initialize			_kernel_target_initialize
+#define target_exit					_kernel_target_exit
+
+/*
+ *  tTraceLog.c
+ */
+#define log_dsp_enter				_kernel_log_dsp_enter
+#define log_dsp_leave				_kernel_log_dsp_leave
+#define log_inh_enter				_kernel_log_inh_enter
+#define log_inh_leave				_kernel_log_inh_leave
+#define log_exc_enter				_kernel_log_exc_enter
+#define log_exc_leave				_kernel_log_exc_leave
+
+
+#include "chip_rename.h"
+
+#endif /* TOPPERS_TARGET_RENAME_H */
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_serial.cfg
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_serial.cfg	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_serial.cfg	(revision 307)
@@ -0,0 +1,15 @@
+/*
+ *  @(#) $Id: target_serial.cfg 2758 2016-03-10 15:15:26Z ertl-honda $
+ */
+
+/*
+ *  SIOãã©ã¤ãï¼GR-PEACHç¨ï¼ã®ã³ã³ãã£ã®ã¥ã¬ã¼ã·ã§ã³ãã¡ã¤ã«
+ */
+
+#include "chip_serial.h"
+ATT_INI({ TA_NULL, 0, sio_initialize });
+
+CRE_ISR(ISR_SIO_RXI, { TA_NULL, 3, INTNO_SCIF_RXI_3, sio_isr_rxi, 1 });
+CFG_INT(INTNO_SCIF_RXI_3, { INTATR_SIO_3, INTPRI_SIO_3 });
+CRE_ISR(ISR_SIO_TXI, { TA_NULL, 3, INTNO_SCIF_TXI_3, sio_isr_txi, 1 });
+CFG_INT(INTNO_SCIF_TXI_3, { INTATR_SIO_3, INTPRI_SIO_3 });
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_serial.h
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_serial.h	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_serial.h	(revision 307)
@@ -0,0 +1,68 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2007 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  @(#) $Id: target_serial.h 2758 2016-03-10 15:15:26Z ertl-honda $
+ */
+
+/*
+ *  SIOãã©ã¤ãï¼GR-PEACHç¨ï¼
+ */
+
+#ifndef TOPPERS_TARGET_SERIAL_H
+#define TOPPERS_TARGET_SERIAL_H
+
+/*
+ *  ãããä¾å­ã¢ã¸ã¥ã¼ã«ï¼RZ/A1ç¨ï¼
+ */
+#include "chip_serial.h"
+
+#endif /* TOPPERS_TARGET_SERIAL_H */
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_sil.h
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_sil.h	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_sil.h	(revision 307)
@@ -0,0 +1,79 @@
+/*
+ *  TOPPERS Software
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *
+ *  Copyright (C) 2007-2015 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  $Id: target_sil.h 720 2016-04-01 22:16:17Z ertl-hiro $
+ */
+
+/*
+ *		sil.hã®ãããä¾å­é¨ï¼GR-PEACHç¨ï¼
+ *
+ *  ãã®ããããã¡ã¤ã«ã¯ï¼sil.hããã¤ã³ã¯ã«ã¼ããããï¼ä»ã®ãã¡ã¤ã«ãã
+ *  ç´æ¥ã¤ã³ã¯ã«ã¼ããããã¨ã¯ãªãï¼ãã®ãã¡ã¤ã«ãã¤ã³ã¯ã«ã¼ãããåã«ï¼
+ *  t_stddef.hãã¤ã³ã¯ã«ã¼ããããã®ã§ï¼ããã«ä¾å­ãã¦ãããï¼
+ */
+
+#ifndef TOPPERS_TARGET_SIL_H
+#define TOPPERS_TARGET_SIL_H
+
+/*
+ *  ãã­ã»ããµã®ã¨ã³ãã£ã¢ã³
+ */
+#define SIL_ENDIAN_LITTLE
+
+/*
+ *  ã³ã¢ã§å
+±éãªå®ç¾©ï¼ãããä¾å­é¨ã¯é£ã°ãï¼
+ */
+#ifndef TECSGEN
+#include "core_sil.h"
+#endif /* TECSGEN */
+
+#endif /* TOPPERS_TARGET_SIL_H */
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_stddef.h
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_stddef.h	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_stddef.h	(revision 307)
@@ -0,0 +1,106 @@
+/*
+ *  TOPPERS Software
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ * 
+ *  Copyright (C) 2007-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  $Id: target_stddef.h 720 2016-04-01 22:16:17Z ertl-hiro $
+ */
+
+/*
+ *		t_stddef.hã®ã¿ã¼ã²ããä¾å­é¨ï¼GR-PEACHç¨ï¼
+ *
+ *  ãã®ããããã¡ã¤ã«ã¯ï¼t_stddef.hã®å
+é ­ã§ã¤ã³ã¯ã«ã¼ããããï¼ä»ã®ãã¡
+ *  ã¤ã«ããã¯ç´æ¥ã¤ã³ã¯ã«ã¼ããããã¨ã¯ãªãï¼ä»ã®ããããã¡ã¤ã«ã«å
+ç«ã£
+ *  ã¦å¦çãããããï¼ä»ã®ããããã¡ã¤ã«ã«ä¾å­ãã¦ã¯ãªããªãï¼
+ */
+
+#ifndef TOPPERS_TARGET_STDDEF_H
+#define TOPPERS_TARGET_STDDEF_H
+
+/*
+ *  ã¿ã¼ã²ãããè­å¥ããããã®ãã¯ã­ã®å®ç¾©
+ */
+#define TOPPERS_GR_PEACH				/* ã·ã¹ãã ç¥ç§° */
+#define TOPPERS_RZA1H					/* RZ/A1H */
+
+/*
+ *  éçºç°å¢ã§å
+±éãªå®ç¾©
+ */
+#ifndef TOPPERS_MACRO_ONLY
+#include <stdint.h>
+#endif /* TOPPERS_MACRO_ONLY */
+
+#define TOPPERS_STDFLOAT_TYPE1
+#include "tool_stddef.h"
+
+/*
+ *  ãããä¾å­ã§å
+±éãªå®ç¾©
+ */
+#include "chip_stddef.h"
+
+/*
+ *  ã¢ãµã¼ã·ã§ã³ã®å¤±ææã®å®è¡ä¸­æ­å¦ç
+ */
+#ifndef TOPPERS_MACRO_ONLY
+
+Inline void
+TOPPERS_assert_abort(void)
+{
+	/*
+	 *  bkptå½ä»¤ã«ãããããã¬ã«å¶å¾¡ãç§»ãï¼ãã©ã¡ã¼ã¿ãä½ãè¯ããæªæ¤è¨ï¼
+	 */
+	Asm("bkpt #0");
+}
+
+#endif /* TOPPERS_MACRO_ONLY */
+#endif /* TOPPERS_TARGET_STDDEF_H */
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_support.S
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_support.S	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_support.S	(revision 307)
@@ -0,0 +1,154 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ * 
+ *  Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
+ *                              Toyohashi Univ. of Technology, JAPAN
+ *  Copyright (C) 2006-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ * 
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ * 
+ *  $Id: target_support.S 720 2016-04-01 22:16:17Z ertl-hiro $
+ */
+
+/*
+ *		ã«ã¼ãã«ã®ã¿ã¼ã²ããä¾å­é¨ã®ã¢ã»ã³ããªè¨èªé¨ï¼GR-PEACHç¨ï¼
+ */
+
+#define TOPPERS_MACRO_ONLY
+#define TOPPERS_ASM_MACRO
+#define UINT_C(val)			(val)		/* uint_tåã®å®æ°ãä½ããã¯ã­ */
+#define ULONG_C(val)		(val)		/* ulong_tåã®å®æ°ãä½ããã¯ã­ */
+#define CAST(type, val)		(val)		/* åã­ã£ã¹ããè¡ããã¯ã­ */
+#include "kernel_impl.h"
+#include "pl310.h"
+#include "core_asm.inc"
+
+/*
+ *  ä½ã¬ãã«ã®ã¿ã¼ã²ããã·ã¹ãã ä¾å­ã®åæå
+ *
+ *  ã¹ã¿ã¼ãã¢ããã¢ã¸ã¥ã¼ã«ã®ä¸­ã§ï¼ã¡ã¢ãªåæåã®åã«å¼ã³åºãããï¼
+ */
+	ATEXT
+	AALIGN(2)
+	AGLOBAL(hardware_init_hook)
+ALABEL(hardware_init_hook)
+	/*
+	 *  å
+èµRAMã¸ã®ã¢ã¯ã»ã¹ï¼æ¸è¾¼ã¿è¨±å¯
+	 */
+	ldr		r2, =(RZA1_SYSCR3)
+	ldr		r0, =0x0f
+	strb	r0, [r2]		/* å
+èµä¿æç¨RAMã®ãã¼ã¸0ã3ã¸ã®æ¸è¾¼ã¿è¨±å¯ */
+	ldrb	r0, [r2]		/* ããã¼ãªã¼ã */
+
+	/* 
+	 *  ã¯ã­ãã¯é¢ä¿ã®åæå
+	 *
+	 *  ä»¥ä¸ã®è¨­å®ã¨ããï¼
+	 *		å
+¥åå¨æ³¢æ°ï¼13.33MHzï¼CKIOï¼66.67MHz
+	 *		CPUã¯ã­ãã¯ï¼IÏï¼ï¼400.00MHz
+	 *		ç»åå¦çã¯ã­ãã¯ï¼GÏï¼ï¼266.67MHz
+	 *		å
+é¨ãã¹ã¯ã­ãã¯ï¼BÏï¼ï¼133.33MHz
+	 *		å¨è¾ºã¯ã­ãã¯1ï¼P1Ïï¼ï¼66.67MHz
+	 *		å¨è¾ºã¯ã­ãã¯0ï¼P0Ïï¼ï¼33.33MHz
+	 */
+	
+	/*
+	 *  L2ã­ã£ãã·ã¥ã®ã¹ã¿ã³ãã¤ã¢ã¼ããã¤ãã¼ãã«ï¼å¨æ³¢æ°å¤æ´æã«å¿
+è¦ï¼
+	 */
+	ldr		r2, =(PL310_POWER_CTRL)
+	ldr		r0, [r2]
+	orr		r0, r0, #0x01	/* ã¹ã¿ã³ãã¤ã¢ã¼ãã« */
+	str		r0, [r2]
+
+ALABEL(set_frqcr)
+	/*
+	 *  CPUã¯ã­ãã¯ããÃ1åãã«ï¼400MHzï¼
+	 */
+	ldr		r2, =(RZA1_FRQCR)
+	ldr		r0, =0x1035
+	strh	r0, [r2]
+	ldrh	r1, [r2]
+	cmp		r0, r1
+	bne		set_frqcr
+
+#ifdef TOPPERS_RZA1H
+	/* 
+	 *  ç»åå¦çã¯ã­ãã¯ããÃ2/3ãã«ï¼266.67MHzï¼
+	 */
+ALABEL(set_frqcr2)
+	ldr		r2, =(RZA1_FRQCR2)
+	ldr		r0, =0x0001
+	strh	r0, [r2]
+	ldrh	r1, [r2]
+	cmp		r0, r1
+	bne		set_frqcr2
+#endif /* TOPPERS_RZA1H */
+
+	/* 
+	 *  ã½ããã¦ã§ã¢ã¹ã¿ã³ãã¤å¾©å¸°ä¸­ã§ãªããªãã¾ã§å¾
+ã¤
+	 */
+wait_isbusy:
+	ldr		r2, =(RZA1_CPUSTS)
+	ldrb	r0, [r2]
+	tst		r0, #0x10
+	bne		wait_isbusy
+
+	/*
+	 *  L2ã­ã£ãã·ã¥ã®ã¹ã¿ã³ãã¤ã¢ã¼ãããã£ã¹ã¨ã¼ãã«
+	 */
+	ldr		r2, =(PL310_POWER_CTRL)
+	ldr		r0, [r2]
+	bfc		r0, #0, #1		/* ã¹ã¿ã³ãã¤ã¢ã¼ãããã£ã¹ã¨ã¼ãã« */
+	str		r0, [r2]
+	bx		lr
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_syssvc.h
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_syssvc.h	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_syssvc.h	(revision 307)
@@ -0,0 +1,121 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
+ *                              Toyohashi Univ. of Technology, JAPAN
+ *  Copyright (C) 2005-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  $Id: target_syssvc.h 720 2016-04-01 22:16:17Z ertl-hiro $
+ */
+
+/*
+ *		ã·ã¹ãã ãµã¼ãã¹ã®ã¿ã¼ã²ããä¾å­é¨ï¼GR-PEACHç¨ï¼
+ *
+ *  ã·ã¹ãã ãµã¼ãã¹ã®ã¿ã¼ã²ããä¾å­é¨ã®ããããã¡ã¤ã«ï¼ã·ã¹ãã ãµã¼ã
+ *  ã¹ã®ã¿ã¼ã²ããä¾å­ã®è¨­å®ã¯ï¼ã§ããéãã³ã³ãã¼ãã³ãè¨è¿°ãã¡ã¤ã«ã§
+ *  è¨è¿°ãï¼ãã®ãã¡ã¤ã«ã«è¨è¿°ãããã®ã¯æå°éã¨ããï¼
+ */
+
+#ifndef TOPPERS_TARGET_SYSSVC_H
+#define TOPPERS_TARGET_SYSSVC_H
+
+
+#include "gr_peach.h"
+
+/*
+ *  ãã¬ã¼ã¹ã­ã°ã«é¢ããè¨­å®
+ */
+#ifdef TOPPERS_ENABLE_TRACE
+#include "logtrace/trace_config.h"
+#endif /* TOPPERS_ENABLE_TRACE */
+
+/*
+ *  èµ·åã¡ãã»ã¼ã¸ã®ã¿ã¼ã²ããã·ã¹ãã å
+ */
+#define TARGET_NAME    "GR-PEACH(RZA1H Cortex-A9)"
+
+/*
+ *  ã·ã¹ãã ã­ã°ã®ä½ã¬ãã«åºåã®ããã®æå­åºå
+ *
+ *  ã¿ã¼ã²ããä¾å­ã®æ¹æ³ã§ï¼æå­cãè¡¨ç¤º/åºå/ä¿å­ããï¼
+ */
+extern void	target_fput_log(char c);
+
+/*
+ *  ã­ã°ã¿ã¹ã¯ã§ä½¿ç¨ãããã¼ã
+ */
+#define LOGTASK_PORTID  USE_SIO_PORTID
+
+/*
+ *  ãã¼ã¬ã¼ãè¨­å®
+ */
+#define UART1_BPS_SETTING  115200
+#define UART2_BPS_SETTING  115200
+#define UART3_BPS_SETTING  115200
+#define UART4_BPS_SETTING  115200
+#define UART5_BPS_SETTING  115200
+#define UART6_BPS_SETTING  115200
+#define UART7_BPS_SETTING  115200
+#define UART8_BPS_SETTING  115200
+
+/*
+ *  ãµãã¼ãããã·ãªã¢ã«ãã¼ãã®æ°
+ */
+#ifndef TNUM_PORT
+#define TNUM_PORT       4
+#endif /* TNUM_PORT */
+
+/*
+ *  ã·ã¹ãã ã­ã°ã¿ã¹ã¯é¢é£ã®å®æ°ã®å®ç¾©
+ *
+ *  ããã©ã«ãå¤ã®éãï¼
+ */
+
+#endif /* TOPPERS_TARGET_SYSSVC_H */
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_test.h
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_test.h	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_test.h	(revision 307)
@@ -0,0 +1,89 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2007-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  $Id: target_test.h 736 2016-04-04 23:50:03Z ertl-hiro $
+ */
+
+/*
+ *		ãã¹ããã­ã°ã©ã ã®ã¿ã¼ã²ããä¾å­å®ç¾©ï¼GR-PEACHç¨ï¼
+ */
+
+#ifndef TOPPERS_TARGET_TEST_H
+#define TOPPERS_TARGET_TEST_H
+
+#include "rza1.h"
+
+/*
+ *  ãµã³ãã«ãã­ã°ã©ã ã§ä½¿ç¨ããå²è¾¼ã¿ã«é¢ããå®ç¾©
+ */
+#define INTNO1				INTNO_IRQ5
+#define INTNO1_INTATR		TA_ENAINT|TA_NEGEDGE
+#define INTNO1_INTPRI		-15
+#define intno1_clear()		rza1_clear_irq(INTNO_IRQ5)
+
+/*
+ *  ãã¹ããã­ã°ã©ã ã§ä½¿ç¨ããæéãã©ã¡ã¼ã¿ã«é¢ããå®ç¾©
+ */
+#define TEST_TIME_CP	4000U		/* 115200bpsãæ³å® */
+
+/*
+ *  ãµã³ãã«ãã­ã°ã©ã ã§ä½¿ç¨ãããã¼ã
+ */
+#define TASK_PORTID    USE_SIO_PORTID
+
+/*
+ *  ã³ã¢ã§å
+±éãªå®ç¾©ï¼ãããä¾å­é¨ã¯é£ã°ãï¼
+ */
+#include "core_test.h"
+
+#endif /* TOPPERS_TARGET_TEST_H */
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_timer.cfg
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_timer.cfg	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_timer.cfg	(revision 307)
@@ -0,0 +1,12 @@
+/*
+ *		ã¿ã¤ããã©ã¤ãã®ã³ã³ãã£ã®ã¥ã¬ã¼ã·ã§ã³ãã¡ã¤ã«
+ *
+ *  $Id: target_timer.cfg 720 2016-04-01 22:16:17Z ertl-hiro $
+ */
+
+#include "target_timer.h"
+
+/*
+ *  ãããä¾å­é¨ï¼RZ/A1ç¨ï¼
+ */
+INCLUDE("chip_timer.cfg");
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_timer.h
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_timer.h	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_timer.h	(revision 307)
@@ -0,0 +1,69 @@
+/*
+ *  TOPPERS/ASP Kernel
+ *      Toyohashi Open Platform for Embedded Real-Time Systems/
+ *      Advanced Standard Profile Kernel
+ *
+ *  Copyright (C) 2007-2016 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *
+ *  ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ï½(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ *  ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ *  å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ *  (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+ *      æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+ *      ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ *  (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+ *      è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+ *      ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *  (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+ *      ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+ *      ã¨ï¼
+ *    (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+ *        ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ *    (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+ *        å ±åãããã¨ï¼
+ *  (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+ *      å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+ *      ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+ *      ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+ *      å
+è²¬ãããã¨ï¼
+ *
+ *  æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ *  ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ *  ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ *  ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ *  ã®è²¬ä»»ãè² ããªãï¼
+ *
+ *  $Id: target_timer.h 720 2016-04-01 22:16:17Z ertl-hiro $
+ */
+
+/*
+ *		ã¿ã¤ããã©ã¤ãï¼GR-PEACHç¨ï¼
+ */
+
+#ifndef TOPPERS_TARGET_TIMER_H
+#define TOPPERS_TARGET_TIMER_H
+
+/*
+ *  ãããã§å
+±éãªå®ç¾©ï¼RZ/A1ç¨ï¼
+ */
+#include "chip_timer.h"
+
+#endif /* TOPPERS_TARGET_TIMER_H */
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_unrename.h
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_unrename.h	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_unrename.h	(revision 307)
@@ -0,0 +1,26 @@
+/* This file is generated from target_rename.def by genrename. */
+
+/* This file is included only when target_rename.h has been included. */
+#ifdef TOPPERS_TARGET_RENAME_H
+#undef TOPPERS_TARGET_RENAME_H
+
+/*
+ *  target_kernel_impl.c
+ */
+#undef target_initialize
+#undef target_exit
+
+/*
+ *  tTraceLog.c
+ */
+#undef log_dsp_enter
+#undef log_dsp_leave
+#undef log_inh_enter
+#undef log_inh_leave
+#undef log_exc_enter
+#undef log_exc_leave
+
+
+#include "chip_unrename.h"
+
+#endif /* TOPPERS_TARGET_RENAME_H */
Index: /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_user.txt
===================================================================
--- /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_user.txt	(revision 307)
+++ /asp3_wo_tecs/trunk/target/gr_peach_gcc/target_user.txt	(revision 307)
@@ -0,0 +1,378 @@
+
+		TOPPERS/ASP3ã«ã¼ãã«
+		GR-PEACHä¾å­é¨ ã¦ã¼ã¶ã¼ãºããã¥ã¢ã«
+
+		å¯¾å¿ãã¼ã¸ã§ã³: Release 3.1
+		æçµæ´æ°: 2016å¹´4æ2æ¥
+
+ãã®ãã­ã¥ã¡ã³ãã¯ï¼TOPPERS/ASP3ã«ã¼ãã«ã®GR-PEACHã¿ã¼ã²ããä¾å­é¨ãä½¿
+ç¨ããããã«å¿
+è¦ãªäºé 
+ãèª¬æãããã®ã§ããï¼
+
+----------------------------------------------------------------------
+ TOPPERS/ASP Kernel
+     Toyohashi Open Platform for Embedded Real-Time Systems/
+     Advanced Standard Profile Kernel
+
+ Copyright (C) 2008-2016 by Embedded and Real-Time Systems Laboratory
+             Graduate School of Information Science, Nagoya Univ., JAPAN
+ 
+ ä¸è¨èä½æ¨©è
+ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
+ ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ãä½¿ç¨ã»è¤è£½ã»æ¹
+ å¤ã»åé
+å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
+ (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
+     æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
+     ã¹ã³ã¼ãä¸­ã«å«ã¾ãã¦ãããã¨ï¼
+ (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+     ç¨ã§ããå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨
+     è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
+     ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+ (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
+     ç¨ã§ããªãå½¢ã§åé
+å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
+     ã¨ï¼
+   (a) åé
+å¸ã«ä¼´ããã­ã¥ã¡ã³ãï¼å©ç¨è
+ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
+       ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
+   (b) åé
+å¸ã®å½¢æ
+ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSãã­ã¸ã§ã¯ãã«
+       å ±åãããã¨ï¼
+ (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
+     å®³ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ããå
+è²¬ãããã¨ï¼
+     ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
+     ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
+ããã³TOPPERSãã­ã¸ã§ã¯ãã
+     å
+è²¬ãããã¨ï¼
+ 
+ æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
+ã
+ ãã³TOPPERSãã­ã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
+ ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
+ ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæå®³ã«é¢ãã¦ãï¼ã
+ ã®è²¬ä»»ãè² ããªãï¼
+ 
+ $Id: target_user.txt 752 2016-05-14 15:06:22Z ertl-hiro $
+----------------------------------------------------------------------
+
+âã©ã¤ã»ã³ã¹ã«é¢ããæ³¨æäºé 
+
+
+GR-PEACHã¿ã¼ã²ããä¾å­é¨ã«ã¯ï¼ROMå®è¡ã®ããã®ãã¼ãã­ã¼ãï¼sf_boot.cï¼
+ãå«ãã§ãããï¼ãã®ã½ããã¦ã§ã¢ã¯ã«ããµã¹ã¨ã¬ã¯ãã­ãã¯ã¹ãéçºããã
+ã®ã§ããï¼ã©ã¤ã»ã³ã¹æ¡ä»¶ãã«ããµã¹ã¨ã¬ã¯ãã­ãã¯ã¹ç¬èªã®ãã®ã§ããï¼
+TOPPERSã©ã¤ã»ã³ã¹ã§ãªãããæ³¨æãããã¨ï¼
+
+âç®æ¬¡
+
+
+ï¼ï¼GR-PEACHã¿ã¼ã²ããä¾å­é¨ã®æ¦è¦
+
+GR-PEACHã¿ã¼ã²ããä¾å­é¨ï¼GNUéçºç°å¢åãï¼ã¯ï¼TOPPERS/ASP3ã«ã¼ãã«ãï¼
+ã«ããµã¹ RZ/A1Hãæ­è¼ããGR-PEACHãã¼ãä¸ã§åä½ãããç°å¢ãæ§ç¯ãããã
+ã®ãã®ã§ããï¼
+
+1.1 å¯¾å¿ããã¿ã¼ã²ããã·ã¹ãã ã¨ã¿ã¼ã²ããç¥ç§°
+
+GR-PEACHã¿ã¼ã²ããä¾å­é¨ï¼GNUéçºç°å¢åãï¼ã®åä½ç¢ºèªã¯ï¼å®æ©ãç¨ãã¦è¡ã£
+ã¦ããï¼GR-PEACHã«é¢ããæ
+å ±ã¯ï¼ä»¥ä¸ã®ã¦ã§ããµã¤ãã«ããï¼
+
+	http://gadget.renesas.com/ja/product/peach.html
+
+ãã­ã°ã©ã ããã©ãã·ã¥ã¡ã¢ãªã«æ¸ãè¾¼ãã§å®è¡ããæ¹æ³ï¼ROMå®è¡ï¼ã¨ï¼ããã
+ã¬ã«ããRAMã«ãã¦ã³ã­ã¼ããã¦å®è¡ããæ¹æ³ï¼RAMå®è¡ï¼ããµãã¼ããã¦ããï¼
+
+ã¿ã¼ã²ããç¥ç§°ç­ã¯æ¬¡ã®éãï¼
+
+	ã¿ã¼ã²ããç¥ç§°ï¼gr_peach_gcc
+	ã·ã¹ãã ç¥ç§°ï¼gr_peach
+	éçºç°å¢ç¥ç§°ï¼gcc
+
+1.2 ã¿ã¼ã²ããä¾å­é¨ã®æ§æ
+
+GR-PEACHã¿ã¼ã²ããä¾å­é¨ï¼GNUéçºç°å¢åãï¼ã¯ï¼ãããä¾å­é¨ã¨ãã¦RZ/A1
+ãããä¾å­é¨ï¼GNUéçºç°å¢åãï¼ãï¼ã³ã¢ä¾å­é¨ã¨ãã¦ARMã³ã¢ä¾å­é¨ï¼GNUé
+çºç°å¢åãï¼ãä½¿ç¨ãã¦ããï¼
+
+ã¿ã¼ã²ããä¾å­é¨ï¼targetãã£ã¬ã¯ããªï¼ããã³ã¿ã¼ã²ããä¾å­é¨ã®å
+±éé¨
+ï¼archãã£ã¬ã¯ããªï¼ã®ãã£ã¬ã¯ããªã¯æ¬¡ã®éãï¼
+
+	target/
+		gr_peach_gcc/		GR-PEACHã¿ã¼ã²ããä¾å­é¨
+
+	arch/
+		arm_gcc/common/		ARMã³ã¢ä¾å­é¨
+		arm_gcc/rza1/		RZ/A1ãããä¾å­é¨
+		arm_gcc/doc/		ARMä¾å­é¨ã«é¢ãããã­ã¥ã¡ã³ã
+		gcc/				GCCéçºç°å¢ä¾å­é¨
+		tracelog/			ãã¬ã¼ã¹ã­ã°è¨é²ã®ãµã³ãã«ã³ã¼ã
+
+1.3 ä¾å­ãã¦ããåå¥ããã±ã¼ã¸ã®ãã¼ã¸ã§ã³çªå·
+
+GR-PEACHã¿ã¼ã²ããä¾å­é¨ï¼ãã¼ã¸ã§ã³ 3.1.0ï¼ã®åå¥ããã±ã¼ã¸ãä¾å­ãã¦
+ããåå¥ããã±ã¼ã¸ã¨ï¼åä½ç¢ºèªãè¡ã£ããã¼ã¸ã§ã³ã¯æ¬¡ã®éãï¼
+
+	åå¥ããã±ã¼ã¸ã®åç§°	ãã¼ã¸ã§ã³	åå¥ããã±ã¼ã¸ãã¡ã¤ã«å
+	------------------------------------------------------------------
+	ã¿ã¼ã²ããéä¾å­é¨		3.1.0		asp3-3.1.0.tar.gz
+
+1.4 éçºç°å¢ï¼ãããã°ç°å¢ã¨åä½ç¢ºèªæ¡ä»¶
+
+éçºç°å¢ã¨ãã¦ï¼ä»¥ä¸ã®URLããããªãã«ãçããã¦ã³ã­ã¼ããããã¨ãã§ãã
+GCC ARM Embeddedãç¨ãã¦ããï¼
+
+	https://launchpad.net/gcc-arm-embedded/
+
+åä½ç¢ºèªãè¡ã£ããã¼ã¸ã§ã³ã¯æ¬¡ã®éãï¼
+
+	gcc: version 4.8.3 20140228
+	binutilsï¼objcopyï¼objdumpï¼ï¼2.23.2.20140228
+
+ãããã°ç°å¢ã¨ãã¦ï¼ãªã³ãã¼ãã®CMSIS-DAPããï¼OpenOCDãçµç±ãã¦ï¼GDBã
+ç¨ããç°å¢ã§åä½ç¢ºèªãè¡ã£ã¦ããï¼åä½ç¢ºèªãè¡ã£ããããã°ç°å¢ã®ãã¼ã¸ã§
+ã³ã¯æ¬¡ã®éãï¼
+
+	gdb: 7.6.0.20140228-cvs
+	openocd: 0.10.0-dev-00287-g85cec24
+
+å¤ããã¼ã¸ã§ã³ã®OpenOCDã§ã¯æ­£ããåä½ããªããã¨ãå ±åããã¦ããããï¼æ³¨
+æãå¿
+è¦ã§ããï¼
+
+GUIãã¼ã¹ã®éçºç°å¢ï¼ãããã°ç°å¢ã¨ãã¦ï¼Atollic TrueStudioãç¨ãããã¨
+ãã§ããï¼
+
+1.5 ã¡ã¢ãªããã
+
+ROMå®è¡ã®å ´åã¯ï¼ä»¥ä¸ã®ã¡ã¢ãªããããæ³å®ãã¦ããï¼
+
+	0x18000000 - 0x1fffffffï¼ã·ãªã¢ã«ãã©ãã·ã¥ã¡ã¢ãªï¼128MBï¼
+	0x20000000 - 0x209fffffï¼å
+èµSRAMï¼10MBï¼
+	0x3fe00000 - 0x3fffffffï¼I/Oé åï¼2MBï¼ï¼äºç´é åãå«ã
+	0xe8000000 - 0xffffffffï¼I/Oé åï¼384MBï¼ï¼äºç´é åãå«ã
+
+å
+èµSRAMé åã®å
+é ­ã®16KBã¯ï¼ãã¼ãã­ã¼ããç½®ãããã«ä½¿ç¨ããï¼
+
+RAMå®è¡ã®å ´åã¯ï¼ä»¥ä¸ã®ã¡ã¢ãªããããæ³å®ãã¦ããï¼
+
+	0x20000000 - 0x200fffffï¼å
+èµSRAMï¼1MBï¼â¦ ROMé åã¨ãã¦ä½¿ç¨
+	0x20100000 - 0x209fffffï¼å
+èµSRAMï¼9MBï¼
+	0x3fe00000 - 0x3fffffffï¼I/Oé åï¼2MBï¼ï¼äºç´é åãå«ã
+	0xe8000000 - 0xffffffffï¼I/Oé åï¼384MBï¼ï¼äºç´é åãå«ã
+
+ãã­ã°ã©ã ããã³å®æ°ãã¼ã¿é åã¯ï¼å
+èµSRAMé åã®å
+é ­ã®1MBã«ç½®ãæ³å®ã¨ã
+ã¦ï¼ï¼å®æ°ã§ãªãï¼ãã¼ã¿é åã¯ï¼ãã®å¾ã«é
+ç½®ããï¼
+
+ã¡ã¢ãªããããå¤æ´ããå ´åã«ã¯ï¼target_kernel_impl.cã¨gr_peach_rom.ld
+ï¼ã¾ãã¯ï¼pr_peach_ram.kdï¼ãä¿®æ­£ããå¿
+è¦ãããï¼
+
+
+ï¼ï¼ã¿ã¼ã²ããå®ç¾©äºé 
+ã®è¦å®
+
+GR-PEACHã¿ã¼ã²ããä¾å­é¨ã¯ï¼ARMã³ã¢ä¾å­é¨ã¨RZ/A1ãããä¾å­é¨ãç¨ãã¦å®
+è£
+ããã¦ããï¼ARMã³ã¢ä¾å­é¨ããã³RZ/A1ãããä¾å­é¨ã«ãããã¿ã¼ã²ããå®
+ç¾©äºé 
+ã®è¦å®ã«ã¤ãã¦ã¯ï¼ãARMä¾å­é¨ ã¦ã¼ã¶ã¼ãºããã¥ã¢ã«ããåç
+§ããã
+ã¨ï¼ãããã®è¦å®ä»¥å¤ã«ï¼GR-PEACHã¿ã¼ã²ããå®ç¾©ã®äºé 
+ã¯ãªãï¼
+
+
+ï¼ï¼ãã©ã¤ãé¢é£ã®æ
+å ±
+
+3.1 ã¿ã¤ããã©ã¤ã
+
+é«åè§£è½ã¿ã¤ãã¯ï¼RZ/A1Hãæã¤2ãã£ã³ãã«ã®OSã¿ã¤ãã®å
+ã®1ã¤ãç¨ãã¦å®
+ç¾ãã¦ããï¼ã¾ãï¼ãã1ã¤ã®OSã¿ã¤ããç¨ãã¦ï¼ãªã¼ãã©ã³ã¿ã¤ããå®ç¾ãã¦
+ããï¼
+
+3.2 ã·ãªã¢ã«ã¤ã³ã¿ãã§ã¼ã¹ãã©ã¤ã
+
+ã·ãªã¢ã«ã¤ã³ã¿ãã§ã¼ã¹ãã©ã¤ãã¯ï¼RZ/A1Hãæã¤8ãã¼ãã®FIFOå
+èµã·ãªã¢ã«
+ã³ãã¥ãã±ã¼ã·ã§ã³ã¤ã³ã¿ãã§ã¼ã¹ããµãã¼ããã¦ããï¼
+
+USBçµç±ã§ãã¹ãã¨æ¥ç¶ã§ãããã¼ãã¯ï¼SCIFã®ãã£ãã«2ï¼ãã£ãã«çªå·ã¯0ã
+ãå§ã¾ãã®ã§ï¼ãã¼ã3ã«ç¸å½ï¼ã§ããï¼ä¸æ¹ï¼sample1.cdlã§ã¯ï¼ã­ã°ã¿ã¹ã¯
+ããã³ãµã³ãã«ãã­ã°ã©ã ãä½¿ããã¼ãããã¼ã1ã¨ãªã£ã¦ããããï¼ãã¼ã1
+ã¨ãã¼ã3ãå
+¥ãæãã¦ããï¼ããªãã¡ï¼ã·ãªã¢ã«ã¤ã³ã¿ãã§ã¼ã¹ãã©ã¤ãã®ãã¼
+ã1ãSCIFã®ãã£ãã«2ï¼ãã¼ã2ããã£ãã«1ï¼ãã¼ã3ããã£ãã«0ï¼ãã¼ã4ã
+ãã£ãã«3ï¼â¦ã«å¯¾å¿ãã¦ããï¼
+
+	ãã¼ã¬ã¼ãï¼115200bps
+	ãã¼ã¿ï¼8ããã
+	ããªãã£ï¼ãªã
+	ã¹ããããããï¼1ããã
+	ãã­ã¼å¶å¾¡ï¼ãªã
+
+ãã®å¯¾å¿ãå¤æ´ããã«ã¯ï¼tSIOPortGRPeach.cdlãä¿®æ­£ããå¿
+è¦ãããï¼
+
+3.3 ã·ã¹ãã ã­ã°ã®ä½ã¬ãã«åºå
+
+ã·ã¹ãã ã­ã°ã®ä½ã¬ãã«åºåã¯ï¼ã·ãªã¢ã«ã¤ã³ã¿ãã§ã¼ã¹ãã©ã¤ãã®ãã¼ã1ã¨
+åããã£ãã«ï¼ããªãã¡ï¼SCIFã®ãã£ãã«2ï¼ã«å¯¾ãã¦ï¼ãã¼ãªã³ã°ã«ããæå­
+ãåºåããæ¹æ³ã§å®ç¾ãã¦ããï¼
+
+ç¨ãããã¼ããå¤æ´ããå ´åã«ã¯ï¼target.cdlãä¿®æ­£ããå¿
+è¦ãããï¼
+
+
+ï¼ï¼ã·ã¹ãã æ§ç¯æé ã¨å®è¡æé 
+
+GR-PEACHç¨ã®ASP3ã«ã¼ãã«ããã³ãµã³ãã«ãã­ã°ã©ã ãæ§ç¯ããæé ã¯ï¼åºæ¬
+çã«ã¯ï¼ãTOPPERS/ASP3ã«ã¼ãã« ã¦ã¼ã¶ã¼ãºããã¥ã¢ã«ãã®ãï¼ï¼ã¯ã¤ãã¯ã¹
+ã¿ã¼ãã¬ã¤ããã®ç« ã«è¨è¿°ããã¦ããéãã§ãããï¼ROMå®è¡ãRAMå®è¡ãã«ãã£
+ã¦ï¼æ§ç¯æé ã¨å®è¡æé ã«éããããï¼
+
+4.1 ROMå®è¡ã®å ´åã®æ§ç¯æé ã¨å®è¡æé 
+
+ã«ã¼ãã«ã®æ§ç¯åã«ï¼GR-PEACHã¿ã¼ã²ããä¾å­é¨ã®Makefile.targetãç·¨éãï¼
+ä»¥ä¸ã®è¡ãæå¹ã«ããï¼ã³ã¡ã³ãã¢ã¦ãããï¼ï¼
+
+	EXECUTE_ON = ROM
+
+ROMå®è¡ããå ´åã«ã¯ï¼ãã¤ããªå½¢å¼ãå¿
+è¦ã§ããããï¼ãµã³ãã«ãã­ã°ã©ã ã®
+æ§ç¯å¾ã«ï¼ä»¥ä¸ã®ã³ãã³ããå®è¡ããï¼
+
+	% make asp.bin
+
+GR-PEACHã®USBãã¼ãã¨PCãæ¥ç¶ããã¨ï¼GR-PEACHããã©ã¤ãã¨ãã¦èªè­ããã
+ããï¼ãã®ãã©ã¤ãã«asp.binãæ¸ãè¾¼ããã¨ã§ï¼GR-PEACHã®ãã©ãã·ã¥ã¡ã¢ãª
+ã«ãã­ã°ã©ã ãæ¸ãè¾¼ã¾ããï¼
+
+æ¸ãè¾¼ã¿å¾ï¼ãªã»ãããã¿ã³ãæ¼ããã¨ã«ããï¼ãã­ã°ã©ã ã®å®è¡ãéå§ãã
+ãï¼
+
+4.2 RAMå®è¡ã®å ´åã®æ§ç¯æé ã¨å®è¡æé 
+
+ã«ã¼ãã«ã®æ§ç¯åã«ï¼GR-PEACHã¿ã¼ã²ããä¾å­é¨ã®Makefile.targetãç·¨éãï¼
+ä»¥ä¸ã®è¡ãæå¹ã«ããï¼ã³ã¡ã³ãã¢ã¦ãããï¼ï¼
+
+	EXECUTE_ON = RAM
+
+ä»¥ä¸ï¼ASP3ã«ã¼ãã«ãç½®ãããã£ã¬ã¯ããªã<SRCDIR>ï¼OpenOCDãã¤ã³ã¹ãã¼ã«
+ãããã£ã¬ã¯ããªã<OPENOCD_DIR>ã¨æ¸ãï¼openocdã®å®è¡ãã­ã°ã©ã ã¯ï¼å®è¡
+ãã¹ã«æå®ããããã£ã¬ã¯ããªã«ã³ãã¼ã¾ãã¯ã·ã³ããªãã¯ãªã³ã¯ãã¦ããï¼
+
+	% cd /usr/local/bin
+	% ln -s <OPENOCD_DIR>/bin/openocd .
+
+ã¾ãï¼GR-PEACHã¿ã¼ã²ããä¾å­é¨ã®ãã£ã¬ã¯ããªã«ããrenesas_rza1h_swd.cfg
+ãï¼<OPENOCD_DIR>/scripts/targetsã«ã³ãã¼ãã¦ããï¼
+
+æ¬¡ã«ï¼GR-PEACHã®USBãã¼ãã¨PCãæ¥ç¶ãï¼ä»¥ä¸ã®ã³ãã³ãã§openocdãèµ·åããï¼
+
+	% setenv OPENOCD_SCRIPTS <OPENOCD_DIR>/scripts
+	% openocd -f interface/cmsis-dap.cfg -f target/renesas_rza1h_swd.cfg
+
+ä»¥ä¸ã®ã³ãã³ãã§gdbãèµ·åãï¼aspãã­ã¼ãããå¾ï¼continueã³ãã³ãã§ãã­
+ã°ã©ã ã®å®è¡ãéå§ãããï¼
+
+	% arm-none-eabi-gdb asp -x <SRCDIR>/target/gr_peach_gcc/gdb_ram.ini
+	(gdb) continue
+
+<SRCDIR>/target/gr_peach_gcc/gdb_ram.iniãï¼ã«ã¬ã³ããã£ã¬ã¯ããªã®
+.gdbinitã«ã³ãã¼ãã¦ãããã¨ã§ï¼gdbã®èµ·åæ¯ã«ã¹ã¯ãªãããæå®ããå¿
+è¦ã
+ãªããªãï¼
+
+4.3 ãã©ã¤ãã®ã¤ã³ã¹ãã¼ã«
+
+GR-PEACHã®USBãã¼ãã¨PCãæ¥ç¶ãã¦ãï¼GR-PEACHãã·ãªã¢ã«ãã¼ãã¨ãã¦èªè­
+ãããªãå ´åã«ã¯ï¼USBã·ãªã¢ã«ãã©ã¤ããã¤ã³ã¹ãã¼ã«ããå¿
+è¦ãããï¼
+
+Windowsåãã®ãã©ã¤ãã¯ï¼ä»¥ä¸ã®URLã«ããï¼
+
+	https://developer.mbed.org/handbook/Windows-serial-configuration
+
+MacOS Xç¨ã®USBã·ãªã¢ã«ãã©ã¤ãã¯ï¼ä¾ãã°ï¼ä»¥ä¸ã®URLã«ãããã®ãä½¿ç¨ãã
+ãã¨ãã§ããï¼
+
+	http://www.ftdichip.com/Drivers/VCP.htm
+
+
+ï¼ï¼ãªãã¡ã¬ã³ã¹
+
+5.1 ãã£ã¬ã¯ããªæ§æã»ãã¡ã¤ã«æ§æ
+
+	target/gr_peach_gcc/
+		E_PACKAGE				ç°¡æããã±ã¼ã¸ã®ãã¡ã¤ã«ãªã¹ã
+		MANIFEST				åå¥ããã±ã¼ã¸ã®ãã¡ã¤ã«ãªã¹ã
+		Makefile.target			Makefileã®ã¿ã¼ã²ããä¾å­é¨
+		gdb_ram.ini				GDBã®èµ·åã¹ã¯ãªããï¼RAMå®è¡ç¨ï¼
+		gdb_rom.ini				GDBã®èµ·åã¹ã¯ãªããï¼ROMå®è¡ç¨ï¼
+		gr_peach.h				ã¿ã¼ã²ããã®ãã¼ãã¦ã§ã¢è³æºã®å®ç¾©
+		gr_peach_ram.ld			æ¨æºã®ãªã³ã«ã¹ã¯ãªããï¼RAMå®è¡ç¨ï¼
+		gr_peach_rom.ld			æ¨æºã®ãªã³ã«ã¹ã¯ãªããï¼ROMå®è¡ç¨ï¼
+		renesas_rza1h_swd.cfg	OpenOCDã®èµ·åã¹ã¯ãªãã
+		sf_boot.c				ãã¼ãã­ã¼ãï¼ROMå®è¡ç¨ï¼
+		tPutLogGRPeach.c		ã·ã¹ãã ã­ã°ã®ä½ã¬ãã«åºå
+		tPutLogGRPeach.cdl		ã·ã¹ãã ã­ã°ã®ä½ã¬ãã«åºåã®ã³ã³ãã¼ãã³ãè¨è¿°
+		tSIOPortGRPeach.cdl		ã·ãªã¢ã«ã¤ã³ã¿ãã§ã¼ã¹ãã©ã¤ãã®ã¿ã¼ã²ãã
+								ä¾å­é¨ï¼GR-PEACHç¨ï¼ã®ã³ã³ãã¼ãã³ãè¨è¿°
+		tSIOPortGRPeachMain_inline.h	ã·ãªã¢ã«ã¤ã³ã¿ãã§ã¼ã¹ãã©ã¤ãã®
+								ã¿ã¼ã²ããä¾å­é¨ï¼GR-PEACHç¨ï¼
+		target.cdl				ã³ã³ãã¼ãã³ãè¨è¿°ãã¡ã¤ã«ã®ã¿ã¼ã²ããä¾å­é¨
+		target_cfg1_out.h		cfg1_out.cã®ãªã³ã¯ã«å¿
+è¦ãªã¹ã¿ãã®å®ç¾©
+		target_kernel.cfg		ã«ã¼ãã«å®è£
+ã®ã³ã³ãã£ã®ã¥ã¬ã¼ã·ã§ã³ãã¡ã¤ã«
+		target_kernel.h			kernel.hã®ã¿ã¼ã²ããä¾å­é¨
+		target_kernel.trb		kernel.trbã®ã¿ã¼ã²ããä¾å­é¨
+		target_check.trb		kernel_check.trbã®ã¿ã¼ã²ããä¾å­é¨
+		target_kernel_impl.c	ã«ã¼ãã«å®è£
+ã®ã¿ã¼ã²ããä¾å­é¨
+		target_kernel_impl.h	ã«ã¼ãã«å®è£
+ã®ã¿ã¼ã²ããä¾å­é¨ã«é¢ããå®ç¾©
+		target_rename.def		ã¿ã¼ã²ããä¾å­é¨ã®å
+é¨è­å¥åã®ãªãã¼ã å®ç¾©
+		target_rename.h			ã¿ã¼ã²ããä¾å­é¨ã®å
+é¨è­å¥åã®ãªãã¼ã 
+		target_sil.h			sil.hã®ã¿ã¼ã²ããä¾å­é¨
+		target_stddef.h			t_stddef.hã®ã¿ã¼ã²ããä¾å­é¨
+		target_support.S		ã«ã¼ãã«å®è£
+ã®ã¿ã¼ã²ããä¾å­é¨ï¼ã¢ã»ã³ã
+								ãªè¨èªã§è¨è¿°ããé¨åï¼
+		target_syssvc.h			ã·ã¹ãã ãµã¼ãã¹ã®ã¿ã¼ã²ããä¾å­å®ç¾©
+		target_test.h			ãã¹ããã­ã°ã©ã ã®ã¿ã¼ã²ããä¾å­å®ç¾©
+		target_timer.cfg		ã¿ã¤ããã©ã¤ãã®ã³ã³ãã£ã®ã¥ã¬ã¼ã·ã§ã³ãã¡ã¤ã«
+		target_timer.h			ã¿ã¤ããã©ã¤ããä½¿ç¨ããããã®å®ç¾©
+		target_unrename.h		ã¿ã¼ã²ããä¾å­é¨ã®å
+é¨è­å¥åã®ãªãã¼ã è§£é¤
+		target_user.txt			ã¿ã¼ã²ããä¾å­é¨ã®ã¦ã¼ã¶ã¼ãºããã¥ã¢ã«
+
+5.2 ãã¼ã¸ã§ã³å±¥æ­´
+
+	2016å¹´5æ15æ¥	Release	3.1.0		æåã®ä¸è¬å
+¬é
+
+ä»¥ä¸
