Index: _os_nios2/README.txt
===================================================================
--- /rc_os_nios2/README.txt	(revision 294)
+++ 	(revision )
@@ -1,173 +1,0 @@
-
-		ATK2 RCJ[(Nios2Å)
-		[U[}j
-A
-
-		Îo[W: Release 0.1.0
-		ÅIXV: 2015N831ú
-
-----------------------------------------------------------------------
- TOPPERS Software
-     Toyohashi Open Platform for Embedded Real-Time Systems/
-     Software
-
- Copyright (C) 2015 by Embedded and Real-Time Systems Laboratory
-             Graduate School of Information Science, Nagoya Univ., JAPAN
- 
- ãLì ÒÍCÈºÌ(1)`(4)Ìðð½·êÉÀèC{\tgEF
- Ai{\tgEFAðüÏµ½àÌðÜÞDÈº¯¶jðgpE¡»Eü
- ÏEÄzziÈºCpÆÄÔj·é±Æð³Åø·éD
- (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
-      \¦C±Ìpð¨æÑºLÌ³ÛØKèªC»ÌÜÜÌ`Å\[
-     XR[hÉÜÜêÄ¢é±ÆD
- (2) {\tgEFAðCCu`®ÈÇC¼Ì\tgEFAJ­Ég
-     pÅ«é`ÅÄzz·éêÉÍCÄzzÉº¤hL
-gip
-     Ò}j
-AÈÇjÉCãLÌì \¦C±Ìpð¨æÑºL
-     Ì³ÛØKèðfÚ·é±ÆD
- (3) {\tgEFAðC@íÉgÝÞÈÇC¼Ì\tgEFAJ­Ég
-     pÅ«È¢`ÅÄzz·éêÉÍCÌ¢¸ê©Ìðð½·±
-     ÆD
-   (a) ÄzzÉº¤hL
-gipÒ}j
-AÈÇjÉCãLÌ
-       ì \¦C±Ìpð¨æÑºLÌ³ÛØKèðfÚ·é±ÆD
-   (b) ÄzzÌ`ÔðCÊÉèßéû@ÉæÁÄCTOPPERSvWFNgÉ
-       ñ·é±ÆD
- (4) {\tgEFAÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶é¢©Èé¹
-     Q©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆD
-     Ü½C{\tgEFAÌ[UÜ½ÍGh[U©çÌ¢©Èé
-     RÉîÃ­¿©çàCãLì Ò¨æÑTOPPERSvWFNgð
-     ÆÓ·é±ÆD
- 
- {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì Ò¨
- æÑTOPPERSvWFNgÍC{\tgEFAÉÖµÄCÁèÌgpÚI
- ÉÎ·éK«àÜßÄC¢©ÈéÛØàsíÈ¢DÜ½C{\tgEF
- AÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶½¢©Èé¹QÉÖµÄàC»
- ÌÓCðíÈ¢D
- 
- $Id: $
-----------------------------------------------------------------------
-
-PDTv
-
-ATK2 RCJ[(Nios2Å)fJ[§ävOÍRCJ[ðx[XÆµ½f
-J[ð§ä·é½ßÌvOÅ èCTOPPERSvWFNg©çöJ³
-êÄ¢éATK2ðgpµÄ¢éD
-
-{}j
-AÍÈÕIÈ¨Å é½ßC¡ãg[·é\èÅ éD¿âÍC
-
- users@toppers.jp
- 
-Åó¯t¯éD
-
-
-QDtH_\¬
-
-./sbxbt_ps3_140113.patch  : SBDBT5VpÌt@[EFApb`
-./DE0_Nano_QSYS_DEMO      : DE0pn[hEFApt@C
-./atk2-sc1_1.3.2          : atk2-sc1_1.3.2pt@C
-
-RDOt@C
-
-{vOðgp·é½ßÉÍCÈºÌOt@CªKvÆÈéD
-
-1. ATK2-SC1 
-  TOPPERSvWFNg©çÌt@Cð_E[h
-  atk2-sc1_nios2_dev_gcc-20150406.tar.gz
-
-2. SBDBTpt@[EFA
-   jOGNgjNXÐÌWebTCg©çÈºÌt@Cð_E
-   [h
-   http://runningele.web.fc2.com/ps3/sbxbt_ps3_src_140113.zip
-   
-3.DE0pÌn[hEFAfUC
- TerasicÌTCg©ç_E[h(DE0_Nano_QSYS_DEMOðgp)
-
-
-SDOc[
-
-1.SBDBT«Ýp\tg
-  MicrochipÐÌWebTCg©ç MPLAB IDEÆC32ðüèµÄCXg[
-  
-2.QuratusII
-  AlteraÐÌWebTCg©çQurartusII WebGfBV 14.1ð_E[hµ
-  ÄCXg[
-
-
-TDKv@Þ
-
-{vOðÀs·éÉÍÌ@ÞªKvÅ éD
-
-ERCJ[
-  ®¬iðöxÅÊÌX©çwü
-Ex[X{[h
-  ¼Y¤©çwü
-EDE0-Nano x 1`3
-  AlteraãX©çwü
-ESBDBTTV
-  jOGNgjNX©çwü
-EBluetoothhO
-  SBDBTTVpÊÌX©çwü
-EPS3Rg[
-  ÊÌX©çwü
-EPICC^[
-  ÊÌX©çwü
-ERCJ[ÆDE0-NanoÌÚ±P[u
-  eíÚ±P[uªKv  
-
-
-UDn[hEFAÌõ
-
-E}CR{[hÁH
-  RlN^ðÚ±·é½ß¢­Â©Ìg£sðØf·é
-  
-Ex[XîÂÆ}CR{[hÌZbgAbv
-  E}CR{[hðx[XîÂÉÚ±·é
-  EÇÌnðÀs·é©fBbvXCb`ðÝè·é
-    {fBn  : DIP1 ON
-    §än    : DIP2 ON
-    ÊMn    : DIP3 ON
-    
-EBluetoothW
-[ÌZbgAbv
-  ESBDBTpt@[EFAð_E[h
-  Ezzt@CÌpb`ðKpµÄMAPLAB IDEÉæèrh
-  EPICC^[ðp¢Ä_E[h
-  Et@[EFAt®Ì}j
-AÉ]ÁÄCPS3Rg[ÆyAO·é
-  
-Ex[XîÂÆRCJ[ÌZbgAbv
-  EeRlN^ðÚ±·é
-
-
-VD\tgEFAÌrhÆÀs
-
-1.t@CÌpÓ
- atk2-sc1_nios2_dev_gcc-20150406.tar.gz ðWJ
- zzt@CÌ atk2-sc1_1.3.2 Ìet@Cðã«·é
- 
- autosar.org ©ç_E[hµ½XL[}t@C
- (AUTOSAR_4-0-3_STRICT.xsd, xml.xsd) ðÈºÌtH_ÉRs[·é±ÆD
-
-Eatk2-sc1\cfg\cfg
-
-2.rh
-  atk2-sc1/obj/nios2_dev_rc É¨¢ÄrhðÀ{
-  $ make depend
-  $ make
-  
-3.n[hEFAC[WÌì¬
- atk2-sc1/obj/nios2_dev_rc ÅÈºÌR}hðÀs·é±ÆÅ«Ýt
- @Cª¶¬³êé
-  $ make flash
-  
-4.n[hEFAÌ«Ý
- atk2-sc1/obj/nios2_dev_rc ÅÈºÌR}hðÀs·é±ÆÅDE0-NanoÉ
- «Üêé
- $ make prog
-
-
-Èã
Index: _os_nios2/sbxbt_ps3_140113.patch
===================================================================
--- /rc_os_nios2/sbxbt_ps3_140113.patch	(revision 294)
+++ 	(revision )
@@ -1,44 +1,0 @@
-diff -r sbxbt_ps3_140113_org/btstack/config.h sbxbt_ps3_140113/btstack/config.h
-4,6c4,6
-< #define	ENABLE_LOG_DEBUG
-< #define	ENABLE_LOG_INFO
-< #define	ENABLE_LOG_ERROR
----
-> //#define	ENABLE_LOG_DEBUG
-> //#define	ENABLE_LOG_INFO
-> //#define	ENABLE_LOG_ERROR
-diff -r sbxbt_ps3_140113_org/Common/uart1.c sbxbt_ps3_140113/Common/uart1.c
-78c78
-< #define	RXBUFSIZ			16
----
-> #define	RXBUFSIZ			16*100
-diff -r sbxbt_ps3_140113_org/global.h sbxbt_ps3_140113/global.h
-30c30
-< 	#define BAUDRATE1				2400		//UART1{[[g
----
-> 	#define BAUDRATE1				115200		//UART1{[[g
-117,120c117,128
-< // Configure U1RX - put on pin 3 (RP23)
-< #define	u1rx_setup()		(RPINR18bits.U1RXR = 23)
-< // Configure U1TX - put on pin 2 (RP22)
-< #define u1tx_setup()		(RPOR11bits.RP22R = 3)
----
-> //// Configure U1RX - put on pin 3 (RP23)
-> //#define	u1rx_setup()		(RPINR18bits.U1RXR = 23)
-> 
-> // Configure U1RX - put on pin 22(PGFC1) (RP1)  board pin 5
-> #define	u1rx_setup()		(RPINR18bits.U1RXR = 1)
-> 
-> //// Configure U1TX - put on pin 2 (RP22)
-> //#define u1tx_setup()		(RPOR11bits.RP22R = 3)
-> 
-> // Configure U1TX - put on pin 21(PGFD1) (RP0)  board pin 4
-> #define u1tx_setup()		(RPOR0bits.RP0R = 3)
-> 
-diff -r sbxbt_ps3_140113_org/main.c sbxbt_ps3_140113/main.c
-44c44
-< char							lineBuffer[50];
----
-> char							lineBuffer[50*10];
-sbxbt_ps3_140113/output ã®ã¿ã«å­å¨: sbxbt_ps3.map
-sbxbt_ps3_140113 ã®ã¿ã«å­å¨: PS3-um-2.pdf
Index: /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/DE0_Nano.v
===================================================================
--- /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/DE0_Nano.v	(revision 295)
+++ /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/DE0_Nano.v	(revision 295)
@@ -0,0 +1,271 @@
+// --------------------------------------------------------------------
+// Copyright (c) 2011 by Terasic Technologies Inc. 
+// --------------------------------------------------------------------
+//
+// Permission:
+//
+//   Terasic grants permission to use and modify this code for use
+//   in synthesis for all Terasic Development Boards and Altera Development 
+//   Kits made by Terasic.  Other use of this code, including the selling 
+//   ,duplication, or modification of any portion is strictly prohibited.
+//
+// Disclaimer:
+//
+//   This VHDL/Verilog or C/C++ source code is intended as a design reference
+//   which illustrates how these types of functions can be implemented.
+//   It is the user's responsibility to verify their design for
+//   consistency and functionality through the use of formal
+//   verification methods.  Terasic provides no warranty regarding the use 
+//   or functionality of this code.
+//
+// --------------------------------------------------------------------
+//           
+//                     Terasic Technologies Inc
+//                     E. Rd Sec. 1. JhuBei City,
+//                     HsinChu County, Taiwan
+//                     302
+//
+//                     web: http://www.terasic.com/   
+//                     email: support@terasic.com
+//
+// --------------------------------------------------------------------
+
+module DE0_Nano(
+
+	//////////// CLOCK //////////
+	CLOCK_50,
+
+	//////////// LED //////////
+	LED,
+
+	//////////// KEY //////////
+	KEY,
+
+	//////////// SW //////////
+	SW,
+
+	//////////// SDRAM //////////
+	DRAM_ADDR,
+	DRAM_BA,
+	DRAM_CAS_N,
+	DRAM_CKE,
+	DRAM_CLK,
+	DRAM_CS_N,
+	DRAM_DQ,
+	DRAM_DQM,
+	DRAM_RAS_N,
+	DRAM_WE_N,
+	
+	//////////// ECPS //////////
+	EPCS_ASDO,
+	EPCS_DATA0,
+	EPCS_DCLK,
+	EPCS_NCSO,
+
+	//////////// Accelerometer and EEPROM //////////
+	G_SENSOR_CS_N,
+	G_SENSOR_INT,
+	I2C_SCLK,
+	I2C_SDAT,
+
+	//////////// ADC //////////
+	ADC_CS_N,
+	ADC_SADDR,
+	ADC_SCLK,
+	ADC_SDAT,
+
+	//////////// 2x13 GPIO Header //////////
+	GPIO_2,
+	GPIO_2_IN,
+
+	//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
+	GPIO_0,
+	GPIO_0_IN,
+
+	//////////// GPIO_1, GPIO_1 connect to GPIO Default //////////
+	GPIO_1,
+	GPIO_1_IN 
+);
+
+//=======================================================
+//  PARAMETER declarations
+//=======================================================
+
+
+//=======================================================
+//  PORT declarations
+//=======================================================
+
+//////////// CLOCK //////////
+input 		          		CLOCK_50;
+
+//////////// LED //////////
+output		     [7:0]		LED;
+
+//////////// KEY //////////
+input 		     [1:0]		KEY;
+
+//////////// SW //////////
+input 		     [3:0]		SW;
+
+//////////// SDRAM //////////
+output		    [12:0]		DRAM_ADDR;
+output		     [1:0]		DRAM_BA;
+output		          		DRAM_CAS_N;
+output		          		DRAM_CKE;
+output		          		DRAM_CLK;
+output		          		DRAM_CS_N;
+inout 		    [15:0]		DRAM_DQ;
+output		     [1:0]		DRAM_DQM;
+output		          		DRAM_RAS_N;
+output		          		DRAM_WE_N;
+
+//////////// EPCS //////////
+output		          		EPCS_ASDO;
+input 		          		EPCS_DATA0;
+output		          		EPCS_DCLK;
+output		          		EPCS_NCSO;
+
+//////////// Accelerometer and EEPROM //////////
+output		          		G_SENSOR_CS_N;
+input 		          		G_SENSOR_INT;
+output							I2C_SCLK;
+inout 		          		I2C_SDAT;
+
+//////////// ADC //////////
+output		          		ADC_CS_N;
+output		          		ADC_SADDR;
+output		          		ADC_SCLK;
+input 		          		ADC_SDAT;
+
+//////////// 2x13 GPIO Header //////////
+inout 		    [12:0]		GPIO_2;
+input 		     [2:0]		GPIO_2_IN;
+
+//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
+inout 		    [33:0]		GPIO_0;
+input 		     [1:0]		GPIO_0_IN;
+
+//////////// GPIO_1, GPIO_1 connect to GPIO Default //////////
+inout 		    [33:0]		GPIO_1;
+input 		     [1:0]		GPIO_1_IN;
+
+
+//=======================================================
+//  REG/WIRE declarations
+//=======================================================
+wire reset_n;
+wire select_i2c_clk;
+wire i2c_clk;
+wire spi_clk;
+
+
+
+//=======================================================
+//  Structural coding
+//=======================================================
+
+assign reset_n = 1'b1;
+
+DE0_Nano_SOPC DE0_Nano_SOPC_inst(
+                      // 1) global signals:
+                       .altpll_io(),
+                       .altpll_sdram(DRAM_CLK),
+                       .altpll_sys(),
+                       .clk_50(CLOCK_50),
+//                       .clk_50_clk_in_reset_reset_n(reset_n),
+                       .clk_50_clk_in_reset_reset_n(KEY[0]),
+							  
+                      // the_select_i2c_clk
+                       .out_port_from_the_select_i2c_clk(select_i2c_clk),							  
+
+							  
+                      // the_adc_spi_read
+                       .SPI_CLK_from_the_adc_spi_read(ADC_SCLK),
+                       .SPI_CS_n_from_the_adc_spi_read(ADC_CS_N),
+                       .SPI_IN_to_the_adc_spi_read(ADC_SDAT),
+                       .SPI_OUT_from_the_adc_spi_read(ADC_SADDR),
+							  
+							  
+                      // the_altpll_0
+                       .locked_from_the_altpll_0(),
+                       .phasedone_from_the_altpll_0(),
+
+                      // the_epcs
+                       .data0_to_the_epcs(EPCS_DATA0), 
+                       .dclk_from_the_epcs(EPCS_DCLK), 
+                       .sce_from_the_epcs(EPCS_NCSO), 
+                       .sdo_from_the_epcs(EPCS_ASDO), 
+
+							  
+                      // the_gsensor_spi
+                       .SPI_CS_n_from_the_gsensor_spi(G_SENSOR_CS_N),
+                       .SPI_SCLK_from_the_gsensor_spi(spi_clk),
+                       .SPI_SDIO_to_and_from_the_gsensor_spi(I2C_SDAT),							  
+						  
+
+                      // the_g_sensor_int
+                       .in_port_to_the_g_sensor_int(G_SENSOR_INT),
+
+                      // the_i2c_scl
+                       .out_port_from_the_i2c_scl(i2c_clk),
+
+                      // the_i2c_sda
+                       .bidir_port_to_and_from_the_i2c_sda(I2C_SDAT),
+
+                      // the_key
+                       .in_port_to_the_key(KEY),
+
+                      // the_led
+                       .out_port_from_the_led(LED),
+
+                      // the_sdram
+                       .zs_addr_from_the_sdram(DRAM_ADDR),
+                       .zs_ba_from_the_sdram(DRAM_BA),
+                       .zs_cas_n_from_the_sdram(DRAM_CAS_N),
+                       .zs_cke_from_the_sdram(DRAM_CKE),
+                       .zs_cs_n_from_the_sdram(DRAM_CS_N),
+                       .zs_dq_to_and_from_the_sdram(DRAM_DQ),
+                       .zs_dqm_from_the_sdram(DRAM_DQM),
+                       .zs_ras_n_from_the_sdram(DRAM_RAS_N),
+                       .zs_we_n_from_the_sdram(DRAM_WE_N),
+
+							  // the_can_top_0-ch1
+							  .can_top_0_conduit_end_rx_i(GPIO_2[2]),
+							  .can_top_0_conduit_end_tx_o(GPIO_2[0]),
+
+							  // the_can_top_1-ch2
+//							  .can_top_0_conduit_end_rx_i(GPIO_2[6]),
+//							  .can_top_0_conduit_end_tx_o(GPIO_2[4]),
+
+							  // UART-ch1
+							  .uart_0_external_connection_rxd(GPIO_2[12]),
+							  .uart_0_external_connection_txd(GPIO_2[10]),
+
+							  // UART-ch2
+//							  .uart_1_external_connection_rxd(GPIO_2[3]),
+//							  .uart_1_external_connection_txd(GPIO_2[1]),
+//							  .uart_1_external_connection_rxd(GPIO_0[24]),
+//							  .uart_1_external_connection_txd(GPIO_0[25]),
+							  .uart_1_external_connection_rxd(GPIO_1[2]),
+							  .uart_1_external_connection_txd(GPIO_1[3]),
+
+//							  .pio_0_external_connection_export(GPIO_0[7:0]),
+//							  .pio_0_external_connection_export(GPIO_1[15:8]),
+							  .pio_0_external_connection_export(GPIO_1[31:24]),
+
+							  .multi_pwm_0_conduit_end_pwm1(GPIO_0[2]),
+							  .multi_pwm_0_conduit_end_pwm2(GPIO_0[3]),
+							  .multi_pwm_0_conduit_end_pwm3(GPIO_0[4]),
+							  .multi_pwm_0_conduit_end_pwm4(GPIO_0[5]),
+							  .multi_pwm_0_conduit_end_pwm5(GPIO_0[6]),
+							  .multi_pwm_0_conduit_end_pwm6(GPIO_0[7]), 
+
+                      // the_sw
+                       .in_port_to_the_sw(SW)
+                    );
+
+						  
+assign I2C_SCLK = (select_i2c_clk)?i2c_clk:spi_clk;
+
+endmodule
Index: /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/DE0_Nano_SOPC.qsys
===================================================================
--- /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/DE0_Nano_SOPC.qsys	(revision 295)
+++ /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/DE0_Nano_SOPC.qsys	(revision 295)
@@ -0,0 +1,2856 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element $${FILENAME}
+   {
+   }
+   element adc_spi_read
+   {
+      datum _sortIndex
+      {
+         value = "40";
+         type = "int";
+      }
+   }
+   element altpll_sys
+   {
+      datum _sortIndex
+      {
+         value = "9";
+         type = "int";
+      }
+   }
+   element jtag_uart.avalon_jtag_slave
+   {
+      datum baseAddress
+      {
+         value = "416";
+         type = "String";
+      }
+   }
+   element sysver_0.avalon_slave_0
+   {
+      datum baseAddress
+      {
+         value = "448";
+         type = "String";
+      }
+   }
+   element multi_pwm_0.avalon_slave_0
+   {
+      datum baseAddress
+      {
+         value = "160";
+         type = "String";
+      }
+   }
+   element c0
+   {
+      datum _sortIndex
+      {
+         value = "4";
+         type = "int";
+      }
+   }
+   element c2
+   {
+      datum _sortIndex
+      {
+         value = "5";
+         type = "int";
+      }
+   }
+   element c4
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+   }
+   element can_top_0
+   {
+      datum _sortIndex
+      {
+         value = "43";
+         type = "int";
+      }
+   }
+   element clk_50
+   {
+      datum _sortIndex
+      {
+         value = "7";
+         type = "int";
+      }
+   }
+   element clock_crossing_io
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+   element clock_crossing_io2
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+   }
+   element sysid.control_slave
+   {
+      datum baseAddress
+      {
+         value = "112";
+         type = "long";
+      }
+   }
+   element cpu
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
+   element epcs
+   {
+      datum _sortIndex
+      {
+         value = "38";
+         type = "int";
+      }
+      datum megawizard_uipreferences
+      {
+         value = "{output_language=VERILOG, output_directory=D:\\Q_DE_NANO}";
+         type = "String";
+      }
+   }
+   element g_sensor_int
+   {
+      datum _sortIndex
+      {
+         value = "17";
+         type = "int";
+      }
+      datum megawizard_uipreferences
+      {
+         value = "{}";
+         type = "String";
+      }
+   }
+   element gsensor_spi
+   {
+      datum _sortIndex
+      {
+         value = "39";
+         type = "int";
+      }
+   }
+   element i2c_scl
+   {
+      datum _sortIndex
+      {
+         value = "37";
+         type = "int";
+      }
+      datum megawizard_uipreferences
+      {
+         value = "{}";
+         type = "String";
+      }
+   }
+   element i2c_sda
+   {
+      datum _sortIndex
+      {
+         value = "36";
+         type = "int";
+      }
+      datum megawizard_uipreferences
+      {
+         value = "{}";
+         type = "String";
+      }
+   }
+   element cpu.jtag_debug_module
+   {
+      datum baseAddress
+      {
+         value = "33554432";
+         type = "String";
+      }
+   }
+   element jtag_uart
+   {
+      datum _sortIndex
+      {
+         value = "11";
+         type = "int";
+      }
+   }
+   element key
+   {
+      datum _sortIndex
+      {
+         value = "12";
+         type = "int";
+      }
+      datum megawizard_uipreferences
+      {
+         value = "{}";
+         type = "String";
+      }
+   }
+   element led
+   {
+      datum _sortIndex
+      {
+         value = "14";
+         type = "int";
+      }
+      datum megawizard_uipreferences
+      {
+         value = "{}";
+         type = "String";
+      }
+   }
+   element multi_pwm_0
+   {
+      datum _sortIndex
+      {
+         value = "16";
+         type = "int";
+      }
+   }
+   element pio
+   {
+      datum _sortIndex
+      {
+         value = "15";
+         type = "int";
+      }
+   }
+   element altpll_sys.pll_slave
+   {
+      datum baseAddress
+      {
+         value = "100667392";
+         type = "long";
+      }
+   }
+   element clock_crossing_io.s0
+   {
+      datum baseAddress
+      {
+         value = "134217728";
+         type = "String";
+      }
+   }
+   element clock_crossing_io2.s0
+   {
+      datum baseAddress
+      {
+         value = "117440512";
+         type = "String";
+      }
+   }
+   element sdram.s1
+   {
+      datum _lockedAddress
+      {
+         value = "0";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element pio.s1
+   {
+      datum baseAddress
+      {
+         value = "128";
+         type = "String";
+      }
+   }
+   element timer_5.s1
+   {
+      datum baseAddress
+      {
+         value = "672";
+         type = "String";
+      }
+   }
+   element timer_11.s1
+   {
+      datum baseAddress
+      {
+         value = "864";
+         type = "String";
+      }
+   }
+   element timer_1.s1
+   {
+      datum baseAddress
+      {
+         value = "544";
+         type = "String";
+      }
+   }
+   element key.s1
+   {
+      datum baseAddress
+      {
+         value = "32";
+         type = "long";
+      }
+   }
+   element timer_13.s1
+   {
+      datum baseAddress
+      {
+         value = "928";
+         type = "String";
+      }
+   }
+   element timer_6.s1
+   {
+      datum baseAddress
+      {
+         value = "704";
+         type = "String";
+      }
+   }
+   element select_i2c_clk.s1
+   {
+      datum baseAddress
+      {
+         value = "96";
+         type = "long";
+      }
+   }
+   element sys_clk_timer.s1
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "long";
+      }
+   }
+   element sw.s1
+   {
+      datum baseAddress
+      {
+         value = "64";
+         type = "long";
+      }
+   }
+   element timer_12.s1
+   {
+      datum baseAddress
+      {
+         value = "896";
+         type = "String";
+      }
+   }
+   element g_sensor_int.s1
+   {
+      datum baseAddress
+      {
+         value = "80";
+         type = "long";
+      }
+   }
+   element timer_4.s1
+   {
+      datum baseAddress
+      {
+         value = "640";
+         type = "String";
+      }
+   }
+   element timer_10.s1
+   {
+      datum baseAddress
+      {
+         value = "832";
+         type = "String";
+      }
+   }
+   element timer_14.s1
+   {
+      datum baseAddress
+      {
+         value = "960";
+         type = "String";
+      }
+   }
+   element timer_2.s1
+   {
+      datum baseAddress
+      {
+         value = "576";
+         type = "String";
+      }
+   }
+   element timer_9.s1
+   {
+      datum baseAddress
+      {
+         value = "800";
+         type = "String";
+      }
+   }
+   element led.s1
+   {
+      datum baseAddress
+      {
+         value = "48";
+         type = "long";
+      }
+   }
+   element timer_15.s1
+   {
+      datum baseAddress
+      {
+         value = "992";
+         type = "String";
+      }
+   }
+   element timer_3.s1
+   {
+      datum baseAddress
+      {
+         value = "608";
+         type = "String";
+      }
+   }
+   element timer_8.s1
+   {
+      datum baseAddress
+      {
+         value = "768";
+         type = "String";
+      }
+   }
+   element timer_0.s1
+   {
+      datum baseAddress
+      {
+         value = "512";
+         type = "String";
+      }
+   }
+   element timer_7.s1
+   {
+      datum baseAddress
+      {
+         value = "736";
+         type = "String";
+      }
+   }
+   element sdram
+   {
+      datum _sortIndex
+      {
+         value = "8";
+         type = "int";
+      }
+      datum megawizard_uipreferences
+      {
+         value = "{output_language=VERILOG, output_directory=D:\\DE_NANO\\Q_DE_NANO_RTL}";
+         type = "String";
+      }
+   }
+   element select_i2c_clk
+   {
+      datum _sortIndex
+      {
+         value = "18";
+         type = "int";
+      }
+   }
+   element sram_dummy
+   {
+      datum _sortIndex
+      {
+         value = "41";
+         type = "int";
+      }
+   }
+   element sw
+   {
+      datum _sortIndex
+      {
+         value = "13";
+         type = "int";
+      }
+      datum megawizard_uipreferences
+      {
+         value = "{}";
+         type = "String";
+      }
+   }
+   element sys_clk_timer
+   {
+      datum _sortIndex
+      {
+         value = "10";
+         type = "int";
+      }
+      datum megawizard_uipreferences
+      {
+         value = "{}";
+         type = "String";
+      }
+   }
+   element sysid
+   {
+      datum _sortIndex
+      {
+         value = "3";
+         type = "int";
+      }
+   }
+   element sysver_0
+   {
+      datum _sortIndex
+      {
+         value = "19";
+         type = "int";
+      }
+   }
+   element timer_0
+   {
+      datum _sortIndex
+      {
+         value = "20";
+         type = "int";
+      }
+   }
+   element timer_1
+   {
+      datum _sortIndex
+      {
+         value = "21";
+         type = "int";
+      }
+   }
+   element timer_10
+   {
+      datum _sortIndex
+      {
+         value = "30";
+         type = "int";
+      }
+   }
+   element timer_11
+   {
+      datum _sortIndex
+      {
+         value = "31";
+         type = "int";
+      }
+   }
+   element timer_12
+   {
+      datum _sortIndex
+      {
+         value = "32";
+         type = "int";
+      }
+   }
+   element timer_13
+   {
+      datum _sortIndex
+      {
+         value = "33";
+         type = "int";
+      }
+   }
+   element timer_14
+   {
+      datum _sortIndex
+      {
+         value = "34";
+         type = "int";
+      }
+   }
+   element timer_15
+   {
+      datum _sortIndex
+      {
+         value = "35";
+         type = "int";
+      }
+   }
+   element timer_2
+   {
+      datum _sortIndex
+      {
+         value = "22";
+         type = "int";
+      }
+   }
+   element timer_3
+   {
+      datum _sortIndex
+      {
+         value = "23";
+         type = "int";
+      }
+   }
+   element timer_4
+   {
+      datum _sortIndex
+      {
+         value = "24";
+         type = "int";
+      }
+   }
+   element timer_5
+   {
+      datum _sortIndex
+      {
+         value = "25";
+         type = "int";
+      }
+   }
+   element timer_6
+   {
+      datum _sortIndex
+      {
+         value = "26";
+         type = "int";
+      }
+   }
+   element timer_7
+   {
+      datum _sortIndex
+      {
+         value = "27";
+         type = "int";
+      }
+   }
+   element timer_8
+   {
+      datum _sortIndex
+      {
+         value = "28";
+         type = "int";
+      }
+   }
+   element timer_9
+   {
+      datum _sortIndex
+      {
+         value = "29";
+         type = "int";
+      }
+   }
+   element uart_0
+   {
+      datum _sortIndex
+      {
+         value = "44";
+         type = "int";
+      }
+   }
+   element uart_1
+   {
+      datum _sortIndex
+      {
+         value = "45";
+         type = "int";
+      }
+   }
+   element vic_0
+   {
+      datum _sortIndex
+      {
+         value = "42";
+         type = "int";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="EP4CE22F17C6" />
+ <parameter name="deviceFamily" value="Cyclone IV E" />
+ <parameter name="deviceSpeedGrade" value="6" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="maxAdditionalLatency" value="0" />
+ <parameter name="projectName" value="DE0_Nano.qpf" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="1" />
+ <parameter name="timeStamp" value="1415543992401" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="clk_50_clk_in" internal="clk_50.clk_in" type="clock" dir="end">
+  <port name="clk_50" internal="in_clk" />
+ </interface>
+ <interface
+   name="key_external_connection"
+   internal="key.external_connection"
+   type="conduit"
+   dir="end">
+  <port name="in_port_to_the_key" internal="in_port" />
+ </interface>
+ <interface
+   name="sw_external_connection"
+   internal="sw.external_connection"
+   type="conduit"
+   dir="end">
+  <port name="in_port_to_the_sw" internal="in_port" />
+ </interface>
+ <interface
+   name="led_external_connection"
+   internal="led.external_connection"
+   type="conduit"
+   dir="end">
+  <port name="out_port_from_the_led" internal="out_port" />
+ </interface>
+ <interface
+   name="i2c_scl_external_connection"
+   internal="i2c_scl.external_connection"
+   type="conduit"
+   dir="end">
+  <port name="out_port_from_the_i2c_scl" internal="out_port" />
+ </interface>
+ <interface
+   name="i2c_sda_external_connection"
+   internal="i2c_sda.external_connection"
+   type="conduit"
+   dir="end">
+  <port name="bidir_port_to_and_from_the_i2c_sda" internal="bidir_port" />
+ </interface>
+ <interface name="sdram_wire" internal="sdram.wire" type="conduit" dir="end">
+  <port name="zs_addr_from_the_sdram" internal="zs_addr" />
+  <port name="zs_ba_from_the_sdram" internal="zs_ba" />
+  <port name="zs_cas_n_from_the_sdram" internal="zs_cas_n" />
+  <port name="zs_cke_from_the_sdram" internal="zs_cke" />
+  <port name="zs_cs_n_from_the_sdram" internal="zs_cs_n" />
+  <port name="zs_dq_to_and_from_the_sdram" internal="zs_dq" />
+  <port name="zs_dqm_from_the_sdram" internal="zs_dqm" />
+  <port name="zs_ras_n_from_the_sdram" internal="zs_ras_n" />
+  <port name="zs_we_n_from_the_sdram" internal="zs_we_n" />
+ </interface>
+ <interface name="c0_out_clk" internal="c0.out_clk" type="clock" dir="start">
+  <port name="altpll_sys" internal="out_clk" />
+ </interface>
+ <interface
+   name="altpll_sys_c1"
+   internal="altpll_sys.c1"
+   type="clock"
+   dir="start">
+  <port name="altpll_sdram" internal="c1" />
+ </interface>
+ <interface name="c2_out_clk" internal="c2.out_clk" type="clock" dir="start">
+  <port name="altpll_io" internal="out_clk" />
+ </interface>
+ <interface
+   name="altpll_sys_c3"
+   internal="altpll_sys.c3"
+   type="clock"
+   dir="start">
+  <port name="altpll_sys_c3_out" internal="c3" />
+ </interface>
+ <interface name="c4_out_clk" internal="c4.out_clk" type="clock" dir="start">
+  <port name="altpll_adc" internal="out_clk" />
+ </interface>
+ <interface
+   name="altpll_sys_locked_conduit"
+   internal="altpll_sys.locked_conduit"
+   type="conduit"
+   dir="end">
+  <port name="locked_from_the_altpll_sys" internal="locked" />
+ </interface>
+ <interface
+   name="altpll_sys_phasedone_conduit"
+   internal="altpll_sys.phasedone_conduit"
+   type="conduit"
+   dir="end">
+  <port name="phasedone_from_the_altpll_sys" internal="phasedone" />
+ </interface>
+ <interface
+   name="g_sensor_int_external_connection"
+   internal="g_sensor_int.external_connection"
+   type="conduit"
+   dir="end">
+  <port name="in_port_to_the_g_sensor_int" internal="in_port" />
+ </interface>
+ <interface
+   name="epcs_external"
+   internal="epcs.external"
+   type="conduit"
+   dir="end">
+  <port name="dclk_from_the_epcs" internal="dclk" />
+  <port name="sce_from_the_epcs" internal="sce" />
+  <port name="sdo_from_the_epcs" internal="sdo" />
+  <port name="data0_to_the_epcs" internal="data0" />
+ </interface>
+ <interface
+   name="adc_spi_read_conduit_end"
+   internal="adc_spi_read.conduit_end"
+   type="conduit"
+   dir="end">
+  <port name="SPI_OUT_from_the_adc_spi_read" internal="SPI_OUT" />
+  <port name="SPI_IN_to_the_adc_spi_read" internal="SPI_IN" />
+  <port name="SPI_CS_n_from_the_adc_spi_read" internal="SPI_CS_n" />
+  <port name="SPI_CLK_from_the_adc_spi_read" internal="SPI_CLK" />
+ </interface>
+ <interface
+   name="gsensor_spi_conduit_end"
+   internal="gsensor_spi.conduit_end"
+   type="conduit"
+   dir="end">
+  <port name="SPI_SDIO_to_and_from_the_gsensor_spi" internal="SPI_SDIO" />
+  <port name="SPI_SCLK_from_the_gsensor_spi" internal="SPI_SCLK" />
+  <port name="SPI_CS_n_from_the_gsensor_spi" internal="SPI_CS_n" />
+ </interface>
+ <interface
+   name="select_i2c_clk_external_connection"
+   internal="select_i2c_clk.external_connection"
+   type="conduit"
+   dir="end">
+  <port name="out_port_from_the_select_i2c_clk" internal="out_port" />
+ </interface>
+ <interface
+   name="altpll_sys_areset_conduit"
+   internal="altpll_sys.areset_conduit"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="can_top_0_conduit_end"
+   internal="can_top_0.conduit_end"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="uart_0_external_connection"
+   internal="uart_0.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="uart_1_external_connection"
+   internal="uart_1.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="pio_0_external_connection"
+   internal="pio.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="multi_pwm_0_conduit_end"
+   internal="multi_pwm_0.conduit_end"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="clk_50_clk_in_reset"
+   internal="clk_50.clk_in_reset"
+   type="reset"
+   dir="end" />
+ <module kind="clock_source" version="13.0" enabled="1" name="clk_50">
+  <parameter name="clockFrequency" value="50000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="0" />
+  <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module
+   kind="altera_avalon_timer"
+   version="13.0.1.99.2"
+   enabled="0"
+   name="sys_clk_timer">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="systemFrequency" value="60000000" />
+ </module>
+ <module kind="altera_avalon_pio" version="13.0.1.99.2" enabled="1" name="key">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="true" />
+  <parameter name="direction" value="Input" />
+  <parameter name="edgeType" value="FALLING" />
+  <parameter name="generateIRQ" value="true" />
+  <parameter name="irqType" value="EDGE" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="2" />
+  <parameter name="clockRate" value="60000000" />
+ </module>
+ <module kind="altera_avalon_pio" version="13.0.1.99.2" enabled="1" name="sw">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="true" />
+  <parameter name="direction" value="Input" />
+  <parameter name="edgeType" value="ANY" />
+  <parameter name="generateIRQ" value="true" />
+  <parameter name="irqType" value="EDGE" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="4" />
+  <parameter name="clockRate" value="60000000" />
+ </module>
+ <module kind="altera_avalon_pio" version="13.0.1.99.2" enabled="1" name="led">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="8" />
+  <parameter name="clockRate" value="60000000" />
+ </module>
+ <module
+   kind="altera_avalon_pio"
+   version="13.0.1.99.2"
+   enabled="1"
+   name="i2c_scl">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="1" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="1" />
+  <parameter name="clockRate" value="50000000" />
+ </module>
+ <module
+   kind="altera_avalon_pio"
+   version="13.0.1.99.2"
+   enabled="1"
+   name="i2c_sda">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="direction" value="Bidir" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="1" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="1" />
+  <parameter name="clockRate" value="50000000" />
+ </module>
+ <module
+   kind="altera_avalon_new_sdram_controller"
+   version="13.0.1.99.2"
+   enabled="1"
+   name="sdram">
+  <parameter name="TAC" value="5.5" />
+  <parameter name="TRCD" value="20.0" />
+  <parameter name="TRFC" value="70.0" />
+  <parameter name="TRP" value="20.0" />
+  <parameter name="TWR" value="14.0" />
+  <parameter name="casLatency" value="3" />
+  <parameter name="columnWidth" value="9" />
+  <parameter name="dataWidth" value="16" />
+  <parameter name="generateSimulationModel" value="true" />
+  <parameter name="initRefreshCommands" value="2" />
+  <parameter name="model" value="custom" />
+  <parameter name="numberOfBanks" value="4" />
+  <parameter name="numberOfChipSelects" value="1" />
+  <parameter name="pinsSharedViaTriState" value="false" />
+  <parameter name="powerUpDelay" value="100.0" />
+  <parameter name="refreshPeriod" value="15.625" />
+  <parameter name="rowWidth" value="13" />
+  <parameter name="masteredTristateBridgeSlave" value="0" />
+  <parameter name="TMRD" value="3" />
+  <parameter name="initNOPDelay" value="0.0" />
+  <parameter name="registerDataIn" value="true" />
+  <parameter name="clockRate" value="100000000" />
+  <parameter name="componentName" value="DE0_Nano_SOPC_sdram" />
+ </module>
+ <module kind="altpll" version="13.0" enabled="1" name="altpll_sys">
+  <parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
+  <parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
+  <parameter name="INTENDED_DEVICE_FAMILY" value="Cyclone IV E" />
+  <parameter name="WIDTH_CLOCK" value="5" />
+  <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
+  <parameter name="PRIMARY_CLOCK" value="" />
+  <parameter name="INCLK0_INPUT_FREQUENCY" value="20000" />
+  <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
+  <parameter name="OPERATION_MODE" value="NORMAL" />
+  <parameter name="PLL_TYPE" value="AUTO" />
+  <parameter name="QUALIFY_CONF_DONE" value="" />
+  <parameter name="COMPENSATE_CLOCK" value="CLK0" />
+  <parameter name="SCAN_CHAIN" value="" />
+  <parameter name="GATE_LOCK_SIGNAL" value="" />
+  <parameter name="GATE_LOCK_COUNTER" value="" />
+  <parameter name="LOCK_HIGH" value="" />
+  <parameter name="LOCK_LOW" value="" />
+  <parameter name="VALID_LOCK_MULTIPLIER" value="" />
+  <parameter name="INVALID_LOCK_MULTIPLIER" value="" />
+  <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
+  <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
+  <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
+  <parameter name="SKIP_VCO" value="" />
+  <parameter name="SWITCH_OVER_COUNTER" value="" />
+  <parameter name="SWITCH_OVER_TYPE" value="" />
+  <parameter name="FEEDBACK_SOURCE" value="" />
+  <parameter name="BANDWIDTH" value="" />
+  <parameter name="BANDWIDTH_TYPE" value="AUTO" />
+  <parameter name="SPREAD_FREQUENCY" value="" />
+  <parameter name="DOWN_SPREAD" value="" />
+  <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
+  <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
+  <parameter name="CLK0_MULTIPLY_BY" value="2" />
+  <parameter name="CLK1_MULTIPLY_BY" value="2" />
+  <parameter name="CLK2_MULTIPLY_BY" value="6" />
+  <parameter name="CLK3_MULTIPLY_BY" value="4" />
+  <parameter name="CLK4_MULTIPLY_BY" value="1" />
+  <parameter name="CLK5_MULTIPLY_BY" value="" />
+  <parameter name="CLK6_MULTIPLY_BY" value="" />
+  <parameter name="CLK7_MULTIPLY_BY" value="" />
+  <parameter name="CLK8_MULTIPLY_BY" value="" />
+  <parameter name="CLK9_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
+  <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
+  <parameter name="CLK0_DIVIDE_BY" value="1" />
+  <parameter name="CLK1_DIVIDE_BY" value="1" />
+  <parameter name="CLK2_DIVIDE_BY" value="5" />
+  <parameter name="CLK3_DIVIDE_BY" value="5" />
+  <parameter name="CLK4_DIVIDE_BY" value="25" />
+  <parameter name="CLK5_DIVIDE_BY" value="" />
+  <parameter name="CLK6_DIVIDE_BY" value="" />
+  <parameter name="CLK7_DIVIDE_BY" value="" />
+  <parameter name="CLK8_DIVIDE_BY" value="" />
+  <parameter name="CLK9_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK0_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK1_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK2_DIVIDE_BY" value="" />
+  <parameter name="EXTCLK3_DIVIDE_BY" value="" />
+  <parameter name="CLK0_PHASE_SHIFT" value="0" />
+  <parameter name="CLK1_PHASE_SHIFT" value="-1806" />
+  <parameter name="CLK2_PHASE_SHIFT" value="0" />
+  <parameter name="CLK3_PHASE_SHIFT" value="0" />
+  <parameter name="CLK4_PHASE_SHIFT" value="0" />
+  <parameter name="CLK5_PHASE_SHIFT" value="" />
+  <parameter name="CLK6_PHASE_SHIFT" value="" />
+  <parameter name="CLK7_PHASE_SHIFT" value="" />
+  <parameter name="CLK8_PHASE_SHIFT" value="" />
+  <parameter name="CLK9_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
+  <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
+  <parameter name="CLK0_DUTY_CYCLE" value="50" />
+  <parameter name="CLK1_DUTY_CYCLE" value="50" />
+  <parameter name="CLK2_DUTY_CYCLE" value="50" />
+  <parameter name="CLK3_DUTY_CYCLE" value="50" />
+  <parameter name="CLK4_DUTY_CYCLE" value="50" />
+  <parameter name="CLK5_DUTY_CYCLE" value="" />
+  <parameter name="CLK6_DUTY_CYCLE" value="" />
+  <parameter name="CLK7_DUTY_CYCLE" value="" />
+  <parameter name="CLK8_DUTY_CYCLE" value="" />
+  <parameter name="CLK9_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
+  <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
+  <parameter name="PORT_clkena0" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena1" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena2" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena3" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena4" value="PORT_UNUSED" />
+  <parameter name="PORT_clkena5" value="PORT_UNUSED" />
+  <parameter name="PORT_extclkena0" value="" />
+  <parameter name="PORT_extclkena1" value="" />
+  <parameter name="PORT_extclkena2" value="" />
+  <parameter name="PORT_extclkena3" value="" />
+  <parameter name="PORT_extclk0" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk1" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk2" value="PORT_UNUSED" />
+  <parameter name="PORT_extclk3" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
+  <parameter name="PORT_clk0" value="PORT_USED" />
+  <parameter name="PORT_clk1" value="PORT_USED" />
+  <parameter name="PORT_clk2" value="PORT_USED" />
+  <parameter name="PORT_clk3" value="PORT_USED" />
+  <parameter name="PORT_clk4" value="PORT_USED" />
+  <parameter name="PORT_clk5" value="PORT_UNUSED" />
+  <parameter name="PORT_clk6" value="" />
+  <parameter name="PORT_clk7" value="" />
+  <parameter name="PORT_clk8" value="" />
+  <parameter name="PORT_clk9" value="" />
+  <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
+  <parameter name="PORT_SCLKOUT1" value="" />
+  <parameter name="PORT_SCLKOUT0" value="" />
+  <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
+  <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
+  <parameter name="PORT_INCLK0" value="PORT_USED" />
+  <parameter name="PORT_FBIN" value="PORT_UNUSED" />
+  <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
+  <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
+  <parameter name="PORT_ARESET" value="PORT_USED" />
+  <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
+  <parameter name="PORT_ENABLE0" value="" />
+  <parameter name="PORT_ENABLE1" value="" />
+  <parameter name="PORT_LOCKED" value="PORT_USED" />
+  <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
+  <parameter name="PORT_FBOUT" value="" />
+  <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
+  <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
+  <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
+  <parameter name="PORT_VCOOVERRANGE" value="" />
+  <parameter name="PORT_VCOUNDERRANGE" value="" />
+  <parameter name="DPA_MULTIPLY_BY" value="" />
+  <parameter name="DPA_DIVIDE_BY" value="" />
+  <parameter name="DPA_DIVIDER" value="" />
+  <parameter name="VCO_MULTIPLY_BY" value="" />
+  <parameter name="VCO_DIVIDE_BY" value="" />
+  <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
+  <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
+  <parameter name="VCO_FREQUENCY_CONTROL" value="" />
+  <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
+  <parameter name="USING_FBMIMICBIDIR_PORT" value="" />
+  <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
+  <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
+  <parameter name="HIDDEN_CONSTANTS">CT#CLK2_DIVIDE_BY 5 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_USED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 2 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 5 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT 0 CT#PORT_SCANCLKENA PORT_UNUSED CT#CLK4_DIVIDE_BY 25 CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#CLK4_MULTIPLY_BY 1 CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 2 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#CLK4_PHASE_SHIFT 0 CT#INCLK0_INPUT_FREQUENCY 20000 CT#CLK4_DUTY_CYCLE 50 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT -1806 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 6 CT#INTENDED_DEVICE_FAMILY {Cyclone IV E} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#CLK3_MULTIPLY_BY 4 CT#PORT_LOCKED PORT_USED</parameter>
+  <parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT4 MHz PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK4 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT4 deg PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#OUTPUT_FREQ_MODE4 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ4 2.00000000 PT#OUTPUT_FREQ3 40.00000000 PT#OUTPUT_FREQ2 60.00000000 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 6 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#PHASE_SHIFT4 0.00000000 PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 0.00000000 PT#DIV_FACTOR4 1 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 1 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT1 -65.00000000 PT#DIV_FACTOR1 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA4 0 PT#USE_CLKENA3 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE4 2.000000 PT#EFF_OUTPUT_FREQ_VALUE3 40.000000 PT#EFF_OUTPUT_FREQ_VALUE2 60.000000 PT#EFF_OUTPUT_FREQ_VALUE1 100.000000 PT#EFF_OUTPUT_FREQ_VALUE0 100.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 1 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#MIRROR_CLK4 0 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK3 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT4 deg PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR4 1 PT#MULT_FACTOR3 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE4 50.00000000 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Cyclone IV E} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1290674183995785.mif PT#ACTIVECLK_CHECK 0</parameter>
+  <parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c4 used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
+  <parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK4_MULTIPLY_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#CLK4_DIVIDE_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR4 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK4_DUTY_CYCLE 1 IN#CLK2_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR4 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
+  <parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
+  <parameter name="HIDDEN_IF_PORTS">IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#c2 {output 0} IF#address {input 2} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}</parameter>
+  <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
+  <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="50000000" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
+ </module>
+ <module
+   kind="altera_avalon_pio"
+   version="13.0.1.99.2"
+   enabled="1"
+   name="g_sensor_int">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="true" />
+  <parameter name="direction" value="Input" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="true" />
+  <parameter name="irqType" value="EDGE" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="1" />
+  <parameter name="clockRate" value="60000000" />
+ </module>
+ <module
+   kind="altera_avalon_epcs_flash_controller"
+   version="13.0.1.99.2"
+   enabled="1"
+   name="epcs">
+  <parameter name="autoSelectASMIAtom" value="true" />
+  <parameter name="useASMIAtom" value="false" />
+  <parameter name="clockRate" value="100000000" />
+  <parameter name="deviceFamilyString" value="Cyclone IV E" />
+  <parameter name="autoInitializationFileName" value="DE0_Nano_SOPC_epcs" />
+ </module>
+ <module
+   kind="altera_avalon_jtag_uart"
+   version="13.0.1.99.2"
+   enabled="1"
+   name="jtag_uart">
+  <parameter name="allowMultipleConnections" value="false" />
+  <parameter name="hubInstanceID" value="0" />
+  <parameter name="readBufferDepth" value="64" />
+  <parameter name="readIRQThreshold" value="8" />
+  <parameter name="simInputCharacterStream" value="" />
+  <parameter name="simInteractiveOptions">INTERACTIVE_ASCII_OUTPUT</parameter>
+  <parameter name="useRegistersForReadBuffer" value="true" />
+  <parameter name="useRegistersForWriteBuffer" value="true" />
+  <parameter name="useRelativePathForSimFile" value="false" />
+  <parameter name="writeBufferDepth" value="64" />
+  <parameter name="writeIRQThreshold" value="8" />
+  <parameter name="avalonSpec" value="2.0" />
+ </module>
+ <module kind="TERASIC_ADC_READ" version="1.0" enabled="1" name="adc_spi_read">
+  <parameter name="AUTO_CLOCK_CLOCK_RATE" value="2000000" />
+ </module>
+ <module kind="TERASIC_SPI_3WIRE" version="1.0" enabled="1" name="gsensor_spi">
+  <parameter name="AUTO_CLOCK_RESET_CLOCK_RATE" value="50000000" />
+ </module>
+ <module
+   kind="altera_avalon_pio"
+   version="13.0.1.99.2"
+   enabled="1"
+   name="select_i2c_clk">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="1" />
+  <parameter name="clockRate" value="60000000" />
+ </module>
+ <module
+   kind="altera_avalon_mm_clock_crossing_bridge"
+   version="13.0"
+   enabled="1"
+   name="clock_crossing_io">
+  <parameter name="DATA_WIDTH" value="32" />
+  <parameter name="SYMBOL_WIDTH" value="8" />
+  <parameter name="ADDRESS_WIDTH" value="10" />
+  <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
+  <parameter name="MAX_BURST_SIZE" value="1" />
+  <parameter name="COMMAND_FIFO_DEPTH" value="16" />
+  <parameter name="RESPONSE_FIFO_DEPTH" value="32" />
+  <parameter name="MASTER_SYNC_DEPTH" value="3" />
+  <parameter name="SLAVE_SYNC_DEPTH" value="3" />
+  <parameter name="AUTO_M0_CLK_CLOCK_RATE" value="60000000" />
+  <parameter name="AUTO_S0_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
+ </module>
+ <module
+   kind="altera_avalon_mm_clock_crossing_bridge"
+   version="13.0"
+   enabled="1"
+   name="clock_crossing_io2">
+  <parameter name="DATA_WIDTH" value="32" />
+  <parameter name="SYMBOL_WIDTH" value="8" />
+  <parameter name="ADDRESS_WIDTH" value="12" />
+  <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
+  <parameter name="MAX_BURST_SIZE" value="1" />
+  <parameter name="COMMAND_FIFO_DEPTH" value="16" />
+  <parameter name="RESPONSE_FIFO_DEPTH" value="64" />
+  <parameter name="MASTER_SYNC_DEPTH" value="3" />
+  <parameter name="SLAVE_SYNC_DEPTH" value="3" />
+  <parameter name="AUTO_M0_CLK_CLOCK_RATE" value="50000000" />
+  <parameter name="AUTO_S0_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
+ </module>
+ <module kind="altera_nios2_qsys" version="13.0" enabled="1" name="cpu">
+  <parameter name="setting_showUnpublishedSettings" value="false" />
+  <parameter name="setting_showInternalSettings" value="false" />
+  <parameter name="setting_preciseSlaveAccessErrorException" value="false" />
+  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+  <parameter name="setting_preciseDivisionErrorException" value="true" />
+  <parameter name="setting_performanceCounter" value="false" />
+  <parameter name="setting_illegalMemAccessDetection" value="false" />
+  <parameter name="setting_illegalInstructionsTrap" value="false" />
+  <parameter name="setting_fullWaveformSignals" value="false" />
+  <parameter name="setting_extraExceptionInfo" value="false" />
+  <parameter name="setting_exportPCB" value="false" />
+  <parameter name="setting_debugSimGen" value="false" />
+  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+  <parameter name="setting_bit31BypassDCache" value="true" />
+  <parameter name="setting_bigEndian" value="false" />
+  <parameter name="setting_export_large_RAMs" value="false" />
+  <parameter name="setting_asic_enabled" value="false" />
+  <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
+  <parameter name="setting_oci_export_jtag_signals" value="false" />
+  <parameter name="setting_bhtIndexPcOnly" value="false" />
+  <parameter name="setting_avalonDebugPortPresent" value="false" />
+  <parameter name="setting_alwaysEncrypt" value="true" />
+  <parameter name="setting_allowFullAddressRange" value="false" />
+  <parameter name="setting_activateTrace" value="true" />
+  <parameter name="setting_activateTestEndChecker" value="false" />
+  <parameter name="setting_activateMonitors" value="true" />
+  <parameter name="setting_activateModelChecker" value="false" />
+  <parameter name="setting_HDLSimCachesCleared" value="true" />
+  <parameter name="setting_HBreakTest" value="false" />
+  <parameter name="muldiv_divider" value="true" />
+  <parameter name="mpu_useLimit" value="false" />
+  <parameter name="mpu_enabled" value="false" />
+  <parameter name="mmu_enabled" value="false" />
+  <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
+  <parameter name="manuallyAssignCpuID" value="false" />
+  <parameter name="debug_triggerArming" value="true" />
+  <parameter name="debug_embeddedPLL" value="true" />
+  <parameter name="debug_debugReqSignals" value="false" />
+  <parameter name="debug_assignJtagInstanceID" value="false" />
+  <parameter name="dcache_omitDataMaster" value="false" />
+  <parameter name="cpuReset" value="false" />
+  <parameter name="is_hardcopy_compatible" value="false" />
+  <parameter name="setting_shadowRegisterSets" value="0" />
+  <parameter name="mpu_numOfInstRegion" value="16" />
+  <parameter name="mpu_numOfDataRegion" value="16" />
+  <parameter name="mmu_TLBMissExcOffset" value="0" />
+  <parameter name="debug_jtagInstanceID" value="0" />
+  <parameter name="resetOffset" value="0" />
+  <parameter name="exceptionOffset" value="32" />
+  <parameter name="cpuID" value="0" />
+  <parameter name="cpuID_stored" value="0" />
+  <parameter name="breakOffset" value="32" />
+  <parameter name="userDefinedSettings" value="" />
+  <parameter name="resetSlave">epcs.epcs_control_port</parameter>
+  <parameter name="mmu_TLBMissExcSlave" value="" />
+  <parameter name="exceptionSlave" value="sdram.s1" />
+  <parameter name="breakSlave">cpu.jtag_debug_module</parameter>
+  <parameter name="setting_perfCounterWidth" value="32" />
+  <parameter name="setting_interruptControllerType" value="External" />
+  <parameter name="setting_branchPredictionType" value="Automatic" />
+  <parameter name="setting_bhtPtrSz" value="8" />
+  <parameter name="muldiv_multiplierType" value="EmbeddedMulFast" />
+  <parameter name="mpu_minInstRegionSize" value="6" />
+  <parameter name="mpu_minDataRegionSize" value="6" />
+  <parameter name="mmu_uitlbNumEntries" value="4" />
+  <parameter name="mmu_udtlbNumEntries" value="6" />
+  <parameter name="mmu_tlbPtrSz" value="7" />
+  <parameter name="mmu_tlbNumWays" value="16" />
+  <parameter name="mmu_processIDNumBits" value="8" />
+  <parameter name="impl" value="Fast" />
+  <parameter name="icache_size" value="4096" />
+  <parameter name="icache_tagramBlockType" value="Automatic" />
+  <parameter name="icache_ramBlockType" value="Automatic" />
+  <parameter name="icache_numTCIM" value="0" />
+  <parameter name="icache_burstType" value="Sequential" />
+  <parameter name="dcache_bursts" value="false" />
+  <parameter name="dcache_victim_buf_impl" value="ram" />
+  <parameter name="debug_level" value="Level1" />
+  <parameter name="debug_OCIOnchipTrace" value="_128" />
+  <parameter name="dcache_size" value="0" />
+  <parameter name="dcache_tagramBlockType" value="Automatic" />
+  <parameter name="dcache_ramBlockType" value="Automatic" />
+  <parameter name="dcache_numTCDM" value="0" />
+  <parameter name="dcache_lineSize" value="32" />
+  <parameter name="setting_exportvectors" value="false" />
+  <parameter name="setting_ecc_present" value="false" />
+  <parameter name="regfile_ramBlockType" value="Automatic" />
+  <parameter name="ocimem_ramBlockType" value="Automatic" />
+  <parameter name="mmu_ramBlockType" value="Automatic" />
+  <parameter name="bht_ramBlockType" value="Automatic" />
+  <parameter name="instAddrWidth" value="26" />
+  <parameter name="dataAddrWidth" value="28" />
+  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='sdram.s1' start='0x0' end='0x2000000' /><slave name='cpu.jtag_debug_module' start='0x2000000' end='0x2000800' /><slave name='epcs.epcs_control_port' start='0x3000000' end='0x3000800' /></address-map>]]></parameter>
+  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sdram.s1' start='0x0' end='0x2000000' /><slave name='cpu.jtag_debug_module' start='0x2000000' end='0x2000800' /><slave name='uart_0.s1' start='0x2000D00' end='0x2000D20' /><slave name='uart_1.s1' start='0x2000D40' end='0x2000D60' /><slave name='epcs.epcs_control_port' start='0x3000000' end='0x3000800' /><slave name='altpll_sys.pll_slave' start='0x6001000' end='0x6001010' /><slave name='adc_spi_read.slave' start='0x6001018' end='0x600101C' /><slave name='gsensor_spi.slave' start='0x7000800' end='0x7000840' /><slave name='i2c_sda.s1' start='0x7000840' end='0x7000850' /><slave name='i2c_scl.s1' start='0x7000850' end='0x7000860' /><slave name='key.s1' start='0x8000020' end='0x8000030' /><slave name='led.s1' start='0x8000030' end='0x8000040' /><slave name='sw.s1' start='0x8000040' end='0x8000050' /><slave name='g_sensor_int.s1' start='0x8000050' end='0x8000060' /><slave name='select_i2c_clk.s1' start='0x8000060' end='0x8000070' /><slave name='pio.s1' start='0x8000080' end='0x8000090' /><slave name='multi_pwm_0.avalon_slave_0' start='0x80000A0' end='0x80000C0' /><slave name='jtag_uart.avalon_jtag_slave' start='0x80001A0' end='0x80001A8' /><slave name='sysver_0.avalon_slave_0' start='0x80001C0' end='0x80001E0' /><slave name='timer_0.s1' start='0x8000200' end='0x8000220' /><slave name='timer_1.s1' start='0x8000220' end='0x8000240' /><slave name='timer_2.s1' start='0x8000240' end='0x8000260' /><slave name='timer_3.s1' start='0x8000260' end='0x8000280' /><slave name='can_top_0.avalon_slave_0' start='0x8020000' end='0x8020400' /><slave name='vic_0.csr_access' start='0xF000000' end='0xF000400' /></address-map>]]></parameter>
+  <parameter name="clockFrequency" value="100000000" />
+  <parameter name="deviceFamilyName" value="Cyclone IV E" />
+  <parameter name="internalIrqMaskSystemInfo" value="0" />
+  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
+  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+ </module>
+ <module
+   kind="altera_avalon_sysid_qsys"
+   version="13.0"
+   enabled="0"
+   name="sysid">
+  <parameter name="id" value="0" />
+  <parameter name="timestamp" value="0" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="60000000" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
+ </module>
+ <module kind="altera_clock_bridge" version="13.0" enabled="1" name="c0">
+  <parameter name="DERIVED_CLOCK_RATE" value="100000000" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module kind="altera_clock_bridge" version="13.0" enabled="1" name="c2">
+  <parameter name="DERIVED_CLOCK_RATE" value="60000000" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module kind="altera_clock_bridge" version="13.0" enabled="1" name="c4">
+  <parameter name="DERIVED_CLOCK_RATE" value="2000000" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module kind="sysver" version="1.0" enabled="1" name="sysver_0">
+  <parameter name="VER1_ROM_REG_VALUE" value="7" />
+  <parameter name="VER2_ROM_REG_VALUE" value="0" />
+  <parameter name="VER3_ROM_REG_VALUE" value="1" />
+  <parameter name="VER4_ROM_REG_VALUE" value="0" />
+  <parameter name="VER5_RAM_REG_VALUE" value="0" />
+  <parameter name="VER6_RAM_REG_VALUE" value="0" />
+  <parameter name="VER7_RAM_REG_VALUE" value="0" />
+  <parameter name="VER8_RAM_REG_VALUE" value="0" />
+  <parameter name="AUTO_CLOCK_RESET_CLOCK_RATE" value="60000000" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
+ </module>
+ <module
+   kind="altera_avalon_timer"
+   version="13.0.1.99.2"
+   enabled="1"
+   name="timer_0">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="systemFrequency" value="60000000" />
+ </module>
+ <module
+   kind="altera_avalon_timer"
+   version="13.0.1.99.2"
+   enabled="1"
+   name="timer_1">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="systemFrequency" value="60000000" />
+ </module>
+ <module
+   kind="altera_avalon_timer"
+   version="13.0.1.99.2"
+   enabled="1"
+   name="timer_2">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="systemFrequency" value="60000000" />
+ </module>
+ <module
+   kind="altera_avalon_timer"
+   version="13.0.1.99.2"
+   enabled="1"
+   name="timer_3">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="systemFrequency" value="60000000" />
+ </module>
+ <module
+   kind="altera_avalon_timer"
+   version="13.0.1.99.2"
+   enabled="0"
+   name="timer_4">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="systemFrequency" value="60000000" />
+ </module>
+ <module
+   kind="altera_avalon_timer"
+   version="13.0.1.99.2"
+   enabled="0"
+   name="timer_5">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="systemFrequency" value="60000000" />
+ </module>
+ <module
+   kind="altera_avalon_timer"
+   version="13.0.1.99.2"
+   enabled="0"
+   name="timer_6">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="systemFrequency" value="60000000" />
+ </module>
+ <module
+   kind="altera_avalon_timer"
+   version="13.0.1.99.2"
+   enabled="0"
+   name="timer_7">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="systemFrequency" value="60000000" />
+ </module>
+ <module
+   kind="altera_avalon_timer"
+   version="13.0.1.99.2"
+   enabled="0"
+   name="timer_8">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="systemFrequency" value="60000000" />
+ </module>
+ <module
+   kind="altera_avalon_timer"
+   version="13.0.1.99.2"
+   enabled="0"
+   name="timer_9">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="systemFrequency" value="60000000" />
+ </module>
+ <module
+   kind="altera_avalon_timer"
+   version="13.0.1.99.2"
+   enabled="0"
+   name="timer_10">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="systemFrequency" value="60000000" />
+ </module>
+ <module
+   kind="altera_avalon_timer"
+   version="13.0.1.99.2"
+   enabled="0"
+   name="timer_11">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="systemFrequency" value="60000000" />
+ </module>
+ <module
+   kind="altera_avalon_timer"
+   version="13.0.1.99.2"
+   enabled="0"
+   name="timer_12">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="systemFrequency" value="60000000" />
+ </module>
+ <module
+   kind="altera_avalon_timer"
+   version="13.0.1.99.2"
+   enabled="0"
+   name="timer_13">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="systemFrequency" value="60000000" />
+ </module>
+ <module
+   kind="altera_avalon_timer"
+   version="13.0.1.99.2"
+   enabled="0"
+   name="timer_14">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="systemFrequency" value="60000000" />
+ </module>
+ <module
+   kind="altera_avalon_timer"
+   version="13.0.1.99.2"
+   enabled="0"
+   name="timer_15">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="systemFrequency" value="60000000" />
+ </module>
+ <module
+   kind="altera_avalon_onchip_memory2"
+   version="13.0.1.99.2"
+   enabled="0"
+   name="sram_dummy">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="dataWidth" value="32" />
+  <parameter name="dualPort" value="false" />
+  <parameter name="initMemContent" value="true" />
+  <parameter name="initializationFileName" value="onchip_mem.hex" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="32768" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+  <parameter name="autoInitializationFileName">DE0_Nano_SOPC_sram_dummy</parameter>
+  <parameter name="deviceFamily" value="Cyclone IV E" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+ </module>
+ <module kind="altera_vic" version="13.0" enabled="1" name="vic_0">
+  <parameter name="NUMBER_OF_INT_PORTS" value="32" />
+  <parameter name="RIL_WIDTH" value="6" />
+  <parameter name="DAISY_CHAIN_ENABLE" value="0" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
+  <parameter name="AUTO_DEVICE" value="EP4CE22F17C6" />
+ </module>
+ <module kind="can_top" version="2.6" enabled="1" name="can_top_0">
+  <parameter name="Tp" value="1" />
+  <parameter name="TXMBOX_DEPTH" value="1" />
+  <parameter name="RXMBOX_DEPTH" value="1" />
+  <parameter name="AUTO_CLOCK_CLOCK_RATE" value="50000000" />
+ </module>
+ <module
+   kind="altera_avalon_uart"
+   version="13.0.1.99.2"
+   enabled="1"
+   name="uart_0">
+  <parameter name="baud" value="115200" />
+  <parameter name="dataBits" value="8" />
+  <parameter name="fixedBaud" value="true" />
+  <parameter name="parity" value="NONE" />
+  <parameter name="simCharStream" value="" />
+  <parameter name="simInteractiveInputEnable" value="false" />
+  <parameter name="simInteractiveOutputEnable" value="false" />
+  <parameter name="simTrueBaud" value="false" />
+  <parameter name="stopBits" value="1" />
+  <parameter name="syncRegDepth" value="2" />
+  <parameter name="useCtsRts" value="false" />
+  <parameter name="useEopRegister" value="false" />
+  <parameter name="useRelativePathForSimFile" value="false" />
+  <parameter name="clockRate" value="100000000" />
+ </module>
+ <module
+   kind="altera_avalon_uart"
+   version="13.0.1.99.2"
+   enabled="1"
+   name="uart_1">
+  <parameter name="baud" value="115200" />
+  <parameter name="dataBits" value="8" />
+  <parameter name="fixedBaud" value="true" />
+  <parameter name="parity" value="NONE" />
+  <parameter name="simCharStream" value="" />
+  <parameter name="simInteractiveInputEnable" value="false" />
+  <parameter name="simInteractiveOutputEnable" value="false" />
+  <parameter name="simTrueBaud" value="false" />
+  <parameter name="stopBits" value="1" />
+  <parameter name="syncRegDepth" value="2" />
+  <parameter name="useCtsRts" value="false" />
+  <parameter name="useEopRegister" value="false" />
+  <parameter name="useRelativePathForSimFile" value="false" />
+  <parameter name="clockRate" value="100000000" />
+ </module>
+ <module kind="altera_avalon_pio" version="13.0.1.99.2" enabled="1" name="pio">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="8" />
+  <parameter name="clockRate" value="60000000" />
+ </module>
+ <module kind="multi_pwm" version="1.0" enabled="1" name="multi_pwm_0">
+  <parameter name="W" value="32" />
+  <parameter name="AUTO_CLOCK_RESET_CLOCK_RATE" value="60000000" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
+ </module>
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="cpu.instruction_master"
+   end="cpu.jtag_debug_module">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x02000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="cpu.data_master"
+   end="cpu.jtag_debug_module">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x02000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="13.0"
+   start="clk_50.clk"
+   end="altpll_sys.inclk_interface" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="cpu.data_master"
+   end="altpll_sys.pll_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x06001000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="13.0" start="altpll_sys.c0" end="cpu.clk" />
+ <connection kind="clock" version="13.0" start="altpll_sys.c2" end="sysid.clk" />
+ <connection
+   kind="clock"
+   version="13.0"
+   start="altpll_sys.c2"
+   end="sys_clk_timer.clk" />
+ <connection kind="clock" version="13.0" start="altpll_sys.c2" end="key.clk" />
+ <connection kind="clock" version="13.0" start="altpll_sys.c2" end="sw.clk" />
+ <connection kind="clock" version="13.0" start="altpll_sys.c2" end="led.clk" />
+ <connection kind="avalon" version="13.0" start="cpu.data_master" end="sdram.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="13.0" start="altpll_sys.c0" end="sdram.clk" />
+ <connection
+   kind="clock"
+   version="13.0"
+   start="altpll_sys.c2"
+   end="g_sensor_int.clk" />
+ <connection kind="clock" version="13.0" start="clk_50.clk" end="i2c_scl.clk" />
+ <connection kind="clock" version="13.0" start="clk_50.clk" end="i2c_sda.clk" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="cpu.data_master"
+   end="adc_spi_read.slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x06001018" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="13.0"
+   start="altpll_sys.c4"
+   end="adc_spi_read.clock" />
+ <connection
+   kind="clock"
+   version="13.0"
+   start="clk_50.clk"
+   end="gsensor_spi.clock_reset" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="cpu.instruction_master"
+   end="sdram.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="13.0"
+   start="altpll_sys.c2"
+   end="select_i2c_clk.clk" />
+ <connection
+   kind="clock"
+   version="13.0"
+   start="altpll_sys.c2"
+   end="clock_crossing_io.m0_clk" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="cpu.data_master"
+   end="clock_crossing_io.s0">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x08000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io.m0"
+   end="sys_clk_timer.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io.m0"
+   end="sysid.control_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0070" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io.m0"
+   end="key.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0020" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io.m0"
+   end="led.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0030" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="avalon" version="13.0" start="clock_crossing_io.m0" end="sw.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0040" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io.m0"
+   end="g_sensor_int.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0050" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io.m0"
+   end="select_i2c_clk.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0060" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="13.0"
+   start="clk_50.clk"
+   end="clock_crossing_io2.m0_clk" />
+ <connection
+   kind="clock"
+   version="13.0"
+   start="altpll_sys.c0"
+   end="clock_crossing_io2.s0_clk" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="cpu.data_master"
+   end="clock_crossing_io2.s0">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x07000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io2.m0"
+   end="i2c_sda.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0840" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io2.m0"
+   end="i2c_scl.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0850" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io2.m0"
+   end="gsensor_spi.slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0800" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="sys_clk_timer.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="sys_clk_timer.reset" />
+ <connection kind="reset" version="13.0" start="clk_50.clk_reset" end="key.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="key.reset" />
+ <connection kind="reset" version="13.0" start="clk_50.clk_reset" end="sw.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="sw.reset" />
+ <connection kind="reset" version="13.0" start="clk_50.clk_reset" end="led.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="led.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="i2c_scl.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="i2c_scl.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="i2c_sda.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="i2c_sda.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="sdram.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="sdram.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="altpll_sys.inclk_interface_reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="altpll_sys.inclk_interface_reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="g_sensor_int.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="g_sensor_int.reset" />
+ <connection kind="reset" version="13.0" start="clk_50.clk_reset" end="epcs.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="epcs.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="jtag_uart.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="jtag_uart.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="adc_spi_read.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="adc_spi_read.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="gsensor_spi.clock_reset_reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="gsensor_spi.clock_reset_reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="select_i2c_clk.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="select_i2c_clk.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="clock_crossing_io.m0_reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="clock_crossing_io.m0_reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="clock_crossing_io.s0_reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="clock_crossing_io.s0_reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="clock_crossing_io2.m0_reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="clock_crossing_io2.m0_reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="clock_crossing_io2.s0_reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="clock_crossing_io2.s0_reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="sysid.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="sysid.reset" />
+ <connection kind="clock" version="13.0" start="altpll_sys.c0" end="c0.in_clk" />
+ <connection kind="clock" version="13.0" start="altpll_sys.c2" end="c2.in_clk" />
+ <connection kind="clock" version="13.0" start="altpll_sys.c4" end="c4.in_clk" />
+ <connection kind="clock" version="13.0" start="altpll_sys.c2" end="jtag_uart.clk" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io.m0"
+   end="jtag_uart.avalon_jtag_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x01a0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="13.0"
+   start="altpll_sys.c2"
+   end="sysver_0.clock_reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="sysver_0.clock_reset_reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="sysver_0.clock_reset_reset" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io.m0"
+   end="sysver_0.avalon_slave_0">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x01c0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="13.0" start="altpll_sys.c2" end="timer_0.clk" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="timer_0.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="timer_0.reset" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io.m0"
+   end="timer_0.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0200" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="13.0" start="altpll_sys.c2" end="timer_1.clk" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="timer_1.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="timer_1.reset" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io.m0"
+   end="timer_1.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0220" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="13.0" start="altpll_sys.c2" end="timer_2.clk" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="timer_2.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="timer_2.reset" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io.m0"
+   end="timer_2.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0240" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="13.0" start="altpll_sys.c2" end="timer_3.clk" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="timer_3.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="timer_3.reset" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io.m0"
+   end="timer_3.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0260" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="13.0" start="altpll_sys.c2" end="timer_4.clk" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="timer_4.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="timer_4.reset" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io.m0"
+   end="timer_4.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0280" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="13.0" start="altpll_sys.c2" end="timer_5.clk" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="timer_5.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="timer_5.reset" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io.m0"
+   end="timer_5.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x02a0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="13.0" start="altpll_sys.c2" end="timer_6.clk" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="timer_6.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="timer_6.reset" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io.m0"
+   end="timer_6.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x02c0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="13.0" start="altpll_sys.c2" end="timer_7.clk" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="timer_7.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="timer_7.reset" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io.m0"
+   end="timer_7.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x02e0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="13.0" start="altpll_sys.c2" end="timer_8.clk" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="timer_8.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="timer_8.reset" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io.m0"
+   end="timer_8.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0300" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="13.0" start="altpll_sys.c2" end="timer_9.clk" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="timer_9.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="timer_9.reset" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io.m0"
+   end="timer_9.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0320" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="13.0" start="altpll_sys.c2" end="timer_10.clk" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="timer_10.reset" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io.m0"
+   end="timer_10.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0340" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="timer_10.reset" />
+ <connection kind="clock" version="13.0" start="altpll_sys.c2" end="timer_11.clk" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="timer_11.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="timer_11.reset" />
+ <connection kind="clock" version="13.0" start="altpll_sys.c2" end="timer_12.clk" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io.m0"
+   end="timer_11.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0360" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="timer_12.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="timer_12.reset" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io.m0"
+   end="timer_12.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0380" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="13.0" start="altpll_sys.c2" end="timer_13.clk" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="timer_13.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="timer_13.reset" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io.m0"
+   end="timer_13.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x03a0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="13.0" start="altpll_sys.c2" end="timer_14.clk" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="timer_14.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="timer_14.reset" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io.m0"
+   end="timer_14.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x03c0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="13.0" start="altpll_sys.c2" end="timer_15.clk" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="timer_15.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="timer_15.reset" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io.m0"
+   end="timer_15.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x03e0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="13.0"
+   start="altpll_sys.c0"
+   end="sram_dummy.clk1" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="cpu.instruction_master"
+   end="sram_dummy.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x05000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="cpu.data_master"
+   end="sram_dummy.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x05000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="sram_dummy.reset1" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="sram_dummy.reset1" />
+ <connection kind="clock" version="13.0" start="altpll_sys.c0" end="vic_0.clk" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="vic_0.clk_reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="vic_0.clk_reset" />
+ <connection
+   kind="interrupt"
+   version="13.0"
+   start="vic_0.irq_input"
+   end="jtag_uart.irq">
+  <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="13.0"
+   start="vic_0.irq_input"
+   end="sys_clk_timer.irq">
+  <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection kind="interrupt" version="13.0" start="vic_0.irq_input" end="key.irq">
+  <parameter name="irqNumber" value="2" />
+ </connection>
+ <connection kind="interrupt" version="13.0" start="vic_0.irq_input" end="sw.irq">
+  <parameter name="irqNumber" value="3" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="13.0"
+   start="vic_0.irq_input"
+   end="g_sensor_int.irq">
+  <parameter name="irqNumber" value="4" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="13.0"
+   start="vic_0.irq_input"
+   end="timer_0.irq">
+  <parameter name="irqNumber" value="16" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="13.0"
+   start="vic_0.irq_input"
+   end="timer_1.irq">
+  <parameter name="irqNumber" value="17" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="13.0"
+   start="vic_0.irq_input"
+   end="timer_2.irq">
+  <parameter name="irqNumber" value="18" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="13.0"
+   start="vic_0.irq_input"
+   end="timer_3.irq">
+  <parameter name="irqNumber" value="19" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="13.0"
+   start="vic_0.irq_input"
+   end="timer_4.irq">
+  <parameter name="irqNumber" value="20" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="13.0"
+   start="vic_0.irq_input"
+   end="timer_5.irq">
+  <parameter name="irqNumber" value="21" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="13.0"
+   start="vic_0.irq_input"
+   end="timer_6.irq">
+  <parameter name="irqNumber" value="22" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="13.0"
+   start="vic_0.irq_input"
+   end="timer_7.irq">
+  <parameter name="irqNumber" value="23" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="13.0"
+   start="vic_0.irq_input"
+   end="timer_8.irq">
+  <parameter name="irqNumber" value="24" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="13.0"
+   start="vic_0.irq_input"
+   end="timer_9.irq">
+  <parameter name="irqNumber" value="25" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="13.0"
+   start="vic_0.irq_input"
+   end="timer_10.irq">
+  <parameter name="irqNumber" value="26" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="13.0"
+   start="vic_0.irq_input"
+   end="timer_11.irq">
+  <parameter name="irqNumber" value="27" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="13.0"
+   start="vic_0.irq_input"
+   end="timer_12.irq">
+  <parameter name="irqNumber" value="28" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="13.0"
+   start="vic_0.irq_input"
+   end="timer_13.irq">
+  <parameter name="irqNumber" value="29" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="13.0"
+   start="vic_0.irq_input"
+   end="timer_14.irq">
+  <parameter name="irqNumber" value="30" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="13.0"
+   start="vic_0.irq_input"
+   end="timer_15.irq">
+  <parameter name="irqNumber" value="31" />
+ </connection>
+ <connection
+   kind="avalon_streaming"
+   version="13.0"
+   start="vic_0.interrupt_controller_out"
+   end="cpu.interrupt_controller_in" />
+ <connection
+   kind="interrupt"
+   version="13.0"
+   start="vic_0.irq_input"
+   end="epcs.irq">
+  <parameter name="irqNumber" value="5" />
+ </connection>
+ <connection
+   kind="clock"
+   version="13.0"
+   start="altpll_sys.c0"
+   end="clock_crossing_io.s0_clk" />
+ <connection kind="clock" version="13.0" start="clk_50.clk" end="can_top_0.clock" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="can_top_0.clock_reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="can_top_0.clock_reset" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="cpu.data_master"
+   end="can_top_0.avalon_slave_0">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x08020000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="13.0"
+   start="vic_0.irq_input"
+   end="can_top_0.interrupt_sender">
+  <parameter name="irqNumber" value="10" />
+ </connection>
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="uart_0.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="uart_0.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="uart_1.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="uart_1.reset" />
+ <connection
+   kind="interrupt"
+   version="13.0"
+   start="vic_0.irq_input"
+   end="uart_0.irq">
+  <parameter name="irqNumber" value="6" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="13.0"
+   start="vic_0.irq_input"
+   end="uart_1.irq">
+  <parameter name="irqNumber" value="7" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="cpu.data_master"
+   end="epcs.epcs_control_port">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x03000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="cpu.instruction_master"
+   end="epcs.epcs_control_port">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x03000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="13.0" start="altpll_sys.c0" end="epcs.clk" />
+ <connection kind="clock" version="13.0" start="altpll_sys.c2" end="pio.clk" />
+ <connection kind="reset" version="13.0" start="clk_50.clk_reset" end="pio.reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="pio.reset" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io.m0"
+   end="pio.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0080" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="13.0" start="altpll_sys.c0" end="uart_0.clk" />
+ <connection kind="clock" version="13.0" start="altpll_sys.c0" end="uart_1.clk" />
+ <connection kind="avalon" version="13.0" start="cpu.data_master" end="uart_0.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x02000d00" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="avalon" version="13.0" start="cpu.data_master" end="uart_1.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x02000d40" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="cpu.data_master"
+   end="vic_0.csr_access">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0f000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="multi_pwm_0.clock_reset_reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="multi_pwm_0.clock_reset_reset" />
+ <connection
+   kind="avalon"
+   version="13.0"
+   start="clock_crossing_io.m0"
+   end="multi_pwm_0.avalon_slave_0">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00a0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="13.0"
+   start="altpll_sys.c2"
+   end="multi_pwm_0.clock_reset" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="clk_50.clk_reset"
+   end="cpu.reset_n" />
+ <connection
+   kind="reset"
+   version="13.0"
+   start="cpu.jtag_debug_module_reset"
+   end="cpu.reset_n" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="0" />
+</system>
Index: /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/can_top_hw.tcl
===================================================================
--- /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/can_top_hw.tcl	(revision 295)
+++ /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/can_top_hw.tcl	(revision 295)
@@ -0,0 +1,198 @@
+# TCL File Generated by Component Editor 11.0sp1
+# Tue Jun 17 13:13:43 JST 2014
+# DO NOT MODIFY
+
+
+# +-----------------------------------
+# | 
+# | can_top "can_top" v2.6
+# | null 2014.06.17.13:13:43
+# | 
+# | 
+# | F:/Sync/DE2_115_NIOS_DEVICE_LED_MATSU_restored_ACAN/DE2_115_NIOS_DEVICE_LED_MATSU_restored/canc/hdl/can_top.v
+# | 
+# |    ./hdl/can_acf.v syn, sim
+# |    ./hdl/can_bsp.v syn, sim
+# |    ./hdl/can_btl.v syn, sim
+# |    ./hdl/can_crc.v syn, sim
+# |    ./hdl/can_defines.v syn, sim
+# |    ./hdl/can_fifo.v syn, sim
+# |    ./hdl/can_ibo.v syn, sim
+# |    ./hdl/can_register.v syn, sim
+# |    ./hdl/can_register_asyn.v syn, sim
+# |    ./hdl/can_register_asyn_syn.v syn, sim
+# |    ./hdl/can_register_syn.v syn, sim
+# |    ./hdl/can_registers.v syn, sim
+# |    ./hdl/can_rxmboxacf.v syn, sim
+# |    ./hdl/can_top.v syn, sim
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | request TCL package from ACDS 11.0
+# | 
+package require -exact sopc 11.0
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | module can_top
+# | 
+set_module_property NAME can_top
+set_module_property VERSION 2.6
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP Other
+set_module_property DISPLAY_NAME can_top
+set_module_property TOP_LEVEL_HDL_FILE hdl/can_top.v
+set_module_property TOP_LEVEL_HDL_MODULE can_top
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property ANALYZE_HDL TRUE
+set_module_property STATIC_TOP_LEVEL_MODULE_NAME can_top
+set_module_property FIX_110_VIP_PATH false
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | files
+# | 
+add_file hdl/can_acf.v {SYNTHESIS SIMULATION}
+add_file hdl/can_bsp.v {SYNTHESIS SIMULATION}
+add_file hdl/can_btl.v {SYNTHESIS SIMULATION}
+add_file hdl/can_crc.v {SYNTHESIS SIMULATION}
+add_file hdl/can_defines.v {SYNTHESIS SIMULATION}
+add_file hdl/can_fifo.v {SYNTHESIS SIMULATION}
+add_file hdl/can_ibo.v {SYNTHESIS SIMULATION}
+add_file hdl/can_register.v {SYNTHESIS SIMULATION}
+add_file hdl/can_register_asyn.v {SYNTHESIS SIMULATION}
+add_file hdl/can_register_asyn_syn.v {SYNTHESIS SIMULATION}
+add_file hdl/can_register_syn.v {SYNTHESIS SIMULATION}
+add_file hdl/can_registers.v {SYNTHESIS SIMULATION}
+add_file hdl/can_rxmboxacf.v {SYNTHESIS SIMULATION}
+add_file hdl/can_top.v {SYNTHESIS SIMULATION}
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | parameters
+# | 
+add_parameter Tp INTEGER 1
+set_parameter_property Tp DEFAULT_VALUE 1
+set_parameter_property Tp DISPLAY_NAME Tp
+set_parameter_property Tp TYPE INTEGER
+set_parameter_property Tp UNITS None
+set_parameter_property Tp ALLOWED_RANGES -2147483648:2147483647
+set_parameter_property Tp AFFECTS_GENERATION false
+set_parameter_property Tp HDL_PARAMETER true
+add_parameter TXMBOX_DEPTH INTEGER 4 ""
+set_parameter_property TXMBOX_DEPTH DEFAULT_VALUE 4
+set_parameter_property TXMBOX_DEPTH DISPLAY_NAME TXMBOX_DEPTH
+set_parameter_property TXMBOX_DEPTH TYPE INTEGER
+set_parameter_property TXMBOX_DEPTH UNITS None
+set_parameter_property TXMBOX_DEPTH ALLOWED_RANGES -2147483648:2147483647
+set_parameter_property TXMBOX_DEPTH DESCRIPTION ""
+set_parameter_property TXMBOX_DEPTH AFFECTS_GENERATION false
+set_parameter_property TXMBOX_DEPTH HDL_PARAMETER true
+add_parameter RXMBOX_DEPTH INTEGER 5 ""
+set_parameter_property RXMBOX_DEPTH DEFAULT_VALUE 5
+set_parameter_property RXMBOX_DEPTH DISPLAY_NAME RXMBOX_DEPTH
+set_parameter_property RXMBOX_DEPTH TYPE INTEGER
+set_parameter_property RXMBOX_DEPTH UNITS None
+set_parameter_property RXMBOX_DEPTH ALLOWED_RANGES -2147483648:2147483647
+set_parameter_property RXMBOX_DEPTH DESCRIPTION ""
+set_parameter_property RXMBOX_DEPTH AFFECTS_GENERATION false
+set_parameter_property RXMBOX_DEPTH HDL_PARAMETER true
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | display items
+# | 
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point clock
+# | 
+add_interface clock clock end
+set_interface_property clock clockRate 0
+
+set_interface_property clock ENABLED true
+
+add_interface_port clock clk_i clk Input 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point clock_reset
+# | 
+add_interface clock_reset reset end
+set_interface_property clock_reset associatedClock clock
+set_interface_property clock_reset synchronousEdges DEASSERT
+
+set_interface_property clock_reset ENABLED true
+
+add_interface_port clock_reset av_rst_i reset Input 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point avalon_slave_0
+# | 
+add_interface avalon_slave_0 avalon end
+set_interface_property avalon_slave_0 addressAlignment DYNAMIC
+set_interface_property avalon_slave_0 addressUnits WORDS
+set_interface_property avalon_slave_0 associatedClock clock
+set_interface_property avalon_slave_0 associatedReset clock_reset
+set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
+set_interface_property avalon_slave_0 explicitAddressSpan 0
+set_interface_property avalon_slave_0 holdTime 0
+set_interface_property avalon_slave_0 isMemoryDevice false
+set_interface_property avalon_slave_0 isNonVolatileStorage false
+set_interface_property avalon_slave_0 linewrapBursts false
+set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
+set_interface_property avalon_slave_0 printableDevice false
+set_interface_property avalon_slave_0 readLatency 0
+set_interface_property avalon_slave_0 readWaitTime 1
+set_interface_property avalon_slave_0 setupTime 0
+set_interface_property avalon_slave_0 timingUnits Cycles
+set_interface_property avalon_slave_0 writeWaitTime 0
+
+set_interface_property avalon_slave_0 ENABLED true
+
+add_interface_port avalon_slave_0 av_wr_i write Input 1
+add_interface_port avalon_slave_0 av_dat_i writedata Input 32
+add_interface_port avalon_slave_0 av_dat_o readdata Output 32
+add_interface_port avalon_slave_0 av_cs_i chipselect Input 1
+add_interface_port avalon_slave_0 av_adr_i address Input 8
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point conduit_end
+# | 
+add_interface conduit_end conduit end
+
+set_interface_property conduit_end ENABLED true
+
+add_interface_port conduit_end rx_i export Input 1
+add_interface_port conduit_end tx_o export Output 1
+add_interface_port conduit_end bus_off_on export Output 1
+add_interface_port conduit_end clkout_o export Output 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point interrupt_sender
+# | 
+add_interface interrupt_sender interrupt end
+set_interface_property interrupt_sender associatedAddressablePoint avalon_slave_0
+set_interface_property interrupt_sender associatedClock clock
+set_interface_property interrupt_sender associatedReset clock_reset
+
+set_interface_property interrupt_sender ENABLED true
+
+add_interface_port interrupt_sender irq_on irq_n Output 1
+# | 
+# +-----------------------------------
Index: /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_acf.v
===================================================================
--- /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_acf.v	(revision 295)
+++ /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_acf.v	(revision 295)
@@ -0,0 +1,382 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  can_acf.v                                                   ////
+////                                                              ////
+////                                                              ////
+////  This file is part of the CAN Protocol Controller            ////
+////  http://www.opencores.org/projects/can/                      ////
+////                                                              ////
+////                                                              ////
+////  Author(s):                                                  ////
+////       Igor Mohor                                             ////
+////       igorm@opencores.org                                    ////
+////                                                              ////
+////                                                              ////
+////  All additional information is available in the README.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002, 2003, 2004 Authors                       ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//// The CAN protocol is developed by Robert Bosch GmbH and       ////
+//// protected by patents. Anybody who wants to implement this    ////
+//// CAN IP core on silicon has to obtain a CAN protocol license  ////
+//// from Bosch.                                                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: can_acf.v,v $
+// Revision 1.9  2004/05/31 14:46:11  igorm
+// Bit acceptance_filter_mode was inverted.
+//
+// Revision 1.8  2004/02/08 14:16:44  mohor
+// Header changed.
+//
+// Revision 1.7  2003/07/16 13:41:34  mohor
+// Fixed according to the linter.
+//
+// Revision 1.6  2003/02/10 16:02:11  mohor
+// CAN is working according to the specification. WB interface and more
+// registers (status, IRQ, ...) needs to be added.
+//
+// Revision 1.5  2003/02/09 18:40:29  mohor
+// Overload fixed. Hard synchronization also enabled at the last bit of
+// interframe.
+//
+// Revision 1.4  2003/02/09 02:24:33  mohor
+// Bosch license warning added. Error counters finished. Overload frames
+// still need to be fixed.
+//
+// Revision 1.3  2003/01/31 01:13:37  mohor
+// backup.
+//
+// Revision 1.2  2003/01/14 12:19:35  mohor
+// rx_fifo is now working.
+//
+// Revision 1.1  2003/01/08 02:13:15  mohor
+// Acceptance filter added.
+//
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "can_defines.v"
+
+module can_acf
+( 
+  clk,
+  rst,
+
+  id,
+  
+  /* Mode register */
+  reset_mode,
+  acceptance_filter_mode,
+
+  extended_mode,
+  
+  acceptance_code_0,
+  acceptance_code_1,
+  acceptance_code_2,
+  acceptance_code_3,
+  acceptance_mask_0,
+  acceptance_mask_1,
+  acceptance_mask_2,
+  acceptance_mask_3,
+  
+  go_rx_crc_lim,
+  go_rx_inter,
+  go_error_frame,
+  
+  data0,
+  data1,
+  rtr1,
+  rtr2,
+  ide,
+  no_byte0,
+  no_byte1,
+
+  
+  id_ok
+  
+  
+);
+
+parameter Tp = 1;
+
+input         clk;
+input         rst;
+input  [28:0] id;
+input         reset_mode;
+input         acceptance_filter_mode;
+input         extended_mode;
+
+input   [7:0] acceptance_code_0;
+input   [7:0] acceptance_code_1;
+input   [7:0] acceptance_code_2;
+input   [7:0] acceptance_code_3;
+input   [7:0] acceptance_mask_0;
+input   [7:0] acceptance_mask_1;
+input   [7:0] acceptance_mask_2;
+input   [7:0] acceptance_mask_3;
+input         go_rx_crc_lim;
+input         go_rx_inter;
+input         go_error_frame;
+input   [7:0] data0;
+input   [7:0] data1;
+input         rtr1;
+input         rtr2;
+input         ide;
+input         no_byte0;
+input         no_byte1;
+
+
+output        id_ok;
+
+reg           id_ok;
+
+wire          match;
+wire          match_sf_std;
+wire          match_sf_ext;
+wire          match_df_std;
+wire          match_df_ext;
+
+
+// Working in basic mode. ID match for standard format (11-bit ID).
+assign match =        ( (id[3]  == acceptance_code_0[0] | acceptance_mask_0[0] ) &
+                        (id[4]  == acceptance_code_0[1] | acceptance_mask_0[1] ) &
+                        (id[5]  == acceptance_code_0[2] | acceptance_mask_0[2] ) &
+                        (id[6]  == acceptance_code_0[3] | acceptance_mask_0[3] ) &
+                        (id[7]  == acceptance_code_0[4] | acceptance_mask_0[4] ) &
+                        (id[8]  == acceptance_code_0[5] | acceptance_mask_0[5] ) &
+                        (id[9]  == acceptance_code_0[6] | acceptance_mask_0[6] ) &
+                        (id[10] == acceptance_code_0[7] | acceptance_mask_0[7] )
+                      );
+
+
+// Working in extended mode. ID match for standard format (11-bit ID). Using single filter.
+assign match_sf_std = ( (id[3]  == acceptance_code_0[0] | acceptance_mask_0[0] ) &
+                        (id[4]  == acceptance_code_0[1] | acceptance_mask_0[1] ) &
+                        (id[5]  == acceptance_code_0[2] | acceptance_mask_0[2] ) &
+                        (id[6]  == acceptance_code_0[3] | acceptance_mask_0[3] ) &
+                        (id[7]  == acceptance_code_0[4] | acceptance_mask_0[4] ) &
+                        (id[8]  == acceptance_code_0[5] | acceptance_mask_0[5] ) &
+                        (id[9]  == acceptance_code_0[6] | acceptance_mask_0[6] ) &
+                        (id[10] == acceptance_code_0[7] | acceptance_mask_0[7] ) &
+
+                        (rtr1   == acceptance_code_1[4] | acceptance_mask_1[4] ) &
+                        (id[0]  == acceptance_code_1[5] | acceptance_mask_1[5] ) &
+                        (id[1]  == acceptance_code_1[6] | acceptance_mask_1[6] ) &
+                        (id[2]  == acceptance_code_1[7] | acceptance_mask_1[7] ) &
+
+                        (data0[0]  == acceptance_code_2[0] | acceptance_mask_2[0] | no_byte0) &
+                        (data0[1]  == acceptance_code_2[1] | acceptance_mask_2[1] | no_byte0) &
+                        (data0[2]  == acceptance_code_2[2] | acceptance_mask_2[2] | no_byte0) &
+                        (data0[3]  == acceptance_code_2[3] | acceptance_mask_2[3] | no_byte0) &
+                        (data0[4]  == acceptance_code_2[4] | acceptance_mask_2[4] | no_byte0) &
+                        (data0[5]  == acceptance_code_2[5] | acceptance_mask_2[5] | no_byte0) &
+                        (data0[6]  == acceptance_code_2[6] | acceptance_mask_2[6] | no_byte0) &
+                        (data0[7]  == acceptance_code_2[7] | acceptance_mask_2[7] | no_byte0) &
+
+                        (data1[0]  == acceptance_code_3[0] | acceptance_mask_3[0] | no_byte1) &
+                        (data1[1]  == acceptance_code_3[1] | acceptance_mask_3[1] | no_byte1) &
+                        (data1[2]  == acceptance_code_3[2] | acceptance_mask_3[2] | no_byte1) &
+                        (data1[3]  == acceptance_code_3[3] | acceptance_mask_3[3] | no_byte1) &
+                        (data1[4]  == acceptance_code_3[4] | acceptance_mask_3[4] | no_byte1) &
+                        (data1[5]  == acceptance_code_3[5] | acceptance_mask_3[5] | no_byte1) &
+                        (data1[6]  == acceptance_code_3[6] | acceptance_mask_3[6] | no_byte1) &
+                        (data1[7]  == acceptance_code_3[7] | acceptance_mask_3[7] | no_byte1)
+                      );
+
+
+
+// Working in extended mode. ID match for extended format (29-bit ID). Using single filter.
+assign match_sf_ext = ( (id[21]  == acceptance_code_0[0] | acceptance_mask_0[0] ) &
+                        (id[22]  == acceptance_code_0[1] | acceptance_mask_0[1] ) &
+                        (id[23]  == acceptance_code_0[2] | acceptance_mask_0[2] ) &
+                        (id[24]  == acceptance_code_0[3] | acceptance_mask_0[3] ) &
+                        (id[25]  == acceptance_code_0[4] | acceptance_mask_0[4] ) &
+                        (id[26]  == acceptance_code_0[5] | acceptance_mask_0[5] ) &
+                        (id[27]  == acceptance_code_0[6] | acceptance_mask_0[6] ) &
+                        (id[28]  == acceptance_code_0[7] | acceptance_mask_0[7] ) &
+
+                        (id[13]  == acceptance_code_1[0] | acceptance_mask_1[0] ) &
+                        (id[14]  == acceptance_code_1[1] | acceptance_mask_1[1] ) &
+                        (id[15]  == acceptance_code_1[2] | acceptance_mask_1[2] ) &
+                        (id[16]  == acceptance_code_1[3] | acceptance_mask_1[3] ) &
+                        (id[17]  == acceptance_code_1[4] | acceptance_mask_1[4] ) &
+                        (id[18]  == acceptance_code_1[5] | acceptance_mask_1[5] ) &
+                        (id[19]  == acceptance_code_1[6] | acceptance_mask_1[6] ) &
+                        (id[20]  == acceptance_code_1[7] | acceptance_mask_1[7] ) &
+
+                        (id[5]  == acceptance_code_2[0] | acceptance_mask_2[0] ) &
+                        (id[6]  == acceptance_code_2[1] | acceptance_mask_2[1] ) &
+                        (id[7]  == acceptance_code_2[2] | acceptance_mask_2[2] ) &
+                        (id[8]  == acceptance_code_2[3] | acceptance_mask_2[3] ) &
+                        (id[9]  == acceptance_code_2[4] | acceptance_mask_2[4] ) &
+                        (id[10] == acceptance_code_2[5] | acceptance_mask_2[5] ) &
+                        (id[11] == acceptance_code_2[6] | acceptance_mask_2[6] ) &
+                        (id[12] == acceptance_code_2[7] | acceptance_mask_2[7] ) &
+
+                        (rtr2   == acceptance_code_3[2] | acceptance_mask_3[2] ) &
+                        (id[0]  == acceptance_code_3[3] | acceptance_mask_3[3] ) &
+                        (id[1]  == acceptance_code_3[4] | acceptance_mask_3[4] ) &
+                        (id[2]  == acceptance_code_3[5] | acceptance_mask_3[5] ) &
+                        (id[3]  == acceptance_code_3[6] | acceptance_mask_3[6] ) &
+                        (id[4]  == acceptance_code_3[7] | acceptance_mask_3[7] )
+
+                      );
+
+
+// Working in extended mode. ID match for standard format (11-bit ID). Using double filter.
+assign match_df_std = (((id[3]  == acceptance_code_0[0] | acceptance_mask_0[0] ) &
+                        (id[4]  == acceptance_code_0[1] | acceptance_mask_0[1] ) &
+                        (id[5]  == acceptance_code_0[2] | acceptance_mask_0[2] ) &
+                        (id[6]  == acceptance_code_0[3] | acceptance_mask_0[3] ) &
+                        (id[7]  == acceptance_code_0[4] | acceptance_mask_0[4] ) &
+                        (id[8]  == acceptance_code_0[5] | acceptance_mask_0[5] ) &
+                        (id[9]  == acceptance_code_0[6] | acceptance_mask_0[6] ) &
+                        (id[10] == acceptance_code_0[7] | acceptance_mask_0[7] ) &
+
+                        (rtr1   == acceptance_code_1[4] | acceptance_mask_1[4] ) &
+                        (id[0]  == acceptance_code_1[5] | acceptance_mask_1[5] ) &
+                        (id[1]  == acceptance_code_1[6] | acceptance_mask_1[6] ) &
+                        (id[2]  == acceptance_code_1[7] | acceptance_mask_1[7] ) &
+
+                        (data0[0] == acceptance_code_3[0] | acceptance_mask_3[0] | no_byte0) &
+                        (data0[1] == acceptance_code_3[1] | acceptance_mask_3[1] | no_byte0) &
+                        (data0[2] == acceptance_code_3[2] | acceptance_mask_3[2] | no_byte0) &
+                        (data0[3] == acceptance_code_3[3] | acceptance_mask_3[3] | no_byte0) &
+                        (data0[4] == acceptance_code_1[4] | acceptance_mask_1[4] | no_byte0) &
+                        (data0[5] == acceptance_code_1[5] | acceptance_mask_1[5] | no_byte0) &
+                        (data0[6] == acceptance_code_1[6] | acceptance_mask_1[6] | no_byte0) &
+                        (data0[7] == acceptance_code_1[7] | acceptance_mask_1[7] | no_byte0) )
+                        
+                       |
+
+                       ((id[3]  == acceptance_code_2[0] | acceptance_mask_2[0] ) &
+                        (id[4]  == acceptance_code_2[1] | acceptance_mask_2[1] ) &
+                        (id[5]  == acceptance_code_2[2] | acceptance_mask_2[2] ) &
+                        (id[6]  == acceptance_code_2[3] | acceptance_mask_2[3] ) &
+                        (id[7]  == acceptance_code_2[4] | acceptance_mask_2[4] ) &
+                        (id[8]  == acceptance_code_2[5] | acceptance_mask_2[5] ) &
+                        (id[9]  == acceptance_code_2[6] | acceptance_mask_2[6] ) &
+                        (id[10] == acceptance_code_2[7] | acceptance_mask_2[7] ) &
+
+                        (rtr1   == acceptance_code_3[4] | acceptance_mask_3[4] ) &
+                        (id[0]  == acceptance_code_3[5] | acceptance_mask_3[5] ) &
+                        (id[1]  == acceptance_code_3[6] | acceptance_mask_3[6] ) &
+                        (id[2]  == acceptance_code_3[7] | acceptance_mask_3[7] ) )
+
+                      );
+
+
+// Working in extended mode. ID match for extended format (29-bit ID). Using double filter.
+assign match_df_ext = (((id[21]  == acceptance_code_0[0] | acceptance_mask_0[0] ) &
+                        (id[22]  == acceptance_code_0[1] | acceptance_mask_0[1] ) &
+                        (id[23]  == acceptance_code_0[2] | acceptance_mask_0[2] ) &
+                        (id[24]  == acceptance_code_0[3] | acceptance_mask_0[3] ) &
+                        (id[25]  == acceptance_code_0[4] | acceptance_mask_0[4] ) &
+                        (id[26]  == acceptance_code_0[5] | acceptance_mask_0[5] ) &
+                        (id[27]  == acceptance_code_0[6] | acceptance_mask_0[6] ) &
+                        (id[28]  == acceptance_code_0[7] | acceptance_mask_0[7] ) &
+
+                        (id[13]  == acceptance_code_1[0] | acceptance_mask_1[0] ) &
+                        (id[14]  == acceptance_code_1[1] | acceptance_mask_1[1] ) &
+                        (id[15]  == acceptance_code_1[2] | acceptance_mask_1[2] ) &
+                        (id[16]  == acceptance_code_1[3] | acceptance_mask_1[3] ) &
+                        (id[17]  == acceptance_code_1[4] | acceptance_mask_1[4] ) &
+                        (id[18]  == acceptance_code_1[5] | acceptance_mask_1[5] ) &
+                        (id[19]  == acceptance_code_1[6] | acceptance_mask_1[6] ) &
+                        (id[20]  == acceptance_code_1[7] | acceptance_mask_1[7] ) )
+                        
+                       |
+                        
+                       ((id[21]  == acceptance_code_2[0] | acceptance_mask_2[0] ) &
+                        (id[22]  == acceptance_code_2[1] | acceptance_mask_2[1] ) &
+                        (id[23]  == acceptance_code_2[2] | acceptance_mask_2[2] ) &
+                        (id[24]  == acceptance_code_2[3] | acceptance_mask_2[3] ) &
+                        (id[25]  == acceptance_code_2[4] | acceptance_mask_2[4] ) &
+                        (id[26]  == acceptance_code_2[5] | acceptance_mask_2[5] ) &
+                        (id[27]  == acceptance_code_2[6] | acceptance_mask_2[6] ) &
+                        (id[28]  == acceptance_code_2[7] | acceptance_mask_2[7] ) &
+
+                        (id[13]  == acceptance_code_3[0] | acceptance_mask_3[0] ) &
+                        (id[14]  == acceptance_code_3[1] | acceptance_mask_3[1] ) &
+                        (id[15]  == acceptance_code_3[2] | acceptance_mask_3[2] ) &
+                        (id[16]  == acceptance_code_3[3] | acceptance_mask_3[3] ) &
+                        (id[17]  == acceptance_code_3[4] | acceptance_mask_3[4] ) &
+                        (id[18]  == acceptance_code_3[5] | acceptance_mask_3[5] ) &
+                        (id[19]  == acceptance_code_3[6] | acceptance_mask_3[6] ) &
+                        (id[20]  == acceptance_code_3[7] | acceptance_mask_3[7] ) )
+                      );
+
+
+
+// ID ok signal generation
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    id_ok <= 1'b0;
+  else if (go_rx_crc_lim)                   // sample_point is already included in go_rx_crc_lim
+    begin
+      if (extended_mode)
+        begin
+          if (~acceptance_filter_mode)      // dual filter
+            begin
+              if (ide)                      // extended frame message
+                id_ok <=#Tp match_df_ext;
+              else                          // standard frame message
+                id_ok <=#Tp match_df_std;
+            end           
+          else                              // single filter
+            begin
+              if (ide)                      // extended frame message
+                id_ok <=#Tp match_sf_ext;
+              else                          // standard frame message
+                id_ok <=#Tp match_sf_std;
+            end
+        end
+      else      
+        id_ok <=#Tp match;
+    end
+  else if (reset_mode | go_rx_inter | go_error_frame)        // sample_point is already included in go_rx_inter
+    id_ok <=#Tp 1'b0;
+end
+
+
+
+
+
+
+
+
+
+endmodule
Index: /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_bsp.v
===================================================================
--- /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_bsp.v	(revision 295)
+++ /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_bsp.v	(revision 295)
@@ -0,0 +1,2196 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  can_bsp.v                                                   ////
+////                                                              ////
+////                                                              ////
+////  This file is part of the CAN Protocol Controller            ////
+////  http://www.opencores.org/projects/can/                      ////
+////                                                              ////
+////                                                              ////
+////  Author(s):                                                  ////
+////       Igor Mohor                                             ////
+////       igorm@opencores.org                                    ////
+////                                                              ////
+////                                                              ////
+////  All additional information is available in the README.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002, 2003, 2004 Authors                       ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//// The CAN protocol is developed by Robert Bosch GmbH and       ////
+//// protected by patents. Anybody who wants to implement this    ////
+//// CAN IP core on silicon has to obtain a CAN protocol license  ////
+//// from Bosch.                                                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: can_bsp.v,v $
+// Revision 1.53  2004/11/22 19:18:03  igorm
+// Arbitration capture register changed. SW reset (setting the reset_mode bit)
+// doesn't work as HW reset.
+//
+// Revision 1.52  2004/11/18 12:39:21  igorm
+// Fixes for compatibility after the SW reset.
+//
+// Revision 1.51  2004/11/15 18:23:21  igorm
+// When CAN was reset by setting the reset_mode signal in mode register, it
+// was possible that CAN was blocked for a short period of time. Problem
+// occured very rarly.
+//
+// Revision 1.50  2004/10/27 18:51:36  igorm
+// Fixed synchronization problem in real hardware when 0xf is used for TSEG1.
+//
+// Revision 1.49  2004/10/25 06:37:51  igorm
+// Arbitration bug fixed.
+//
+// Revision 1.48  2004/05/12 15:58:41  igorm
+// Core improved to pass all tests with the Bosch VHDL Reference system.
+//
+// Revision 1.47  2004/02/08 14:24:10  mohor
+// Error counters changed.
+//
+// Revision 1.46  2003/10/17 05:55:20  markom
+// mbist signals updated according to newest convention
+//
+// Revision 1.45  2003/09/30 21:14:33  mohor
+// Error counters changed.
+//
+// Revision 1.44  2003/09/30 00:55:12  mohor
+// Error counters fixed to be compatible with Bosch VHDL reference model.
+// Small synchronization changes.
+//
+// Revision 1.43  2003/09/25 18:55:49  mohor
+// Synchronization changed, error counters fixed.
+//
+// Revision 1.42  2003/08/29 07:01:14  mohor
+// When detecting bus-free, signal bus_free_cnt_en was cleared to zero
+// although the last sampled bit was zero instead of one.
+//
+// Revision 1.41  2003/07/18 15:23:31  tadejm
+// Tx and rx length are limited to 8 bytes regardless to the DLC value.
+//
+// Revision 1.40  2003/07/16 15:10:17  mohor
+// Fixed according to the linter.
+//
+// Revision 1.39  2003/07/16 13:12:46  mohor
+// Fixed according to the linter.
+//
+// Revision 1.38  2003/07/10 01:59:04  tadejm
+// Synchronization fixed. In some strange cases it didn't work according to
+// the VHDL reference model.
+//
+// Revision 1.37  2003/07/07 11:21:37  mohor
+// Little fixes (to fix warnings).
+//
+// Revision 1.36  2003/07/03 09:32:20  mohor
+// Synchronization changed.
+//
+// Revision 1.35  2003/06/27 20:56:12  simons
+// Virtual silicon ram instances added.
+//
+// Revision 1.34  2003/06/22 09:43:03  mohor
+// synthesi full_case parallel_case fixed.
+//
+// Revision 1.33  2003/06/21 12:16:30  mohor
+// paralel_case and full_case compiler directives added to case statements.
+//
+// Revision 1.32  2003/06/17 14:28:32  mohor
+// Form error was detected when stuff bit occured at the end of crc.
+//
+// Revision 1.31  2003/06/16 14:31:29  tadejm
+// Bit stuffing corrected when stuffing comes at the end of the crc.
+//
+// Revision 1.30  2003/06/16 13:57:58  mohor
+// tx_point generated one clk earlier. rx_i registered. Data corrected when
+// using extended mode.
+//
+// Revision 1.29  2003/06/11 14:21:35  mohor
+// When switching to tx, sync stage is overjumped.
+//
+// Revision 1.28  2003/03/01 22:53:33  mohor
+// Actel APA ram supported.
+//
+// Revision 1.27  2003/02/20 00:26:02  mohor
+// When a dominant bit was detected at the third bit of the intermission and
+// node had a message to transmit, bit_stuff error could occur. Fixed.
+//
+// Revision 1.26  2003/02/19 23:21:54  mohor
+// When bit error occured while active error flag was transmitted, counter was
+// not incremented.
+//
+// Revision 1.25  2003/02/19 14:44:03  mohor
+// CAN core finished. Host interface added. Registers finished.
+// Synchronization to the wishbone finished.
+//
+// Revision 1.24  2003/02/18 00:10:15  mohor
+// Most of the registers added. Registers "arbitration lost capture", "error code
+// capture" + few more still need to be added.
+//
+// Revision 1.23  2003/02/14 20:17:01  mohor
+// Several registers added. Not finished, yet.
+//
+// Revision 1.22  2003/02/12 14:23:59  mohor
+// abort_tx added. Bit destuff fixed.
+//
+// Revision 1.21  2003/02/11 00:56:06  mohor
+// Wishbone interface added.
+//
+// Revision 1.20  2003/02/10 16:02:11  mohor
+// CAN is working according to the specification. WB interface and more
+// registers (status, IRQ, ...) needs to be added.
+//
+// Revision 1.19  2003/02/09 18:40:29  mohor
+// Overload fixed. Hard synchronization also enabled at the last bit of
+// interframe.
+//
+// Revision 1.18  2003/02/09 02:24:33  mohor
+// Bosch license warning added. Error counters finished. Overload frames
+// still need to be fixed.
+//
+// Revision 1.17  2003/02/04 17:24:41  mohor
+// Backup.
+//
+// Revision 1.16  2003/02/04 14:34:52  mohor
+// *** empty log message ***
+//
+// Revision 1.15  2003/01/31 01:13:37  mohor
+// backup.
+//
+// Revision 1.14  2003/01/16 13:36:19  mohor
+// Form error supported. When receiving messages, last bit of the end-of-frame
+// does not generate form error. Receiver goes to the idle mode one bit sooner.
+// (CAN specification ver 2.0, part B, page 57).
+//
+// Revision 1.13  2003/01/15 21:59:45  mohor
+// Data is stored to fifo at the end of ack stage.
+//
+// Revision 1.12  2003/01/15 21:05:11  mohor
+// CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).
+//
+// Revision 1.11  2003/01/15 14:40:23  mohor
+// RX state machine fixed to receive "remote request" frames correctly.
+// No data bytes are written to fifo when such frames are received.
+//
+// Revision 1.10  2003/01/15 13:16:47  mohor
+// When a frame with "remote request" is received, no data is stored to
+// fifo, just the frame information (identifier, ...). Data length that
+// is stored is the received data length and not the actual data length
+// that is stored to fifo.
+//
+// Revision 1.9  2003/01/14 12:19:35  mohor
+// rx_fifo is now working.
+//
+// Revision 1.8  2003/01/10 17:51:33  mohor
+// Temporary version (backup).
+//
+// Revision 1.7  2003/01/09 21:54:45  mohor
+// rx fifo added. Not 100 % verified, yet.
+//
+// Revision 1.6  2003/01/09 14:46:58  mohor
+// Temporary files (backup).
+//
+// Revision 1.5  2003/01/08 13:30:31  mohor
+// Temp version.
+//
+// Revision 1.4  2003/01/08 02:10:53  mohor
+// Acceptance filter added.
+//
+// Revision 1.3  2002/12/28 04:13:23  mohor
+// Backup version.
+//
+// Revision 1.2  2002/12/27 00:12:52  mohor
+// Header changed, testbench improved to send a frame (crc still missing).
+//
+// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
+// Initial
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "can_defines.v"
+
+module can_bsp
+( 
+  clk,
+  rst,
+
+  sample_point,
+  sampled_bit,
+  sampled_bit_q,
+  tx_point,
+  hard_sync,
+
+  addr,
+  data_in,
+  data_out,
+  fifo_selected,
+  
+
+
+  /* Mode register */
+  reset_mode,
+  listen_only_mode,
+  acceptance_filter_mode,
+  self_test_mode,
+
+  /* Command register */
+  release_buffer,
+  tx_request,
+  abort_tx,
+  self_rx_request,
+  single_shot_transmission,
+  tx_state,
+  tx_state_q,
+  overload_request,
+  overload_frame,
+
+  /* Arbitration Lost Capture Register */
+  read_arbitration_lost_capture_reg,
+
+  /* Error Code Capture Register */
+  read_error_code_capture_reg,
+  error_capture_code,
+
+  /* Error Warning Limit register */
+  error_warning_limit,
+
+  /* Rx Error Counter register */
+  we_rx_err_cnt,
+
+  /* Tx Error Counter register */
+  we_tx_err_cnt,
+
+  /* Clock Divider register */
+  extended_mode,
+
+  rx_idle,
+  transmitting,
+  transmitter,
+  go_rx_inter,
+  not_first_bit_of_inter,
+  rx_inter,
+  set_reset_mode,
+  node_bus_off,
+  error_status,
+  rx_err_cnt,
+  tx_err_cnt,
+  transmit_status,
+  receive_status,
+  tx_successful,
+  need_to_tx,
+  overrun,
+  info_empty,
+  set_bus_error_irq,
+  set_arbitration_lost_irq,
+  arbitration_lost_capture,
+  node_error_passive,
+  node_error_active,
+  rx_message_counter,
+
+  /* This section is for BASIC and EXTENDED mode */
+  /* Acceptance code register */
+  acceptance_code_0,
+
+  /* Acceptance mask register */
+  acceptance_mask_0,
+  /* End: This section is for BASIC and EXTENDED mode */
+  
+  /* This section is for EXTENDED mode */
+  /* Acceptance code register */
+  acceptance_code_1,
+  acceptance_code_2,
+  acceptance_code_3,
+
+  /* Acceptance mask register */
+  acceptance_mask_1,
+  acceptance_mask_2,
+  acceptance_mask_3,
+  /* End: This section is for EXTENDED mode */
+  
+  /* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
+  tx_data_0,
+  tx_data_1,
+  tx_data_2,
+  tx_data_3,
+  tx_data_4,
+  tx_data_5,
+  tx_data_6,
+  tx_data_7,
+  tx_data_8,
+  tx_data_9,
+  tx_data_10,
+  tx_data_11,
+  tx_data_12,
+  /* End: Tx data registers */
+  rx_dt,
+  rx_we,
+  
+  /* Tx signal */
+  tx,
+  tx_next,
+  bus_off_on,
+
+  go_overload_frame,
+  go_error_frame,
+  go_tx,
+  send_ack
+
+  /* Bist */
+`ifdef CAN_BIST
+  ,
+  mbist_si_i,
+  mbist_so_o,
+  mbist_ctrl_i
+`endif
+);
+
+parameter Tp = 1;
+
+input         clk;
+input         rst;
+input         sample_point;
+input         sampled_bit;
+input         sampled_bit_q;
+input         tx_point;
+input         hard_sync;
+input   [7:0] addr;
+input  [31:0] data_in;
+output  [7:0] data_out;
+input         fifo_selected;
+
+input         reset_mode;
+input         listen_only_mode;
+input         acceptance_filter_mode;
+input         extended_mode;
+input         self_test_mode;
+
+/* Command register */
+input         release_buffer;
+input         tx_request;
+input         abort_tx;
+input         self_rx_request;
+input         single_shot_transmission;
+output        tx_state;
+output        tx_state_q;
+input         overload_request;     // When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to
+output        overload_frame;       // be send in a row. This is not implemented, yet,  because host can not send an overload request.
+
+/* Arbitration Lost Capture Register */
+input         read_arbitration_lost_capture_reg;
+
+/* Error Code Capture Register */
+input         read_error_code_capture_reg;
+output  [7:0] error_capture_code;
+
+/* Error Warning Limit register */
+input   [7:0] error_warning_limit;
+
+/* Rx Error Counter register */
+input         we_rx_err_cnt;
+
+/* Tx Error Counter register */
+input         we_tx_err_cnt;
+
+output        rx_idle;
+output        transmitting;
+output        transmitter;
+output        go_rx_inter;
+output        not_first_bit_of_inter;
+output        rx_inter;
+output        set_reset_mode;
+output        node_bus_off;
+output        error_status;
+output  [8:0] rx_err_cnt;
+output  [8:0] tx_err_cnt;
+output        transmit_status;
+output        receive_status;
+output        tx_successful;
+output        need_to_tx;
+output        overrun;
+output        info_empty;
+output        set_bus_error_irq;
+output        set_arbitration_lost_irq;
+output  [4:0] arbitration_lost_capture;
+output        node_error_passive;
+output        node_error_active;
+output  [6:0] rx_message_counter;
+
+
+/* This section is for BASIC and EXTENDED mode */
+/* Acceptance code register */
+input   [7:0] acceptance_code_0;
+
+/* Acceptance mask register */
+input   [7:0] acceptance_mask_0;
+
+/* End: This section is for BASIC and EXTENDED mode */
+
+
+/* This section is for EXTENDED mode */
+/* Acceptance code register */
+input   [7:0] acceptance_code_1;
+input   [7:0] acceptance_code_2;
+input   [7:0] acceptance_code_3;
+
+/* Acceptance mask register */
+input   [7:0] acceptance_mask_1;
+input   [7:0] acceptance_mask_2;
+input   [7:0] acceptance_mask_3;
+/* End: This section is for EXTENDED mode */
+
+/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
+input   [7:0] tx_data_0;
+input   [7:0] tx_data_1;
+input   [7:0] tx_data_2;
+input   [7:0] tx_data_3;
+input   [7:0] tx_data_4;
+input   [7:0] tx_data_5;
+input   [7:0] tx_data_6;
+input   [7:0] tx_data_7;
+input   [7:0] tx_data_8;
+input   [7:0] tx_data_9;
+input   [7:0] tx_data_10;
+input   [7:0] tx_data_11;
+input   [7:0] tx_data_12;
+/* End: Tx data registers */
+output [127:0] rx_dt;
+output         rx_we;
+
+/* Tx signal */
+output        tx;
+output        tx_next;
+output        bus_off_on;
+
+output        go_overload_frame;
+output        go_error_frame;
+output        go_tx;
+output        send_ack;
+
+/* Bist */
+`ifdef CAN_BIST
+input         mbist_si_i;
+output        mbist_so_o;
+input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
+`endif
+
+reg           reset_mode_q;
+reg     [5:0] bit_cnt;
+
+reg     [3:0] data_len;
+reg    [28:0] id;
+reg     [2:0] bit_stuff_cnt;
+reg     [2:0] bit_stuff_cnt_tx;
+reg           tx_point_q;
+
+reg           rx_idle;
+reg           rx_id1;
+reg           rx_rtr1;
+reg           rx_ide;
+reg           rx_id2;
+reg           rx_rtr2;
+reg           rx_r1;
+reg           rx_r0;
+reg           rx_dlc;
+reg           rx_data;
+reg           rx_crc;
+reg           rx_crc_lim;
+reg           rx_ack;
+reg           rx_ack_lim;
+reg           rx_eof;
+reg           rx_inter;
+reg           go_early_tx_latched;
+
+reg           rtr1;
+reg           ide;
+reg           rtr2;
+reg    [14:0] crc_in;
+
+reg     [7:0] tmp_data;
+reg     [7:0] tmp_fifo [0:7];
+reg           write_data_to_tmp_fifo;
+reg     [2:0] byte_cnt;
+reg           bit_stuff_cnt_en;
+reg           crc_enable;
+
+reg     [2:0] eof_cnt;
+reg     [2:0] passive_cnt;
+
+reg           transmitting;
+
+reg           error_frame;
+reg           enable_error_cnt2;
+reg     [2:0] error_cnt1;
+reg     [2:0] error_cnt2;
+reg     [2:0] delayed_dominant_cnt;
+reg           enable_overload_cnt2;
+reg           overload_frame;
+reg           overload_frame_blocked;
+reg     [1:0] overload_request_cnt;
+reg     [2:0] overload_cnt1;
+reg     [2:0] overload_cnt2;
+reg           tx;
+reg           crc_err;
+
+reg           arbitration_lost;
+reg           arbitration_lost_q;
+reg           arbitration_field_d;
+reg     [4:0] arbitration_lost_capture;
+reg     [4:0] arbitration_cnt;
+reg           arbitration_blocked;
+reg           tx_q;
+
+reg           need_to_tx;   // When the CAN core has something to transmit and a dominant bit is sampled at the third bit
+reg     [3:0] data_cnt;     // Counting the data bytes that are written to FIFO
+reg     [2:0] header_cnt;   // Counting header length
+reg           wr_fifo;      // Write data and header to 64-byte fifo
+reg           wr_fifo_q;    // Write data and header to 64-byte fifo
+reg     [7:0] data_for_fifo;// Multiplexed data that is stored to 64-byte fifo
+
+reg     [5:0] tx_pointer;
+reg           tx_bit;
+reg           tx_state;
+reg           tx_state_q;
+reg           transmitter;
+reg           finish_msg;
+
+reg     [8:0] rx_err_cnt;
+reg     [8:0] tx_err_cnt;
+reg     [3:0] bus_free_cnt;
+reg           bus_free_cnt_en;
+reg           bus_free;
+reg           waiting_for_bus_free;
+
+reg           node_error_passive;
+reg           node_bus_off;
+reg           node_bus_off_q;
+reg           ack_err_latched;
+reg           bit_err_latched;
+reg           stuff_err_latched;
+reg           form_err_latched;
+reg           rule3_exc1_1;
+reg           rule3_exc1_2;
+reg           suspend;
+reg           susp_cnt_en;
+reg     [2:0] susp_cnt;
+reg           error_flag_over_latched;
+
+reg     [7:0] error_capture_code;
+reg     [7:6] error_capture_code_type;
+reg           error_capture_code_blocked;
+reg           tx_next;
+reg           first_compare_bit;
+
+reg   [127:0] rx_dt;
+
+
+wire    [4:0] error_capture_code_segment;
+wire          error_capture_code_direction;
+
+wire          bit_de_stuff;
+wire          bit_de_stuff_tx;
+
+wire          rule5;
+
+/* Rx state machine */
+wire          go_rx_idle;
+wire          go_rx_id1;
+wire          go_rx_rtr1;
+wire          go_rx_ide;
+wire          go_rx_id2;
+wire          go_rx_rtr2;
+wire          go_rx_r1;
+wire          go_rx_r0;
+wire          go_rx_dlc;
+wire          go_rx_data;
+wire          go_rx_crc;
+wire          go_rx_crc_lim;
+wire          go_rx_ack;
+wire          go_rx_ack_lim;
+wire          go_rx_eof;
+wire          go_rx_inter;
+
+wire          last_bit_of_inter;
+
+wire          go_crc_enable;
+wire          rst_crc_enable;
+
+wire          bit_de_stuff_set;
+wire          bit_de_stuff_reset;
+
+wire          go_early_tx;
+
+wire   [14:0] calculated_crc;
+wire   [15:0] r_calculated_crc;
+wire          remote_rq;
+wire    [3:0] limited_data_len;
+wire          form_err;
+
+wire          error_frame_ended;
+wire          overload_frame_ended;
+wire          bit_err;
+wire          ack_err;
+wire          stuff_err;
+
+wire          id_ok;                // If received ID matches ID set in registers
+wire          no_byte0;             // There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.
+wire          no_byte1;             // There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.
+
+wire    [2:0] header_len;
+wire          storing_header;
+wire    [3:0] limited_data_len_minus1;
+wire          reset_wr_fifo;
+wire          err;
+
+wire          arbitration_field;
+
+wire   [18:0] basic_chain;
+wire   [63:0] basic_chain_data;
+wire   [18:0] extended_chain_std;
+wire   [38:0] extended_chain_ext;
+wire   [63:0] extended_chain_data_std;
+wire   [63:0] extended_chain_data_ext;
+
+wire          rst_tx_pointer;
+
+wire    [7:0] r_tx_data_0;
+wire    [7:0] r_tx_data_1;
+wire    [7:0] r_tx_data_2;
+wire    [7:0] r_tx_data_3;
+wire    [7:0] r_tx_data_4;
+wire    [7:0] r_tx_data_5;
+wire    [7:0] r_tx_data_6;
+wire    [7:0] r_tx_data_7;
+wire    [7:0] r_tx_data_8;
+wire    [7:0] r_tx_data_9;
+wire    [7:0] r_tx_data_10;
+wire    [7:0] r_tx_data_11;
+wire    [7:0] r_tx_data_12;
+
+wire          send_ack;
+wire          bit_err_exc1;
+wire          bit_err_exc2;
+wire          bit_err_exc3;
+wire          bit_err_exc4;
+wire          bit_err_exc5;
+wire          bit_err_exc6;
+wire          error_flag_over;
+wire          overload_flag_over;
+
+wire    [5:0] limited_tx_cnt_ext;
+wire    [5:0] limited_tx_cnt_std;
+
+assign go_rx_idle     =                   sample_point &  sampled_bit & last_bit_of_inter | bus_free & (~node_bus_off);
+assign go_rx_id1      =                   sample_point &  (~sampled_bit) & (rx_idle | last_bit_of_inter);
+assign go_rx_rtr1     = (~bit_de_stuff) & sample_point &  rx_id1  & (bit_cnt[3:0] == 4'd10);
+assign go_rx_ide      = (~bit_de_stuff) & sample_point &  rx_rtr1;
+assign go_rx_id2      = (~bit_de_stuff) & sample_point &  rx_ide  &   sampled_bit;
+assign go_rx_rtr2     = (~bit_de_stuff) & sample_point &  rx_id2  & (bit_cnt[4:0] == 5'd17);
+assign go_rx_r1       = (~bit_de_stuff) & sample_point &  rx_rtr2;
+assign go_rx_r0       = (~bit_de_stuff) & sample_point & (rx_ide  & (~sampled_bit) | rx_r1);
+assign go_rx_dlc      = (~bit_de_stuff) & sample_point &  rx_r0;
+assign go_rx_data     = (~bit_de_stuff) & sample_point &  rx_dlc  & (bit_cnt[1:0] == 2'd3) &  (sampled_bit   |   (|data_len[2:0])) & (~remote_rq);
+assign go_rx_crc      = (~bit_de_stuff) & sample_point & (rx_dlc  & (bit_cnt[1:0] == 2'd3) & ((~sampled_bit) & (~(|data_len[2:0])) | remote_rq) |
+                                                          rx_data & (bit_cnt[5:0] == ((limited_data_len<<3) - 1'b1)));  // overflow works ok at max value (8<<3 = 64 = 0). 0-1 = 6'h3f
+assign go_rx_crc_lim  = (~bit_de_stuff) & sample_point &  rx_crc  & (bit_cnt[3:0] == 4'd14);
+assign go_rx_ack      = (~bit_de_stuff) & sample_point &  rx_crc_lim;
+assign go_rx_ack_lim  =                   sample_point &  rx_ack;
+assign go_rx_eof      =                   sample_point &  rx_ack_lim;
+assign go_rx_inter    =                 ((sample_point &  rx_eof  & (eof_cnt == 3'd6)) | error_frame_ended | overload_frame_ended) & (~overload_request);
+
+assign go_error_frame = (form_err | stuff_err | bit_err | ack_err | (crc_err & go_rx_eof));
+assign error_frame_ended = (error_cnt2 == 3'd7) & tx_point;
+assign overload_frame_ended = (overload_cnt2 == 3'd7) & tx_point;
+
+assign go_overload_frame = (     sample_point & ((~sampled_bit) | overload_request) & (rx_eof & (~transmitter) & (eof_cnt == 3'd6) | error_frame_ended | overload_frame_ended) | 
+                                 sample_point & (~sampled_bit) & rx_inter & (bit_cnt[1:0] < 2'd2)                                                            |
+                                 sample_point & (~sampled_bit) & ((error_cnt2 == 3'd7) | (overload_cnt2 == 3'd7))
+                           )
+                           & (~overload_frame_blocked)
+                           ;
+
+
+assign go_crc_enable  = hard_sync | go_tx;
+assign rst_crc_enable = go_rx_crc;
+
+assign bit_de_stuff_set   = go_rx_id1 & (~go_error_frame);
+assign bit_de_stuff_reset = go_rx_ack | go_error_frame | go_overload_frame;
+
+assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);
+assign limited_data_len = (data_len < 4'h8)? data_len : 4'h8;
+
+assign ack_err = rx_ack & sample_point & sampled_bit & tx_state & (~self_test_mode);
+assign bit_err = (tx_state | error_frame | overload_frame | rx_ack) & sample_point & (tx != sampled_bit) & (~bit_err_exc1) & (~bit_err_exc2) & (~bit_err_exc3) & (~bit_err_exc4) & (~bit_err_exc5) & (~bit_err_exc6) & (~reset_mode);
+assign bit_err_exc1 = tx_state & arbitration_field & tx;
+assign bit_err_exc2 = rx_ack & tx;
+assign bit_err_exc3 = error_frame & node_error_passive & (error_cnt1 < 3'd7);
+assign bit_err_exc4 = (error_frame & (error_cnt1 == 3'd7) & (~enable_error_cnt2)) | (overload_frame & (overload_cnt1 == 3'd7) & (~enable_overload_cnt2));
+assign bit_err_exc5 = (error_frame & (error_cnt2 == 3'd7)) | (overload_frame & (overload_cnt2 == 3'd7));
+assign bit_err_exc6 = (eof_cnt == 3'd6) & rx_eof & (~transmitter); 
+
+assign arbitration_field = rx_id1 | rx_rtr1 | rx_ide | rx_id2 | rx_rtr2;
+
+assign last_bit_of_inter = rx_inter & (bit_cnt[1:0] == 2'd2);
+assign not_first_bit_of_inter = rx_inter & (bit_cnt[1:0] != 2'd0);
+
+
+// Rx idle state
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    rx_idle <= 1'b0;
+  else if (go_rx_id1 | go_error_frame)
+    rx_idle <=#Tp 1'b0;
+  else if (go_rx_idle)
+    rx_idle <=#Tp 1'b1;
+end
+
+
+// Rx id1 state
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    rx_id1 <= 1'b0;
+  else if (go_rx_rtr1 | go_error_frame)
+    rx_id1 <=#Tp 1'b0;
+  else if (go_rx_id1)
+    rx_id1 <=#Tp 1'b1;
+end
+
+
+// Rx rtr1 state
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    rx_rtr1 <= 1'b0;
+  else if (go_rx_ide | go_error_frame)
+    rx_rtr1 <=#Tp 1'b0;
+  else if (go_rx_rtr1)
+    rx_rtr1 <=#Tp 1'b1;
+end
+
+
+// Rx ide state
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    rx_ide <= 1'b0;
+  else if (go_rx_r0 | go_rx_id2 | go_error_frame)
+    rx_ide <=#Tp 1'b0;
+  else if (go_rx_ide)
+    rx_ide <=#Tp 1'b1;
+end
+
+
+// Rx id2 state
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    rx_id2 <= 1'b0;
+  else if (go_rx_rtr2 | go_error_frame)
+    rx_id2 <=#Tp 1'b0;
+  else if (go_rx_id2)
+    rx_id2 <=#Tp 1'b1;
+end
+
+
+// Rx rtr2 state
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    rx_rtr2 <= 1'b0;
+  else if (go_rx_r1 | go_error_frame)
+    rx_rtr2 <=#Tp 1'b0;
+  else if (go_rx_rtr2)
+    rx_rtr2 <=#Tp 1'b1;
+end
+
+
+// Rx r0 state
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    rx_r1 <= 1'b0;
+  else if (go_rx_r0 | go_error_frame)
+    rx_r1 <=#Tp 1'b0;
+  else if (go_rx_r1)
+    rx_r1 <=#Tp 1'b1;
+end
+
+
+// Rx r0 state
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    rx_r0 <= 1'b0;
+  else if (go_rx_dlc | go_error_frame)
+    rx_r0 <=#Tp 1'b0;
+  else if (go_rx_r0)
+    rx_r0 <=#Tp 1'b1;
+end
+
+
+// Rx dlc state
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    rx_dlc <= 1'b0;
+  else if (go_rx_data | go_rx_crc | go_error_frame)
+    rx_dlc <=#Tp 1'b0;
+  else if (go_rx_dlc)
+    rx_dlc <=#Tp 1'b1;
+end
+
+
+// Rx data state
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    rx_data <= 1'b0;
+  else if (go_rx_crc | go_error_frame)
+    rx_data <=#Tp 1'b0;
+  else if (go_rx_data)
+    rx_data <=#Tp 1'b1;
+end
+
+
+// Rx crc state
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    rx_crc <= 1'b0;
+  else if (go_rx_crc_lim | go_error_frame)
+    rx_crc <=#Tp 1'b0;
+  else if (go_rx_crc)
+    rx_crc <=#Tp 1'b1;
+end
+
+
+// Rx crc delimiter state
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    rx_crc_lim <= 1'b0;
+  else if (go_rx_ack | go_error_frame)
+    rx_crc_lim <=#Tp 1'b0;
+  else if (go_rx_crc_lim)
+    rx_crc_lim <=#Tp 1'b1;
+end
+
+
+// Rx ack state
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    rx_ack <= 1'b0;
+  else if (go_rx_ack_lim | go_error_frame)
+    rx_ack <=#Tp 1'b0;
+  else if (go_rx_ack)
+    rx_ack <=#Tp 1'b1;
+end
+
+
+// Rx ack delimiter state
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    rx_ack_lim <= 1'b0;
+  else if (go_rx_eof | go_error_frame)
+    rx_ack_lim <=#Tp 1'b0;
+  else if (go_rx_ack_lim)
+    rx_ack_lim <=#Tp 1'b1;
+end
+
+
+// Rx eof state
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    rx_eof <= 1'b0;
+  else if (go_rx_inter | go_error_frame | go_overload_frame)
+    rx_eof <=#Tp 1'b0;
+  else if (go_rx_eof)
+    rx_eof <=#Tp 1'b1;
+end
+
+
+
+// Interframe space
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    rx_inter <= 1'b0;
+  else if (go_rx_idle | go_rx_id1 | go_overload_frame | go_error_frame)
+    rx_inter <=#Tp 1'b0;
+  else if (go_rx_inter)
+    rx_inter <=#Tp 1'b1;
+end
+
+
+// ID register
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    id <= 29'h0;
+  else if (sample_point & (rx_id1 | rx_id2) & (~bit_de_stuff))
+    id <=#Tp {id[27:0], sampled_bit};
+end
+
+
+// rtr1 bit
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    rtr1 <= 1'b0;
+  else if (sample_point & rx_rtr1 & (~bit_de_stuff))
+    rtr1 <=#Tp sampled_bit;
+end
+
+
+// rtr2 bit
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    rtr2 <= 1'b0;
+  else if (sample_point & rx_rtr2 & (~bit_de_stuff))
+    rtr2 <=#Tp sampled_bit;
+end
+
+
+// ide bit
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    ide <= 1'b0;
+  else if (sample_point & rx_ide & (~bit_de_stuff))
+    ide <=#Tp sampled_bit;
+end
+
+
+// Data length
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    data_len <= 4'b0;
+  else if (sample_point & rx_dlc & (~bit_de_stuff))
+    data_len <=#Tp {data_len[2:0], sampled_bit};
+end
+
+
+// Data
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    tmp_data <= 8'h0;
+  else if (sample_point & rx_data & (~bit_de_stuff))
+    tmp_data <=#Tp {tmp_data[6:0], sampled_bit};
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    write_data_to_tmp_fifo <= 1'b0;
+  else if (sample_point & rx_data & (~bit_de_stuff) & (&bit_cnt[2:0]))
+    write_data_to_tmp_fifo <=#Tp 1'b1;
+  else
+    write_data_to_tmp_fifo <=#Tp 1'b0;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    byte_cnt <= 3'h0;
+  else if (write_data_to_tmp_fifo)
+    byte_cnt <=#Tp byte_cnt + 1'b1;
+  else if (sample_point & go_rx_crc_lim)
+    byte_cnt <=#Tp 3'h0;
+end
+
+
+//always @ (posedge clk)
+always @ (posedge clk or posedge rst)
+begin
+  if(rst)
+  begin
+    tmp_fifo[0] <= 8'h0;
+    tmp_fifo[1] <= 8'h0;
+    tmp_fifo[2] <= 8'h0;
+    tmp_fifo[3] <= 8'h0;
+    tmp_fifo[4] <= 8'h0;
+    tmp_fifo[5] <= 8'h0;
+    tmp_fifo[6] <= 8'h0;
+    tmp_fifo[7] <= 8'h0;
+  end
+  else if (write_data_to_tmp_fifo)
+    tmp_fifo[byte_cnt] <=#Tp tmp_data;
+end
+
+
+
+// CRC
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    crc_in <= 15'h0;
+  else if (sample_point & rx_crc & (~bit_de_stuff))
+    crc_in <=#Tp {crc_in[13:0], sampled_bit};
+end
+
+
+// bit_cnt
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    bit_cnt <= 6'd0;
+  else if (go_rx_id1 | go_rx_id2 | go_rx_dlc | go_rx_data | go_rx_crc | 
+           go_rx_ack | go_rx_eof | go_rx_inter | go_error_frame | go_overload_frame)
+    bit_cnt <=#Tp 6'd0;
+  else if (sample_point & (~bit_de_stuff))
+    bit_cnt <=#Tp bit_cnt + 1'b1;
+end
+
+
+// eof_cnt
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    eof_cnt <= 3'd0;
+  else if (sample_point)
+    begin
+      if (go_rx_inter | go_error_frame | go_overload_frame)
+        eof_cnt <=#Tp 3'd0;
+      else if (rx_eof)
+        eof_cnt <=#Tp eof_cnt + 1'b1;
+    end
+end
+
+
+// Enabling bit de-stuffing
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    bit_stuff_cnt_en <= 1'b0;
+  else if (bit_de_stuff_set)
+    bit_stuff_cnt_en <=#Tp 1'b1;
+  else if (bit_de_stuff_reset)
+    bit_stuff_cnt_en <=#Tp 1'b0;
+end
+
+
+// bit_stuff_cnt
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    bit_stuff_cnt <= 3'h1;
+  else if (bit_de_stuff_reset)
+    bit_stuff_cnt <=#Tp 3'h1;
+  else if (sample_point & bit_stuff_cnt_en)
+    begin
+      if (bit_stuff_cnt == 3'h5)
+        bit_stuff_cnt <=#Tp 3'h1;
+      else if (sampled_bit == sampled_bit_q)
+        bit_stuff_cnt <=#Tp bit_stuff_cnt + 1'b1;
+      else
+        bit_stuff_cnt <=#Tp 3'h1;
+    end
+end
+
+
+// bit_stuff_cnt_tx
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    bit_stuff_cnt_tx <= 3'h1;
+  else if (reset_mode || bit_de_stuff_reset)
+    bit_stuff_cnt_tx <=#Tp 3'h1;
+  else if (tx_point_q & bit_stuff_cnt_en)
+    begin
+      if (bit_stuff_cnt_tx == 3'h5)
+        bit_stuff_cnt_tx <=#Tp 3'h1;
+      else if (tx == tx_q)
+        bit_stuff_cnt_tx <=#Tp bit_stuff_cnt_tx + 1'b1;
+      else
+        bit_stuff_cnt_tx <=#Tp 3'h1;
+    end
+end
+
+
+assign bit_de_stuff = bit_stuff_cnt == 3'h5;
+assign bit_de_stuff_tx = bit_stuff_cnt_tx == 3'h5;
+
+
+
+// stuff_err
+assign stuff_err = sample_point & bit_stuff_cnt_en & bit_de_stuff & (sampled_bit == sampled_bit_q);
+
+
+
+// Generating delayed signals
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    begin
+      reset_mode_q <=#Tp 1'b0;
+      node_bus_off_q <=#Tp 1'b0;
+    end
+  else
+    begin
+      reset_mode_q <=#Tp reset_mode;
+      node_bus_off_q <=#Tp node_bus_off;
+    end
+end
+
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    crc_enable <= 1'b0;
+  else if (rst_crc_enable)
+    crc_enable <=#Tp 1'b0;
+  else if (go_crc_enable)
+    crc_enable <=#Tp 1'b1;
+end
+
+
+// CRC error generation
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    crc_err <= 1'b0;
+  else if (reset_mode | error_frame_ended)
+    crc_err <=#Tp 1'b0;
+  else if (go_rx_ack)
+    crc_err <=#Tp crc_in != calculated_crc;
+end
+
+
+// Conditions for form error
+assign form_err = sample_point & ( ((~bit_de_stuff) & rx_crc_lim & (~sampled_bit)                  ) |
+                                   (                  rx_ack_lim & (~sampled_bit)                  ) |
+                                   ((eof_cnt < 3'd6)& rx_eof     & (~sampled_bit) & (~transmitter) ) |
+                                   (                & rx_eof     & (~sampled_bit) &   transmitter  )
+                                 );
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    ack_err_latched <= 1'b0;
+  else if (reset_mode | error_frame_ended | go_overload_frame)
+    ack_err_latched <=#Tp 1'b0;
+  else if (ack_err)
+    ack_err_latched <=#Tp 1'b1;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    bit_err_latched <= 1'b0;
+  else if (reset_mode | error_frame_ended | go_overload_frame)
+    bit_err_latched <=#Tp 1'b0;
+  else if (bit_err)
+    bit_err_latched <=#Tp 1'b1;
+end
+
+
+
+// Rule 5 (Fault confinement).
+assign rule5 = bit_err &  ( (~node_error_passive) & error_frame    & (error_cnt1    < 3'd7)
+                            | 
+                                                    overload_frame & (overload_cnt1 < 3'd7)
+                          );
+
+// Rule 3 exception 1 - first part (Fault confinement).
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    rule3_exc1_1 <= 1'b0;
+  else if (error_flag_over | rule3_exc1_2)
+    rule3_exc1_1 <=#Tp 1'b0;
+  else if (transmitter & node_error_passive & ack_err)
+    rule3_exc1_1 <=#Tp 1'b1;
+end
+
+
+// Rule 3 exception 1 - second part (Fault confinement).
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    rule3_exc1_2 <= 1'b0;
+  else if (go_error_frame | rule3_exc1_2)
+    rule3_exc1_2 <=#Tp 1'b0;
+  else if (rule3_exc1_1 & (error_cnt1 < 3'd7) & sample_point & (~sampled_bit))
+    rule3_exc1_2 <=#Tp 1'b1;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    stuff_err_latched <= 1'b0;
+  else if (reset_mode | error_frame_ended | go_overload_frame)
+    stuff_err_latched <=#Tp 1'b0;
+  else if (stuff_err)
+    stuff_err_latched <=#Tp 1'b1;
+end
+
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    form_err_latched <= 1'b0;
+  else if (reset_mode | error_frame_ended | go_overload_frame)
+    form_err_latched <=#Tp 1'b0;
+  else if (form_err)
+    form_err_latched <=#Tp 1'b1;
+end
+
+
+
+// Instantiation of the RX CRC module
+can_crc i_can_crc_rx 
+(
+  .clk(clk),
+  .data(sampled_bit),
+  .enable(crc_enable & sample_point & (~bit_de_stuff)),
+  .initialize(go_crc_enable),
+  .crc(calculated_crc)
+);
+
+
+
+
+assign no_byte0 = rtr1 | (data_len<4'h1);
+assign no_byte1 = rtr1 | (data_len<4'h2);
+
+can_acf i_can_acf
+(
+  .clk(clk),
+  .rst(rst),
+  
+  .id(id),
+
+  /* Mode register */
+  .reset_mode(reset_mode),
+  .acceptance_filter_mode(acceptance_filter_mode),
+
+  // Clock Divider register
+  .extended_mode(extended_mode),
+  
+  /* This section is for BASIC and EXTENDED mode */
+  /* Acceptance code register */
+  .acceptance_code_0(acceptance_code_0),
+
+  /* Acceptance mask register */
+  .acceptance_mask_0(acceptance_mask_0),
+  /* End: This section is for BASIC and EXTENDED mode */
+  
+  /* This section is for EXTENDED mode */
+  /* Acceptance code register */
+  .acceptance_code_1(acceptance_code_1),
+  .acceptance_code_2(acceptance_code_2),
+  .acceptance_code_3(acceptance_code_3),
+
+  /* Acceptance mask register */
+  .acceptance_mask_1(acceptance_mask_1),
+  .acceptance_mask_2(acceptance_mask_2),
+  .acceptance_mask_3(acceptance_mask_3),
+  /* End: This section is for EXTENDED mode */
+
+  .go_rx_crc_lim(go_rx_crc_lim),
+  .go_rx_inter(go_rx_inter),
+  .go_error_frame(go_error_frame),
+  
+  .data0(tmp_fifo[0]),
+  .data1(tmp_fifo[1]),
+  .rtr1(rtr1),
+  .rtr2(rtr2),
+  .ide(ide),
+  .no_byte0(no_byte0),
+  .no_byte1(no_byte1),
+
+  .id_ok(id_ok)
+
+);
+
+
+
+
+assign header_len[2:0] = extended_mode ? (ide? (3'h5) : (3'h3)) : 3'h2;
+assign storing_header = header_cnt < header_len;
+assign limited_data_len_minus1[3:0] = remote_rq? 4'hf : ((data_len < 4'h8)? (data_len -1'b1) : 4'h7);   // - 1 because counter counts from 0
+assign reset_wr_fifo = (data_cnt == (limited_data_len_minus1 + {1'b0, header_len})) || reset_mode;
+
+assign err = form_err | stuff_err | bit_err | ack_err | form_err_latched | stuff_err_latched | bit_err_latched | ack_err_latched | crc_err;
+
+
+
+// Write enable signal for 64-byte rx fifo
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    wr_fifo <= 1'b0;
+  else if (reset_wr_fifo)
+    wr_fifo <=#Tp 1'b0;
+  else if (go_rx_inter & id_ok & (~error_frame_ended) & ((~tx_state) | self_rx_request))
+    wr_fifo <=#Tp 1'b1;
+end
+
+
+// Header counter. Header length depends on the mode of operation and frame format.
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    header_cnt <= 3'h0;
+  else if (reset_wr_fifo)
+    header_cnt <=#Tp 3'h0;
+  else if (wr_fifo & storing_header)
+    header_cnt <=#Tp header_cnt + 1'h1;
+end
+
+
+// Data counter. Length of the data is limited to 8 bytes.
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    data_cnt <= 4'h0;
+  else if (reset_wr_fifo)
+    data_cnt <=#Tp 4'h0;
+  else if (wr_fifo)
+    data_cnt <=#Tp data_cnt + 4'h1;
+end
+
+
+// Multiplexing data that is stored to 64-byte fifo depends on the mode of operation and frame format
+always @ (extended_mode or ide or data_cnt or header_cnt or  header_len or 
+          storing_header or id or rtr1 or rtr2 or data_len or
+          tmp_fifo[0] or tmp_fifo[2] or tmp_fifo[4] or tmp_fifo[6] or 
+          tmp_fifo[1] or tmp_fifo[3] or tmp_fifo[5] or tmp_fifo[7])
+begin
+  casex ({storing_header, extended_mode, ide, header_cnt}) /* synthesis parallel_case */ 
+    6'b1_1_1_000  : data_for_fifo = {1'b1, rtr2, 2'h0, data_len};  // extended mode, extended format header
+    6'b1_1_1_001  : data_for_fifo = id[28:21];                     // extended mode, extended format header
+    6'b1_1_1_010  : data_for_fifo = id[20:13];                     // extended mode, extended format header
+    6'b1_1_1_011  : data_for_fifo = id[12:5];                      // extended mode, extended format header
+    6'b1_1_1_100  : data_for_fifo = {id[4:0], 3'h0};               // extended mode, extended format header
+    6'b1_1_0_000  : data_for_fifo = {1'b0, rtr1, 2'h0, data_len};  // extended mode, standard format header
+    6'b1_1_0_001  : data_for_fifo = id[10:3];                      // extended mode, standard format header
+    6'b1_1_0_010  : data_for_fifo = {id[2:0], rtr1, 4'h0};         // extended mode, standard format header
+    6'b1_0_x_000  : data_for_fifo = id[10:3];                      // normal mode                    header
+    6'b1_0_x_001  : data_for_fifo = {id[2:0], rtr1, data_len};     // normal mode                    header
+    default       : data_for_fifo = tmp_fifo[data_cnt - {1'b0, header_len}]; // data 
+  endcase
+end
+
+
+assign rx_we = (~wr_fifo) & wr_fifo_q;
+
+// Delayed write signal
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    wr_fifo_q <=#Tp 1'b0;
+  else if (reset_mode)
+    wr_fifo_q <=#Tp 1'b0;
+  else
+    wr_fifo_q <=#Tp wr_fifo;
+end
+
+wire [28:0] rxid;
+wire rxfmt = (extended_mode&ide)? 1'h1: 1'h0;
+wire rxrtr = (extended_mode&ide)? rtr2: rtr1;
+assign rxid  = (extended_mode&ide)? id: {id[10:0],18'h0};
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+  begin
+    rx_dt <= 128'h0;
+  end
+  else if (wr_fifo)
+  begin
+    rx_dt[0*32+31:0*32+00] <= {rxfmt, 2'h0, rxid};
+    rx_dt[1*32+31:1*32+00] <= {24'h0, 3'h0, rxrtr, data_len};
+    rx_dt[2*32+31:2*32+00] <= {tmp_fifo[3], tmp_fifo[2], tmp_fifo[1], tmp_fifo[0]};
+    rx_dt[3*32+31:3*32+00] <= {tmp_fifo[7], tmp_fifo[6], tmp_fifo[5], tmp_fifo[4]};
+  end
+end
+
+
+// Instantiation of the RX fifo module
+can_fifo i_can_fifo
+( 
+  .clk(clk),
+  .rst(rst),
+
+  .wr(1'h0),
+
+  .data_in(data_for_fifo),
+  .addr(addr[5:0]),
+  .data_out(data_out),
+  .fifo_selected(fifo_selected),
+
+  .reset_mode(reset_mode),
+  .release_buffer(release_buffer),
+  .extended_mode(extended_mode),
+  .overrun(overrun),
+  .info_empty(info_empty),
+  .info_cnt(rx_message_counter)
+
+`ifdef CAN_BIST
+  ,
+  .mbist_si_i(mbist_si_i),
+  .mbist_so_o(mbist_so_o),
+  .mbist_ctrl_i(mbist_ctrl_i)
+`endif
+);
+
+
+// Transmitting error frame.
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    error_frame <= 1'b0;
+//  else if (reset_mode || error_frame_ended || go_overload_frame)
+  else if (set_reset_mode || error_frame_ended || go_overload_frame)
+    error_frame <=#Tp 1'b0;
+  else if (go_error_frame)
+    error_frame <=#Tp 1'b1;
+end
+
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    error_cnt1 <= 3'd0;
+  else if (error_frame_ended | go_error_frame | go_overload_frame)
+    error_cnt1 <=#Tp 3'd0;
+  else if (error_frame & tx_point & (error_cnt1 < 3'd7))
+    error_cnt1 <=#Tp error_cnt1 + 1'b1;
+end
+
+
+
+assign error_flag_over = ((~node_error_passive) & sample_point & (error_cnt1 == 3'd7) | node_error_passive  & sample_point & (passive_cnt == 3'h6)) & (~enable_error_cnt2);
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    error_flag_over_latched <= 1'b0;
+  else if (error_frame_ended | go_error_frame | go_overload_frame)
+    error_flag_over_latched <=#Tp 1'b0;
+  else if (error_flag_over)
+    error_flag_over_latched <=#Tp 1'b1;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    enable_error_cnt2 <= 1'b0;
+  else if (error_frame_ended | go_error_frame | go_overload_frame)
+    enable_error_cnt2 <=#Tp 1'b0;
+  else if (error_frame & (error_flag_over & sampled_bit))
+    enable_error_cnt2 <=#Tp 1'b1;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    error_cnt2 <= 3'd0;
+  else if (error_frame_ended | go_error_frame | go_overload_frame)
+    error_cnt2 <=#Tp 3'd0;
+  else if (enable_error_cnt2 & tx_point)
+    error_cnt2 <=#Tp error_cnt2 + 1'b1;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    delayed_dominant_cnt <= 3'h0;
+  else if (enable_error_cnt2 | go_error_frame | enable_overload_cnt2 | go_overload_frame)
+    delayed_dominant_cnt <=#Tp 3'h0;
+  else if (sample_point & (~sampled_bit) & ((error_cnt1 == 3'd7) | (overload_cnt1 == 3'd7)))
+    delayed_dominant_cnt <=#Tp delayed_dominant_cnt + 1'b1;
+end
+
+
+// passive_cnt
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    passive_cnt <= 3'h1;
+  else if (error_frame_ended | go_error_frame | go_overload_frame | first_compare_bit)
+    passive_cnt <=#Tp 3'h1;
+  else if (sample_point & (passive_cnt < 3'h6))
+    begin
+      if (error_frame & (~enable_error_cnt2) & (sampled_bit == sampled_bit_q))
+        passive_cnt <=#Tp passive_cnt + 1'b1;
+      else
+        passive_cnt <=#Tp 3'h1;
+    end
+end
+
+
+// When comparing 6 equal bits, first is always equal
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    first_compare_bit <= 1'b0;
+  else if (go_error_frame)
+    first_compare_bit <=#Tp 1'b1;
+  else if (sample_point)
+    first_compare_bit <= 1'b0;
+end
+
+
+// Transmitting overload frame.
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    overload_frame <= 1'b0;
+  else if (overload_frame_ended | go_error_frame)
+    overload_frame <=#Tp 1'b0;
+  else if (go_overload_frame)
+    overload_frame <=#Tp 1'b1;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    overload_cnt1 <= 3'd0;
+  else if (overload_frame_ended | go_error_frame | go_overload_frame)
+    overload_cnt1 <=#Tp 3'd0;
+  else if (overload_frame & tx_point & (overload_cnt1 < 3'd7))
+    overload_cnt1 <=#Tp overload_cnt1 + 1'b1;
+end
+
+
+assign overload_flag_over = sample_point & (overload_cnt1 == 3'd7) & (~enable_overload_cnt2);
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    enable_overload_cnt2 <= 1'b0;
+  else if (overload_frame_ended | go_error_frame | go_overload_frame)
+    enable_overload_cnt2 <=#Tp 1'b0;
+  else if (overload_frame & (overload_flag_over & sampled_bit))
+    enable_overload_cnt2 <=#Tp 1'b1;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    overload_cnt2 <= 3'd0;
+  else if (overload_frame_ended | go_error_frame | go_overload_frame)
+    overload_cnt2 <=#Tp 3'd0;
+  else if (enable_overload_cnt2 & tx_point)
+    overload_cnt2 <=#Tp overload_cnt2 + 1'b1;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    overload_request_cnt <= 2'b0;
+  else if (go_error_frame | go_rx_id1)
+    overload_request_cnt <=#Tp 2'b0;
+  else if (overload_request & overload_frame)
+    overload_request_cnt <=#Tp overload_request_cnt + 1'b1;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    overload_frame_blocked <= 1'b0;
+  else if (go_error_frame | go_rx_id1)
+    overload_frame_blocked <=#Tp 1'b0;
+  else if (overload_request & overload_frame & overload_request_cnt == 2'h2)   // This is a second sequential overload_request
+    overload_frame_blocked <=#Tp 1'b1;
+end
+
+
+assign send_ack = (~tx_state) & rx_ack & (~err) & (~listen_only_mode);
+
+
+
+always @ (reset_mode or node_bus_off or tx_state or go_tx or bit_de_stuff_tx or tx_bit or tx_q or
+          send_ack or go_overload_frame or overload_frame or overload_cnt1 or
+          go_error_frame or error_frame or error_cnt1 or node_error_passive)
+begin
+  if (reset_mode | node_bus_off)                                                // Reset or node_bus_off
+    tx_next = 1'b1;
+  else
+    begin
+      if (go_error_frame | error_frame)                                         // Transmitting error frame
+        begin
+          if (error_cnt1 < 3'd6)
+            begin
+              if (node_error_passive)
+                tx_next = 1'b1;
+              else
+                tx_next = 1'b0;
+            end
+          else
+            tx_next = 1'b1;
+        end
+      else if (go_overload_frame | overload_frame)                              // Transmitting overload frame
+        begin
+          if (overload_cnt1 < 3'd6)
+            tx_next = 1'b0;
+          else
+            tx_next = 1'b1;
+        end
+      else if (go_tx | tx_state)                                                        // Transmitting message
+        tx_next = ((~bit_de_stuff_tx) & tx_bit) | (bit_de_stuff_tx & (~tx_q));
+      else if (send_ack)                                                        // Acknowledge
+        tx_next = 1'b0;
+      else
+        tx_next = 1'b1;
+    end
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    tx <= 1'b1;
+  else if (reset_mode)
+    tx <= 1'b1;
+  else if (tx_point)
+    tx <=#Tp tx_next;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    tx_q <=#Tp 1'b0;
+  else if (reset_mode)
+    tx_q <=#Tp 1'b0;
+  else if (tx_point)
+    tx_q <=#Tp tx & (~go_early_tx_latched);
+end
+
+
+/* Delayed tx point */
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    tx_point_q <=#Tp 1'b0;
+  else if (reset_mode)
+    tx_point_q <=#Tp 1'b0;
+  else
+    tx_point_q <=#Tp tx_point;
+end
+
+
+/* Changing bit order from [7:0] to [0:7] */
+can_ibo i_ibo_tx_data_0  (.di(tx_data_0),  .do(r_tx_data_0));
+can_ibo i_ibo_tx_data_1  (.di(tx_data_1),  .do(r_tx_data_1));
+can_ibo i_ibo_tx_data_2  (.di(tx_data_2),  .do(r_tx_data_2));
+can_ibo i_ibo_tx_data_3  (.di(tx_data_3),  .do(r_tx_data_3));
+can_ibo i_ibo_tx_data_4  (.di(tx_data_4),  .do(r_tx_data_4));
+can_ibo i_ibo_tx_data_5  (.di(tx_data_5),  .do(r_tx_data_5));
+can_ibo i_ibo_tx_data_6  (.di(tx_data_6),  .do(r_tx_data_6));
+can_ibo i_ibo_tx_data_7  (.di(tx_data_7),  .do(r_tx_data_7));
+can_ibo i_ibo_tx_data_8  (.di(tx_data_8),  .do(r_tx_data_8));
+can_ibo i_ibo_tx_data_9  (.di(tx_data_9),  .do(r_tx_data_9));
+can_ibo i_ibo_tx_data_10 (.di(tx_data_10), .do(r_tx_data_10));
+can_ibo i_ibo_tx_data_11 (.di(tx_data_11), .do(r_tx_data_11));
+can_ibo i_ibo_tx_data_12 (.di(tx_data_12), .do(r_tx_data_12));
+
+/* Changing bit order from [14:0] to [0:14] */
+can_ibo i_calculated_crc0 (.di(calculated_crc[14:7]), .do(r_calculated_crc[7:0]));
+can_ibo i_calculated_crc1 (.di({calculated_crc[6:0], 1'b0}), .do(r_calculated_crc[15:8]));
+
+
+assign basic_chain = {r_tx_data_1[7:4], 2'h0, r_tx_data_1[3:0], r_tx_data_0[7:0], 1'b0};
+assign basic_chain_data = {r_tx_data_9, r_tx_data_8, r_tx_data_7, r_tx_data_6, r_tx_data_5, r_tx_data_4, r_tx_data_3, r_tx_data_2};
+assign extended_chain_std = {r_tx_data_0[7:4], 2'h0, r_tx_data_0[1], r_tx_data_2[2:0], r_tx_data_1[7:0], 1'b0};
+assign extended_chain_ext = {r_tx_data_0[7:4], 2'h0, r_tx_data_0[1], r_tx_data_4[4:0], r_tx_data_3[7:0], r_tx_data_2[7:3], 1'b1, 1'b1, r_tx_data_2[2:0], r_tx_data_1[7:0], 1'b0};
+assign extended_chain_data_std = {r_tx_data_10, r_tx_data_9, r_tx_data_8, r_tx_data_7, r_tx_data_6, r_tx_data_5, r_tx_data_4, r_tx_data_3};
+assign extended_chain_data_ext = {r_tx_data_12, r_tx_data_11, r_tx_data_10, r_tx_data_9, r_tx_data_8, r_tx_data_7, r_tx_data_6, r_tx_data_5};
+
+always @ (extended_mode or rx_data or tx_pointer or extended_chain_data_std or extended_chain_data_ext or rx_crc or r_calculated_crc or
+          r_tx_data_0   or extended_chain_ext or extended_chain_std or basic_chain_data or basic_chain or
+          finish_msg)
+begin
+  if (extended_mode)
+    begin
+      if (rx_data)  // data stage
+        if (r_tx_data_0[0])    // Extended frame
+          tx_bit = extended_chain_data_ext[tx_pointer];
+        else
+          tx_bit = extended_chain_data_std[tx_pointer];
+      else if (rx_crc)
+        tx_bit = r_calculated_crc[tx_pointer];
+      else if (finish_msg)
+        tx_bit = 1'b1;
+      else
+        begin
+          if (r_tx_data_0[0])    // Extended frame
+            tx_bit = extended_chain_ext[tx_pointer];
+          else
+            tx_bit = extended_chain_std[tx_pointer];
+        end
+    end
+  else  // Basic mode
+    begin
+      if (rx_data)  // data stage
+        tx_bit = basic_chain_data[tx_pointer];
+      else if (rx_crc)
+        tx_bit = r_calculated_crc[tx_pointer];
+      else if (finish_msg)
+        tx_bit = 1'b1;
+      else
+        tx_bit = basic_chain[tx_pointer];
+    end
+end
+
+
+assign limited_tx_cnt_ext = tx_data_0[3] ? 6'h3f : ((tx_data_0[2:0] <<3) - 1'b1);
+assign limited_tx_cnt_std = tx_data_1[3] ? 6'h3f : ((tx_data_1[2:0] <<3) - 1'b1);
+
+assign rst_tx_pointer = ((~bit_de_stuff_tx) & tx_point & (~rx_data) &   extended_mode  &   r_tx_data_0[0]   & tx_pointer == 6'd38             ) |   // arbitration + control for extended format
+                        ((~bit_de_stuff_tx) & tx_point & (~rx_data) &   extended_mode  & (~r_tx_data_0[0])  & tx_pointer == 6'd18             ) |   // arbitration + control for extended format
+                        ((~bit_de_stuff_tx) & tx_point & (~rx_data) & (~extended_mode)                      & tx_pointer == 6'd18             ) |   // arbitration + control for standard format
+                        ((~bit_de_stuff_tx) & tx_point &   rx_data  &   extended_mode                       & tx_pointer == limited_tx_cnt_ext) |   // data       (overflow is OK here)
+                        ((~bit_de_stuff_tx) & tx_point &   rx_data  & (~extended_mode)                      & tx_pointer == limited_tx_cnt_std) |   // data       (overflow is OK here)
+                        (                     tx_point &   rx_crc_lim                                                                         ) |   // crc
+                        (go_rx_idle                                                                                                           ) |   // at the end
+                        (reset_mode                                                                                                           ) |
+                        (overload_frame                                                                                                       ) |
+                        (error_frame                                                                                                          ) ;
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    tx_pointer <= 6'h0;
+  else if (rst_tx_pointer)
+    tx_pointer <=#Tp 6'h0;
+  else if (go_early_tx | (tx_point & (tx_state | go_tx) & (~bit_de_stuff_tx)))
+    tx_pointer <=#Tp tx_pointer + 1'b1;
+end
+
+
+assign tx_successful = transmitter & go_rx_inter & (~go_error_frame) & (~error_frame_ended) & (~overload_frame_ended) & (~arbitration_lost);
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    need_to_tx <= 1'b0;
+  else if (tx_successful | reset_mode | (abort_tx & (~transmitting)) | ((~tx_state) & tx_state_q & single_shot_transmission))
+    need_to_tx <=#Tp 1'h0;
+  else if (tx_request & sample_point)
+    need_to_tx <=#Tp 1'b1;
+end
+
+
+
+assign go_early_tx = (~listen_only_mode) & need_to_tx & (~tx_state) & (~suspend | (susp_cnt == 3'h7)) & sample_point & (~sampled_bit) & (rx_idle | last_bit_of_inter);
+assign go_tx       = (~listen_only_mode) & need_to_tx & (~tx_state) & (~suspend | (sample_point & (susp_cnt == 3'h7))) & (go_early_tx | rx_idle);
+
+// go_early_tx latched (for proper bit_de_stuff generation)
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    go_early_tx_latched <= 1'b0;
+  else if (reset_mode || tx_point)
+    go_early_tx_latched <=#Tp 1'b0;
+  else if (go_early_tx)
+    go_early_tx_latched <=#Tp 1'b1;
+end
+
+
+
+// Tx state
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    tx_state <= 1'b0;
+  else if (reset_mode | go_rx_inter | error_frame | arbitration_lost)
+    tx_state <=#Tp 1'b0;
+  else if (go_tx)
+    tx_state <=#Tp 1'b1;
+end
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    tx_state_q <=#Tp 1'b0;
+  else if (reset_mode)
+    tx_state_q <=#Tp 1'b0;
+  else
+    tx_state_q <=#Tp tx_state;
+end
+
+
+
+// Node is a transmitter
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    transmitter <= 1'b0;
+  else if (go_tx)
+    transmitter <=#Tp 1'b1;
+  else if (reset_mode | go_rx_idle | suspend & go_rx_id1)
+    transmitter <=#Tp 1'b0;
+end
+ 
+
+
+// Signal "transmitting" signals that the core is a transmitting (message, error frame or overload frame). No synchronization is done meanwhile.
+// Node might be both transmitter or receiver (sending error or overload frame)
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    transmitting <= 1'b0;
+  else if (go_error_frame | go_overload_frame | go_tx | send_ack)
+    transmitting <=#Tp 1'b1;
+  else if (reset_mode | go_rx_idle | (go_rx_id1 & (~tx_state)) | (arbitration_lost & tx_state))
+    transmitting <=#Tp 1'b0;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    suspend <= 1'b0;
+  else if (reset_mode | (sample_point & (susp_cnt == 3'h7)))
+    suspend <=#Tp 1'b0;
+  else if (not_first_bit_of_inter & transmitter & node_error_passive)
+    suspend <=#Tp 1'b1;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    susp_cnt_en <= 1'b0;
+  else if (reset_mode | (sample_point & (susp_cnt == 3'h7)))
+    susp_cnt_en <=#Tp 1'b0;
+  else if (suspend & sample_point & last_bit_of_inter)
+    susp_cnt_en <=#Tp 1'b1;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    susp_cnt <= 3'h0;
+  else if (reset_mode | (sample_point & (susp_cnt == 3'h7)))
+    susp_cnt <=#Tp 3'h0;
+  else if (susp_cnt_en & sample_point)
+    susp_cnt <=#Tp susp_cnt + 1'b1;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    finish_msg <= 1'b0;
+  else if (go_rx_idle | go_rx_id1 | error_frame | reset_mode)
+    finish_msg <=#Tp 1'b0;
+  else if (go_rx_crc_lim)
+    finish_msg <=#Tp 1'b1;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    arbitration_lost <= 1'b0;
+  else if (go_rx_idle | error_frame_ended)
+    arbitration_lost <=#Tp 1'b0;
+  else if (transmitter & sample_point & tx & arbitration_field & ~sampled_bit)
+    arbitration_lost <=#Tp 1'b1;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    arbitration_lost_q <=#Tp 1'b0;
+  else
+    arbitration_lost_q <=#Tp arbitration_lost;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    arbitration_field_d <=#Tp 1'b0;
+  else if (sample_point)
+    arbitration_field_d <=#Tp arbitration_field;
+end
+
+
+assign set_arbitration_lost_irq = arbitration_lost & (~arbitration_lost_q) & (~arbitration_blocked);
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    arbitration_cnt <= 5'h0;
+  else if (sample_point && !bit_de_stuff)
+    if (arbitration_field_d)
+      arbitration_cnt <=#Tp arbitration_cnt + 1'b1;
+    else
+      arbitration_cnt <=#Tp 5'h0;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    arbitration_lost_capture <= 5'h0;
+  else if (set_arbitration_lost_irq)
+    arbitration_lost_capture <=#Tp arbitration_cnt;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    arbitration_blocked <= 1'b0;
+  else if (read_arbitration_lost_capture_reg)
+    arbitration_blocked <=#Tp 1'b0;
+  else if (set_arbitration_lost_irq)
+    arbitration_blocked <=#Tp 1'b1;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    rx_err_cnt <= 9'h0;
+  else if (we_rx_err_cnt & (~node_bus_off))
+    rx_err_cnt <=#Tp {1'b0, data_in[23:16]};
+  else if (set_reset_mode)
+    rx_err_cnt <=#Tp 9'h0;
+  else
+    begin
+      if ((~listen_only_mode) & (~transmitter | arbitration_lost))
+        begin
+          if (go_rx_ack_lim & (~go_error_frame) & (~crc_err) & (rx_err_cnt > 9'h0))
+            begin
+              if (rx_err_cnt > 9'd127)
+                rx_err_cnt <=#Tp 9'd127;
+              else
+                rx_err_cnt <=#Tp rx_err_cnt - 1'b1;
+            end
+          else if (rx_err_cnt < 9'd128)
+            begin
+              if (go_error_frame & (~rule5))                                                                                          // 1  (rule 5 is just the opposite then rule 1 exception
+                rx_err_cnt <=#Tp rx_err_cnt + 1'b1;
+              else if ( (error_flag_over & (~error_flag_over_latched) & sample_point & (~sampled_bit) & (error_cnt1 == 3'd7)     ) |  // 2
+                        (go_error_frame & rule5                                                                                  ) |  // 5
+                        (sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7)                            )                  // 6
+                      )
+                rx_err_cnt <=#Tp rx_err_cnt + 4'h8;
+            end
+        end
+    end
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    tx_err_cnt <= 9'h0;
+  else if (we_tx_err_cnt)
+    tx_err_cnt <=#Tp {1'b0, data_in[31:24]};
+  else
+    begin
+      if (set_reset_mode)
+        tx_err_cnt <=#Tp 9'd128;
+      else if ((tx_err_cnt > 9'd0) & (tx_successful | bus_free))
+        tx_err_cnt <=#Tp tx_err_cnt - 1'h1;
+      else if (transmitter & (~arbitration_lost))
+        begin
+          if ( (sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7)                                          ) |       // 6
+               (go_error_frame & rule5                                                                                  ) |       // 4  (rule 5 is the same as rule 4)
+               (go_error_frame & (~(transmitter & node_error_passive & ack_err)) & (~(transmitter & stuff_err & 
+                arbitration_field & sample_point & tx & (~sampled_bit)))                                                ) |       // 3 
+               (error_frame & rule3_exc1_2                                                                              )         // 3
+             )
+            tx_err_cnt <=#Tp tx_err_cnt + 4'h8;
+        end
+    end
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    node_error_passive <= 1'b0;
+  else if ((rx_err_cnt < 128) & (tx_err_cnt < 9'd128))
+    node_error_passive <=#Tp 1'b0;
+  else if (((rx_err_cnt >= 128) | (tx_err_cnt >= 9'd128)) & (error_frame_ended | go_error_frame | (~reset_mode) & reset_mode_q) & (~node_bus_off))
+    node_error_passive <=#Tp 1'b1;
+end
+
+
+assign node_error_active = ~(node_error_passive | node_bus_off);
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    node_bus_off <= 1'b0;
+  else if ((rx_err_cnt == 9'h0) & (tx_err_cnt == 9'd0) & (~reset_mode) | (we_tx_err_cnt & (data_in[31:24] < 8'd255)))
+    node_bus_off <=#Tp 1'b0;
+  else if ((tx_err_cnt >= 9'd256) | (we_tx_err_cnt & (data_in[31:24] == 8'd255)))
+    node_bus_off <=#Tp 1'b1;
+end
+
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    bus_free_cnt <= 4'h0;
+  else if (sample_point)
+    begin
+      if (sampled_bit & bus_free_cnt_en & (bus_free_cnt < 4'd10))
+        bus_free_cnt <=#Tp bus_free_cnt + 1'b1;
+      else
+        bus_free_cnt <=#Tp 4'h0;
+    end
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    bus_free_cnt_en <= 1'b0;
+  else if ((~reset_mode) & reset_mode_q | node_bus_off_q & (~reset_mode))
+    bus_free_cnt_en <=#Tp 1'b1;
+  else if (sample_point & sampled_bit & (bus_free_cnt==4'd10) & (~node_bus_off))
+    bus_free_cnt_en <=#Tp 1'b0;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    bus_free <= 1'b0;
+  else if (sample_point & sampled_bit & (bus_free_cnt==4'd10) && waiting_for_bus_free)
+    bus_free <=#Tp 1'b1;
+  else
+    bus_free <=#Tp 1'b0;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    waiting_for_bus_free <= 1'b1;
+  else if (bus_free & (~node_bus_off))
+    waiting_for_bus_free <=#Tp 1'b0;
+  else if (node_bus_off_q & (~reset_mode))
+    waiting_for_bus_free <=#Tp 1'b1;
+end
+
+
+assign bus_off_on = ~node_bus_off;
+
+assign set_reset_mode = node_bus_off & (~node_bus_off_q);
+assign error_status = extended_mode? ((rx_err_cnt >= error_warning_limit) | (tx_err_cnt >= error_warning_limit))    :
+                                     ((rx_err_cnt >= 9'd96) | (tx_err_cnt >= 9'd96))                                ;
+
+assign transmit_status = transmitting  || (extended_mode && waiting_for_bus_free);
+assign receive_status  = extended_mode ? (waiting_for_bus_free || (!rx_idle) && (!transmitting)) : 
+                                         ((!waiting_for_bus_free) && (!rx_idle) && (!transmitting));
+
+/* Error code capture register */
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    error_capture_code <= 8'h0;
+  else if (read_error_code_capture_reg)
+    error_capture_code <=#Tp 8'h0;
+  else if (set_bus_error_irq)
+    error_capture_code <=#Tp {error_capture_code_type[7:6], error_capture_code_direction, error_capture_code_segment[4:0]};
+end
+
+
+
+assign error_capture_code_segment[0] = rx_idle | rx_ide | (rx_id2 & (bit_cnt<6'd13)) | rx_r1 | rx_r0 | rx_dlc | rx_ack | rx_ack_lim | error_frame & node_error_active;
+assign error_capture_code_segment[1] = rx_idle | rx_id1 | rx_id2 | rx_dlc | rx_data | rx_ack_lim | rx_eof | rx_inter | error_frame & node_error_passive;
+assign error_capture_code_segment[2] = (rx_id1 & (bit_cnt>6'd7)) | rx_rtr1 | rx_ide | rx_id2 | rx_rtr2 | rx_r1 | error_frame & node_error_passive | overload_frame;
+assign error_capture_code_segment[3] = (rx_id2 & (bit_cnt>6'd4)) | rx_rtr2 | rx_r1 | rx_r0 | rx_dlc | rx_data | rx_crc | rx_crc_lim | rx_ack | rx_ack_lim | rx_eof | overload_frame;
+assign error_capture_code_segment[4] = rx_crc_lim | rx_ack | rx_ack_lim | rx_eof | rx_inter | error_frame | overload_frame;
+assign error_capture_code_direction  = ~transmitting;
+
+
+always @ (bit_err or form_err or stuff_err)
+begin
+  if (bit_err)
+    error_capture_code_type[7:6] = 2'b00;
+  else if (form_err)
+    error_capture_code_type[7:6] = 2'b01;
+  else if (stuff_err)
+    error_capture_code_type[7:6] = 2'b10;
+  else
+    error_capture_code_type[7:6] = 2'b11;
+end
+
+
+assign set_bus_error_irq = go_error_frame & (~error_capture_code_blocked);
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    error_capture_code_blocked <= 1'b0;
+  else if (read_error_code_capture_reg)
+    error_capture_code_blocked <=#Tp 1'b0;
+  else if (set_bus_error_irq)
+    error_capture_code_blocked <=#Tp 1'b1;
+end
+
+
+endmodule
+
Index: /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_btl.v
===================================================================
--- /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_btl.v	(revision 295)
+++ /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_btl.v	(revision 295)
@@ -0,0 +1,484 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  can_btl.v                                                   ////
+////                                                              ////
+////                                                              ////
+////  This file is part of the CAN Protocol Controller            ////
+////  http://www.opencores.org/projects/can/                      ////
+////                                                              ////
+////                                                              ////
+////  Author(s):                                                  ////
+////       Igor Mohor                                             ////
+////       igorm@opencores.org                                    ////
+////                                                              ////
+////                                                              ////
+////  All additional information is available in the README.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002, 2003, 2004 Authors                       ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//// The CAN protocol is developed by Robert Bosch GmbH and       ////
+//// protected by patents. Anybody who wants to implement this    ////
+//// CAN IP core on silicon has to obtain a CAN protocol license  ////
+//// from Bosch.                                                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: can_btl.v,v $
+// Revision 1.30  2004/10/27 18:51:37  igorm
+// Fixed synchronization problem in real hardware when 0xf is used for TSEG1.
+//
+// Revision 1.29  2004/05/12 15:58:41  igorm
+// Core improved to pass all tests with the Bosch VHDL Reference system.
+//
+// Revision 1.28  2004/02/08 14:25:26  mohor
+// Header changed.
+//
+// Revision 1.27  2003/09/30 00:55:13  mohor
+// Error counters fixed to be compatible with Bosch VHDL reference model.
+// Small synchronization changes.
+//
+// Revision 1.26  2003/09/25 18:55:49  mohor
+// Synchronization changed, error counters fixed.
+//
+// Revision 1.25  2003/07/16 13:40:35  mohor
+// Fixed according to the linter.
+//
+// Revision 1.24  2003/07/10 15:32:28  mohor
+// Unused signal removed.
+//
+// Revision 1.23  2003/07/10 01:59:04  tadejm
+// Synchronization fixed. In some strange cases it didn't work according to
+// the VHDL reference model.
+//
+// Revision 1.22  2003/07/07 11:21:37  mohor
+// Little fixes (to fix warnings).
+//
+// Revision 1.21  2003/07/03 09:32:20  mohor
+// Synchronization changed.
+//
+// Revision 1.20  2003/06/20 14:51:11  mohor
+// Previous change removed. When resynchronization occurs we go to seg1
+// stage. sync stage does not cause another start of seg1 stage.
+//
+// Revision 1.19  2003/06/20 14:28:20  mohor
+// When hard_sync or resync occure we need to go to seg1 segment. Going to
+// sync segment is in that case blocked.
+//
+// Revision 1.18  2003/06/17 15:53:33  mohor
+// clk_cnt reduced from [8:0] to [6:0].
+//
+// Revision 1.17  2003/06/17 14:32:17  mohor
+// Removed few signals.
+//
+// Revision 1.16  2003/06/16 13:57:58  mohor
+// tx_point generated one clk earlier. rx_i registered. Data corrected when
+// using extended mode.
+//
+// Revision 1.15  2003/06/13 15:02:24  mohor
+// Synchronization is also needed when transmitting a message.
+//
+// Revision 1.14  2003/06/13 14:55:11  mohor
+// Counters width changed.
+//
+// Revision 1.13  2003/06/11 14:21:35  mohor
+// When switching to tx, sync stage is overjumped.
+//
+// Revision 1.12  2003/02/14 20:17:01  mohor
+// Several registers added. Not finished, yet.
+//
+// Revision 1.11  2003/02/09 18:40:29  mohor
+// Overload fixed. Hard synchronization also enabled at the last bit of
+// interframe.
+//
+// Revision 1.10  2003/02/09 02:24:33  mohor
+// Bosch license warning added. Error counters finished. Overload frames
+// still need to be fixed.
+//
+// Revision 1.9  2003/01/31 01:13:38  mohor
+// backup.
+//
+// Revision 1.8  2003/01/10 17:51:34  mohor
+// Temporary version (backup).
+//
+// Revision 1.7  2003/01/08 02:10:53  mohor
+// Acceptance filter added.
+//
+// Revision 1.6  2002/12/28 04:13:23  mohor
+// Backup version.
+//
+// Revision 1.5  2002/12/27 00:12:52  mohor
+// Header changed, testbench improved to send a frame (crc still missing).
+//
+// Revision 1.4  2002/12/26 01:33:05  mohor
+// Tripple sampling supported.
+//
+// Revision 1.3  2002/12/25 23:44:16  mohor
+// Commented lines removed.
+//
+// Revision 1.2  2002/12/25 14:17:00  mohor
+// Synchronization working.
+//
+// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
+// Initial
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "can_defines.v"
+
+module can_btl
+( 
+  clk,
+  rst,
+  rx,
+  tx,
+
+  /* Bus Timing 0 register */
+  baud_r_presc,
+  sync_jump_width,
+
+  /* Bus Timing 1 register */
+  time_segment1,
+  time_segment2,
+  triple_sampling,
+
+  /* Output signals from this module */
+  sample_point,
+  sampled_bit,
+  sampled_bit_q,
+  tx_point,
+  hard_sync,
+  
+  /* Output from can_bsp module */
+  rx_idle,
+  rx_inter,
+  transmitting,
+  transmitter,
+  go_rx_inter,
+  tx_next,
+
+  go_overload_frame,
+  go_error_frame,
+  go_tx,
+  send_ack,
+  node_error_passive
+);
+
+parameter Tp = 1;
+
+input         clk;
+input         rst;
+input         rx;
+input         tx;
+
+
+/* Bus Timing 0 register */
+input   [5:0] baud_r_presc;
+input   [1:0] sync_jump_width;
+
+/* Bus Timing 1 register */
+input   [3:0] time_segment1;
+input   [2:0] time_segment2;
+input         triple_sampling;
+
+/* Output from can_bsp module */
+input         rx_idle;
+input         rx_inter;
+input         transmitting;
+input         transmitter;
+input         go_rx_inter;
+input         tx_next;
+
+input         go_overload_frame;
+input         go_error_frame;
+input         go_tx;
+input         send_ack;
+input         node_error_passive;
+
+/* Output signals from this module */
+output        sample_point;
+output        sampled_bit;
+output        sampled_bit_q;
+output        tx_point;
+output        hard_sync;
+
+reg     [6:0] clk_cnt;
+reg           clk_en;
+reg           clk_en_q;
+reg           sync_blocked;
+reg           hard_sync_blocked;
+reg           sampled_bit;
+reg           sampled_bit_q;
+reg     [4:0] quant_cnt;
+reg     [3:0] delay;
+reg           sync;
+reg           seg1;
+reg           seg2;
+reg           resync_latched;
+reg           sample_point;
+reg     [1:0] sample;
+reg           tx_point;
+reg           tx_next_sp;
+
+wire          go_sync;
+wire          go_seg1;
+wire          go_seg2;
+wire [7:0]    preset_cnt;
+wire          sync_window;
+wire          resync;
+
+
+assign preset_cnt = (baud_r_presc + 1'b1)<<1;        // (BRP+1)*2
+assign hard_sync  =   (rx_idle | rx_inter)    & (~rx) & sampled_bit & (~hard_sync_blocked);  // Hard synchronization
+assign resync     =  (~rx_idle) & (~rx_inter) & (~rx) & sampled_bit & (~sync_blocked);       // Re-synchronization
+
+
+
+/* Generating general enable signal that defines baud rate. */
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    clk_cnt <= 7'h0;
+  else if (clk_cnt >= (preset_cnt-1'b1))
+    clk_cnt <=#Tp 7'h0;
+  else
+    clk_cnt <=#Tp clk_cnt + 1'b1;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    clk_en  <= 1'b0;
+  else if ({1'b0, clk_cnt} == (preset_cnt-1'b1))
+    clk_en  <=#Tp 1'b1;
+  else
+    clk_en  <=#Tp 1'b0;
+end
+
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    clk_en_q  <= 1'b0;
+  else
+    clk_en_q  <=#Tp clk_en;
+end
+
+
+
+/* Changing states */
+assign go_sync = clk_en_q & seg2 & (quant_cnt[2:0] == time_segment2) & (~hard_sync) & (~resync);
+assign go_seg1 = clk_en_q & (sync | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
+assign go_seg2 = clk_en_q & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));
+
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    tx_point <= 1'b0;
+  else
+    tx_point <=#Tp ~tx_point & seg2 & (  clk_en & (quant_cnt[2:0] == time_segment2)
+                                       | (clk_en | clk_en_q) & (resync | hard_sync)
+                                      );    // When transmitter we should transmit as soon as possible.
+end
+
+
+
+/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
+   SJW is reached */
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    resync_latched <= 1'b0;
+  else if (resync & seg2 & (~sync_window))
+    resync_latched <=#Tp 1'b1;
+  else if (go_seg1)
+    resync_latched <= 1'b0;
+end
+
+
+
+/* Synchronization stage/segment */
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    sync <= 1'b0;
+  else if (clk_en_q)
+    sync <=#Tp go_sync;
+end
+
+
+/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    seg1 <= 1'b1;
+  else if (go_seg1)
+    seg1 <=#Tp 1'b1;
+  else if (go_seg2)
+    seg1 <=#Tp 1'b0;
+end
+
+
+/* Seg2 stage/segment */
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    seg2 <= 1'b0;
+  else if (go_seg2)
+    seg2 <=#Tp 1'b1;
+  else if (go_sync | go_seg1)
+    seg2 <=#Tp 1'b0;
+end
+
+
+/* Quant counter */
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    quant_cnt <= 5'h0;
+  else if (go_sync | go_seg1 | go_seg2)
+    quant_cnt <=#Tp 5'h0;
+  else if (clk_en_q)
+    quant_cnt <=#Tp quant_cnt + 1'b1;
+end
+
+
+/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    delay <= 4'h0;
+  else if (resync & seg1 & (~transmitting | transmitting & (tx_next_sp | (tx & (~rx)))))  // when transmitting 0 with positive error delay is set to 0
+    delay <=#Tp (quant_cnt > {3'h0, sync_jump_width})? ({2'h0, sync_jump_width} + 1'b1) : (quant_cnt + 1'b1);
+  else if (go_sync | go_seg1)
+    delay <=#Tp 4'h0;
+end
+
+
+// If early edge appears within this window (in seg2 stage), phase error is fully compensated
+assign sync_window = ((time_segment2 - quant_cnt[2:0]) < ( sync_jump_width + 1'b1));
+
+
+// Sampling data (memorizing two samples all the time).
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    sample <= 2'b11;
+  else if (clk_en_q)
+    sample <= {sample[0], rx};
+end
+
+
+// When enabled, tripple sampling is done here.
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    begin
+      sampled_bit <= 1'b1;
+      sampled_bit_q <= 1'b1;
+      sample_point <= 1'b0;
+    end
+  else if (go_error_frame)
+    begin
+      sampled_bit_q <=#Tp sampled_bit;
+      sample_point <=#Tp 1'b0;
+    end
+  else if (clk_en_q & (~hard_sync))
+    begin
+      if (seg1 & (quant_cnt == (time_segment1 + delay)))
+        begin
+          sample_point <=#Tp 1'b1;
+          sampled_bit_q <=#Tp sampled_bit;
+          if (triple_sampling)
+            sampled_bit <=#Tp (sample[0] & sample[1]) | ( sample[0] & rx) | (sample[1] & rx);
+          else
+            sampled_bit <=#Tp rx;
+        end
+    end
+  else
+    sample_point <=#Tp 1'b0;
+end
+
+
+// tx_next_sp shows next value that will be driven on the TX. When driving 1 and receiving 0 we
+// need to synchronize (even when we are a transmitter)
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    tx_next_sp <= 1'b0;
+  else if (go_overload_frame | (go_error_frame & (~node_error_passive)) | go_tx | send_ack)
+    tx_next_sp <=#Tp 1'b0;
+  else if (go_error_frame & node_error_passive)
+    tx_next_sp <=#Tp 1'b1;
+  else if (sample_point)
+    tx_next_sp <=#Tp tx_next;
+end
+
+
+
+/* Blocking synchronization (can occur only once in a bit time) */
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    sync_blocked <=#Tp 1'b1;
+  else if (clk_en_q)
+    begin
+      if (resync)
+        sync_blocked <=#Tp 1'b1;
+      else if (go_seg2)
+        sync_blocked <=#Tp 1'b0;
+    end
+end
+
+
+/* Blocking hard synchronization when occurs once or when we are transmitting a msg */
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    hard_sync_blocked <=#Tp 1'b0;
+  else if (hard_sync & clk_en_q | (transmitting & transmitter | go_tx) & tx_point & (~tx_next))
+    hard_sync_blocked <=#Tp 1'b1;
+  else if (go_rx_inter | (rx_idle | rx_inter) & sample_point & sampled_bit)  // When a glitch performed synchronization
+    hard_sync_blocked <=#Tp 1'b0;
+end
+
+
+
+
+
+endmodule
+
Index: /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_crc.v
===================================================================
--- /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_crc.v	(revision 295)
+++ /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_crc.v	(revision 295)
@@ -0,0 +1,113 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  can_crc.v                                                   ////
+////                                                              ////
+////                                                              ////
+////  This file is part of the CAN Protocol Controller            ////
+////  http://www.opencores.org/projects/can/                      ////
+////                                                              ////
+////                                                              ////
+////  Author(s):                                                  ////
+////       Igor Mohor                                             ////
+////       igorm@opencores.org                                    ////
+////                                                              ////
+////                                                              ////
+////  All additional information is available in the README.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002, 2003, 2004 Authors                       ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//// The CAN protocol is developed by Robert Bosch GmbH and       ////
+//// protected by patents. Anybody who wants to implement this    ////
+//// CAN IP core on silicon has to obtain a CAN protocol license  ////
+//// from Bosch.                                                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: can_crc.v,v $
+// Revision 1.5  2004/02/08 14:25:57  mohor
+// Header changed.
+//
+// Revision 1.4  2003/07/16 13:16:51  mohor
+// Fixed according to the linter.
+//
+// Revision 1.3  2003/02/10 16:02:11  mohor
+// CAN is working according to the specification. WB interface and more
+// registers (status, IRQ, ...) needs to be added.
+//
+// Revision 1.2  2003/02/09 02:24:33  mohor
+// Bosch license warning added. Error counters finished. Overload frames
+// still need to be fixed.
+//
+// Revision 1.1  2003/01/08 02:10:54  mohor
+// Acceptance filter added.
+//
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+
+module can_crc (clk, data, enable, initialize, crc);
+
+
+parameter Tp = 1;
+
+input         clk;
+input         data;
+input         enable;
+input         initialize;
+
+output [14:0] crc;
+
+reg    [14:0] crc;
+
+wire          crc_next;
+wire   [14:0] crc_tmp;
+
+
+assign crc_next = data ^ crc[14];
+assign crc_tmp = {crc[13:0], 1'b0};
+
+always @ (posedge clk)
+begin
+  if(initialize)
+    crc <= #Tp 15'h0;
+  else if (enable)
+    begin
+      if (crc_next)
+        crc <= #Tp crc_tmp ^ 15'h4599;
+      else
+        crc <= #Tp crc_tmp;
+    end    
+end
+
+
+endmodule
Index: /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_defines.v
===================================================================
--- /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_defines.v	(revision 295)
+++ /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_defines.v	(revision 295)
@@ -0,0 +1,124 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  can_defines.v                                               ////
+////                                                              ////
+////                                                              ////
+////  This file is part of the CAN Protocol Controller            ////
+////  http://www.opencores.org/projects/can/                      ////
+////                                                              ////
+////                                                              ////
+////  Author(s):                                                  ////
+////       Igor Mohor                                             ////
+////       igorm@opencores.org                                    ////
+////                                                              ////
+////                                                              ////
+////  All additional information is available in the README.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002, 2003, 2004 Authors                       ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//// The CAN protocol is developed by Robert Bosch GmbH and       ////
+//// protected by patents. Anybody who wants to implement this    ////
+//// CAN IP core on silicon has to obtain a CAN protocol license  ////
+//// from Bosch.                                                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: can_defines.v,v $
+// Revision 1.14  2004/05/12 15:58:41  igorm
+// Core improved to pass all tests with the Bosch VHDL Reference system.
+//
+// Revision 1.13  2004/02/08 14:28:03  mohor
+// Header changed.
+//
+// Revision 1.12  2003/10/17 05:55:20  markom
+// mbist signals updated according to newest convention
+//
+// Revision 1.11  2003/09/05 12:46:42  mohor
+// ALTERA_RAM supported.
+//
+// Revision 1.10  2003/08/14 16:04:52  simons
+// Artisan ram instances added.
+//
+// Revision 1.9  2003/06/27 20:56:15  simons
+// Virtual silicon ram instances added.
+//
+// Revision 1.8  2003/06/09 11:32:36  mohor
+// Ports added for the CAN_BIST.
+//
+// Revision 1.7  2003/03/20 16:51:55  mohor
+// *** empty log message ***
+//
+// Revision 1.6  2003/03/12 04:19:13  mohor
+// 8051 interface added (besides WISHBONE interface). Selection is made in
+// can_defines.v file.
+//
+// Revision 1.5  2003/03/05 15:03:20  mohor
+// Xilinx RAM added.
+//
+// Revision 1.4  2003/03/01 22:52:47  mohor
+// Actel APA ram supported.
+//
+// Revision 1.3  2003/02/09 02:24:33  mohor
+// Bosch license warning added. Error counters finished. Overload frames
+// still need to be fixed.
+//
+// Revision 1.2  2002/12/27 00:12:52  mohor
+// Header changed, testbench improved to send a frame (crc still missing).
+//
+// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
+// Initial
+//
+//
+//
+
+
+// Uncomment following line if you want to use WISHBONE interface. Otherwise
+// 8051 interface is used.
+// `define   CAN_WISHBONE_IF
+`define   CAN_AVALON_IF
+
+// Uncomment following line if you want to use CAN in Actel APA devices (embedded memory used)
+// `define   ACTEL_APA_RAM
+
+// Uncomment following line if you want to use CAN in Altera devices (embedded memory used)
+//`define   ALTERA_RAM
+
+// Uncomment following line if you want to use CAN in Xilinx devices (embedded memory used)
+// `define   XILINX_RAM
+
+// Uncomment the line for the ram used in ASIC implementation
+// `define   VIRTUALSILICON_RAM
+// `define   ARTISAN_RAM
+
+// Uncomment the following line when RAM BIST is needed (ASIC implementation)
+//`define CAN_BIST                    // Bist (for ASIC implementation)
+
+/* width of MBIST control bus */
+//`define CAN_MBIST_CTRL_WIDTH 3
+
Index: /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_fifo.v
===================================================================
--- /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_fifo.v	(revision 295)
+++ /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_fifo.v	(revision 295)
@@ -0,0 +1,716 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  can_fifo.v                                                  ////
+////                                                              ////
+////                                                              ////
+////  This file is part of the CAN Protocol Controller            ////
+////  http://www.opencores.org/projects/can/                      ////
+////                                                              ////
+////                                                              ////
+////  Author(s):                                                  ////
+////       Igor Mohor                                             ////
+////       igorm@opencores.org                                    ////
+////                                                              ////
+////                                                              ////
+////  All additional information is available in the README.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002, 2003, 2004 Authors                       ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//// The CAN protocol is developed by Robert Bosch GmbH and       ////
+//// protected by patents. Anybody who wants to implement this    ////
+//// CAN IP core on silicon has to obtain a CAN protocol license  ////
+//// from Bosch.                                                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: can_fifo.v,v $
+// Revision 1.27  2004/11/18 12:39:34  igorm
+// Fixes for compatibility after the SW reset.
+//
+// Revision 1.26  2004/02/08 14:30:57  mohor
+// Header changed.
+//
+// Revision 1.25  2003/10/23 16:52:17  mohor
+// Active high/low problem when Altera devices are used. Bug fixed by
+// Rojhalat Ibrahim.
+//
+// Revision 1.24  2003/10/17 05:55:20  markom
+// mbist signals updated according to newest convention
+//
+// Revision 1.23  2003/09/05 12:46:41  mohor
+// ALTERA_RAM supported.
+//
+// Revision 1.22  2003/08/20 09:59:16  mohor
+// Artisan RAM fixed (when not using BIST).
+//
+// Revision 1.21  2003/08/14 16:04:52  simons
+// Artisan ram instances added.
+//
+// Revision 1.20  2003/07/16 14:00:45  mohor
+// Fixed according to the linter.
+//
+// Revision 1.19  2003/07/03 09:30:44  mohor
+// PCI_BIST replaced with CAN_BIST.
+//
+// Revision 1.18  2003/06/27 22:14:23  simons
+// Overrun fifo implemented with FFs, because it is not possible to create such a memory.
+//
+// Revision 1.17  2003/06/27 20:56:15  simons
+// Virtual silicon ram instances added.
+//
+// Revision 1.16  2003/06/18 23:03:44  mohor
+// Typo fixed.
+//
+// Revision 1.15  2003/06/11 09:37:05  mohor
+// overrun and length_info fifos are initialized at the end of reset.
+//
+// Revision 1.14  2003/03/05 15:02:30  mohor
+// Xilinx RAM added.
+//
+// Revision 1.13  2003/03/01 22:53:33  mohor
+// Actel APA ram supported.
+//
+// Revision 1.12  2003/02/19 14:44:03  mohor
+// CAN core finished. Host interface added. Registers finished.
+// Synchronization to the wishbone finished.
+//
+// Revision 1.11  2003/02/14 20:17:01  mohor
+// Several registers added. Not finished, yet.
+//
+// Revision 1.10  2003/02/11 00:56:06  mohor
+// Wishbone interface added.
+//
+// Revision 1.9  2003/02/09 02:24:33  mohor
+// Bosch license warning added. Error counters finished. Overload frames
+// still need to be fixed.
+//
+// Revision 1.8  2003/01/31 01:13:38  mohor
+// backup.
+//
+// Revision 1.7  2003/01/17 17:44:31  mohor
+// Fifo corrected to be synthesizable.
+//
+// Revision 1.6  2003/01/15 13:16:47  mohor
+// When a frame with "remote request" is received, no data is stored
+// to fifo, just the frame information (identifier, ...). Data length
+// that is stored is the received data length and not the actual data
+// length that is stored to fifo.
+//
+// Revision 1.5  2003/01/14 17:25:09  mohor
+// Addresses corrected to decimal values (previously hex).
+//
+// Revision 1.4  2003/01/14 12:19:35  mohor
+// rx_fifo is now working.
+//
+// Revision 1.3  2003/01/09 21:54:45  mohor
+// rx fifo added. Not 100 % verified, yet.
+//
+// Revision 1.2  2003/01/09 14:46:58  mohor
+// Temporary files (backup).
+//
+// Revision 1.1  2003/01/08 02:10:55  mohor
+// Acceptance filter added.
+//
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "can_defines.v"
+
+module can_fifo
+( 
+  clk,
+  rst,
+
+  wr,
+
+  data_in,
+  addr,
+  data_out,
+  fifo_selected,
+
+  reset_mode,
+  release_buffer,
+  extended_mode,
+  overrun,
+  info_empty,
+  info_cnt
+
+`ifdef CAN_BIST
+  ,
+  mbist_si_i,
+  mbist_so_o,
+  mbist_ctrl_i
+`endif
+);
+
+parameter Tp = 1;
+
+input         clk;
+input         rst;
+input         wr;
+input   [7:0] data_in;
+input   [5:0] addr;
+input         reset_mode;
+input         release_buffer;
+input         extended_mode;
+input         fifo_selected;
+
+output  [7:0] data_out;
+output        overrun;
+output        info_empty;
+output  [6:0] info_cnt;
+
+`ifdef CAN_BIST
+input         mbist_si_i;
+output        mbist_so_o;
+input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
+wire          mbist_s_0;
+`endif
+
+`ifdef ALTERA_RAM
+`else
+`ifdef ACTEL_APA_RAM
+`else
+`ifdef XILINX_RAM
+`else
+`ifdef ARTISAN_RAM
+  reg           overrun_info[0:63];
+`else
+`ifdef VIRTUALSILICON_RAM
+  reg           overrun_info[0:63];
+`else
+  reg     [7:0] fifo [0:63];
+  reg     [3:0] length_fifo[0:63];
+  reg           overrun_info[0:63];
+`endif
+`endif
+`endif
+`endif
+`endif
+
+reg     [5:0] rd_pointer;
+reg     [5:0] wr_pointer;
+reg     [5:0] read_address;
+reg     [5:0] wr_info_pointer;
+reg     [5:0] rd_info_pointer;
+reg           wr_q;
+reg     [3:0] len_cnt;
+reg     [6:0] fifo_cnt;
+reg     [6:0] info_cnt;
+reg           latch_overrun;
+reg           initialize_memories;
+
+wire    [3:0] length_info;
+wire          write_length_info;
+wire          fifo_empty;
+wire          fifo_full;
+wire          info_full;
+
+assign write_length_info = (~wr) & wr_q;
+
+// Delayed write signal
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    wr_q <=#Tp 1'b0;
+  else if (reset_mode)
+    wr_q <=#Tp 1'b0;
+  else
+    wr_q <=#Tp wr;
+end
+
+
+// length counter
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    len_cnt <= 4'h0;
+  else if (reset_mode | write_length_info)
+    len_cnt <=#Tp 4'h0;
+  else if (wr & (~fifo_full))
+    len_cnt <=#Tp len_cnt + 1'b1;
+end
+
+
+// wr_info_pointer
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    wr_info_pointer <= 6'h0;
+  else if (write_length_info & (~info_full) | initialize_memories)
+    wr_info_pointer <=#Tp wr_info_pointer + 1'b1;
+  else if (reset_mode)
+    wr_info_pointer <=#Tp rd_info_pointer;
+end
+
+
+
+// rd_info_pointer
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    rd_info_pointer <= 6'h0;
+  else if (release_buffer & (~fifo_empty))
+    rd_info_pointer <=#Tp rd_info_pointer + 1'b1;
+end
+
+
+// rd_pointer
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    rd_pointer <= 5'h0;
+  else if (release_buffer & (~fifo_empty))
+    rd_pointer <=#Tp rd_pointer + {2'h0, length_info};
+end
+
+
+// wr_pointer
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    wr_pointer <= 5'h0;
+  else if (reset_mode)
+    wr_pointer <=#Tp rd_pointer;
+  else if (wr & (~fifo_full))
+    wr_pointer <=#Tp wr_pointer + 1'b1;
+end
+
+
+// latch_overrun
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    latch_overrun <= 1'b0;
+  else if (reset_mode | write_length_info)
+    latch_overrun <=#Tp 1'b0;
+  else if (wr & fifo_full)
+    latch_overrun <=#Tp 1'b1;
+end
+
+
+// Counting data in fifo
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    fifo_cnt <= 7'h0;
+  else if (reset_mode)
+    fifo_cnt <=#Tp 7'h0;
+  else if (wr & (~release_buffer) & (~fifo_full))
+    fifo_cnt <=#Tp fifo_cnt + 1'b1;
+  else if ((~wr) & release_buffer & (~fifo_empty))
+    fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info};
+  else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))
+    fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info} + 1'b1;
+end
+
+assign fifo_full = fifo_cnt == 7'd64;
+assign fifo_empty = fifo_cnt == 7'd0;
+
+
+// Counting data in length_fifo and overrun_info fifo
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    info_cnt <=#Tp 7'h0;
+  else if (reset_mode)
+    info_cnt <=#Tp 7'h0;
+  else if (write_length_info ^ release_buffer)
+    begin
+      if (release_buffer & (~info_empty))
+        info_cnt <=#Tp info_cnt - 1'b1;
+      else if (write_length_info & (~info_full))
+        info_cnt <=#Tp info_cnt + 1'b1;
+    end
+end
+        
+assign info_full = info_cnt == 7'd64;
+assign info_empty = info_cnt == 7'd0;
+
+
+// Selecting which address will be used for reading data from rx fifo
+always @ (extended_mode or rd_pointer or addr)
+begin
+  if (extended_mode)      // extended mode
+    read_address = rd_pointer + (addr - 6'd16);
+  else                    // normal mode
+    read_address = rd_pointer + (addr - 6'd20);
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    initialize_memories <= 1'b1;
+  else if (&wr_info_pointer)
+    initialize_memories <=#Tp 1'b0;
+end
+
+
+`ifdef ALTERA_RAM
+//  altera_ram_64x8_sync fifo
+  lpm_ram_dp fifo
+  (
+    .q         (data_out),
+    .rdclock   (clk),
+    .wrclock   (clk),
+    .data      (data_in),
+    .wren      (wr & (~fifo_full)),
+    .rden      (fifo_selected),
+    .wraddress (wr_pointer),
+    .rdaddress (read_address)
+  );
+  defparam fifo.lpm_width = 8;
+  defparam fifo.lpm_widthad = 6;
+  defparam fifo.lpm_numwords = 64;
+
+
+//  altera_ram_64x4_sync info_fifo
+  lpm_ram_dp info_fifo
+  (
+    .q         (length_info),
+    .rdclock   (clk),
+    .wrclock   (clk),
+    .data      (len_cnt & {4{~initialize_memories}}),
+    .wren      (write_length_info & (~info_full) | initialize_memories),
+    .wraddress (wr_info_pointer),
+    .rdaddress (rd_info_pointer)
+  );
+  defparam info_fifo.lpm_width = 4;
+  defparam info_fifo.lpm_widthad = 6;
+  defparam info_fifo.lpm_numwords = 64;
+
+
+//  altera_ram_64x1_sync overrun_fifo
+  lpm_ram_dp overrun_fifo
+  (
+    .q         (overrun),
+    .rdclock   (clk),
+    .wrclock   (clk),
+    .data      ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
+    .wren      (write_length_info & (~info_full) | initialize_memories),
+    .wraddress (wr_info_pointer),
+    .rdaddress (rd_info_pointer)
+  );
+  defparam overrun_fifo.lpm_width = 1;
+  defparam overrun_fifo.lpm_widthad = 6;
+  defparam overrun_fifo.lpm_numwords = 64;
+
+`else
+`ifdef ACTEL_APA_RAM
+  actel_ram_64x8_sync fifo
+  (
+    .DO      (data_out),
+    .RCLOCK  (clk),
+    .WCLOCK  (clk),
+    .DI      (data_in),
+    .PO      (),                       // parity not used
+    .WRB     (~(wr & (~fifo_full))),
+    .RDB     (~fifo_selected),
+    .WADDR   (wr_pointer),
+    .RADDR   (read_address)
+  );
+
+
+  actel_ram_64x4_sync info_fifo
+  (
+    .DO      (length_info),
+    .RCLOCK  (clk),
+    .WCLOCK  (clk),
+    .DI      (len_cnt & {4{~initialize_memories}}),
+    .PO      (),                       // parity not used
+    .WRB     (~(write_length_info & (~info_full) | initialize_memories)),
+    .RDB     (1'b0),                   // always enabled
+    .WADDR   (wr_info_pointer),
+    .RADDR   (rd_info_pointer)
+  );
+
+
+  actel_ram_64x1_sync overrun_fifo
+  (
+    .DO      (overrun),
+    .RCLOCK  (clk),
+    .WCLOCK  (clk),
+    .DI      ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
+    .PO      (),                       // parity not used
+    .WRB     (~(write_length_info & (~info_full) | initialize_memories)),
+    .RDB     (1'b0),                   // always enabled
+    .WADDR   (wr_info_pointer),
+    .RADDR   (rd_info_pointer)
+  );
+`else
+`ifdef XILINX_RAM
+
+  RAMB4_S8_S8 fifo
+  (
+    .DOA(),
+    .DOB(data_out),
+    .ADDRA({3'h0, wr_pointer}),
+    .CLKA(clk),
+    .DIA(data_in),
+    .ENA(1'b1),
+    .RSTA(1'b0),
+    .WEA(wr & (~fifo_full)),
+    .ADDRB({3'h0, read_address}),
+    .CLKB(clk),
+    .DIB(8'h0),
+    .ENB(1'b1),
+    .RSTB(1'b0),
+    .WEB(1'b0)
+  );
+
+
+  RAMB4_S4_S4 info_fifo
+  (
+    .DOA(),
+    .DOB(length_info),
+    .ADDRA({4'h0, wr_info_pointer}),
+    .CLKA(clk),
+    .DIA(len_cnt & {4{~initialize_memories}}),
+    .ENA(1'b1),
+    .RSTA(1'b0),
+    .WEA(write_length_info & (~info_full) | initialize_memories),
+    .ADDRB({4'h0, rd_info_pointer}),
+    .CLKB(clk),
+    .DIB(4'h0),
+    .ENB(1'b1),
+    .RSTB(1'b0),
+    .WEB(1'b0)
+  );
+
+
+  RAMB4_S1_S1 overrun_fifo
+  (
+    .DOA(),
+    .DOB(overrun),
+    .ADDRA({6'h0, wr_info_pointer}),
+    .CLKA(clk),
+    .DIA((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
+    .ENA(1'b1),
+    .RSTA(1'b0),
+    .WEA(write_length_info & (~info_full) | initialize_memories),
+    .ADDRB({6'h0, rd_info_pointer}),
+    .CLKB(clk),
+    .DIB(1'h0),
+    .ENB(1'b1),
+    .RSTB(1'b0),
+    .WEB(1'b0)
+  );
+
+
+`else
+`ifdef VIRTUALSILICON_RAM
+
+`ifdef CAN_BIST
+    vs_hdtp_64x8_bist fifo
+`else
+    vs_hdtp_64x8 fifo
+`endif
+    (
+        .RCK        (clk),
+        .WCK        (clk),
+        .RADR       (read_address),
+        .WADR       (wr_pointer),
+        .DI         (data_in),
+        .DOUT       (data_out),
+        .REN        (~fifo_selected),
+        .WEN        (~(wr & (~fifo_full)))
+    `ifdef CAN_BIST
+        ,
+        // debug chain signals
+        .mbist_si_i   (mbist_si_i),
+        .mbist_so_o   (mbist_s_0),
+        .mbist_ctrl_i   (mbist_ctrl_i)
+    `endif
+    );
+
+`ifdef CAN_BIST
+    vs_hdtp_64x4_bist info_fifo
+`else
+    vs_hdtp_64x4 info_fifo
+`endif
+    (
+        .RCK        (clk),
+        .WCK        (clk),
+        .RADR       (rd_info_pointer),
+        .WADR       (wr_info_pointer),
+        .DI         (len_cnt & {4{~initialize_memories}}),
+        .DOUT       (length_info),
+        .REN        (1'b0),
+        .WEN        (~(write_length_info & (~info_full) | initialize_memories))
+    `ifdef CAN_BIST
+        ,
+        // debug chain signals
+        .mbist_si_i   (mbist_s_0),
+        .mbist_so_o   (mbist_so_o),
+        .mbist_ctrl_i   (mbist_ctrl_i)
+    `endif
+    );
+
+    // overrun_info
+    always @ (posedge clk)
+    begin
+      if (write_length_info & (~info_full) | initialize_memories)
+        overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
+    end
+    
+    
+    // reading overrun
+    assign overrun = overrun_info[rd_info_pointer];
+
+`else
+`ifdef ARTISAN_RAM
+
+`ifdef CAN_BIST
+    art_hstp_64x8_bist fifo
+    (
+        .CLKR       (clk),
+        .CLKW       (clk),
+        .AR         (read_address),
+        .AW         (wr_pointer),
+        .D          (data_in),
+        .Q          (data_out),
+        .REN        (~fifo_selected),
+        .WEN        (~(wr & (~fifo_full))),
+        .mbist_si_i   (mbist_si_i),
+        .mbist_so_o   (mbist_s_0),
+        .mbist_ctrl_i   (mbist_ctrl_i)
+    );
+    art_hstp_64x4_bist info_fifo
+    (
+        .CLKR       (clk),
+        .CLKW       (clk),
+        .AR         (rd_info_pointer),
+        .AW         (wr_info_pointer),
+        .D          (len_cnt & {4{~initialize_memories}}),
+        .Q          (length_info),
+        .REN        (1'b0),
+        .WEN        (~(write_length_info & (~info_full) | initialize_memories)),
+        .mbist_si_i   (mbist_s_0),
+        .mbist_so_o   (mbist_so_o),
+        .mbist_ctrl_i   (mbist_ctrl_i)
+    );
+`else
+    art_hsdp_64x8 fifo
+    (
+        .CENA       (1'b0),
+        .CENB       (1'b0),
+        .CLKA       (clk),
+        .CLKB       (clk),
+        .AA         (read_address),
+        .AB         (wr_pointer),
+        .DA         (8'h00),
+        .DB         (data_in),
+        .QA         (data_out),
+        .QB         (),
+        .OENA       (~fifo_selected),
+        .OENB       (1'b1),
+        .WENA       (1'b1),
+        .WENB       (~(wr & (~fifo_full)))
+    );
+    art_hsdp_64x4 info_fifo
+    (
+        .CENA       (1'b0),
+        .CENB       (1'b0),
+        .CLKA       (clk),
+        .CLKB       (clk),
+        .AA         (rd_info_pointer),
+        .AB         (wr_info_pointer),
+        .DA         (4'h0),
+        .DB         (len_cnt & {4{~initialize_memories}}),
+        .QA         (length_info),
+        .QB         (),
+        .OENA       (1'b0),
+        .OENB       (1'b1),
+        .WENA       (1'b1),
+        .WENB       (~(write_length_info & (~info_full) | initialize_memories))
+    );
+`endif
+
+    // overrun_info
+    always @ (posedge clk)
+    begin
+      if (write_length_info & (~info_full) | initialize_memories)
+        overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
+    end
+    
+    
+    // reading overrun
+    assign overrun = overrun_info[rd_info_pointer];
+
+`else
+  // writing data to fifo
+  always @ (posedge clk)
+  begin
+    if (wr & (~fifo_full))
+      fifo[wr_pointer] <=#Tp data_in;
+  end
+
+  // reading from fifo
+  assign data_out = fifo[read_address];
+
+
+  // writing length_fifo
+  always @ (posedge clk)
+  begin
+    if (write_length_info & (~info_full) | initialize_memories)
+      length_fifo[wr_info_pointer] <=#Tp len_cnt & {4{~initialize_memories}};
+  end
+
+
+  // reading length_fifo
+  assign length_info = length_fifo[rd_info_pointer];
+
+  // overrun_info
+  always @ (posedge clk)
+  begin
+    if (write_length_info & (~info_full) | initialize_memories)
+      overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
+  end
+  
+  
+  // reading overrun
+  assign overrun = overrun_info[rd_info_pointer];
+
+
+`endif
+`endif
+`endif
+`endif
+`endif
+
+
+
+
+
+endmodule
Index: /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_ibo.v
===================================================================
--- /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_ibo.v	(revision 295)
+++ /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_ibo.v	(revision 295)
@@ -0,0 +1,87 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  can_ibo.v                                                   ////
+////                                                              ////
+////                                                              ////
+////  This file is part of the CAN Protocol Controller            ////
+////  http://www.opencores.org/projects/can/                      ////
+////                                                              ////
+////                                                              ////
+////  Author(s):                                                  ////
+////       Igor Mohor                                             ////
+////       igorm@opencores.org                                    ////
+////                                                              ////
+////                                                              ////
+////  All additional information is available in the README.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002, 2003, 2004 Authors                       ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//// The CAN protocol is developed by Robert Bosch GmbH and       ////
+//// protected by patents. Anybody who wants to implement this    ////
+//// CAN IP core on silicon has to obtain a CAN protocol license  ////
+//// from Bosch.                                                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: can_ibo.v,v $
+// Revision 1.3  2004/02/08 14:31:44  mohor
+// Header changed.
+//
+// Revision 1.2  2003/02/09 02:24:33  mohor
+// Bosch license warning added. Error counters finished. Overload frames
+// still need to be fixed.
+//
+// Revision 1.1  2003/02/04 14:34:52  mohor
+// *** empty log message ***
+//
+//
+//
+//
+
+
+// This module only inverts bit order
+module can_ibo
+( 
+  di,
+  do
+);
+
+input   [7:0] di;
+output  [7:0] do;
+
+assign do[0] = di[7];
+assign do[1] = di[6];
+assign do[2] = di[5];
+assign do[3] = di[4];
+assign do[4] = di[3];
+assign do[5] = di[2];
+assign do[6] = di[1];
+assign do[7] = di[0];
+
+endmodule
Index: /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_register.v
===================================================================
--- /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_register.v	(revision 295)
+++ /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_register.v	(revision 295)
@@ -0,0 +1,106 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  can_register.v                                              ////
+////                                                              ////
+////                                                              ////
+////  This file is part of the CAN Protocol Controller            ////
+////  http://www.opencores.org/projects/can/                      ////
+////                                                              ////
+////                                                              ////
+////  Author(s):                                                  ////
+////       Igor Mohor                                             ////
+////       igorm@opencores.org                                    ////
+////                                                              ////
+////                                                              ////
+////  All additional information is available in the README.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002, 2003, 2004 Authors                       ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//// The CAN protocol is developed by Robert Bosch GmbH and       ////
+//// protected by patents. Anybody who wants to implement this    ////
+//// CAN IP core on silicon has to obtain a CAN protocol license  ////
+//// from Bosch.                                                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: can_register.v,v $
+// Revision 1.7  2004/02/08 14:32:31  mohor
+// Header changed.
+//
+// Revision 1.6  2003/03/20 16:58:50  mohor
+// unix.
+//
+// Revision 1.4  2003/03/11 16:32:34  mohor
+// timescale.v is used for simulation only.
+//
+// Revision 1.3  2003/02/09 02:24:33  mohor
+// Bosch license warning added. Error counters finished. Overload frames
+// still need to be fixed.
+//
+// Revision 1.2  2002/12/27 00:12:52  mohor
+// Header changed, testbench improved to send a frame (crc still missing).
+//
+// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
+// Initial
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+
+
+module can_register
+( data_in,
+  data_out,
+  we,
+  clk
+);
+
+parameter WIDTH = 8; // default parameter of the register width
+
+input [WIDTH-1:0] data_in;
+input             we;
+input             clk;
+
+output [WIDTH-1:0] data_out;
+reg    [WIDTH-1:0] data_out;
+
+
+
+always @ (posedge clk)
+begin
+  if (we)                        // write
+    data_out<=#1 data_in;
+end
+
+
+
+endmodule
Index: /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_register_asyn.v
===================================================================
--- /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_register_asyn.v	(revision 295)
+++ /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_register_asyn.v	(revision 295)
@@ -0,0 +1,111 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  can_register_asyn.v                                         ////
+////                                                              ////
+////                                                              ////
+////  This file is part of the CAN Protocol Controller            ////
+////  http://www.opencores.org/projects/can/                      ////
+////                                                              ////
+////                                                              ////
+////  Author(s):                                                  ////
+////       Igor Mohor                                             ////
+////       igorm@opencores.org                                    ////
+////                                                              ////
+////                                                              ////
+////  All additional information is available in the README.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002, 2003, 2004 Authors                       ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//// The CAN protocol is developed by Robert Bosch GmbH and       ////
+//// protected by patents. Anybody who wants to implement this    ////
+//// CAN IP core on silicon has to obtain a CAN protocol license  ////
+//// from Bosch.                                                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: can_register_asyn.v,v $
+// Revision 1.7  2004/02/08 14:33:19  mohor
+// Header changed.
+//
+// Revision 1.6  2003/03/20 16:58:50  mohor
+// unix.
+//
+// Revision 1.4  2003/03/11 16:32:34  mohor
+// timescale.v is used for simulation only.
+//
+// Revision 1.3  2003/02/09 02:24:33  mohor
+// Bosch license warning added. Error counters finished. Overload frames
+// still need to be fixed.
+//
+// Revision 1.2  2002/12/27 00:12:52  mohor
+// Header changed, testbench improved to send a frame (crc still missing).
+//
+// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
+// Initial
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+
+
+module can_register_asyn
+( data_in,
+  data_out,
+  we,
+  clk,
+  rst
+);
+
+parameter WIDTH = 8; // default parameter of the register width
+parameter RESET_VALUE = 8'h0;
+
+input [WIDTH-1:0] data_in;
+input             we;
+input             clk;
+input             rst;
+
+output [WIDTH-1:0] data_out;
+reg    [WIDTH-1:0] data_out;
+
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)                            // asynchronous reset
+    data_out<=#1 RESET_VALUE;
+  else if (we)                        // write
+    data_out<=#1 data_in;
+end
+
+
+
+endmodule
Index: /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_register_asyn_syn.v
===================================================================
--- /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_register_asyn_syn.v	(revision 295)
+++ /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_register_asyn_syn.v	(revision 295)
@@ -0,0 +1,115 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  can_register_asyn_syn.v                                     ////
+////                                                              ////
+////                                                              ////
+////  This file is part of the CAN Protocol Controller            ////
+////  http://www.opencores.org/projects/can/                      ////
+////                                                              ////
+////                                                              ////
+////  Author(s):                                                  ////
+////       Igor Mohor                                             ////
+////       igorm@opencores.org                                    ////
+////                                                              ////
+////                                                              ////
+////  All additional information is available in the README.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002, 2003, 2004 Authors                       ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//// The CAN protocol is developed by Robert Bosch GmbH and       ////
+//// protected by patents. Anybody who wants to implement this    ////
+//// CAN IP core on silicon has to obtain a CAN protocol license  ////
+//// from Bosch.                                                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: can_register_asyn_syn.v,v $
+// Revision 1.7  2004/02/08 14:33:59  mohor
+// Header changed.
+//
+// Revision 1.6  2003/03/20 16:52:43  mohor
+// unix.
+//
+// Revision 1.4  2003/03/11 16:32:34  mohor
+// timescale.v is used for simulation only.
+//
+// Revision 1.3  2003/02/09 02:24:33  mohor
+// Bosch license warning added. Error counters finished. Overload frames
+// still need to be fixed.
+//
+// Revision 1.2  2002/12/27 00:12:52  mohor
+// Header changed, testbench improved to send a frame (crc still missing).
+//
+// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
+// Initial
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+
+
+module can_register_asyn_syn
+( data_in,
+  data_out,
+  we,
+  clk,
+  rst,
+  rst_sync
+);
+
+parameter WIDTH = 8; // default parameter of the register width
+parameter RESET_VALUE =8'h0;
+
+input [WIDTH-1:0] data_in;
+input             we;
+input             clk;
+input             rst;
+input             rst_sync;
+
+output [WIDTH-1:0] data_out;
+reg    [WIDTH-1:0] data_out;
+
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if(rst)
+    data_out<=#1 RESET_VALUE;
+  else if (rst_sync)                  // synchronous reset
+    data_out<=#1 RESET_VALUE;
+  else if (we)                        // write
+    data_out<=#1 data_in;
+end
+
+
+
+endmodule
Index: /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_register_syn.v
===================================================================
--- /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_register_syn.v	(revision 295)
+++ /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_register_syn.v	(revision 295)
@@ -0,0 +1,108 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  can_register_syn.v                                          ////
+////                                                              ////
+////                                                              ////
+////  This file is part of the CAN Protocol Controller            ////
+////  http://www.opencores.org/projects/can/                      ////
+////                                                              ////
+////                                                              ////
+////  Author(s):                                                  ////
+////       Igor Mohor                                             ////
+////       igorm@opencores.org                                    ////
+////                                                              ////
+////                                                              ////
+////  All additional information is available in the README.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002, 2003, 2004 Authors                       ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//// The CAN protocol is developed by Robert Bosch GmbH and       ////
+//// protected by patents. Anybody who wants to implement this    ////
+//// CAN IP core on silicon has to obtain a CAN protocol license  ////
+//// from Bosch.                                                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: can_register_syn.v,v $
+// Revision 1.5  2004/02/08 14:34:40  mohor
+// Header changed.
+//
+// Revision 1.4  2003/03/11 16:31:58  mohor
+// timescale.v is used for simulation only.
+//
+// Revision 1.3  2003/02/09 02:24:33  mohor
+// Bosch license warning added. Error counters finished. Overload frames
+// still need to be fixed.
+//
+// Revision 1.2  2002/12/27 00:12:52  mohor
+// Header changed, testbench improved to send a frame (crc still missing).
+//
+// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
+// Initial
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+
+
+module can_register_syn
+( data_in,
+  data_out,
+  we,
+  clk,
+  rst_sync
+);
+
+parameter WIDTH = 8; // default parameter of the register width
+parameter RESET_VALUE = 0;
+
+input [WIDTH-1:0] data_in;
+input             we;
+input             clk;
+input             rst_sync;
+
+output [WIDTH-1:0] data_out;
+reg    [WIDTH-1:0] data_out;
+
+
+
+always @ (posedge clk)
+begin
+  if (rst_sync)                       // synchronous reset
+    data_out<=#1 RESET_VALUE;
+  else if (we)                        // write
+    data_out<=#1 data_in;
+end
+
+
+
+endmodule
Index: /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_registers.v
===================================================================
--- /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_registers.v	(revision 295)
+++ /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_registers.v	(revision 295)
@@ -0,0 +1,1807 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  can_registers.v                                             ////
+////                                                              ////
+////                                                              ////
+////  This file is part of the CAN Protocol Controller            ////
+////  http://www.opencores.org/projects/can/                      ////
+////                                                              ////
+////                                                              ////
+////  Author(s):                                                  ////
+////       Igor Mohor                                             ////
+////       igorm@opencores.org                                    ////
+////                                                              ////
+////                                                              ////
+////  All additional information is available in the README.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002, 2003 Authors                             ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//// The CAN protocol is developed by Robert Bosch GmbH and       ////
+//// protected by patents. Anybody who wants to implement this    ////
+//// CAN IP core on silicon has to obtain a CAN protocol license  ////
+//// from Bosch.                                                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: can_registers.v,v $
+// Revision 1.35  2004/11/30 15:08:26  igorm
+// irq is cleared after the release_buffer command. This bug was entered with
+// changes for the edge triggered interrupts.
+//
+// Revision 1.34  2004/11/18 12:39:43  igorm
+// Fixes for compatibility after the SW reset.
+//
+// Revision 1.33  2004/10/25 11:44:38  igorm
+// Interrupt is always cleared for one clock after the irq register is read.
+// This fixes problems when CPU is using IRQs that are edge triggered.
+//
+// Revision 1.32  2004/05/12 15:58:41  igorm
+// Core improved to pass all tests with the Bosch VHDL Reference system.
+//
+// Revision 1.31  2003/09/25 18:55:49  mohor
+// Synchronization changed, error counters fixed.
+//
+// Revision 1.30  2003/07/16 15:19:34  mohor
+// Fixed according to the linter.
+// Case statement for data_out joined.
+//
+// Revision 1.29  2003/07/10 01:59:04  tadejm
+// Synchronization fixed. In some strange cases it didn't work according to
+// the VHDL reference model.
+//
+// Revision 1.28  2003/07/07 11:21:37  mohor
+// Little fixes (to fix warnings).
+//
+// Revision 1.27  2003/06/22 09:43:03  mohor
+// synthesi full_case parallel_case fixed.
+//
+// Revision 1.26  2003/06/22 01:33:14  mohor
+// clkout is clk/2 after the reset.
+//
+// Revision 1.25  2003/06/21 12:16:30  mohor
+// paralel_case and full_case compiler directives added to case statements.
+//
+// Revision 1.24  2003/06/09 11:22:54  mohor
+// data_out is already registered in the can_top.v file.
+//
+// Revision 1.23  2003/04/15 15:31:24  mohor
+// Some features are supported in extended mode only (listen_only_mode...).
+//
+// Revision 1.22  2003/03/20 16:58:50  mohor
+// unix.
+//
+// Revision 1.20  2003/03/11 16:31:05  mohor
+// Mux used for clkout to avoid "gated clocks warning".
+//
+// Revision 1.19  2003/03/10 17:34:25  mohor
+// Doubled declarations removed.
+//
+// Revision 1.18  2003/03/01 22:52:11  mohor
+// Data is latched on read.
+//
+// Revision 1.17  2003/02/19 15:09:02  mohor
+// Incomplete sensitivity list fixed.
+//
+// Revision 1.16  2003/02/19 14:44:03  mohor
+// CAN core finished. Host interface added. Registers finished.
+// Synchronization to the wishbone finished.
+//
+// Revision 1.15  2003/02/18 00:10:15  mohor
+// Most of the registers added. Registers "arbitration lost capture", "error code
+// capture" + few more still need to be added.
+//
+// Revision 1.14  2003/02/14 20:17:01  mohor
+// Several registers added. Not finished, yet.
+//
+// Revision 1.13  2003/02/12 14:25:30  mohor
+// abort_tx added.
+//
+// Revision 1.12  2003/02/11 00:56:06  mohor
+// Wishbone interface added.
+//
+// Revision 1.11  2003/02/09 02:24:33  mohor
+// Bosch license warning added. Error counters finished. Overload frames
+// still need to be fixed.
+//
+// Revision 1.10  2003/01/31 01:13:38  mohor
+// backup.
+//
+// Revision 1.9  2003/01/15 13:16:48  mohor
+// When a frame with "remote request" is received, no data is stored
+// to fifo, just the frame information (identifier, ...). Data length
+// that is stored is the received data length and not the actual data
+// length that is stored to fifo.
+//
+// Revision 1.8  2003/01/14 17:25:09  mohor
+// Addresses corrected to decimal values (previously hex).
+//
+// Revision 1.7  2003/01/14 12:19:35  mohor
+// rx_fifo is now working.
+//
+// Revision 1.6  2003/01/10 17:51:34  mohor
+// Temporary version (backup).
+//
+// Revision 1.5  2003/01/09 14:46:58  mohor
+// Temporary files (backup).
+//
+// Revision 1.4  2003/01/08 02:10:55  mohor
+// Acceptance filter added.
+//
+// Revision 1.3  2002/12/27 00:12:52  mohor
+// Header changed, testbench improved to send a frame (crc still missing).
+//
+// Revision 1.2  2002/12/26 16:00:34  mohor
+// Testbench define file added. Clock divider register added.
+//
+// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
+// Initial
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "can_defines.v"
+
+module can_registers
+( 
+  clk,
+  rst,
+  cs,
+  we,
+  addr,
+  data_in,
+  data_out,
+  irq_n,
+
+  sample_point,
+  transmitting,
+  set_reset_mode,
+  node_bus_off,
+  error_status,
+  rx_err_cnt,
+  tx_err_cnt,
+  transmit_status,
+  receive_status,
+  tx_successful,
+  need_to_tx,
+  overrun,
+  info_empty,
+  set_bus_error_irq,
+  set_arbitration_lost_irq,
+  arbitration_lost_capture,
+  node_error_passive,
+  node_error_active,
+  rx_message_counter,
+
+
+  /* Mode register */
+  reset_mode,
+  listen_only_mode,
+  acceptance_filter_mode,
+  self_test_mode,
+
+
+  /* Command register */
+  clear_data_overrun,
+  release_buffer,
+  abort_tx,
+  tx_request,
+  self_rx_request,
+  single_shot_transmission,
+  tx_state,
+  tx_state_q,
+  overload_request,
+  overload_frame,
+
+  /* Arbitration Lost Capture Register */
+  read_arbitration_lost_capture_reg,
+
+  /* Error Code Capture Register */
+  read_error_code_capture_reg,
+  error_capture_code,
+
+  /* Bus Timing 0 register */
+  baud_r_presc,
+  sync_jump_width,
+
+  /* Bus Timing 1 register */
+  time_segment1,
+  time_segment2,
+  triple_sampling,
+  
+  /* Error Warning Limit register */
+  error_warning_limit,
+
+  /* Rx Error Counter register */
+  we_rx_err_cnt,
+
+  /* Tx Error Counter register */
+  we_tx_err_cnt,
+
+  /* Clock Divider register */
+  extended_mode,
+  clkout,
+  
+  
+  /* This section is for BASIC and EXTENDED mode */
+  /* Acceptance code register */
+  acceptance_code_0,
+
+  /* Acceptance mask register */
+  acceptance_mask_0,
+  /* End: This section is for BASIC and EXTENDED mode */
+  
+  /* This section is for EXTENDED mode */
+  /* Acceptance code register */
+  acceptance_code_1,
+  acceptance_code_2,
+  acceptance_code_3,
+
+  /* Acceptance mask register */
+  acceptance_mask_1,
+  acceptance_mask_2,
+  acceptance_mask_3,
+  /* End: This section is for EXTENDED mode */
+  
+  rx_dt,
+  rx_we,
+  /* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
+  tx_data_0,
+  tx_data_1,
+  tx_data_2,
+  tx_data_3,
+  tx_data_4,
+  tx_data_5,
+  tx_data_6,
+  tx_data_7,
+  tx_data_8,
+  tx_data_9,
+  tx_data_10,
+  tx_data_11,
+  tx_data_12
+  /* End: Tx data registers */
+  
+  
+
+
+);
+
+parameter Tp = 1;
+parameter TXMBOX_DEPTH = 1; /* 1(Min=2) - 4(Max=16) */
+parameter RXMBOX_DEPTH = 1; /* 1(Min=2) - 5(Max=32) */
+localparam TXMBOX_BITS = (TXMBOX_DEPTH > 4) ? 16 : (2**TXMBOX_DEPTH);
+localparam RXMBOX_BITS = (RXMBOX_DEPTH > 5) ? 32 :(2**RXMBOX_DEPTH);
+
+input         clk;
+input         rst;
+input         cs;
+input         we;
+input   [9:0] addr;
+input  [31:0] data_in;
+
+output [31:0] data_out;
+reg    [31:0] data_out;
+
+output        irq_n;
+
+input         sample_point;
+input         transmitting;
+input         set_reset_mode;
+input         node_bus_off;
+input         error_status;
+input   [7:0] rx_err_cnt;
+input   [7:0] tx_err_cnt;
+input         transmit_status;
+input         receive_status;
+input         tx_successful;
+input         need_to_tx;
+input         overrun;
+input         info_empty;
+input         set_bus_error_irq;
+input         set_arbitration_lost_irq;
+input   [4:0] arbitration_lost_capture;
+input         node_error_passive;
+input         node_error_active;
+input   [6:0] rx_message_counter;
+
+
+
+/* Mode register */
+output        reset_mode;
+output        listen_only_mode;
+output        acceptance_filter_mode;
+output        self_test_mode;
+
+/* Command register */
+output        clear_data_overrun;
+output        release_buffer;
+output        abort_tx;
+output        tx_request;
+output        self_rx_request;
+output        single_shot_transmission;
+input         tx_state;
+input         tx_state_q;
+output        overload_request;
+input         overload_frame;
+
+
+/* Arbitration Lost Capture Register */
+output        read_arbitration_lost_capture_reg;
+
+/* Error Code Capture Register */
+output        read_error_code_capture_reg;
+input   [7:0] error_capture_code;
+
+/* Bus Timing 0 register */
+output  [5:0] baud_r_presc;
+output  [1:0] sync_jump_width;
+
+
+/* Bus Timing 1 register */
+output  [3:0] time_segment1;
+output  [2:0] time_segment2;
+output        triple_sampling;
+
+/* Error Warning Limit register */
+output  [7:0] error_warning_limit;
+
+/* Rx Error Counter register */
+output        we_rx_err_cnt;
+
+/* Tx Error Counter register */
+output        we_tx_err_cnt;
+
+/* Clock Divider register */
+output        extended_mode;
+output        clkout;
+
+
+/* This section is for BASIC and EXTENDED mode */
+/* Acceptance code register */
+output  [7:0] acceptance_code_0;
+
+/* Acceptance mask register */
+output  [7:0] acceptance_mask_0;
+
+/* End: This section is for BASIC and EXTENDED mode */
+
+
+/* This section is for EXTENDED mode */
+/* Acceptance code register */
+output  [7:0] acceptance_code_1;
+output  [7:0] acceptance_code_2;
+output  [7:0] acceptance_code_3;
+
+/* Acceptance mask register */
+output  [7:0] acceptance_mask_1;
+output  [7:0] acceptance_mask_2;
+output  [7:0] acceptance_mask_3;
+
+/* End: This section is for EXTENDED mode */
+
+
+input [127:0] rx_dt;
+input         rx_we;
+/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
+output  [7:0] tx_data_0;
+output  [7:0] tx_data_1;
+output  [7:0] tx_data_2;
+output  [7:0] tx_data_3;
+output  [7:0] tx_data_4;
+output  [7:0] tx_data_5;
+output  [7:0] tx_data_6;
+output  [7:0] tx_data_7;
+output  [7:0] tx_data_8;
+output  [7:0] tx_data_9;
+output  [7:0] tx_data_10;
+output  [7:0] tx_data_11;
+output  [7:0] tx_data_12;
+/* End: Tx data registers */
+
+
+reg  [TXMBOX_BITS-1:0]   transmit_cancel;
+reg  [RXMBOX_BITS-1:0]   rxovrwrite;
+//reg  [15:0]   transmit_cancel;
+//reg  [31:0]   rxovrwrite;
+reg           tx_successful_q;
+reg           overrun_q;
+reg           overrun_status;
+reg           transmission_complete;
+reg           transmit_buffer_status_q;
+reg           receive_buffer_status;
+reg           error_status_q;
+reg           node_bus_off_q;
+reg           node_error_passive_q;
+reg           transmit_buffer_status;
+reg           single_shot_transmission;
+reg           self_rx_request;
+reg           irq_n;
+
+// Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
+wire          data_overrun_irq_en;
+wire          error_warning_irq_en;
+wire          transmit_irq_en;
+wire          receive_irq_en;
+
+wire    [7:0] irq_reg;
+wire          irq;
+
+reg   [TXMBOX_BITS-1:0] txreq;
+reg   [TXMBOX_BITS-1:0] txabort;
+reg   [TXMBOX_BITS-1:0] txcmp;
+reg   [RXMBOX_BITS-1:0] rxwait;
+reg   [RXMBOX_BITS-1:0] rxcmp;
+reg   [TXMBOX_BITS-1:0] rxselfreq;
+//reg   [15:0] txreq;
+//reg   [15:0] txabort;
+//reg   [15:0] txcmp;
+//reg   [31:0] rxwait;
+//reg   [31:0] rxcmp;
+//reg   [15:0] rxselfreq;
+
+// fsm
+reg [1:0] state;
+reg [2:0] st_sel_cnt;
+parameter st_idle = 2'h0;
+parameter st_sel  = 2'h1;
+parameter st_set  = 2'h2;
+parameter st_wait = 2'h3;
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    state <= st_idle;
+  else if (reset_mode)
+    state <=#Tp st_idle;
+  else case (state)
+    st_idle : if (|(txreq & ~txabort)) state <=#Tp st_sel;
+    st_sel  : if (&st_sel_cnt)         state <=#Tp st_set;
+    st_set  : if ( need_to_tx)         state <=#Tp st_wait;
+    st_wait : if (~need_to_tx)         state <=#Tp st_idle;
+  endcase
+end
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    st_sel_cnt <= 3'h0;
+  else if (state == st_sel)
+    st_sel_cnt <=#Tp st_sel_cnt +3'h1;
+  else
+    st_sel_cnt <=#Tp 3'h0;
+end
+
+
+
+// sort tx data
+wire [127:0] txdata [0:TXMBOX_BITS-1];
+//wire [127:0] txdata [0:15];
+reg [127:0] txtmp  ;
+reg [28:0]  txid   ;
+reg         txfmt  ;
+reg         txrtr  ;
+reg [3:0]   txdlc  ;
+reg [7:0]   txdata1;
+reg [7:0]   txdata2;
+reg [7:0]   txdata3;
+reg [7:0]   txdata4;
+reg [7:0]   txdata5;
+reg [7:0]   txdata6;
+reg [7:0]   txdata7;
+reg [7:0]   txdata8;
+reg [3:0]   txmsgbox;
+wire        rxselfreq_en = rxselfreq[txmsgbox];
+
+always @ (*)
+begin
+  txtmp   = txdata[txmsgbox];
+  txfmt   = txtmp[0*32+31];
+  txid    = txtmp[0*32+28:0*32];
+  txrtr   = txtmp[1*32+4];
+  txdlc   = txtmp[1*32+3:1*32];
+  txdata1 = txtmp[2*32+0*8+7:2*32+0*8];
+  txdata2 = txtmp[2*32+1*8+7:2*32+1*8];
+  txdata3 = txtmp[2*32+2*8+7:2*32+2*8];
+  txdata4 = txtmp[2*32+3*8+7:2*32+3*8];
+  txdata5 = txtmp[3*32+0*8+7:3*32+0*8];
+  txdata6 = txtmp[3*32+1*8+7:3*32+1*8];
+  txdata7 = txtmp[3*32+2*8+7:3*32+2*8];
+  txdata8 = txtmp[3*32+3*8+7:3*32+3*8];
+end
+
+
+// latch tx data
+wire we_txstart;
+reg  [7:0] tx_data_0;
+reg  [7:0] tx_data_1;
+reg  [7:0] tx_data_2;
+reg  [7:0] tx_data_3;
+reg  [7:0] tx_data_4;
+reg  [7:0] tx_data_5;
+reg  [7:0] tx_data_6;
+reg  [7:0] tx_data_7;
+reg  [7:0] tx_data_8;
+reg  [7:0] tx_data_9;
+reg  [7:0] tx_data_10;
+reg  [7:0] tx_data_11;
+reg  [7:0] tx_data_12;
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+  begin
+    tx_data_0  <= 8'h0;
+    tx_data_1  <= 8'h0;
+    tx_data_2  <= 8'h0;
+    tx_data_3  <= 8'h0;
+    tx_data_4  <= 8'h0;
+    tx_data_5  <= 8'h0;
+    tx_data_6  <= 8'h0;
+    tx_data_7  <= 8'h0;
+    tx_data_8  <= 8'h0;
+    tx_data_9  <= 8'h0;
+    tx_data_10 <= 8'h0;
+    tx_data_11 <= 8'h0;
+    tx_data_12 <= 8'h0;
+  end
+  else if (we_txstart)
+  begin
+    if(~extended_mode)
+    begin
+      tx_data_0  <=#Tp txid[28:21];
+      tx_data_1  <=#Tp {txid[20:18],txrtr,txdlc};
+      tx_data_2  <=#Tp txdata1;
+      tx_data_3  <=#Tp txdata2;
+      tx_data_4  <=#Tp txdata3;
+      tx_data_5  <=#Tp txdata4;
+      tx_data_6  <=#Tp txdata5;
+      tx_data_7  <=#Tp txdata6;
+      tx_data_8  <=#Tp txdata7;
+      tx_data_9  <=#Tp txdata8;
+      tx_data_10 <=#Tp 8'h0;
+      tx_data_11 <=#Tp 8'h0;
+      tx_data_12 <=#Tp 8'h0;
+    end
+    else
+    begin
+      tx_data_0  <=#Tp {txfmt,txrtr,2'h0,txdlc};
+      tx_data_1  <=#Tp txid[28:21];
+      tx_data_2  <=#Tp (~txfmt)? {txid[20:18],5'h0}: txid[20:13];
+      tx_data_3  <=#Tp (~txfmt)? txdata1: txid[12:5];
+      tx_data_4  <=#Tp (~txfmt)? txdata2: {txid[4:0],3'h0};
+      tx_data_5  <=#Tp (~txfmt)? txdata3: txdata1;
+      tx_data_6  <=#Tp (~txfmt)? txdata4: txdata2;
+      tx_data_7  <=#Tp (~txfmt)? txdata5: txdata3;
+      tx_data_8  <=#Tp (~txfmt)? txdata6: txdata4;
+      tx_data_9  <=#Tp (~txfmt)? txdata7: txdata5;
+      tx_data_10 <=#Tp (~txfmt)? txdata8: txdata6;
+      tx_data_11 <=#Tp                    txdata7;
+      tx_data_12 <=#Tp                    txdata8;
+    end
+  end
+end
+
+
+// arbitration lost
+reg [3:0] arbitration_lost_capture_mbox;
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    arbitration_lost_capture_mbox <= 4'h0;
+  else if (set_arbitration_lost_irq)
+    arbitration_lost_capture_mbox <=#Tp txmsgbox;
+end
+
+// error capture
+reg set_bus_error_irq_q;
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    set_bus_error_irq_q <= 1'h0;
+  else
+    set_bus_error_irq_q <=#Tp set_bus_error_irq;
+end
+
+reg [3:0] error_capture_code_mbox;
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    error_capture_code_mbox <= 4'h0;
+  else if(set_bus_error_irq_q)
+    error_capture_code_mbox <=#Tp (error_capture_code[5])? 4'h0: txmsgbox;//0:tx error 1:rx error
+end
+
+
+wire we_mode                  = cs & we & (addr == 10'h0);
+wire we_command               = 0;
+wire we_bus_timing_0          = cs & we & (addr == 10'h034) & reset_mode;
+wire we_bus_timing_1          = cs & we & (addr == 10'h034) & reset_mode;
+wire we_clock_divider_low     = cs & we & (addr == 10'h034);
+wire we_clock_divider_hi      = we_clock_divider_low & reset_mode;
+
+wire we_txreq    = cs & we & (addr == 10'h004);
+wire we_txabort  = cs & we & (addr == 10'h008);
+wire we_txcmp    = cs & we & (addr == 10'h00C);
+wire we_txcancel = cs & we & (addr == 10'h010);
+wire we_rxwait   = cs & we & (addr == 10'h014);
+wire we_rxcmp    = cs & we & (addr == 10'h018);
+wire we_rxselfreq= cs & we & (addr == 10'h020);
+
+
+wire read = cs & (~we);
+wire read_rxovrwrite = read & (addr == 10'h01C);
+wire read_irq_reg = read & (addr == 10'h028);
+assign read_arbitration_lost_capture_reg = read & extended_mode & (addr == 10'h040);
+assign read_error_code_capture_reg = read & extended_mode & (addr == 10'h044);
+
+/* This section is for BASIC and EXTENDED mode */
+wire we_acceptance_code_0       = cs & we &   reset_mode  & (addr == 10'h038);
+wire we_acceptance_mask_0       = cs & we &   reset_mode  & (addr == 10'h03C);
+wire we_datawin                 = cs & we & (addr == 10'h04C);
+assign we_txstart               = (state == st_set) & transmit_buffer_status;
+/* End: This section is for BASIC and EXTENDED mode */
+
+
+/* This section is for EXTENDED mode */
+wire   we_interrupt_enable      = cs & we & (addr == 10'h02C) ;
+wire   we_irq_rxen              = cs & we & (addr == 10'h030) ;
+wire   we_error_warning_limit   = cs & we & (addr == 10'h048) & reset_mode ;
+assign we_rx_err_cnt            = cs & we & (addr == 10'h048) & reset_mode ;
+assign we_tx_err_cnt            = cs & we & (addr == 10'h048) & reset_mode ;
+wire   we_acceptance_code_1     = cs & we & (addr == 10'h038) & reset_mode ;
+wire   we_acceptance_code_2     = cs & we & (addr == 10'h038) & reset_mode ;
+wire   we_acceptance_code_3     = cs & we & (addr == 10'h038) & reset_mode ;
+wire   we_acceptance_mask_1     = cs & we & (addr == 10'h03C) & reset_mode ;
+wire   we_acceptance_mask_2     = cs & we & (addr == 10'h03C) & reset_mode ;
+wire   we_acceptance_mask_3     = cs & we & (addr == 10'h03C) & reset_mode ;
+/* End: This section is for EXTENDED mode */
+
+
+
+always @ (posedge clk)
+begin
+  tx_successful_q           <=#Tp tx_successful;
+  overrun_q                 <=#Tp overrun;
+  transmit_buffer_status_q  <=#Tp transmit_buffer_status;
+  error_status_q            <=#Tp error_status;
+  node_bus_off_q            <=#Tp node_bus_off;
+  node_error_passive_q      <=#Tp node_error_passive;
+end
+
+
+
+/* Mode register */
+wire   [0:0] mode;
+wire   [4:1] mode_basic;
+wire   [3:1] mode_ext;
+wire         receive_irq_en_basic;
+wire         transmit_irq_en_basic;
+wire         error_irq_en_basic;
+wire         overrun_irq_en_basic;
+
+can_register_asyn_syn #(1, 1'h1) MODE_REG0
+( .data_in(data_in[0]),
+  .data_out(mode[0]),
+  .we(we_mode),
+  .clk(clk),
+  .rst(rst),
+  .rst_sync(set_reset_mode)
+);
+
+can_register_asyn #(4, 4'h0) MODE_REG_BASIC
+( .data_in(data_in[4:1]),
+  .data_out(mode_basic[4:1]),
+  .we(we_mode),
+  .clk(clk),
+  .rst(rst)
+);
+
+can_register_asyn #(3, 3'h0) MODE_REG_EXT
+( .data_in(data_in[3:1]),
+  .data_out(mode_ext[3:1]),
+  .we(we_mode & reset_mode),
+  .clk(clk),
+  .rst(rst)
+);
+
+assign reset_mode             = mode[0];
+assign listen_only_mode       = extended_mode & mode_ext[1];
+assign self_test_mode         = extended_mode & mode_ext[2];
+assign acceptance_filter_mode = extended_mode & mode_ext[3];
+
+assign receive_irq_en_basic  = mode_basic[1];
+assign transmit_irq_en_basic = mode_basic[2];
+assign error_irq_en_basic    = mode_basic[3];
+assign overrun_irq_en_basic  = mode_basic[4];
+/* End Mode register */
+
+
+/* Command register */
+wire   [4:0] command;
+can_register_asyn_syn #(1, 1'h0) COMMAND_REG0
+( .data_in(~rxselfreq_en),
+  .data_out(command[0]),
+  .we(we_txstart),
+  .clk(clk),
+  .rst(rst),
+  .rst_sync(command[0] & sample_point | reset_mode)
+);
+
+can_register_asyn_syn #(1, 1'h0) COMMAND_REG1
+( .data_in(1'h1),
+  .data_out(command[1]),
+  .we(we_txstart),
+  .clk(clk),
+  .rst(rst),
+  .rst_sync(sample_point & (tx_request | (abort_tx & ~transmitting)) | reset_mode)
+);
+
+can_register_asyn_syn #(2, 2'h0) COMMAND_REG
+( .data_in(data_in[3:2]),
+  .data_out(command[3:2]),
+  .we(we_command),
+  .clk(clk),
+  .rst(rst),
+  .rst_sync(|command[3:2] | reset_mode)
+);
+
+can_register_asyn_syn #(1, 1'h0) COMMAND_REG4
+( .data_in(rxselfreq_en),
+  .data_out(command[4]),
+  .we(we_txstart),
+  .clk(clk),
+  .rst(rst),
+  .rst_sync(command[4] & sample_point | reset_mode)
+);
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    self_rx_request <= 1'b0;
+  else if (command[4] & (~command[0]))
+    self_rx_request <=#Tp 1'b1;
+  else if ((~tx_state) & tx_state_q)
+    self_rx_request <=#Tp 1'b0;
+end
+
+
+assign clear_data_overrun = command[3];
+assign release_buffer = command[2];
+assign tx_request = command[0] | command[4];
+assign abort_tx = (state == st_wait) & txabort[txmsgbox] & (~tx_request);//command[1] & (~tx_request);
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    single_shot_transmission <= 1'b0;
+//  else if (tx_request & command[1] & sample_point)
+    else if (tx_request & sample_point)
+    single_shot_transmission <=#Tp 1'b1;
+//else if ((~tx_state) & tx_state_q)
+else if ((~tx_state) & tx_state_q | (abort_tx & (~transmitting)))
+    single_shot_transmission <=#Tp 1'b0;
+end
+
+
+/*
+can_register_asyn_syn #(1, 1'h0) COMMAND_REG_OVERLOAD  // Uncomment this to enable overload requests !!!
+( .data_in(data_in[5]),
+  .data_out(overload_request),
+  .we(we_command),
+  .clk(clk),
+  .rst(rst),
+  .rst_sync(overload_frame & ~overload_frame_q)
+);
+
+reg           overload_frame_q;
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    overload_frame_q <= 1'b0;
+  else
+    overload_frame_q <=#Tp overload_frame;
+end
+*/
+assign overload_request = 0;  // Overload requests are not supported, yet !!!
+
+
+
+
+
+/* End Command register */
+
+
+/* Status register */
+
+wire   [7:0] status;
+
+assign status[7] = node_bus_off;
+assign status[6] = error_status;
+assign status[5] = transmit_status;
+assign status[4] = receive_status;
+assign status[3] = transmission_complete;
+assign status[2] = transmit_buffer_status;
+assign status[1] = overrun_status;
+assign status[0] = receive_buffer_status;
+
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    transmission_complete <= 1'b1;
+  else if (tx_successful & (~tx_successful_q) | abort_tx)
+    transmission_complete <=#Tp 1'b1;
+  else if (tx_request)
+    transmission_complete <=#Tp 1'b0;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    transmit_buffer_status <= 1'b1;
+  else if (tx_request)
+    transmit_buffer_status <=#Tp 1'b0;
+  else if (reset_mode || !need_to_tx)
+    transmit_buffer_status <=#Tp 1'b1;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    overrun_status <= 1'b0;
+  else if (overrun & (~overrun_q))
+    overrun_status <=#Tp 1'b1;
+  else if (reset_mode || clear_data_overrun)
+    overrun_status <=#Tp 1'b0;
+end
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    receive_buffer_status <= 1'b0;
+  else if (reset_mode || release_buffer)
+    receive_buffer_status <=#Tp 1'b0;
+  else if (~info_empty)
+    receive_buffer_status <=#Tp 1'b1;
+end
+
+/* End Status register */
+
+
+/* Interrupt Enable register (extended mode) */
+wire   [7:0] irq_en_ext;
+wire  [31:0] irq_rxen;
+wire         bus_error_irq_en;
+wire         arbitration_lost_irq_en;
+wire         error_passive_irq_en;
+wire         transmit_cancel_irq_en;
+wire         data_overrun_irq_en_ext;
+wire         error_warning_irq_en_ext;
+wire         transmit_irq_en_ext;
+wire         receive_irq_en_ext;
+
+can_register_asyn #(8, 8'h0) IRQ_EN_REG
+( .data_in(data_in[7:0]),
+  .data_out(irq_en_ext),
+  .we(we_interrupt_enable),
+  .clk(clk),
+  .rst(rst)
+);
+
+can_register_asyn #(32, 32'h0) IRQ_RXEN_REG
+( .data_in(data_in),
+  .data_out(irq_rxen),
+  .we(we_irq_rxen),
+  .clk(clk),
+  .rst(rst)
+);
+
+
+assign bus_error_irq_en             = extended_mode & irq_en_ext[7];
+assign arbitration_lost_irq_en      = extended_mode & irq_en_ext[6];
+assign error_passive_irq_en         = extended_mode & irq_en_ext[5];
+assign transmit_cancel_irq_en       = irq_en_ext[4];
+assign data_overrun_irq_en_ext      = irq_en_ext[3];
+assign error_warning_irq_en_ext     = irq_en_ext[2];
+assign transmit_irq_en_ext          = irq_en_ext[1];
+assign receive_irq_en_ext           = irq_en_ext[0];
+/* End Bus Timing 0 register */
+
+
+/* Bus Timing 0 register */
+wire   [7:0] bus_timing_0;
+can_register_asyn #(8, 8'h0) BUS_TIMING_0_REG
+( .data_in(data_in[0*8+7:0*8]),
+  .data_out(bus_timing_0),
+  .we(we_bus_timing_0),
+  .clk(clk),
+  .rst(rst)
+);
+
+assign baud_r_presc = bus_timing_0[5:0];
+assign sync_jump_width = bus_timing_0[7:6];
+/* End Bus Timing 0 register */
+
+
+/* Bus Timing 1 register */
+wire   [7:0] bus_timing_1;
+can_register_asyn #(8, 8'h0) BUS_TIMING_1_REG
+( .data_in(data_in[1*8+7:1*8]),
+  .data_out(bus_timing_1),
+  .we(we_bus_timing_1),
+  .clk(clk),
+  .rst(rst)
+);
+
+assign time_segment1 = bus_timing_1[3:0];
+assign time_segment2 = bus_timing_1[6:4];
+assign triple_sampling = bus_timing_1[7];
+/* End Bus Timing 1 register */
+
+
+/* Error Warning Limit register */
+can_register_asyn #(8, 8'd96) ERROR_WARNING_REG
+( .data_in(data_in[0*8+7:0*8]),
+  .data_out(error_warning_limit),
+  .we(we_error_warning_limit),
+  .clk(clk),
+  .rst(rst)
+);
+/* End Error Warning Limit register */
+
+
+
+/* Clock Divider register */
+wire   [7:0] clock_divider;
+wire         clock_off;
+wire   [2:0] cd;
+reg    [2:0] clkout_div;
+reg    [2:0] clkout_cnt;
+reg          clkout_tmp;
+
+can_register_asyn #(1, 1'h0) CLOCK_DIVIDER_REG_7
+( .data_in(data_in[3*8+7]),
+  .data_out(clock_divider[7]),
+  .we(we_clock_divider_hi),
+  .clk(clk),
+  .rst(rst)
+);
+
+assign clock_divider[6:4] = 3'h0;
+
+can_register_asyn #(1, 1'h0) CLOCK_DIVIDER_REG_3
+( .data_in(data_in[3*8+3]),
+  .data_out(clock_divider[3]),
+  .we(we_clock_divider_hi),
+  .clk(clk),
+  .rst(rst)
+);
+
+can_register_asyn #(3, 3'h0) CLOCK_DIVIDER_REG_LOW
+( .data_in(data_in[3*8+2:3*8]),
+  .data_out(clock_divider[2:0]),
+  .we(we_clock_divider_low),
+  .clk(clk),
+  .rst(rst)
+);
+
+assign extended_mode = clock_divider[7];
+assign clock_off     = clock_divider[3];
+assign cd[2:0]       = clock_divider[2:0];
+
+
+
+always @ (cd)
+begin
+  case (cd)                       /* synthesis full_case parallel_case */ 
+    3'b000 : clkout_div = 3'd0;
+    3'b001 : clkout_div = 3'd1;
+    3'b010 : clkout_div = 3'd2;
+    3'b011 : clkout_div = 3'd3;
+    3'b100 : clkout_div = 3'd4;
+    3'b101 : clkout_div = 3'd5;
+    3'b110 : clkout_div = 3'd6;
+    3'b111 : clkout_div = 3'd0;
+  endcase
+end
+
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    clkout_cnt <= 3'h0;
+  else if (clkout_cnt == clkout_div)
+    clkout_cnt <=#Tp 3'h0;
+  else
+    clkout_cnt <= clkout_cnt + 1'b1;
+end
+
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    clkout_tmp <= 1'b0;
+  else if (clkout_cnt == clkout_div)
+    clkout_tmp <=#Tp ~clkout_tmp;
+end
+
+
+assign clkout = clock_off ? 1'b1 : ((&cd)? clk : clkout_tmp);
+
+
+
+/* End Clock Divider register */
+
+
+
+
+/* This section is for BASIC and EXTENDED mode */
+
+/* Acceptance code register */
+can_register_asyn #(8, 8'h0) ACCEPTANCE_CODE_REG0
+( .data_in(data_in[3*8+7:3*8]),
+  .data_out(acceptance_code_0),
+  .we(we_acceptance_code_0),
+  .clk(clk),
+  .rst(rst)
+);
+/* End: Acceptance code register */
+
+
+/* Acceptance mask register */
+can_register_asyn #(8, 8'h0) ACCEPTANCE_MASK_REG0
+( .data_in(data_in[3*8+7:3*8]),
+  .data_out(acceptance_mask_0),
+  .we(we_acceptance_mask_0),
+  .clk(clk),
+  .rst(rst)
+);
+/* End: Acceptance mask register */
+
+
+/* Data window register */
+wire [RXMBOX_DEPTH-1:0] rxdatawin;
+//wire [4:0] rxdatawin;
+can_register_asyn #((RXMBOX_DEPTH), {(RXMBOX_DEPTH){1'h0}}) MODE_RXDATAWIN_REG
+//can_register_asyn #(5, 5'h0) MODE_RXDATAWIN_REG
+( .data_in(data_in[(RXMBOX_DEPTH-1+16):16]),
+  .data_out(rxdatawin),
+  .we(we_datawin),
+  .clk(clk),
+  .rst(rst)
+);
+/* End: Data window register */
+/* End: This section is for BASIC and EXTENDED mode */
+
+
+/* Tx data register. */
+//parameter t = 16;
+wire [(TXMBOX_BITS)*4-1:0] we_txdata;
+wire [(TXMBOX_BITS)*128-1:0] txdata_reg;
+wire [(TXMBOX_BITS)*29+28:0] txdata_reg_id;
+reg [(TXMBOX_BITS)*34-1:0] txdata_ff;
+//wire [63:0] we_txdata;
+//wire [2047:0] txdata_reg;
+//wire [16*29+28:0] txdata_reg_id;
+//reg [16*34-1:0] txdata_ff;
+reg [ 8*34-1:0] rank_lvl1;
+reg [ 4*34-1:0] rank_lvl2;
+reg [ 2*34-1:0] rank_lvl3;
+wire [63:0] mboxnum;
+
+reg aleb1[7:0];
+reg aleb2[3:0];
+reg aleb3[1:0];
+reg aleb4;
+
+assign mboxnum = 64'hfedcba9876543210;
+generate
+  genvar i,j;
+  for (i=0; i<16; i=i+1) begin :txdata_i_reg
+    for (j=0; j<4; j=j+1) begin :txdata_j_reg
+      if (i < TXMBOX_BITS) begin
+        assign we_txdata[i*4+j] = cs & we & ~txreq[i] & (addr[9:8] == 2'h1) & (addr[7:4] == i) & (addr[3:0] == (4'h4*j));
+        can_register_asyn #(32, 32'h0) TXDATA_REG( .data_in(data_in),  .data_out(txdata_reg[i*128+j*32+31:i*128+j*32]),  .we(we_txdata[i*4+j]),  .clk(clk),  .rst(rst));
+      end //for
+    end //for
+
+    if (i < TXMBOX_BITS) begin
+      assign txdata[i] = txdata_reg[i*128+127:i*128];
+
+      // arbiter
+      assign txdata_reg_id[i*29+28:i*29] = (extended_mode & txdata_reg[i*128+31])? txdata_reg[i*128+28:i*128]: {txdata_reg[i*128+28:i*128+18],18'h0};
+
+      always @ (posedge clk or posedge rst) begin
+        if (rst) begin
+          txdata_ff[i*34+33:i*34] <= 34'h0;
+        end else if (~reset_mode & (state == st_idle) & |(txreq & ~txabort)) begin
+          txdata_ff[i*34+33:i*34] <=#Tp {txreq[i] & ~txabort[i] , mboxnum[i*4+3:i*4] , txdata_reg_id[i*29+28:i*29]};
+        end
+      end
+    end
+
+    if(i<8) begin
+      always @ (posedge clk) begin
+        if (i >= (TXMBOX_BITS-1)) begin
+          aleb1[i] <= 0;
+        end else begin
+          aleb1[i] <= (txdata_ff[2*i*34+28:2*i*34]<=txdata_ff[(2*i+1)*34+28:(2*i+1)*34]);
+        end
+      end
+
+      always @ (posedge clk or posedge rst) begin
+        if (i >= (TXMBOX_BITS-1)) begin
+           rank_lvl1[i*34+33:i*34] <= #Tp 0;
+        end else begin
+          case({txdata_ff[(2*i+1)*34+33],txdata_ff[2*i*34+33]})
+            2'h0: rank_lvl1[i*34+33:i*34] <=#Tp txdata_ff[2*i*34+33:2*i*34];
+            2'h1: rank_lvl1[i*34+33:i*34] <=#Tp txdata_ff[2*i*34+33:2*i*34];
+            2'h2: rank_lvl1[i*34+33:i*34] <=#Tp txdata_ff[(2*i+1)*34+33:(2*i+1)*34];
+            2'h3: rank_lvl1[i*34+33:i*34] <=#Tp (aleb1[i])? txdata_ff[2*i*34+33:2*i*34]: txdata_ff[(2*i+1)*34+33:(2*i+1)*34];
+            //(txdata_ff[2*i*34+28:2*i*34]<=txdata_ff[(2*i+1)*34+28:(2*i+1)*34])? txdata_ff[2*i*34+33:2*i*34]: txdata_ff[(2*i+1)*34+33:(2*i+1)*34];
+          endcase
+        end
+      end
+    end
+ 
+    if(i<4) begin
+      always @ (posedge clk) begin
+        if (i >= (TXMBOX_BITS-1)) begin
+          aleb2[i] <= 0;
+        end else begin
+          aleb2[i] <= (rank_lvl1[2*i*34+28:2*i*34]<=rank_lvl1[(2*i+1)*34+28:(2*i+1)*34]);
+        end
+      end
+
+      always @ (posedge clk) begin
+        if (i >= (TXMBOX_BITS-1)) begin
+           rank_lvl2[i*34+33:i*34] <= #Tp 0;
+        end else begin
+          case({rank_lvl1[(2*i+1)*34+33],rank_lvl1[2*i*34+33]})
+            2'h0: rank_lvl2[i*34+33:i*34] <=#Tp rank_lvl1[2*i*34+33:2*i*34];
+            2'h1: rank_lvl2[i*34+33:i*34] <=#Tp rank_lvl1[2*i*34+33:2*i*34];
+            2'h2: rank_lvl2[i*34+33:i*34] <=#Tp rank_lvl1[(2*i+1)*34+33:(2*i+1)*34];
+            2'h3: rank_lvl2[i*34+33:i*34] <=#Tp (aleb2[i])? rank_lvl1[2*i*34+33:2*i*34]: rank_lvl1[(2*i+1)*34+33:(2*i+1)*34];//rank_lvl1[(2*i+1)*34+33:(2*i+1)*34];
+          endcase
+        end
+      end
+    end
+
+    if(i<2) begin
+      always @ (posedge clk or posedge rst) begin
+        if (i >= (TXMBOX_BITS-1)) begin
+          aleb3[i] <= 0;
+        end else begin
+          aleb3[i] <= (rank_lvl2[2*i*34+28:2*i*34]<=rank_lvl2[(2*i+1)*34+28:(2*i+1)*34]);
+        end
+      end
+
+      always @ (posedge clk or posedge rst) begin
+        if (i >= (TXMBOX_BITS-1)) begin
+           rank_lvl3[i*34+33:i*34] <= #Tp 0;
+        end else begin
+          case({rank_lvl2[(2*i+1)*34+33],rank_lvl2[2*i*34+33]})
+            2'h0: rank_lvl3[i*34+33:i*34] <=#Tp rank_lvl2[2*i*34+33:2*i*34];
+            2'h1: rank_lvl3[i*34+33:i*34] <=#Tp rank_lvl2[2*i*34+33:2*i*34];
+            2'h2: rank_lvl3[i*34+33:i*34] <=#Tp rank_lvl2[(2*i+1)*34+33:(2*i+1)*34];
+            2'h3: rank_lvl3[i*34+33:i*34] <=#Tp (aleb3[i])? rank_lvl2[2*i*34+33:2*i*34]: rank_lvl2[(2*i+1)*34+33:(2*i+1)*34];//rank_lvl2[(2*i+1)*34+33:(2*i+1)*34];
+            //(rank_lvl2[2*i*34+28:2*i*34]<=rank_lvl2[(2*i+1)*34+28:(2*i+1)*34])? rank_lvl2[2*i*34+33:2*i*34]: rank_lvl2[(2*i+1)*34+33:(2*i+1)*34];
+          endcase
+        end
+      end
+    end
+
+    if(i<1) begin
+      always @ (posedge clk or posedge rst) begin
+        if (i >= (TXMBOX_BITS-1)) begin
+          aleb4 <= 0;
+        end else begin
+          aleb4 <= (rank_lvl3[2*i*34+28:2*i*34]<=rank_lvl3[(2*i+1)*34+28:(2*i+1)*34]);
+        end
+      end
+
+      always @ (posedge clk or posedge rst) begin
+        case({rank_lvl3[(2*i+1)*34+33],rank_lvl3[2*i*34+33]})
+          2'h0: txmsgbox <=#Tp rank_lvl3[2*i*34+32:2*i*34+29];
+          2'h1: txmsgbox <=#Tp rank_lvl3[2*i*34+32:2*i*34+29];
+          2'h2: txmsgbox <=#Tp rank_lvl3[(2*i+1)*34+32:(2*i+1)*34+29];
+          2'h3: txmsgbox <=#Tp (aleb4)? rank_lvl3[2*i*34+32:2*i*34+29]: rank_lvl3[(2*i+1)*34+32:(2*i+1)*34+29];//rank_lvl3[(2*i+1)*34+32:(2*i+1)*34+29];
+          //(rank_lvl3[2*i*34+28:2*i*34]<=rank_lvl3[(2*i+1)*34+28:(2*i+1)*34])? rank_lvl3[2*i*34+32:2*i*34+29]: rank_lvl3[(2*i+1)*34+32:(2*i+1)*34+29];
+          endcase
+      end
+    end
+
+  end //for
+endgenerate
+
+
+
+//generate
+//  genvar i,j;
+//  for (i=0; i<16; i=i+1) begin :txdata_i_reg
+//    for (j=0; j<4; j=j+1) begin :txdata_j_reg
+//      assign we_txdata[i*4+j] = cs & we & ~txreq[i] & (addr[9:8] == 2'h1) & (addr[7:4] == i) & (addr[3:0] == (4'h4*j));
+//      can_register_asyn #(32, 32'h0) TXDATA_REG( .data_in(data_in),  .data_out(txdata_reg[i*128+j*32+31:i*128+j*32]),  .we(we_txdata[i*4+j]),  .clk(clk),  .rst(rst));
+//    end //for
+//    assign txdata[i] = txdata_reg[i*128+127:i*128];
+//
+//
+//
+//  // arbiter
+//    assign txdata_reg_id[i*29+28:i*29] = (extended_mode & txdata_reg[i*128+31])? txdata_reg[i*128+28:i*128]: {txdata_reg[i*128+28:i*128+18],18'h0};
+//
+//    always @ (posedge clk or posedge rst)
+//    begin
+//      if (rst)
+//        txdata_ff[i*34+33:i*34] <= 34'h0;
+//      else if (~reset_mode & (state == st_idle) & |(txreq & ~txabort))
+//        txdata_ff[i*34+33:i*34] <=#Tp {txreq[i] & ~txabort[i] , mboxnum[i*4+3:i*4] , txdata_reg_id[i*29+28:i*29]};
+//    end
+//
+//    if(i<8)begin
+//
+//
+//always @ (posedge clk) aleb1[i] <= (txdata_ff[2*i*34+28:2*i*34]<=txdata_ff[(2*i+1)*34+28:(2*i+1)*34]);
+//
+//    begin
+//      always @ (posedge clk or posedge rst)
+//      begin
+//        case({txdata_ff[(2*i+1)*34+33],txdata_ff[2*i*34+33]})
+//          2'h0: rank_lvl1[i*34+33:i*34] <=#Tp txdata_ff[2*i*34+33:2*i*34];
+//          2'h1: rank_lvl1[i*34+33:i*34] <=#Tp txdata_ff[2*i*34+33:2*i*34];
+//          2'h2: rank_lvl1[i*34+33:i*34] <=#Tp txdata_ff[(2*i+1)*34+33:(2*i+1)*34];
+//          2'h3: rank_lvl1[i*34+33:i*34] <=#Tp (aleb1[i])? txdata_ff[2*i*34+33:2*i*34]: txdata_ff[(2*i+1)*34+33:(2*i+1)*34];
+//          //(txdata_ff[2*i*34+28:2*i*34]<=txdata_ff[(2*i+1)*34+28:(2*i+1)*34])? txdata_ff[2*i*34+33:2*i*34]: txdata_ff[(2*i+1)*34+33:(2*i+1)*34];
+//        endcase
+//      end
+//    end
+//end
+//    if(i<4)begin
+//
+//always @ (posedge clk) aleb2[i] <= (rank_lvl1[2*i*34+28:2*i*34]<=rank_lvl1[(2*i+1)*34+28:(2*i+1)*34]);
+//
+//    begin
+//      always @ (posedge clk or posedge rst)
+//      begin
+//        case({rank_lvl1[(2*i+1)*34+33],rank_lvl1[2*i*34+33]})
+//          2'h0: rank_lvl2[i*34+33:i*34] <=#Tp rank_lvl1[2*i*34+33:2*i*34];
+//          2'h1: rank_lvl2[i*34+33:i*34] <=#Tp rank_lvl1[2*i*34+33:2*i*34];
+//          2'h2: rank_lvl2[i*34+33:i*34] <=#Tp rank_lvl1[(2*i+1)*34+33:(2*i+1)*34];
+//          2'h3: rank_lvl2[i*34+33:i*34] <=#Tp (aleb2[i])? rank_lvl1[2*i*34+33:2*i*34]: rank_lvl1[(2*i+1)*34+33:(2*i+1)*34];//rank_lvl1[(2*i+1)*34+33:(2*i+1)*34];
+//          //(rank_lvl1[2*i*34+28:2*i*34]<=rank_lvl1[(2*i+1)*34+28:(2*i+1)*34])? rank_lvl1[2*i*34+33:2*i*34]: rank_lvl1[(2*i+1)*34+33:(2*i+1)*34];
+//        endcase
+//      end
+//    end
+//end
+//    if(i<2)
+//    begin
+//
+//always @ (posedge clk) aleb3[i] <= (rank_lvl2[2*i*34+28:2*i*34]<=rank_lvl2[(2*i+1)*34+28:(2*i+1)*34]);
+//
+//
+//      always @ (posedge clk or posedge rst)
+//      begin
+//        case({rank_lvl2[(2*i+1)*34+33],rank_lvl2[2*i*34+33]})
+//          2'h0: rank_lvl3[i*34+33:i*34] <=#Tp rank_lvl2[2*i*34+33:2*i*34];
+//          2'h1: rank_lvl3[i*34+33:i*34] <=#Tp rank_lvl2[2*i*34+33:2*i*34];
+//          2'h2: rank_lvl3[i*34+33:i*34] <=#Tp rank_lvl2[(2*i+1)*34+33:(2*i+1)*34];
+//          2'h3: rank_lvl3[i*34+33:i*34] <=#Tp (aleb3[i])? rank_lvl2[2*i*34+33:2*i*34]: rank_lvl2[(2*i+1)*34+33:(2*i+1)*34];//rank_lvl2[(2*i+1)*34+33:(2*i+1)*34];
+//          //(rank_lvl2[2*i*34+28:2*i*34]<=rank_lvl2[(2*i+1)*34+28:(2*i+1)*34])? rank_lvl2[2*i*34+33:2*i*34]: rank_lvl2[(2*i+1)*34+33:(2*i+1)*34];
+//        endcase
+//      end
+//    end
+//
+//
+//    if(i<1)
+//    begin
+//
+//always @ (posedge clk) aleb4 <= (rank_lvl3[2*i*34+28:2*i*34]<=rank_lvl3[(2*i+1)*34+28:(2*i+1)*34]);
+//
+//
+//      always @ (posedge clk or posedge rst)
+//      begin
+//        case({rank_lvl3[(2*i+1)*34+33],rank_lvl3[2*i*34+33]})
+//          2'h0: txmsgbox <=#Tp rank_lvl3[2*i*34+32:2*i*34+29];
+//          2'h1: txmsgbox <=#Tp rank_lvl3[2*i*34+32:2*i*34+29];
+//          2'h2: txmsgbox <=#Tp rank_lvl3[(2*i+1)*34+32:(2*i+1)*34+29];
+//          2'h3: txmsgbox <=#Tp (aleb4)? rank_lvl3[2*i*34+32:2*i*34+29]: rank_lvl3[(2*i+1)*34+32:(2*i+1)*34+29];//rank_lvl3[(2*i+1)*34+32:(2*i+1)*34+29];
+//          //(rank_lvl3[2*i*34+28:2*i*34]<=rank_lvl3[(2*i+1)*34+28:(2*i+1)*34])? rank_lvl3[2*i*34+32:2*i*34+29]: rank_lvl3[(2*i+1)*34+32:(2*i+1)*34+29];
+//        endcase
+//      end
+//    end
+//
+//
+//  end //for
+//endgenerate
+///* End: Tx data register. */
+
+
+/* Rx data register. */
+//parameter r = 32;
+wire [RXMBOX_BITS-1:0] rx_we_ff;
+wire [127:0] rxdata [0:RXMBOX_BITS-1];
+//wire [31:0] rx_we_ff;
+//wire [127:0] rxdata [0:31];
+wire [31:0] we_rxcode;
+wire [31:0] we_rxmask;
+wire [31:0] rxmask [0:RXMBOX_BITS-1];
+wire [31:0] rxcode [0:RXMBOX_BITS-1];
+//wire [31:0] rxmask [0:31];
+//wire [31:0] rxcode [0:31];
+wire [1023:0] rxmask_in; // XXX
+wire [1023:0] rxcode_in; // XXX
+generate
+  genvar k;
+  for (k=0; k<RXMBOX_BITS; k=k+1) begin :rxdata_reg
+//  for (k=0; k<32; k=k+1) begin :rxdata_reg
+//  can_register_asyn #(128, 128'h0) RXWRDATA_REG0( .data_in(rx_dt_ff),  .data_out(rxdata[k]),  .we(rx_we_ff[k]),  .clk(clk),  .rst(rst));
+
+    assign we_rxcode[k] = cs & we & (addr == 10'h070) & (rxdatawin == k) & reset_mode;
+    assign we_rxmask[k] = cs & we & (addr == 10'h074) & (rxdatawin == k) & reset_mode;
+
+    can_register_asyn #(32, 32'h0) RXWRDATA_REG2( .data_in(data_in),  .data_out(rxcode[k]),  .we(we_rxcode[k]),  .clk(clk),  .rst(rst));
+    can_register_asyn #(32, 32'h0) RXWRDATA_REG3( .data_in(data_in),  .data_out(rxmask[k]),  .we(we_rxmask[k]),  .clk(clk),  .rst(rst));
+
+    assign rxmask_in[32*k+31:32*k] = rxmask[k];
+    assign rxcode_in[32*k+31:32*k] = rxcode[k];
+
+  end //for
+endgenerate
+
+wire [127:0] rxmsgdata;
+//can_rxmboxacf can_rxmboxacf(
+can_rxmboxacf #(.TXMBOX_DEPTH(TXMBOX_DEPTH), .RXMBOX_DEPTH(RXMBOX_DEPTH)) can_rxmboxacf(
+  .clk(clk),
+  .rst(rst),
+  .sample_point(sample_point),
+  .rxwait(rxwait),
+  .rxcmp(rxcmp),
+  .reset_mode(reset_mode),
+  .acceptance_filter_mode(acceptance_filter_mode),
+  .extended_mode(extended_mode),
+  .rxcode(rxcode_in),
+  .rxmask(rxmask_in),
+  .rxdatawin(addr[(RXMBOX_DEPTH-1+4):4]),
+//  .rxdatawin(addr[8:4]),
+  .rx_dt(rx_dt),
+  .rx_we(rx_we),
+  .rxmsgdata(rxmsgdata),
+  .rx_we_ff(rx_we_ff)
+);
+/* End: Rx data register. */
+
+
+/* Tx controll register. */
+generate
+  genvar a;
+  for (a=0; a<TXMBOX_BITS; a=a+1) begin :txsts_reg
+//  for (a=0; a<16; a=a+1) begin :txsts_reg
+    
+    
+    always @ (posedge clk or posedge rst)
+    begin
+      if (rst)
+        txreq[a] <= 1'h0;
+      else if (reset_mode)
+        txreq[a] <=#Tp 1'h0;
+      else if (we_txreq & data_in[a] & ~txreq[a])
+        txreq[a] <=#Tp 1'h1;
+      else if ((state == st_wait) & (txmsgbox == a) & tx_successful & (~tx_successful_q))
+        txreq[a] <=#Tp 1'h0;
+      else if (txabort[a])
+        case(state)
+          st_idle :                    txreq[a] <=#Tp 1'h0;
+          st_sel  :                    txreq[a] <=#Tp txreq[a];
+          default : if (txmsgbox != a) txreq[a] <=#Tp 1'h0;
+        endcase
+    end
+    
+    
+    always @ (posedge clk or posedge rst)
+    begin
+      if (rst)
+        txabort[a] <= 1'h0;
+      else if (reset_mode)
+        txabort[a] <=#Tp 1'h0;
+      else if (~txreq[a])
+        txabort[a] <=#Tp 1'h0;
+      else if (we_txabort & data_in[a] & txreq[a])
+        txabort[a] <=#Tp 1'h1;
+    end
+    
+    
+    always @ (posedge clk or posedge rst)
+    begin
+      if (rst)
+        transmit_cancel[a] <= 1'h0;
+      else if (txreq[a] & txabort[a])
+        case(state)
+          st_idle :                    transmit_cancel[a] <=#Tp 1'h1;
+          st_sel  :                    transmit_cancel[a] <=#Tp transmit_cancel[a];
+          default : if (txmsgbox != a) transmit_cancel[a] <=#Tp 1'h1;
+        endcase
+      else if (we_txcancel & data_in[a])
+        transmit_cancel[a] <=#Tp 1'h0;
+    end
+    
+    
+    always @ (posedge clk or posedge rst)
+    begin
+      if (rst)
+        txcmp[a] <= 1'h0;
+      else if ((state == st_wait) & (txmsgbox == a) & tx_successful & (~tx_successful_q))
+        txcmp[a] <=#Tp 1'h1;
+      else if (we_txcmp & data_in[a])
+        txcmp[a] <=#Tp 1'h0;
+    end
+    
+    
+    always @ (posedge clk or posedge rst)
+    begin
+      if (rst)
+        rxselfreq[a] <= 1'h0;
+      else if (we_rxselfreq)
+        rxselfreq[a] <=#Tp data_in[a];
+    end
+    
+    
+  end //for
+endgenerate
+/* End: Tx controll register. */
+
+
+/* Rx controll register. */
+generate
+  genvar b;
+  for (b=0; b<RXMBOX_BITS; b=b+1) begin :rxsts_reg
+//  for (b=0; b<32; b=b+1) begin :rxsts_reg
+
+
+    always @ (posedge clk or posedge rst)
+    begin
+      if (rst)
+        rxwait[b] <= 1'h0;
+      else if (we_rxwait)
+        rxwait[b] <=#Tp data_in[b];
+    end
+    
+    
+    always @ (posedge clk or posedge rst)
+    begin
+      if (rst)
+        rxcmp[b] <= 1'h0;
+      else if (rx_we_ff[b])
+        rxcmp[b] <=#Tp 1'h1;
+      else if (we_rxcmp & data_in[b])
+        rxcmp[b] <=#Tp 1'h0;
+    end
+    
+    
+    always @ (posedge clk or posedge rst)
+    begin
+      if (rst)
+        rxovrwrite[b] <= 1'h0;
+      else if (rx_we_ff[b] & rxcmp[b])
+        rxovrwrite[b] <=#Tp 1'h1;
+      else if (read_rxovrwrite)
+        rxovrwrite[b] <=#Tp 1'h0;
+    end
+    
+    
+  end //for
+endgenerate
+/* End: Rx controll register. */
+
+
+/* This section is for EXTENDED mode */
+
+/* Acceptance code register 1 */
+can_register_asyn #(8, 8'h0) ACCEPTANCE_CODE_REG1
+( .data_in(data_in[2*8+7:2*8+0]),
+  .data_out(acceptance_code_1),
+  .we(we_acceptance_code_1),
+  .clk(clk),
+  .rst(rst)
+);
+/* End: Acceptance code register */
+
+
+/* Acceptance code register 2 */
+can_register_asyn #(8, 8'h0) ACCEPTANCE_CODE_REG2
+( .data_in(data_in[1*8+7:1*8+0]),
+  .data_out(acceptance_code_2),
+  .we(we_acceptance_code_2),
+  .clk(clk),
+  .rst(rst)
+);
+/* End: Acceptance code register */
+
+
+/* Acceptance code register 3 */
+can_register_asyn #(8, 8'h0) ACCEPTANCE_CODE_REG3
+( .data_in(data_in[0*8+7:0*8+0]),
+  .data_out(acceptance_code_3),
+  .we(we_acceptance_code_3),
+  .clk(clk),
+  .rst(rst)
+);
+/* End: Acceptance code register */
+
+
+/* Acceptance mask register 1 */
+can_register_asyn #(8, 8'h0) ACCEPTANCE_MASK_REG1
+( .data_in(data_in[2*8+7:2*8+0]),
+  .data_out(acceptance_mask_1),
+  .we(we_acceptance_mask_1),
+  .clk(clk),
+  .rst(rst)
+);
+/* End: Acceptance code register */
+
+
+/* Acceptance mask register 2 */
+can_register_asyn #(8, 8'h0) ACCEPTANCE_MASK_REG2
+( .data_in(data_in[1*8+7:1*8+0]),
+  .data_out(acceptance_mask_2),
+  .we(we_acceptance_mask_2),
+  .clk(clk),
+  .rst(rst)
+);
+/* End: Acceptance code register */
+
+
+/* Acceptance mask register 3 */
+can_register_asyn #(8, 8'h0) ACCEPTANCE_MASK_REG3
+( .data_in(data_in[0*8+7:0*8+0]),
+  .data_out(acceptance_mask_3),
+  .we(we_acceptance_mask_3),
+  .clk(clk),
+  .rst(rst)
+);
+/* End: Acceptance code register */
+
+
+/* End: This section is for EXTENDED mode */
+
+
+
+
+// Selecting massage read data 
+reg [127:0] txmsgdata;
+always @ (*)
+begin
+  txmsgdata = txdata[addr[7:4]];
+end
+
+// Reading data from registers
+reg [31:0] data_out_reg;
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    data_out_reg <= 32'b0;
+  else if(addr[9:8] == 2'h0)
+  begin
+    case(addr[7:0])  /* synthesis parallel_case */ 
+      8'h00   : data_out_reg <= {24'h0, 4'h0, mode_ext[3:1], mode[0]};
+      8'h04   : data_out_reg <= {16'h0, txreq};
+      8'h08   : data_out_reg <= {16'h0, txabort};
+      8'h0C   : data_out_reg <= {16'h0, txcmp};
+      8'h10   : data_out_reg <= {16'h0, transmit_cancel};
+      8'h14   : data_out_reg <= rxwait;
+      8'h18   : data_out_reg <= rxcmp;
+      8'h1C   : data_out_reg <= rxovrwrite;
+      8'h20   : data_out_reg <= {16'h0, rxselfreq};
+      8'h24   : data_out_reg <= {24'h0, status};
+      8'h28   : data_out_reg <= {24'h0, irq_reg};
+      8'h2C   : data_out_reg <= {24'h0, irq_en_ext};
+      8'h30   : data_out_reg <= irq_rxen;
+      8'h34   : data_out_reg <= {clock_divider, 8'h0, bus_timing_1, bus_timing_0};
+      8'h38   : data_out_reg <= {acceptance_code_0, acceptance_code_1, acceptance_code_2, acceptance_code_3};
+      8'h3C   : data_out_reg <= {acceptance_mask_0, acceptance_mask_1, acceptance_mask_2, acceptance_mask_3};
+      8'h40   : data_out_reg <= (extended_mode)? {8'h0, 4'h0, arbitration_lost_capture_mbox, 8'h0, 3'h0, arbitration_lost_capture[4:0]}: 32'h0;
+      8'h44   : data_out_reg <= (extended_mode)? {8'h0, 4'h0, error_capture_code_mbox, 8'h0, error_capture_code}: 32'h0;
+      8'h48   : data_out_reg <= {tx_err_cnt, rx_err_cnt, 8'h0, error_warning_limit};
+      8'h4C   : data_out_reg <= {11'h0, rxdatawin, 16'h0};
+      8'h70   : data_out_reg <= rxcode[rxdatawin];
+      8'h74   : data_out_reg <= rxmask[rxdatawin];
+      default : data_out_reg <= 32'h0;                                   // the rest is read as 0
+    endcase
+  end
+  else
+  begin
+    case(addr[3:2])
+      2'h0   : data_out_reg <= {txmsgdata[0*32+31], 2'h0, txmsgdata[0*32+28:0*32]};
+      2'h1   : data_out_reg <= {27'h0, txmsgdata[1*32+4:1*32]};
+      2'h2   : data_out_reg <= txmsgdata[2*32+31:2*32];
+      2'h3   : data_out_reg <= txmsgdata[3*32+31:3*32];
+    endcase
+  end
+end
+always @ ( * )
+begin
+  if(~addr[9])
+    data_out = data_out_reg;
+  else
+    case(addr[3:2])
+      2'h0   : data_out = {rxmsgdata[0*32+31], 2'h0, rxmsgdata[0*32+28:0*32]};
+      2'h1   : data_out = {27'h0, rxmsgdata[1*32+4:1*32]};
+      2'h2   : data_out = rxmsgdata[2*32+31:2*32];
+      2'h3   : data_out = rxmsgdata[3*32+31:3*32];
+    endcase
+end
+
+
+// Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
+assign data_overrun_irq_en  = data_overrun_irq_en_ext  ;
+assign error_warning_irq_en = error_warning_irq_en_ext ;
+assign transmit_irq_en      = transmit_irq_en_ext      ;
+assign receive_irq_en       = receive_irq_en_ext       ;
+
+
+reg transmit_cancel_irq;
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    transmit_cancel_irq <= 1'b0;
+  else if (we_txcancel)
+    transmit_cancel_irq <=#Tp 1'b0;
+  else if (|transmit_cancel & transmit_cancel_irq_en)
+    transmit_cancel_irq <=#Tp 1'b1;
+//  else if (reset_mode)
+  else
+    transmit_cancel_irq <=#Tp 1'b0;
+end
+
+
+reg data_overrun_irq;
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    data_overrun_irq <= 1'b0;
+  else if (read_rxovrwrite)
+    data_overrun_irq <=#Tp 1'b0;
+  else if (|(rxovrwrite & irq_rxen) & data_overrun_irq_en)
+    data_overrun_irq <=#Tp 1'b1;
+//  else if (reset_mode)
+  else
+    data_overrun_irq <=#Tp 1'b0;
+end
+
+
+reg transmit_irq;
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    transmit_irq <= 1'b0;
+//  else if (reset_mode || read_irq_reg)
+//    transmit_irq <=#Tp 1'b0;
+//  else if (transmit_buffer_status & (~transmit_buffer_status_q) & transmit_irq_en)
+//    transmit_irq <=#Tp 1'b1;  else if (reset_mode)
+  else if (we_txcmp)
+    transmit_irq <=#Tp 1'b0;
+  else if (|txcmp & transmit_irq_en)
+    transmit_irq <=#Tp 1'b1;
+  else
+    transmit_irq <=#Tp 1'b0;
+end
+
+
+reg receive_irq;
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    receive_irq <= 1'b0;
+  else if (we_rxcmp)
+    receive_irq <=#Tp 1'b0;
+  else if (|(rxcmp & irq_rxen) & receive_irq_en)
+    receive_irq <=#Tp 1'b1;
+//  else if (reset_mode)
+  else
+    receive_irq <=#Tp 1'b0;
+end
+
+
+reg error_irq;
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    error_irq <= 1'b0;
+  else if (((error_status ^ error_status_q) | (node_bus_off ^ node_bus_off_q)) & error_warning_irq_en)
+    error_irq <=#Tp 1'b1;
+  else if (read_irq_reg)
+    error_irq <=#Tp 1'b0;
+end
+
+
+reg bus_error_irq;
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    bus_error_irq <= 1'b0;
+  else if (set_bus_error_irq & bus_error_irq_en)
+    bus_error_irq <=#Tp 1'b1;
+  else if (reset_mode || read_irq_reg)
+    bus_error_irq <=#Tp 1'b0;
+end
+
+
+reg arbitration_lost_irq;
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    arbitration_lost_irq <= 1'b0;
+  else if (set_arbitration_lost_irq & arbitration_lost_irq_en)
+    arbitration_lost_irq <=#Tp 1'b1;
+  else if (reset_mode || read_irq_reg)
+    arbitration_lost_irq <=#Tp 1'b0;
+end
+
+
+
+reg error_passive_irq;
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    error_passive_irq <= 1'b0;
+  else if ((node_error_passive & (~node_error_passive_q) | (~node_error_passive) & node_error_passive_q & node_error_active) & error_passive_irq_en)
+    error_passive_irq <=#Tp 1'b1;
+  else if (reset_mode || read_irq_reg)
+    error_passive_irq <=#Tp 1'b0;
+end
+
+
+
+assign irq_reg = {bus_error_irq, arbitration_lost_irq, error_passive_irq, transmit_cancel_irq, data_overrun_irq, error_irq, transmit_irq, receive_irq};
+
+assign irq = data_overrun_irq | transmit_irq | receive_irq | error_irq | bus_error_irq | arbitration_lost_irq | error_passive_irq | transmit_cancel_irq;
+
+wire irq_clr = we_txcancel | read_rxovrwrite | we_txcmp | we_rxcmp;
+
+always @ (posedge clk or posedge rst)
+begin
+  if (rst)
+    irq_n <= 1'b1;
+  else if (read_irq_reg || release_buffer || irq_clr)
+    irq_n <=#Tp 1'b1;
+  else if (irq)
+    irq_n <=#Tp 1'b0;
+end
+
+
+
+endmodule
+
Index: /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_rxmboxacf.v
===================================================================
--- /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_rxmboxacf.v	(revision 295)
+++ /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_rxmboxacf.v	(revision 295)
@@ -0,0 +1,422 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  can_rxmboxacf.v                                             ////
+////                                                              ////
+////                                                              ////
+////  This file is part of the CAN Protocol Controller            ////
+////                                                              ////
+////                                                              ////
+////  Author(s):                                                  ////
+////       Center for Embedded Computing Systems                  ////
+////  Graduate School of Information Science, Nagoya Univ., JAPAN ////
+////                                                              ////
+////                                                              ////
+////  All additional information is available in the README.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2011-2013 Authors                              ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//// The CAN protocol is developed by Robert Bosch GmbH and       ////
+//// protected by patents. Anybody who wants to implement this    ////
+//// CAN IP core on silicon has to obtain a CAN protocol license  ////
+//// from Bosch.                                                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "can_defines.v"
+
+module can_rxmboxacf(
+  clk,
+  rst,
+  sample_point,
+
+  rxwait,
+  rxcmp,
+
+  reset_mode,
+  acceptance_filter_mode,
+  extended_mode,
+
+  rxmask,
+  rxcode,
+
+  rxdatawin,
+
+  rx_dt,
+  rx_we,
+
+  rxmsgdata,
+  rx_we_ff 
+//  input  wire clk,
+//  input  wire rst,
+//  input  wire sample_point,
+//
+//  input  wire [31:0] rxwait,
+//  input  wire [31:0] rxcmp,
+//
+//  input  wire reset_mode,
+//  input  wire acceptance_filter_mode,
+//  input  wire extended_mode,
+//
+//  input  wire [1023:0] rxmask,
+//  input  wire [1023:0] rxcode,
+//
+//  input  wire [   4:0] rxdatawin,
+//
+//  input  wire [ 127:0] rx_dt,
+//  input                rx_we,
+//
+//  output reg  [ 127:0] rxmsgdata,
+//  output wire [  31:0] rx_we_ff 
+);
+
+parameter Tp = 1;
+parameter TXMBOX_DEPTH = 1; /* 1(Min=2) - 4(Max=16) */
+parameter RXMBOX_DEPTH = 1; /* 1(Min=2) - 5(Max=32) */
+localparam TXMBOX_BITS = (TXMBOX_DEPTH > 4) ? 16 : (2**TXMBOX_DEPTH);
+localparam RXMBOX_BITS = (RXMBOX_DEPTH > 5) ? 32 :(2**RXMBOX_DEPTH);
+
+input  wire clk;
+input  wire rst;
+input  wire sample_point;
+
+input  wire [RXMBOX_BITS-1:0] rxwait;
+input  wire [RXMBOX_BITS-1:0] rxcmp;
+
+input  wire reset_mode;
+input  wire acceptance_filter_mode;
+input  wire extended_mode;
+
+//input  wire [RXMBOX_BITS*32-1:0] rxmask;
+//input  wire [RXMBOX_BITS*32-1:0] rxcode;
+input  wire [1023:0] rxmask;
+input  wire [1023:0] rxcode;
+
+input  wire [RXMBOX_DEPTH-1:0] rxdatawin;
+//input  wire [   4:0] rxdatawin;
+
+input  wire [ 127:0] rx_dt;
+input                rx_we;
+
+output reg  [ 127:0] rxmsgdata;
+//output wire [31:0] rx_we_ff;
+output wire [RXMBOX_BITS-1:0] rx_we_ff;
+
+wire id_ok;
+reg [RXMBOX_BITS-1:0] rx_we_on,rx_we_on_q;
+//reg [31:0] rx_we_on,rx_we_on_q;
+wire [RXMBOX_BITS-1:0] rx_we_off;
+//wire [31:0] rx_we_off;
+reg [2:0] cnt;
+reg [RXMBOX_BITS-1:0] rx_en;
+//reg [31:0] rx_en;
+reg [31:0] rxcode_in;
+reg [31:0] rxmask_in;
+reg timovr;
+reg [RXMBOX_DEPTH-1:0] rmbox_cnt;
+//reg [4:0] rmbox_cnt;
+wire [28:0] id;
+
+always @ (posedge clk or posedge rst)
+begin
+  if(rst)              rmbox_cnt <= {(RXMBOX_DEPTH){1'h0}};
+  else if(rx_we)       rmbox_cnt <=#Tp 1'b1;
+  else if(~|rmbox_cnt) rmbox_cnt <=#Tp rmbox_cnt;
+  else                 rmbox_cnt <=#Tp rmbox_cnt + 1'b1;
+//  if(rst)              rmbox_cnt <= 5'h0;
+//  else if(rx_we)       rmbox_cnt <=#Tp 5'h1;
+//  else if(~|rmbox_cnt) rmbox_cnt <=#Tp rmbox_cnt;
+//  else                 rmbox_cnt <=#Tp rmbox_cnt+ 5'h1;
+end
+
+wire no_byte0 = rx_dt[1*32+4] | (rx_dt[1*32+3:1*32]<4'h1); //rtr1 | (data_len<4'h1);
+wire no_byte1 = rx_dt[1*32+4] | (rx_dt[1*32+3:1*32]<4'h2); //rtr1 | (data_len<4'h2);
+assign id     = (rx_dt[0*32+31])? rx_dt[0*32+28:0*32]: {18'h0,rx_dt[0*32+28:0*32+18]};
+
+always @ (*) begin
+       if (rmbox_cnt ==  0) begin rxcode_in = rxcode[ 0*32+31: 0*32]; rxmask_in = rxmask[ 0*32+31: 0*32]; end
+  else if (rmbox_cnt ==  1) begin rxcode_in = rxcode[ 1*32+31: 1*32]; rxmask_in = rxmask[ 1*32+31: 1*32]; end
+  else if (rmbox_cnt ==  2) begin rxcode_in = rxcode[ 2*32+31: 2*32]; rxmask_in = rxmask[ 2*32+31: 2*32]; end
+  else if (rmbox_cnt ==  3) begin rxcode_in = rxcode[ 3*32+31: 3*32]; rxmask_in = rxmask[ 3*32+31: 3*32]; end
+  else if (rmbox_cnt ==  4) begin rxcode_in = rxcode[ 4*32+31: 4*32]; rxmask_in = rxmask[ 4*32+31: 4*32]; end
+  else if (rmbox_cnt ==  5) begin rxcode_in = rxcode[ 5*32+31: 5*32]; rxmask_in = rxmask[ 5*32+31: 5*32]; end
+  else if (rmbox_cnt ==  6) begin rxcode_in = rxcode[ 6*32+31: 6*32]; rxmask_in = rxmask[ 6*32+31: 6*32]; end
+  else if (rmbox_cnt ==  7) begin rxcode_in = rxcode[ 7*32+31: 7*32]; rxmask_in = rxmask[ 7*32+31: 7*32]; end
+  else if (rmbox_cnt ==  8) begin rxcode_in = rxcode[ 8*32+31: 8*32]; rxmask_in = rxmask[ 8*32+31: 8*32]; end
+  else if (rmbox_cnt ==  9) begin rxcode_in = rxcode[ 9*32+31: 9*32]; rxmask_in = rxmask[ 9*32+31: 9*32]; end
+  else if (rmbox_cnt == 10) begin rxcode_in = rxcode[10*32+31:10*32]; rxmask_in = rxmask[10*32+31:10*32]; end
+  else if (rmbox_cnt == 11) begin rxcode_in = rxcode[11*32+31:11*32]; rxmask_in = rxmask[11*32+31:11*32]; end
+  else if (rmbox_cnt == 12) begin rxcode_in = rxcode[12*32+31:12*32]; rxmask_in = rxmask[12*32+31:12*32]; end
+  else if (rmbox_cnt == 13) begin rxcode_in = rxcode[13*32+31:13*32]; rxmask_in = rxmask[13*32+31:13*32]; end
+  else if (rmbox_cnt == 14) begin rxcode_in = rxcode[14*32+31:14*32]; rxmask_in = rxmask[14*32+31:14*32]; end
+  else if (rmbox_cnt == 15) begin rxcode_in = rxcode[15*32+31:15*32]; rxmask_in = rxmask[15*32+31:15*32]; end
+  else if (rmbox_cnt == 16) begin rxcode_in = rxcode[16*32+31:16*32]; rxmask_in = rxmask[16*32+31:16*32]; end
+  else if (rmbox_cnt == 17) begin rxcode_in = rxcode[17*32+31:17*32]; rxmask_in = rxmask[17*32+31:17*32]; end
+  else if (rmbox_cnt == 18) begin rxcode_in = rxcode[18*32+31:18*32]; rxmask_in = rxmask[18*32+31:18*32]; end
+  else if (rmbox_cnt == 19) begin rxcode_in = rxcode[19*32+31:19*32]; rxmask_in = rxmask[19*32+31:19*32]; end
+  else if (rmbox_cnt == 20) begin rxcode_in = rxcode[20*32+31:20*32]; rxmask_in = rxmask[20*32+31:20*32]; end
+  else if (rmbox_cnt == 21) begin rxcode_in = rxcode[21*32+31:21*32]; rxmask_in = rxmask[21*32+31:21*32]; end
+  else if (rmbox_cnt == 22) begin rxcode_in = rxcode[22*32+31:22*32]; rxmask_in = rxmask[22*32+31:22*32]; end
+  else if (rmbox_cnt == 23) begin rxcode_in = rxcode[23*32+31:23*32]; rxmask_in = rxmask[23*32+31:23*32]; end
+  else if (rmbox_cnt == 24) begin rxcode_in = rxcode[24*32+31:24*32]; rxmask_in = rxmask[24*32+31:24*32]; end
+  else if (rmbox_cnt == 25) begin rxcode_in = rxcode[25*32+31:25*32]; rxmask_in = rxmask[25*32+31:25*32]; end
+  else if (rmbox_cnt == 26) begin rxcode_in = rxcode[26*32+31:26*32]; rxmask_in = rxmask[26*32+31:26*32]; end
+  else if (rmbox_cnt == 27) begin rxcode_in = rxcode[27*32+31:27*32]; rxmask_in = rxmask[27*32+31:27*32]; end
+  else if (rmbox_cnt == 28) begin rxcode_in = rxcode[28*32+31:28*32]; rxmask_in = rxmask[28*32+31:28*32]; end
+  else if (rmbox_cnt == 29) begin rxcode_in = rxcode[29*32+31:29*32]; rxmask_in = rxmask[29*32+31:29*32]; end
+  else if (rmbox_cnt == 30) begin rxcode_in = rxcode[30*32+31:30*32]; rxmask_in = rxmask[30*32+31:30*32]; end
+  else if (rmbox_cnt == 31) begin rxcode_in = rxcode[31*32+31:31*32]; rxmask_in = rxmask[31*32+31:31*32]; end
+  else if (rmbox_cnt == 32) begin rxcode_in = rxcode[32*32+31:32*32]; rxmask_in = rxmask[32*32+31:32*32]; end
+end
+
+//always @ (*)
+//begin
+//  case(rmbox_cnt)
+//    5'h00: begin rxcode_in = rxcode[ 0*32+31: 0*32]; rxmask_in = rxmask[ 0*32+31: 0*32]; end
+//    5'h01: begin rxcode_in = rxcode[ 1*32+31: 1*32]; rxmask_in = rxmask[ 1*32+31: 1*32]; end
+//    5'h02: begin rxcode_in = rxcode[ 2*32+31: 2*32]; rxmask_in = rxmask[ 2*32+31: 2*32]; end
+//    5'h03: begin rxcode_in = rxcode[ 3*32+31: 3*32]; rxmask_in = rxmask[ 3*32+31: 3*32]; end
+//    5'h04: begin rxcode_in = rxcode[ 4*32+31: 4*32]; rxmask_in = rxmask[ 4*32+31: 4*32]; end
+//    5'h05: begin rxcode_in = rxcode[ 5*32+31: 5*32]; rxmask_in = rxmask[ 5*32+31: 5*32]; end
+//    5'h06: begin rxcode_in = rxcode[ 6*32+31: 6*32]; rxmask_in = rxmask[ 6*32+31: 6*32]; end
+//    5'h07: begin rxcode_in = rxcode[ 7*32+31: 7*32]; rxmask_in = rxmask[ 7*32+31: 7*32]; end
+//    5'h08: begin rxcode_in = rxcode[ 8*32+31: 8*32]; rxmask_in = rxmask[ 8*32+31: 8*32]; end
+//    5'h09: begin rxcode_in = rxcode[ 9*32+31: 9*32]; rxmask_in = rxmask[ 9*32+31: 9*32]; end
+//    5'h0A: begin rxcode_in = rxcode[10*32+31:10*32]; rxmask_in = rxmask[10*32+31:10*32]; end
+//    5'h0B: begin rxcode_in = rxcode[11*32+31:11*32]; rxmask_in = rxmask[11*32+31:11*32]; end
+//    5'h0C: begin rxcode_in = rxcode[12*32+31:12*32]; rxmask_in = rxmask[12*32+31:12*32]; end
+//    5'h0D: begin rxcode_in = rxcode[13*32+31:13*32]; rxmask_in = rxmask[13*32+31:13*32]; end
+//    5'h0E: begin rxcode_in = rxcode[14*32+31:14*32]; rxmask_in = rxmask[14*32+31:14*32]; end
+//    5'h0F: begin rxcode_in = rxcode[15*32+31:15*32]; rxmask_in = rxmask[15*32+31:15*32]; end
+//    5'h10: begin rxcode_in = rxcode[16*32+31:16*32]; rxmask_in = rxmask[16*32+31:16*32]; end
+//    5'h11: begin rxcode_in = rxcode[17*32+31:17*32]; rxmask_in = rxmask[17*32+31:17*32]; end
+//    5'h12: begin rxcode_in = rxcode[18*32+31:18*32]; rxmask_in = rxmask[18*32+31:18*32]; end
+//    5'h13: begin rxcode_in = rxcode[19*32+31:19*32]; rxmask_in = rxmask[19*32+31:19*32]; end
+//    5'h14: begin rxcode_in = rxcode[20*32+31:20*32]; rxmask_in = rxmask[20*32+31:20*32]; end
+//    5'h15: begin rxcode_in = rxcode[21*32+31:21*32]; rxmask_in = rxmask[21*32+31:21*32]; end
+//    5'h16: begin rxcode_in = rxcode[22*32+31:22*32]; rxmask_in = rxmask[22*32+31:22*32]; end
+//    5'h17: begin rxcode_in = rxcode[23*32+31:23*32]; rxmask_in = rxmask[23*32+31:23*32]; end
+//    5'h18: begin rxcode_in = rxcode[24*32+31:24*32]; rxmask_in = rxmask[24*32+31:24*32]; end
+//    5'h19: begin rxcode_in = rxcode[25*32+31:25*32]; rxmask_in = rxmask[25*32+31:25*32]; end
+//    5'h1A: begin rxcode_in = rxcode[26*32+31:26*32]; rxmask_in = rxmask[26*32+31:26*32]; end
+//    5'h1B: begin rxcode_in = rxcode[27*32+31:27*32]; rxmask_in = rxmask[27*32+31:27*32]; end
+//    5'h1C: begin rxcode_in = rxcode[28*32+31:28*32]; rxmask_in = rxmask[28*32+31:28*32]; end
+//    5'h1D: begin rxcode_in = rxcode[29*32+31:29*32]; rxmask_in = rxmask[29*32+31:29*32]; end
+//    5'h1E: begin rxcode_in = rxcode[30*32+31:30*32]; rxmask_in = rxmask[30*32+31:30*32]; end
+//    5'h1F: begin rxcode_in = rxcode[31*32+31:31*32]; rxmask_in = rxmask[31*32+31:31*32]; end
+//  endcase
+//end
+
+
+can_acf i_can_acf
+(
+  .clk(clk),
+  .rst(rst),
+  
+  .id(id),
+
+  /* Mode register */
+  .reset_mode(1'h0),
+  .acceptance_filter_mode(acceptance_filter_mode),
+
+  // Clock Divider register
+  .extended_mode(extended_mode),
+
+  /* This section is for BASIC and EXTENDED mode */
+  /* Acceptance code register */
+  .acceptance_code_0(rxcode_in[3*8+7:3*8]),
+
+  /* Acceptance mask register */
+  .acceptance_mask_0(rxmask_in[3*8+7:3*8]),
+  /* End: This section is for BASIC and EXTENDED mode */
+
+  /* This section is for EXTENDED mode */
+  /* Acceptance code register */
+  .acceptance_code_1(rxcode_in[2*8+7:2*8]),
+  .acceptance_code_2(rxcode_in[1*8+7:1*8]),
+  .acceptance_code_3(rxcode_in[0*8+7:0*8]),
+
+  /* Acceptance mask register */
+  .acceptance_mask_1(rxmask_in[2*8+7:2*8]),
+  .acceptance_mask_2(rxmask_in[1*8+7:1*8]),
+  .acceptance_mask_3(rxmask_in[0*8+7:0*8]),
+  /* End: This section is for EXTENDED mode */
+
+  .go_rx_crc_lim(1'h1),
+  .go_rx_inter(1'h0),
+  .go_error_frame(1'h0),
+
+  .data0(rx_dt[2*32+0*8+7:2*32+0*8]),
+  .data1(rx_dt[2*32+1*8+7:2*32+1*8]),
+  .rtr1(rx_dt[1*32+4]),
+  .rtr2(rx_dt[1*32+4]),
+  .ide(rx_dt[0*32+31]),
+  .no_byte0(no_byte0),
+  .no_byte1(no_byte1),
+
+  .id_ok(id_ok)
+
+);
+
+generate
+  genvar i;
+
+  for (i=0; i<RXMBOX_BITS; i=i+1) begin :msgbox_afc
+//  for (i=0; i<32; i=i+1) begin :msgbox_afc
+
+    assign rx_we_off[i] = rx_we_on[i] & (timovr | ~rxcmp[i]| (rxcmp[i] & ~rxwait[i]));
+
+    if(i==0)
+    begin
+      always @ (posedge clk or posedge rst)
+      begin
+        if(rst)                   rx_we_on[i] <= 1'h0;
+        else if(id_ok & rx_en[i]) rx_we_on[i] <=#Tp 1'h1;
+        else if(rx_we_off[i])     rx_we_on[i] <=#Tp 1'h0;
+      end
+    end
+    else
+    begin
+      always @ (posedge clk or posedge rst)
+      begin
+        if(rst)                   rx_we_on[i] <= 1'h0;
+        else if(id_ok & rx_en[i]) rx_we_on[i] <=#Tp 1'h1;
+        else if(rx_we_off[i])     rx_we_on[i] <=#Tp (|rx_we_off[i-1:0])? rx_we_on[i]: 1'h0;
+      end
+    end
+
+  end //for
+
+endgenerate
+
+reg [127:0] rx_dt_ff;
+always @ (posedge clk)
+begin
+  rx_dt_ff <=#Tp (rx_we)? rx_dt: rx_dt_ff;
+  rx_en <=#Tp {rx_en[RXMBOX_BITS-2:0],rx_we};
+//  rx_en <=#Tp {rx_en[30:0],rx_we};
+  rx_we_on_q <=#Tp rx_we_on;
+end
+
+always @ (posedge clk or posedge rst)
+begin
+  if(rst)               cnt <= 3'h0;
+  else if(rx_en[0])     cnt <=#Tp 3'h1;
+  else if(cnt == 0)     cnt <=#Tp 3'h0;
+  else if(~|rx_we_on)   cnt <=#Tp 3'h0;
+  else if(sample_point) cnt <=#Tp cnt+3'h1;
+end
+
+assign rx_we_ff = (reset_mode)? {(RXMBOX_BITS-1){1'h0}}: ~rx_we_on & rx_we_on_q;
+//assign rx_we_ff = (reset_mode)? 32'h0: ~rx_we_on & rx_we_on_q;
+
+
+always @ (posedge clk or posedge rst)
+begin
+  if(rst)                       timovr <= 1'h0;
+  else if(rx_we)                timovr <=#Tp 1'h0;
+  else if(~|cnt & sample_point) timovr <=#Tp 1'h1;
+end
+
+reg [127:0] rxdata [0:RXMBOX_BITS-1];
+//reg [127:0] rxdata [0:31];
+reg [4:0] waddr;
+
+function [4:0] match_lower_number;
+  input [RXMBOX_BITS-1:0] x;
+  reg [7:0] i;
+begin
+   match_lower_number = 0;
+   for (i=0; i<RXMBOX_BITS; i=i+1) begin
+      if (x[i] && match_lower_number == 0) begin
+         match_lower_number = i;
+      end
+   end
+end
+endfunction
+
+always @ (*)
+begin
+  waddr = match_lower_number(rx_we_ff);
+end
+
+//always @ (*)
+//begin
+//       if(rx_we_ff[00]) waddr = 5'h00;
+//  else if(rx_we_ff[01]) waddr = 5'h01;
+//  else if(rx_we_ff[02]) waddr = 5'h02;
+//  else if(rx_we_ff[03]) waddr = 5'h03;
+//  else if(rx_we_ff[04]) waddr = 5'h04;
+//  else if(rx_we_ff[05]) waddr = 5'h05;
+//  else if(rx_we_ff[06]) waddr = 5'h06;
+//  else if(rx_we_ff[07]) waddr = 5'h07;
+//  else if(rx_we_ff[08]) waddr = 5'h08;
+//  else if(rx_we_ff[09]) waddr = 5'h09;
+//  else if(rx_we_ff[10]) waddr = 5'h0A;
+//  else if(rx_we_ff[11]) waddr = 5'h0B;
+//  else if(rx_we_ff[12]) waddr = 5'h0C;
+//  else if(rx_we_ff[13]) waddr = 5'h0D;
+//  else if(rx_we_ff[14]) waddr = 5'h0E;
+//  else if(rx_we_ff[15]) waddr = 5'h0F;
+//  else if(rx_we_ff[16]) waddr = 5'h10;
+//  else if(rx_we_ff[17]) waddr = 5'h11;
+//  else if(rx_we_ff[18]) waddr = 5'h12;
+//  else if(rx_we_ff[19]) waddr = 5'h13;
+//  else if(rx_we_ff[20]) waddr = 5'h14;
+//  else if(rx_we_ff[21]) waddr = 5'h15;
+//  else if(rx_we_ff[22]) waddr = 5'h16;
+//  else if(rx_we_ff[23]) waddr = 5'h17;
+//  else if(rx_we_ff[24]) waddr = 5'h18;
+//  else if(rx_we_ff[25]) waddr = 5'h19;
+//  else if(rx_we_ff[26]) waddr = 5'h1A;
+//  else if(rx_we_ff[27]) waddr = 5'h1B;
+//  else if(rx_we_ff[28]) waddr = 5'h1C;
+//  else if(rx_we_ff[29]) waddr = 5'h1D;
+//  else if(rx_we_ff[30]) waddr = 5'h1E;
+//  else if(rx_we_ff[31]) waddr = 5'h1F;
+//  else                  waddr = 5'h00;
+//end
+
+
+integer j;
+initial begin
+//  for(j=0;j<32;j=j+1) rxdata[j]=0;
+  for(j=0;j<RXMBOX_BITS;j=j+1) rxdata[j]=0;
+end
+
+
+always @ (posedge clk)
+begin
+  if(|rx_we_ff) rxdata[waddr] <=#Tp rx_dt_ff;
+  rxmsgdata <=#Tp rxdata[rxdatawin];
+end
+
+
+endmodule
Index: /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_top.v
===================================================================
--- /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_top.v	(revision 295)
+++ /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/canc/hdl/can_top.v	(revision 295)
@@ -0,0 +1,923 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  can_top.v                                                   ////
+////                                                              ////
+////                                                              ////
+////  This file is part of the CAN Protocol Controller            ////
+////  http://www.opencores.org/projects/can/                      ////
+////                                                              ////
+////                                                              ////
+////  Author(s):                                                  ////
+////       Igor Mohor                                             ////
+////       igorm@opencores.org                                    ////
+////                                                              ////
+////                                                              ////
+////  All additional information is available in the README.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002, 2003, 2004 Authors                       ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//// The CAN protocol is developed by Robert Bosch GmbH and       ////
+//// protected by patents. Anybody who wants to implement this    ////
+//// CAN IP core on silicon has to obtain a CAN protocol license  ////
+//// from Bosch.                                                  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: can_top.v,v $
+// Revision 1.48  2004/10/25 11:44:47  igorm
+// Interrupt is always cleared for one clock after the irq register is read.
+// This fixes problems when CPU is using IRQs that are edge triggered.
+//
+// Revision 1.47  2004/02/08 14:53:54  mohor
+// Header changed. Address latched to posedge. bus_off_on signal added.
+//
+// Revision 1.46  2003/10/17 05:55:20  markom
+// mbist signals updated according to newest convention
+//
+// Revision 1.45  2003/09/30 00:55:13  mohor
+// Error counters fixed to be compatible with Bosch VHDL reference model.
+// Small synchronization changes.
+//
+// Revision 1.44  2003/09/25 18:55:49  mohor
+// Synchronization changed, error counters fixed.
+//
+// Revision 1.43  2003/08/20 09:57:39  mohor
+// Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
+// to be joined together on higher level.
+//
+// Revision 1.42  2003/07/16 15:11:28  mohor
+// Fixed according to the linter.
+//
+// Revision 1.41  2003/07/10 15:32:27  mohor
+// Unused signal removed.
+//
+// Revision 1.40  2003/07/10 01:59:04  tadejm
+// Synchronization fixed. In some strange cases it didn't work according to
+// the VHDL reference model.
+//
+// Revision 1.39  2003/07/07 11:21:37  mohor
+// Little fixes (to fix warnings).
+//
+// Revision 1.38  2003/07/03 09:32:20  mohor
+// Synchronization changed.
+//
+// Revision 1.37  2003/06/27 20:56:15  simons
+// Virtual silicon ram instances added.
+//
+// Revision 1.36  2003/06/17 14:30:30  mohor
+// "chip select" signal cs_can_i is used only when not using WISHBONE
+// interface.
+//
+// Revision 1.35  2003/06/16 13:57:58  mohor
+// tx_point generated one clk earlier. rx_i registered. Data corrected when
+// using extended mode.
+//
+// Revision 1.34  2003/06/13 15:02:24  mohor
+// Synchronization is also needed when transmitting a message.
+//
+// Revision 1.33  2003/06/11 14:21:35  mohor
+// When switching to tx, sync stage is overjumped.
+//
+// Revision 1.32  2003/06/09 11:32:36  mohor
+// Ports added for the CAN_BIST.
+//
+// Revision 1.31  2003/03/26 11:19:46  mohor
+// CAN interrupt is active low.
+//
+// Revision 1.30  2003/03/20 17:01:17  mohor
+// unix.
+//
+// Revision 1.28  2003/03/14 19:36:48  mohor
+// can_cs signal used for generation of the cs.
+//
+// Revision 1.27  2003/03/12 05:56:33  mohor
+// Bidirectional port_0_i changed to port_0_io.
+// input cs_can changed to cs_can_i.
+//
+// Revision 1.26  2003/03/12 04:39:40  mohor
+// rd_i and wr_i are active high signals. If 8051 is connected, these two signals
+// need to be negated one level higher.
+//
+// Revision 1.25  2003/03/12 04:17:36  mohor
+// 8051 interface added (besides WISHBONE interface). Selection is made in
+// can_defines.v file.
+//
+// Revision 1.24  2003/03/10 17:24:40  mohor
+// wire declaration added.
+//
+// Revision 1.23  2003/03/05 15:33:13  mohor
+// tx_o is now tristated signal. tx_oen and tx_o combined together.
+//
+// Revision 1.22  2003/03/05 15:01:56  mohor
+// Top level signal names changed.
+//
+// Revision 1.21  2003/03/01 22:53:33  mohor
+// Actel APA ram supported.
+//
+// Revision 1.20  2003/02/19 15:09:02  mohor
+// Incomplete sensitivity list fixed.
+//
+// Revision 1.19  2003/02/19 15:04:14  mohor
+// Typo fixed.
+//
+// Revision 1.18  2003/02/19 14:44:03  mohor
+// CAN core finished. Host interface added. Registers finished.
+// Synchronization to the wishbone finished.
+//
+// Revision 1.17  2003/02/18 00:10:15  mohor
+// Most of the registers added. Registers "arbitration lost capture", "error code
+// capture" + few more still need to be added.
+//
+// Revision 1.16  2003/02/14 20:17:01  mohor
+// Several registers added. Not finished, yet.
+//
+// Revision 1.15  2003/02/12 14:25:30  mohor
+// abort_tx added.
+//
+// Revision 1.14  2003/02/11 00:56:06  mohor
+// Wishbone interface added.
+//
+// Revision 1.13  2003/02/09 18:40:29  mohor
+// Overload fixed. Hard synchronization also enabled at the last bit of
+// interframe.
+//
+// Revision 1.12  2003/02/09 02:24:33  mohor
+// Bosch license warning added. Error counters finished. Overload frames
+// still need to be fixed.
+//
+// Revision 1.11  2003/02/04 14:34:52  mohor
+// *** empty log message ***
+//
+// Revision 1.10  2003/01/31 01:13:38  mohor
+// backup.
+//
+// Revision 1.9  2003/01/15 13:16:48  mohor
+// When a frame with "remote request" is received, no data is stored to
+// fifo, just the frame information (identifier, ...). Data length that
+// is stored is the received data length and not the actual data length
+// that is stored to fifo.
+//
+// Revision 1.8  2003/01/14 17:25:09  mohor
+// Addresses corrected to decimal values (previously hex).
+//
+// Revision 1.7  2003/01/10 17:51:34  mohor
+// Temporary version (backup).
+//
+// Revision 1.6  2003/01/09 21:54:45  mohor
+// rx fifo added. Not 100 % verified, yet.
+//
+// Revision 1.5  2003/01/08 02:10:56  mohor
+// Acceptance filter added.
+//
+// Revision 1.4  2002/12/28 04:13:23  mohor
+// Backup version.
+//
+// Revision 1.3  2002/12/27 00:12:52  mohor
+// Header changed, testbench improved to send a frame (crc still missing).
+//
+// Revision 1.2  2002/12/26 16:00:34  mohor
+// Testbench define file added. Clock divider register added.
+//
+// Revision 1.1.1.1  2002/12/20 16:39:21  mohor
+// Initial
+//
+//
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+`include "can_defines.v"
+
+module can_top
+( 
+  `ifdef CAN_WISHBONE_IF
+    wb_clk_i,
+    wb_rst_i,
+    wb_dat_i,
+    wb_dat_o,
+    wb_cyc_i,
+    wb_stb_i,
+    wb_we_i,
+    wb_adr_i,
+    wb_ack_o,
+  `else  
+   `ifdef CAN_AVALON_IF
+     av_rst_i,
+     av_cs_i,
+     av_wr_i,
+     av_adr_i,
+     av_dat_i,
+     av_dat_o,
+   `else
+     rst_i,
+     ale_i,
+     rd_i,
+     wr_i,
+     port_0_io,
+     cs_can_i,
+   `endif
+  `endif
+  clk_i,
+  rx_i,
+  tx_o,
+  bus_off_on,
+  irq_on,
+  clkout_o
+
+  // Bist
+`ifdef CAN_BIST
+  ,
+  // debug chain signals
+  mbist_si_i,       // bist scan serial in
+  mbist_so_o,       // bist scan serial out
+  mbist_ctrl_i        // bist chain shift control
+`endif
+);
+
+parameter Tp = 1;
+parameter TXMBOX_DEPTH = 1; /* 2(Min=4) - 4(Max=16) */
+parameter RXMBOX_DEPTH = 4; /* 2(Min=4) - 5(Max=32) */
+
+
+`ifdef CAN_WISHBONE_IF
+  input        wb_clk_i;
+  input        wb_rst_i;
+  input [31:0] wb_dat_i;
+  output [31:0] wb_dat_o;
+  input        wb_cyc_i;
+  input        wb_stb_i;
+  input        wb_we_i;
+  input  [7:0] wb_adr_i;
+  output       wb_ack_o;
+
+  reg          wb_ack_o;
+  reg          cs_sync1;
+  reg          cs_sync2;
+  reg          cs_sync3;
+  
+  reg          cs_ack1;
+  reg          cs_ack2;
+  reg          cs_ack3;
+  reg          cs_sync_rst1;
+  reg          cs_sync_rst2;
+  wire         cs_can_i;
+`else
+ `ifdef CAN_AVALON_IF
+   input        av_rst_i;
+   input        av_cs_i;  
+   input        av_wr_i;
+   input  [31:0] av_dat_i;
+   output [31:0] av_dat_o;
+   input   [7:0] av_adr_i;
+  
+   wire         av_cs_i;
+ `else
+   input        rst_i;
+   input        ale_i;
+   input        rd_i;
+   input        wr_i;
+   inout [31:0] port_0_io;
+   input        cs_can_i;
+  
+   reg    [9:0] addr_latched;
+   reg          wr_i_q;
+   reg          rd_i_q;
+ `endif
+`endif
+
+input        clk_i;
+input        rx_i;
+output       tx_o;
+output       bus_off_on;
+output       irq_on;
+output       clkout_o;
+
+// Bist
+`ifdef CAN_BIST
+input   mbist_si_i;       // bist scan serial in
+output  mbist_so_o;       // bist scan serial out
+input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
+`endif
+
+reg          data_out_fifo_selected;
+
+
+wire   [7:0] data_out_fifo;
+wire   [31:0] data_out_regs;
+
+
+/* Mode register */
+wire         reset_mode;
+wire         listen_only_mode;
+wire         acceptance_filter_mode;
+wire         self_test_mode;
+
+/* Command register */
+wire         release_buffer;
+wire         tx_request;
+wire         abort_tx;
+wire         self_rx_request;
+wire         single_shot_transmission;
+wire         tx_state;
+wire         tx_state_q;
+wire         overload_request;
+wire         overload_frame;
+
+
+/* Arbitration Lost Capture Register */
+wire         read_arbitration_lost_capture_reg;
+
+/* Error Code Capture Register */
+wire         read_error_code_capture_reg;
+wire   [7:0] error_capture_code;
+
+/* Bus Timing 0 register */
+wire   [5:0] baud_r_presc;
+wire   [1:0] sync_jump_width;
+
+/* Bus Timing 1 register */
+wire   [3:0] time_segment1;
+wire   [2:0] time_segment2;
+wire         triple_sampling;
+
+/* Error Warning Limit register */
+wire   [7:0] error_warning_limit;
+
+/* Rx Error Counter register */
+wire         we_rx_err_cnt;
+
+/* Tx Error Counter register */
+wire         we_tx_err_cnt;
+
+/* Clock Divider register */
+wire         extended_mode;
+
+/* This section is for BASIC and EXTENDED mode */
+/* Acceptance code register */
+wire   [7:0] acceptance_code_0;
+
+/* Acceptance mask register */
+wire   [7:0] acceptance_mask_0;
+/* End: This section is for BASIC and EXTENDED mode */
+
+
+/* This section is for EXTENDED mode */
+/* Acceptance code register */
+wire   [7:0] acceptance_code_1;
+wire   [7:0] acceptance_code_2;
+wire   [7:0] acceptance_code_3;
+
+/* Acceptance mask register */
+wire   [7:0] acceptance_mask_1;
+wire   [7:0] acceptance_mask_2;
+wire   [7:0] acceptance_mask_3;
+/* End: This section is for EXTENDED mode */
+
+/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
+wire   [7:0] tx_data_0;
+wire   [7:0] tx_data_1;
+wire   [7:0] tx_data_2;
+wire   [7:0] tx_data_3;
+wire   [7:0] tx_data_4;
+wire   [7:0] tx_data_5;
+wire   [7:0] tx_data_6;
+wire   [7:0] tx_data_7;
+wire   [7:0] tx_data_8;
+wire   [7:0] tx_data_9;
+wire   [7:0] tx_data_10;
+wire   [7:0] tx_data_11;
+wire   [7:0] tx_data_12;
+/* End: Tx data registers */
+wire [127:0] rx_dt;
+wire         rx_we;
+
+wire         cs;
+
+/* Output signals from can_btl module */
+wire         sample_point;
+wire         sampled_bit;
+wire         sampled_bit_q;
+wire         tx_point;
+wire         hard_sync;
+
+/* output from can_bsp module */
+wire         rx_idle;
+wire         transmitting;
+wire         transmitter;
+wire         go_rx_inter;
+wire         not_first_bit_of_inter;
+wire         set_reset_mode;
+wire         node_bus_off;
+wire         error_status;
+wire   [7:0] rx_err_cnt;
+wire   [7:0] tx_err_cnt;
+wire         rx_err_cnt_dummy;  // The MSB is not displayed. It is just used for easier calculation (no counter overflow).
+wire         tx_err_cnt_dummy;  // The MSB is not displayed. It is just used for easier calculation (no counter overflow).
+wire         transmit_status;
+wire         receive_status;
+wire         tx_successful;
+wire         need_to_tx;
+wire         overrun;
+wire         info_empty;
+wire         set_bus_error_irq;
+wire         set_arbitration_lost_irq;
+wire   [4:0] arbitration_lost_capture;
+wire         node_error_passive;
+wire         node_error_active;
+wire   [6:0] rx_message_counter;
+wire         tx_next;
+
+wire         go_overload_frame;
+wire         go_error_frame;
+wire         go_tx;
+wire         send_ack;
+
+wire         rst;
+wire         we;
+wire   [9:0] addr;
+wire  [31:0] data_in;
+wire  [31:0] data_out;
+reg          rx_sync_tmp;
+reg          rx_sync;
+
+/* Connecting can_registers module */
+//can_registers i_can_registers
+can_registers #(.TXMBOX_DEPTH(TXMBOX_DEPTH), .RXMBOX_DEPTH(RXMBOX_DEPTH)) i_can_registers
+
+( 
+  .clk(clk_i),
+  .rst(rst),
+  .cs(cs),
+  .we(we),
+  .addr(addr),
+  .data_in(data_in),
+  .data_out(data_out),
+  .irq_n(irq_on),
+
+  .sample_point(sample_point),
+  .transmitting(transmitting),
+  .set_reset_mode(set_reset_mode),
+  .node_bus_off(node_bus_off),
+  .error_status(error_status),
+  .rx_err_cnt(rx_err_cnt),
+  .tx_err_cnt(tx_err_cnt),
+  .transmit_status(transmit_status),
+  .receive_status(receive_status),
+  .tx_successful(tx_successful),
+  .need_to_tx(need_to_tx),
+  .overrun(overrun),
+  .info_empty(info_empty),
+  .set_bus_error_irq(set_bus_error_irq),
+  .set_arbitration_lost_irq(set_arbitration_lost_irq),
+  .arbitration_lost_capture(arbitration_lost_capture),
+  .node_error_passive(node_error_passive),
+  .node_error_active(node_error_active),
+  .rx_message_counter(rx_message_counter),
+
+
+  /* Mode register */
+  .reset_mode(reset_mode),
+  .listen_only_mode(listen_only_mode),
+  .acceptance_filter_mode(acceptance_filter_mode),
+  .self_test_mode(self_test_mode),
+
+  /* Command register */
+  .clear_data_overrun(),
+  .release_buffer(release_buffer),
+  .abort_tx(abort_tx),
+  .tx_request(tx_request),
+  .self_rx_request(self_rx_request),
+  .single_shot_transmission(single_shot_transmission),
+  .tx_state(tx_state),
+  .tx_state_q(tx_state_q),
+  .overload_request(overload_request),
+  .overload_frame(overload_frame),
+
+  /* Arbitration Lost Capture Register */
+  .read_arbitration_lost_capture_reg(read_arbitration_lost_capture_reg),
+
+  /* Error Code Capture Register */
+  .read_error_code_capture_reg(read_error_code_capture_reg),
+  .error_capture_code(error_capture_code),
+
+  /* Bus Timing 0 register */
+  .baud_r_presc(baud_r_presc),
+  .sync_jump_width(sync_jump_width),
+
+  /* Bus Timing 1 register */
+  .time_segment1(time_segment1),
+  .time_segment2(time_segment2),
+  .triple_sampling(triple_sampling),
+
+  /* Error Warning Limit register */
+  .error_warning_limit(error_warning_limit),
+
+  /* Rx Error Counter register */
+  .we_rx_err_cnt(we_rx_err_cnt),
+
+  /* Tx Error Counter register */
+  .we_tx_err_cnt(we_tx_err_cnt),
+
+  /* Clock Divider register */
+  .extended_mode(extended_mode),
+  .clkout(clkout_o),
+  
+  /* This section is for BASIC and EXTENDED mode */
+  /* Acceptance code register */
+  .acceptance_code_0(acceptance_code_0),
+
+  /* Acceptance mask register */
+  .acceptance_mask_0(acceptance_mask_0),
+  /* End: This section is for BASIC and EXTENDED mode */
+  
+  /* This section is for EXTENDED mode */
+  /* Acceptance code register */
+  .acceptance_code_1(acceptance_code_1),
+  .acceptance_code_2(acceptance_code_2),
+  .acceptance_code_3(acceptance_code_3),
+
+  /* Acceptance mask register */
+  .acceptance_mask_1(acceptance_mask_1),
+  .acceptance_mask_2(acceptance_mask_2),
+  .acceptance_mask_3(acceptance_mask_3),
+  /* End: This section is for EXTENDED mode */
+
+  .rx_dt(rx_dt),
+  .rx_we(rx_we),
+  /* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
+  .tx_data_0(tx_data_0),
+  .tx_data_1(tx_data_1),
+  .tx_data_2(tx_data_2),
+  .tx_data_3(tx_data_3),
+  .tx_data_4(tx_data_4),
+  .tx_data_5(tx_data_5),
+  .tx_data_6(tx_data_6),
+  .tx_data_7(tx_data_7),
+  .tx_data_8(tx_data_8),
+  .tx_data_9(tx_data_9),
+  .tx_data_10(tx_data_10),
+  .tx_data_11(tx_data_11),
+  .tx_data_12(tx_data_12)
+  /* End: Tx data registers */
+);
+
+
+
+
+/* Connecting can_btl module */
+can_btl i_can_btl
+( 
+  .clk(clk_i),
+  .rst(rst),
+  .rx(rx_sync), 
+  .tx(tx_o),
+
+  /* Bus Timing 0 register */
+  .baud_r_presc(baud_r_presc),
+  .sync_jump_width(sync_jump_width),
+
+  /* Bus Timing 1 register */
+  .time_segment1(time_segment1),
+  .time_segment2(time_segment2),
+  .triple_sampling(triple_sampling),
+
+  /* Output signals from this module */
+  .sample_point(sample_point),
+  .sampled_bit(sampled_bit),
+  .sampled_bit_q(sampled_bit_q),
+  .tx_point(tx_point),
+  .hard_sync(hard_sync),
+
+  
+  /* output from can_bsp module */
+  .rx_idle(rx_idle),
+  .rx_inter(rx_inter),
+  .transmitting(transmitting),
+  .transmitter(transmitter),
+  .go_rx_inter(go_rx_inter),
+  .tx_next(tx_next),
+
+  .go_overload_frame(go_overload_frame),
+  .go_error_frame(go_error_frame),
+  .go_tx(go_tx),
+  .send_ack(send_ack),
+  .node_error_passive(node_error_passive)
+  
+
+
+);
+
+
+
+can_bsp i_can_bsp
+(
+  .clk(clk_i),
+  .rst(rst),
+  
+  /* From btl module */
+  .sample_point(sample_point),
+  .sampled_bit(sampled_bit),
+  .sampled_bit_q(sampled_bit_q),
+  .tx_point(tx_point),
+  .hard_sync(hard_sync),
+
+  .addr(8'h0),
+  .data_in(data_in),
+  .data_out(data_out_fifo),
+  .fifo_selected(data_out_fifo_selected),
+
+  /* Mode register */
+  .reset_mode(reset_mode),
+  .listen_only_mode(listen_only_mode),
+  .acceptance_filter_mode(acceptance_filter_mode),
+  .self_test_mode(self_test_mode),
+  
+  /* Command register */
+  .release_buffer(release_buffer),
+  .tx_request(tx_request),
+  .abort_tx(abort_tx),
+  .self_rx_request(self_rx_request),
+  .single_shot_transmission(single_shot_transmission),
+  .tx_state(tx_state),
+  .tx_state_q(tx_state_q),
+  .overload_request(overload_request),
+  .overload_frame(overload_frame),
+
+  /* Arbitration Lost Capture Register */
+  .read_arbitration_lost_capture_reg(read_arbitration_lost_capture_reg),
+
+  /* Error Code Capture Register */
+  .read_error_code_capture_reg(read_error_code_capture_reg),
+  .error_capture_code(error_capture_code),
+
+  /* Error Warning Limit register */
+  .error_warning_limit(error_warning_limit),
+
+  /* Rx Error Counter register */
+  .we_rx_err_cnt(we_rx_err_cnt),
+
+  /* Tx Error Counter register */
+  .we_tx_err_cnt(we_tx_err_cnt),
+
+  /* Clock Divider register */
+  .extended_mode(extended_mode),
+
+  /* output from can_bsp module */
+  .rx_idle(rx_idle),
+  .transmitting(transmitting),
+  .transmitter(transmitter),
+  .go_rx_inter(go_rx_inter),
+  .not_first_bit_of_inter(not_first_bit_of_inter),
+  .rx_inter(rx_inter),
+  .set_reset_mode(set_reset_mode),
+  .node_bus_off(node_bus_off),
+  .error_status(error_status),
+  .rx_err_cnt({rx_err_cnt_dummy, rx_err_cnt[7:0]}),   // The MSB is not displayed. It is just used for easier calculation (no counter overflow).
+  .tx_err_cnt({tx_err_cnt_dummy, tx_err_cnt[7:0]}),   // The MSB is not displayed. It is just used for easier calculation (no counter overflow).
+  .transmit_status(transmit_status),
+  .receive_status(receive_status),
+  .tx_successful(tx_successful),
+  .need_to_tx(need_to_tx),
+  .overrun(overrun),
+  .info_empty(info_empty),
+  .set_bus_error_irq(set_bus_error_irq),
+  .set_arbitration_lost_irq(set_arbitration_lost_irq),
+  .arbitration_lost_capture(arbitration_lost_capture),
+  .node_error_passive(node_error_passive),
+  .node_error_active(node_error_active),
+  .rx_message_counter(rx_message_counter),
+  
+  /* This section is for BASIC and EXTENDED mode */
+  /* Acceptance code register */
+  .acceptance_code_0(acceptance_code_0),
+
+  /* Acceptance mask register */
+  .acceptance_mask_0(acceptance_mask_0),
+  /* End: This section is for BASIC and EXTENDED mode */
+  
+  /* This section is for EXTENDED mode */
+  /* Acceptance code register */
+  .acceptance_code_1(acceptance_code_1),
+  .acceptance_code_2(acceptance_code_2),
+  .acceptance_code_3(acceptance_code_3),
+
+  /* Acceptance mask register */
+  .acceptance_mask_1(acceptance_mask_1),
+  .acceptance_mask_2(acceptance_mask_2),
+  .acceptance_mask_3(acceptance_mask_3),
+  /* End: This section is for EXTENDED mode */
+
+  /* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
+  .tx_data_0(tx_data_0),
+  .tx_data_1(tx_data_1),
+  .tx_data_2(tx_data_2),
+  .tx_data_3(tx_data_3),
+  .tx_data_4(tx_data_4),
+  .tx_data_5(tx_data_5),
+  .tx_data_6(tx_data_6),
+  .tx_data_7(tx_data_7),
+  .tx_data_8(tx_data_8),
+  .tx_data_9(tx_data_9),
+  .tx_data_10(tx_data_10),
+  .tx_data_11(tx_data_11),
+  .tx_data_12(tx_data_12),
+  /* End: Tx data registers */
+  .rx_dt(rx_dt),
+  .rx_we(rx_we),
+  
+  /* Tx signal */
+  .tx(tx_o),
+  .tx_next(tx_next),
+  .bus_off_on(bus_off_on),
+
+  .go_overload_frame(go_overload_frame),
+  .go_error_frame(go_error_frame),
+  .go_tx(go_tx),
+  .send_ack(send_ack)
+
+
+`ifdef CAN_BIST
+  ,
+  /* BIST signals */
+  .mbist_si_i(mbist_si_i),
+  .mbist_so_o(mbist_so_o),
+  .mbist_ctrl_i(mbist_ctrl_i)
+`endif
+);
+
+assign extended_mode_o = extended_mode;
+
+// Multiplexing wb_dat_o from registers and rx fifo
+always @ (extended_mode or addr or reset_mode)
+begin
+  if (extended_mode & (~reset_mode) & ((addr >= 10'd16) && (addr <= 10'd28)) | (~extended_mode) & ((addr >= 10'd20) && (addr <= 10'd29)))
+    data_out_fifo_selected = 1'b1;
+  else
+    data_out_fifo_selected = 1'b0;
+end
+
+
+//always @ (posedge clk_i or posedge rst)
+//begin
+//  if (rst)
+//    begin
+//      data_out <= 0;
+//    end
+//  else if (cs & (~we))
+//    begin
+//      if (data_out_fifo_selected)
+//        data_out <=#Tp data_out_fifo;
+//      else
+//        data_out <=#Tp data_out_regs;
+//    end
+//end
+
+
+
+always @ (posedge clk_i or posedge rst)
+begin
+  if (rst)
+    begin
+      rx_sync_tmp <= 1'b1;
+      rx_sync     <= 1'b1;
+    end
+  else
+    begin
+      rx_sync_tmp <=#Tp rx_i;
+      rx_sync     <=#Tp rx_sync_tmp;
+    end
+end
+
+
+
+`ifdef CAN_WISHBONE_IF
+
+  assign cs_can_i = 1'b1;
+
+  // Combining wb_cyc_i and wb_stb_i signals to cs signal. Than synchronizing to clk_i clock domain. 
+  always @ (posedge clk_i or posedge rst)
+  begin
+    if (rst)
+      begin
+        cs_sync1     <= 1'b0;
+        cs_sync2     <= 1'b0;
+        cs_sync3     <= 1'b0;
+        cs_sync_rst1 <= 1'b0;
+        cs_sync_rst2 <= 1'b0;
+      end
+    else
+      begin
+        cs_sync1     <=#Tp wb_cyc_i & wb_stb_i & (~cs_sync_rst2) & cs_can_i;
+        cs_sync2     <=#Tp cs_sync1            & (~cs_sync_rst2);
+        cs_sync3     <=#Tp cs_sync2            & (~cs_sync_rst2);
+        cs_sync_rst1 <=#Tp cs_ack3;
+        cs_sync_rst2 <=#Tp cs_sync_rst1;
+      end
+  end
+  
+  
+  assign cs = cs_sync2 & (~cs_sync3);
+  
+  
+  always @ (posedge wb_clk_i)
+  begin
+    cs_ack1 <=#Tp cs_sync3;
+    cs_ack2 <=#Tp cs_ack1;
+    cs_ack3 <=#Tp cs_ack2;
+  end
+  
+  
+  
+  // Generating acknowledge signal
+  always @ (posedge wb_clk_i)
+  begin
+    wb_ack_o <=#Tp (cs_ack2 & (~cs_ack3));
+  end
+
+
+  assign rst      = wb_rst_i;
+  assign we       = wb_we_i;
+  assign addr     = wb_adr_i;
+  assign data_in  = wb_dat_i;
+  assign wb_dat_o = data_out;
+
+
+`else
+ `ifdef CAN_AVALON_IF
+
+   assign rst        = av_rst_i;
+   assign cs         = av_cs_i;
+   assign we         = av_wr_i;
+   assign addr       = {av_adr_i,2'h0};
+   assign data_in    = av_dat_i;
+   assign av_dat_o   = data_out;
+
+ `else
+
+   // Latching address
+   always @ (posedge clk_i or posedge rst)
+   begin
+     if (rst)
+       addr_latched <= 10'h0;
+     else if (ale_i)
+       addr_latched <=#Tp port_0_io;
+   end
+
+
+   // Generating delayed wr_i and rd_i signals
+   always @ (posedge clk_i or posedge rst)
+   begin
+     if (rst)
+       begin
+         wr_i_q <= 1'b0;
+         rd_i_q <= 1'b0;
+       end
+     else
+       begin
+         wr_i_q <=#Tp wr_i;
+         rd_i_q <=#Tp rd_i;
+       end
+   end
+
+
+   assign cs = ((wr_i & (~wr_i_q)) | (rd_i & (~rd_i_q))) & cs_can_i;
+
+
+   assign rst       = rst_i;
+   assign we        = wr_i;
+   assign addr      = addr_latched;
+   assign data_in   = port_0_io;
+   assign port_0_io = (cs_can_i & rd_i)? data_out : {4{8'hz}};
+
+ `endif 
+`endif
+
+
+endmodule
Index: /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/hw_sw.cof
===================================================================
--- /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/hw_sw.cof	(revision 295)
+++ /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/hw_sw.cof	(revision 295)
@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
+<cof>
+	<eprom_name>EPCS64</eprom_name>
+	<flash_loader_device>EP4CE22</flash_loader_device>
+	<output_filename>hw_sw.jic</output_filename>
+	<n_pages>0</n_pages>
+	<width>1</width>
+	<mode>7</mode>
+	<hex_block>
+		<hex_filename>hw_sw.hex</hex_filename>
+		<hex_addressing>absolute</hex_addressing>
+	</hex_block>
+	<version>5</version>
+	<create_cvp_file>0</create_cvp_file>
+	<options>
+		<map_file>1</map_file>
+	</options>
+</cof>
Index: /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/multi_pwm/multi_pwm.vhd
===================================================================
--- /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/multi_pwm/multi_pwm.vhd	(revision 295)
+++ /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/multi_pwm/multi_pwm.vhd	(revision 295)
@@ -0,0 +1,219 @@
+----------------------------------------------------------------------
+-- Copyright (c) 2009 Shinya Honda (honda@ertl.jp)
+--
+-- multi_pwm.vhd
+--
+-- @(#) $Id: LoadLStoreCHw.vhd 1465 2009-08-27 05:39:47Z honda $
+----------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+entity multi_pwm is
+	generic (
+		 W:integer := 16
+	);  
+	port(
+		clk         : in  std_logic;
+		reset_n     : in  std_logic;
+		chipselect  : in  std_logic;
+		address     : in  std_logic_vector(2 downto 0);
+		write       : in  std_logic;
+		writedata   : in  std_logic_vector(31 downto 0);
+		read        : in  std_logic;
+		readdata    : out std_logic_vector(31 downto 0);
+		byteenable  : in  std_logic_vector(3 downto 0);
+		waitrequest : out std_logic;
+		pwm1        : out std_logic;
+		pwm2        : out std_logic;
+		pwm3        : out std_logic;
+		pwm4        : out std_logic;
+		pwm5        : out std_logic;
+		pwm6        : out std_logic
+	);
+end multi_pwm;
+
+
+----------------------------------------------------------------------
+-- Architecture section
+----------------------------------------------------------------------
+architecture rtl of multi_pwm is
+	signal ver1_select   : std_logic;
+	signal ver2_select   : std_logic;
+	signal ver3_select   : std_logic;
+	signal ver4_select   : std_logic;
+	signal ver5_select   : std_logic;
+	signal ver6_select   : std_logic;
+	signal ver7_select   : std_logic;
+	signal ver8_select   : std_logic;
+
+	signal control_reg : std_logic_vector(31 downto 0);
+	signal pwm_counter, pwm_counter_max, pwm_value1, pwm_value2, pwm_value3,
+		   pwm_value4, pwm_value5,pwm_value6 : std_logic_vector(W-1 downto 0);
+
+	signal pwm_value1_v, pwm_value2_v, pwm_value3_v,
+		   pwm_value4_v, pwm_value5_v, pwm_value6_v : std_logic_vector(W-1 downto 0);
+
+begin
+
+	-- ¢gpM
+	waitrequest <= '0';
+
+	-- ZN^
+	process(address, chipselect)
+	begin
+		ver1_select   <= '0';
+		ver2_select   <= '0';
+		ver3_select   <= '0';
+		ver4_select   <= '0';
+		ver5_select   <= '0';
+		ver6_select   <= '0';
+		ver7_select   <= '0';
+		ver8_select   <= '0';
+		if chipselect = '1' then
+			case  address is 
+				when "000" => ver1_select <= '1'; -- 0x00
+				when "001" => ver2_select <= '1'; -- 0x04
+				when "010" => ver3_select <= '1'; -- 0x08
+				when "011" => ver4_select <= '1'; -- 0x0C
+				when "100" => ver5_select <= '1'; -- 0x10
+				when "101" => ver6_select <= '1'; -- 0x14
+				when "110" => ver7_select <= '1'; -- 0x18
+				when "111" => ver8_select <= '1'; -- 0x1C
+				when others => null;
+			end case;
+		end if;
+	end process;
+
+	-- [h}`vNT
+	process(ver1_select,ver2_select,ver3_select,ver4_select,
+			ver5_select,ver6_select,ver7_select,ver8_select)
+	begin
+		readdata <= (others=>'0');
+		if ver1_select = '1' then
+			readdata <= control_reg;
+		elsif ver2_select = '1' then
+			readdata(W-1 downto 0) <= pwm_counter_max;
+		elsif ver3_select = '1' then
+			readdata(W-1 downto 0) <= pwm_value1;
+		elsif ver4_select = '1' then
+			readdata(W-1 downto 0) <= pwm_value2;
+		elsif ver5_select = '1' then
+			readdata(W-1 downto 0) <= pwm_value3;
+		elsif ver6_select = '1' then
+			readdata(W-1 downto 0) <= pwm_value4;
+		elsif ver7_select = '1' then
+			readdata(W-1 downto 0) <= pwm_value5;
+		elsif ver8_select = '1' then
+			readdata(W-1 downto 0) <= pwm_value6;
+		end if;
+	end process;
+
+	process(clk, reset_n)
+	begin
+		if ( reset_n = '0' ) then
+			control_reg <= (others=>'0');
+			pwm_counter_max <= (others=>'0');
+			pwm_value1 <= (others=>'0');
+			pwm_value2 <= (others=>'0');
+			pwm_value3 <= (others=>'0');
+			pwm_value4 <= (others=>'0');
+			pwm_value5 <= (others=>'0');
+			pwm_value6 <= (others=>'0');
+		elsif( clk = '1' and clk'event ) then
+
+			if (write = '1' and ver1_select = '1') then
+				control_reg <= writedata;
+			end if; 
+
+			if (write = '1' and ver2_select = '1') then
+				pwm_counter_max <= writedata(W-1 downto 0);
+			end if; 
+
+			if (write = '1' and ver3_select = '1') then
+				pwm_value1 <= writedata(W-1 downto 0);
+			end if; 
+
+			if (write = '1' and ver4_select = '1') then
+				pwm_value2 <= writedata(W-1 downto 0);
+			end if; 
+
+			if (write = '1' and ver5_select = '1') then
+				pwm_value3 <= writedata(W-1 downto 0);
+			end if; 
+
+			if (write = '1' and ver6_select = '1') then
+				pwm_value4 <= writedata(W-1 downto 0);
+			end if; 
+
+			if (write = '1' and ver7_select = '1') then
+				pwm_value5 <= writedata(W-1 downto 0);
+			end if; 
+
+			if (write = '1' and ver8_select = '1') then
+				pwm_value6 <= writedata(W-1 downto 0);
+			end if; 
+
+		end if;
+	end process;
+
+	-- generate pwm
+	process(clk, reset_n)
+	begin
+		if ( reset_n = '0' ) then
+			PWM1 <= '0';
+			PWM2 <= '0';
+			PWM3 <= '0';
+			PWM4 <= '0';
+			PWM5 <= '0';
+			PWM6 <= '0';
+			pwm_counter <= (others=>'0');
+			pwm_value1_v <= (others=>'0');
+			pwm_value2_v <= (others=>'0');
+			pwm_value3_v <= (others=>'0');
+			pwm_value4_v <= (others=>'0');
+			pwm_value5_v <= (others=>'0');
+			pwm_value6_v <= (others=>'0');
+		elsif( clk = '1' and clk'event ) then
+
+			if (pwm_counter > pwm_counter_max) then
+				pwm_counter <= (others=>'0');
+				pwm_value1_v <= pwm_value1;
+				pwm_value2_v <= pwm_value2;
+				pwm_value3_v <= pwm_value3;
+				pwm_value4_v <= pwm_value4;
+				pwm_value5_v <= pwm_value5;
+				pwm_value6_v <= pwm_value6;
+			else
+				pwm_counter <= pwm_counter + 1;
+			end if;
+
+			if ((pwm_counter<pwm_value1_v)and (pwm_value1_v>0)) then
+				PWM1<='1';
+			else PWM1<='0'; end if; 
+			  
+			 if ((pwm_counter<pwm_value2_v)and (pwm_value2_v>0)) then
+				PWM2<='1';
+			else PWM2<='0'; end if; 
+
+			if ((pwm_counter<pwm_value3_v)and (pwm_value3_v>0)) then
+				PWM3<='1';
+			else PWM3<='0'; end if; 
+			  
+			if ((pwm_counter<pwm_value4_v)and (pwm_value4_v>0)) then
+				PWM4<='1';
+			else PWM4<='0'; end if; 
+			  
+			if ((pwm_counter<pwm_value5_v)and (pwm_value5_v>0)) then
+				PWM5<='1';
+			else PWM5<='0'; end if; 
+			  
+			if ((pwm_counter<pwm_value6_v)and (pwm_value6_v>0)) then
+				PWM6<='1';
+			else PWM6<='0'; end if; 
+		end if;
+	end process;
+
+
+end rtl;
Index: /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/multi_pwm/multi_pwm_hw.tcl
===================================================================
--- /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/multi_pwm/multi_pwm_hw.tcl	(revision 295)
+++ /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/multi_pwm/multi_pwm_hw.tcl	(revision 295)
@@ -0,0 +1,113 @@
+# TCL File Generated by Component Editor 8.1
+# Fri Aug 28 12:47:32 JST 2009
+# DO NOT MODIFY
+
+
+# +-----------------------------------
+# | 
+# | multi_pwm "multi_pwm" v1.0
+# | null 2009.08.28.12:47:32
+# | 
+# | 
+# | C:/home/nces/os/hw/queuing_lock/1s40_dual_fmp/multi_pwm/multi_pwm.vhd
+# | 
+# |    ./multi_pwm.vhd syn, sim
+# | 
+# +-----------------------------------
+
+
+# +-----------------------------------
+# | module multi_pwm
+# | 
+set_module_property NAME multi_pwm
+set_module_property VERSION 1.0
+set_module_property GROUP Other
+set_module_property DISPLAY_NAME multi_pwm
+set_module_property LIBRARIES {ieee.std_logic_1164.all std.standard.all}
+set_module_property TOP_LEVEL_HDL_FILE multi_pwm.vhd
+set_module_property TOP_LEVEL_HDL_MODULE multi_pwm
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE false
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | files
+# | 
+add_file multi_pwm.vhd {SYNTHESIS SIMULATION}
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | parameters
+# | 
+add_parameter W INTEGER 15
+set_parameter_property W DEFAULT_VALUE 15
+set_parameter_property W DISPLAY_NAME WIDTH
+set_parameter_property W UNITS None
+set_parameter_property W ALLOWED_RANGES -2147483648:2147483647
+set_parameter_property W DISPLAY_HINT ""
+set_parameter_property W AFFECTS_GENERATION false
+set_parameter_property W HDL_PARAMETER true
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point clock_reset
+# | 
+add_interface clock_reset clock end
+set_interface_property clock_reset ptfSchematicName ""
+
+add_interface_port clock_reset clk clk Input 1
+add_interface_port clock_reset reset_n reset_n Input 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point avalon_slave_0
+# | 
+add_interface avalon_slave_0 avalon end
+set_interface_property avalon_slave_0 addressAlignment DYNAMIC
+set_interface_property avalon_slave_0 addressSpan 32
+set_interface_property avalon_slave_0 bridgesToMaster ""
+set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
+set_interface_property avalon_slave_0 holdTime 0
+set_interface_property avalon_slave_0 isMemoryDevice false
+set_interface_property avalon_slave_0 isNonVolatileStorage false
+set_interface_property avalon_slave_0 linewrapBursts false
+set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
+set_interface_property avalon_slave_0 minimumUninterruptedRunLength 1
+set_interface_property avalon_slave_0 printableDevice false
+set_interface_property avalon_slave_0 readLatency 0
+set_interface_property avalon_slave_0 readWaitTime 1
+set_interface_property avalon_slave_0 setupTime 0
+set_interface_property avalon_slave_0 timingUnits Cycles
+set_interface_property avalon_slave_0 writeWaitTime 0
+
+set_interface_property avalon_slave_0 ASSOCIATED_CLOCK clock_reset
+
+add_interface_port avalon_slave_0 chipselect chipselect Input 1
+add_interface_port avalon_slave_0 address address Input 3
+add_interface_port avalon_slave_0 write write Input 1
+add_interface_port avalon_slave_0 writedata writedata Input 32
+add_interface_port avalon_slave_0 read read Input 1
+add_interface_port avalon_slave_0 readdata readdata Output 32
+add_interface_port avalon_slave_0 byteenable byteenable Input 4
+add_interface_port avalon_slave_0 waitrequest waitrequest Output 1
+
+# +-----------------------------------
+# | connection point conduit_end
+# | 
+add_interface conduit_end conduit end
+
+set_interface_property conduit_end ENABLED true
+
+add_interface_port conduit_end PWM1 export Output 1
+add_interface_port conduit_end PWM3 export Output 1
+add_interface_port conduit_end PWM2 export Output 1
+add_interface_port conduit_end PWM4 export Output 1
+add_interface_port conduit_end PWM5 export Output 1
+add_interface_port conduit_end PWM6 export Output 1
+
+# | 
+# +-----------------------------------
Index: /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/sysver/sysver.vhd
===================================================================
--- /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/sysver/sysver.vhd	(revision 295)
+++ /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/sysver/sysver.vhd	(revision 295)
@@ -0,0 +1,156 @@
+----------------------------------------------------------------------
+-- Copyright (c) 2009 Shinya Honda (honda@ertl.jp)
+--
+-- sysver.vhd
+--
+-- @(#) $Id: LoadLStoreCHw.vhd 1465 2009-08-27 05:39:47Z honda $
+----------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity sysver is
+	generic (
+		VER1_ROM_REG_VALUE : std_logic_vector(31 downto 0) := X"0000_0000";
+		VER2_ROM_REG_VALUE : std_logic_vector(31 downto 0) := X"0000_0000";
+		VER3_ROM_REG_VALUE : std_logic_vector(31 downto 0) := X"0000_0000";
+		VER4_ROM_REG_VALUE : std_logic_vector(31 downto 0) := X"0000_0000";
+		VER5_RAM_REG_VALUE : std_logic_vector(31 downto 0) := X"0000_0000";
+		VER6_RAM_REG_VALUE : std_logic_vector(31 downto 0) := X"0000_0000";
+		VER7_RAM_REG_VALUE : std_logic_vector(31 downto 0) := X"0000_0000";
+		VER8_RAM_REG_VALUE : std_logic_vector(31 downto 0) := X"0000_0000"
+	);  
+	port(
+		clk         : in  std_logic;
+		reset_n     : in  std_logic;
+		chipselect  : in  std_logic;
+		address     : in  std_logic_vector(2 downto 0);
+		write       : in  std_logic;
+		writedata   : in  std_logic_vector(31 downto 0);
+		read        : in  std_logic;
+		readdata    : out std_logic_vector(31 downto 0);
+		byteenable  : in  std_logic_vector(3 downto 0);
+		waitrequest : out std_logic
+	);
+end sysver;
+
+
+----------------------------------------------------------------------
+-- Architecture section
+----------------------------------------------------------------------
+architecture rtl of sysver is
+	signal ver1_select   : std_logic;
+	signal ver2_select   : std_logic;
+	signal ver3_select   : std_logic;
+	signal ver4_select   : std_logic;
+	signal ver5_select   : std_logic;
+	signal ver6_select   : std_logic;
+	signal ver7_select   : std_logic;
+	signal ver8_select   : std_logic;
+
+	signal ver5_reg : std_logic_vector(31 downto 0);
+	signal ver6_reg : std_logic_vector(31 downto 0);
+	signal ver7_reg : std_logic_vector(31 downto 0);
+	signal ver8_reg : std_logic_vector(31 downto 0);
+
+begin
+
+	-- ¢gpM
+	waitrequest <= '0';
+
+	-- ZN^
+	process(address, chipselect)
+	begin
+		ver1_select   <= '0';
+		ver2_select   <= '0';
+		ver3_select   <= '0';
+		ver4_select   <= '0';
+		ver5_select   <= '0';
+		ver6_select   <= '0';
+		ver7_select   <= '0';
+		ver8_select   <= '0';
+
+		if chipselect = '1' then
+			case  address is 
+				when "000" => ver1_select <= '1'; -- 0x00
+				when "001" => ver2_select <= '1'; -- 0x04
+				when "010" => ver3_select <= '1'; -- 0x08
+				when "011" => ver4_select <= '1'; -- 0x0C
+				when "100" => ver5_select <= '1'; -- 0x10
+				when "101" => ver6_select <= '1'; -- 0x14
+				when "110" => ver7_select <= '1'; -- 0x18
+				when "111" => ver8_select <= '1'; -- 0x1C
+				when others => null;
+			end case;
+		end if;
+	end process;
+
+	-- [h}`vNT
+	process(ver1_select,ver2_select,ver3_select,ver4_select,
+			ver5_select,ver6_select,ver7_select,ver8_select)
+	begin
+		readdata <= (others=>'0');
+		if ver1_select = '1' then
+			readdata <= VER1_ROM_REG_VALUE;
+		elsif ver2_select = '1' then
+			readdata <= VER2_ROM_REG_VALUE;
+		elsif ver3_select = '1' then
+			readdata <= VER3_ROM_REG_VALUE;
+		elsif ver4_select = '1' then
+			readdata <= VER4_ROM_REG_VALUE;
+		elsif ver5_select = '1' then
+			readdata <= ver5_reg;
+		elsif ver6_select = '1' then
+			readdata <= ver6_reg;
+		elsif ver7_select = '1' then
+			readdata <= ver7_reg;
+		elsif ver8_select = '1' then
+			readdata <= ver8_reg;
+		end if;
+	end process;
+
+	process(clk, reset_n)
+	begin
+		if ( reset_n = '0' ) then
+			ver5_reg <= VER5_RAM_REG_VALUE;
+		elsif( clk = '1' and clk'event ) then
+			if (write = '1' and ver5_select = '1') then
+				ver5_reg <= writedata;
+			end if; 
+		end if;
+	end process;
+
+	process(clk, reset_n)
+	begin
+		if ( reset_n = '0' ) then
+			ver6_reg <= VER6_RAM_REG_VALUE;
+		elsif( clk = '1' and clk'event ) then
+			if (write = '1' and ver6_select = '1') then
+				ver6_reg <= writedata;
+			end if; 
+		end if;
+	end process;
+
+	process(clk, reset_n)
+	begin
+		if ( reset_n = '0' ) then
+			ver7_reg <= VER7_RAM_REG_VALUE;
+		elsif( clk = '1' and clk'event ) then
+			if (write = '1' and ver7_select = '1') then
+				ver7_reg <= writedata;
+			end if; 
+		end if;
+	end process;
+
+	process(clk, reset_n)
+	begin
+		if ( reset_n = '0' ) then
+			ver8_reg <= VER8_RAM_REG_VALUE;
+		elsif( clk = '1' and clk'event ) then
+			if (write = '1' and ver8_select = '1') then
+				ver8_reg <= writedata;
+			end if; 
+		end if;
+	end process;
+
+
+end rtl;
Index: /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/sysver/sysver_hw.tcl
===================================================================
--- /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/sysver/sysver_hw.tcl	(revision 295)
+++ /rc_os_nios2/trunk/DE0_Nano_QSYS_DEMO/sysver/sysver_hw.tcl	(revision 295)
@@ -0,0 +1,138 @@
+# TCL File Generated by Component Editor 8.1
+# Fri Aug 28 12:47:32 JST 2009
+# DO NOT MODIFY
+
+
+# +-----------------------------------
+# | 
+# | sysver "sysver" v1.0
+# | null 2009.08.28.12:47:32
+# | 
+# | 
+# | C:/home/nces/os/hw/queuing_lock/1s40_dual_fmp/sysver/sysver.vhd
+# | 
+# |    ./sysver.vhd syn, sim
+# | 
+# +-----------------------------------
+
+
+# +-----------------------------------
+# | module sysver
+# | 
+set_module_property NAME sysver
+set_module_property VERSION 1.0
+set_module_property GROUP Other
+set_module_property DISPLAY_NAME sysver
+set_module_property LIBRARIES {ieee.std_logic_1164.all std.standard.all}
+set_module_property TOP_LEVEL_HDL_FILE sysver.vhd
+set_module_property TOP_LEVEL_HDL_MODULE sysver
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE false
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | files
+# | 
+add_file sysver.vhd {SYNTHESIS SIMULATION}
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | parameters
+# | 
+add_parameter VER1_ROM_REG_VALUE STD_LOGIC_VECTOR 0 ""
+set_parameter_property VER1_ROM_REG_VALUE DISPLAY_NAME VER1_ROM_REG_VALUE
+set_parameter_property VER1_ROM_REG_VALUE UNITS None
+set_parameter_property VER1_ROM_REG_VALUE ALLOWED_RANGES 0:4294967295
+set_parameter_property VER1_ROM_REG_VALUE DESCRIPTION ""
+set_parameter_property VER1_ROM_REG_VALUE AFFECTS_PORT_WIDTHS true
+add_parameter VER2_ROM_REG_VALUE STD_LOGIC_VECTOR 0 ""
+set_parameter_property VER2_ROM_REG_VALUE DISPLAY_NAME VER2_ROM_REG_VALUE
+set_parameter_property VER2_ROM_REG_VALUE UNITS None
+set_parameter_property VER2_ROM_REG_VALUE ALLOWED_RANGES 0:4294967295
+set_parameter_property VER2_ROM_REG_VALUE DESCRIPTION ""
+set_parameter_property VER2_ROM_REG_VALUE AFFECTS_PORT_WIDTHS true
+add_parameter VER3_ROM_REG_VALUE STD_LOGIC_VECTOR 0 ""
+set_parameter_property VER3_ROM_REG_VALUE DISPLAY_NAME VER3_ROM_REG_VALUE
+set_parameter_property VER3_ROM_REG_VALUE UNITS None
+set_parameter_property VER3_ROM_REG_VALUE ALLOWED_RANGES 0:4294967295
+set_parameter_property VER3_ROM_REG_VALUE DESCRIPTION ""
+set_parameter_property VER3_ROM_REG_VALUE AFFECTS_PORT_WIDTHS true
+add_parameter VER4_ROM_REG_VALUE STD_LOGIC_VECTOR 0 ""
+set_parameter_property VER4_ROM_REG_VALUE DISPLAY_NAME VER4_ROM_REG_VALUE
+set_parameter_property VER4_ROM_REG_VALUE UNITS None
+set_parameter_property VER4_ROM_REG_VALUE ALLOWED_RANGES 0:4294967295
+set_parameter_property VER4_ROM_REG_VALUE DESCRIPTION ""
+set_parameter_property VER4_ROM_REG_VALUE AFFECTS_PORT_WIDTHS true
+add_parameter VER5_RAM_REG_VALUE STD_LOGIC_VECTOR 0 ""
+set_parameter_property VER5_RAM_REG_VALUE DISPLAY_NAME VER5_RAM_REG_VALUE
+set_parameter_property VER5_RAM_REG_VALUE UNITS None
+set_parameter_property VER5_RAM_REG_VALUE ALLOWED_RANGES 0:4294967295
+set_parameter_property VER5_RAM_REG_VALUE DESCRIPTION ""
+set_parameter_property VER5_RAM_REG_VALUE AFFECTS_PORT_WIDTHS true
+add_parameter VER6_RAM_REG_VALUE STD_LOGIC_VECTOR 0 ""
+set_parameter_property VER6_RAM_REG_VALUE DISPLAY_NAME VER6_RAM_REG_VALUE
+set_parameter_property VER6_RAM_REG_VALUE UNITS None
+set_parameter_property VER6_RAM_REG_VALUE ALLOWED_RANGES 0:4294967295
+set_parameter_property VER6_RAM_REG_VALUE DESCRIPTION ""
+set_parameter_property VER6_RAM_REG_VALUE AFFECTS_PORT_WIDTHS true
+add_parameter VER7_RAM_REG_VALUE STD_LOGIC_VECTOR 0 ""
+set_parameter_property VER7_RAM_REG_VALUE DISPLAY_NAME VER7_RAM_REG_VALUE
+set_parameter_property VER7_RAM_REG_VALUE UNITS None
+set_parameter_property VER7_RAM_REG_VALUE ALLOWED_RANGES 0:4294967295
+set_parameter_property VER7_RAM_REG_VALUE DESCRIPTION ""
+set_parameter_property VER7_RAM_REG_VALUE AFFECTS_PORT_WIDTHS true
+add_parameter VER8_RAM_REG_VALUE STD_LOGIC_VECTOR 0 ""
+set_parameter_property VER8_RAM_REG_VALUE DISPLAY_NAME VER8_RAM_REG_VALUE
+set_parameter_property VER8_RAM_REG_VALUE UNITS None
+set_parameter_property VER8_RAM_REG_VALUE ALLOWED_RANGES 0:4294967295
+set_parameter_property VER8_RAM_REG_VALUE DESCRIPTION ""
+set_parameter_property VER8_RAM_REG_VALUE AFFECTS_PORT_WIDTHS true
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point clock_reset
+# | 
+add_interface clock_reset clock end
+set_interface_property clock_reset ptfSchematicName ""
+
+add_interface_port clock_reset clk clk Input 1
+add_interface_port clock_reset reset_n reset_n Input 1
+# | 
+# +-----------------------------------
+
+# +-----------------------------------
+# | connection point avalon_slave_0
+# | 
+add_interface avalon_slave_0 avalon end
+set_interface_property avalon_slave_0 addressAlignment DYNAMIC
+set_interface_property avalon_slave_0 addressSpan 32
+set_interface_property avalon_slave_0 bridgesToMaster ""
+set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
+set_interface_property avalon_slave_0 holdTime 0
+set_interface_property avalon_slave_0 isMemoryDevice false
+set_interface_property avalon_slave_0 isNonVolatileStorage false
+set_interface_property avalon_slave_0 linewrapBursts false
+set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
+set_interface_property avalon_slave_0 minimumUninterruptedRunLength 1
+set_interface_property avalon_slave_0 printableDevice false
+set_interface_property avalon_slave_0 readLatency 0
+set_interface_property avalon_slave_0 readWaitTime 1
+set_interface_property avalon_slave_0 setupTime 0
+set_interface_property avalon_slave_0 timingUnits Cycles
+set_interface_property avalon_slave_0 writeWaitTime 0
+
+set_interface_property avalon_slave_0 ASSOCIATED_CLOCK clock_reset
+
+add_interface_port avalon_slave_0 chipselect chipselect Input 1
+add_interface_port avalon_slave_0 address address Input 3
+add_interface_port avalon_slave_0 write write Input 1
+add_interface_port avalon_slave_0 writedata writedata Input 32
+add_interface_port avalon_slave_0 read read Input 1
+add_interface_port avalon_slave_0 readdata readdata Output 32
+add_interface_port avalon_slave_0 byteenable byteenable Input 4
+add_interface_port avalon_slave_0 waitrequest waitrequest Output 1
+# | 
+# +-----------------------------------
Index: /rc_os_nios2/trunk/README.txt
===================================================================
--- /rc_os_nios2/trunk/README.txt	(revision 295)
+++ /rc_os_nios2/trunk/README.txt	(revision 295)
@@ -0,0 +1,173 @@
+
+		ATK2 RCJ[(Nios2Å)
+		[U[}j
+A
+
+		Îo[W: Release 0.1.0
+		ÅIXV: 2015N831ú
+
+----------------------------------------------------------------------
+ TOPPERS Software
+     Toyohashi Open Platform for Embedded Real-Time Systems/
+     Software
+
+ Copyright (C) 2015 by Embedded and Real-Time Systems Laboratory
+             Graduate School of Information Science, Nagoya Univ., JAPAN
+ 
+ ãLì ÒÍCÈºÌ(1)`(4)Ìðð½·êÉÀèC{\tgEF
+ Ai{\tgEFAðüÏµ½àÌðÜÞDÈº¯¶jðgpE¡»Eü
+ ÏEÄzziÈºCpÆÄÔj·é±Æð³Åø·éD
+ (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
+      \¦C±Ìpð¨æÑºLÌ³ÛØKèªC»ÌÜÜÌ`Å\[
+     XR[hÉÜÜêÄ¢é±ÆD
+ (2) {\tgEFAðCCu`®ÈÇC¼Ì\tgEFAJ­Ég
+     pÅ«é`ÅÄzz·éêÉÍCÄzzÉº¤hL
+gip
+     Ò}j
+AÈÇjÉCãLÌì \¦C±Ìpð¨æÑºL
+     Ì³ÛØKèðfÚ·é±ÆD
+ (3) {\tgEFAðC@íÉgÝÞÈÇC¼Ì\tgEFAJ­Ég
+     pÅ«È¢`ÅÄzz·éêÉÍCÌ¢¸ê©Ìðð½·±
+     ÆD
+   (a) ÄzzÉº¤hL
+gipÒ}j
+AÈÇjÉCãLÌ
+       ì \¦C±Ìpð¨æÑºLÌ³ÛØKèðfÚ·é±ÆD
+   (b) ÄzzÌ`ÔðCÊÉèßéû@ÉæÁÄCTOPPERSvWFNgÉ
+       ñ·é±ÆD
+ (4) {\tgEFAÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶é¢©Èé¹
+     Q©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆD
+     Ü½C{\tgEFAÌ[UÜ½ÍGh[U©çÌ¢©Èé
+     RÉîÃ­¿©çàCãLì Ò¨æÑTOPPERSvWFNgð
+     ÆÓ·é±ÆD
+ 
+ {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì Ò¨
+ æÑTOPPERSvWFNgÍC{\tgEFAÉÖµÄCÁèÌgpÚI
+ ÉÎ·éK«àÜßÄC¢©ÈéÛØàsíÈ¢DÜ½C{\tgEF
+ AÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶½¢©Èé¹QÉÖµÄàC»
+ ÌÓCðíÈ¢D
+ 
+ $Id: $
+----------------------------------------------------------------------
+
+PDTv
+
+ATK2 RCJ[(Nios2Å)fJ[§ävOÍRCJ[ðx[XÆµ½f
+J[ð§ä·é½ßÌvOÅ èCTOPPERSvWFNg©çöJ³
+êÄ¢éATK2ðgpµÄ¢éD
+
+{}j
+AÍÈÕIÈ¨Å é½ßC¡ãg[·é\èÅ éD¿âÍC
+
+ users@toppers.jp
+ 
+Åó¯t¯éD
+
+
+QDtH_\¬
+
+./sbxbt_ps3_140113.patch  : SBDBT5VpÌt@[EFApb`
+./DE0_Nano_QSYS_DEMO      : DE0pn[hEFApt@C
+./atk2-sc1_1.3.2          : atk2-sc1_1.3.2pt@C
+
+RDOt@C
+
+{vOðgp·é½ßÉÍCÈºÌOt@CªKvÆÈéD
+
+1. ATK2-SC1 
+  TOPPERSvWFNg©çÌt@Cð_E[h
+  atk2-sc1_nios2_dev_gcc-20150406.tar.gz
+
+2. SBDBTpt@[EFA
+   jOGNgjNXÐÌWebTCg©çÈºÌt@Cð_E
+   [h
+   http://runningele.web.fc2.com/ps3/sbxbt_ps3_src_140113.zip
+   
+3.DE0pÌn[hEFAfUC
+ TerasicÌTCg©ç_E[h(DE0_Nano_QSYS_DEMOðgp)
+
+
+SDOc[
+
+1.SBDBT«Ýp\tg
+  MicrochipÐÌWebTCg©ç MPLAB IDEÆC32ðüèµÄCXg[
+  
+2.QuratusII
+  AlteraÐÌWebTCg©çQurartusII WebGfBV 14.1ð_E[hµ
+  ÄCXg[
+
+
+TDKv@Þ
+
+{vOðÀs·éÉÍÌ@ÞªKvÅ éD
+
+ERCJ[
+  ®¬iðöxÅÊÌX©çwü
+Ex[X{[h
+  ¼Y¤©çwü
+EDE0-Nano x 1`3
+  AlteraãX©çwü
+ESBDBTTV
+  jOGNgjNX©çwü
+EBluetoothhO
+  SBDBTTVpÊÌX©çwü
+EPS3Rg[
+  ÊÌX©çwü
+EPICC^[
+  ÊÌX©çwü
+ERCJ[ÆDE0-NanoÌÚ±P[u
+  eíÚ±P[uªKv  
+
+
+UDn[hEFAÌõ
+
+E}CR{[hÁH
+  RlN^ðÚ±·é½ß¢­Â©Ìg£sðØf·é
+  
+Ex[XîÂÆ}CR{[hÌZbgAbv
+  E}CR{[hðx[XîÂÉÚ±·é
+  EÇÌnðÀs·é©fBbvXCb`ðÝè·é
+    {fBn  : DIP1 ON
+    §än    : DIP2 ON
+    ÊMn    : DIP3 ON
+    
+EBluetoothW
+[ÌZbgAbv
+  ESBDBTpt@[EFAð_E[h
+  Ezzt@CÌpb`ðKpµÄMAPLAB IDEÉæèrh
+  EPICC^[ðp¢Ä_E[h
+  Et@[EFAt®Ì}j
+AÉ]ÁÄCPS3Rg[ÆyAO·é
+  
+Ex[XîÂÆRCJ[ÌZbgAbv
+  EeRlN^ðÚ±·é
+
+
+VD\tgEFAÌrhÆÀs
+
+1.t@CÌpÓ
+ atk2-sc1_nios2_dev_gcc-20150406.tar.gz ðWJ
+ zzt@CÌ atk2-sc1_1.3.2 Ìet@Cðã«·é
+ 
+ autosar.org ©ç_E[hµ½XL[}t@C
+ (AUTOSAR_4-0-3_STRICT.xsd, xml.xsd) ðÈºÌtH_ÉRs[·é±ÆD
+
+Eatk2-sc1\cfg\cfg
+
+2.rh
+  atk2-sc1/obj/nios2_dev_rc É¨¢ÄrhðÀ{
+  $ make depend
+  $ make
+  
+3.n[hEFAC[WÌì¬
+ atk2-sc1/obj/nios2_dev_rc ÅÈºÌR}hðÀs·é±ÆÅ«Ýt
+ @Cª¶¬³êé
+  $ make flash
+  
+4.n[hEFAÌ«Ý
+ atk2-sc1/obj/nios2_dev_rc ÅÈºÌR}hðÀs·é±ÆÅDE0-NanoÉ
+ «Üêé
+ $ make prog
+
+
+Èã
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/Makefile
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/Makefile	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/Makefile	(revision 295)
@@ -0,0 +1,625 @@
+#
+#  TOPPERS ATK2
+#      Toyohashi Open Platform for Embedded Real-Time Systems
+#      Automotive Kernel Version 2
+#
+#  Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
+#                              Toyohashi Univ. of Technology, JAPAN
+#  Copyright (C) 2006-2014 by Center for Embedded Computing Systems
+#              Graduate School of Information Science, Nagoya Univ., JAPAN
+#  Copyright (C) 2011-2014 by FUJISOFT INCORPORATED, JAPAN
+#  Copyright (C) 2011-2013 by Spansion LLC, USA
+#  Copyright (C) 2011-2013 by NEC Communication Systems, Ltd., JAPAN
+#  Copyright (C) 2011-2014 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
+#  Copyright (C) 2011-2014 by Renesas Electronics Corporation, JAPAN
+#  Copyright (C) 2011-2014 by Sunny Giken Inc., JAPAN
+#  Copyright (C) 2011-2014 by TOSHIBA CORPORATION, JAPAN
+#  Copyright (C) 2011-2014 by Witz Corporation, JAPAN
+#
+#  上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
+#  ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
+#  変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
+#  (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
+#      権表示，この利用条件および下記の無保証規定が，そのままの形でソー
+#      スコード中に含まれていること．
+#  (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
+#      用できる形で再配布する場合には，再配布に伴うドキュメント（利用
+#      者マニュアルなど）に，上記の著作権表示，この利用条件および下記
+#      の無保証規定を掲載すること．
+#  (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
+#      用できない形で再配布する場合には，次のいずれかの条件を満たすこ
+#      と．
+#    (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
+#        作権表示，この利用条件および下記の無保証規定を掲載すること．
+#    (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
+#        報告すること．
+#  (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
+#      害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
+#      また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
+#      由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
+#      免責すること．
+#
+#  本ソフトウェアは，AUTOSAR（AUTomotive Open System ARchitecture）仕
+#  様に基づいている．上記の許諾は，AUTOSARの知的財産権を許諾するもので
+#  はない．AUTOSARは，AUTOSAR仕様に基づいたソフトウェアを商用目的で利
+#  用する者に対して，AUTOSARパートナーになることを求めている．
+#
+#  本ソフトウェアは，無保証で提供されているものである．上記著作権者お
+#  よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
+#  に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
+#  アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
+#  の責任を負わない．
+#
+#  $Id: Makefile 8482 2014-03-07 03:55:38Z shigihara $
+#
+
+#
+#  ターゲットの指定（Makefile.targetで上書きされるのを防ぐため）
+#
+all:
+
+SOF_FILE = ../../../DE0_Nano_QSYS_DEMO/DE0_Nano.sof
+COF_FILE = ../../../DE0_Nano_QSYS_DEMO/hw_sw.cof
+
+flash: atk2-sc1.exe
+	sof2flash --epcs --input=$(SOF_FILE) --output=hw.flash --quiet
+	elf2flash --epcs --after=hw.flash --input=atk2-sc1.exe --output=sw.flash --boot=epcs_controller_boot_rom.flash
+	cp hw.flash hw_sw.flash
+	cat sw.flash >> hw_sw.flash
+	nios2-elf-objcopy.exe --input-target srec --output-target ihex hw_sw.flash hw_sw.hex
+	quartus_cpf.exe -c $(COF_FILE)
+
+prog : hw_sw.jic
+	quartus_pgm.exe -c USB-BLASTER -m jtag -o pvbi\;hw_sw.jic
+
+#
+# RCカーでのROM_BOOTをサポート
+# JTAG経由の出力をbluetooth経由に変更
+CDEFS := $(CDEFS) -DRC_ROM_BOOT
+
+#
+#  ターゲット略称の定義
+#
+TARGET = nios2_dev_gcc
+
+#
+#  プログラミング言語の定義
+#
+SRCLANG = c
+ifeq ($(SRCLANG),c++)
+  USE_CXX = true
+  CXXLIBS = -lstdc++ -lm -lc
+  CXXRTS = cxxrt.o newlibrt.o
+endif
+
+#
+#  ソースファイルのディレクトリの定義
+#
+SRCDIR = ../..
+
+#
+#  オブジェクトファイル名の拡張子の設定
+#
+OBJEXT = exe
+
+#
+#  実行環境の定義（ターゲット依存に上書きされる場合がある）
+#
+DBGENV := 
+
+#
+#  カーネルライブラリ（libkernel.a）のディレクトリ名
+#  （カーネルライブラリもmake対象にする時は，空に定義する）
+#
+KERNEL_LIB = 
+
+#
+#  カーネルを関数単位でコンパイルするかどうかの定義
+#
+KERNEL_FUNCOBJS = 
+
+#
+#  トレースログを取得するかどうかの定義
+#
+ENABLE_TRACE = 
+
+#
+#  システムタイマ(タイマドライバ)を使用するかどうかの定義
+#
+ENABLE_SYS_TIMER = 
+
+#
+#  ハードウェアカウンタを無効にするかどうかの定義
+#
+OMIT_HW_COUNTER = 
+
+#
+#  コンフィギュレーションファイルに関する定義
+#
+CFGNAME = rc_car
+ifeq ($(CFGNAME),sample1)
+  CFGNAME := $(CFGNAME) target_serial
+endif
+ifdef ENABLE_SYS_TIMER
+  CFGNAME := $(CFGNAME) target_timer
+endif
+ifndef OMIT_HW_COUNTER
+  CFGNAME := $(CFGNAME) target_hw_counter
+endif
+
+CFGNAME := $(CFGNAME) comuart target_serial target_hw_counter nces_can
+
+#
+#  ユーティリティプログラムの名称
+#
+PERL = /usr/bin/perl
+CFG = $(SRCDIR)/cfg/cfg/cfg
+
+#
+#  オブジェクトファイル名の定義
+#
+OBJNAME = atk2-sc1
+ifdef OBJEXT
+  OBJFILE = $(OBJNAME).$(OBJEXT)
+  CFG1_OUT = cfg1_out.$(OBJEXT)
+else
+  OBJFILE = $(OBJNAME)
+  CFG1_OUT = cfg1_out
+endif
+
+#
+#  ターゲット依存部のディレクトリの定義
+#
+TARGETDIR = $(SRCDIR)/target/$(TARGET)
+
+#
+#  ターゲット依存の定義のインクルード
+#
+include $(TARGETDIR)/Makefile.target
+
+#
+#  ジェネレータ関係の変数の定義
+#
+PASS2_TF = $(SRCDIR)/kernel/kernel.tf
+DEF_TABS = $(SRCDIR)/kernel/kernel.csv
+CFG_KERNEL = atk2
+CFG_TABS := --ini-file $(SRCDIR)/kernel/kernel.ini $(CFG_TABS)
+
+CFG_TABS := --api-table $(DEF_TABS) \
+			--cfg1-def-table $(SRCDIR)/kernel/kernel_def.csv $(CFG_TABS)
+CFG_OBJS := Os_Lcfg.o $(CFG_OBJS)
+CFG2_OUT := Os_Lcfg.c Os_Lcfg.h Os_Cfg.h $(CFG2_OUT)
+ALL_CFG_OBJS := $(CFG_OBJS) cfg1_out.o
+
+#
+#  共通コンパイルオプションの定義
+#
+COPTS := $(COPTS) -g 
+ifndef OMIT_WARNING_ALL
+  COPTS := $(COPTS) -Wall -Wno-unused-label -Wpointer-arith
+endif
+ifndef OMIT_OPTIMIZATION
+  COPTS := $(COPTS) -O2
+endif
+CDEFS := $(CDEFS) 
+INCLUDES := -I. -I$(SRCDIR)/include -I$(SRCDIR)/arch -I$(SRCDIR) $(INCLUDES)
+LDFLAGS := $(LDFLAGS) 
+LIBS := $(LIBS) $(CXXLIBS)
+CFLAGS = $(COPTS) $(CDEFS) $(INCLUDES)
+
+#
+#  アプリケーションプログラムに関する定義
+#
+APPLNAME = rc_car
+APPLDIR = 
+APPL_CFG_INPUT := $(foreach file,$(CFGNAME),$(file).arxml)
+
+APPL_DIR = $(APPLDIR) $(SRCDIR)/library
+APPL_ASMOBJS =
+ifdef USE_CXX
+  APPL_CXXOBJS = $(APPLNAME).o 
+  APPL_COBJS =
+else
+  APPL_COBJS = $(APPLNAME).o comuart.o rcb3.o nces_can.o
+endif
+APPL_CFLAGS =
+APPL_LIBS =
+ifdef APPLDIR
+  INCLUDES := $(INCLUDES) $(foreach dir,$(APPLDIR),-I$(dir))
+endif
+
+
+#
+#  システムモジュールに関する定義
+#
+SYSMOD_DIR := $(SYSMOD_DIR) $(SRCDIR)/sysmod $(SRCDIR)/library
+SYSMOD_ASMOBJS := $(SYSMOD_ASMOBJS)
+SYSMOD_COBJS := $(SYSMOD_COBJS) banner.o syslog.o serial.o \
+				log_output.o vasyslog.o t_perror.o strerror.o \
+				$(CXXRTS)
+SYSMOD_CFLAGS := $(SYSMOD_CFLAGS)
+SYSMOD_LIBS := $(SYSMOD_LIBS)
+INCLUDES := $(INCLUDES)
+
+#
+#  カーネルに関する定義
+#
+#  KERNEL_ASMOBJS: カーネルライブラリに含める，ソースがアセンブリ言語の
+#				   オブジェクトファイル．
+#  KERNEL_COBJS: カーネルのライブラリに含める，ソースがC言語で，ソース
+#				 ファイルと1対1に対応するオブジェクトファイル．
+#  KERNEL_LCSRCS: カーネルのライブラリに含めるC言語のソースファイルで，
+#				  1つのソースファイルから複数のオブジェクトファイルを生
+#				  成するもの．
+#  KERNEL_LCOBJS: 上のソースファイルから生成されるオブジェクトファイル．
+#  KERNEL_AUX_COBJS: ロードモジュールに含めないが，カーネルのソースファ
+#					 イルと同じオプションを適用してコンパイルすべき，ソー
+#					 スがC言語のオブジェクトファイル．
+#
+KERNEL_DIR := $(KERNEL_DIR) $(SRCDIR)/kernel
+KERNEL_ASMOBJS := $(KERNEL_ASMOBJS)
+KERNEL_COBJS := $(KERNEL_COBJS)
+KERNEL_CFLAGS := $(KERNEL_CFLAGS) -I$(SRCDIR)/kernel
+ifdef OMIT_MAKEOFFSET
+  OFFSET_H =
+else
+  OFFSET_H = offset.h
+endif
+
+
+#
+#  ターゲットファイル（複数を同時に選択してはならない）
+#
+all: $(OBJFILE)
+#all: $(OBJNAME).bin
+#all: $(OBJNAME).srec
+
+##### 以下は編集しないこと #####
+
+#
+#  環境に依存するコンパイルオプションの定義
+#
+ifdef DBGENV
+  CDEFS := $(CDEFS) -D$(DBGENV)
+endif
+
+#
+#  カーネルのファイル構成の定義
+#
+include $(SRCDIR)/kernel/Makefile.kernel
+ifdef KERNEL_FUNCOBJS
+  KERNEL_LCSRCS := $(KERNEL_FCSRCS)
+  KERNEL_LCOBJS := $(foreach file,$(KERNEL_FCSRCS),$($(file:.c=)))
+else
+  KERNEL_CFLAGS := -DALLFUNC $(KERNEL_CFLAGS)
+  KERNEL_COBJS := $(KERNEL_COBJS) \
+					$(foreach file,$(KERNEL_FCSRCS),$(file:.c=.o))
+endif
+
+#
+#  ソースファイルのあるディレクトリに関する定義
+#
+vpath %.c $(KERNEL_DIR) $(SYSMOD_DIR) $(APPL_DIR)
+vpath %.S $(KERNEL_DIR) $(SYSMOD_DIR) $(APPL_DIR)
+vpath %.arxml $(KERNEL_DIR) $(SYSMOD_DIR) $(APPL_DIR)
+
+#
+#  コンパイルのための変数の定義
+#
+KERNEL_LIB_OBJS = $(KERNEL_ASMOBJS) $(KERNEL_COBJS) $(KERNEL_LCOBJS)
+SYSMOD_OBJS = $(SYSMOD_ASMOBJS) $(SYSMOD_COBJS)
+APPL_OBJS = $(APPL_ASMOBJS) $(APPL_COBJS) $(APPL_CXXOBJS)
+ALL_OBJS = $(START_OBJS) $(APPL_OBJS) $(SYSMOD_OBJS) $(CFG_OBJS) \
+											$(END_OBJS) $(HIDDEN_OBJS)
+ifdef KERNEL_LIB
+  ALL_LIBS = $(APPL_LIBS) $(SYSMOD_LIBS) -lkernel $(LIBS)
+  LIBS_DEP = $(filter %.a,$(ALL_LIBS)) $(KERNEL_LIB)/libkernel.a
+  LDFLAGS := $(LDFLAGS) -L$(KERNEL_LIB)
+else
+  ALL_LIBS = $(APPL_LIBS) $(SYSMOD_LIBS) libkernel.a $(LIBS)
+  LIBS_DEP = $(filter %.a,$(ALL_LIBS))
+endif
+
+ifdef TEXT_START_ADDRESS
+  LDFLAGS := $(LDFLAGS) -Wl,-Ttext,$(TEXT_START_ADDRESS)
+endif
+ifdef DATA_START_ADDRESS
+  LDFLAGS := $(LDFLAGS) -Wl,-Tdata,$(DATA_START_ADDRESS)
+endif
+ifdef LDSCRIPT
+  LDFLAGS := $(LDFLAGS) -T $(LDSCRIPT)
+endif
+
+#
+#  オフセットファイル（offset.h）の生成規則
+#
+offset.h: $(APPL_CFG_INPUT) Os_Lcfg.timestamp $(SRCDIR)/kernel/genoffset.tf
+	$(CFG) --pass 3 --kernel $(CFG_KERNEL) $(INCLUDES) \
+				--rom-image cfg1_out.srec --symbol-table cfg1_out.syms \
+				-T $(OFFSET_TF) $(CFG_TABS) $(filter %.arxml,$^)
+
+#
+#  カーネルのコンフィギュレーションファイルの生成
+#
+cfg1_out.c: $(APPL_CFG_INPUT) $(SRCDIR)/kernel/kernel_def.csv
+	$(CFG) --pass 1 --kernel $(CFG_KERNEL) $(INCLUDES) $(CFG_TABS) $(filter %.arxml,$^)
+
+$(CFG2_OUT): Os_Lcfg.timestamp
+Os_Lcfg.timestamp: $(APPL_CFG_INPUT) $(START_OBJS) cfg1_out.o $(END_OBJS) $(HIDDEN_OBJS) $(PASS2_TF) $(DEF_TABS)
+	$(LINK) $(CFLAGS) $(LDFLAGS) $(CFG1_OUT_LDFLAGS) -o $(CFG1_OUT) \
+						$(START_OBJS) cfg1_out.o $(END_OBJS)
+	$(NM) -n $(CFG1_OUT) > cfg1_out.syms
+	$(OBJCOPY) -O srec -S $(CFG1_OUT) cfg1_out.srec
+	$(CFG) --pass 2 --kernel $(CFG_KERNEL) $(INCLUDES) \
+				-T $(TARGETDIR)/target.tf $(CFG_TABS) $(filter %.arxml,$^)
+
+#  既存Os_Cfg.hとpass2で生成したOs_Cfg_tmp.hとの差分がある場合Os_Cfg.hを上書き
+	if ! cmp Os_Cfg.h Os_Cfg_tmp.h >/dev/null 2>&1 ; then \
+		mv Os_Cfg_tmp.h Os_Cfg.h ;\
+	else \
+		rm Os_Cfg_tmp.h ;\
+	fi
+ifdef KERNEL_LIB
+	if ! cmp Os_Cfg.h $(KERNEL_LIB)/Os_Cfg.h >/dev/null 2>&1 ; then \
+		echo Config files Os_Cfg.h and $(KERNEL_LIB)/Os_Cfg.h differ! ;\
+		diff -c Os_Cfg.h $(KERNEL_LIB)/Os_Cfg.h ;\
+		false;\
+	fi
+endif
+
+	touch -r Os_Lcfg.c Os_Lcfg.timestamp
+
+#
+#  カーネルライブラリファイルの生成
+#
+libkernel.a: $(OFFSET_H) $(KERNEL_LIB_OBJS)
+	rm -f libkernel.a
+	$(AR) -rcs libkernel.a $(KERNEL_LIB_OBJS)
+	$(RANLIB) libkernel.a
+
+#
+#  特別な依存関係の定義
+#
+banner.o: Os_Lcfg.timestamp $(filter-out banner.o,$(ALL_OBJS)) $(LIBS_DEP)
+
+#
+#  全体のリンク
+#
+$(OBJFILE): $(APPL_CFG_INPUT) Os_Lcfg.timestamp $(ALL_OBJS) $(LIBS_DEP)
+	$(LINK) $(CFLAGS) $(LDFLAGS) -o $(OBJFILE) $(START_OBJS) \
+			-Wl,-Map,$(OBJNAME).map \
+			$(APPL_OBJS) $(SYSMOD_OBJS) $(CFG_OBJS) $(ALL_LIBS) $(END_OBJS)
+	$(NM) -n $(OBJFILE) > $(OBJNAME).syms
+	$(OBJCOPY) -O srec -S $(OBJFILE) $(OBJNAME).srec
+	$(CFG) --pass 3 --kernel $(CFG_KERNEL) $(INCLUDES) \
+				--rom-image $(OBJNAME).srec --symbol-table $(OBJNAME).syms \
+				-T $(TARGETDIR)/target_check.tf $(CFG_TABS) $(filter %.arxml,$^)
+	$(OBJDUMP) -d $(OBJFILE) > $(OBJNAME).dump
+
+#
+#  バイナリファイルの生成
+#
+$(OBJNAME).bin: $(OBJFILE)
+	$(OBJCOPY) -O binary -S $(OBJFILE) $(OBJNAME).bin
+
+#
+#  Sレコードファイルの生成
+#
+$(OBJNAME).srec: $(OBJFILE)
+	$(OBJCOPY) -O srec -S $(OBJFILE) $(OBJNAME).srec
+
+#
+#  コンパイル結果の消去
+#
+.PHONY: clean
+clean:
+	rm -f \#* *~ *.o $(CLEAN_FILES)
+	rm -f $(OBJFILE) $(OBJNAME).syms $(OBJNAME).srec $(OBJNAME).bin $(OBJNAME).map
+	rm -f Os_Lcfg.timestamp $(CFG2_OUT)
+	rm -f cfg2_out.tf
+	rm -f cfg1_out.c $(CFG1_OUT) cfg1_out.syms cfg1_out.srec
+	rm -f $(OBJNAME).dump
+	rm -f kernel.res
+	rm -f hw.flash hw_sw.hex sw.flash hw.flash hw_sw.flash
+ifndef KERNEL_LIB
+	rm -f libkernel.a
+endif
+	rm -f offset.h
+
+.PHONY: cleankernel
+cleankernel:
+	rm -rf $(KERNEL_LIB_OBJS)
+	rm -f offset.h
+
+.PHONY: cleandep
+cleandep:
+	if ! [ -f Makefile.depend ]; then \
+		rm -f Os_Lcfg.timestamp $(CFG2_OUT); \
+		rm -f cfg1_out.c cfg1_out.o $(CFG1_OUT) cfg1_out.syms cfg1_out.srec; \
+		rm -f offset.h; \
+	fi
+	rm -f Makefile.depend
+
+.PHONY: realclean
+realclean: cleandep clean
+	rm -f $(REALCLEAN_FILES)
+
+#
+#  ジェネレータが生成したファイルのコンパイルルールと依存関係作成
+#  ルールの定義
+#
+#  ジェネレータが生成したファイルは，アプリケーションプログラム用，シス
+#  テムサービス用，カーネル用のすべてのオプションを付けてコンパイルする．
+#
+OS_LCFG_CFLAGS = $(APPL_CFLAGS) $(SYSMOD_CFLAGS) $(KERNEL_CFLAGS)
+
+$(ALL_CFG_OBJS): %.o: %.c
+	$(CC) -c $(CFLAGS) $(OS_LCFG_CFLAGS) $<
+
+$(ALL_CFG_OBJS:.o=.s): %.s: %.c
+	$(CC) -S $(CFLAGS) $(OS_LCFG_CFLAGS) $<
+
+$(ALL_CFG_OBJS:.o=.d): %.d: %.c
+	@$(PERL) $(SRCDIR)/utils/makedep -C $(CC) $(MAKEDEP_OPTS) \
+		-O "$(CFLAGS) $(OS_LCFG_CFLAGS)" $< >> Makefile.depend
+
+#
+#  特殊な依存関係作成ルールの定義
+#
+cfg1_out.depend: $(APPL_CFG_INPUT)
+	@$(CFG) -M cfg1_out.c $(INCLUDES) $< >> Makefile.depend
+
+#
+#  依存関係ファイルの生成
+#
+.PHONY: gendepend
+gendepend:
+	@echo "Generating Makefile.depend."
+
+.PHONY: depend
+ifdef KERNEL_LIB
+depend: cleandep Os_Lcfg.timestamp gendepend \
+		cfg1_out.depend cfg1_out.d \
+		$(ALL_OBJS:.o=.d)
+else
+depend: cleandep $(OFFSET_H) Os_Lcfg.timestamp gendepend \
+		cfg1_out.depend cfg1_out.d \
+		$(KERNEL_AUX_COBJS:.o=.d) $(KERNEL_ASMOBJS:.o=.d) \
+		$(KERNEL_COBJS:.o=.d) $(KERNEL_LCSRCS:.c=.d) $(ALL_OBJS:.o=.d)
+endif
+
+#
+#  依存関係ファイルをインクルード
+#
+-include Makefile.depend
+
+#
+#  開発ツールのコマンド名の定義
+#
+ifeq ($(TOOL),gcc)
+  #
+  #  GNU開発環境用
+  #
+  ifdef GCC_TARGET
+    GCC_TARGET_PREFIX = $(GCC_TARGET)-
+  else
+    GCC_TARGET_PREFIX =
+  endif
+  CC = $(GCC_TARGET_PREFIX)gcc
+  CXX = $(GCC_TARGET_PREFIX)g++
+  AS = $(GCC_TARGET_PREFIX)as
+  LD = $(GCC_TARGET_PREFIX)ld
+  AR = $(GCC_TARGET_PREFIX)ar
+  NM = $(GCC_TARGET_PREFIX)nm
+  RANLIB = $(GCC_TARGET_PREFIX)ranlib
+  OBJCOPY = $(GCC_TARGET_PREFIX)objcopy
+  OBJDUMP = $(GCC_TARGET_PREFIX)objdump
+endif
+
+ifdef USE_CXX
+  LINK = $(CXX)
+else
+  LINK = $(CC)
+endif
+
+#
+#  コンパイルルールの定義
+#
+KERNEL_ALL_COBJS = $(KERNEL_COBJS) $(KERNEL_AUX_COBJS)
+
+$(KERNEL_ALL_COBJS): %.o: %.c
+	$(CC) -c $(CFLAGS) $(KERNEL_CFLAGS) $<
+
+$(KERNEL_ALL_COBJS:.o=.s): %.s: %.c
+	$(CC) -S $(CFLAGS) $(KERNEL_CFLAGS) $<
+
+$(KERNEL_LCOBJS): %.o:
+	$(CC) -DTOPPERS_$(*F) -o $@ -c $(CFLAGS) $(KERNEL_CFLAGS) $<
+
+$(KERNEL_LCOBJS:.o=.s): %.s:
+	$(CC) -DTOPPERS_$(*F) -o $@ -S $(CFLAGS) $(KERNEL_CFLAGS) $<
+
+$(KERNEL_ASMOBJS): %.o: %.S
+	$(CC) -c $(CFLAGS) $(KERNEL_CFLAGS) $<
+
+$(SYSMOD_COBJS): %.o: %.c
+	$(CC) -c $(CFLAGS) $(SYSMOD_CFLAGS) $<
+
+$(SYSMOD_COBJS:.o=.s): %.s: %.c
+	$(CC) -S $(CFLAGS) $(SYSMOD_CFLAGS) $<
+
+$(SYSMOD_ASMOBJS): %.o: %.S
+	$(CC) -c $(CFLAGS) $(SYSMOD_CFLAGS) $<
+
+$(APPL_COBJS): %.o: %.c
+	$(CC) -c $(CFLAGS) $(APPL_CFLAGS) $<
+
+$(APPL_COBJS:.o=.s): %.s: %.c
+	$(CC) -S $(CFLAGS) $(APPL_CFLAGS) $<
+
+$(APPL_CXXOBJS): %.o: %.cpp
+	$(CXX) -c $(CFLAGS) $(APPL_CFLAGS) $<
+
+$(APPL_CXXOBJS:.o=.s): %.s: %.cpp
+	$(CXX) -S $(CFLAGS) $(APPL_CFLAGS) $<
+
+$(APPL_ASMOBJS): %.o: %.S
+	$(CC) -c $(CFLAGS) $(APPL_CFLAGS) $<
+
+#
+#  依存関係作成ルールの定義
+#
+$(KERNEL_COBJS:.o=.d): %.d: %.c
+	@$(PERL) $(SRCDIR)/utils/makedep -C $(CC) $(MAKEDEP_OPTS) \
+		-O "$(CFLAGS) $(KERNEL_CFLAGS)" $< >> Makefile.depend
+
+$(KERNEL_LCSRCS:.c=.d): %.d: %.c
+	@$(PERL) $(SRCDIR)/utils/makedep -C $(CC) $(MAKEDEP_OPTS) -T "$($*)" \
+		-O "-DALLFUNC $(CFLAGS) $(KERNEL_CFLAGS)" $< >> Makefile.depend
+
+$(KERNEL_ASMOBJS:.o=.d): %.d: %.S
+	@$(PERL) $(SRCDIR)/utils/makedep -C $(CC) $(MAKEDEP_OPTS) \
+		-O "$(CFLAGS) $(KERNEL_CFLAGS)" $< >> Makefile.depend
+
+$(SYSMOD_COBJS:.o=.d): %.d: %.c
+	@$(PERL) $(SRCDIR)/utils/makedep -C $(CC) $(MAKEDEP_OPTS) \
+		-O "$(CFLAGS) $(SYSMOD_CFLAGS)" $< >> Makefile.depend
+
+$(SYSMOD_ASMOBJS:.o=.d): %.d: %.S
+	@$(PERL) $(SRCDIR)/utils/makedep -C $(CC) $(MAKEDEP_OPTS) \
+		-O "$(CFLAGS) $(SYSMOD_CFLAGS)" $< >> Makefile.depend
+
+$(APPL_COBJS:.o=.d): %.d: %.c
+	@$(PERL) $(SRCDIR)/utils/makedep -C $(CC) $(MAKEDEP_OPTS) \
+		-O "$(CFLAGS) $(APPL_CFLAGS)" $< >> Makefile.depend
+
+$(APPL_CXXOBJS:.o=.d): %.d: %.cpp
+	@$(PERL) $(SRCDIR)/utils/makedep -C $(CXX) $(MAKEDEP_OPTS) \
+		-O "$(CFLAGS) $(APPL_CFLAGS)" $< >> Makefile.depend
+
+$(APPL_ASMOBJS:.o=.d): %.d: %.S
+	@$(PERL) $(SRCDIR)/utils/makedep -C $(CC) $(MAKEDEP_OPTS) \
+		-O "$(CFLAGS) $(APPL_CFLAGS)" $< >> Makefile.depend
+
+#
+#  デフォルトコンパイルルールを上書き
+#
+%.o: %.c
+	@echo "*** Default compile rules should not be used."
+	$(CC) -c $(CFLAGS) $<
+
+%.s: %.c
+	@echo "*** Default compile rules should not be used."
+	$(CC) -S $(CFLAGS) $<
+
+%.o: %.cpp
+	@echo "*** Default compile rules should not be used."
+	$(CXX) -c $(CFLAGS) $<
+
+%.s: %.cpp
+	@echo "*** Default compile rules should not be used."
+	$(CXX) -S $(CFLAGS) $<
+
+%.o: %.S
+	@echo "*** Default compile rules should not be used."
+	$(CC) -c $(CFLAGS) $<
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/Rte_Type.h
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/Rte_Type.h	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/Rte_Type.h	(revision 295)
@@ -0,0 +1,59 @@
+/*
+ *  TOPPERS ATK2
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *      Automotive Kernel Version 2
+ *
+ *  Copyright (C) 2013-2014 by Center for Embedded Computing Systems
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2013-2014 by FUJISOFT INCORPORATED, JAPAN
+ *  Copyright (C) 2013-2014 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
+ *  Copyright (C) 2013-2014 by Renesas Electronics Corporation, JAPAN
+ *  Copyright (C) 2013-2014 by Sunny Giken Inc., JAPAN
+ *  Copyright (C) 2013-2014 by TOSHIBA CORPORATION, JAPAN
+ *  Copyright (C) 2013-2014 by Witz Corporation, JAPAN
+ *
+ *  上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
+ *  ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
+ *  変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
+ *  (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
+ *      権表示，この利用条件および下記の無保証規定が，そのままの形でソー
+ *      スコード中に含まれていること．
+ *  (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
+ *      用できる形で再配布する場合には，再配布に伴うドキュメント（利用
+ *      者マニュアルなど）に，上記の著作権表示，この利用条件および下記
+ *      の無保証規定を掲載すること．
+ *  (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
+ *      用できない形で再配布する場合には，次のいずれかの条件を満たすこ
+ *      と．
+ *    (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
+ *        作権表示，この利用条件および下記の無保証規定を掲載すること．
+ *    (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
+ *        報告すること．
+ *  (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
+ *      害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
+ *      また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
+ *      由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
+ *      免責すること．
+ *
+ *  本ソフトウェアは，AUTOSAR（AUTomotive Open System ARchitecture）仕
+ *  様に基づいている．上記の許諾は，AUTOSARの知的財産権を許諾するもので
+ *  はない．AUTOSARは，AUTOSAR仕様に基づいたソフトウェアを商用目的で利
+ *  用する者に対して，AUTOSARパートナーになることを求めている．
+ *
+ *  本ソフトウェアは，無保証で提供されているものである．上記著作権者お
+ *  よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
+ *  に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
+ *  アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
+ *  の責任を負わない．
+ *
+ *  $Id: Rte_Type.h 8482 2014-03-07 03:55:38Z shigihara $
+ */
+
+/*
+ *  サンプル用ヘッダファイル(Rte_Type.hはRTEジェネレータが生成する)
+ */
+
+#ifndef RTE_TYPE_H
+#define RTE_TYPE_H
+
+#endif /* RTE_TYPE_H */
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/cmd_rcb3.c
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/cmd_rcb3.c	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/cmd_rcb3.c	(revision 295)
@@ -0,0 +1,952 @@
+/*
+ *  Copyright (C) 2013-2014 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  $Id: cmd_rcb3_can.c 228 2014-09-12 13:21:15Z honda $
+ */
+
+/*
+
+dl
+
+ER}h
+  SBXBTÌ PS3Rg[/USBQ[pbhUARTÏ·t@[EFA
+  (http://runningele.web.fc2.com/) ÅT|[gµÄ¢éRCB3ÉÎ
+  µÄ¢éD
+
+  UART|[g2ÆCANoRÅR}hðó¯æéD¹p·éÆUART©çÌ
+  R}hÌæè±Úµª­¶·é½ßÓ·é±ÆD
+  
+EN®
+  SÄÌLEDð0.5büúÅ3b_Å³¹éD
+
+E{^Ç
+  ¶EE {^
+   EXeAOÌj
+[gð²®D
+   E{^ð·Æûüw¦íªONC£·ÆOFF
+  ã{^
+   EXeAOðj
+[gÉ·é
+  º{^
+   E[^§äÌQCðúlÉ·é
+  L1/R1
+   Eûüw¦íðON/OFF·éD
+  L2/R2
+   E[^§äÌQCðÏX
+  ~
+   Eu[L
+  ¢
+   EnU[h
+  
+   ECwbhCgØèÖ¦()
+   
+   EMAØèÖ¦(D -> N -> B -> N)
+ */
+//#include "rc.h"
+//#include "cmd_msg.h"
+//#include "uart.h"
+//#include "fcan.h"
+#include "rcb3.h"
+#include "comuart.h"
+
+/*
+ *  OûQÆ
+ */
+static void onMsgUart(void);
+static void onMsgCAN(void);
+static void onMsgPS3(void);
+static void onTimer10m(void);
+static void onTimer50m(void);
+static void onTimer100m(void);
+
+/*
+ *  eíè`
+ */
+
+/*
+ *  j
+[gÌXeAOpxÌúl
+ */
+#define STEER_NEUTRAL_INIT   0
+
+
+/*
+ *  [^QCÌúl
+ */
+#define MOTOR_GAIN_INIT  2
+
+
+/*
+ *  OoÍpÌ|[gÔÆCxgÔ
+ */
+#define RC_OUTPUT_PORT 2
+#define RC_EVENT_OUTPUT_PORT (0x10 << RC_OUTPUT_PORT)
+
+
+/*
+ *  N®Ì{fB[nÌÚ±eXgpÝè
+ */
+#define INIT_BODY_BLINK_COUNT   3 
+#define INIT_BODY_BLINK_CYCLE 500
+
+
+/*
+ *  §äÖAÌÏ
+ */
+float g_steer_neutral = STEER_NEUTRAL_INIT;
+float g_angle = 0;
+float g_speed = 0;
+int   g_speed_gain = MOTOR_GAIN_INIT;
+boolean  g_blinker_l_blink = FALSE;
+boolean  g_blinker_r_blink = FALSE; 
+boolean  g_isBrake = FALSE;  
+
+
+/*
+ *  CANÖA
+ */
+
+/*
+ *  {fB[nÖÌw¦R}hpCANbZ[WID
+ */
+#define BODY_CAN_MSG_ID  16
+
+/*
+ *  óMR}hpCANbZ[WID
+ */
+#define CONT_CMD_CAN_MSG_ID    3
+
+/*
+ *  MÌgCñÌãÀ
+ */
+#define CAN_RETRY_LIMIT 50
+
+/*
+ *  CANÊMðgp·é©ÌtO
+ */
+boolean g_use_can = TRUE;
+
+/*
+ *  CANÊMðÄJ·éñ
+ */
+#define CAN_REUSE_CNT_LIMIT 1000
+
+/*
+ *  CANÊMÄJpÏ
+ */
+int g_can_reuse_cnt = 0;
+
+/*
+ *  CANÖAÌú»
+ */
+void
+can_init(void)
+{
+	/* CAN|[gú» */
+	FCan0InitPort(0);
+
+	/* CAMú» */
+	FcanInit(0);
+
+	/* [{bNXú» */
+	FcanSetMailBoxInfo(0, 0, DIR_SEND, IDE_STD, BODY_CAN_MSG_ID, 0, 0 );
+	FcanSetMailBoxInfo(0, 1, DIR_RECV, IDE_STD, CONT_CMD_CAN_MSG_ID, 0, 0 );
+
+	/* CANX^[g */
+	FcanEnable(0);
+}
+
+/*
+ *  CANbZ[WÌM
+ */
+void
+can_send(uint8 *tx_data, uint8 len)
+{
+	int cnt = 0;
+	STATUS status;
+
+	/* CANÊMâ~óÔÌê */
+	if (!g_use_can) {
+		g_can_reuse_cnt++;
+		if (g_can_reuse_cnt == CAN_REUSE_CNT_LIMIT) {
+			g_use_can = TRUE;
+			g_can_reuse_cnt = 0;
+		} else {
+			return;
+		}
+	}
+
+	while(1){
+		status = FcanSetTxData(0, 0, &tx_data[0], len);
+		if(status != STATUS_OK ) {
+			if (cnt++ > CAN_RETRY_LIMIT) {
+				g_use_can = FALSE;
+				uart_PSendString(RC_OUTPUT_PORT, "CAN connect error! Execute without CAN. \r\n");
+				break;
+			}
+		}else{
+			break;
+		}
+	}
+}
+
+/*
+ *  {fB[ECUÖÌóÔw¦\¢Ì
+ */
+typedef struct {
+	uint8_t headlight1;
+	uint8_t headlight2;
+	uint8_t headlight3;
+	uint8_t breaklamp;
+	uint8_t backlamp;
+	uint8_t buzzer;
+	uint8_t blinker_l;
+	uint8_t blinker_r;
+	uint8_t hazardlamp;
+}BODY_CONT_INFO;
+
+/*
+ *  {fB[ÌACeÌON/OFF}N
+ */
+#define BODY_CONT_ON     1
+#define BODY_CONT_OFF    0
+#define BODY_CONT_BLINK  2
+
+/*
+ *  {fB[ECUÖÌóÔw¦pÏ
+ */
+BODY_CONT_INFO g_body_cont_info;
+
+/*
+ *  üúMÆ·é©
+ */
+boolean g_body_can_msg_cyclic = TRUE;
+
+/*
+ {fB[§äCANbZ[Wdl
+
+ Müú     : 50ms
+ bZ[WID : 16 
+ bZ[W· : 11bit
+
+                  offset  bits   bit assign
+  wbhCg1  :  0  :   1   : 1:ON 0:OFF 
+  wbhCg2  :  1  :   1   : 1:ON 0:OFF 
+  wbhCg3  :  2  :   1   : 1:ON 0:OFF  
+  u[Lv :  3  :   1   : 1:ON 0:OFF  
+  obNv   :  4  :   1   : 1:ON 0:OFF
+  uU[         :  5  :   1   : 1:ON 0:OFF 2:BLINK
+  EBJ[L    :  8  :   2   : 1:ON 0:OFF 2:BLINK
+  EBJ[R    : 10  :   2   : 1:ON 0:OFF 2:BLINK
+  nU[hv : 12  :   1   : 1:ON 0:OFF 2:BLINK     
+ */
+
+void
+body_can_msg_send(void)
+{
+	uint8 tx_data[8];
+	/* OñtÌóÔ */
+	static BODY_CONT_INFO g_pre_body_cont_info;
+
+	/* óÔw¦ÉÏ»ª³¯êÎMµÈ¢ */
+	if (!g_body_can_msg_cyclic){
+		if((g_body_cont_info.headlight1 == g_pre_body_cont_info.headlight1) &&
+		   (g_body_cont_info.headlight2 == g_pre_body_cont_info.headlight2) &&
+		   (g_body_cont_info.headlight3 == g_pre_body_cont_info.headlight3) &&
+		   (g_body_cont_info.breaklamp  == g_pre_body_cont_info.breaklamp) &&
+		   (g_body_cont_info.backlamp   == g_pre_body_cont_info.backlamp) &&
+		   (g_body_cont_info.buzzer     == g_pre_body_cont_info.buzzer) && 
+		   (g_body_cont_info.blinker_l  == g_pre_body_cont_info.blinker_l) &&
+		   (g_body_cont_info.blinker_r  == g_pre_body_cont_info.blinker_r) &&
+		   (g_body_cont_info.hazardlamp == g_pre_body_cont_info.hazardlamp)) {
+			return;
+		}
+	}
+
+	/* MbZ[Wð¶¬ */
+	tx_data[0] = ((g_body_cont_info.headlight1 << 7) &  0x80) | 
+				 ((g_body_cont_info.headlight2 << 6) &  0x40) |
+				 ((g_body_cont_info.headlight3 << 5) &  0x20) |
+				 ((g_body_cont_info.breaklamp  << 4) &  0x10) |
+				 ((g_body_cont_info.backlamp   << 3) &  0x08) |
+				 ((g_body_cont_info.buzzer     << 1) &  0x06);
+
+	tx_data[1] = ((g_body_cont_info.blinker_l  << 6) &  0xc0) | 
+				 ((g_body_cont_info.blinker_r  << 4) &  0x30) | 
+				 ((g_body_cont_info.hazardlamp << 3) &  0x08);
+
+	can_send(tx_data, 2);
+
+	g_pre_body_cont_info = g_body_cont_info;
+}
+
+
+/*
+ *  N®Ì{fB[ÌÚ±mF
+ * 
+ *  SLED_ÅÆuU[ðÂç·D
+ */
+void
+body_check(void)
+{
+	int loop, tcnt;
+	uint8_t status = BODY_CONT_ON;
+
+	for(loop = 0; loop < INIT_BODY_BLINK_COUNT*2; loop++) {
+		g_body_cont_info.headlight1 = status;
+		g_body_cont_info.headlight2 = status;
+		g_body_cont_info.headlight3 = status;
+		g_body_cont_info.breaklamp  = status;
+		g_body_cont_info.backlamp   = status;
+		g_body_cont_info.buzzer     = status;
+		g_body_cont_info.blinker_l  = status;
+		g_body_cont_info.blinker_r  = status;
+
+		body_can_msg_send();
+
+		tcnt = 0;
+		while(1) {
+			rc_WaitEvent(RC_EVENT_TIMER);
+			rc_ClearEvent(RC_EVENT_TIMER);
+			tcnt++;
+			if (tcnt == INIT_BODY_BLINK_CYCLE) {
+				break;
+			}
+		}
+
+		status = (status == BODY_CONT_ON)? BODY_CONT_OFF : BODY_CONT_ON;
+	}
+}
+
+
+/*
+ *  CÖ 
+ */
+void
+cmd_rcb3_Main(void)
+{
+	int tcnt = 0;
+	uint32_t event;
+
+	uart_Init(RC_OUTPUT_PORT, 115200);
+
+	uart_PSendString(RC_OUTPUT_PORT, "Initialize hardware start. \r\n");
+
+	can_init();
+
+	body_check();
+
+	SetServoControlMode(TRUE);
+	SetServoEnable(SERVO_ON);
+	SetSteerAngle(STEER_NEUTRAL_INIT);
+	SetControlParam(1.0f, 1.0f, 0);
+	SetMotorEnable(MOTOR_ON);
+
+	rcb3_Init();
+
+	uart_PSendString(RC_OUTPUT_PORT, "Initialize hardware done. \r\n");
+
+	while (1) {
+		event = rc_WaitEvent(RC_EVENT_CMD_PORT|RC_EVENT_TIMER);
+
+		if (event & RC_EVENT_OUTPUT_PORT) {
+			rc_ClearEvent(RC_EVENT_OUTPUT_PORT);
+			onMsgUart();
+		}
+
+		if (event & RC_EVENT_TIMER) {
+			rc_ClearEvent(RC_EVENT_TIMER);
+			onMsgCAN();
+			tcnt++;
+			if (tcnt % 10 == 0) {
+				onTimer10m();
+			}
+			if (tcnt % 50 == 0) {
+				onTimer50m();
+			}
+			if (tcnt == 100) {
+				tcnt = 0;
+				onTimer100m();
+			}
+		}
+	}
+}
+
+/*
+ *  I¹
+ */
+void
+cmd_rcb3_Exit(void)
+{
+	/* ì®[^ðâ~ */
+	mot_SetOutput(0);
+}
+
+/*
+ *  UART©çÌbZ[WÌóM
+ */
+void
+onMsgUart(void)
+{
+	uint8_t c;
+	while (uart_Get(RC_OUTPUT_PORT, &c, 1)) {
+		/*
+		 * LøÈd¶ðó¯æÁ½êÍCd¶É¶½ðÀ{
+		 */
+		if (rcb3_AddReceivedByte(c)) {
+			onMsgPS3();
+		}
+	}
+}
+
+/*
+ * CAN©çÌbZ[WóM
+ */
+void onMsgCAN(void)
+{
+	uint8 rx_data[8];
+	uint8 rx_size;
+	int   loop;
+	BOOL  result;
+	char str[30];
+
+	FcanGetRxData(0, 1, &rx_data[0], &rx_size);
+	if (rx_size == 0) {
+		return;
+	}
+
+//	sprintf(str, "Can data 0x%x, 0x%x, 0x%x\r\n", rx_data[0], rx_data[1], rx_data[2]);
+//	uart_PSendString(RC_OUTPUT_PORT, str);
+
+	for (loop = 0; loop < rx_size; loop++){
+		result = rcb3_AddReceivedByte(rx_data[loop]);
+	}
+
+	if (result) {
+		onMsgPS3();
+	}
+	else {
+		sprintf(str, "Received Can data Error!\r\n");
+		uart_PSendString(RC_OUTPUT_PORT, str);
+	}
+}
+
+/*
+ *  10müúÅÄÑo³êéD
+ */
+void onTimer10m(void)
+{
+
+}
+
+/*
+ *  50müúÅÄÑo³êéD
+ */
+void onTimer50m(void)
+{
+	/* {fB[nÖÌw¦ðM */
+	body_can_msg_send();
+}
+
+/*
+ *  100müúÅÄÑo³êéD
+ */
+void onTimer100m(void)
+{
+
+}
+
+
+/*
+ *  RoboCar§äCu
+ */
+
+
+/*
+ *  XeAOj
+[gðúlÉ
+ */
+void
+InitSteerNetural(void)
+{
+	char str[30];
+	g_steer_neutral = STEER_NEUTRAL_INIT;
+	SetSteerAngle(g_steer_neutral);
+	sprintf(str, "Set steer neutral = %2.1f \r\n", g_steer_neutral);
+	uart_PSendString(RC_OUTPUT_PORT, str);
+}
+
+/*
+ *  XeAOj
+[gð¶¤É
+ */
+void
+AdjustSteerNeturalL(void)
+{
+	char str[30];
+	if(g_steer_neutral < 30) {
+		g_steer_neutral++;
+		SetSteerAngle(g_steer_neutral);
+		sprintf(str, "Adjust steer neutral = %2.1f \r\n", g_steer_neutral);
+		uart_PSendString(RC_OUTPUT_PORT, str);
+	}
+}
+
+/*
+ *  XeAOj
+[gðE¤É
+ */
+void
+AdjustSteerNeturalR(void)
+{
+	char str[30];
+	if(g_steer_neutral > -30) {
+		g_steer_neutral--;
+		SetSteerAngle(g_steer_neutral);
+		sprintf(str, "Adjust steer neutral = %2.1f \r\n", g_steer_neutral);
+		uart_PSendString(RC_OUTPUT_PORT, str);
+	}
+}
+
+
+/*
+ *  Xs[hQCðã°é
+ */
+void
+AdjustSpeedGainU(void)
+{
+	char str[30];
+	if(g_speed_gain < 10) {
+		g_speed_gain++;
+		SetDriveSpeed(g_speed/g_speed_gain);
+		sprintf(str, "Adjust speed gain = %d \r\n", g_speed_gain);
+		uart_PSendString(RC_OUTPUT_PORT, str);
+	}
+}
+
+/*
+ *  Xs[hQCðº°é
+ */
+void
+AdjustSpeedGainD(void)
+{
+	char str[30];
+	if(g_speed_gain > 1) {
+		g_speed_gain--;
+		SetDriveSpeed(g_speed/g_speed_gain);
+		sprintf(str, "Adjust speed gain = %d \r\n", g_speed_gain);
+		uart_PSendString(RC_OUTPUT_PORT, str);
+	}
+}
+
+
+/*
+ *  PS3Rg[ÌAiO{^Ì
+ */
+#define PS3ANALOG_MAX  63
+#define PS3ANALOG_MIN -63
+
+/*
+ *  ¶AiORg[Ì¶E®ì
+ *  XeAOðì 
+ */
+void
+onPS3AnalogL_LR(void)
+{
+	char str[30];
+	float angle;
+	float cur_analog = p_g_cur_ps3analog[NO_PS3ANALOG_L_LR];
+
+	if ((cur_analog <= PS3ANALOG_MAX) && (cur_analog >= PS3ANALOG_MIN)) {
+		angle = -(cur_analog/2);
+		angle += g_steer_neutral;
+		if (angle != g_angle) {
+			g_angle = angle;
+			SetSteerAngle(g_angle);
+			sprintf(str, "Steer angle = %2.1f\r\n", g_angle);
+			uart_PSendString(RC_OUTPUT_PORT, str);
+		}
+	}
+}
+
+/*
+ *  ¶AiORg[Ìãº®ì
+ */
+void
+onPS3AnalogL_UD(void)
+{
+
+}
+
+/*
+ *  EAiORg[Ì¶E®ì
+ */
+void
+onPS3AnalogR_LR(void)
+{
+
+}
+
+/*
+ *  ¶AiORg[Ìãº®ì
+ */
+void
+onPS3AnalogR_UD(void)
+{
+	float speed = 0;
+	char str[30];
+	float cur_analog = p_g_cur_ps3analog[NO_PS3ANALOG_R_UD];
+
+	/* u[L{^ª³êÄ¢êÎobNvÆuU[ðÁ· */
+	if (g_isBrake == TRUE) {
+		g_body_cont_info.backlamp = BODY_CONT_OFF;
+		g_body_cont_info.buzzer   = BODY_CONT_OFF;
+		return;
+	}
+
+	/* Rg[Ìißl©çXs[hðßé */
+	speed = -((cur_analog / 2) * 0.1);
+
+	/* ißlÉÏ»ª Á½ê */
+	if (g_speed != speed) {
+		float abs_g_speed;
+		float abs_speed;
+
+		/*
+		 *  ^u[L
+		 */
+		/* OñißlÆVµ¢ißlÌâÎðßé */
+		abs_g_speed = (g_speed < 0)? -g_speed : g_speed;
+		abs_speed = (speed < 0)? -speed : speed;
+
+		if(abs_g_speed > abs_speed){
+			/* Oñißlæè¸Á½êÍu[LvðON */
+			g_body_cont_info.breaklamp = BODY_CONT_ON;
+		}
+		else {
+			/* OñißlæèÁµ½êÍu[LvðOFF */
+			g_body_cont_info.breaklamp = BODY_CONT_OFF;
+		}
+
+		/*
+		 *  ANZ
+		 */
+		g_speed = speed;
+		SetDriveSpeed(g_speed/g_speed_gain);
+		if (speed < 0){
+			g_body_cont_info.backlamp = BODY_CONT_ON;
+			g_body_cont_info.buzzer   = BODY_CONT_BLINK;
+		}
+		else {
+			g_body_cont_info.backlamp = BODY_CONT_OFF;
+			g_body_cont_info.buzzer   = BODY_CONT_OFF;
+		}
+
+		sprintf(str, "Drive speed = %1.1f\r\n", speed/g_speed_gain);
+		uart_PSendString(RC_OUTPUT_PORT, str);
+	}
+}
+
+/*
+ *  PS3Rg[ÌfW^{^Ì
+ */
+
+#define TOGGLE_ON_OFF(item) item = (item == BODY_CONT_ON)?  BODY_CONT_OFF : BODY_CONT_ON;
+
+/*
+ *  ~ : u[L
+ */
+void
+onPS3ButtonCrossEdgeOn(void) {
+	g_isBrake = TRUE;
+	SetDriveSpeed(0);
+	g_body_cont_info.breaklamp = BODY_CONT_ON;
+}
+
+
+void
+onPS3ButtonCrossEdgeOff(void) {
+	g_isBrake =  FALSE;
+	g_body_cont_info.breaklamp = BODY_CONT_OFF;
+}
+
+/*
+ *  ¢ : nU[h
+ */
+void
+onPS3ButtonTriangleEdgeOn(void) {
+	TOGGLE_ON_OFF(g_body_cont_info.hazardlamp);
+}
+
+void
+onPS3ButtonTriangleEdgeOff(void) {
+
+}
+
+/*
+ *   : CwbhCg(wbhCg1/wbhCg2) ØèÖ¦
+ */
+void
+onPS3ButtonNoughtEdgeOn(void) {
+	TOGGLE_ON_OFF(g_body_cont_info.headlight1);
+	TOGGLE_ON_OFF(g_body_cont_info.headlight2);
+}
+
+void
+onPS3ButtonNoughtEdgeOff(void) {
+
+}
+
+/*
+ *    : tHO(wbhCg3) ØèÖ¦
+ */
+void
+onPS3ButtonSquareEdgeOn(void) {
+	TOGGLE_ON_OFF(g_body_cont_info.headlight3);
+}
+
+void
+onPS3ButtonSquareEdgeOff(void) {
+
+}
+
+/*
+ *  ¶{^ : XeAOÌj
+[gð²®
+ */
+void
+onPS3ButtonLeftEdgeOn(void) {
+	AdjustSteerNeturalL();
+	g_body_cont_info.blinker_l = BODY_CONT_ON;
+}
+
+void
+onPS3ButtonLeftEdgeOff(void) {
+	g_body_cont_info.blinker_l = (g_blinker_l_blink)? BODY_CONT_BLINK : BODY_CONT_OFF;
+}
+
+/*
+ *  E{^ : XeAOÌj
+[gð²®
+ */
+void
+onPS3ButtonRightEdgeOn(void) {
+	AdjustSteerNeturalR();
+	g_body_cont_info.blinker_r = BODY_CONT_ON;
+}
+
+void
+onPS3ButtonRightEdgeOff(void) {
+	g_body_cont_info.blinker_r = (g_blinker_r_blink)? BODY_CONT_BLINK : BODY_CONT_OFF;
+}
+
+/*
+ *  ã{^ : XeAOðj
+[gÉ·é
+ */
+void
+onPS3ButtonUpEdgeOn(void) {
+	InitSteerNetural();
+	g_body_cont_info.blinker_l = BODY_CONT_ON;
+	g_body_cont_info.blinker_r = BODY_CONT_ON;
+}
+
+void
+onPS3ButtonUpEdgeOff(void) {
+	g_body_cont_info.blinker_l = (g_blinker_l_blink)? BODY_CONT_BLINK : BODY_CONT_OFF;
+	g_body_cont_info.blinker_r = (g_blinker_r_blink)? BODY_CONT_BLINK : BODY_CONT_OFF;
+}
+
+/*
+ *  º{^ : [^§äÌQCðúlÉ·é
+ */
+void
+onPS3ButtonDownEdgeOn(void) {
+	char str[30];
+
+	g_speed_gain = MOTOR_GAIN_INIT;
+	SetDriveSpeed(g_speed/g_speed_gain);
+	g_body_cont_info.blinker_l = BODY_CONT_ON;
+	g_body_cont_info.blinker_r = BODY_CONT_ON;
+
+	sprintf(str, "Adjust speed gain = %d \r\n", g_speed_gain);
+	uart_PSendString(RC_OUTPUT_PORT, str);
+}
+
+void
+onPS3ButtonDownEdgeOff(void) {
+	g_body_cont_info.blinker_l = (g_blinker_l_blink)? BODY_CONT_BLINK : BODY_CONT_OFF;
+	g_body_cont_info.blinker_r = (g_blinker_r_blink)? BODY_CONT_BLINK : BODY_CONT_OFF;
+}
+
+
+/*
+ *  L1/R1 : ûüw¦íÌON/OFF
+ */
+void
+onPS3ButtonL1EdgeOn(void){
+	if (g_blinker_l_blink) {
+		g_blinker_l_blink = FALSE;
+		/* {fB[ÖÌw¦ªONÌêÍ¼Ì@\ªONÉµÄ¢é½ß½àµÈ¢ */
+		if (!(g_body_cont_info.blinker_l == BODY_CONT_ON)) {
+			g_body_cont_info.blinker_l = BODY_CONT_OFF;
+		}
+	} else {
+		g_blinker_l_blink = TRUE;
+		/* {fB[ÖÌw¦ªONÌêÍ¼Ì@\ªONÉµÄ¢é½ß½àµÈ¢ */
+		if (!(g_body_cont_info.blinker_l == BODY_CONT_ON)) {
+			g_body_cont_info.blinker_l = BODY_CONT_BLINK;
+		}
+	}
+}
+
+void
+onPS3ButtonL1EdgeOff(void) {
+
+}
+
+void
+onPS3ButtonR1EdgeOn(void){
+	if (g_blinker_r_blink) {
+		g_blinker_r_blink = FALSE;
+		/* {fB[ÖÌw¦ªONÌêÍ¼Ì@\ªONÉµÄ¢é½ß½àµÈ¢ */
+		if (!(g_body_cont_info.blinker_r == BODY_CONT_ON)) {
+			g_body_cont_info.blinker_r = BODY_CONT_OFF;
+		}
+	} else {
+		g_blinker_r_blink = TRUE;
+		/* {fB[ÖÌw¦ªONÌêÍ¼Ì@\ªONÉµÄ¢é½ß½àµÈ¢ */
+		if (!(g_body_cont_info.blinker_r == BODY_CONT_ON)) {
+			g_body_cont_info.blinker_r = BODY_CONT_BLINK;
+		}
+	}
+}
+
+void
+onPS3ButtonR1EdgeOff(void) {
+
+}
+
+/*
+ *  L2/R2 : [^§äÌQCðÏX
+ */
+void
+onPS3ButtonL2EdgeOn(void){
+	AdjustSpeedGainD();
+	g_body_cont_info.blinker_l = BODY_CONT_ON;
+}
+
+void
+onPS3ButtonL2EdgeOff(void){
+	g_body_cont_info.blinker_l = (g_blinker_l_blink)? BODY_CONT_BLINK : BODY_CONT_OFF;
+}
+
+void
+onPS3ButtonR2EdgeOn(void){
+	AdjustSpeedGainU();
+	g_body_cont_info.blinker_r = BODY_CONT_ON;
+}
+
+void
+onPS3ButtonR2EdgeOff(void){
+	g_body_cont_info.blinker_r = (g_blinker_r_blink)? BODY_CONT_BLINK : BODY_CONT_OFF;
+}
+
+
+/*
+ *  {^ÌÏ»oÌ½ßÌ}N
+ */
+#define PS3BUTTON_EDGE_ON(no)  ((p_g_pre_ps3button[no] == FALSE) && (p_g_cur_ps3button[no] == TRUE))
+#define PS3BUTTON_EDGE_OFF(no) ((p_g_pre_ps3button[no] == TRUE) && (p_g_cur_ps3button[no] == FALSE))
+#define PS3ANALOG_CHANGE(no)   (p_g_pre_ps3analog[no] != p_g_cur_ps3analog[no])
+
+/*
+ *  PS3Rg[©çÌCxgÌ
+ */
+void
+onMsgPS3(void) {
+	if (PS3BUTTON_EDGE_OFF(NO_PS3BUTTON_CROSS)){
+		onPS3ButtonCrossEdgeOff();
+	}
+	if (PS3BUTTON_EDGE_ON(NO_PS3BUTTON_TRIANGLE)){
+		onPS3ButtonTriangleEdgeOn();
+	}
+	if (PS3BUTTON_EDGE_OFF(NO_PS3BUTTON_TRIANGLE)){
+		onPS3ButtonTriangleEdgeOff();
+	}
+	if (PS3BUTTON_EDGE_ON(NO_PS3BUTTON_NOUGHT)){
+		onPS3ButtonNoughtEdgeOn();
+	}
+	if (PS3BUTTON_EDGE_OFF(NO_PS3BUTTON_NOUGHT)){
+		onPS3ButtonNoughtEdgeOff();
+	}
+	if (PS3BUTTON_EDGE_ON(NO_PS3BUTTON_SQUARE)){
+		onPS3ButtonSquareEdgeOn();
+	}
+	if (PS3BUTTON_EDGE_OFF(NO_PS3BUTTON_SQUARE)){
+		onPS3ButtonSquareEdgeOff();
+	}
+
+
+	if (PS3BUTTON_EDGE_ON(NO_PS3BUTTON_LEFT)){
+		onPS3ButtonLeftEdgeOn();
+	}
+	if (PS3BUTTON_EDGE_OFF(NO_PS3BUTTON_LEFT)){
+		onPS3ButtonLeftEdgeOff();
+	}
+	if (PS3BUTTON_EDGE_ON(NO_PS3BUTTON_RIGHT)){
+		onPS3ButtonRightEdgeOn();
+	}
+	if (PS3BUTTON_EDGE_OFF(NO_PS3BUTTON_RIGHT)){
+		onPS3ButtonRightEdgeOff();
+	}
+	if (PS3BUTTON_EDGE_ON(NO_PS3BUTTON_UP)){
+		onPS3ButtonUpEdgeOn();
+	}
+	if (PS3BUTTON_EDGE_OFF(NO_PS3BUTTON_UP)){
+		onPS3ButtonUpEdgeOff();
+	}
+	if (PS3BUTTON_EDGE_ON(NO_PS3BUTTON_DOWN)){
+		onPS3ButtonDownEdgeOn();
+	}
+	if (PS3BUTTON_EDGE_OFF(NO_PS3BUTTON_DOWN)){
+		onPS3ButtonDownEdgeOff();
+	}
+	if (PS3BUTTON_EDGE_ON(NO_PS3BUTTON_CROSS)){
+		onPS3ButtonCrossEdgeOn();
+	}
+
+	
+	if (PS3BUTTON_EDGE_ON(NO_PS3BUTTON_L1)){
+		onPS3ButtonL1EdgeOn();
+	}
+	if (PS3BUTTON_EDGE_ON(NO_PS3BUTTON_R1)){
+		onPS3ButtonR1EdgeOn();
+	}
+	
+	if (PS3BUTTON_EDGE_ON(NO_PS3BUTTON_L2)){
+		onPS3ButtonL2EdgeOn();
+	}
+	if (PS3BUTTON_EDGE_OFF(NO_PS3BUTTON_L2)){
+		onPS3ButtonL2EdgeOff();
+	}
+	if (PS3BUTTON_EDGE_ON(NO_PS3BUTTON_R2)){
+		onPS3ButtonR2EdgeOn();
+	}
+	if (PS3BUTTON_EDGE_OFF(NO_PS3BUTTON_R2)){
+		onPS3ButtonR2EdgeOff();
+	}
+	if (PS3ANALOG_CHANGE(NO_PS3ANALOG_L_LR)) {
+		onPS3AnalogL_LR();
+	}
+	if (PS3ANALOG_CHANGE(NO_PS3ANALOG_L_UD)) {
+		onPS3AnalogL_UD();
+	}
+	if (PS3ANALOG_CHANGE(NO_PS3ANALOG_R_LR)) {
+		onPS3AnalogR_LR();
+	}
+	if (PS3ANALOG_CHANGE(NO_PS3ANALOG_R_UD)) {
+		onPS3AnalogR_UD();
+	}
+}
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/comuart.arxml
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/comuart.arxml	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/comuart.arxml	(revision 295)
@@ -0,0 +1,55 @@
+<?xml version="1.0" encoding="EUC-JP"?>
+<!-- Generated by ABREX Ver. 1.0.0 -->
+<AUTOSAR xmlns="http://autosar.org/schema/r4.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://autosar.org/schema/r4.0 AUTOSAR_4-0-3_STRICT.xsd">
+	<AR-PACKAGES>
+		<AR-PACKAGE>
+			<SHORT-NAME>Ecuc</SHORT-NAME>
+			<ELEMENTS>
+				<ECUC-MODULE-CONFIGURATION-VALUES>
+					<SHORT-NAME>Os</SHORT-NAME>
+					<DEFINITION-REF DEST="ECUC-MODULE-DEF">/AUTOSAR/EcucDefs/Os</DEFINITION-REF>
+					<ECUC-DEF-EDITION>4.2.0</ECUC-DEF-EDITION>
+					<IMPLEMENTATION-CONFIG-VARIANT>VARIANT-PRE-COMPILE</IMPLEMENTATION-CONFIG-VARIANT>
+					<CONTAINERS>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>OsInclude</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsInclude</DEFINITION-REF>
+							<PARAMETER-VALUES>
+								<ECUC-TEXTUAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-STRING-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsInclude/OsIncludeFileName</DEFINITION-REF>
+									<VALUE>comuart.h</VALUE>
+								</ECUC-TEXTUAL-PARAM-VALUE>
+							</PARAMETER-VALUES>
+						</ECUC-CONTAINER-VALUE>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>COMUART_Interrupt</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsIsr</DEFINITION-REF>
+							<PARAMETER-VALUES>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsIsr/OsIsrInterruptNumber</DEFINITION-REF>
+									<VALUE>INTNO_COMUART</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsIsr/OsIsrInterruptPriority</DEFINITION-REF>
+									<VALUE>INTPRI_COMUART</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+								<ECUC-TEXTUAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsIsr/OsIsrCategory</DEFINITION-REF>
+									<VALUE>CATEGORY_2</VALUE>
+								</ECUC-TEXTUAL-PARAM-VALUE>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsIsr/OsIsrStackSize</DEFINITION-REF>
+									<VALUE>592</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+							</PARAMETER-VALUES>
+						</ECUC-CONTAINER-VALUE>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>COMUartEvt</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsEvent</DEFINITION-REF>
+						</ECUC-CONTAINER-VALUE>
+					</CONTAINERS>
+				</ECUC-MODULE-CONFIGURATION-VALUES>
+			</ELEMENTS>
+		</AR-PACKAGE>
+	</AR-PACKAGES>
+</AUTOSAR>
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/comuart.c
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/comuart.c	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/comuart.c	(revision 295)
@@ -0,0 +1,249 @@
+#include "Os.h"
+#include "t_stdlib.h"
+#include "prc_sil.h"
+#include "comuart.h"
+
+/*
+ *  WX^ItZbg
+ */
+#define UART_RXDATA_OFFSET	UINT_C(0x00)
+#define UART_TXDATA_OFFSET	UINT_C(0x04)
+#define UART_STATUS_OFFSET	UINT_C(0x08)
+#define UART_CONTROL_OFFSET	UINT_C(0x0c)
+#define UART_DIVISOR_OFFSET	UINT_C(0x10)
+
+/*
+ *  WX^rbgè`
+ */
+#define UART_STATUS_TRDY	UINT_C(0x0040)
+#define UART_STATUS_RRDY	UINT_C(0x0080)
+
+#define UART_CONTROL_ITRDY	UINT_C(0x0040)
+#define UART_CONTROL_IRRDY	UINT_C(0x0080)
+
+/*
+ *  UART
+ */
+#define RxBUFF_SIZE 256
+#define TxBUFF_SIZE 256
+
+static uint8 s_rxbuff[RxBUFF_SIZE];
+static uint8 s_txbuff[TxBUFF_SIZE];
+
+static int s_rxbuff_tail;
+static int s_rxbuff_head;
+static int s_rxbuff_cnt;
+static int s_txbuff_tail;
+static int s_txbuff_head;
+static int s_txbuff_cnt;
+
+static boolean s_do_tx;
+
+
+static void
+ena_rx_int(void){
+	sil_wrw_iop((void *) (COMUART_BASE + UART_CONTROL_OFFSET),
+				sil_rew_iop((void *) (COMUART_BASE + UART_CONTROL_OFFSET))
+				| UART_CONTROL_IRRDY);
+}
+
+static void
+dis_rx_int(void){
+	sil_wrw_iop((void *) (COMUART_BASE + UART_CONTROL_OFFSET),
+				sil_rew_iop((void *) (COMUART_BASE + UART_CONTROL_OFFSET))
+				& ~UART_CONTROL_IRRDY);
+}
+
+static void
+ena_tx_int(void){
+	sil_wrw_iop((void *) (COMUART_BASE + UART_CONTROL_OFFSET),
+				sil_rew_iop((void *) (COMUART_BASE + UART_CONTROL_OFFSET))
+				| UART_CONTROL_ITRDY);
+}
+
+static void
+dis_tx_int(void){
+	sil_wrw_iop((void *) (COMUART_BASE + UART_CONTROL_OFFSET),
+				sil_rew_iop((void *) (COMUART_BASE + UART_CONTROL_OFFSET))
+				& ~UART_CONTROL_ITRDY);
+}
+
+static void
+comuart_putc(unsigned char c){
+	sil_wrw_iop((void *) (COMUART_BASE + UART_TXDATA_OFFSET), (uint32) c);
+}
+
+static unsigned char
+comuart_getc(void){
+	return((uint8) sil_rew_iop((void *) (COMUART_BASE + UART_RXDATA_OFFSET)));
+}
+
+static boolean
+comuart_getready(void)
+{
+	return((sil_rew_iop((void *) (COMUART_BASE + UART_STATUS_OFFSET)) & UART_STATUS_RRDY) != 0U);
+}
+
+static boolean
+comuart_putready(void)
+{
+	return((sil_rew_iop((void *) (COMUART_BASE + UART_STATUS_OFFSET)) & UART_STATUS_TRDY) != 0U);
+}
+
+void
+comuart_pputc(unsigned char c){
+	while(!(comuart_putready())){}
+	comuart_putc(c);
+}
+
+/*
+ * ú»
+ */
+void
+comuart_init(void)
+{
+	/*
+	 *  óMÝÂ
+	 */
+	ena_rx_int();
+}
+
+
+/*
+ * óMµ½f[^· 
+ */
+int
+comuart_get_rxcnt(void)
+{
+	return s_rxbuff_cnt;
+}
+
+/*
+ *  óM 
+ */
+boolean
+comuart_receive(unsigned char *data, int len)
+{
+	boolean result = TRUE;
+	int loop;
+
+	SuspendOSInterrupts();
+	if (s_rxbuff_cnt < len) {
+		result = FALSE;
+	}else {
+		for(loop = 0; loop < len; loop++) {
+			*data++ = s_rxbuff[s_rxbuff_head++];
+			s_rxbuff_head = s_rxbuff_head % RxBUFF_SIZE;
+			s_rxbuff_cnt--;
+		}
+	}
+	ResumeOSInterrupts();
+
+	return result;
+}
+
+/*
+ *  M
+ */
+boolean
+comuart_send(const unsigned char *data, int len)
+{
+	int loop;
+	char c;
+
+	/* ó«ª³¯êÎG[ */
+	if (s_txbuff_cnt + len > TxBUFF_SIZE) {
+		return FALSE;
+	}
+
+	/* Oobt@ÉRs[ */
+	for(loop = 0; loop < len; loop++){
+		s_txbuff[s_txbuff_tail++] = *data++;
+		s_txbuff_tail = s_txbuff_tail % TxBUFF_SIZE;
+		s_txbuff_cnt++;
+	}
+
+	if (!(s_do_tx)) {
+		SuspendOSInterrupts();
+		/* Oobt@©çæèoµM */
+		c = s_txbuff[s_txbuff_head++];
+		s_txbuff_head = s_txbuff_head % TxBUFF_SIZE;
+		s_txbuff_cnt--;
+		s_do_tx = TRUE;
+		comuart_putc(c);
+		ResumeOSInterrupts();
+
+		/* óMÝÂ */
+		if(s_txbuff_cnt > 0){
+		  ena_tx_int();
+		}
+	}
+
+	return TRUE;
+}
+
+/*
+ *  UART2Ýnh
+ */
+#define TASK_NONE  0xFFFFFFFF
+static TaskType COMUartWaitTask = TASK_NONE;
+
+/*
+ *  Ýnh
+ */
+ISR(COMUART_Interrupt)
+{
+	char c;
+
+	if (comuart_putready() != FALSE) {
+		/* M */
+		if (s_txbuff_cnt == 0) {
+			/* obt@ªó */
+			s_do_tx = FALSE;
+			dis_tx_int();
+		}
+		else {
+			/* obt@©çf[^ðæèoµoÍ */
+			c = s_txbuff[s_txbuff_head++];
+			s_txbuff_head = s_txbuff_head % TxBUFF_SIZE;
+			s_txbuff_cnt--;
+			comuart_putc(c);
+			s_do_tx = TRUE;
+		}
+	}
+
+	if (comuart_getready() != FALSE) {
+		/* óM */
+		c = comuart_getc();
+
+		if (s_rxbuff_cnt < RxBUFF_SIZE) {
+			s_rxbuff[s_rxbuff_tail++] = c;
+			s_rxbuff_tail = s_rxbuff_tail % RxBUFF_SIZE;
+			s_rxbuff_cnt++;
+		}
+		else {
+			com_error();
+		}
+		
+		if (COMUartWaitTask != TASK_NONE) {
+			SetEvent(COMUartWaitTask, COMUartEvt);
+		}
+	}
+}
+
+/*
+ *  UARTE2ÌCxgÒ¿
+ */
+void
+WaitCOMUartEvent(void) {
+
+	TaskType task_id;
+	GetTaskID(&task_id);
+
+	COMUartWaitTask = task_id;
+	if(comuart_get_rxcnt() == 0) {
+		WaitEvent(COMUartEvt);
+		ClearEvent(COMUartEvt);
+	}
+	COMUartWaitTask = TASK_NONE;
+}
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/comuart.h
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/comuart.h	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/comuart.h	(revision 295)
@@ -0,0 +1,14 @@
+#ifndef _COMUART_H_
+#define _COMUART_H_
+
+#include "de0_nano.h"
+
+extern void comuart_init(void);
+extern void comuart_pputc(unsigned char c);
+extern int  comuart_get_rxcnt(void);
+extern boolean comuart_receive(unsigned char *data, int len);
+extern boolean comuart_send(const unsigned char *data, int len);
+extern void comuart_pputc(unsigned char c);
+extern void WaitCOMUartEvent(void);
+
+#endif  /* _COMUART_H_ */
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/comuart.yaml
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/comuart.yaml	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/comuart.yaml	(revision 295)
@@ -0,0 +1,12 @@
+Ecuc:
+  Os:
+    OsInclude:
+      OsIncludeFileName: comuart.h
+    COMUART_Interrupt:
+      DefinitionRef: OsIsr
+      OsIsrInterruptNumber: INTNO_COMUART
+      OsIsrInterruptPriority: INTPRI_COMUART
+      OsIsrCategory: CATEGORY_2
+      OsIsrStackSize: 0x250
+    COMUartEvt:
+      DefinitionRef: OsEvent  
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/de0_nano.h
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/de0_nano.h	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/de0_nano.h	(revision 295)
@@ -0,0 +1,48 @@
+/*
+ *  DE0-NANOのハードウェアに関する定義
+ */
+#ifndef DE0_NANO_H
+#define DE0_NANO_H
+
+/*
+ * DIPSWのポート 関連
+ */
+#define DIPSW_PIO_BASE 0x08000040
+
+/*
+ * LEDのポート 関連
+ */
+#define LED_PIO_BASE   0x08000030
+
+/*
+ *  ボディー接続のIOポート 関連
+ */
+#define TLU01_PIO_BASE 0x08000080
+
+/*
+ *  通信モジュール接続のUART 関連
+ */
+#define COMUART_BASE   0x02000d40
+#define INTNO_COMUART   7
+#define INTPRI_COMUART  2
+
+/*
+ *  NCES CAN 関連
+ */
+#define CANC_0_BASE		0x08020000U    /* CANコントローラ0のベースアドレス */
+#define CANC_0_INTNO	10             /* 割込み番号 */
+
+#define	DEF_RMB_MAX		( 2 )  /* 受信メールボックス数 */
+#define	DEF_TMB_MAX		( 2 )  /* 送信メールボックス数 */
+
+
+/*
+ *  PWM関連
+ */
+#define PWM_CLK_MH 60
+#define PWM_BASE      0x080000a0
+#define PWM_MAX_ADDR  (PWM_BASE + 0x04)
+#define PWM1_ADDR     (PWM_BASE + 0x08)
+#define PWM2_ADDR     (PWM_BASE + 0x0c)
+
+#endif /* DE0_NANO_H */
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/gdbini
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/gdbini	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/gdbini	(revision 295)
@@ -0,0 +1,3 @@
+target remote localhost:1234
+load
+c
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/nces_can.arxml
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/nces_can.arxml	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/nces_can.arxml	(revision 295)
@@ -0,0 +1,51 @@
+<?xml version="1.0" encoding="EUC-JP"?>
+<!-- Generated by ABREX Ver. 1.0.0 -->
+<AUTOSAR xmlns="http://autosar.org/schema/r4.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://autosar.org/schema/r4.0 AUTOSAR_4-0-3_STRICT.xsd">
+	<AR-PACKAGES>
+		<AR-PACKAGE>
+			<SHORT-NAME>Ecuc</SHORT-NAME>
+			<ELEMENTS>
+				<ECUC-MODULE-CONFIGURATION-VALUES>
+					<SHORT-NAME>Os</SHORT-NAME>
+					<DEFINITION-REF DEST="ECUC-MODULE-DEF">/AUTOSAR/EcucDefs/Os</DEFINITION-REF>
+					<ECUC-DEF-EDITION>4.2.0</ECUC-DEF-EDITION>
+					<IMPLEMENTATION-CONFIG-VARIANT>VARIANT-PRE-COMPILE</IMPLEMENTATION-CONFIG-VARIANT>
+					<CONTAINERS>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>OsInclude</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsInclude</DEFINITION-REF>
+							<PARAMETER-VALUES>
+								<ECUC-TEXTUAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-STRING-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsInclude/OsIncludeFileName</DEFINITION-REF>
+									<VALUE>nces_can.h</VALUE>
+								</ECUC-TEXTUAL-PARAM-VALUE>
+							</PARAMETER-VALUES>
+						</ECUC-CONTAINER-VALUE>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>Ncan_ISR</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsIsr</DEFINITION-REF>
+							<PARAMETER-VALUES>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsIsr/OsIsrInterruptNumber</DEFINITION-REF>
+									<VALUE>10</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsIsr/OsIsrInterruptPriority</DEFINITION-REF>
+									<VALUE>1</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsIsr/OsIsrStackSize</DEFINITION-REF>
+									<VALUE>4096</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+								<ECUC-TEXTUAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsIsr/OsIsrCategory</DEFINITION-REF>
+									<VALUE>CATEGORY_2</VALUE>
+								</ECUC-TEXTUAL-PARAM-VALUE>
+							</PARAMETER-VALUES>
+						</ECUC-CONTAINER-VALUE>
+					</CONTAINERS>
+				</ECUC-MODULE-CONFIGURATION-VALUES>
+			</ELEMENTS>
+		</AR-PACKAGE>
+	</AR-PACKAGES>
+</AUTOSAR>
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/nces_can.c
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/nces_can.c	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/nces_can.c	(revision 295)
@@ -0,0 +1,350 @@
+/*----------------------------------------------------------------------
+	INCLUDE
+----------------------------------------------------------------------*/
+#include "Os.h"
+#include "nces_can.h"
+#include "rc_car.h"
+
+#define	NULL				( 0 )
+
+/* ID^Cv */
+typedef uint32 TYPE_ID;
+
+typedef struct {
+	TYPE_ID		recv_id;		/* óMµ½ID */
+	uint8 mask;			/* }XNp^[ */
+	uint8 enable;		/* bZ[Wobt@Lø³ø */
+	uint8 len;			/* bZ[Wf[^· */
+	uint8 data[8];		/* óMf[^ */
+} TYPE_RMB_INFO;
+
+typedef struct {
+	TYPE_ID		set_id;			/* Ýèµ½ID */
+	uint8 mask;			/* }XNp^[ */
+	uint8 enable;		/* bZ[Wobt@Lø³ø */
+	uint8 len;			/* bZ[Wf[^· */
+	uint8 data[8];		/* óMf[^ */
+} TYPE_TMB_INFO;
+
+static TYPE_RMB_INFO  g_RMB_INFO[DEF_RMB_MAX];
+static TYPE_TMB_INFO  g_TMB_INFO[DEF_TMB_MAX];
+
+STATUS
+NcanInit(uint8 no)
+{
+	uint16 j, k;
+
+	for( j = 0; j < DEF_RMB_MAX; j++ )
+	{
+		g_RMB_INFO[j].recv_id		= 0;
+		g_RMB_INFO[j].mask			= 0;
+		g_RMB_INFO[j].enable		= 0;
+		g_RMB_INFO[j].len			= 0;
+		for( k = 0; k < 8; k++ )
+		{
+			g_RMB_INFO[j].data[k]	= 0;
+		}
+	}
+
+	for( j = 0; j < DEF_TMB_MAX; j++ )
+	{
+		g_TMB_INFO[j].set_id		= 0;
+		g_TMB_INFO[j].mask			= 0;
+		g_TMB_INFO[j].enable		= 0;
+		g_TMB_INFO[j].len			= 0;
+		for( k = 0; k < 8; k++ )
+		{
+			g_RMB_INFO[j].data[k]	= 0;
+		}
+	}
+
+	/* Rg[ðâ~óÔÅú» */
+	CANC_WR_MODE_REG(CANC_MODE_STOP);
+
+	/* ÝÂ */
+//	CANC_WR_IRQ_EN_REG(IRQ_SET_ENABLE);
+	CANC_WR_IRQ_EN_REG(0x03);
+
+	/* ANZv^XtB^ÌÝè */
+	/* SÌÌANZv^XR[hWX^(SÄÂ)ÌÝè */
+	CANC_WR_ACCEPTANCE_CODE_REG(0xFFFFFFFFU);
+
+	/* SÌÌANZv^X}XNWX^(SÄÂ)ÌÝè */
+	CANC_WR_ACCEPTANCE_MASK_REG(0xFFFFFFFFU);
+
+	/* WX^Ìú» */
+	/* ¢MÌbZ[WðLZ·é */
+	CANC_WR_TXABORT_REG(TXABORT_CLEAR);
+
+	/* G[JE^WX^Ìlðú»·é(MAóMÆàÉlª0Å³¢êAóMG[JE^ÌÏXÍsÂ) */
+	CANC_WR_ERROR_CNT_REG(ERROR_CNT_CLEAR);
+
+	/* ZtóMvWX^ðóMvð³µÉ·é */
+	CANC_WR_RXSELFREQ_REG(RXSELFREQ_CLEAR);
+
+	/* óMEFCgWX^ðEFCgItÉ·é */
+	CANC_WR_RXWAIT_REG(RXWAIT_OFF);
+
+	/* M®¹WX^ðM¢®¹É·é */
+	CANC_WR_TXCMP_REG(TXCMP_CLEAR);
+
+	/* MLZ®¹WX^ðMLZ¢®¹É·é */
+	CANC_WR_TXABORTCMP_REG(TXABORTCMP_CLEAR);
+
+	/* óM®¹WX^ðóMf[^³µÉ·é */
+	CANC_WR_RXCMP_REG(RXCMP_CLEAR);
+
+	/* óMI[o[CgWX^ðã«¢­¶É·é */
+	CANC_RD_RXOVERWRITE_REG();
+
+	/* óMÝÂWX^ðèÝÂÉ·é */
+	CANC_WR_IRQ_RXEN_REG(IRQ_RXEN_PERMIT);
+
+	/* èÝvWX^ðèÝ¢­¶É·é */
+	/* read·é±ÆÅAlªúl(Ý¢­¶)ÉZbg³êé */
+	CANC_RD_IRQ_REG();
+
+	/* {[[gÌÝè */
+	CANC_WR_CLKDIV_BUSTIM_REG(BAUDRATE_500);
+
+	return( STATUS_OK );
+}
+
+/** [{bNXÝè
+ * @param *mb_num:MBÔ
+ * @param *direction:óMûü DIR_RECV or DIR_SND
+ * @param ide:IDíÊ
+ * @param *id:ID
+ * @param *mask:}XN
+ * @param remote:f[^íÊ
+ * @retval STATUS_OK
+ * @retval STATUS_ERROR
+ */
+STATUS
+NcanSetMailBoxInfo(uint8 no, uint8 mb_num, uint8 direction,
+				   uint8 ide, uint32 id, uint8 mask, uint32 remote){
+	uint32	can_id_reg;
+	if (direction == DIR_RECV) {
+		/* ÎÛðÝè·é */
+		CANC_WR_MBOXWIN_REG(mb_num);
+
+		/* eóMbZ[W{bNXÌANZv^XR[hWX^ÌÝè */
+		can_id_reg = ((uint32) id) << ACCEPTANCE_OFFSET;
+		CANC_WR_RXMBOX_ACCEPTANCE_CODE_REG(can_id_reg);
+
+		/* eóMbZ[W{bNXÌANZv^X}XNWX^ÌÝè */
+		CANC_WR_RXMBOX_ACCEPTANCE_MASK_REG(ACCEPTANCE_MASK);
+	}
+
+	if (direction == DIR_SEND) {
+		g_TMB_INFO[mb_num].set_id = id;
+	}
+
+	return( STATUS_OK );
+}
+
+void
+NcanEnable(uint8 no){
+	CANC_WR_MODE_REG(CANC_MODE_START);
+}
+
+void
+NcanDisable(uint8 no){
+	CANC_WR_MODE_REG(CANC_MODE_STOP);
+}
+
+#include "t_syslog.h"
+#include "t_stdlib.h"
+#include "sysmod/serial.h"
+#include "sysmod/syslog.h"
+
+STATUS
+NcanSetTxData(uint8 no, uint8 mb_num, uint8 id, uint8 *p_data, uint8 len){
+	uint8			i, j;
+	uint32			temp_data1 = 0;         /* f[^(1`4byte)i[p */
+	uint32			temp_data2 = 0;         /* f[^(5`8byte)i[p */
+	uint32			request_bit;
+
+	/* bZ[WÌf[^ª5byteÈãÈçA5byteÚÈ~ðæÉæ¾·é */
+	if (len > BYTE_LENGTH) {
+		/* 5`8byteÌf[^ðRs[·é */
+		for (i = 0U; i < (len - BYTE_LENGTH); i++) {
+			if (i > 0U) {
+				temp_data2 = temp_data2 << 8U;
+			}
+			temp_data2 = (temp_data2 | p_data[len - (1U + i)]);
+		}
+	}
+	else {
+		i = 0U;
+	}
+
+	/* bZ[WÌf[^ª1byteÈãÈçA1byteÚÈ~ðæ¾·é */
+	if (len > 0) {
+		/* 1`4byteÌf[^ðRs[·é */
+		for (j = i; j < len; j++) {
+			if (j > i) {
+				temp_data1 = temp_data1 << 8U;
+			}
+			temp_data1 = (temp_data1 | p_data[len - (1U + j)]);
+		}
+	}
+
+	/* CAN-IDÌi[ */
+	CANC_WR_TXMBOX_DATA0_REG((id << EXTEND_CAN_ID_LENGTH), mb_num);
+
+	/* f[^·Ìi[ */
+	CANC_WR_TXMBOX_DATA1_REG(len, mb_num);
+
+	if (len > 0) {
+		/* f[^(1`4)Ìi[ */
+		CANC_WR_TXMBOX_DATA2_REG(temp_data1, mb_num);
+	}
+	/* f[^ª5byteÈãÈçi[ */
+	if (len > BYTE_LENGTH) {
+		/* f[^(5`8)Ìi[ */
+		CANC_WR_TXMBOX_DATA3_REG(temp_data2, mb_num);
+	}
+
+	SuspendAllInterrupts();
+
+	request_bit = 1U << mb_num;
+	CANC_WR_TXREQ_REG(request_bit);
+
+	ResumeAllInterrupts();
+
+	set_led7(TRUE);
+	return( STATUS_OK );
+}
+
+/*
+ * f[^ðóMµÄ¢È¢êÍp_lenÉ0ðÔ·
+ */
+STATUS
+NcanGetRxData(uint8 no, uint8 mb_num, uint8 *p_data, uint8 *p_len){
+	uint16 j, len;
+	TYPE_RMB_INFO *rmb_info;
+
+	rmb_info = &g_RMB_INFO[mb_num];
+
+	if( mb_num >= DEF_RMB_MAX )
+	{
+		return( STATUS_ERROR );
+	}
+
+	if( p_data == NULL )
+	{
+		return( STATUS_ERROR );
+	}
+	if( p_len == NULL )
+	{
+		return( STATUS_ERROR );
+	}
+
+	len = (*rmb_info).len;
+	(*rmb_info).len = 0;
+
+	for( j = 0;j < len; j++ )
+	{
+		p_data[j] = (*rmb_info).data[j];
+	}
+
+	*p_len = len;
+
+	if(len != 0){
+		set_led0(FALSE);
+	}
+
+	return( STATUS_OK );
+}
+
+static int cnt;
+
+ISR(Ncan_ISR)
+{
+	uint32				irq_reg;
+	uint32				cmp_reg;
+	uint32				clear_bit;
+	uint32				temp_data;
+	uint32				i;
+	uint32				j;
+	uint32				wait_reg;
+	uint8				can_dlc;
+
+	irq_reg = CANC_RD_IRQ_REG();
+
+	/* óM®¹Ý */
+	if ((irq_reg & RECEIVE_IRQ) != 0U) {
+		set_led0(TRUE);
+		clear_bit = 1U;
+		cmp_reg = CANC_RD_RXCMP_REG();
+		if (cmp_reg != 0U) {
+			for (i = 0U; i < DEF_RMB_MAX; i++) {
+				if ((cmp_reg & 1U) != 0U) {
+					/* ÎÛóMEFCgWX^ÌY·érbgðEFCgONÉ·é */
+					wait_reg = CANC_RD_RXWAIT_REG();
+					wait_reg |= clear_bit;
+					CANC_WR_RXWAIT_REG(wait_reg);
+
+					/* CAN-IDæoµ */
+					g_RMB_INFO[i].recv_id = ((CANC_RD_RXMBOX_DATA0_REG(i) & MASK_CAN_ID_MASK) >> EXTEND_CAN_ID_LENGTH);
+
+					/* DLCÌæèoµ */
+					g_RMB_INFO[i].len = (uint8) (CANC_RD_RXMBOX_DATA1_REG(i) & MASK_4BIT);
+					can_dlc = g_RMB_INFO[i].len;
+
+					if (can_dlc > BYTE_LENGTH) {
+						/* 5byteÈãÌêA5byteÚÈ~ÌWX^àÇÝÞ */
+						/* SDU(1`4byte)Ìæèoµ */
+						temp_data = CANC_RD_RXMBOX_DATA2_REG(i);
+						for (j = 0U; j < BYTE_LENGTH; j++) {
+							g_RMB_INFO[i].data[j] = (uint8) (temp_data & MASK_8BIT);
+							temp_data >>= 8U;
+						}
+						/* SDU(5`8byte)Ìæèoµ */
+						temp_data = CANC_RD_RXMBOX_DATA3_REG(i);
+						for (j = BYTE_LENGTH; j < can_dlc; j++) {
+							g_RMB_INFO[i].data[j] = (uint8) (temp_data & MASK_8BIT);
+							temp_data >>= 8U;
+						}
+					}
+					else {
+						/* 4byteÈºÌêA5byteÚÈ~ÌWX^ÍÇÝÜÈ¢ */
+						/* SDU(1`4byte)Ìæèoµ */
+						temp_data = CANC_RD_RXMBOX_DATA2_REG(i);
+						for (j = 0U; j < can_dlc; j++) {
+							g_RMB_INFO[i].data[j] = (uint8) (temp_data & MASK_8BIT);
+							temp_data >>= 8U;
+						}
+					}
+					CANC_WR_RXCMP_REG(clear_bit);
+					/* ÎÛóMEFCgWX^ÌY·érbgðEFCgOFFÉ·é */
+					wait_reg = wait_reg ^ clear_bit;
+					CANC_WR_RXWAIT_REG(wait_reg);
+				}
+				cmp_reg >>= 1U;
+				clear_bit <<= 1U;
+			}
+		}
+	}
+
+	/* M®¹Ý */
+	if ((irq_reg & TRANSMIT_IRQ) != 0U) {
+		set_led7(FALSE);
+		clear_bit = 1U;
+		cmp_reg = CANC_RD_TXCMP_REG();
+		if (cmp_reg != 0U) {
+			for (i = 0U; i < DEF_TMB_MAX; i++) {
+				if ((cmp_reg & 1U) != 0U) {
+					CANC_WR_TXCMP_REG(clear_bit);
+				}
+				cmp_reg >>= 1U;
+				clear_bit <<= 1U;
+			}
+		}
+	}
+
+	if ((irq_reg & 0x80) == 0x80U) {
+		syslog(LOG_NOTICE, "NCAN : buserror! %d", cnt++);
+	}
+}
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/nces_can.h
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/nces_can.h	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/nces_can.h	(revision 295)
@@ -0,0 +1,165 @@
+#ifndef __NCES_CAN_H__
+#define __NCES_CAN_H__
+
+#include "Os.h"
+#include "prc_sil.h"
+#include "de0_nano.h"
+
+/*
+ *  NCES CAN ÌWX^è`
+ */
+#define EXTEND_CAN_ID_LENGTH	18U             /* g£ªÌCAN-ID */
+#define ACCEPTANCE_OFFSET		21U             /* ANZv^XR[hWX^ÌItZbg */
+#define ACCEPTANCE_MASK			0x001FFFFFU     /* ANZv^X}XNWX^ÉÝè·é}XN */
+
+/* [hWX^ */
+#define RESET_MODE			0x00000001U                                                                 /* ®ì[hðRESET_MODEÉ·é */
+#define OPERATING_MODE		0x00000000U                                                                 /* ®ì[hðOPERATING_MODEÉ·é */
+#define LISTEN_ONLY_MODE	0x00000002U                                                                 /* MÖ~ */
+#define NO_LISTEN_ONLY_MODE	0x00000000U                                                                 /* MÂ */
+#define NO_SEND_ACK_MODE	0x00000004U                                                                 /* ACKMÖ~ */
+#define SEND_ACK_MODE		0x00000000U                                                                 /* ACKM */
+#define SINGLE_FILTER_MODE	0x00000008U                                                                 /* Single filter mode */
+#define DUAL_FILTER_MODE	0x00000000U                                                                 /* Dual filter mode */
+#define CANC_MODE_START		(OPERATING_MODE | NO_LISTEN_ONLY_MODE | SEND_ACK_MODE | SINGLE_FILTER_MODE) /* CANRg[ÌSTARTóÔ */
+#define CANC_MODE_STOP		(RESET_MODE     | NO_LISTEN_ONLY_MODE | SEND_ACK_MODE | SINGLE_FILTER_MODE) /* CANRg[ÌSTOPóÔ */
+
+/* Ýv */
+#define RECEIVE_IRQ			0x00000001U     /* óM®¹ */
+#define TRANSMIT_IRQ		0x00000002U     /* M®¹ */
+
+#define IRQ_SET_DISABLE		0x00000000U     /* [ÝÂWX^]SÝvðÖ~ */
+#define IRQ_SET_ENABLE		0x000000FFU     /* [ÝÂWX^]wèÌÝvðÂ */
+#define TXABORT_CLEAR		0x0000FFFFU     /* [MLZWX^]SbZ[W{bNXMLZ */
+#define TXCMP_CLEAR			0x0000FFFFU     /* [M®¹WX^]M®¹rbgNA */
+#define TXABORTCMP_CLEAR	0x0000FFFFU     /* [MLZ®¹WX^]MLZ®¹rbgNA */
+#define RXWAIT_OFF			0x00000000U     /* [óMEFCgWX^]EFCgOFF */
+#define RXCMP_CLEAR			0xFFFFFFFFU     /* [óM®¹WX^]óM®¹rbgNA */
+#define RXSELFREQ_CLEAR		0x00000000U     /* [ZtóMvWX^]óMvÈµ */
+#define ERROR_CNT_CLEAR		0x00000060U     /* [G[JE^WX^]G[JE^ðúlÉ·é */
+#define BAUDRATE_250		0x80007F03U     /* [NbN§äCoX^C~OWX^]{[[g:250kbps */
+#define BAUDRATE_500		0x80007F01U     /* [NbN§äCoX^C~OWX^]{[[g:500kbps */
+#define IRQ_RXEN_PERMIT		0xFFFFFFFFU     /* [óMèÝÂWX^]óMèÝÂ */
+
+#define MASK_CAN_ID_MASK	0x1FFFFFFFU     /* CanIdæ¾}XN */
+#define MASK_4BIT			0x0000000FU     /* 4rbg}XN */
+#define MASK_8BIT			0x000000FFU     /* 8rbg}XN */
+
+/*  */
+/* eWX^ÜÅÌItZbgAhX */
+#define CANC_MODE_REG							0x0000U     /* [h */
+#define CANC_TXREQ_REG							0x0004U
+#define CANC_TXABORT_REG						0x0008U     /* MLZWX^ */
+#define CANC_TXCMP_REG							0x000CU
+#define CANC_TXABORTCMP_REG						0x0010U
+#define CANC_RXWAIT_REG							0x0014U
+#define CANC_RXCMP_REG							0x0018U
+#define CANC_RXOVERWRITE_REG					0x001CU
+#define CANC_RXSELFREQ_REG						0x0020U
+#define CANC_STATUS_REG							0x0024U
+#define CANC_IRQ_REG							0x0028U
+#define CANC_IRQ_EN_REG							0x002CU     /* ÝÂWX^ */
+#define CANC_IRQ_RXEN_REG						0x0030U
+#define CANC_CLKDIV_BUSTIM_REG					0x0034U     /* NbN§äCoX^C~O */
+#define CANC_ACCEPTANCE_CODE_REG				0x0038U     /* ANZv^XR[hWX^ */
+#define CANC_ACCEPTANCE_MASK_REG				0x003CU     /* ANZv^X}XNWX^ */
+#define CANC_ARBITRATION_LOST_CAPTURE_REG		0x0040U
+#define CANC_ERROR_CAPTURE_CODE_REG				0x0044U
+#define CANC_ERROR_CNT_REG						0x0048U
+#define CANC_MBOXWIN_REG						0x004CU     /* bZ[W{bNXEBhEWX^ */
+#define CANC_RXMBOX_ACCEPTANCE_CODE_REG			0x0070U     /* óMbZ[W{bNXÌANZv^XR[hWX^ */
+#define CANC_RXMBOX_ACCEPTANCE_MASK_REG			0x0074U     /* óMbZ[W{bNXÌANZv^X}XNWX^ */
+#define CANC_TXMBOX_DATA0_REG					0x0100U
+#define CANC_TXMBOX_DATA1_REG					0x0104U
+#define CANC_TXMBOX_DATA2_REG					0x0108U
+#define CANC_TXMBOX_DATA3_REG					0x010CU
+#define CANC_RXMBOX_DATA0_REG					0x0200U
+#define CANC_RXMBOX_DATA1_REG					0x0204U
+#define CANC_RXMBOX_DATA2_REG					0x0208U
+#define CANC_RXMBOX_DATA3_REG					0x020CU
+
+#define SIL_REW_IOP_CANC_0_BASE(mem)		sil_rew_iop((void *) (CANC_0_BASE + (mem)))
+#define SIL_WRW_IOP_CANC_0_BASE(mem, data)	sil_wrw_iop((void *) (CANC_0_BASE + (mem)), (data))
+
+/* ÇæèpWX^ANZX}N */
+#define CANC_RD_TXCMP_REG()							SIL_REW_IOP_CANC_0_BASE(CANC_TXCMP_REG)
+#define CANC_RD_TXABORTCMP_REG()					SIL_REW_IOP_CANC_0_BASE(CANC_TXABORTCMP_REG)
+#define CANC_RD_RXWAIT_REG()						SIL_REW_IOP_CANC_0_BASE(CANC_RXWAIT_REG)
+#define CANC_RD_RXCMP_REG()							SIL_REW_IOP_CANC_0_BASE(CANC_RXCMP_REG)
+#define CANC_RD_RXOVERWRITE_REG()					SIL_REW_IOP_CANC_0_BASE(CANC_RXOVERWRITE_REG)
+#define CANC_RD_STATUS_REG()						SIL_REW_IOP_CANC_0_BASE(CANC_STATUS_REG)
+#define CANC_RD_IRQ_REG()							SIL_REW_IOP_CANC_0_BASE(CANC_IRQ_REG)
+#define CANC_RD_CLKDIV_BUSTIM_REG()					SIL_REW_IOP_CANC_0_BASE(CANC_CLKDIV_BUSTIM_REG)
+#define CANC_RD_ERROR_CNT_REG()						SIL_REW_IOP_CANC_0_BASE(CANC_ERROR_CNT_REG)
+#define CANC_RD_RXMBOX_DATA0_REG(box_num)			SIL_REW_IOP_CANC_0_BASE((CANC_RXMBOX_DATA0_REG + (0x0010U * (box_num))))
+#define CANC_RD_RXMBOX_DATA1_REG(box_num)			SIL_REW_IOP_CANC_0_BASE((CANC_RXMBOX_DATA1_REG + (0x0010U * (box_num))))
+#define CANC_RD_RXMBOX_DATA2_REG(box_num)			SIL_REW_IOP_CANC_0_BASE((CANC_RXMBOX_DATA2_REG + (0x0010U * (box_num))))
+#define CANC_RD_RXMBOX_DATA3_REG(box_num)			SIL_REW_IOP_CANC_0_BASE((CANC_RXMBOX_DATA3_REG + (0x0010U * (box_num))))
+
+/* ÝpWX^ANZX}N */
+#define CANC_WR_MODE_REG(data)						SIL_WRW_IOP_CANC_0_BASE(CANC_MODE_REG, data)
+#define CANC_WR_TXREQ_REG(data)						SIL_WRW_IOP_CANC_0_BASE(CANC_TXREQ_REG, data)
+#define CANC_WR_TXABORT_REG(data)					SIL_WRW_IOP_CANC_0_BASE(CANC_TXABORT_REG, data)
+#define CANC_WR_TXCMP_REG(data)						SIL_WRW_IOP_CANC_0_BASE(CANC_TXCMP_REG, data)
+#define CANC_WR_TXABORTCMP_REG(data)				SIL_WRW_IOP_CANC_0_BASE(CANC_TXABORTCMP_REG, data)
+#define CANC_WR_RXWAIT_REG(data)					SIL_WRW_IOP_CANC_0_BASE(CANC_RXWAIT_REG, data)
+#define CANC_WR_RXCMP_REG(data)						SIL_WRW_IOP_CANC_0_BASE(CANC_RXCMP_REG, data)
+#define CANC_WR_RXSELFREQ_REG(data)					SIL_WRW_IOP_CANC_0_BASE(CANC_RXSELFREQ_REG, data)
+#define CANC_WR_IRQ_EN_REG(data)					SIL_WRW_IOP_CANC_0_BASE(CANC_IRQ_EN_REG, data)
+#define CANC_WR_IRQ_RXEN_REG(data)					SIL_WRW_IOP_CANC_0_BASE(CANC_IRQ_RXEN_REG, data)
+#define CANC_WR_CLKDIV_BUSTIM_REG(data)				SIL_WRW_IOP_CANC_0_BASE(CANC_CLKDIV_BUSTIM_REG, data)
+#define CANC_WR_ACCEPTANCE_CODE_REG(data)			SIL_WRW_IOP_CANC_0_BASE(CANC_ACCEPTANCE_CODE_REG, data)
+#define CANC_WR_ACCEPTANCE_MASK_REG(data)			SIL_WRW_IOP_CANC_0_BASE(CANC_ACCEPTANCE_MASK_REG, data)
+#define CANC_WR_ERROR_CNT_REG(data)					SIL_WRW_IOP_CANC_0_BASE(CANC_ERROR_CNT_REG, data)
+#define CANC_WR_MBOXWIN_REG(box_num)				SIL_WRW_IOP_CANC_0_BASE(CANC_MBOXWIN_REG, ((box_num) << 16))
+#define CANC_WR_RXMBOX_ACCEPTANCE_CODE_REG(data)	SIL_WRW_IOP_CANC_0_BASE(CANC_RXMBOX_ACCEPTANCE_CODE_REG, data)
+#define CANC_WR_RXMBOX_ACCEPTANCE_MASK_REG(data)	SIL_WRW_IOP_CANC_0_BASE(CANC_RXMBOX_ACCEPTANCE_MASK_REG, data)
+#define CANC_WR_TXMBOX_DATA0_REG(data, box_num)		SIL_WRW_IOP_CANC_0_BASE((CANC_TXMBOX_DATA0_REG + (0x0010U * (box_num))), data)
+#define CANC_WR_TXMBOX_DATA1_REG(data, box_num)		SIL_WRW_IOP_CANC_0_BASE((CANC_TXMBOX_DATA1_REG + (0x0010U * (box_num))), data)
+#define CANC_WR_TXMBOX_DATA2_REG(data, box_num)		SIL_WRW_IOP_CANC_0_BASE((CANC_TXMBOX_DATA2_REG + (0x0010U * (box_num))), data)
+#define CANC_WR_TXMBOX_DATA3_REG(data, box_num)		SIL_WRW_IOP_CANC_0_BASE((CANC_TXMBOX_DATA3_REG + (0x0010U * (box_num))), data)
+
+/*----------------------------------------------------------------------
+	}Nè`
+----------------------------------------------------------------------*/
+#define	DIR_RECV			( 0 )				/* óMûü */
+#define	DIR_SEND			( 1 )				/* Mûü */
+
+/* Xe[^XÖW */
+#define	STATUS_OK			( 0 )
+#define	STATUS_ERROR		( 1 )
+
+#define	STATUS_READY		( 2 )
+#define	STATUS_SEND			( 3 )
+#define	STATUS_RECV			( 4 )
+
+#define BYTE_LENGTH			( 4 )
+
+
+/*----------------------------------------------------------------------
+	^Cvè`
+----------------------------------------------------------------------*/
+/* Xe[^X */
+typedef uint8 STATUS;
+
+/*----------------------------------------------------------------------
+	vg^Cvé¾
+----------------------------------------------------------------------*/
+extern STATUS NcanInit(uint8 no);
+extern void NcanEnable(uint8 no);
+extern void NcanDisable(uint8 no);
+extern STATUS NcanComStatus(uint8 no);
+extern STATUS NcanSetTxData(uint8 no, uint8 mb_num, uint8 id, uint8 *p_data, uint8 len );
+extern STATUS NcanGetRxData(uint8 no, uint8 mb_num, uint8 *p_data, uint8 *p_len );
+extern STATUS NcanSetMailBoxInfo(uint8 no, uint8 mb_num, uint8 direction,
+								uint8 ide, uint32 id, uint8 mask, uint32 remote);
+
+extern void Ncan0InterruptRx(void);
+extern void Ncan0InterruptTx(void);
+
+/*----------------------------------------------------------------------
+	O[oÏiOQÆj
+----------------------------------------------------------------------*/
+
+#endif /* __NCES_CAN_H__ */
+
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/nces_can.yaml
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/nces_can.yaml	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/nces_can.yaml	(revision 295)
@@ -0,0 +1,10 @@
+Ecuc:
+  Os:
+    OsInclude:
+      OsIncludeFileName: nces_can.h
+    Ncan_ISR:
+      DefinitionRef: OsIsr
+      OsIsrInterruptNumber: 10
+      OsIsrInterruptPriority: 1
+      OsIsrStackSize: 0x1000
+      OsIsrCategory: CATEGORY_2
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/rc_car.arxml
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/rc_car.arxml	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/rc_car.arxml	(revision 295)
@@ -0,0 +1,917 @@
+<?xml version="1.0" encoding="EUC-JP"?>
+<!-- Generated by ABREX Ver. 1.0.0 -->
+<AUTOSAR xmlns="http://autosar.org/schema/r4.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://autosar.org/schema/r4.0 AUTOSAR_4-0-3_STRICT.xsd">
+	<AR-PACKAGES>
+		<AR-PACKAGE>
+			<SHORT-NAME>Ecuc</SHORT-NAME>
+			<ELEMENTS>
+				<ECUC-MODULE-CONFIGURATION-VALUES>
+					<SHORT-NAME>Os</SHORT-NAME>
+					<DEFINITION-REF DEST="ECUC-MODULE-DEF">/AUTOSAR/EcucDefs/Os</DEFINITION-REF>
+					<ECUC-DEF-EDITION>4.2.0</ECUC-DEF-EDITION>
+					<IMPLEMENTATION-CONFIG-VARIANT>VARIANT-PRE-COMPILE</IMPLEMENTATION-CONFIG-VARIANT>
+					<CONTAINERS>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>OsInclude</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsInclude</DEFINITION-REF>
+							<PARAMETER-VALUES>
+								<ECUC-TEXTUAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-STRING-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsInclude/OsIncludeFileName</DEFINITION-REF>
+									<VALUE>rc_car.h</VALUE>
+								</ECUC-TEXTUAL-PARAM-VALUE>
+							</PARAMETER-VALUES>
+						</ECUC-CONTAINER-VALUE>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>AppMode_ALL</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsAppMode</DEFINITION-REF>
+						</ECUC-CONTAINER-VALUE>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>AppMode_Body</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsAppMode</DEFINITION-REF>
+						</ECUC-CONTAINER-VALUE>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>AppMode_Cnt</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsAppMode</DEFINITION-REF>
+						</ECUC-CONTAINER-VALUE>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>AppMode_Ope</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsAppMode</DEFINITION-REF>
+						</ECUC-CONTAINER-VALUE>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>AppMode_Body_Cnt</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsAppMode</DEFINITION-REF>
+						</ECUC-CONTAINER-VALUE>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>AppMode_Body_Ope</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsAppMode</DEFINITION-REF>
+						</ECUC-CONTAINER-VALUE>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>AppMode_Cnt_Ope</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsAppMode</DEFINITION-REF>
+						</ECUC-CONTAINER-VALUE>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>OsOS</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsOS</DEFINITION-REF>
+							<PARAMETER-VALUES>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsOS/OsStackMonitoring</DEFINITION-REF>
+									<VALUE>true</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsOS/OsUseGetServiceId</DEFINITION-REF>
+									<VALUE>true</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsOS/OsUseParameterAccess</DEFINITION-REF>
+									<VALUE>true</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+								<ECUC-TEXTUAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsOS/OsScalabilityClass</DEFINITION-REF>
+									<VALUE>SC1</VALUE>
+								</ECUC-TEXTUAL-PARAM-VALUE>
+								<ECUC-TEXTUAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsOS/OsStatus</DEFINITION-REF>
+									<VALUE>EXTENDED</VALUE>
+								</ECUC-TEXTUAL-PARAM-VALUE>
+							</PARAMETER-VALUES>
+							<SUB-CONTAINERS>
+								<ECUC-CONTAINER-VALUE>
+									<SHORT-NAME>OsHooks</SHORT-NAME>
+									<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsOS/OsHooks</DEFINITION-REF>
+									<PARAMETER-VALUES>
+										<ECUC-NUMERICAL-PARAM-VALUE>
+											<DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>
+											<VALUE>true</VALUE>
+										</ECUC-NUMERICAL-PARAM-VALUE>
+										<ECUC-NUMERICAL-PARAM-VALUE>
+											<DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>
+											<VALUE>true</VALUE>
+										</ECUC-NUMERICAL-PARAM-VALUE>
+										<ECUC-NUMERICAL-PARAM-VALUE>
+											<DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>
+											<VALUE>true</VALUE>
+										</ECUC-NUMERICAL-PARAM-VALUE>
+										<ECUC-NUMERICAL-PARAM-VALUE>
+											<DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>
+											<VALUE>true</VALUE>
+										</ECUC-NUMERICAL-PARAM-VALUE>
+										<ECUC-NUMERICAL-PARAM-VALUE>
+											<DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>
+											<VALUE>true</VALUE>
+										</ECUC-NUMERICAL-PARAM-VALUE>
+										<ECUC-NUMERICAL-PARAM-VALUE>
+											<DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>
+											<VALUE>true</VALUE>
+										</ECUC-NUMERICAL-PARAM-VALUE>
+									</PARAMETER-VALUES>
+								</ECUC-CONTAINER-VALUE>
+								<ECUC-CONTAINER-VALUE>
+									<SHORT-NAME>OsHookStack</SHORT-NAME>
+									<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsOS/OsHookStack</DEFINITION-REF>
+									<PARAMETER-VALUES>
+										<ECUC-NUMERICAL-PARAM-VALUE>
+											<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsOS/OsHookStack/OsHookStackSize</DEFINITION-REF>
+											<VALUE>512</VALUE>
+										</ECUC-NUMERICAL-PARAM-VALUE>
+									</PARAMETER-VALUES>
+								</ECUC-CONTAINER-VALUE>
+							</SUB-CONTAINERS>
+						</ECUC-CONTAINER-VALUE>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>MainEvt</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsEvent</DEFINITION-REF>
+						</ECUC-CONTAINER-VALUE>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>MainTask</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsTask</DEFINITION-REF>
+							<PARAMETER-VALUES>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskActivation</DEFINITION-REF>
+									<VALUE>1U</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskPriority</DEFINITION-REF>
+									<VALUE>14</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskStackSize</DEFINITION-REF>
+									<VALUE>4096</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+								<ECUC-TEXTUAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskSchedule</DEFINITION-REF>
+									<VALUE>FULL</VALUE>
+								</ECUC-TEXTUAL-PARAM-VALUE>
+							</PARAMETER-VALUES>
+							<REFERENCE-VALUES>
+								<ECUC-REFERENCE-VALUE>
+									<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskEventRef</DEFINITION-REF>
+									<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/MainEvt</VALUE-REF>
+								</ECUC-REFERENCE-VALUE>
+								<ECUC-REFERENCE-VALUE>
+									<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskEventRef</DEFINITION-REF>
+									<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/COMUartEvt</VALUE-REF>
+								</ECUC-REFERENCE-VALUE>
+							</REFERENCE-VALUES>
+							<SUB-CONTAINERS>
+								<ECUC-CONTAINER-VALUE>
+									<SHORT-NAME>OsTaskAutostart</SHORT-NAME>
+									<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskAutostart</DEFINITION-REF>
+									<REFERENCE-VALUES>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskAutostart/OsTaskAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_ALL</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskAutostart/OsTaskAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Body</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskAutostart/OsTaskAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Cnt</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskAutostart/OsTaskAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Ope</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskAutostart/OsTaskAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Body_Cnt</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskAutostart/OsTaskAppModeRef</DEFINITION-REF>
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+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskAutostart/OsTaskAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Cnt_Ope</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+									</REFERENCE-VALUES>
+								</ECUC-CONTAINER-VALUE>
+							</SUB-CONTAINERS>
+						</ECUC-CONTAINER-VALUE>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>MainCycArm</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm</DEFINITION-REF>
+							<REFERENCE-VALUES>
+								<ECUC-REFERENCE-VALUE>
+									<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>
+									<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/MAIN_HW_COUNTER</VALUE-REF>
+								</ECUC-REFERENCE-VALUE>
+							</REFERENCE-VALUES>
+							<SUB-CONTAINERS>
+								<ECUC-CONTAINER-VALUE>
+									<SHORT-NAME>OsAlarmAction</SHORT-NAME>
+									<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAction</DEFINITION-REF>
+									<SUB-CONTAINERS>
+										<ECUC-CONTAINER-VALUE>
+											<SHORT-NAME>OsAlarmSetEvent</SHORT-NAME>
+											<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent</DEFINITION-REF>
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+												<ECUC-REFERENCE-VALUE>
+													<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventTaskRef</DEFINITION-REF>
+													<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/MainTask</VALUE-REF>
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+									</SUB-CONTAINERS>
+								</ECUC-CONTAINER-VALUE>
+								<ECUC-CONTAINER-VALUE>
+									<SHORT-NAME>OsAlarmAutostart</SHORT-NAME>
+									<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart</DEFINITION-REF>
+									<PARAMETER-VALUES>
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+											<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAlarmTime</DEFINITION-REF>
+											<VALUE>TICK_FOR_10MS</VALUE>
+										</ECUC-NUMERICAL-PARAM-VALUE>
+										<ECUC-NUMERICAL-PARAM-VALUE>
+											<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmCycleTime</DEFINITION-REF>
+											<VALUE>TICK_FOR_10MS</VALUE>
+										</ECUC-NUMERICAL-PARAM-VALUE>
+										<ECUC-TEXTUAL-PARAM-VALUE>
+											<DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAutostartType</DEFINITION-REF>
+											<VALUE>ABSOLUTE</VALUE>
+										</ECUC-TEXTUAL-PARAM-VALUE>
+									</PARAMETER-VALUES>
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+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_ALL</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Body</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Cnt</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Ope</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Body_Cnt</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Body_Ope</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Cnt_Ope</VALUE-REF>
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+									</REFERENCE-VALUES>
+								</ECUC-CONTAINER-VALUE>
+							</SUB-CONTAINERS>
+						</ECUC-CONTAINER-VALUE>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>RCOperatorTask</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsTask</DEFINITION-REF>
+							<PARAMETER-VALUES>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskActivation</DEFINITION-REF>
+									<VALUE>1U</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskPriority</DEFINITION-REF>
+									<VALUE>2</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskStackSize</DEFINITION-REF>
+									<VALUE>4096</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+								<ECUC-TEXTUAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskSchedule</DEFINITION-REF>
+									<VALUE>FULL</VALUE>
+								</ECUC-TEXTUAL-PARAM-VALUE>
+							</PARAMETER-VALUES>
+							<REFERENCE-VALUES>
+								<ECUC-REFERENCE-VALUE>
+									<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskEventRef</DEFINITION-REF>
+									<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/COMUartEvt</VALUE-REF>
+								</ECUC-REFERENCE-VALUE>
+								<ECUC-REFERENCE-VALUE>
+									<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskEventRef</DEFINITION-REF>
+									<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/RCOperatorEvt</VALUE-REF>
+								</ECUC-REFERENCE-VALUE>
+							</REFERENCE-VALUES>
+							<SUB-CONTAINERS>
+								<ECUC-CONTAINER-VALUE>
+									<SHORT-NAME>OsTaskAutostart</SHORT-NAME>
+									<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskAutostart</DEFINITION-REF>
+									<REFERENCE-VALUES>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskAutostart/OsTaskAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_ALL</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskAutostart/OsTaskAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Ope</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskAutostart/OsTaskAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Body_Ope</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
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+										</ECUC-REFERENCE-VALUE>
+									</REFERENCE-VALUES>
+								</ECUC-CONTAINER-VALUE>
+							</SUB-CONTAINERS>
+						</ECUC-CONTAINER-VALUE>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>RCOperatorEvt</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsEvent</DEFINITION-REF>
+						</ECUC-CONTAINER-VALUE>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>RCOperatorCycArm</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm</DEFINITION-REF>
+							<REFERENCE-VALUES>
+								<ECUC-REFERENCE-VALUE>
+									<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>
+									<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/MAIN_HW_COUNTER</VALUE-REF>
+								</ECUC-REFERENCE-VALUE>
+							</REFERENCE-VALUES>
+							<SUB-CONTAINERS>
+								<ECUC-CONTAINER-VALUE>
+									<SHORT-NAME>OsAlarmAction</SHORT-NAME>
+									<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAction</DEFINITION-REF>
+									<SUB-CONTAINERS>
+										<ECUC-CONTAINER-VALUE>
+											<SHORT-NAME>OsAlarmSetEvent</SHORT-NAME>
+											<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent</DEFINITION-REF>
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+													<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventTaskRef</DEFINITION-REF>
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+													<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventRef</DEFINITION-REF>
+													<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/RCControlEvt</VALUE-REF>
+												</ECUC-REFERENCE-VALUE>
+											</REFERENCE-VALUES>
+										</ECUC-CONTAINER-VALUE>
+									</SUB-CONTAINERS>
+								</ECUC-CONTAINER-VALUE>
+								<ECUC-CONTAINER-VALUE>
+									<SHORT-NAME>OsAlarmAutostart</SHORT-NAME>
+									<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart</DEFINITION-REF>
+									<PARAMETER-VALUES>
+										<ECUC-NUMERICAL-PARAM-VALUE>
+											<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAlarmTime</DEFINITION-REF>
+											<VALUE>TICK_FOR_10MS</VALUE>
+										</ECUC-NUMERICAL-PARAM-VALUE>
+										<ECUC-NUMERICAL-PARAM-VALUE>
+											<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmCycleTime</DEFINITION-REF>
+											<VALUE>TICK_FOR_10MS</VALUE>
+										</ECUC-NUMERICAL-PARAM-VALUE>
+										<ECUC-TEXTUAL-PARAM-VALUE>
+											<DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAutostartType</DEFINITION-REF>
+											<VALUE>ABSOLUTE</VALUE>
+										</ECUC-TEXTUAL-PARAM-VALUE>
+									</PARAMETER-VALUES>
+									<REFERENCE-VALUES>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_ALL</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Cnt</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Body_Cnt</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Cnt_Ope</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+									</REFERENCE-VALUES>
+								</ECUC-CONTAINER-VALUE>
+							</SUB-CONTAINERS>
+						</ECUC-CONTAINER-VALUE>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>RCPowerTrainTask</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsTask</DEFINITION-REF>
+							<PARAMETER-VALUES>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskActivation</DEFINITION-REF>
+									<VALUE>1U</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskPriority</DEFINITION-REF>
+									<VALUE>14</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskStackSize</DEFINITION-REF>
+									<VALUE>4096</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+								<ECUC-TEXTUAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskSchedule</DEFINITION-REF>
+									<VALUE>NON</VALUE>
+								</ECUC-TEXTUAL-PARAM-VALUE>
+							</PARAMETER-VALUES>
+							<REFERENCE-VALUES>
+								<ECUC-REFERENCE-VALUE>
+									<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskEventRef</DEFINITION-REF>
+									<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/RCPowerTrainEvt</VALUE-REF>
+								</ECUC-REFERENCE-VALUE>
+							</REFERENCE-VALUES>
+							<SUB-CONTAINERS>
+								<ECUC-CONTAINER-VALUE>
+									<SHORT-NAME>OsTaskAutostart</SHORT-NAME>
+									<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskAutostart</DEFINITION-REF>
+									<REFERENCE-VALUES>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskAutostart/OsTaskAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_ALL</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskAutostart/OsTaskAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Cnt</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskAutostart/OsTaskAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Body_Cnt</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsTask/OsTaskAutostart/OsTaskAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Cnt_Ope</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+									</REFERENCE-VALUES>
+								</ECUC-CONTAINER-VALUE>
+							</SUB-CONTAINERS>
+						</ECUC-CONTAINER-VALUE>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>RCPowerTrainEvt</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsEvent</DEFINITION-REF>
+						</ECUC-CONTAINER-VALUE>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>RCPowerTrainCycArm</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm</DEFINITION-REF>
+							<REFERENCE-VALUES>
+								<ECUC-REFERENCE-VALUE>
+									<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>
+									<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/MAIN_HW_COUNTER</VALUE-REF>
+								</ECUC-REFERENCE-VALUE>
+							</REFERENCE-VALUES>
+							<SUB-CONTAINERS>
+								<ECUC-CONTAINER-VALUE>
+									<SHORT-NAME>OsAlarmAction</SHORT-NAME>
+									<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAction</DEFINITION-REF>
+									<SUB-CONTAINERS>
+										<ECUC-CONTAINER-VALUE>
+											<SHORT-NAME>OsAlarmSetEvent</SHORT-NAME>
+											<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent</DEFINITION-REF>
+											<REFERENCE-VALUES>
+												<ECUC-REFERENCE-VALUE>
+													<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventTaskRef</DEFINITION-REF>
+													<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/RCPowerTrainTask</VALUE-REF>
+												</ECUC-REFERENCE-VALUE>
+												<ECUC-REFERENCE-VALUE>
+													<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventRef</DEFINITION-REF>
+													<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/RCPowerTrainEvt</VALUE-REF>
+												</ECUC-REFERENCE-VALUE>
+											</REFERENCE-VALUES>
+										</ECUC-CONTAINER-VALUE>
+									</SUB-CONTAINERS>
+								</ECUC-CONTAINER-VALUE>
+								<ECUC-CONTAINER-VALUE>
+									<SHORT-NAME>OsAlarmAutostart</SHORT-NAME>
+									<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart</DEFINITION-REF>
+									<PARAMETER-VALUES>
+										<ECUC-NUMERICAL-PARAM-VALUE>
+											<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAlarmTime</DEFINITION-REF>
+											<VALUE>TICK_FOR_10MS</VALUE>
+										</ECUC-NUMERICAL-PARAM-VALUE>
+										<ECUC-NUMERICAL-PARAM-VALUE>
+											<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmCycleTime</DEFINITION-REF>
+											<VALUE>TICK_FOR_10MS</VALUE>
+										</ECUC-NUMERICAL-PARAM-VALUE>
+										<ECUC-TEXTUAL-PARAM-VALUE>
+											<DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAutostartType</DEFINITION-REF>
+											<VALUE>ABSOLUTE</VALUE>
+										</ECUC-TEXTUAL-PARAM-VALUE>
+									</PARAMETER-VALUES>
+									<REFERENCE-VALUES>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_ALL</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Cnt</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Body_Cnt</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Cnt_Ope</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+									</REFERENCE-VALUES>
+								</ECUC-CONTAINER-VALUE>
+							</SUB-CONTAINERS>
+						</ECUC-CONTAINER-VALUE>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>ActiveLEDCycArm</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm</DEFINITION-REF>
+							<REFERENCE-VALUES>
+								<ECUC-REFERENCE-VALUE>
+									<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>
+									<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/MAIN_HW_COUNTER</VALUE-REF>
+								</ECUC-REFERENCE-VALUE>
+							</REFERENCE-VALUES>
+							<SUB-CONTAINERS>
+								<ECUC-CONTAINER-VALUE>
+									<SHORT-NAME>OsAlarmAction</SHORT-NAME>
+									<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAction</DEFINITION-REF>
+									<SUB-CONTAINERS>
+										<ECUC-CONTAINER-VALUE>
+											<SHORT-NAME>OsAlarmCallback</SHORT-NAME>
+											<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAction/OsAlarmCallback</DEFINITION-REF>
+											<PARAMETER-VALUES>
+												<ECUC-TEXTUAL-PARAM-VALUE>
+													<DEFINITION-REF DEST="ECUC-FUNCTION-NAME-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAction/OsAlarmCallback/OsAlarmCallbackName</DEFINITION-REF>
+													<VALUE>ActiveLEDCycCb</VALUE>
+												</ECUC-TEXTUAL-PARAM-VALUE>
+											</PARAMETER-VALUES>
+										</ECUC-CONTAINER-VALUE>
+									</SUB-CONTAINERS>
+								</ECUC-CONTAINER-VALUE>
+								<ECUC-CONTAINER-VALUE>
+									<SHORT-NAME>OsAlarmAutostart</SHORT-NAME>
+									<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart</DEFINITION-REF>
+									<PARAMETER-VALUES>
+										<ECUC-NUMERICAL-PARAM-VALUE>
+											<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAlarmTime</DEFINITION-REF>
+											<VALUE>TICK_FOR_10MS/100</VALUE>
+										</ECUC-NUMERICAL-PARAM-VALUE>
+										<ECUC-NUMERICAL-PARAM-VALUE>
+											<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmCycleTime</DEFINITION-REF>
+											<VALUE>TICK_FOR_10MS/100</VALUE>
+										</ECUC-NUMERICAL-PARAM-VALUE>
+										<ECUC-TEXTUAL-PARAM-VALUE>
+											<DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAutostartType</DEFINITION-REF>
+											<VALUE>ABSOLUTE</VALUE>
+										</ECUC-TEXTUAL-PARAM-VALUE>
+									</PARAMETER-VALUES>
+									<REFERENCE-VALUES>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_ALL</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Body</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Cnt</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Ope</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Body_Cnt</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Body_Ope</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+										<ECUC-REFERENCE-VALUE>
+											<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsAlarm/OsAlarmAutostart/OsAlarmAppModeRef</DEFINITION-REF>
+											<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/AppMode_Cnt_Ope</VALUE-REF>
+										</ECUC-REFERENCE-VALUE>
+									</REFERENCE-VALUES>
+								</ECUC-CONTAINER-VALUE>
+							</SUB-CONTAINERS>
+						</ECUC-CONTAINER-VALUE>
+					</CONTAINERS>
+				</ECUC-MODULE-CONFIGURATION-VALUES>
+			</ELEMENTS>
+		</AR-PACKAGE>
+	</AR-PACKAGES>
+</AUTOSAR>
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/rc_car.c
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/rc_car.c	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/rc_car.c	(revision 295)
@@ -0,0 +1,1787 @@
+#include "Os.h"
+#include "t_syslog.h"
+#include "t_stdlib.h"
+#include "sysmod/serial.h"
+#include "sysmod/syslog.h"
+#include "rc_car.h"
+
+#include "sysmod/banner.h"
+#include "target_sysmod.h"
+#include "target_serial.h"
+#include "prc_sil.h"
+
+#include "de0_nano.h"
+#include "comuart.h"
+#include "nces_can.h"
+#include "rcb3.h"
+
+/*
+
+○仕様
+
+・コマンド
+  SBXBTの PS3コントローラ/USBゲームパッドUART変換ファームウェア
+  (http://runningele.web.fc2.com/) でサポートしているRCB3に対応
+  している．
+  
+・起動時
+  全てのLEDを0.5秒周期で3秒点滅させる．
+
+・ボタン操舵
+  左・右 ボタン
+   ・ステアリングのニュートラルを調整．
+   ・ボタンを押すと方向指示器がON，離すとOFF
+  上ボタン
+   ・ドライブにする．
+  下ボタン
+   ・リバースににする．
+  L1/R1
+   ・方向指示器をON/OFFする．
+  L2/R2
+   ・モータ制御のゲインを変更
+  ×
+   ・ブレーキ
+  △
+   ・ハザード
+  ○
+   ・メインヘッドライトON/OFF
+  □
+   ・ニュートラルにする．
+ */
+
+/*
+ ボディ系コマンドCANメッセージ仕様
+
+ 送信周期     : 50ms
+ メッセージID : 16 
+ メッセージ長 : 11bit
+
+                  offset  bits   bit assign
+  ヘッドライト1  :  0  :   1   : 1:ON 0:OFF 
+  ヘッドライト2  :  1  :   1   : 1:ON 0:OFF 
+  ヘッドライト3  :  2  :   1   : 1:ON 0:OFF  
+  ブレーキランプ :  3  :   1   : 1:ON 0:OFF  
+  バックランプ   :  4  :   1   : 1:ON 0:OFF
+  ブザー         :  5  :   1   : 1:ON 0:OFF 2:BLINK
+  ウィンカーL    :  8  :   2   : 1:ON 0:OFF 2:BLINK
+  ウィンカーR    : 10  :   2   : 1:ON 0:OFF 2:BLINK
+  ハザードランプ : 12  :   1   : 1:ON 0:OFF 2:BLINK
+
+
+  制御系コマンドCANメッセージ仕様
+
+ 送信周期     : メッセージ到達毎
+ メッセージID : 3
+ メッセージ長 : 64bit
+  
+ */
+
+/*
+ *  各種パラメータ定義
+ */
+
+/*
+ *  CAN関連 : ボディ系コマンド用CANメッセージID
+ */
+#define BODY_CAN_MSG_ID  16
+
+/*
+ *  CAN関連 : 制御系コマンド用CANメッセージID
+ */
+#define CONT_CMD_CAN_MSG_ID    3
+
+/*
+ *  CAN関連 : ボディ系コマンド用CAN送受信メールボックスID
+ */
+#define BODY_CAN_MSG_RMB  1
+#define BODY_CAN_MSG_TMB  1
+
+/*
+ *  CAN関連 : 制御系コマンド用CANメッセージ用CAN送受信メールボックスID
+ */
+#define CONT_CMD_CAN_MSG_RMB  0
+#define CONT_CMD_CAN_MSG_TMB  0
+
+
+/*
+ *  制御系 : ニュートラル時のステアリング角度の初期値
+ */
+#define STEER_NEUTRAL_INIT   0
+
+/*
+ *  制御系 : 起動時のボディー系の接続テスト用設定
+ */
+#define INIT_BODY_BLINK_COUNT      3 
+#define INIT_BODY_BLINK_CYCLE_MS 500
+
+/*
+ *  制御系 : 起動周期
+ */
+#define RC_CONTRL_TASK_CYCLE_MS  10
+
+/*
+ *  制御系 : CAN送信周期
+ */
+#define BODY_CAN_SEND_CYCLE_MS   500
+
+
+#define SPEED_GAIN_INIT 10
+#define SPEED_GAIN_MIN   1
+#define SPEED_GAIN_MAX  20
+
+/*
+ *  未整理
+ */
+
+/*
+ *  内部データバッファ
+ */
+static volatile uint8		command_tbl[8];         /* コマンド引渡しテーブル */
+
+/*
+ *  ファイル名，行番号の参照用の変数
+ */
+extern const char8	*fatal_file_name;   /* ファイル名 */
+extern sint32		fatal_line_num;     /* 行番号 */
+
+/*
+ *  APIエラーログマクロ
+ *
+ *  ErrorHookが有効の場合はErrorHookから
+ *  エラーログを出力し, ErrorHookが無効の場合は
+ *  以下のマクロよりエラーログ出力を行う
+ */
+#if defined(CFG_USE_ERRORHOOK)
+#define error_log(api)	(api)
+#else /* !defined( CFG_USE_ERRORHOOK ) */
+#define	error_log(api)										   \
+	{														   \
+		StatusType ercd;									   \
+		ercd = api;     /* 各API実行 */						   \
+		if (ercd != E_OK) {									   \
+			syslog(LOG_INFO, "Error:%d", atk2_strerror(ercd)); \
+		}													   \
+	}
+#endif /* defined( CFG_USE_ERRORHOOK ) */
+
+void
+set_led(uint8 pattern){
+	sil_wrw_iop((void *)LED_PIO_BASE, pattern);
+}
+
+uint8
+get_dipsw(void){
+	return (uint8)sil_rew_iop((void *)DIPSW_PIO_BASE);
+}
+
+volatile boolean IsBodyOnECU = FALSE;
+volatile boolean IsOpeOnECU  = FALSE;
+volatile boolean IsCntOnECU  = FALSE;
+
+void
+appmode_error(void){
+	volatile int i;
+	uint8 pattern = 0;
+	while(1){
+		for(i = 0; i < 1000000; i++);
+		set_led(pattern);
+		pattern = ~pattern;
+	}
+}
+
+/*
+ *  ユーザメイン関数
+ *
+ *  アプリケーションモードの判断と，カーネル起動
+ */
+sint32
+main(void)
+{
+	AppModeType	crt_app_mode;
+	uint8 dipsw;
+
+	crt_app_mode = AppMode_ALL;
+
+	dipsw = get_dipsw();
+
+	switch (dipsw & 0x7) {
+	  case 0x00:
+		appmode_error();
+		break;
+	  case 0x01:
+		crt_app_mode = AppMode_Body;
+		IsBodyOnECU = TRUE;
+		break;
+	  case 0x02:
+		crt_app_mode = AppMode_Cnt;
+		IsCntOnECU = TRUE;
+		break;
+	  case 0x04:
+		crt_app_mode = AppMode_Ope;
+		IsOpeOnECU = TRUE;
+		break;
+	  case 0x01|0x02:
+		crt_app_mode = AppMode_Body_Cnt;
+		IsBodyOnECU = TRUE;
+		IsCntOnECU = TRUE;
+		break;
+	  case 0x01|0x04:
+		crt_app_mode = AppMode_Body_Ope;
+		IsBodyOnECU = TRUE;
+		IsOpeOnECU = TRUE;
+		break;
+	  case 0x02|0x04:
+		crt_app_mode = AppMode_Cnt_Ope;
+		IsCntOnECU = TRUE;
+		IsOpeOnECU = TRUE;
+		break;
+	  case 0x07:
+		crt_app_mode = AppMode_ALL;
+		IsBodyOnECU = TRUE;
+		IsCntOnECU  = TRUE;
+		IsOpeOnECU  = TRUE;
+		break;
+	  default:
+		appmode_error();
+		break;
+	}
+
+	/*
+	 *  カーネル起動
+	 */
+	StartOS(crt_app_mode);
+
+	while (1) {
+	}
+}
+
+//////////////////////////////////////////////////////////////////////////
+/*
+ *   
+ *  ボディー制御関連
+ * 
+ */
+
+/*
+ *  ボディーECUへの状態指示構造体
+ */
+typedef struct {
+	uint8 headlight1;
+	uint8 headlight2;
+	uint8 headlight3;
+	uint8 breaklamp;
+	uint8 backlamp;
+	uint8 buzzer;
+	uint8 blinker_l;
+	uint8 blinker_r;
+	uint8 hazardlamp;
+}BODY_CONT_INFO;
+
+/*
+ *  ボディーのアイテムのON/OFFマクロ
+ */
+#define BODY_CONT_ON     1
+#define BODY_CONT_OFF    0
+#define BODY_CONT_BLINK  2
+
+/*
+ *  ボディーECUへの状態指示用変数
+ */
+volatile BODY_CONT_INFO g_body_cont_info;
+
+void
+set_tlu01(unsigned int pattern){
+	sil_wrw_iop((void *)TLU01_PIO_BASE, pattern);
+}
+
+unsigned int
+get_tlu01(void){
+	return (sil_rew_iop((void *)TLU01_PIO_BASE));
+}
+
+/*
+ *  tlu01_set() で指示する値
+ */
+#define BLINKER_L_NO    0
+#define BLINKER_R_NO    1
+#define BREAK_LAMP_NO   2
+#define HEAD_LAMP1_NO   3
+#define HEAD_LAMP2_NO   4  /* 未実装 */
+#define HEAD_LAMP3_NO   5  /* 未実装 */
+#define BACK_LAMP_NO    6
+#define BUZZER_NO       7
+
+#define TLU01_PORT_MIN 0
+#define TLU01_PORT_MAX 7
+
+static const uint8 tlu01_pinfo[8] ={
+	0x01,
+	0x40,
+	0x08|0x20, //BREAK
+	0x04|0x10,  
+	0x10,
+	0x00,
+	0x80,
+	0x02, //BUZZER
+};
+
+void
+tlu01_set(uint8 no, boolean on)
+{
+	uint32 wk;
+	uint16 pattern;
+
+	if (no > TLU01_PORT_MAX) {
+		return;
+	}
+
+	pattern = tlu01_pinfo[no - 1];
+
+	wk = get_tlu01();
+	if (on) {
+		wk |=  pattern;
+	}
+	else {
+		wk &= ~pattern;
+	}
+	set_tlu01(wk);
+}
+
+
+/*
+ *  TLU01との接続の初期化
+ */
+void
+tlu01_init(void)
+{
+	/* 全消灯 */
+	sil_wrw_iop((void *)TLU01_PIO_BASE, 0x00);
+}
+
+#define BLINK_CYCLE_MS 500
+
+volatile int buzzer_state = 0;
+
+void
+UnpackBodyContCanMsg(uint8 *p_rx_data)
+{
+	g_body_cont_info.headlight1 = (p_rx_data[0] & 0x80)? BODY_CONT_ON : BODY_CONT_OFF;
+	g_body_cont_info.headlight2 = (p_rx_data[0] & 0x40)? BODY_CONT_ON : BODY_CONT_OFF;
+	g_body_cont_info.headlight3 = (p_rx_data[0] & 0x20)? BODY_CONT_ON : BODY_CONT_OFF;
+	g_body_cont_info.breaklamp  = (p_rx_data[0] & 0x10)? BODY_CONT_ON : BODY_CONT_OFF;
+	g_body_cont_info.backlamp   = (p_rx_data[0] & 0x08)? BODY_CONT_ON : BODY_CONT_OFF;
+
+	g_body_cont_info.buzzer     = (p_rx_data[0] & 0x06) >> 1;
+	g_body_cont_info.blinker_l  = (p_rx_data[1] & 0xc0) >> 6;
+	g_body_cont_info.blinker_r  = (p_rx_data[1] & 0x30) >> 4;
+	g_body_cont_info.hazardlamp = (p_rx_data[1] & 0x08)? BODY_CONT_ON : BODY_CONT_OFF;
+}
+
+TASK(RCBodyTask){
+	int cnt = 0;
+	uint32 pattern;
+	boolean blink_on = FALSE;
+	uint8 rx_data[8];
+	uint8 rx_size;
+
+	syslog(LOG_NOTICE, "RCBodyTask : Start!");
+
+	tlu01_init();
+
+	while(1){
+		WaitEvent(RCBodyEvt);     /* 10msの作業時間待ち */
+		ClearEvent(RCBodyEvt);
+
+		/*
+		 *  制御系が別ECUならCANからメッセージを取得する．
+		 */
+		if (!IsCntOnECU) {
+			NcanGetRxData(0, BODY_CAN_MSG_RMB, &rx_data[0], &rx_size );
+			if (rx_size != 0) {
+				/* 受信メッセージの解析 */
+				UnpackBodyContCanMsg(rx_data);
+			}
+		}
+
+		pattern = 0;
+
+		/* ON/OFF処理 */
+		pattern |= (g_body_cont_info.headlight1 == BODY_CONT_ON)? tlu01_pinfo[HEAD_LAMP1_NO] : 0x00;
+		pattern |= (g_body_cont_info.breaklamp  == BODY_CONT_ON)? tlu01_pinfo[BREAK_LAMP_NO] : 0x00;
+		pattern |= (g_body_cont_info.backlamp   == BODY_CONT_ON)? tlu01_pinfo[BACK_LAMP_NO] : 0x00;
+		if(g_body_cont_info.hazardlamp == BODY_CONT_OFF){
+			pattern |= (g_body_cont_info.blinker_l  == BODY_CONT_ON)? tlu01_pinfo[BLINKER_L_NO]  : 0x00;
+			pattern |= (g_body_cont_info.blinker_r  == BODY_CONT_ON)? tlu01_pinfo[BLINKER_R_NO]  : 0x00;
+		}
+
+		if(blink_on == TRUE){
+			/* 点滅処理 */
+			if (g_body_cont_info.hazardlamp == BODY_CONT_ON){
+				pattern |= tlu01_pinfo[BLINKER_L_NO]|tlu01_pinfo[BLINKER_R_NO];
+			}else{
+				if (g_body_cont_info.blinker_l == BODY_CONT_BLINK){
+					pattern |= tlu01_pinfo[BLINKER_L_NO];
+				}
+				if (g_body_cont_info.blinker_r == BODY_CONT_BLINK){
+					pattern |= tlu01_pinfo[BLINKER_R_NO];
+				}
+			}
+		}
+
+		if(cnt++ == BLINK_CYCLE_MS/10){
+			cnt = 0;
+			blink_on = (blink_on)? FALSE : TRUE;
+		}
+
+		if(buzzer_state == 1){
+			set_tlu01(pattern|tlu01_pinfo[BUZZER_NO]);
+		}
+		else{
+			set_tlu01(pattern);
+		}
+	}
+}
+
+
+ALARMCALLBACK(BuzzerCycAlmCb)
+{
+	static uint8 buzzer_on = 0;
+	static uint8 pre_buzzer = BODY_CONT_OFF;
+	static uint32 cnt = 0;
+
+	if (pre_buzzer != g_body_cont_info.buzzer){
+		pre_buzzer = g_body_cont_info.buzzer;
+		cnt = 0;
+	}
+
+	if(g_body_cont_info.buzzer == BODY_CONT_ON){
+		cnt++;
+		if (cnt < 500) {
+			if(buzzer_on == 0){
+				buzzer_on = 1;
+				buzzer_state = 1;
+				set_tlu01(get_tlu01() | tlu01_pinfo[BUZZER_NO]);
+			}else{
+				buzzer_on = 0;
+				buzzer_state = 0;
+				set_tlu01(get_tlu01() & ~tlu01_pinfo[BUZZER_NO]);
+			}
+		}
+		if(cnt > 1000){
+			cnt = 0;
+		}
+	}
+	
+}
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////////////
+/*
+ *  操作系関連
+ */
+
+/*
+ *  制御系へのコマンド更新通知用変数(同一ECU時)
+ */
+volatile boolean UpDateCntrolCmd = FALSE;
+
+/*
+ *  操作タスク
+ */
+TASK(RCOperatorTask)
+{
+	unsigned char c;
+	syslog(LOG_INFO, "RCOperatorTask : Start!");
+
+	comuart_init();
+
+	while(1){
+		WaitCOMUartEvent();
+		while(comuart_receive(&c, 1)) {
+			if (rcb3_AddReceivedByte(c)) {
+				UpDateCntrolCmd = TRUE;
+//				syslog(LOG_NOTICE, "%d,%d,%d,%d,%d,%d", g_rcb3_rmsg[1], g_rcb3_rmsg[2], g_rcb3_rmsg[3], g_rcb3_rmsg[4], g_rcb3_rmsg[5], g_rcb3_rmsg[6]);
+				/*
+				 *  RCControlTaskが別ECUの場合はCANで送信
+				 */
+				if (!IsCntOnECU) {
+					NcanSetTxData(0, CONT_CMD_CAN_MSG_TMB, CONT_CMD_CAN_MSG_ID, &g_rcb3_rmsg[0], RCB3_MSG_LEN);
+				}
+			}
+		}
+	}
+}
+
+///////////////////////////////////////////////////////////////////////////////////////////////////////
+/*
+ *
+ *  制御系関連
+ *  
+ */
+
+
+float g_steer_neutral = STEER_NEUTRAL_INIT;
+float g_angle = 0;
+
+typedef enum{
+	SHIFT_N,
+	SHIFT_D,
+	SHIFT_R,
+}SHIFT_STATE;
+
+/*
+ *  制御関連の変数
+ */
+volatile boolean  g_blinker_l_blink = FALSE;
+volatile boolean  g_blinker_r_blink = FALSE;
+volatile boolean  g_isBrake = FALSE;
+volatile int      g_accelerator = 0;
+volatile int      g_speed_gain  = SPEED_GAIN_INIT;
+volatile SHIFT_STATE g_ShiftState = SHIFT_N;
+
+/*
+ *  PS3コントローラのアナログボタンのパラメータ
+ */
+#define PS3ANALOG_MAX  63
+#define PS3ANALOG_MIN -64
+
+
+void
+AdjustSteerNeturalL(void)
+{
+	if(g_steer_neutral < 30) {
+		g_steer_neutral++;
+		g_angle++;
+		syslog(LOG_NOTICE, "Adjust steer neutral = %d.%d", (int)g_steer_neutral, (int)(g_steer_neutral*100) % 100);
+	}
+}
+
+/*
+ *  ステアリングニュートラルを右側に
+ */
+void
+AdjustSteerNeturalR(void)
+{
+	if(g_steer_neutral > -30) {
+		g_steer_neutral--;
+		g_angle--;
+		syslog(LOG_NOTICE, "Adjust steer neutral = %d.%d", (int)g_steer_neutral, (int)(g_steer_neutral*100) % 100);
+	}
+}
+
+/*
+ *  左アナログコントローラの左右動作
+ *  ステアリングを操作 
+ */
+void
+onPS3AnalogL_LR(void)
+{
+	float angle;
+	float cur_analog = p_g_cur_ps3analog[NO_PS3ANALOG_L_LR];
+
+	if ((cur_analog <= PS3ANALOG_MAX) && (cur_analog >= PS3ANALOG_MIN)) {
+		/* 左 30 から 右 -30 範囲 */
+		angle = -(cur_analog/2);
+		angle += g_steer_neutral;
+		if (angle != g_angle) {
+			g_angle = angle;
+			if(g_angle > 0){
+				syslog(LOG_NOTICE, "Steer angle = %d.%d", (int)g_angle, (int)(g_angle*100) % 100);
+			}
+			else {
+				syslog(LOG_NOTICE, "Steer angle = %d.%d", (int)g_angle, (int)(-g_angle*100) % 100);
+			}
+		}
+	}
+}
+
+/*
+ *  左アナログコントローラの上下動作
+ */
+void
+onPS3AnalogL_UD(void)
+{
+
+}
+
+/*
+ *  右アナログコントローラの左右動作
+ */
+void
+onPS3AnalogR_LR(void)
+{
+
+}
+
+/*
+ *  右アナログコントローラの上下動作
+ *  上 - 方向
+ *  下 + 方向   
+ */
+void
+onPS3AnalogR_UD(void)
+{
+	float cur_analog = p_g_cur_ps3analog[NO_PS3ANALOG_R_UD];
+	g_accelerator = cur_analog;
+
+	if(cur_analog <= 0){
+		g_body_cont_info.backlamp = BODY_CONT_OFF;
+		g_body_cont_info.buzzer   = BODY_CONT_OFF;
+	}
+	else {
+//		g_accelerator = -cur_analog;
+//		syslog(LOG_NOTICE, "Curanalog = %d.%d", (int)cur_analog, (int)(-cur_analog*100) % 100);
+		g_body_cont_info.backlamp = BODY_CONT_ON;
+		g_body_cont_info.buzzer   = BODY_CONT_ON;
+	}
+}
+
+/*
+ *  PS3コントローラのデジタルボタン毎の処理
+ */
+
+#define TOGGLE_ON_OFF(item) item = (item == BODY_CONT_ON)?  BODY_CONT_OFF : BODY_CONT_ON;
+
+/*
+ *  × : ブレーキ
+ */
+void
+onPS3ButtonCrossEdgeOn(void) {
+	g_isBrake = TRUE;
+//	SetDriveSpeed(0);
+	g_body_cont_info.breaklamp = BODY_CONT_ON;
+}
+
+
+void
+onPS3ButtonCrossEdgeOff(void) {
+	g_isBrake =  FALSE;
+	g_body_cont_info.breaklamp = BODY_CONT_OFF;
+}
+
+/*
+ *  △ : ハザード
+ */
+void
+onPS3ButtonTriangleEdgeOn(void) {
+	TOGGLE_ON_OFF(g_body_cont_info.hazardlamp);
+}
+
+void
+onPS3ButtonTriangleEdgeOff(void) {
+
+}
+
+/*
+ *  ○ : メインヘッドライト(ヘッドライト1) 切り替え
+ */
+void
+onPS3ButtonNoughtEdgeOn(void) {
+	TOGGLE_ON_OFF(g_body_cont_info.headlight1);
+}
+
+void
+onPS3ButtonNoughtEdgeOff(void) {
+
+}
+
+/*
+ *  □ : ギア切り替え
+ */
+void
+onPS3ButtonSquareEdgeOn(void) {
+	syslog(LOG_NOTICE, "Shift N");
+	g_ShiftState = SHIFT_N;
+	g_body_cont_info.backlamp = BODY_CONT_OFF;
+	g_body_cont_info.buzzer   = BODY_CONT_OFF;
+#if 0
+	TOGGLE_ON_OFF(g_body_cont_info.headlight3);
+#endif
+}
+
+void
+onPS3ButtonSquareEdgeOff(void) {
+
+}
+
+/*
+ *  左ボタン : ステアリングのニュートラルを調整
+ */
+void
+onPS3ButtonLeftEdgeOn(void) {
+	AdjustSteerNeturalL();
+	g_body_cont_info.blinker_l = BODY_CONT_ON;
+}
+
+void
+onPS3ButtonLeftEdgeOff(void) {
+	g_body_cont_info.blinker_l = (g_blinker_l_blink)? BODY_CONT_BLINK : BODY_CONT_OFF;
+}
+
+/*
+ *  右ボタン : ステアリングのニュートラルを調整
+ */
+void
+onPS3ButtonRightEdgeOn(void) {
+	AdjustSteerNeturalR();
+	g_body_cont_info.blinker_r = BODY_CONT_ON;
+}
+
+void
+onPS3ButtonRightEdgeOff(void) {
+	g_body_cont_info.blinker_r = (g_blinker_r_blink)? BODY_CONT_BLINK : BODY_CONT_OFF;
+}
+
+/*
+ *  上ボタン : ステアリングをニュートラルにする
+ */
+void
+onPS3ButtonUpEdgeOn(void) {
+	g_steer_neutral = STEER_NEUTRAL_INIT;
+	g_angle  = STEER_NEUTRAL_INIT;
+	g_body_cont_info.blinker_l = BODY_CONT_ON;
+	g_body_cont_info.blinker_r = BODY_CONT_ON;
+
+#if 0	
+	if(g_isBrake){
+		syslog(LOG_NOTICE, "Shift D");
+		g_ShiftState = SHIFT_D;
+		g_body_cont_info.backlamp = BODY_CONT_OFF;
+		g_body_cont_info.buzzer   = BODY_CONT_OFF;
+	}else{
+		syslog(LOG_NOTICE, "Shift D : error");
+	}
+#endif	
+#if 0
+	InitSteerNetural();
+	g_body_cont_info.blinker_l = BODY_CONT_ON;
+	g_body_cont_info.blinker_r = BODY_CONT_ON;
+#endif
+}
+
+void
+onPS3ButtonUpEdgeOff(void) {
+	g_body_cont_info.blinker_l = (g_blinker_l_blink)? BODY_CONT_BLINK : BODY_CONT_OFF;
+	g_body_cont_info.blinker_r = (g_blinker_r_blink)? BODY_CONT_BLINK : BODY_CONT_OFF;
+}
+
+/*
+ *  下ボタン : モータ制御のゲインを初期値にする
+ */
+void
+onPS3ButtonDownEdgeOn(void) {
+	
+#if 0
+	if(g_isBrake){
+		syslog(LOG_NOTICE, "Shift R");
+		g_ShiftState = SHIFT_R;
+		g_body_cont_info.backlamp = BODY_CONT_ON;
+		g_body_cont_info.buzzer   = BODY_CONT_ON;
+	}else{
+		syslog(LOG_NOTICE, "Shift R : error");
+	}
+#endif
+
+	g_speed_gain  = SPEED_GAIN_INIT;
+	g_body_cont_info.blinker_l = BODY_CONT_ON;
+	g_body_cont_info.blinker_r = BODY_CONT_ON;
+
+#if 0
+	char str[30];
+
+	g_speed_gain = MOTOR_GAIN_INIT;
+	SetDriveSpeed(g_speed/g_speed_gain);
+	g_body_cont_info.blinker_l = BODY_CONT_ON;
+	g_body_cont_info.blinker_r = BODY_CONT_ON;
+
+	sprintf(str, "Adjust speed gain = %d \r\n", g_speed_gain);
+	uart_PSendString(RC_OUTPUT_PORT, str);
+#endif
+}
+
+void
+onPS3ButtonDownEdgeOff(void) {
+#if 0
+	g_body_cont_info.blinker_l = (g_blinker_l_blink)? BODY_CONT_BLINK : BODY_CONT_OFF;
+	g_body_cont_info.blinker_r = (g_blinker_r_blink)? BODY_CONT_BLINK : BODY_CONT_OFF;
+#endif
+}
+
+
+/*
+ *  L1/R1 : 方向指示器のON/OFF
+ */
+void
+onPS3ButtonL1EdgeOn(void){
+	if (g_blinker_l_blink) {
+		g_blinker_l_blink = FALSE;
+		/* ボディーへの指示がONの場合は他の機能がONにしているため何もしない */
+		if (!(g_body_cont_info.blinker_l == BODY_CONT_ON)) {
+			g_body_cont_info.blinker_l = BODY_CONT_OFF;
+		}
+	} else {
+		g_blinker_l_blink = TRUE;
+		/* ボディーへの指示がONの場合は他の機能がONにしているため何もしない */
+		if (!(g_body_cont_info.blinker_l == BODY_CONT_ON)) {
+			g_body_cont_info.blinker_l = BODY_CONT_BLINK;
+		}
+	}
+}
+
+void
+onPS3ButtonL1EdgeOff(void) {
+
+}
+
+void
+onPS3ButtonR1EdgeOn(void){
+	if (g_blinker_r_blink) {
+		g_blinker_r_blink = FALSE;
+		/* ボディーへの指示がONの場合は他の機能がONにしているため何もしない */
+		if (!(g_body_cont_info.blinker_r == BODY_CONT_ON)) {
+			g_body_cont_info.blinker_r = BODY_CONT_OFF;
+		}
+	} else {
+		g_blinker_r_blink = TRUE;
+		/* ボディーへの指示がONの場合は他の機能がONにしているため何もしない */
+		if (!(g_body_cont_info.blinker_r == BODY_CONT_ON)) {
+			g_body_cont_info.blinker_r = BODY_CONT_BLINK;
+		}
+	}
+}
+
+void
+onPS3ButtonR1EdgeOff(void) {
+
+}
+
+/*
+ *  L2/R2 : モータ制御のゲインを変更
+ */
+void
+onPS3ButtonL2EdgeOn(void){
+	if(g_speed_gain > SPEED_GAIN_MIN){
+		g_speed_gain--;
+   }
+	g_body_cont_info.blinker_l = BODY_CONT_ON;
+#if 0
+	AdjustSpeedGainD();
+	g_body_cont_info.blinker_l = BODY_CONT_ON;
+#endif
+}
+
+void
+onPS3ButtonL2EdgeOff(void){
+#if 0
+	g_body_cont_info.blinker_l = (g_blinker_l_blink)? BODY_CONT_BLINK : BODY_CONT_OFF;
+#endif
+}
+
+void
+onPS3ButtonR2EdgeOn(void){
+	if (g_speed_gain < SPEED_GAIN_MAX){
+		g_speed_gain++;
+		g_body_cont_info.blinker_r = BODY_CONT_ON;
+	}
+
+#if 0
+	AdjustSpeedGainU();
+	g_body_cont_info.blinker_r = BODY_CONT_ON;
+#endif
+}
+
+void
+onPS3ButtonR2EdgeOff(void){
+#if 0
+	g_body_cont_info.blinker_r = (g_blinker_r_blink)? BODY_CONT_BLINK : BODY_CONT_OFF;
+#endif
+}
+
+/*
+ *  ボタンの変化検出のためのマクロ
+ */
+#define PS3BUTTON_EDGE_ON(no)  ((p_g_pre_ps3button[no] == FALSE) && (p_g_cur_ps3button[no] == TRUE))
+#define PS3BUTTON_EDGE_OFF(no) ((p_g_pre_ps3button[no] == TRUE) && (p_g_cur_ps3button[no] == FALSE))
+#define PS3ANALOG_CHANGE(no)   (p_g_pre_ps3analog[no] != p_g_cur_ps3analog[no])
+
+/*
+ *  PS3コントローラからのイベントの処理
+ */
+void
+onMsgPS3(void) {
+	if (PS3BUTTON_EDGE_OFF(NO_PS3BUTTON_CROSS)){
+		onPS3ButtonCrossEdgeOff();
+	}
+	if (PS3BUTTON_EDGE_ON(NO_PS3BUTTON_TRIANGLE)){
+		onPS3ButtonTriangleEdgeOn();
+	}
+	if (PS3BUTTON_EDGE_OFF(NO_PS3BUTTON_TRIANGLE)){
+		onPS3ButtonTriangleEdgeOff();
+	}
+	if (PS3BUTTON_EDGE_ON(NO_PS3BUTTON_NOUGHT)){
+		onPS3ButtonNoughtEdgeOn();
+	}
+	if (PS3BUTTON_EDGE_OFF(NO_PS3BUTTON_NOUGHT)){
+		onPS3ButtonNoughtEdgeOff();
+	}
+	if (PS3BUTTON_EDGE_ON(NO_PS3BUTTON_SQUARE)){
+		onPS3ButtonSquareEdgeOn();
+	}
+	if (PS3BUTTON_EDGE_OFF(NO_PS3BUTTON_SQUARE)){
+		onPS3ButtonSquareEdgeOff();
+	}
+
+
+	if (PS3BUTTON_EDGE_ON(NO_PS3BUTTON_LEFT)){
+		onPS3ButtonLeftEdgeOn();
+	}
+	if (PS3BUTTON_EDGE_OFF(NO_PS3BUTTON_LEFT)){
+		onPS3ButtonLeftEdgeOff();
+	}
+	if (PS3BUTTON_EDGE_ON(NO_PS3BUTTON_RIGHT)){
+		onPS3ButtonRightEdgeOn();
+	}
+	if (PS3BUTTON_EDGE_OFF(NO_PS3BUTTON_RIGHT)){
+		onPS3ButtonRightEdgeOff();
+	}
+	if (PS3BUTTON_EDGE_ON(NO_PS3BUTTON_UP)){
+		onPS3ButtonUpEdgeOn();
+	}
+	if (PS3BUTTON_EDGE_OFF(NO_PS3BUTTON_UP)){
+		onPS3ButtonUpEdgeOff();
+	}
+	if (PS3BUTTON_EDGE_ON(NO_PS3BUTTON_DOWN)){
+		onPS3ButtonDownEdgeOn();
+	}
+	if (PS3BUTTON_EDGE_OFF(NO_PS3BUTTON_DOWN)){
+		onPS3ButtonDownEdgeOff();
+	}
+	if (PS3BUTTON_EDGE_ON(NO_PS3BUTTON_CROSS)){
+		onPS3ButtonCrossEdgeOn();
+	}
+
+	if (PS3BUTTON_EDGE_ON(NO_PS3BUTTON_L1)){
+		onPS3ButtonL1EdgeOn();
+	}
+	if (PS3BUTTON_EDGE_ON(NO_PS3BUTTON_R1)){
+		onPS3ButtonR1EdgeOn();
+	}
+	if (PS3BUTTON_EDGE_ON(NO_PS3BUTTON_L2)){
+		onPS3ButtonL2EdgeOn();
+	}
+	if (PS3BUTTON_EDGE_OFF(NO_PS3BUTTON_L2)){
+		onPS3ButtonL2EdgeOff();
+	}
+	if (PS3BUTTON_EDGE_ON(NO_PS3BUTTON_R2)){
+		onPS3ButtonR2EdgeOn();
+	}
+	if (PS3BUTTON_EDGE_OFF(NO_PS3BUTTON_R2)){
+		onPS3ButtonR2EdgeOff();
+	}
+	if (PS3ANALOG_CHANGE(NO_PS3ANALOG_L_LR)) {
+		onPS3AnalogL_LR();
+	}
+	if (PS3ANALOG_CHANGE(NO_PS3ANALOG_L_UD)) {
+		onPS3AnalogL_UD();
+	}
+	if (PS3ANALOG_CHANGE(NO_PS3ANALOG_R_LR)) {
+		onPS3AnalogR_LR();
+	}
+	if (PS3ANALOG_CHANGE(NO_PS3ANALOG_R_UD)) {
+		onPS3AnalogR_UD();
+	}
+}
+
+/*
+ *  周期送信とするか
+ */
+boolean g_body_can_msg_cyclic = FALSE;
+
+
+void
+body_can_msg_send(void)
+{
+	uint8 tx_data[8];
+	/* 前回送付の状態 */
+	static BODY_CONT_INFO g_pre_body_cont_info;
+
+	/* 状態指示に変化が無ければ送信しない */
+	if (!g_body_can_msg_cyclic){
+		if((g_body_cont_info.headlight1 == g_pre_body_cont_info.headlight1) &&
+		   (g_body_cont_info.headlight2 == g_pre_body_cont_info.headlight2) &&
+		   (g_body_cont_info.headlight3 == g_pre_body_cont_info.headlight3) &&
+		   (g_body_cont_info.breaklamp  == g_pre_body_cont_info.breaklamp) &&
+		   (g_body_cont_info.backlamp   == g_pre_body_cont_info.backlamp) &&
+		   (g_body_cont_info.buzzer     == g_pre_body_cont_info.buzzer) && 
+		   (g_body_cont_info.blinker_l  == g_pre_body_cont_info.blinker_l) &&
+		   (g_body_cont_info.blinker_r  == g_pre_body_cont_info.blinker_r) &&
+		   (g_body_cont_info.hazardlamp == g_pre_body_cont_info.hazardlamp)) {
+			return;
+		}
+	}
+
+	/* 送信メッセージを生成 */
+	tx_data[0] = ((g_body_cont_info.headlight1 << 7) &  0x80) | 
+				 ((g_body_cont_info.headlight2 << 6) &  0x40) |
+				 ((g_body_cont_info.headlight3 << 5) &  0x20) |
+				 ((g_body_cont_info.breaklamp  << 4) &  0x10) |
+				 ((g_body_cont_info.backlamp   << 3) &  0x08) |
+				 ((g_body_cont_info.buzzer     << 1) &  0x06);
+
+	tx_data[1] = ((g_body_cont_info.blinker_l  << 6) &  0xc0) | 
+				 ((g_body_cont_info.blinker_r  << 4) &  0x30) | 
+				 ((g_body_cont_info.hazardlamp << 3) &  0x08);
+
+	NcanSetTxData(0, BODY_CAN_MSG_RMB, BODY_CAN_MSG_ID, tx_data, 2);
+
+	g_pre_body_cont_info = g_body_cont_info;
+}
+
+
+/*
+ *  起動時のボディーの接続確認
+ * 
+ *  全LED点滅とブザーを鳴らす．
+ */
+void
+body_check(void)
+{
+	int loop, tcnt;
+	uint8 status = BODY_CONT_ON;
+
+	for(loop = 0; loop < INIT_BODY_BLINK_COUNT*2; loop++) {
+		g_body_cont_info.headlight1 = status;
+		g_body_cont_info.headlight2 = status;
+		g_body_cont_info.headlight3 = status;
+		g_body_cont_info.breaklamp  = status;
+		g_body_cont_info.backlamp   = status;
+		g_body_cont_info.buzzer     = status;
+		g_body_cont_info.blinker_l  = status;
+		g_body_cont_info.blinker_r  = status;
+
+		tcnt = 0;
+
+		if (!IsBodyOnECU){
+			body_can_msg_send();
+		}
+
+		while(1) {
+			WaitEvent(RCOperatorEvt);
+			ClearEvent(RCOperatorEvt);
+			tcnt++;
+			if (tcnt == INIT_BODY_BLINK_CYCLE_MS/10) {
+				break;
+			}
+		}
+
+		status = (status == BODY_CONT_ON)? BODY_CONT_OFF : BODY_CONT_ON;
+	}
+}
+void
+rcb3_error(){
+	static int cnt = 0;
+	syslog(LOG_NOTICE, "error 0x%x : 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x \r\n", cnt++, g_rcb3_rmsg[0], g_rcb3_rmsg[1], g_rcb3_rmsg[2], g_rcb3_rmsg[3], g_rcb3_rmsg[4], g_rcb3_rmsg[5], g_rcb3_rmsg[6], g_rcb3_rmsg[7]);
+}
+
+void
+com_error(){
+	syslog(LOG_NOTICE, "com error");
+}
+
+/*
+ *  制御タスク
+ */
+TASK(RCControlTask)
+{
+	uint32 cycle = 0;
+	syslog(LOG_INFO, "RCControlTask : Start!");
+	uint8 rx_data[8];
+	uint8 rx_size;
+	int   loop;
+	boolean result;
+
+	body_check();
+
+	while(1){
+		/* 10m待ち */
+		WaitEvent(RCControlEvt); 
+		ClearEvent(RCControlEvt);
+
+		/*
+		 *  RCOperatorTaskが別ECUの場合はCANで受信
+		 */
+		if (!IsOpeOnECU){
+			NcanGetRxData(0, CONT_CMD_CAN_MSG_RMB, &rx_data[0], &rx_size);
+			if (rx_size != 0) {
+				result = FALSE; 
+				for (loop = 0; loop < rx_size; loop++){
+					result = rcb3_AddReceivedByte(rx_data[loop]);
+				}
+				if (result) {
+					onMsgPS3();
+				}
+				else {
+					syslog(LOG_NOTICE, "RCControlTask : Received Can data Error!\r\n");
+				}
+			}
+		}
+		else {
+			/*
+			 *  同一ECUの場合
+			 */
+			if (UpDateCntrolCmd == TRUE){
+				onMsgPS3();
+				UpDateCntrolCmd = FALSE;
+			}
+		}
+
+		/*
+		 *  RCBodyTaskが別ECUの場合はCANで送信
+		 */
+		if (!IsBodyOnECU) {
+			if (cycle++ == (BODY_CAN_SEND_CYCLE_MS/RC_CONTRL_TASK_CYCLE_MS)) {
+				body_can_msg_send();
+				cycle = 0;
+			}
+		}
+	}
+}
+
+//////////////////////////////////////////////////////////////////////////
+/*
+ *  
+ *   パワトレ関係
+ *
+ */
+#define UEC_TO_PWMCNT(usec)  (usec*PWM_CLK_MH)
+/* 100nsec 単位との変換 */
+#define M100NSEC_TO_PWMCNT(m100nsec)  ((m100nsec*PWM_CLK_MH)/10)
+
+#define SERVO_N    1570
+//#define SERVO_RMAX 1830
+//#define SERVO_LMAX 1400
+
+
+#define SERVO_RMAX 1870 
+#define SERVO_LMAX 1330
+
+void
+servo_setangle(int angle) {
+	sil_wrw_iop((void *)PWM1_ADDR, UEC_TO_PWMCNT(angle));
+}
+
+#define ESC_N      15000
+#define ESC_DMAX   14000
+#define ESC_RMAX   16500
+#define ESC_DTH    14500 
+#define ESC_RTH    15800
+#define ESC_BREAK  16200
+
+void
+RCPowerTrainTaskWait_20msec(void){
+	ClearEvent(RCPowerTrainEvt);
+	WaitEvent(RCPowerTrainEvt); 
+	ClearEvent(RCPowerTrainEvt);
+	WaitEvent(RCPowerTrainEvt); 
+	ClearEvent(RCPowerTrainEvt);
+}
+
+void
+esc_setspeed(int speed){
+	sil_wrw_iop((void *)PWM2_ADDR, M100NSEC_TO_PWMCNT(speed));
+}
+
+void
+esc_dbrak(void){
+	esc_setspeed(ESC_BREAK);
+}
+
+void
+esc_rbrak(void){
+	esc_setspeed(ESC_DTH);
+	RCPowerTrainTaskWait_20msec();
+	RCPowerTrainTaskWait_20msec();
+	esc_setspeed(ESC_BREAK);
+}
+
+void
+esc_neutral(void){
+	esc_setspeed(ESC_N);
+}
+
+void
+esc_reverse(void){
+	esc_neutral();
+	RCPowerTrainTaskWait_20msec();
+	RCPowerTrainTaskWait_20msec();
+}
+
+void
+esc_change_drive_to_reverse(void){
+	esc_setspeed(ESC_BREAK);
+	RCPowerTrainTaskWait_20msec();
+	esc_neutral();
+	RCPowerTrainTaskWait_20msec();
+}
+
+TASK(RCPowerTrainTask){
+	int servo_pwm;
+	static boolean pre_g_isBrake = FALSE;
+	static SHIFT_STATE pre_g_ShiftState = SHIFT_N;
+	static int pre_g_accelerator = 0;
+	int esc_pwm_100nsec = 0;
+
+	syslog(LOG_INFO, "RCPowerTrainTask : Start!");
+
+	/* 周期設定 : 20m周期 */
+	sil_wrw_iop((void *)PWM_MAX_ADDR, UEC_TO_PWMCNT(20000));
+
+	/* ニュートラル */
+	esc_neutral();
+	servo_setangle(SERVO_N);
+	syslog(LOG_INFO, "RCPowerTrainTask : neutral");
+
+	while(1){
+		WaitEvent(RCPowerTrainEvt);     /* 10msの作業時間待ち */
+		ClearEvent(RCPowerTrainEvt);
+
+		/*
+		 * サーボの設定
+		 * 左 32 から 右 -32 範囲
+		 */
+/*
+SERVO_LMAX       SERVO_N       SERVO_RMAX
+ 1400             1570           1830
+  32                0             -32
+*/
+
+		if(g_angle >= 0){
+			/* 左側操舵の場合 */
+			servo_pwm = SERVO_N - ((((SERVO_N - SERVO_LMAX) * 100) / (32 * 100)) * g_angle);
+		}
+		else {
+			/* 右側操舵の場合 */
+			servo_pwm = SERVO_N + ((((SERVO_RMAX - SERVO_N) * 100) / (32 * 100)) * (-g_angle));
+		}
+		servo_setangle(servo_pwm);
+
+		if(pre_g_isBrake != g_isBrake) {
+			/* ブレーキの状態が変化した場合 */
+			pre_g_isBrake = g_isBrake;
+			if (g_isBrake == FALSE) {
+				/* ノンブレーキ状態 */
+				syslog(LOG_INFO, "To non-braking");
+				if (g_ShiftState == SHIFT_R) {
+					esc_reverse();
+				}
+			}
+			else if (g_isBrake == TRUE) {
+				/* ブレーキ状態 */
+				syslog(LOG_INFO, "To braking");
+				if (pre_g_accelerator > 0){
+					esc_dbrak();
+				}
+				else {
+					esc_rbrak();
+				}
+			}
+		}
+
+		if (g_accelerator < 0){
+			g_ShiftState = SHIFT_D;
+			pre_g_ShiftState = SHIFT_D;
+		}
+
+		if (g_accelerator == 0){
+			g_ShiftState = SHIFT_N;
+		}
+
+		if (g_accelerator > 0){
+			if (pre_g_ShiftState == SHIFT_D){
+				esc_change_drive_to_reverse();
+				syslog(LOG_INFO, "RCPowerTrainTask : change drive to reverse");
+			}
+			g_ShiftState = SHIFT_R;
+			pre_g_ShiftState = SHIFT_R;
+		}
+#if 0
+		if(pre_g_ShiftState != g_ShiftState) {
+			pre_g_ShiftState = g_ShiftState;
+			if(g_ShiftState == SHIFT_D){
+				esc_pwm_100nsec = ESC_DTH;
+			}else if(g_ShiftState == SHIFT_R){
+				esc_pwm_100nsec = ESC_RTH;
+				esc_reverse();
+			}
+		}
+#endif
+
+		if(g_isBrake == TRUE){
+			/* ブレーキ状態 */
+		}else{
+			/* ノンブレーキ状態 */
+			if(g_ShiftState == SHIFT_N){
+				/* ニュートラル */
+					esc_neutral();
+			} else {
+				/* ニュートラル以外 */
+
+				/*
+				 *  
+				 */
+				if(g_accelerator == 0){
+					esc_pwm_100nsec = ESC_N;
+				}else{
+					if (g_ShiftState == SHIFT_D){
+						esc_pwm_100nsec = ESC_DTH + ((((ESC_DTH - ESC_DMAX)/64) * g_accelerator));
+						// * g_speed_gain/SPEED_GAIN_INIT
+					}
+					if (g_ShiftState == SHIFT_R){
+						esc_pwm_100nsec = ESC_RTH + ((((ESC_RMAX - ESC_RTH)/64) * g_accelerator));
+						// * g_speed_gain/SPEED_GAIN_INIT
+					}
+				}
+				esc_setspeed(esc_pwm_100nsec);
+			}
+		}
+		pre_g_accelerator = g_accelerator;
+	}
+}
+
+
+
+
+//////////////////////////////////////////////////////////////////////////
+/*
+ *  LED制御系
+ */
+static uint8 led0_enable = FALSE;
+static uint8 led7_enable = FALSE;
+
+void
+set_led7(boolean enable){
+	led7_enable = enable;
+}
+
+void
+set_led0(boolean enable){
+	led0_enable = enable;
+}
+
+#define PWM_CYCLE_100US 100
+#define LED_SHIFT_CYCLE  10
+#define PWM_MAX         100
+
+int led_duty[8];
+
+ALARMCALLBACK(ActiveLEDCycCb){
+	static int pwm_cyccnt = 0;
+	uint8 pattern = 0;
+	static int center_led = 6;
+	static int direction = 1; /* 1:right, 0:left */
+	static int led_shift_cnt = 0;
+	int i;
+
+	/* 100usec毎に呼び出される */
+
+	/* PWM周期 */
+	if (pwm_cyccnt++ >= PWM_CYCLE_100US){
+		pwm_cyccnt = 0;
+	}
+
+	if (pwm_cyccnt == 0) {
+		if(led_shift_cnt++ == LED_SHIFT_CYCLE){
+			led_shift_cnt = 0;
+
+			for(i = 0; i < 7; i++){
+				int pwm = PWM_MAX;
+				if (center_led > i){
+					pwm = PWM_MAX >> ((center_led - i) + 1);
+				}
+				else if (center_led < i){
+					pwm = PWM_MAX >> ((i - center_led) + 1);
+				}
+				else if (center_led == i){
+					pwm = PWM_MAX;
+				}
+				led_duty[i] = pwm;
+			}
+
+			if(direction == 1){
+				/* right */
+				if (--center_led <= 1){
+					direction = 0;
+				}
+			}
+			else {
+				/* left */
+				if (++center_led >= 6){
+					direction = 1;
+				}
+			}
+		}
+	}
+
+	for(i = 1; i < 7; i++){
+		if (pwm_cyccnt < led_duty[i]) {
+			pattern |= 1 << i;
+		}
+	}
+
+	if (led0_enable) {
+		pattern |= 0x01;
+	}
+	if (led7_enable) {
+		pattern |= 0x80;
+	}
+
+	set_led(pattern);
+}
+
+//////////////////////////////////////////////////////////////////////////
+
+/*
+ *  CANの初期化ルーチン
+ */
+void
+can_init(void){
+	/*
+	 *  モードによらず全てのメールボックスを初期化する
+	 */
+	NcanInit(0);
+	NcanSetMailBoxInfo(0, BODY_CAN_MSG_TMB,     DIR_SEND, 0, BODY_CAN_MSG_ID, 0, 0);
+	NcanSetMailBoxInfo(0, CONT_CMD_CAN_MSG_TMB, DIR_SEND, 0, CONT_CMD_CAN_MSG_ID, 0, 0);
+	NcanSetMailBoxInfo(0, BODY_CAN_MSG_RMB,     DIR_RECV, 0, BODY_CAN_MSG_ID, 0, 0);
+	NcanSetMailBoxInfo(0, CONT_CMD_CAN_MSG_RMB, DIR_RECV, 0, CONT_CMD_CAN_MSG_ID, 0, 0);
+	NcanEnable(0);
+}
+
+//////////////////////////////////////////////////////////////////////////
+/*
+ *  スタートアップフックルーチン
+ */
+void
+StartupHook(void)
+{
+	syslog_initialize();
+	syslog_msk_log(LOG_UPTO(LOG_INFO));
+	InitSerial();
+	print_banner();
+	can_init();
+	rcb3_Init();
+}
+
+/*
+ *  シャットダウンフックルーチン
+ */
+void
+ShutdownHook(StatusType Error)
+{
+	/* 終了ログ出力 */
+	syslog(LOG_INFO, "");
+	syslog(LOG_INFO, "Sample System ShutDown");
+	syslog(LOG_INFO, "ShutDownCode:%s", atk2_strerror(Error));
+	syslog(LOG_INFO, "");
+
+	if (Error == E_OS_SYS_ASSERT_FATAL) {
+		syslog(LOG_INFO, "fatal_file_name:%s", fatal_file_name);
+		syslog(LOG_INFO, "fatal_line_num:%d", fatal_line_num);
+	}
+
+	TermSerial();
+}
+
+//////////////////////////////////////////////////////////////////////////
+
+/*
+ *  コマンド受信処理
+ */
+static uint8
+GetCommand(void)
+{
+	uint8 command;          /* コマンド受信バッファ */
+
+	/*
+	 *  コマンドを受信するまでループ
+	 */
+	command = '\0';
+	do {
+		WaitEvent(MainEvt);     /* 10msウェイト */
+		ClearEvent(MainEvt);
+		RecvPolSerialChar(&command);    /* 受信バッファポーリング */
+		if (command == '\n') {
+			command = '\0';
+		}
+	} while (command == '\0');
+
+
+	return(command);
+}   /* GetCommand */
+
+/*
+ *  メインタスク
+ *
+ *  ユーザコマンドの受信と，コマンドごとの処理実行
+ */
+TASK(MainTask)
+{
+	uint8		command;
+	uint8		task_no;
+	uint32		i;
+
+	/*
+	 *  タスク番号・コマンドバッファ初期化
+	 */
+	task_no = (uint8) (0);
+	for (i = 0U; i < (sizeof(command_tbl) / sizeof(command_tbl[0])); i++) {
+		command_tbl[i] = 0U;
+	}
+
+	syslog(LOG_INFO, "Main Task : start!");
+#if 0
+	NcanSetMailBoxInfo(0, 0, DIR_RECV, 0, 3, 0, 0);
+	NcanSetMailBoxInfo(0, 0, DIR_SEND, 0, 4, 0, 0);
+	NcanEnable(0);
+	while(1){
+		WaitEvent(MainEvt);     /* 10msの作業時間待ち */
+		ClearEvent(MainEvt);
+		NcanGetRxData(0, 0, &rx_data[0], &rx_size );
+		if (rx_size != 0) {
+			syslog(LOG_INFO, "Main Task : can receive 0x%x, 0x%x", rx_data[0], rx_data[1]);
+		}
+		i++;
+		if(i == 200){
+			syslog(LOG_INFO, "Main Task : alive");
+			i = 0;
+			tx_data[0] = cnt++;
+			tx_data[1] = 0x02;
+			NcanSetTxData(0, 0, 4, tx_data, 2);
+		}
+	}
+#endif
+
+	/*
+	 *  コマンド実行ループ
+	 */
+	while (1) {
+		WaitEvent(MainEvt);     /* 10msの作業時間待ち */
+		ClearEvent(MainEvt);
+
+		/*
+		 *  入力コマンド取得
+		 */
+		syslog(LOG_INFO, "Input Command:");
+		command = GetCommand();
+
+		/*
+		 *  入力コマンドチェック
+		 */
+		if ((command <= (uint8) (0x1fU)) || (command >= (uint8) (0x80U))) {
+			syslog(LOG_INFO, "Not ASCII character");
+		}
+		else {
+			syslog(LOG_INFO, "%c", command);
+
+			/*
+			 *  コマンド判別
+			 */
+			switch (command) {
+			case '1':
+			default:
+				/* 上記のコマンド以外の場合，処理を行わない */
+				break;
+			}
+		}
+	}
+
+	/*
+	 *  ここにはこない
+	 */
+	syslog(LOG_INFO, "MainTask TERMINATE");
+	error_log(TerminateTask());
+}   /* TASK( MainTask ) */
+
+
+/*
+ *  エラーフックルーチン
+ */
+#ifdef CFG_USE_ERRORHOOK
+void
+ErrorHook(StatusType Error)
+{
+	/*
+	 *  エラー要因ごとのパラメータログ出力
+	 */
+	switch (OSErrorGetServiceId()) {
+	case OSServiceId_ActivateTask:
+		syslog(LOG_INFO, "Error:%s=ActivateTask(%d)", atk2_strerror(Error), OSError_ActivateTask_TaskID());
+		break;
+	case OSServiceId_TerminateTask:
+		syslog(LOG_INFO, "Error:%s=TerminateTask()", atk2_strerror(Error));
+		break;
+	case OSServiceId_ChainTask:
+		syslog(LOG_INFO, "Error:%s=ChainTask(%d)", atk2_strerror(Error), OSError_ChainTask_TaskID());
+		break;
+	case OSServiceId_Schedule:
+		syslog(LOG_INFO, "Error:%s=Schedule()", atk2_strerror(Error));
+		break;
+	case OSServiceId_GetTaskID:
+		syslog(LOG_INFO, "Error:%s=GetTaskID(0x%p)", atk2_strerror(Error), OSError_GetTaskID_TaskID());
+		break;
+	case OSServiceId_GetTaskState:
+		syslog(LOG_INFO, "Error:%s=GetTaskState(%d, 0x%p)", atk2_strerror(Error),
+			   OSError_GetTaskState_TaskID(), OSError_GetTaskState_State());
+		break;
+	case OSServiceId_EnableAllInterrupts:
+		syslog(LOG_INFO, "Error:%s=EnableAllInterrupts()", atk2_strerror(Error));
+		break;
+	case OSServiceId_DisableAllInterrupts:
+		syslog(LOG_INFO, "Error:%s=DisableAllInterrupts()", atk2_strerror(Error));
+		break;
+	case OSServiceId_ResumeAllInterrupts:
+		syslog(LOG_INFO, "Error:%s=ResumeAllInterrupts()", atk2_strerror(Error));
+		break;
+	case OSServiceId_SuspendAllInterrupts:
+		syslog(LOG_INFO, "Error:%s=SuspendAllInterrupts()", atk2_strerror(Error));
+		break;
+	case OSServiceId_ResumeOSInterrupts:
+		syslog(LOG_INFO, "Error:%s=ResumeOSInterrupts()", atk2_strerror(Error));
+		break;
+	case OSServiceId_SuspendOSInterrupts:
+		syslog(LOG_INFO, "Error:%s=SuspendOSInterrupts()", atk2_strerror(Error));
+		break;
+	case OSServiceId_GetISRID:
+		syslog(LOG_INFO, "Error:%s=GetISRID()", atk2_strerror(Error));
+		break;
+	case OSServiceId_GetResource:
+		syslog(LOG_INFO, "Error:%s=GetResource(%d)", atk2_strerror(Error), OSError_GetResource_ResID());
+		break;
+	case OSServiceId_ReleaseResource:
+		syslog(LOG_INFO, "Error:%s=ReleaseResource(%d)", atk2_strerror(Error), OSError_ReleaseResource_ResID());
+		break;
+	case OSServiceId_SetEvent:
+		syslog(LOG_INFO, "Error:%s=SetEvent(%d, 0x%x)", atk2_strerror(Error),
+			   OSError_SetEvent_TaskID(), OSError_SetEvent_Mask());
+		break;
+	case OSServiceId_ClearEvent:
+		syslog(LOG_INFO, "Error:%s=ClearEvent(0x%x)", atk2_strerror(Error), OSError_ClearEvent_Mask());
+		break;
+	case OSServiceId_GetEvent:
+		syslog(LOG_INFO, "Error:%s=GetEvent(%d, 0x%p)", atk2_strerror(Error),
+			   OSError_GetEvent_TaskID(), OSError_GetEvent_Event());
+		break;
+	case OSServiceId_WaitEvent:
+		syslog(LOG_INFO, "Error:%s=WaitEvent(0x%x)", atk2_strerror(Error), OSError_WaitEvent_Mask());
+		break;
+	case OSServiceId_GetAlarmBase:
+		syslog(LOG_INFO, "Error:%s=GetAlarmBase(0x%p)", atk2_strerror(Error), OSError_GetAlarmBase_AlarmID());
+		break;
+	case OSServiceId_GetAlarm:
+		syslog(LOG_INFO, "Error:%s=GetAlarm(%d, 0x%p)", atk2_strerror(Error),
+			   OSError_GetAlarm_AlarmID(), OSError_GetAlarm_Tick());
+		break;
+	case OSServiceId_SetRelAlarm:
+		syslog(LOG_INFO, "Error:%s=SetRelAlarm(%d, %d, %d)", atk2_strerror(Error),
+			   OSError_SetRelAlarm_AlarmID(), OSError_SetRelAlarm_increment(), OSError_SetRelAlarm_cycle());
+		break;
+	case OSServiceId_SetAbsAlarm:
+		syslog(LOG_INFO, "Error:%s=SetAbsAlarm(%d, %d, %d)", atk2_strerror(Error),
+			   OSError_SetAbsAlarm_AlarmID(), OSError_SetAbsAlarm_start(), OSError_SetAbsAlarm_cycle());
+		break;
+	case OSServiceId_CancelAlarm:
+		syslog(LOG_INFO, "Error:%s=CancelAlarm(%d)", atk2_strerror(Error), OSError_CancelAlarm_AlarmID());
+		break;
+	case OSServiceId_StartScheduleTableRel:
+		syslog(LOG_INFO, "Error:%s=StartScheduleTableRel(%d, %d)", atk2_strerror(Error),
+			   OSError_StartScheduleTableRel_ScheduleTableID(), OSError_StartScheduleTableRel_Offset());
+		break;
+	case OSServiceId_StartScheduleTableAbs:
+		syslog(LOG_INFO, "Error:%s=StartScheduleTableAbs(%d, %d)", atk2_strerror(Error),
+			   OSError_StartScheduleTableAbs_ScheduleTableID(), OSError_StartScheduleTableAbs_Start());
+		break;
+	case OSServiceId_StopScheduleTable:
+		syslog(LOG_INFO, "Error:%s=StopScheduleTable(%d)", atk2_strerror(Error), OSError_StopScheduleTable_ScheduleTableID());
+		break;
+	case OSServiceId_NextScheduleTable:
+		syslog(LOG_INFO, "Error:%s=NextScheduleTable(%d, %d)", atk2_strerror(Error),
+			   OSError_NextScheduleTable_ScheduleTableID_From(), OSError_NextScheduleTable_ScheduleTableID_To());
+		break;
+	case OSServiceId_GetScheduleTableStatus:
+		syslog(LOG_INFO, "Error:%s=GetScheduleTableStatus(%d, 0x%p)", atk2_strerror(Error),
+			   OSError_GetScheduleTableStatus_ScheduleTableID(), OSError_GetScheduleTableStatus_ScheduleStatus());
+		break;
+	case OSServiceId_GetActiveApplicationMode:
+		syslog(LOG_INFO, "Error:%s=GetActiveApplicationMode()", atk2_strerror(Error));
+		break;
+	case OSServiceId_StartOS:
+		syslog(LOG_INFO, "Error:%s=StartOS()", atk2_strerror(Error));
+		break;
+	case OSServiceId_ShutdownOS:
+		syslog(LOG_INFO, "Error:%s=ShutdownOS()", atk2_strerror(Error));
+		break;
+	case OSServiceId_IncrementCounter:
+		syslog(LOG_INFO, "Error:%s=IncrementCounter(%d)", atk2_strerror(Error), OSError_IncrementCounter_CounterID());
+		break;
+	case OSServiceId_TaskMissingEnd:
+		syslog(LOG_INFO, "Error:%s=MissingEnd()", atk2_strerror(Error));
+		break;
+	default:
+		syslog(LOG_INFO, "Error:%s=UnKnownFunc()", atk2_strerror(Error));
+		break;
+	}
+
+}   /* ErrorHook */
+#endif /* CFG_USE_ERRORHOOK */
+
+/*
+ *  プレタスクフックルーチン
+ *
+ *  空ルーチンを呼出す
+ */
+#ifdef CFG_USE_PRETASKHOOK
+void
+PreTaskHook(void)
+{
+}   /* PreTaskHook */
+#endif /* CFG_USE_PRETASKHOOK */
+
+/*
+ *  ポストタスクフックルーチン
+ *
+ *  空ルーチンを呼出す
+ */
+#ifdef CFG_USE_POSTTASKHOOK
+void
+PostTaskHook(void)
+{
+}   /* PostTaskHook */
+#endif /* CFG_USE_POSTTASKHOOK */
+
+
+/*
+ *  プロテクションフックルーチン
+ */
+#ifdef CFG_USE_PROTECTIONHOOK
+ProtectionReturnType
+ProtectionHook(StatusType FatalError)
+{
+	StatusType ercd;
+
+	syslog(LOG_INFO, "");
+	syslog(LOG_INFO, "ProtectionHook");
+
+	if (FatalError == E_OS_STACKFAULT) {
+		syslog(LOG_INFO, "E_OS_STACKFAULT");
+		ercd = PRO_SHUTDOWN;
+	}
+	else if (FatalError == E_OS_PROTECTION_EXCEPTION) {
+		syslog(LOG_INFO, "E_OS_PROTECTION_EXCEPTION");
+		ercd = PRO_IGNORE;
+	}
+	else {
+		ercd = PRO_SHUTDOWN;
+	}
+
+	return(ercd);
+}
+#endif /* CFG_USE_PROTECTIONHOOK */
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/rc_car.h
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/rc_car.h	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/rc_car.h	(revision 295)
@@ -0,0 +1,11 @@
+/*
+ *		RC-CAR制御プログラムのヘッダファイル
+ */
+
+#ifndef TOPPERS_RC_CAR_H
+#define TOPPERS_RC_CAR_H
+
+extern void set_led7(boolean enable);
+extern void set_led0(boolean enable);
+
+#endif /* TOPPERS_RC_CAR_H */
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/rc_car.yaml
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/rc_car.yaml	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/rc_car.yaml	(revision 295)
@@ -0,0 +1,239 @@
+Ecuc:
+  Os:
+    OsInclude:
+      OsIncludeFileName: rc_car.h
+    AppMode_ALL:
+      DefinitionRef: OsAppMode
+    AppMode_Body:
+      DefinitionRef: OsAppMode
+    AppMode_Cnt:
+      DefinitionRef: OsAppMode
+    AppMode_Ope:
+      DefinitionRef: OsAppMode
+    AppMode_Body_Cnt:
+      DefinitionRef: OsAppMode
+    AppMode_Body_Ope:
+      DefinitionRef: OsAppMode
+    AppMode_Cnt_Ope:
+      DefinitionRef: OsAppMode
+    OsOS:
+      OsStackMonitoring: true
+      OsUseGetServiceId: true
+      OsUseParameterAccess: true
+      OsScalabilityClass: SC1
+      OsStatus: EXTENDED
+      OsHooks:
+        OsErrorHook: true
+        OsPostTaskHook: true
+        OsPreTaskHook: true
+        OsProtectionHook: true
+        OsShutdownHook: true
+        OsStartupHook: true
+      OsHookStack:
+        OsHookStackSize: 0x200
+    MainEvt:
+      DefinitionRef: OsEvent
+    MainTask:
+      DefinitionRef: OsTask
+      OsTaskActivation: 1U
+      OsTaskPriority: 14
+      OsTaskStackSize: 0x1000
+      OsTaskSchedule: FULL
+      OsTaskEventRef:
+          - /Ecuc/Os/MainEvt
+          - /Ecuc/Os/COMUartEvt
+      OsTaskAutostart:
+        OsTaskAppModeRef:
+          - /Ecuc/Os/AppMode_ALL
+          - /Ecuc/Os/AppMode_Body
+          - /Ecuc/Os/AppMode_Cnt
+          - /Ecuc/Os/AppMode_Ope
+          - /Ecuc/Os/AppMode_Body_Cnt
+          - /Ecuc/Os/AppMode_Body_Ope
+          - /Ecuc/Os/AppMode_Cnt_Ope
+    MainCycArm:
+      DefinitionRef: OsAlarm
+      OsAlarmCounterRef: /Ecuc/Os/MAIN_HW_COUNTER
+      OsAlarmAction:
+        OsAlarmSetEvent:
+          OsAlarmSetEventTaskRef: /Ecuc/Os/MainTask
+          OsAlarmSetEventRef: /Ecuc/Os/MainEvt
+      OsAlarmAutostart:
+        OsAlarmAlarmTime: TICK_FOR_10MS
+        OsAlarmCycleTime: TICK_FOR_10MS
+        OsAlarmAutostartType: ABSOLUTE
+        OsAlarmAppModeRef:
+          - /Ecuc/Os/AppMode_ALL
+          - /Ecuc/Os/AppMode_Body
+          - /Ecuc/Os/AppMode_Cnt
+          - /Ecuc/Os/AppMode_Ope
+          - /Ecuc/Os/AppMode_Body_Cnt
+          - /Ecuc/Os/AppMode_Body_Ope
+          - /Ecuc/Os/AppMode_Cnt_Ope
+
+    RCOperatorTask:
+      DefinitionRef: OsTask
+      OsTaskActivation: 1U
+      OsTaskPriority: 2
+      OsTaskStackSize: 0x1000
+      OsTaskSchedule: FULL
+      OsTaskEventRef:
+          - /Ecuc/Os/COMUartEvt
+          - /Ecuc/Os/RCOperatorEvt
+      OsTaskAutostart:
+        OsTaskAppModeRef:
+          - /Ecuc/Os/AppMode_ALL
+          - /Ecuc/Os/AppMode_Ope
+          - /Ecuc/Os/AppMode_Body_Ope
+          - /Ecuc/Os/AppMode_Cnt_Ope
+    RCOperatorEvt:
+      DefinitionRef: OsEvent
+    RCOperatorCycArm:
+      DefinitionRef: OsAlarm
+      OsAlarmCounterRef: /Ecuc/Os/MAIN_HW_COUNTER
+      OsAlarmAction:
+        OsAlarmSetEvent:
+          OsAlarmSetEventTaskRef: /Ecuc/Os/RCOperatorTask
+          OsAlarmSetEventRef: /Ecuc/Os/RCOperatorEvt
+      OsAlarmAutostart:
+        OsAlarmAlarmTime: TICK_FOR_10MS/10
+        OsAlarmCycleTime: TICK_FOR_10MS/10
+        OsAlarmAutostartType: ABSOLUTE
+        OsAlarmAppModeRef:
+          - /Ecuc/Os/AppMode_ALL
+          - /Ecuc/Os/AppMode_Ope
+          - /Ecuc/Os/AppMode_Body_Ope
+          - /Ecuc/Os/AppMode_Cnt_Ope
+
+    RCBodyTask:
+      DefinitionRef: OsTask
+      OsTaskActivation: 1U
+      OsTaskPriority: 2
+      OsTaskStackSize: 0x1000
+      OsTaskSchedule: FULL
+      OsTaskEventRef:
+          - /Ecuc/Os/RCBodyEvt
+      OsTaskAutostart:
+        OsTaskAppModeRef:
+          - /Ecuc/Os/AppMode_ALL
+          - /Ecuc/Os/AppMode_Body
+          - /Ecuc/Os/AppMode_Body_Cnt
+          - /Ecuc/Os/AppMode_Body_Ope
+    RCBodyEvt:
+      DefinitionRef: OsEvent
+    RCBodyCycArm:
+      DefinitionRef: OsAlarm
+      OsAlarmCounterRef: /Ecuc/Os/MAIN_HW_COUNTER
+      OsAlarmAction:
+        OsAlarmSetEvent:
+          OsAlarmSetEventTaskRef: /Ecuc/Os/RCBodyTask
+          OsAlarmSetEventRef: /Ecuc/Os/RCBodyEvt
+      OsAlarmAutostart:
+        OsAlarmAlarmTime: TICK_FOR_10MS
+        OsAlarmCycleTime: TICK_FOR_10MS
+        OsAlarmAutostartType: ABSOLUTE
+        OsAlarmAppModeRef:
+          - /Ecuc/Os/AppMode_ALL
+          - /Ecuc/Os/AppMode_Body
+          - /Ecuc/Os/AppMode_Body_Cnt
+          - /Ecuc/Os/AppMode_Body_Ope
+    BuzzerCycAlm:
+      DefinitionRef: OsAlarm
+      OsAlarmCounterRef: /Ecuc/Os/MAIN_HW_COUNTER
+      OsAlarmAction:
+        OsAlarmCallback:
+          OsAlarmCallbackName: BuzzerCycAlmCb
+      OsAlarmAutostart:
+        OsAlarmAlarmTime: TICK_FOR_10MS/10
+        OsAlarmCycleTime: TICK_FOR_10MS/10
+        OsAlarmAutostartType: ABSOLUTE
+        OsAlarmAppModeRef:
+          - /Ecuc/Os/AppMode_ALL
+          - /Ecuc/Os/AppMode_Body
+          - /Ecuc/Os/AppMode_Body_Cnt
+          - /Ecuc/Os/AppMode_Body_Ope
+
+    RCControlTask:
+      DefinitionRef: OsTask
+      OsTaskActivation: 1U
+      OsTaskPriority: 3
+      OsTaskStackSize: 0x1000
+      OsTaskSchedule: FULL
+      OsTaskEventRef:
+          - /Ecuc/Os/RCControlEvt
+      OsTaskAutostart:
+        OsTaskAppModeRef:
+          - /Ecuc/Os/AppMode_ALL
+          - /Ecuc/Os/AppMode_Cnt
+          - /Ecuc/Os/AppMode_Body_Cnt
+          - /Ecuc/Os/AppMode_Cnt_Ope
+    RCControlEvt:
+      DefinitionRef: OsEvent
+    RCControlCycArm:
+      DefinitionRef: OsAlarm
+      OsAlarmCounterRef: /Ecuc/Os/MAIN_HW_COUNTER
+      OsAlarmAction:
+        OsAlarmSetEvent:
+          OsAlarmSetEventTaskRef: /Ecuc/Os/RCControlTask
+          OsAlarmSetEventRef: /Ecuc/Os/RCControlEvt
+      OsAlarmAutostart:
+        OsAlarmAlarmTime: TICK_FOR_10MS
+        OsAlarmCycleTime: TICK_FOR_10MS
+        OsAlarmAutostartType: ABSOLUTE
+        OsAlarmAppModeRef:
+          - /Ecuc/Os/AppMode_ALL
+          - /Ecuc/Os/AppMode_Cnt
+          - /Ecuc/Os/AppMode_Body_Cnt
+          - /Ecuc/Os/AppMode_Cnt_Ope
+
+    RCPowerTrainTask:
+      DefinitionRef: OsTask
+      OsTaskActivation: 1U
+      OsTaskPriority: 14
+      OsTaskStackSize: 0x1000
+      OsTaskSchedule: NON
+      OsTaskEventRef:
+          - /Ecuc/Os/RCPowerTrainEvt
+      OsTaskAutostart:
+        OsTaskAppModeRef:
+          - /Ecuc/Os/AppMode_ALL
+          - /Ecuc/Os/AppMode_Cnt
+          - /Ecuc/Os/AppMode_Body_Cnt
+          - /Ecuc/Os/AppMode_Cnt_Ope
+    RCPowerTrainEvt:
+      DefinitionRef: OsEvent
+    RCPowerTrainCycArm:
+      DefinitionRef: OsAlarm
+      OsAlarmCounterRef: /Ecuc/Os/MAIN_HW_COUNTER
+      OsAlarmAction:
+        OsAlarmSetEvent:
+          OsAlarmSetEventTaskRef: /Ecuc/Os/RCPowerTrainTask
+          OsAlarmSetEventRef: /Ecuc/Os/RCPowerTrainEvt
+      OsAlarmAutostart:
+        OsAlarmAlarmTime: TICK_FOR_10MS
+        OsAlarmCycleTime: TICK_FOR_10MS
+        OsAlarmAutostartType: ABSOLUTE
+        OsAlarmAppModeRef:
+          - /Ecuc/Os/AppMode_ALL
+          - /Ecuc/Os/AppMode_Cnt
+          - /Ecuc/Os/AppMode_Body_Cnt
+          - /Ecuc/Os/AppMode_Cnt_Ope
+
+    ActiveLEDCycArm:
+      DefinitionRef: OsAlarm
+      OsAlarmCounterRef: /Ecuc/Os/MAIN_HW_COUNTER
+      OsAlarmAction:
+        OsAlarmCallback:
+          OsAlarmCallbackName: ActiveLEDCycCb
+      OsAlarmAutostart:
+        OsAlarmAlarmTime: TICK_FOR_10MS/100
+        OsAlarmCycleTime: TICK_FOR_10MS/100
+        OsAlarmAutostartType: ABSOLUTE
+        OsAlarmAppModeRef:
+          - /Ecuc/Os/AppMode_ALL
+          - /Ecuc/Os/AppMode_Body
+          - /Ecuc/Os/AppMode_Cnt
+          - /Ecuc/Os/AppMode_Ope
+          - /Ecuc/Os/AppMode_Body_Cnt
+          - /Ecuc/Os/AppMode_Body_Ope
+          - /Ecuc/Os/AppMode_Cnt_Ope
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/rcb3.c
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/rcb3.c	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/rcb3.c	(revision 295)
@@ -0,0 +1,208 @@
+/*
+ *  Copyright (C) 2013-2014 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  $Id: rcb3.c 213 2014-09-02 11:48:58Z honda $
+ */
+
+#include "Os.h"
+#include "rcb3.h"
+
+/*
+ *  PS3Rg[Ì{^Ì
+ */
+#define PS3_NUM_OF_BUTTON 14
+#define PS3_NUM_OF_ANALOG 4
+
+
+/*
+ *  d¶tH[}bgÌ^Cv
+ */
+enum rcb3_st {
+	RCB3_ST_HEADER_1,
+	RCB3_ST_BUTTON_1,
+	RCB3_ST_BUTTON_2, 
+	RCB3_ST_ANALOG_1,
+	RCB3_ST_ANALOG_2,
+	RCB3_ST_ANALOG_3,
+	RCB3_ST_ANALOG_4,
+	RCB3_ST_SUM, 
+};
+
+/*
+ *  óMbZ[WðÍpO[oÏ
+ */
+static enum rcb3_st s_rcb3_st = RCB3_ST_HEADER_1;
+static int          s_rcb3_rmsg_cnt;
+uint8        g_rcb3_rmsg[RCB3_MSG_LEN];
+
+/*
+ *  {^bZ[W»ÊpO[oÏ
+ */
+static const uint16 msg_button_pattern[PS3_NUM_OF_BUTTON] = {
+	RCB3_MSG_BUTTON_UP,
+	RCB3_MSG_BUTTON_DOWN,
+	RCB3_MSG_BUTTON_LEFT,
+	RCB3_MSG_BUTTON_RIGHT,
+	RCB3_MSG_BUTTON_TRIANGLE,
+	RCB3_MSG_BUTTON_CROSS,
+	RCB3_MSG_BUTTON_NOUGHT,
+	RCB3_MSG_BUTTON_SQUARE,
+	RCB3_MSG_BUTTON_L1,
+	RCB3_MSG_BUTTON_L2,
+	RCB3_MSG_BUTTON_R1,
+	RCB3_MSG_BUTTON_R2,
+	RCB3_MSG_BUTTON_START,
+	RCB3_MSG_BUTTON_SELECT
+};
+
+/*
+ *  {^óÔÛpO[oÏ
+ *   _uobt@ÆµÄOóÔÆ»ÝóÔðÛ¶·é
+ */
+static boolean   s_ps3button[2][PS3_NUM_OF_BUTTON];
+static sint8 s_ps3analog[2][PS3_NUM_OF_ANALOG];
+
+/*
+ * OóÔÆ»ÝóÔð¦·|C^
+ */
+boolean   *p_g_pre_ps3button;
+boolean   *p_g_cur_ps3button;
+sint8 *p_g_pre_ps3analog;
+sint8 *p_g_cur_ps3analog;
+
+
+void
+rcb3_Init(void)
+{
+	/* ToDo 0 clear */
+
+	/* Init button */
+	p_g_pre_ps3button = s_ps3button[0];
+	p_g_cur_ps3button = s_ps3button[1];
+	p_g_pre_ps3analog = s_ps3analog[0];
+	p_g_cur_ps3analog = s_ps3analog[1];
+}
+
+/*
+ *  {^îñÍ2oCgÆÈÁÄ¢é½ß2oCgf[^ÆµÄß·
+ */
+static uint16
+rcb3_GetReceivedButton()
+{
+	uint16 button_cmd;
+
+	button_cmd = (g_rcb3_rmsg[RCB3_MSG_OFFSET_BUTTON_H] << 8) | g_rcb3_rmsg[RCB3_MSG_OFFSET_BUTTON_L];
+
+	return button_cmd;
+}
+
+/*
+ *  {^óÔÌXV
+ */
+static void
+rcb3_UpdateStatus(void)
+{
+	boolean *tmp_button;
+	sint8 *tmp_analog;
+	int i;
+	uint16 button = rcb3_GetReceivedButton();
+
+	/*
+	 *  OóÔÆ»ÝóÔÌ|C^ðXV
+	 */
+	tmp_button = p_g_pre_ps3button;
+	tmp_analog = p_g_pre_ps3analog;
+
+	p_g_pre_ps3button = p_g_cur_ps3button;
+	p_g_pre_ps3analog = p_g_cur_ps3analog;
+
+	p_g_cur_ps3button = tmp_button;
+	p_g_cur_ps3analog = tmp_analog;
+
+	/*
+	 *  »ÝÌfW^{^ÌóÔðXV
+	 */
+	for(i = 0; i < PS3_NUM_OF_BUTTON; i++) {
+		if ((button & msg_button_pattern[i])) {
+			p_g_cur_ps3button[i] = TRUE;
+		}
+		else {
+			p_g_cur_ps3button[i] = FALSE;
+		}
+	}
+
+	/*
+	 *  »ÝÌAiO{^ÌóÔðXV
+	 */
+	for(i = 0; i < PS3_NUM_OF_ANALOG; i++) {
+		uint8 val = g_rcb3_rmsg[RCB3_MSG_OFFSET_L_ANALOG_LR + i];
+		p_g_cur_ps3analog[i] = ((sint8)val - RCB3_MSG_ANALOG_NEUTRAL);
+	}
+}
+
+/*
+ *  RCB3R}hÌðÍ
+ * 
+ *  óMµ½1oCgÉøÉwèµÄÄÑo·D
+ *  d¶ÌÅãÅTRUEðÔ·D
+ */
+boolean
+rcb3_AddReceivedByte(uint8 c)
+{
+	boolean rval = FALSE;
+	int i;
+	uint8 sum = 0;
+
+	switch (s_rcb3_st) {
+	case RCB3_ST_HEADER_1:
+		if (c == RCB3_MSG_HEADER_1) {
+			s_rcb3_rmsg_cnt = 0;
+			g_rcb3_rmsg[s_rcb3_rmsg_cnt++] = c;
+			s_rcb3_st = RCB3_ST_BUTTON_1;
+		}
+		break;
+	case RCB3_ST_BUTTON_1:
+		g_rcb3_rmsg[s_rcb3_rmsg_cnt++] = c;
+		s_rcb3_st = RCB3_ST_BUTTON_2;
+		break;
+	case RCB3_ST_BUTTON_2:
+		g_rcb3_rmsg[s_rcb3_rmsg_cnt++] = c;
+		s_rcb3_st = RCB3_ST_ANALOG_1;
+		break;
+	case RCB3_ST_ANALOG_1:
+		g_rcb3_rmsg[s_rcb3_rmsg_cnt++] = c;
+		s_rcb3_st = RCB3_ST_ANALOG_2;
+		break;
+	case RCB3_ST_ANALOG_2:
+		g_rcb3_rmsg[s_rcb3_rmsg_cnt++] = c;
+		s_rcb3_st = RCB3_ST_ANALOG_3;
+		break;
+	case RCB3_ST_ANALOG_3:
+		g_rcb3_rmsg[s_rcb3_rmsg_cnt++] = c;
+		s_rcb3_st = RCB3_ST_ANALOG_4;
+		break;
+	case RCB3_ST_ANALOG_4:
+		g_rcb3_rmsg[s_rcb3_rmsg_cnt++] = c;
+		s_rcb3_st = RCB3_ST_SUM;
+		break;
+	case RCB3_ST_SUM:
+		g_rcb3_rmsg[s_rcb3_rmsg_cnt++] = c;
+		for(i = 1; i < (RCB3_MSG_LEN - 1); i++) {
+			sum += g_rcb3_rmsg[i];
+		}
+		sum &= 0x7f;
+		if (c == sum) {
+			rcb3_UpdateStatus();
+			rval = TRUE;
+		}else{
+			rcb3_error();
+			for(i = 0; i < (RCB3_MSG_LEN - 1); i++) {
+				g_rcb3_rmsg[0] = 0;
+			}
+		}
+		s_rcb3_st = RCB3_ST_HEADER_1;
+		break;
+	}
+	return rval;
+}
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/rcb3.h
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/rcb3.h	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/obj/nios2_dev_rc/rcb3.h	(revision 295)
@@ -0,0 +1,93 @@
+/*
+ *  Copyright (C) 2013-2014 by Embedded and Real-Time Systems Laboratory
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ * 
+ *  $Id: rcb3.h 213 2014-09-02 11:48:58Z honda $
+ */
+
+#ifndef _RCB3_H_
+#define _RCB3_H_
+
+/*
+ *  RCB3d¶ðÍ
+ */
+/*
+ *  RCB3 Message format
+ */
+#define RCB3_MSG_LEN 8
+#define RCB3_MSG_HEADER_1 0x80
+
+#define RCB3_MSG_OFFSET_BUTTON_H 1
+#define RCB3_MSG_OFFSET_BUTTON_L 2
+#define RCB3_MSG_OFFSET_L_ANALOG_LR  3
+#define RCB3_MSG_OFFSET_L_ANALOG_UD  4
+#define RCB3_MSG_OFFSET_R_ANALOG_LR  5
+#define RCB3_MSG_OFFSET_R_ANALOG_UD  6
+
+#define RCB3_MSG_BUTTON_UP        0x0001
+#define RCB3_MSG_BUTTON_DOWN      0x0002
+#define RCB3_MSG_BUTTON_LEFT      0x0004
+#define RCB3_MSG_BUTTON_RIGHT     0x0008
+#define RCB3_MSG_BUTTON_TRIANGLE  0x0010
+#define RCB3_MSG_BUTTON_CROSS     0x0020
+#define RCB3_MSG_BUTTON_NOUGHT    0x0040
+#define RCB3_MSG_BUTTON_SQUARE    0x0100
+#define RCB3_MSG_BUTTON_L1        0x0200
+#define RCB3_MSG_BUTTON_L2        0x0400
+#define RCB3_MSG_BUTTON_R1        0x0800
+#define RCB3_MSG_BUTTON_R2        0x1000
+#define RCB3_MSG_BUTTON_START     0x0003
+#define RCB3_MSG_BUTTON_SELECT    0x000C
+
+#define RCB3_MSG_ANALOG_MAX      127
+#define RCB3_MSG_ANALOG_MIN        1
+#define RCB3_MSG_ANALOG_NEUTRAL   64
+
+
+/*
+ * OóÔÆ»ÝóÔð¦·|C^
+ */
+extern boolean  *p_g_pre_ps3button;
+extern boolean  *p_g_cur_ps3button;
+extern sint8    *p_g_pre_ps3analog;
+extern sint8    *p_g_cur_ps3analog;
+extern uint8     g_rcb3_rmsg[RCB3_MSG_LEN];
+
+/*
+ *  e{^óÔÌÔ
+ */
+#define NO_PS3BUTTON_UP        0
+#define NO_PS3BUTTON_DOWN      1
+#define NO_PS3BUTTON_LEFT      3
+#define NO_PS3BUTTON_RIGHT     2
+#define NO_PS3BUTTON_TRIANGLE  4
+#define NO_PS3BUTTON_CROSS     5
+#define NO_PS3BUTTON_NOUGHT    6
+#define NO_PS3BUTTON_SQUARE    7
+#define NO_PS3BUTTON_L1        8
+#define NO_PS3BUTTON_L2        9
+#define NO_PS3BUTTON_R1        10
+#define NO_PS3BUTTON_R2        11
+#define NO_PS3BUTTON_START     12
+#define NO_PS3BUTTON_SELECT    13
+
+#define NO_PS3ANALOG_L_LR  0
+#define NO_PS3ANALOG_L_UD  1
+#define NO_PS3ANALOG_R_LR  2
+#define NO_PS3ANALOG_R_UD  3
+
+/*
+ *  ú» 
+ */
+void rcb3_Init(void);
+
+
+/*
+ *  RCB3R}hÌðÍ
+ * 
+ *  óMµ½1oCgÉøÉwèµÄÄÑo·D
+ *  d¶ÌÅãÅTRUEðÔ·D
+ */
+extern boolean rcb3_AddReceivedByte(uint8 c);
+
+#endif /* _RCB3_H_ */
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/E_PACKAGE
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/E_PACKAGE	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/E_PACKAGE	(revision 295)
@@ -0,0 +1,11 @@
+E_PACKAGE atk2-sc1_nios2_dev_gcc
+VERSION %date
+
+INCLUDE ./MANIFEST
+INCLUDE ../../MANIFEST
+INCLUDE ../../arch/nios2_gcc/MANIFEST
+INCLUDE ./fpga_design/MANIFEST
+INCLUDE ./fpga_design/canc/MANIFEST
+INCLUDE ./fpga_design/canc/hdl/MANIFEST
+INCLUDE ../../arch/nios2_gcc/sysver/MANIFEST
+
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/MANIFEST
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/MANIFEST	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/MANIFEST	(revision 295)
@@ -0,0 +1,36 @@
+PACKAGE atk2-sc1
+
+E_PACKAGE
+MANIFEST
+com_port.rb
+gdb.ini
+Makefile.target
+nios2_dev_2s180.ld
+nios2_dev_2s180_onchip.ld
+nios2_dev_de2_115.ld
+nios2_dev_de2_115_onchip.ld
+nios2_system.h
+SmpC1ISR.S
+target.tf
+target_cfg1_out.h
+target_check.tf
+target_config.c
+target_config.h
+target_hw_counter.arxml
+target_hw_counter.yaml
+target_hw_counter.c
+target_hw_counter.h
+target_kernel.h
+target_offset.tf
+target_serial.arxml
+target_serial.yaml
+target_serial.h
+target_sysmod.h
+target_test.arxml
+target_test.yaml
+target_test.c
+target_test.h
+target_timer.arxml
+target_timer.yaml
+target_timer.h
+target_user.txt
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/Makefile.target
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/Makefile.target	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/Makefile.target	(revision 295)
@@ -0,0 +1,210 @@
+#
+#  TOPPERS ATK2
+#      Toyohashi Open Platform for Embedded Real-Time Systems
+#      Automotive Kernel Version 2
+#
+#  Copyright (C) 2008-2015 by Center for Embedded Computing Systems
+#              Graduate School of Information Science, Nagoya Univ., JAPAN
+#  Copyright (C) 2011-2015 by FUJI SOFT INCORPORATED, JAPAN
+#  Copyright (C) 2011-2013 by Spansion LLC, USA
+#  Copyright (C) 2011-2015 by NEC Communication Systems, Ltd., JAPAN
+#  Copyright (C) 2011-2015 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
+#  Copyright (C) 2011-2014 by Renesas Electronics Corporation, JAPAN
+#  Copyright (C) 2011-2015 by Sunny Giken Inc., JAPAN
+#  Copyright (C) 2011-2015 by TOSHIBA CORPORATION, JAPAN
+#  Copyright (C) 2011-2015 by Witz Corporation
+#  Copyright (C) 2014-2015 by AISIN COMCRUISE Co., Ltd., JAPAN
+#  Copyright (C) 2014-2015 by eSOL Co.,Ltd., JAPAN
+#  Copyright (C) 2014-2015 by SCSK Corporation, JAPAN
+#
+#  上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
+#  ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
+#  変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
+#  (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
+#      権表示，この利用条件および下記の無保証規定が，そのままの形でソー
+#      スコード中に含まれていること．
+#  (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
+#      用できる形で再配布する場合には，再配布に伴うドキュメント（利用
+#      者マニュアルなど）に，上記の著作権表示，この利用条件および下記
+#      の無保証規定を掲載すること．
+#  (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
+#      用できない形で再配布する場合には，次のいずれかの条件を満たすこ
+#      と．
+#    (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
+#        作権表示，この利用条件および下記の無保証規定を掲載すること．
+#    (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
+#        報告すること．
+#  (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
+#      害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
+#      また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
+#      由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
+#      免責すること．
+#
+#  本ソフトウェアは，AUTOSAR（AUTomotive Open System ARchitecture）仕
+#  様に基づいている．上記の許諾は，AUTOSARの知的財産権を許諾するもので
+#  はない．AUTOSARは，AUTOSAR仕様に基づいたソフトウェアを商用目的で利
+#  用する者に対して，AUTOSARパートナーになることを求めている．
+#
+#  本ソフトウェアは，無保証で提供されているものである．上記著作権者お
+#  よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
+#  に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
+#  アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
+#  の責任を負わない．
+#
+#  $Id: Makefile.target 1801 2015-03-27 06:34:43Z t_ishikawa $
+#
+
+#
+#		Makefile のターゲット依存部（NIOS2_DEV用）
+#
+
+#
+#  ボード名の定義
+#
+#BOARD = nios2_dev_2s180
+#BOARD = nios2_dev_de2_115
+BOARD = nios2_dev_de0_nano
+
+#
+#  32bit境界への関数の配置を有効に
+#
+ALIGN_FUNCTIONS_32 = true
+
+#
+#  コードをSDRAMに配置する
+#
+PLACE_SDRAM = true
+
+#
+#  シリアル出力をUARTにする
+#
+SERIAL_UART = false
+
+ifeq ($(SERIAL_UART),true)
+	CDEFS := $(CDEFS) -DUSE_UART
+	UART_OBJ := uart.o
+else
+	UART_OBJ := jtag_uart.o
+endif
+
+#
+#  ボード毎に設定が異なる項目
+#
+ifeq ($(BOARD),nios2_dev_2s180)
+	CDEFS := $(CDEFS) -DTOPPERS_NIOS2_DEV_2S180
+	LDSCRIPT = $(TARGETDIR)/nios2_dev_2s180_onchip.ld
+	ifeq ($(PLACE_SDRAM),true)
+		LDSCRIPT = $(TARGETDIR)/nios2_dev_2s180.ld
+	endif
+endif
+
+ifeq ($(BOARD),nios2_dev_de2_115)
+	CDEFS := $(CDEFS) -DTOPPERS_NIOS2_DEV_DE2_115
+	LDSCRIPT = $(TARGETDIR)/nios2_dev_de2_115_onchip.ld
+	ifeq ($(PLACE_SDRAM),true)
+		LDSCRIPT = $(TARGETDIR)/nios2_dev_de2_115.ld
+	endif
+endif
+
+ifeq ($(BOARD),nios2_dev_de0_nano)
+	CDEFS := $(CDEFS) -DTOPPERS_NIOS2_DEV_DE0_NANO
+	LDSCRIPT = $(TARGETDIR)/nios2_dev_de0_nano_onchip.ld
+	ifeq ($(PLACE_SDRAM),true)
+		LDSCRIPT = $(TARGETDIR)/nios2_dev_de0_nano.ld
+	endif
+endif
+
+#
+#  コンパイルオプション
+#
+INCLUDES := $(INCLUDES) -I$(TARGETDIR)
+
+#
+#  サポート命令毎のコンパイルオプション
+#
+# ノーマル
+COPTS   := $(COPTS) -mhw-mul -mhw-div
+
+#
+#  カーネルに関する定義
+#
+KERNEL_DIR := $(KERNEL_DIR) $(TARGETDIR)
+KERNEL_ASMOBJS := $(KERNEL_ASMOBJS)
+KERNEL_COBJS := $(KERNEL_COBJS) target_config.o target_hw_counter.o
+
+#
+#  システムモジュールに関する定義
+#
+SYSMOD_DIR := $(SYSMOD_DIR) $(TARGETDIR)
+SYSMOD_COBJS := $(SYSMOD_COBJS) $(UART_OBJ)
+
+
+#
+#  コンフィギュレーション設定
+#
+ifeq ($(findstring target_timer,$(CFGNAME)),target_timer)
+  CFGNAME := $(CFGNAME) avalon_timer
+endif
+ifeq ($(findstring target_serial,$(CFGNAME)),target_serial)
+  CFGNAME := $(CFGNAME) prc_serial
+endif
+
+#
+#  依存関係の定義
+#
+Os_Lcfg.timestamp: $(TARGETDIR)/target.tf
+$(OBJFILE): $(TARGETDIR)/target_check.tf
+offset.h: $(TARGETDIR)/target_offset.tf
+
+#
+#  オフセットファイル生成のための定義
+#
+OFFSET_TF := $(TARGETDIR)/target_offset.tf
+
+#
+#  プロセッサ依存部のインクルード
+#
+include $(SRCDIR)/arch/nios2_gcc/Makefile.prc
+
+#
+#  各種コマンドの実行
+#
+run: $(OBJNAME).srec
+	nios2-gdb-server.exe --cable=USB-Blaster --no-verify -r --go $(OBJNAME).srec &
+	nios2-terminal --cable=USB-Blaster -q
+
+run1: $(OBJNAME).srec
+	nios2-gdb-server.exe --cable="USB-Blaster [USB-0]" --no-verify -r --go $(OBJNAME).srec &
+	nios2-terminal --cable="USB-Blaster [USB-0]" -q
+
+run2: $(OBJNAME).srec
+	nios2-gdb-server.exe --cable="USB-Blaster [USB-1]" --no-verify -r --go $(OBJNAME).srec &
+	nios2-terminal --cable="USB-Blaster [USB-1]" -q
+
+arun: $(OBJNAME).srec
+	@nios2-gdb-server.exe --cable=USB-Blaster --no-verify -r --go $(OBJNAME).srec 1>&2 &
+	@expect -c "set timeout -1; spawn nios2-terminal --cable=USB-Blaster -q; expect \"Kernel Exit...\"; send \"\003\""
+
+urun: $(OBJNAME).srec
+	@cygstart --shownoactivate nios2-gdb-server.exe --cable=USB-Blaster --no-verify --wait 2 -r --go $(OBJNAME).srec &
+	@ruby $(TARGETDIR)/com_port.rb
+
+cppt: $(OBJNAME).srec
+	@nios2-gdb-server.exe --cable=USB-Blaster --no-verify -r --go $(OBJNAME).srec 1>&2 &
+	@expect -c "set timeout -1; spawn nios2-terminal --cable=USB-Blaster -q; expect \"Kernel Exit...\"; send \"\003\"" | tee cpptest_results.txt
+	@grep CLOG: cpptest_results.txt | sed -e "1d" | sed -e 's/^CLOG: //' > temp.clog
+	@hextobin.exe temp.clog cpptest_results.clog
+	@rm -f temp.clog
+
+ucppt: $(OBJNAME).srec
+	@cygstart --shownoactivate nios2-gdb-server.exe --cable=USB-Blaster --no-verify --wait 2 -r --go $(OBJNAME).srec &
+	@ruby $(TARGETDIR)/com_port.rb | tee cpptest_results.txt
+	@grep CLOG: cpptest_results.txt | sed -e "1d" | sed -e 's/^CLOG: //' > temp.clog
+	@hextobin.exe temp.clog cpptest_results.clog
+	@rm -f temp.clog
+
+db: $(OBJFILE)
+	cygstart --shownoactivate `which nios2-gdb-server` --cable=USB-Blaster --tcpport=1234 -r&
+	cygstart --shownoactivate `which nios2-terminal` --cable=USB-Blaster&
+	nios2-gdb $(OBJFILE) -command $(TARGETDIR)/gdb.ini
+
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/SmpC1ISR.S
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/SmpC1ISR.S	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/SmpC1ISR.S	(revision 295)
@@ -0,0 +1,147 @@
+/*
+ *  TOPPERS ATK2
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *      Automotive Kernel Version 2
+ *
+ *  Copyright (C) 2011-2015 by Center for Embedded Computing Systems
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2011-2015 by FUJI SOFT INCORPORATED, JAPAN
+ *  Copyright (C) 2011-2013 by Spansion LLC, USA
+ *  Copyright (C) 2011-2015 by NEC Communication Systems, Ltd., JAPAN
+ *  Copyright (C) 2011-2015 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
+ *  Copyright (C) 2011-2014 by Renesas Electronics Corporation, JAPAN
+ *  Copyright (C) 2011-2015 by Sunny Giken Inc., JAPAN
+ *  Copyright (C) 2011-2015 by TOSHIBA CORPORATION, JAPAN
+ *  Copyright (C) 2011-2015 by Witz Corporation
+ *  Copyright (C) 2014-2015 by AISIN COMCRUISE Co., Ltd., JAPAN
+ *  Copyright (C) 2014-2015 by eSOL Co.,Ltd., JAPAN
+ *  Copyright (C) 2014-2015 by SCSK Corporation, JAPAN
+ *
+ *  上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
+ *  ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
+ *  変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
+ *  (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
+ *      権表示，この利用条件および下記の無保証規定が，そのままの形でソー
+ *      スコード中に含まれていること．
+ *  (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
+ *      用できる形で再配布する場合には，再配布に伴うドキュメント（利用
+ *      者マニュアルなど）に，上記の著作権表示，この利用条件および下記
+ *      の無保証規定を掲載すること．
+ *  (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
+ *      用できない形で再配布する場合には，次のいずれかの条件を満たすこ
+ *      と．
+ *    (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
+ *        作権表示，この利用条件および下記の無保証規定を掲載すること．
+ *    (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
+ *        報告すること．
+ *  (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
+ *      害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
+ *      また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
+ *      由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
+ *      免責すること．
+ *
+ *  本ソフトウェアは，AUTOSAR（AUTomotive Open System ARchitecture）仕
+ *  様に基づいている．上記の許諾は，AUTOSARの知的財産権を許諾するもので
+ *  はない．AUTOSARは，AUTOSAR仕様に基づいたソフトウェアを商用目的で利
+ *  用する者に対して，AUTOSARパートナーになることを求めている．
+ *
+ *  本ソフトウェアは，無保証で提供されているものである．上記著作権者お
+ *  よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
+ *  に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
+ *  アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
+ *  の責任を負わない．
+ *
+ *  $Id: SmpC1ISR.S 1801 2015-03-27 06:34:43Z t_ishikawa $
+ */
+
+#define TOPPERS_MACRO_ONLY
+
+#define UINT_C(val)	(val)
+#define CAST(type, val)	(val)	/* 型キャストを行うマクロ */
+
+#include "kernel/kernel_impl.h"
+#include "vic.h"
+#include "nios2.h"
+#include "target_test.h"
+
+.global C1ISRMainSmpC1ISR
+.set noat
+
+C1ISRMainSmpC1ISR:
+	addi	ea,	ea,	-4	/* 戻り番地をデクリメント */
+
+	/* レジスタの保存 */
+	addi	sp,	sp,	-76
+	stw		at,		0(sp)
+	stw		r2,		4(sp)
+	stw		r3,		8(sp)
+	stw		r4,		12(sp)
+	stw		r5,		16(sp)
+	stw		r6,		20(sp)
+	stw		r7,		24(sp)
+	stw		r8,		28(sp)
+	stw		r9,		32(sp)
+	stw		r10,	36(sp)
+	stw		r11,	40(sp)
+	stw		r12,	44(sp)
+	stw		r13,	48(sp)
+	stw		r14,	52(sp)
+	stw		r15,	56(sp)
+	stw		ra,		60(sp)
+	stw		ea,		64(sp)
+	rdctl	et,		estatus
+	stw		et,		68(sp)
+
+	rdctl   r2, status
+	ori     r2, r2, STATUS_PIE
+	wrctl   status, r2
+
+	/* 割込み発生前のcallevel_statをスタックに保存 */
+	ldh		r2,		%gprel(callevel_stat)(gp)
+	stw		r2,		72(sp)
+
+
+	/* callevel_statにC1ISRをセット */
+	ldhu	et,		%gprel(callevel_stat)(gp)
+	ori		et,		et,	TSYS_ISR1
+	sth		et,		%gprel(callevel_stat)(gp)
+
+	/*
+	 *  タイマ割込みをクリア
+	 */
+	movia	et,		TIMER_STATUS(TIMER_5_IRQ)
+	stwio	zero,	0(et)
+
+	call	c1isr_syslog
+
+	ldw		r2,		72(sp)
+	sth		r2,		%gprel(callevel_stat)(gp)
+
+	rdctl r2, status
+	movi  r3, ~STATUS_PIE
+	and   r2, r2, r3
+	wrctl status, r2
+
+	/* レジスタの復帰 */
+	ldw		at,		0(sp)
+	ldw		r2,		4(sp)
+	ldw		r3,		8(sp)
+	ldw		r4,		12(sp)
+	ldw		r5,		16(sp)
+	ldw		r6,		20(sp)
+	ldw		r7,		24(sp)
+	ldw		r8,		28(sp)
+	ldw		r9,		32(sp)
+	ldw		r10,	36(sp)
+	ldw		r11,	40(sp)
+	ldw		r12,	44(sp)
+	ldw		r13,	48(sp)
+	ldw		r14,	52(sp)
+	ldw		r15,	56(sp)
+	ldw		ra,		60(sp)
+	ldw		ea,		64(sp)
+	ldw		et,		68(sp)
+	wrctl	estatus,	et
+	addi	sp,	sp,	76
+
+	eret
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/com_port.rb
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/com_port.rb	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/com_port.rb	(revision 295)
@@ -0,0 +1,179 @@
+#!ruby
+#
+#  TOPPERS ATK2
+#      Toyohashi Open Platform for Embedded Real-Time Systems
+#      Automotive Kernel Version 2
+#
+#  Copyright (C) 2011-2015 by Center for Embedded Computing Systems
+#              Graduate School of Information Science, Nagoya Univ., JAPAN
+#  Copyright (C) 2011-2015 by FUJI SOFT INCORPORATED, JAPAN
+#  Copyright (C) 2011-2013 by Spansion LLC, USA
+#  Copyright (C) 2011-2015 by NEC Communication Systems, Ltd., JAPAN
+#  Copyright (C) 2011-2015 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
+#  Copyright (C) 2011-2014 by Renesas Electronics Corporation, JAPAN
+#  Copyright (C) 2011-2015 by Sunny Giken Inc., JAPAN
+#  Copyright (C) 2011-2015 by TOSHIBA CORPORATION, JAPAN
+#  Copyright (C) 2011-2015 by Witz Corporation
+#  Copyright (C) 2014-2015 by AISIN COMCRUISE Co., Ltd., JAPAN
+#  Copyright (C) 2014-2015 by eSOL Co.,Ltd., JAPAN
+#  Copyright (C) 2014-2015 by SCSK Corporation, JAPAN
+#
+#  上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
+#  ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
+#  変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
+#  (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
+#      権表示，この利用条件および下記の無保証規定が，そのままの形でソー
+#      スコード中に含まれていること．
+#  (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
+#      用できる形で再配布する場合には，再配布に伴うドキュメント（利用
+#      者マニュアルなど）に，上記の著作権表示，この利用条件および下記
+#      の無保証規定を掲載すること．
+#  (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
+#      用できない形で再配布する場合には，次のいずれかの条件を満たすこ
+#      と．
+#    (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
+#        作権表示，この利用条件および下記の無保証規定を掲載すること．
+#    (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
+#        報告すること．
+#  (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
+#      害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
+#      また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
+#      由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
+#      免責すること．
+#
+#  本ソフトウェアは，AUTOSAR（AUTomotive Open System ARchitecture）仕
+#  様に基づいている．上記の許諾は，AUTOSARの知的財産権を許諾するもので
+#  はない．AUTOSARは，AUTOSAR仕様に基づいたソフトウェアを商用目的で利
+#  用する者に対して，AUTOSARパートナーになることを求めている．
+#
+#  本ソフトウェアは，無保証で提供されているものである．上記著作権者お
+#  よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
+#  に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
+#  アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
+#  の責任を負わない．
+#
+#  $Id: com_port.rb 1801 2015-03-27 06:34:43Z t_ishikawa $
+#
+
+# 要インストール：$ gem install serialport
+require "rubygems"
+require "serialport"
+
+Thread.abort_on_exception = true
+
+# 引数1: CORE0からのオフセット
+nOffset = 0
+if (ARGV.size() >= 1)
+  nOffset = ARGV[0].to_i()
+end
+
+# 引数2: 終了フラグ
+bTerminate = false
+if (ARGV.size() >= 2)
+  bTerminate = ARGV[1]
+end
+
+
+# ctrl+cによる強制終了設定
+Signal.trap(:SIGINT){
+  system("kill -9 #$$")
+}
+
+
+# ポート判定
+PORT_PREFIX = "/dev/ttyS"
+aPorts = []
+thSearchPort = Thread.new {
+  IO.popen("ls -1 #{PORT_PREFIX}*") do |io|
+    while io.gets()
+      aPorts.push($_.gsub!(PORT_PREFIX, "").gsub!("\n", "").to_i())
+    end
+  end
+}
+thSearchPort.join()
+
+# COMポートが存在しない場合は終了
+if (aPorts.empty?())
+  puts("COM port is not found.")
+  exit(1)
+end
+
+nPreNum = -1
+nTargetPort = -1
+aPorts.sort.reverse.each{|nNumber|
+  if (nPreNum == -1)
+    nPreNum = nNumber
+    # ポートが1つのみだった場合への対応
+    nTargetPort = nNumber
+  else
+    # 大きい方から数えて連番でなくなった数値を対象ポートとする
+    if (!((nPreNum - nNumber) == 1))
+      nTargetPort = nPreNum
+      break
+    else
+      nPreNum = nNumber
+      # 全て連番となっていた場合への対応
+      nTargetPort = nNumber
+    end
+  end
+}
+
+
+# CORE0からのオフセット補正
+nTargetPort += nOffset
+
+
+# USBを挿した直後への対応
+sChk = ""
+thUSB = Thread.new {
+  while true
+    IO.popen("stty -F #{PORT_PREFIX}#{nTargetPort}") do |io|
+      while io.gets()
+        sChk = $_
+      end
+    end
+    if (!sChk.include?("Invalid argument"))
+      break
+    end
+  end
+}
+thUSB.join()
+
+
+cCom = nil
+nBaudrate = 921600
+thMain = Thread.new {
+  puts("\nUsing COM port: #{(nTargetPort+1).to_s()} [#{nBaudrate.to_s()}]")
+
+  cCom = SerialPort.open("/dev/ttyS#{nTargetPort}", nBaudrate, 8, 1, SerialPort::NONE)
+
+  while true
+    sLine = cCom.gets()
+    print(sLine)
+    if (sLine == "Kernel Exit...\n")
+      # CORE0もしくは終了フラグがfalseでない場合のみ終了する
+      if ((nOffset == 0) || (bTerminate != false))
+        break
+      end
+    end
+  end
+
+  cCom.close()
+}
+
+
+# COMポート接続中もctrl+cで強制終了するためのダミースレッド
+thDummy = Thread.new {
+  while true
+    sleep(1)
+  end
+}
+
+# 3時間でタイムアウト
+# (シリアル受信が停止した場合への対処)
+result = thMain.join(10800)
+if (result.nil?())
+  puts("[com_port.rb] timeout!!")
+  cCom.close()
+end
+
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/gdb.ini
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/gdb.ini	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/gdb.ini	(revision 295)
@@ -0,0 +1,12 @@
+# .gdbinit for nios2
+
+define show_regs
+	info all-registers
+end
+
+define init_nios2
+	target remote localhost:1234
+	load
+end
+
+init_nios2
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/nios2_dev_2s180.ld
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/nios2_dev_2s180.ld	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/nios2_dev_2s180.ld	(revision 295)
@@ -0,0 +1,319 @@
+ENTRY("start")
+MEMORY
+{
+    ext_flash            : ORIGIN = 0x00000000, LENGTH = 0x01000000
+
+    onchip_ram_64_kbytes : ORIGIN = 0x01100000, LENGTH = 0x00010000
+
+    onchip_reset         : ORIGIN = 0x05000000, LENGTH = 0x20
+    onchip               : ORIGIN = 0x05000020, LENGTH = 0x00080000-0x20
+
+    sram                 : ORIGIN = 0x09000000, LENGTH = 0x00100000
+
+    sdram                : ORIGIN = 0x0a000000, LENGTH = 0x01000000
+}
+
+/* Define symbols for each memory base-address */
+
+/*
+ __alt_mem_ext_flash = 0x00000000 ;
+ __alt_mem_sram = 0x08000000 ;
+ __alt_mem_onchip_ram_64_kbytes = 0x0c010000 ;
+ __alt_mem_sdram = 0x05000000 ;
+*/
+
+PROVIDE(hardware_init_hook = 0);
+PROVIDE(software_init_hook = 0);
+PROVIDE(software_term_hook = 0);
+PROVIDE( __alt_data_end = 0x02000000 );
+
+PROVIDE(StartupHook = 0);
+PROVIDE(ShutdownHook = 0);
+PROVIDE(PreTaskHook = 0);
+PROVIDE(PostTaskHook = 0);
+PROVIDE(ErrorHook = 0);
+PROVIDE(ProtectionHook = 0);
+
+OUTPUT_FORMAT( "elf32-littlenios2",
+               "elf32-littlenios2",
+               "elf32-littlenios2" )
+OUTPUT_ARCH( nios2 )
+STARTUP(start.o)
+ENTRY(start)
+
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;
+ */
+
+SECTIONS
+{
+    .entry :
+    {
+        KEEP (*(.entry))
+    } > onchip_reset
+
+    .exceptions :
+    {
+        . = ALIGN(0x20);
+        *(.irq)
+        KEEP (*(.exceptions));
+    } > onchip
+
+    .text :
+    {
+        /*
+         * All code sections are merged into the text output section, along with
+         * the read only data sections.
+         *
+         */
+
+        PROVIDE (stext = ABSOLUTE(.));
+
+        *(.interp)
+        *(.hash)
+        *(.dynsym)
+        *(.dynstr)
+        *(.gnu.version)
+        *(.gnu.version_d)
+        *(.gnu.version_r)
+        *(.rel.init)
+        *(.rela.init)
+        *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
+        *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+        *(.rel.fini)
+        *(.rela.fini)
+        *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
+        *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+        *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
+        *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+        *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
+        *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+        *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
+        *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+        *(.rel.ctors)
+        *(.rela.ctors)
+        *(.rel.dtors)
+        *(.rela.dtors)
+        *(.rel.got)
+        *(.rela.got)
+        *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)
+        *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
+        *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)
+        *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
+        *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)
+        *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
+        *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)
+        *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
+        *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
+        *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+        *(.rel.plt)
+        *(.rela.plt)
+
+        KEEP (*(.init))
+        *(.plt)
+        *(.text .stub .text.* .gnu.linkonce.t.*)
+
+        /* .gnu.warning sections are handled specially by elf32.em.  */
+
+        *(.gnu.warning.*)
+        KEEP (*(.fini))
+        PROVIDE (__etext = ABSOLUTE(.));
+        PROVIDE (_etext = ABSOLUTE(.));
+        PROVIDE (etext = ABSOLUTE(.));
+
+        *(.eh_frame_hdr)
+        /* Ensure the __preinit_array_start label is properly aligned.  We
+           could instead move the label definition inside the section, but
+           the linker would then create the section even if it turns out to
+           be empty, which isn't pretty.  */
+        . = ALIGN(32 / 8);
+        PROVIDE (__preinit_array_start = ABSOLUTE(.));
+        *(.preinit_array)
+        PROVIDE (__preinit_array_end = ABSOLUTE(.));
+        PROVIDE (__init_array_start = ABSOLUTE(.));
+        *(.init_array)
+        PROVIDE (__init_array_end = ABSOLUTE(.));
+        PROVIDE (__fini_array_start = ABSOLUTE(.));
+        *(.fini_array)
+        PROVIDE (__fini_array_end = ABSOLUTE(.));
+        SORT(CONSTRUCTORS)
+        KEEP (*(.eh_frame))
+        *(.gcc_except_table)
+        *(.dynamic)
+
+        /* gcc normally uses crtbegin.o to find the start of
+           the constructors instead nios2 use crtdotors.o,
+           so we make sure it is
+           first.  Because this is a wildcard, it
+           doesn't matter if the user does not
+           actually link against crtdotors.o; the
+           linker won't look for a file to match a
+           wildcard.  The wildcard also means that it
+           doesn't matter which directory crtdotors.o
+           is in.  */
+        KEEP (*crtdotors.o(.ctors))
+        /* We don't want to include the .ctor section from
+           from the crtendtors (gcc normally uses crtend.o)
+           file until after the sorted ctors.
+           The .ctor section from the crtendtors file contains the
+           end of ctors marker and it must be last */
+        KEEP (*(EXCLUDE_FILE (*crtendtors.o ) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*(.ctors))
+        KEEP (*crtdotors.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtendtors.o ) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*(.dtors))
+        KEEP (*(.jcr))
+    } > sdram =0x0001883a /* NOP on Nios2 */
+
+    .rodata :
+    {
+        . = ALIGN(32 / 8);
+        *(.rodata .rodata.* .gnu.linkonce.r.*)
+        *(.rodata1)
+    } > sdram
+
+    .rwdata :
+    {
+        . = ALIGN(32 / 8);
+        *(.got.plt) *(.got)
+        *(.data1)
+        *(.data .data.* .gnu.linkonce.d.*)
+
+        _gp = ABSOLUTE(. + 0x7ff0);
+        PROVIDE(gp = _gp);
+
+        *(.sdata .sdata.* .gnu.linkonce.s.*)
+        *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
+
+        . = ALIGN(32 / 8);
+        _edata = ABSOLUTE(.);
+        PROVIDE (edata = ABSOLUTE(.));
+    } > sdram
+
+    .bss :
+    {
+        __bss_start = ABSOLUTE(.);
+        PROVIDE (__sbss_start = ABSOLUTE(.));
+        PROVIDE (___sbss_start = ABSOLUTE(.));
+
+        *(.dynsbss)
+        *(.sbss .sbss.* .gnu.linkonce.sb.*)
+        *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)
+        *(.scommon)
+
+        PROVIDE (__sbss_end = ABSOLUTE(.));
+        PROVIDE (___sbss_end = ABSOLUTE(.));
+
+        *(.dynbss)
+        *(.bss .bss.* .gnu.linkonce.b.*)
+        *(COMMON)
+
+        . = ALIGN(32 / 8);
+        __bss_end = ABSOLUTE(.);
+    } > sdram
+
+    /*
+     * One output section for each of the available partitions. These are not
+     * used by default, but can be used by users applications using the .section
+     * directive.
+     *
+     * The memory partition used for the heap is treated in  special way, i.e. a
+     * symbol is added to point to the heap start.
+     *
+     */
+
+    .ext_flash :
+    {
+        PROVIDE (_alt_partition_ext_flash_start = ABSOLUTE(.));
+        *(.ext_flash)
+        . = ALIGN(32 / 8);
+        PROVIDE (_alt_partition_ext_flash_end = ABSOLUTE(.));
+    } > ext_flash
+
+    .sram :
+    {
+        PROVIDE (_alt_partition_sram_start = ABSOLUTE(.));
+        *(.sram)
+        . = ALIGN(32 / 8);
+        PROVIDE (_alt_partition_sram_end = ABSOLUTE(.));
+    } > sram
+
+    .nlsram (NOLOAD):
+    {
+        PROVIDE (_alt_partition_nlsram_start = ABSOLUTE(.));
+        *(.nlsram)
+        . = ALIGN(32 / 8);
+        PROVIDE (_alt_partition_nlsram_end = ABSOLUTE(.));
+    } > sram
+
+    .onchip_ram_64_kbytes :
+    {
+        PROVIDE (_alt_partition_onchip_ram_64_kbytes_start = ABSOLUTE(.));
+        *(.onchip_ram_64_kbytes)
+        . = ALIGN(32 / 8);
+        PROVIDE (_alt_partition_onchip_ram_64_kbytes_end = ABSOLUTE(.));
+    } > onchip_ram_64_kbytes
+
+    .sdram :
+    {
+        PROVIDE (_alt_partition_sdram_start = ABSOLUTE(.));
+        *(.sdram)
+        . = ALIGN(32 / 8);
+        PROVIDE (_alt_partition_sdram_end = ABSOLUTE(.));
+        _end = ABSOLUTE(.);
+        PROVIDE (end = ABSOLUTE(.));
+    } > sdram
+
+    .nlsdram (NOLOAD):
+    {
+        PROVIDE (_alt_partition_nlsdram_start = ABSOLUTE(.));
+        *(.nlsdram)
+        . = ALIGN(32 / 8);
+        PROVIDE (_alt_partition_nlsdram_end = ABSOLUTE(.));
+        _end = ABSOLUTE(.);
+        PROVIDE (end = ABSOLUTE(.));
+    } > sdram
+
+    /*
+     * Stabs debugging sections.
+     *
+     */
+
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+       Symbols in the DWARF debugging sections are relative to the beginning
+       of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
+/* provide a pointer for the stack */
+
+
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/nios2_dev_2s180_onchip.ld
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/nios2_dev_2s180_onchip.ld	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/nios2_dev_2s180_onchip.ld	(revision 295)
@@ -0,0 +1,319 @@
+ENTRY("start")
+MEMORY
+{
+    ext_flash            : ORIGIN = 0x00000000, LENGTH = 0x01000000
+
+    onchip_ram_64_kbytes : ORIGIN = 0x01100000, LENGTH = 0x00010000
+
+    onchip_reset         : ORIGIN = 0x05000000, LENGTH = 0x20
+    onchip               : ORIGIN = 0x05000020, LENGTH = 0x00080000-0x20
+
+    sram                 : ORIGIN = 0x09000000, LENGTH = 0x00100000
+
+    sdram                : ORIGIN = 0x0a000000, LENGTH = 0x01000000
+}
+
+/* Define symbols for each memory base-address */
+
+/*
+ __alt_mem_ext_flash = 0x00000000 ;
+ __alt_mem_sram = 0x08000000 ;
+ __alt_mem_onchip_ram_64_kbytes = 0x0c010000 ;
+ __alt_mem_sdram = 0x05000000 ;
+*/
+
+PROVIDE(hardware_init_hook = 0);
+PROVIDE(software_init_hook = 0);
+PROVIDE(software_term_hook = 0);
+PROVIDE( __alt_data_end = 0x02000000 );
+
+PROVIDE(StartupHook = 0);
+PROVIDE(ShutdownHook = 0);
+PROVIDE(PreTaskHook = 0);
+PROVIDE(PostTaskHook = 0);
+PROVIDE(ErrorHook = 0);
+PROVIDE(ProtectionHook = 0);
+
+OUTPUT_FORMAT( "elf32-littlenios2",
+               "elf32-littlenios2",
+               "elf32-littlenios2" )
+OUTPUT_ARCH( nios2 )
+STARTUP(start.o)
+ENTRY(__reset)
+
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;
+ */
+
+SECTIONS
+{
+    .entry :
+    {
+        KEEP (*(.entry))
+    } > onchip_reset
+
+    .exceptions :
+    {
+        . = ALIGN(0x20);
+        *(.irq)
+        KEEP (*(.exceptions));
+    } > onchip
+
+    .text :
+    {
+        /*
+         * All code sections are merged into the text output section, along with
+         * the read only data sections.
+         *
+         */
+
+        PROVIDE (stext = ABSOLUTE(.));
+
+        *(.interp)
+        *(.hash)
+        *(.dynsym)
+        *(.dynstr)
+        *(.gnu.version)
+        *(.gnu.version_d)
+        *(.gnu.version_r)
+        *(.rel.init)
+        *(.rela.init)
+        *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
+        *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+        *(.rel.fini)
+        *(.rela.fini)
+        *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
+        *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+        *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
+        *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+        *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
+        *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+        *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
+        *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+        *(.rel.ctors)
+        *(.rela.ctors)
+        *(.rel.dtors)
+        *(.rela.dtors)
+        *(.rel.got)
+        *(.rela.got)
+        *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)
+        *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
+        *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)
+        *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
+        *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)
+        *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
+        *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)
+        *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
+        *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
+        *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+        *(.rel.plt)
+        *(.rela.plt)
+
+        KEEP (*(.init))
+        *(.plt)
+        *(.text .stub .text.* .gnu.linkonce.t.*)
+
+        /* .gnu.warning sections are handled specially by elf32.em.  */
+
+        *(.gnu.warning.*)
+        KEEP (*(.fini))
+        PROVIDE (__etext = ABSOLUTE(.));
+        PROVIDE (_etext = ABSOLUTE(.));
+        PROVIDE (etext = ABSOLUTE(.));
+
+        *(.eh_frame_hdr)
+        /* Ensure the __preinit_array_start label is properly aligned.  We
+           could instead move the label definition inside the section, but
+           the linker would then create the section even if it turns out to
+           be empty, which isn't pretty.  */
+        . = ALIGN(32 / 8);
+        PROVIDE (__preinit_array_start = ABSOLUTE(.));
+        *(.preinit_array)
+        PROVIDE (__preinit_array_end = ABSOLUTE(.));
+        PROVIDE (__init_array_start = ABSOLUTE(.));
+        *(.init_array)
+        PROVIDE (__init_array_end = ABSOLUTE(.));
+        PROVIDE (__fini_array_start = ABSOLUTE(.));
+        *(.fini_array)
+        PROVIDE (__fini_array_end = ABSOLUTE(.));
+        SORT(CONSTRUCTORS)
+        KEEP (*(.eh_frame))
+        *(.gcc_except_table)
+        *(.dynamic)
+
+        /* gcc normally uses crtbegin.o to find the start of
+           the constructors instead nios2 use crtdotors.o,
+           so we make sure it is
+           first.  Because this is a wildcard, it
+           doesn't matter if the user does not
+           actually link against crtdotors.o; the
+           linker won't look for a file to match a
+           wildcard.  The wildcard also means that it
+           doesn't matter which directory crtdotors.o
+           is in.  */
+        KEEP (*crtdotors.o(.ctors))
+        /* We don't want to include the .ctor section from
+           from the crtendtors (gcc normally uses crtend.o)
+           file until after the sorted ctors.
+           The .ctor section from the crtendtors file contains the
+           end of ctors marker and it must be last */
+        KEEP (*(EXCLUDE_FILE (*crtendtors.o ) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*(.ctors))
+        KEEP (*crtdotors.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtendtors.o ) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*(.dtors))
+        KEEP (*(.jcr))
+    } > onchip =0x0001883a /* NOP on Nios2 */
+
+    .rodata :
+    {
+        . = ALIGN(32 / 8);
+        *(.rodata .rodata.* .gnu.linkonce.r.*)
+        *(.rodata1)
+    } > onchip
+
+    .rwdata :
+    {
+        . = ALIGN(32 / 8);
+        *(.got.plt) *(.got)
+        *(.data1)
+        *(.data .data.* .gnu.linkonce.d.*)
+
+        _gp = ABSOLUTE(. + 0x7ff0);
+        PROVIDE(gp = _gp);
+
+        *(.sdata .sdata.* .gnu.linkonce.s.*)
+        *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
+
+        . = ALIGN(32 / 8);
+        _edata = ABSOLUTE(.);
+        PROVIDE (edata = ABSOLUTE(.));
+    } > onchip
+
+    .bss :
+    {
+        __bss_start = ABSOLUTE(.);
+        PROVIDE (__sbss_start = ABSOLUTE(.));
+        PROVIDE (___sbss_start = ABSOLUTE(.));
+
+        *(.dynsbss)
+        *(.sbss .sbss.* .gnu.linkonce.sb.*)
+        *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)
+        *(.scommon)
+
+        PROVIDE (__sbss_end = ABSOLUTE(.));
+        PROVIDE (___sbss_end = ABSOLUTE(.));
+
+        *(.dynbss)
+        *(.bss .bss.* .gnu.linkonce.b.*)
+        *(COMMON)
+
+        . = ALIGN(32 / 8);
+        __bss_end = ABSOLUTE(.);
+    } > onchip
+
+    /*
+     * One output section for each of the available partitions. These are not
+     * used by default, but can be used by users applications using the .section
+     * directive.
+     *
+     * The memory partition used for the heap is treated in  special way, i.e. a
+     * symbol is added to point to the heap start.
+     *
+     */
+
+    .ext_flash :
+    {
+        PROVIDE (_alt_partition_ext_flash_start = ABSOLUTE(.));
+        *(.ext_flash)
+        . = ALIGN(32 / 8);
+        PROVIDE (_alt_partition_ext_flash_end = ABSOLUTE(.));
+    } > ext_flash
+
+    .sram :
+    {
+        PROVIDE (_alt_partition_sram_start = ABSOLUTE(.));
+        *(.sram)
+        . = ALIGN(32 / 8);
+        PROVIDE (_alt_partition_sram_end = ABSOLUTE(.));
+    } > sram
+
+    .nlsram (NOLOAD):
+    {
+        PROVIDE (_alt_partition_nlsram_start = ABSOLUTE(.));
+        *(.nlsram)
+        . = ALIGN(32 / 8);
+        PROVIDE (_alt_partition_nlsram_end = ABSOLUTE(.));
+    } > sram
+
+    .onchip_ram_64_kbytes :
+    {
+        PROVIDE (_alt_partition_onchip_ram_64_kbytes_start = ABSOLUTE(.));
+        *(.onchip_ram_64_kbytes)
+        . = ALIGN(32 / 8);
+        PROVIDE (_alt_partition_onchip_ram_64_kbytes_end = ABSOLUTE(.));
+    } > onchip_ram_64_kbytes
+
+    .sdram :
+    {
+        PROVIDE (_alt_partition_sdram_start = ABSOLUTE(.));
+        *(.sdram)
+        . = ALIGN(32 / 8);
+        PROVIDE (_alt_partition_sdram_end = ABSOLUTE(.));
+        _end = ABSOLUTE(.);
+        PROVIDE (end = ABSOLUTE(.));
+    } > sdram
+
+    .nlsdram (NOLOAD):
+    {
+        PROVIDE (_alt_partition_nlsdram_start = ABSOLUTE(.));
+        *(.nlsdram)
+        . = ALIGN(32 / 8);
+        PROVIDE (_alt_partition_nlsdram_end = ABSOLUTE(.));
+        _end = ABSOLUTE(.);
+        PROVIDE (end = ABSOLUTE(.));
+    } > sdram
+
+    /*
+     * Stabs debugging sections.
+     *
+     */
+
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+       Symbols in the DWARF debugging sections are relative to the beginning
+       of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
+/* provide a pointer for the stack */
+
+
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/nios2_dev_de0_nano.ld
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/nios2_dev_de0_nano.ld	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/nios2_dev_de0_nano.ld	(revision 295)
@@ -0,0 +1,298 @@
+MEMORY
+{
+    sdram_UNUSED         : ORIGIN = 0x00000000, LENGTH = 0x00000020
+    sdram                : ORIGIN = 0x00000020, LENGTH = 0x02000000-0x20
+
+    ext_flash            : ORIGIN = 0x04000000, LENGTH = 0x01000000
+
+    sram_reset           : ORIGIN = 0x05000000, LENGTH = 0x00000020
+    sram                 : ORIGIN = 0x05000020, LENGTH = 0x00100000-0x20
+}
+
+/* Define symbols for each memory base-address */
+ __alt_mem_ext_flash = 0x00000000 ;
+ __alt_mem_ext_ram = 0x00800000 ;
+ __alt_mem_onchip_ram_64_kbytes = 0x00900000 ;
+ __alt_mem_sdram = 0x05000000 ;
+
+PROVIDE(hardware_init_hook = 0);
+PROVIDE(software_init_hook = 0);
+PROVIDE(software_term_hook = 0);
+PROVIDE( __alt_data_end = 0x02000000 );
+
+PROVIDE(StartupHook = 0);
+PROVIDE(ShutdownHook = 0);
+PROVIDE(PreTaskHook = 0);
+PROVIDE(PostTaskHook = 0);
+PROVIDE(ErrorHook = 0);
+PROVIDE(ProtectionHook = 0);
+
+OUTPUT_FORMAT( "elf32-littlenios2",
+               "elf32-littlenios2",
+               "elf32-littlenios2" )
+OUTPUT_ARCH( nios2 )
+STARTUP(start.o)
+ENTRY(__reset)
+
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;
+ */
+
+SECTIONS
+{
+    .entry :
+    {
+        KEEP (*(.entry))
+    } > sram_reset
+
+    .exceptions :
+    {
+        . = ALIGN(0x20);
+        *(.irq)
+        KEEP (*(.exceptions));
+    } > sdram
+
+    .text :
+    {
+        /*
+         * All code sections are merged into the text output section, along with
+         * the read only data sections.
+         *
+         */
+
+        PROVIDE (stext = ABSOLUTE(.));
+
+        *(.interp)
+        *(.hash)
+        *(.dynsym)
+        *(.dynstr)
+        *(.gnu.version)
+        *(.gnu.version_d)
+        *(.gnu.version_r)
+        *(.rel.init)
+        *(.rela.init)
+        *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
+        *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+        *(.rel.fini)
+        *(.rela.fini)
+        *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
+        *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+        *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
+        *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+        *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
+        *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+        *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
+        *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+        *(.rel.ctors)
+        *(.rela.ctors)
+        *(.rel.dtors)
+        *(.rela.dtors)
+        *(.rel.got)
+        *(.rela.got)
+        *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)
+        *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
+        *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)
+        *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
+        *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)
+        *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
+        *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)
+        *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
+        *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
+        *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+        *(.rel.plt)
+        *(.rela.plt)
+
+        KEEP (*(.init))
+        *(.plt)
+        *(.text .stub .text.* .gnu.linkonce.t.*)
+
+        /* .gnu.warning sections are handled specially by elf32.em.  */
+
+        *(.gnu.warning.*)
+        KEEP (*(.fini))
+        PROVIDE (__etext = ABSOLUTE(.));
+        PROVIDE (_etext = ABSOLUTE(.));
+        PROVIDE (etext = ABSOLUTE(.));
+
+        *(.eh_frame_hdr)
+        /* Ensure the __preinit_array_start label is properly aligned.  We
+           could instead move the label definition inside the section, but
+           the linker would then create the section even if it turns out to
+           be empty, which isn't pretty.  */
+        . = ALIGN(32 / 8);
+        PROVIDE (__preinit_array_start = ABSOLUTE(.));
+        *(.preinit_array)
+        PROVIDE (__preinit_array_end = ABSOLUTE(.));
+        PROVIDE (__init_array_start = ABSOLUTE(.));
+        *(.init_array)
+        PROVIDE (__init_array_end = ABSOLUTE(.));
+        PROVIDE (__fini_array_start = ABSOLUTE(.));
+        *(.fini_array)
+        PROVIDE (__fini_array_end = ABSOLUTE(.));
+        SORT(CONSTRUCTORS)
+        KEEP (*(.eh_frame))
+        *(.gcc_except_table)
+        *(.dynamic)
+
+        /* gcc normally uses crtbegin.o to find the start of
+           the constructors instead nios2 use crtdotors.o,
+           so we make sure it is
+           first.  Because this is a wildcard, it
+           doesn't matter if the user does not
+           actually link against crtdotors.o; the
+           linker won't look for a file to match a
+           wildcard.  The wildcard also means that it
+           doesn't matter which directory crtdotors.o
+           is in.  */
+        KEEP (*crtdotors.o(.ctors))
+        /* We don't want to include the .ctor section from
+           from the crtendtors (gcc normally uses crtend.o)
+           file until after the sorted ctors.
+           The .ctor section from the crtendtors file contains the
+           end of ctors marker and it must be last */
+        KEEP (*(EXCLUDE_FILE (*crtendtors.o ) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*(.ctors))
+        KEEP (*crtdotors.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtendtors.o ) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*(.dtors))
+        KEEP (*(.jcr))
+    } > sdram =0x0001883a /* NOP on Nios2 */
+
+    .rodata :
+    {
+        . = ALIGN(32 / 8);
+        *(.rodata .rodata.* .gnu.linkonce.r.*)
+        *(.rodata1)
+    } > sdram
+
+    .rwdata :
+    {
+        . = ALIGN(32 / 8);
+        *(.got.plt) *(.got)
+        *(.data1)
+        *(.data .data.* .gnu.linkonce.d.*)
+
+        _gp = ABSOLUTE(. + 0x7ff0);
+        PROVIDE(gp = _gp);
+
+        *(.sdata .sdata.* .gnu.linkonce.s.*)
+        *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
+
+        . = ALIGN(32 / 8);
+        _edata = ABSOLUTE(.);
+        PROVIDE (edata = ABSOLUTE(.));
+    } > sdram
+
+    .bss :
+    {
+        __bss_start = ABSOLUTE(.);
+        PROVIDE (__sbss_start = ABSOLUTE(.));
+        PROVIDE (___sbss_start = ABSOLUTE(.));
+
+        *(.dynsbss)
+        *(.sbss .sbss.* .gnu.linkonce.sb.*)
+        *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)
+        *(.scommon)
+
+        PROVIDE (__sbss_end = ABSOLUTE(.));
+        PROVIDE (___sbss_end = ABSOLUTE(.));
+
+        *(.dynbss)
+        *(.bss .bss.* .gnu.linkonce.b.*)
+        *(COMMON)
+
+        . = ALIGN(32 / 8);
+        __bss_end = ABSOLUTE(.);
+    } > sdram
+
+    /*
+     * One output section for each of the available partitions. These are not
+     * used by default, but can be used by users applications using the .section
+     * directive.
+     *
+     * The memory partition used for the heap is treated in  special way, i.e. a
+     * symbol is added to point to the heap start.
+     *
+     */
+
+    .ext_flash :
+    {
+        PROVIDE (_alt_partition_ext_flash_start = ABSOLUTE(.));
+        *(.ext_flash)
+        . = ALIGN(32 / 8);
+        PROVIDE (_alt_partition_ext_flash_end = ABSOLUTE(.));
+    } > ext_flash
+
+    .sram :
+    {
+        PROVIDE (_alt_partition_sram_start = ABSOLUTE(.));
+        *(.sram)
+        . = ALIGN(32 / 8);
+        PROVIDE (_alt_partition_sram_end = ABSOLUTE(.));
+        _end = ABSOLUTE(.);
+        PROVIDE (end = ABSOLUTE(.));
+    } > sram
+
+    .sdram :
+    {
+        PROVIDE (_alt_partition_sdram_start = ABSOLUTE(.));
+        *(.sdram)
+        . = ALIGN(32 / 8);
+        PROVIDE (_alt_partition_sdram_end = ABSOLUTE(.));
+        _end = ABSOLUTE(.);
+        PROVIDE (end = ABSOLUTE(.));
+    } > sdram
+
+    .nlsdram (NOLOAD):
+    {
+        PROVIDE (_alt_partition_nlsdram_start = ABSOLUTE(.));
+        *(.nlsdram)
+        . = ALIGN(32 / 8);
+        PROVIDE (_alt_partition_nlsdram_end = ABSOLUTE(.));
+        _end = ABSOLUTE(.);
+        PROVIDE (end = ABSOLUTE(.));
+    } > sdram
+
+    /*
+     * Stabs debugging sections.
+     *
+     */
+
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+       Symbols in the DWARF debugging sections are relative to the beginning
+       of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
+/* provide a pointer for the stack */
+
+
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/nios2_dev_de2_115.ld
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/nios2_dev_de2_115.ld	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/nios2_dev_de2_115.ld	(revision 295)
@@ -0,0 +1,298 @@
+MEMORY
+{
+    sdram_UNUSED         : ORIGIN = 0x00000000, LENGTH = 0x00000020
+    sdram                : ORIGIN = 0x00000020, LENGTH = 0x02000000-0x20
+
+    ext_flash            : ORIGIN = 0x04000000, LENGTH = 0x01000000
+
+    sram_reset           : ORIGIN = 0x05000000, LENGTH = 0x00000020
+    sram                 : ORIGIN = 0x05000020, LENGTH = 0x00100000-0x20
+}
+
+/* Define symbols for each memory base-address */
+ __alt_mem_ext_flash = 0x00000000 ;
+ __alt_mem_ext_ram = 0x00800000 ;
+ __alt_mem_onchip_ram_64_kbytes = 0x00900000 ;
+ __alt_mem_sdram = 0x05000000 ;
+
+PROVIDE(hardware_init_hook = 0);
+PROVIDE(software_init_hook = 0);
+PROVIDE(software_term_hook = 0);
+PROVIDE( __alt_data_end = 0x02000000 );
+
+PROVIDE(StartupHook = 0);
+PROVIDE(ShutdownHook = 0);
+PROVIDE(PreTaskHook = 0);
+PROVIDE(PostTaskHook = 0);
+PROVIDE(ErrorHook = 0);
+PROVIDE(ProtectionHook = 0);
+
+OUTPUT_FORMAT( "elf32-littlenios2",
+               "elf32-littlenios2",
+               "elf32-littlenios2" )
+OUTPUT_ARCH( nios2 )
+STARTUP(start.o)
+ENTRY(__reset)
+
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;
+ */
+
+SECTIONS
+{
+    .entry :
+    {
+        KEEP (*(.entry))
+    } > sram_reset
+
+    .exceptions :
+    {
+        . = ALIGN(0x20);
+        *(.irq)
+        KEEP (*(.exceptions));
+    } > sdram
+
+    .text :
+    {
+        /*
+         * All code sections are merged into the text output section, along with
+         * the read only data sections.
+         *
+         */
+
+        PROVIDE (stext = ABSOLUTE(.));
+
+        *(.interp)
+        *(.hash)
+        *(.dynsym)
+        *(.dynstr)
+        *(.gnu.version)
+        *(.gnu.version_d)
+        *(.gnu.version_r)
+        *(.rel.init)
+        *(.rela.init)
+        *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
+        *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+        *(.rel.fini)
+        *(.rela.fini)
+        *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
+        *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+        *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
+        *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+        *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
+        *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+        *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
+        *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+        *(.rel.ctors)
+        *(.rela.ctors)
+        *(.rel.dtors)
+        *(.rela.dtors)
+        *(.rel.got)
+        *(.rela.got)
+        *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)
+        *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
+        *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)
+        *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
+        *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)
+        *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
+        *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)
+        *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
+        *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
+        *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+        *(.rel.plt)
+        *(.rela.plt)
+
+        KEEP (*(.init))
+        *(.plt)
+        *(.text .stub .text.* .gnu.linkonce.t.*)
+
+        /* .gnu.warning sections are handled specially by elf32.em.  */
+
+        *(.gnu.warning.*)
+        KEEP (*(.fini))
+        PROVIDE (__etext = ABSOLUTE(.));
+        PROVIDE (_etext = ABSOLUTE(.));
+        PROVIDE (etext = ABSOLUTE(.));
+
+        *(.eh_frame_hdr)
+        /* Ensure the __preinit_array_start label is properly aligned.  We
+           could instead move the label definition inside the section, but
+           the linker would then create the section even if it turns out to
+           be empty, which isn't pretty.  */
+        . = ALIGN(32 / 8);
+        PROVIDE (__preinit_array_start = ABSOLUTE(.));
+        *(.preinit_array)
+        PROVIDE (__preinit_array_end = ABSOLUTE(.));
+        PROVIDE (__init_array_start = ABSOLUTE(.));
+        *(.init_array)
+        PROVIDE (__init_array_end = ABSOLUTE(.));
+        PROVIDE (__fini_array_start = ABSOLUTE(.));
+        *(.fini_array)
+        PROVIDE (__fini_array_end = ABSOLUTE(.));
+        SORT(CONSTRUCTORS)
+        KEEP (*(.eh_frame))
+        *(.gcc_except_table)
+        *(.dynamic)
+
+        /* gcc normally uses crtbegin.o to find the start of
+           the constructors instead nios2 use crtdotors.o,
+           so we make sure it is
+           first.  Because this is a wildcard, it
+           doesn't matter if the user does not
+           actually link against crtdotors.o; the
+           linker won't look for a file to match a
+           wildcard.  The wildcard also means that it
+           doesn't matter which directory crtdotors.o
+           is in.  */
+        KEEP (*crtdotors.o(.ctors))
+        /* We don't want to include the .ctor section from
+           from the crtendtors (gcc normally uses crtend.o)
+           file until after the sorted ctors.
+           The .ctor section from the crtendtors file contains the
+           end of ctors marker and it must be last */
+        KEEP (*(EXCLUDE_FILE (*crtendtors.o ) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*(.ctors))
+        KEEP (*crtdotors.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtendtors.o ) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*(.dtors))
+        KEEP (*(.jcr))
+    } > sdram =0x0001883a /* NOP on Nios2 */
+
+    .rodata :
+    {
+        . = ALIGN(32 / 8);
+        *(.rodata .rodata.* .gnu.linkonce.r.*)
+        *(.rodata1)
+    } > sdram
+
+    .rwdata :
+    {
+        . = ALIGN(32 / 8);
+        *(.got.plt) *(.got)
+        *(.data1)
+        *(.data .data.* .gnu.linkonce.d.*)
+
+        _gp = ABSOLUTE(. + 0x7ff0);
+        PROVIDE(gp = _gp);
+
+        *(.sdata .sdata.* .gnu.linkonce.s.*)
+        *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
+
+        . = ALIGN(32 / 8);
+        _edata = ABSOLUTE(.);
+        PROVIDE (edata = ABSOLUTE(.));
+    } > sdram
+
+    .bss :
+    {
+        __bss_start = ABSOLUTE(.);
+        PROVIDE (__sbss_start = ABSOLUTE(.));
+        PROVIDE (___sbss_start = ABSOLUTE(.));
+
+        *(.dynsbss)
+        *(.sbss .sbss.* .gnu.linkonce.sb.*)
+        *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)
+        *(.scommon)
+
+        PROVIDE (__sbss_end = ABSOLUTE(.));
+        PROVIDE (___sbss_end = ABSOLUTE(.));
+
+        *(.dynbss)
+        *(.bss .bss.* .gnu.linkonce.b.*)
+        *(COMMON)
+
+        . = ALIGN(32 / 8);
+        __bss_end = ABSOLUTE(.);
+    } > sdram
+
+    /*
+     * One output section for each of the available partitions. These are not
+     * used by default, but can be used by users applications using the .section
+     * directive.
+     *
+     * The memory partition used for the heap is treated in  special way, i.e. a
+     * symbol is added to point to the heap start.
+     *
+     */
+
+    .ext_flash :
+    {
+        PROVIDE (_alt_partition_ext_flash_start = ABSOLUTE(.));
+        *(.ext_flash)
+        . = ALIGN(32 / 8);
+        PROVIDE (_alt_partition_ext_flash_end = ABSOLUTE(.));
+    } > ext_flash
+
+    .sram :
+    {
+        PROVIDE (_alt_partition_sram_start = ABSOLUTE(.));
+        *(.sram)
+        . = ALIGN(32 / 8);
+        PROVIDE (_alt_partition_sram_end = ABSOLUTE(.));
+        _end = ABSOLUTE(.);
+        PROVIDE (end = ABSOLUTE(.));
+    } > sram
+
+    .sdram :
+    {
+        PROVIDE (_alt_partition_sdram_start = ABSOLUTE(.));
+        *(.sdram)
+        . = ALIGN(32 / 8);
+        PROVIDE (_alt_partition_sdram_end = ABSOLUTE(.));
+        _end = ABSOLUTE(.);
+        PROVIDE (end = ABSOLUTE(.));
+    } > sdram
+
+    .nlsdram (NOLOAD):
+    {
+        PROVIDE (_alt_partition_nlsdram_start = ABSOLUTE(.));
+        *(.nlsdram)
+        . = ALIGN(32 / 8);
+        PROVIDE (_alt_partition_nlsdram_end = ABSOLUTE(.));
+        _end = ABSOLUTE(.);
+        PROVIDE (end = ABSOLUTE(.));
+    } > sdram
+
+    /*
+     * Stabs debugging sections.
+     *
+     */
+
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+       Symbols in the DWARF debugging sections are relative to the beginning
+       of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
+/* provide a pointer for the stack */
+
+
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/nios2_dev_de2_115_onchip.ld
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/nios2_dev_de2_115_onchip.ld	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/nios2_dev_de2_115_onchip.ld	(revision 295)
@@ -0,0 +1,299 @@
+MEMORY
+{
+    sdram_UNUSED         : ORIGIN = 0x00000000, LENGTH = 0x00000020
+    sdram                : ORIGIN = 0x00000020, LENGTH = 0x02000000-0x20
+
+    ext_flash            : ORIGIN = 0x04000000, LENGTH = 0x01000000
+
+    sram_reset           : ORIGIN = 0x05000000, LENGTH = 0x00000020
+    sram                 : ORIGIN = 0x05000020, LENGTH = 0x00100000-0x20
+	onchip_memory        : ORIGIN = 0xA000000, LENGTH = 0x0020000
+}
+
+/* Define symbols for each memory base-address */
+ __alt_mem_ext_flash = 0x00000000 ;
+ __alt_mem_ext_ram = 0x00800000 ;
+ __alt_mem_onchip_ram_64_kbytes = 0x00900000 ;
+ __alt_mem_sdram = 0x05000000 ;
+
+PROVIDE(hardware_init_hook = 0);
+PROVIDE(software_init_hook = 0);
+PROVIDE(software_term_hook = 0);
+PROVIDE( __alt_data_end = 0x02000000 );
+
+PROVIDE(StartupHook = 0);
+PROVIDE(ShutdownHook = 0);
+PROVIDE(PreTaskHook = 0);
+PROVIDE(PostTaskHook = 0);
+PROVIDE(ErrorHook = 0);
+PROVIDE(ProtectionHook = 0);
+
+OUTPUT_FORMAT( "elf32-littlenios2",
+               "elf32-littlenios2",
+               "elf32-littlenios2" )
+OUTPUT_ARCH( nios2 )
+STARTUP(start.o)
+ENTRY(__reset)
+
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;
+ */
+
+SECTIONS
+{
+    .entry :
+    {
+        KEEP (*(.entry))
+    } > sram_reset
+
+    .exceptions :
+    {
+        . = ALIGN(0x20);
+        *(.irq)
+        KEEP (*(.exceptions));
+    } > sdram
+
+    .text :
+    {
+        /*
+         * All code sections are merged into the text output section, along with
+         * the read only data sections.
+         *
+         */
+
+        PROVIDE (stext = ABSOLUTE(.));
+
+        *(.interp)
+        *(.hash)
+        *(.dynsym)
+        *(.dynstr)
+        *(.gnu.version)
+        *(.gnu.version_d)
+        *(.gnu.version_r)
+        *(.rel.init)
+        *(.rela.init)
+        *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
+        *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+        *(.rel.fini)
+        *(.rela.fini)
+        *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
+        *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+        *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
+        *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+        *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
+        *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+        *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
+        *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+        *(.rel.ctors)
+        *(.rela.ctors)
+        *(.rel.dtors)
+        *(.rela.dtors)
+        *(.rel.got)
+        *(.rela.got)
+        *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)
+        *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
+        *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)
+        *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
+        *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)
+        *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
+        *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)
+        *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
+        *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
+        *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+        *(.rel.plt)
+        *(.rela.plt)
+
+        KEEP (*(.init))
+        *(.plt)
+        *(.text .stub .text.* .gnu.linkonce.t.*)
+
+        /* .gnu.warning sections are handled specially by elf32.em.  */
+
+        *(.gnu.warning.*)
+        KEEP (*(.fini))
+        PROVIDE (__etext = ABSOLUTE(.));
+        PROVIDE (_etext = ABSOLUTE(.));
+        PROVIDE (etext = ABSOLUTE(.));
+
+        *(.eh_frame_hdr)
+        /* Ensure the __preinit_array_start label is properly aligned.  We
+           could instead move the label definition inside the section, but
+           the linker would then create the section even if it turns out to
+           be empty, which isn't pretty.  */
+        . = ALIGN(32 / 8);
+        PROVIDE (__preinit_array_start = ABSOLUTE(.));
+        *(.preinit_array)
+        PROVIDE (__preinit_array_end = ABSOLUTE(.));
+        PROVIDE (__init_array_start = ABSOLUTE(.));
+        *(.init_array)
+        PROVIDE (__init_array_end = ABSOLUTE(.));
+        PROVIDE (__fini_array_start = ABSOLUTE(.));
+        *(.fini_array)
+        PROVIDE (__fini_array_end = ABSOLUTE(.));
+        SORT(CONSTRUCTORS)
+        KEEP (*(.eh_frame))
+        *(.gcc_except_table)
+        *(.dynamic)
+
+        /* gcc normally uses crtbegin.o to find the start of
+           the constructors instead nios2 use crtdotors.o,
+           so we make sure it is
+           first.  Because this is a wildcard, it
+           doesn't matter if the user does not
+           actually link against crtdotors.o; the
+           linker won't look for a file to match a
+           wildcard.  The wildcard also means that it
+           doesn't matter which directory crtdotors.o
+           is in.  */
+        KEEP (*crtdotors.o(.ctors))
+        /* We don't want to include the .ctor section from
+           from the crtendtors (gcc normally uses crtend.o)
+           file until after the sorted ctors.
+           The .ctor section from the crtendtors file contains the
+           end of ctors marker and it must be last */
+        KEEP (*(EXCLUDE_FILE (*crtendtors.o ) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*(.ctors))
+        KEEP (*crtdotors.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtendtors.o ) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*(.dtors))
+        KEEP (*(.jcr))
+    } > onchip_memory =0x0001883a /* NOP on Nios2 */
+
+    .rodata :
+    {
+        . = ALIGN(32 / 8);
+        *(.rodata .rodata.* .gnu.linkonce.r.*)
+        *(.rodata1)
+    } > onchip_memory
+
+    .rwdata :
+    {
+        . = ALIGN(32 / 8);
+        *(.got.plt) *(.got)
+        *(.data1)
+        *(.data .data.* .gnu.linkonce.d.*)
+
+        _gp = ABSOLUTE(. + 0x7ff0);
+        PROVIDE(gp = _gp);
+
+        *(.sdata .sdata.* .gnu.linkonce.s.*)
+        *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
+
+        . = ALIGN(32 / 8);
+        _edata = ABSOLUTE(.);
+        PROVIDE (edata = ABSOLUTE(.));
+    } > onchip_memory
+
+    .bss :
+    {
+        __bss_start = ABSOLUTE(.);
+        PROVIDE (__sbss_start = ABSOLUTE(.));
+        PROVIDE (___sbss_start = ABSOLUTE(.));
+
+        *(.dynsbss)
+        *(.sbss .sbss.* .gnu.linkonce.sb.*)
+        *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)
+        *(.scommon)
+
+        PROVIDE (__sbss_end = ABSOLUTE(.));
+        PROVIDE (___sbss_end = ABSOLUTE(.));
+
+        *(.dynbss)
+        *(.bss .bss.* .gnu.linkonce.b.*)
+        *(COMMON)
+
+        . = ALIGN(32 / 8);
+        __bss_end = ABSOLUTE(.);
+    } > onchip_memory
+
+    /*
+     * One output section for each of the available partitions. These are not
+     * used by default, but can be used by users applications using the .section
+     * directive.
+     *
+     * The memory partition used for the heap is treated in  special way, i.e. a
+     * symbol is added to point to the heap start.
+     *
+     */
+
+    .ext_flash :
+    {
+        PROVIDE (_alt_partition_ext_flash_start = ABSOLUTE(.));
+        *(.ext_flash)
+        . = ALIGN(32 / 8);
+        PROVIDE (_alt_partition_ext_flash_end = ABSOLUTE(.));
+    } > ext_flash
+
+    .sram :
+    {
+        PROVIDE (_alt_partition_sram_start = ABSOLUTE(.));
+        *(.sram)
+        . = ALIGN(32 / 8);
+        PROVIDE (_alt_partition_sram_end = ABSOLUTE(.));
+        _end = ABSOLUTE(.);
+        PROVIDE (end = ABSOLUTE(.));
+    } > sram
+
+    .onchip_memory :
+    {
+        PROVIDE (_alt_partition_onchip_memory_start = ABSOLUTE(.));
+        *(.onchip_memory)
+        . = ALIGN(32 / 8);
+        PROVIDE (_alt_partition_onchip_memory_end = ABSOLUTE(.));
+        _end = ABSOLUTE(.);
+        PROVIDE (end = ABSOLUTE(.));
+    } > onchip_memory
+
+    .nlonchip_memory (NOLOAD):
+    {
+        PROVIDE (_alt_partition_nlonchip_memory_start = ABSOLUTE(.));
+        *(.nlonchip_memory)
+        . = ALIGN(32 / 8);
+        PROVIDE (_alt_partition_nlonchip_memory_end = ABSOLUTE(.));
+        _end = ABSOLUTE(.);
+        PROVIDE (end = ABSOLUTE(.));
+    } > onchip_memory
+
+    /*
+     * Stabs debugging sections.
+     *
+     */
+
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+       Symbols in the DWARF debugging sections are relative to the beginning
+       of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
+/* provide a pointer for the stack */
+
+
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/nios2_system.h
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/nios2_system.h	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/nios2_system.h	(revision 295)
@@ -0,0 +1,250 @@
+/*
+ *  TOPPERS ATK2
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *      Automotive Kernel Version 2
+ *
+ *  Copyright (C) 2011-2015 by Center for Embedded Computing Systems
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2011-2015 by FUJI SOFT INCORPORATED, JAPAN
+ *  Copyright (C) 2011-2013 by Spansion LLC, USA
+ *  Copyright (C) 2011-2015 by NEC Communication Systems, Ltd., JAPAN
+ *  Copyright (C) 2011-2015 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
+ *  Copyright (C) 2011-2014 by Renesas Electronics Corporation, JAPAN
+ *  Copyright (C) 2011-2015 by Sunny Giken Inc., JAPAN
+ *  Copyright (C) 2011-2015 by TOSHIBA CORPORATION, JAPAN
+ *  Copyright (C) 2011-2015 by Witz Corporation
+ *  Copyright (C) 2014-2015 by AISIN COMCRUISE Co., Ltd., JAPAN
+ *  Copyright (C) 2014-2015 by eSOL Co.,Ltd., JAPAN
+ *  Copyright (C) 2014-2015 by SCSK Corporation, JAPAN
+ *
+ *  上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
+ *  ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
+ *  変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
+ *  (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
+ *      権表示，この利用条件および下記の無保証規定が，そのままの形でソー
+ *      スコード中に含まれていること．
+ *  (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
+ *      用できる形で再配布する場合には，再配布に伴うドキュメント（利用
+ *      者マニュアルなど）に，上記の著作権表示，この利用条件および下記
+ *      の無保証規定を掲載すること．
+ *  (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
+ *      用できない形で再配布する場合には，次のいずれかの条件を満たすこ
+ *      と．
+ *    (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
+ *        作権表示，この利用条件および下記の無保証規定を掲載すること．
+ *    (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
+ *        報告すること．
+ *  (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
+ *      害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
+ *      また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
+ *      由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
+ *      免責すること．
+ *
+ *  本ソフトウェアは，AUTOSAR（AUTomotive Open System ARchitecture）仕
+ *  様に基づいている．上記の許諾は，AUTOSARの知的財産権を許諾するもので
+ *  はない．AUTOSARは，AUTOSAR仕様に基づいたソフトウェアを商用目的で利
+ *  用する者に対して，AUTOSARパートナーになることを求めている．
+ *
+ *  本ソフトウェアは，無保証で提供されているものである．上記著作権者お
+ *  よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
+ *  に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
+ *  アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
+ *  の責任を負わない．
+ *
+ *  $Id: nios2_system.h 1801 2015-03-27 06:34:43Z t_ishikawa $
+ */
+
+/*
+ *		Nios2システムの定義
+ *
+ *  ペリフェラルのアドレスや割込み番号を定義する
+ */
+
+#ifndef TOPPERS_NIOS2_SYSTEM_H
+#define TOPPERS_NIOS2_SYSTEM_H
+
+#ifdef TOPPERS_NIOS2_DEV_2S180
+
+/*
+ *  NIOS2_DEV_2S180 用の定義
+ */
+
+/*
+ *  起動メッセージのターゲットシステム名
+ */
+#define TARGET_NAME	"NIOS2_DEV_2S180(NIOS2)"
+
+/*
+ *  タイマ値の内部表現とミリ秒単位との変換
+ */
+#define TIMER_CLOCK		UINT_C(50000)
+
+/*
+ *  キャッシュサイズ
+ */
+#define NIOS2_ICACHE_SIZE			UINT_C(0x1000)   /* 4Kbyte */
+#define NIOS2_ICACHE_LINE_SIZE		UINT_C(32)
+#define NIOS2_DCACHE_SIZE			UINT_C(0)
+#define NIOS2_DCACHE_LINE_SIZE		UINT_C(0)
+
+/*
+ *  Interval Timer
+ */
+#define SYS_CLK_TIMER_BASE	UINT_C(0x01001000)
+#define SYS_CLK_TIMER_INT	UINT_C(0)
+
+/*
+ *  JTAG UART
+ */
+#define JTAG_UART_PORT1_BASE	UINT_C(0x010008a0)
+#define JTAG_UART_PORT1_INT		UINT_C(1)
+
+/*
+ *  システムバージョンレジスタのベースアドレス
+ */
+#define SYSVER_BASE				UINT_C(0x0f000000)
+
+/*
+ *  システムバージョン参照値
+ */
+#define TNUM_HWCORE				UINT_C(1)           /* コア数 */
+#define MAJOR_VAR				UINT_C(5)           /* メジャーバージョン */
+
+/*
+ *  ベクタ割込みコントローラ
+ */
+#define VIC_BASE				UINT_C(0x01000c00)  /* ベースアドレス */
+#define VIC_INT_NUM				UINT_C(32)
+
+#elif defined(TOPPERS_NIOS2_DEV_DE2_115)
+
+/*
+ *  NIOS2_DEV_DE2_115 用の定義
+ */
+
+/*
+ *  起動メッセージのターゲットシステム名
+ */
+#define TARGET_NAME	"NIOS2_DEV_DE2_115(NIOS2)"
+
+/*
+ *  タイマ値の内部表現とミリ秒単位との変換
+ */
+#define TIMER_CLOCK		UINT_C(60000)
+
+/*
+ *  キャッシュサイズ
+ */
+#define NIOS2_ICACHE_SIZE			UINT_C(0x1000)   /* 4Kbyte */
+#define NIOS2_ICACHE_LINE_SIZE		UINT_C(32)
+#define NIOS2_DCACHE_SIZE			UINT_C(0)
+#define NIOS2_DCACHE_LINE_SIZE		UINT_C(0)
+
+/*
+ *  Interval Timer
+ */
+#define SYS_CLK_TIMER_BASE	UINT_C(0x08000160)
+#define SYS_CLK_TIMER_INT	UINT_C(0)
+
+/*
+ *  JTAG UART
+ */
+#define JTAG_UART_PORT1_BASE	UINT_C(0x080001a0)
+#define JTAG_UART_PORT1_INT		UINT_C(1)
+
+/*
+ *  UART
+ */
+#define UART_PORT1_BASE	UINT_C(0x02000d00)
+#define UART_PORT1_INT	UINT_C(3)
+
+/*
+ *  システムバージョンレジスタのベースアドレス
+ */
+#define SYSVER_BASE				UINT_C(0x080001c0)
+
+/*
+ *  システムバージョン参照値
+ */
+#define TNUM_HWCORE				UINT_C(1)           /* コア数 */
+#define MAJOR_VAR				UINT_C(7)           /* メジャーバージョン */
+
+/*
+ *  ベクタ割込みコントローラ
+ */
+#define VIC_BASE				UINT_C(0x0f000000)  /* ベースアドレス */
+#define VIC_INT_NUM				UINT_C(32)
+
+#elif defined(TOPPERS_NIOS2_DEV_DE0_NANO)
+
+/*
+ *  NIOS2_DEV_DE2_115 用の定義
+ */
+
+/*
+ *  起動メッセージのターゲットシステム名
+ */
+#define TARGET_NAME	"NIOS2_DEV_DE0_NANO(NIOS2)"
+
+/*
+ *  タイマ値の内部表現とミリ秒単位との変換
+ */
+#define TIMER_CLOCK		UINT_C(60000)
+
+/*
+ *  キャッシュサイズ
+ */
+#define NIOS2_ICACHE_SIZE			UINT_C(0x1000)   /* 4Kbyte */
+#define NIOS2_ICACHE_LINE_SIZE		UINT_C(32)
+#define NIOS2_DCACHE_SIZE			UINT_C(0)
+#define NIOS2_DCACHE_LINE_SIZE		UINT_C(0)
+
+/*
+ *  Interval Timer
+ */
+#define SYS_CLK_TIMER_BASE	UINT_C(0x08000160)
+#define SYS_CLK_TIMER_INT	UINT_C(0)
+
+/*
+ *  JTAG UART
+ */
+#define JTAG_UART_PORT1_BASE	UINT_C(0x080001a0)
+#define JTAG_UART_PORT1_INT		UINT_C(1)
+
+/*
+ *  UART
+ *  0x02000d00 = TTL level
+ *  0x02000d40 = RS232C level
+ */
+#define UART_PORT1_BASE	UINT_C(0x02000d00)
+#define UART_PORT1_INT	UINT_C(6)
+//#define UART_PORT1_BASE	UINT_C(0x02000d40)
+//#define UART_PORT1_INT	UINT_C(7)
+
+/*
+ *  システムバージョンレジスタのベースアドレス
+ */
+#define SYSVER_BASE				UINT_C(0x080001c0)
+
+/*
+ *  システムバージョン参照値
+ */
+#define TNUM_HWCORE				UINT_C(1)           /* コア数 */
+#define MAJOR_VAR				UINT_C(7)           /* メジャーバージョン */
+
+/*
+ *  ベクタ割込みコントローラ
+ */
+#define VIC_BASE				UINT_C(0x0f000000)  /* ベースアドレス */
+#define VIC_INT_NUM				UINT_C(32)
+
+#endif /* TOPPERS_NIOS2_DEV_DE0_NANO */
+
+/*
+ *  システムバージョンレジスタ(sysver)
+ */
+#define SYSVER_MAJOR_VAR	(SYSVER_BASE + 0x00U)
+#define SYSVER_MINOR_VAR	(SYSVER_BASE + 0x04U)
+#define SYSVER_NUM_CORE		(SYSVER_BASE + 0x08U)
+
+#endif /* TOPPERS_NIOS2_SYSTEM_H */
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target.tf
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target.tf	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target.tf	(revision 295)
@@ -0,0 +1,64 @@
+$
+$  TOPPERS ATK2
+$      Toyohashi Open Platform for Embedded Real-Time Systems
+$      Automotive Kernel Version 2
+$
+$  Copyright (C) 2011-2015 by Center for Embedded Computing Systems
+$              Graduate School of Information Science, Nagoya Univ., JAPAN
+$  Copyright (C) 2011-2015 by FUJI SOFT INCORPORATED, JAPAN
+$  Copyright (C) 2011-2013 by Spansion LLC, USA
+$  Copyright (C) 2011-2015 by NEC Communication Systems, Ltd., JAPAN
+$  Copyright (C) 2011-2015 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
+$  Copyright (C) 2011-2014 by Renesas Electronics Corporation, JAPAN
+$  Copyright (C) 2011-2015 by Sunny Giken Inc., JAPAN
+$  Copyright (C) 2011-2015 by TOSHIBA CORPORATION, JAPAN
+$  Copyright (C) 2011-2015 by Witz Corporation
+$  Copyright (C) 2014-2015 by AISIN COMCRUISE Co., Ltd., JAPAN
+$  Copyright (C) 2014-2015 by eSOL Co.,Ltd., JAPAN
+$  Copyright (C) 2014-2015 by SCSK Corporation, JAPAN
+$
+$  上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
+$  ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
+$  変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
+$  (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
+$      権表示，この利用条件および下記の無保証規定が，そのままの形でソー
+$      スコード中に含まれていること．
+$  (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
+$      用できる形で再配布する場合には，再配布に伴うドキュメント（利用
+$      者マニュアルなど）に，上記の著作権表示，この利用条件および下記
+$      の無保証規定を掲載すること．
+$  (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
+$      用できない形で再配布する場合には，次のいずれかの条件を満たすこ
+$      と．
+$    (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
+$        作権表示，この利用条件および下記の無保証規定を掲載すること．
+$    (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
+$        報告すること．
+$  (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
+$      害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
+$      また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
+$      由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
+$      免責すること．
+$
+$  本ソフトウェアは，AUTOSAR（AUTomotive Open System ARchitecture）仕
+$  様に基づいている．上記の許諾は，AUTOSARの知的財産権を許諾するもので
+$  はない．AUTOSARは，AUTOSAR仕様に基づいたソフトウェアを商用目的で利
+$  用する者に対して，AUTOSARパートナーになることを求めている．
+$
+$  本ソフトウェアは，無保証で提供されているものである．上記著作権者お
+$  よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
+$  に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
+$  アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
+$  の責任を負わない．
+$
+$  $Id: target.tf 1801 2015-03-27 06:34:43Z t_ishikawa $
+$
+
+$
+$     パス2のターゲット依存テンプレート（NIOS2_DEV用）
+$
+
+$
+$  プロセッサ依存テンプレートのインクルード
+$
+$INCLUDE "nios2_gcc/prc.tf"$
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_cfg1_out.h
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_cfg1_out.h	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_cfg1_out.h	(revision 295)
@@ -0,0 +1,68 @@
+/*
+ *  TOPPERS ATK2
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *      Automotive Kernel Version 2
+ *
+ *  Copyright (C) 2011-2015 by Center for Embedded Computing Systems
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2011-2015 by FUJI SOFT INCORPORATED, JAPAN
+ *  Copyright (C) 2011-2013 by Spansion LLC, USA
+ *  Copyright (C) 2011-2015 by NEC Communication Systems, Ltd., JAPAN
+ *  Copyright (C) 2011-2015 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
+ *  Copyright (C) 2011-2014 by Renesas Electronics Corporation, JAPAN
+ *  Copyright (C) 2011-2015 by Sunny Giken Inc., JAPAN
+ *  Copyright (C) 2011-2015 by TOSHIBA CORPORATION, JAPAN
+ *  Copyright (C) 2011-2015 by Witz Corporation
+ *  Copyright (C) 2014-2015 by AISIN COMCRUISE Co., Ltd., JAPAN
+ *  Copyright (C) 2014-2015 by eSOL Co.,Ltd., JAPAN
+ *  Copyright (C) 2014-2015 by SCSK Corporation, JAPAN
+ *
+ *  上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
+ *  ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
+ *  変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
+ *  (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
+ *      権表示，この利用条件および下記の無保証規定が，そのままの形でソー
+ *      スコード中に含まれていること．
+ *  (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
+ *      用できる形で再配布する場合には，再配布に伴うドキュメント（利用
+ *      者マニュアルなど）に，上記の著作権表示，この利用条件および下記
+ *      の無保証規定を掲載すること．
+ *  (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
+ *      用できない形で再配布する場合には，次のいずれかの条件を満たすこ
+ *      と．
+ *    (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
+ *        作権表示，この利用条件および下記の無保証規定を掲載すること．
+ *    (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
+ *        報告すること．
+ *  (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
+ *      害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
+ *      また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
+ *      由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
+ *      免責すること．
+ *
+ *  本ソフトウェアは，AUTOSAR（AUTomotive Open System ARchitecture）仕
+ *  様に基づいている．上記の許諾は，AUTOSARの知的財産権を許諾するもので
+ *  はない．AUTOSARは，AUTOSAR仕様に基づいたソフトウェアを商用目的で利
+ *  用する者に対して，AUTOSARパートナーになることを求めている．
+ *
+ *  本ソフトウェアは，無保証で提供されているものである．上記著作権者お
+ *  よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
+ *  に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
+ *  アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
+ *  の責任を負わない．
+ *
+ *  $Id: target_cfg1_out.h 1801 2015-03-27 06:34:43Z t_ishikawa $
+ */
+
+/*
+ *		cfg1_out.cをリンクするために必要なスタブの定義
+ */
+
+/*
+ *  コア依存のスタブの定義
+ */
+#include "nios2_gcc/prc_cfg1_out.h"
+void
+target_hardware_initialize(void)
+{
+}
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_check.tf
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_check.tf	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_check.tf	(revision 295)
@@ -0,0 +1,64 @@
+$
+$  TOPPERS ATK2
+$      Toyohashi Open Platform for Embedded Real-Time Systems
+$      Automotive Kernel Version 2
+$
+$  Copyright (C) 2011-2015 by Center for Embedded Computing Systems
+$              Graduate School of Information Science, Nagoya Univ., JAPAN
+$  Copyright (C) 2011-2015 by FUJI SOFT INCORPORATED, JAPAN
+$  Copyright (C) 2011-2013 by Spansion LLC, USA
+$  Copyright (C) 2011-2015 by NEC Communication Systems, Ltd., JAPAN
+$  Copyright (C) 2011-2015 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
+$  Copyright (C) 2011-2014 by Renesas Electronics Corporation, JAPAN
+$  Copyright (C) 2011-2015 by Sunny Giken Inc., JAPAN
+$  Copyright (C) 2011-2015 by TOSHIBA CORPORATION, JAPAN
+$  Copyright (C) 2011-2015 by Witz Corporation
+$  Copyright (C) 2014-2015 by AISIN COMCRUISE Co., Ltd., JAPAN
+$  Copyright (C) 2014-2015 by eSOL Co.,Ltd., JAPAN
+$  Copyright (C) 2014-2015 by SCSK Corporation, JAPAN
+$
+$  上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
+$  ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
+$  変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
+$  (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
+$      権表示，この利用条件および下記の無保証規定が，そのままの形でソー
+$      スコード中に含まれていること．
+$  (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
+$      用できる形で再配布する場合には，再配布に伴うドキュメント（利用
+$      者マニュアルなど）に，上記の著作権表示，この利用条件および下記
+$      の無保証規定を掲載すること．
+$  (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
+$      用できない形で再配布する場合には，次のいずれかの条件を満たすこ
+$      と．
+$    (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
+$        作権表示，この利用条件および下記の無保証規定を掲載すること．
+$    (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
+$        報告すること．
+$  (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
+$      害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
+$      また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
+$      由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
+$      免責すること．
+$
+$  本ソフトウェアは，AUTOSAR（AUTomotive Open System ARchitecture）仕
+$  様に基づいている．上記の許諾は，AUTOSARの知的財産権を許諾するもので
+$  はない．AUTOSARは，AUTOSAR仕様に基づいたソフトウェアを商用目的で利
+$  用する者に対して，AUTOSARパートナーになることを求めている．
+$
+$  本ソフトウェアは，無保証で提供されているものである．上記著作権者お
+$  よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
+$  に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
+$  アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
+$  の責任を負わない．
+$
+$  $Id: target_check.tf 1801 2015-03-27 06:34:43Z t_ishikawa $
+$
+
+$
+$     パス3のターゲット依存テンプレート（NIOS2_DEV用）
+$
+
+$
+$  コア依存のテンプレートのインクルード
+$
+$INCLUDE "nios2_gcc/prc_check.tf"$
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_config.c
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_config.c	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_config.c	(revision 295)
@@ -0,0 +1,219 @@
+/*
+ *  TOPPERS ATK2
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *      Automotive Kernel Version 2
+ *
+ *  Copyright (C) 2008-2015 by Center for Embedded Computing Systems
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2011-2015 by FUJI SOFT INCORPORATED, JAPAN
+ *  Copyright (C) 2011-2013 by Spansion LLC, USA
+ *  Copyright (C) 2011-2015 by NEC Communication Systems, Ltd., JAPAN
+ *  Copyright (C) 2011-2015 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
+ *  Copyright (C) 2011-2014 by Renesas Electronics Corporation, JAPAN
+ *  Copyright (C) 2011-2015 by Sunny Giken Inc., JAPAN
+ *  Copyright (C) 2011-2015 by TOSHIBA CORPORATION, JAPAN
+ *  Copyright (C) 2011-2015 by Witz Corporation
+ *  Copyright (C) 2014-2015 by AISIN COMCRUISE Co., Ltd., JAPAN
+ *  Copyright (C) 2014-2015 by eSOL Co.,Ltd., JAPAN
+ *  Copyright (C) 2014-2015 by SCSK Corporation, JAPAN
+ *
+ *  上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
+ *  ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
+ *  変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
+ *  (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
+ *      権表示，この利用条件および下記の無保証規定が，そのままの形でソー
+ *      スコード中に含まれていること．
+ *  (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
+ *      用できる形で再配布する場合には，再配布に伴うドキュメント（利用
+ *      者マニュアルなど）に，上記の著作権表示，この利用条件および下記
+ *      の無保証規定を掲載すること．
+ *  (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
+ *      用できない形で再配布する場合には，次のいずれかの条件を満たすこ
+ *      と．
+ *    (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
+ *        作権表示，この利用条件および下記の無保証規定を掲載すること．
+ *    (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
+ *        報告すること．
+ *  (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
+ *      害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
+ *      また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
+ *      由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
+ *      免責すること．
+ *
+ *  本ソフトウェアは，AUTOSAR（AUTomotive Open System ARchitecture）仕
+ *  様に基づいている．上記の許諾は，AUTOSARの知的財産権を許諾するもので
+ *  はない．AUTOSARは，AUTOSAR仕様に基づいたソフトウェアを商用目的で利
+ *  用する者に対して，AUTOSARパートナーになることを求めている．
+ *
+ *  本ソフトウェアは，無保証で提供されているものである．上記著作権者お
+ *  よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
+ *  に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
+ *  アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
+ *  の責任を負わない．
+ *
+ *  $Id: target_config.c 1801 2015-03-27 06:34:43Z t_ishikawa $
+ */
+
+/*
+ *		ターゲット依存モジュール（NIOS2_DEV用）
+ */
+
+#include "kernel_impl.h"
+#include "nios2_gcc/prc_sil.h"
+#include "target_sysmod.h"
+#ifdef ENABLE_RETURN_MAIN
+#include "interrupt.h"
+#endif /* ENABLE_RETURN_MAIN */
+#ifdef TOPPERS_ENABLE_TRACE
+#include "logtrace/trace_config.h"
+#endif /* TOPPERS_ENABLE_TRACE */
+
+#ifdef USE_UART
+#include "nios2_gcc/uart.h"
+#else /* USE_UART */
+#include "nios2_gcc/jtag_uart.h"
+#endif /* USE_UART */
+
+/* 内部関数のプロトタイプ宣言 */
+static void hw_version_check(void);
+
+LOCAL_INLINE void
+nios2_dev_putc_rom(char8 c)
+{
+#ifndef RC_ROM_BOOT
+	while ((sil_rew_iop((void *) (JTAG_UART_PORT1_BASE + JTAG_UART_CONTROL_OFFSET)) & JTAG_UART_CONTROL_WSAPCE) == 0U) {
+		/* 実行すべき処理がない */
+	}
+	sil_wrw_iop((void *) (JTAG_UART_PORT1_BASE + JTAG_UART_DATA_OFFSET), (uint32) c);
+#else /* RC_ROM_BOOT */
+	volatile int cnt = 0;
+	static boolean enable = TRUE;
+	if (enable == TRUE) {
+		while ((sil_rew_iop((void *) (JTAG_UART_PORT1_BASE + JTAG_UART_CONTROL_OFFSET)) & JTAG_UART_CONTROL_WSAPCE) == 0U) {
+			/* 実行すべき処理がない */
+			if(cnt++ == 2000000){
+				enable = FALSE;
+				break;
+			}
+		}
+		sil_wrw_iop((void *) (JTAG_UART_PORT1_BASE + JTAG_UART_DATA_OFFSET), (uint32) c);
+	}
+#endif /* RC_ROM_BOOT */
+}
+
+
+/*
+ *  文字列の出力
+ */
+void
+target_fput_str(const char8 *c)
+{
+	while (*c != '\0') {
+		nios2_dev_putc_rom(*c);
+		c++;
+	}
+	nios2_dev_putc_rom('\n');
+}
+
+/*
+ *  バージョンチェック
+ */
+static void
+hw_version_check(void)
+{
+	/* コア数を確認 */
+	if (sil_rew_iop((void *) (SYSVER_NUM_CORE)) != TNUM_HWCORE) {
+		target_fput_str("Number of core is mismatch!!");
+		while (1) {
+		}
+	}
+
+	if (sil_rew_iop((void *) (SYSVER_MAJOR_VAR)) != MAJOR_VAR) {
+		target_fput_str("Hardware Major version is mismatch!!");
+		while (1) {
+		}
+	}
+}
+void
+target_hardware_initialize(void)
+{
+	/*
+	 *  ハードウェアバージョンの確認
+	 */
+	hw_version_check();
+
+	prc_hardware_initialize();
+}
+
+/*
+ *  ターゲット依存の初期化
+ */
+void
+target_initialize(void)
+{
+	/*
+	 *  Nios2依存の初期化
+	 */
+	prc_initialize();
+
+#ifdef TOPPERS_ENABLE_TRACE
+	/*
+	 *  トレースログ機能の初期化
+	 */
+	trace_initialize((uintptr) (TRACE_AUTOSTOP));
+#endif /* TOPPERS_ENABLE_TRACE */
+}
+
+/*
+ *  ターゲット依存の終了処理
+ */
+void
+target_exit(void)
+{
+#ifdef TOPPERS_ENABLE_TRACE
+	/*
+	 *  トレースログのダンプ
+	 */
+	trace_dump(&target_fput_log);
+#endif /* TOPPERS_ENABLE_TRACE */
+
+#ifndef ENABLE_RETURN_MAIN
+	/*
+	 *  シャットダウン処理の出力
+	 */
+	target_fput_str("Kernel Exit...");
+#else
+	target_fput_str("Kernel Shutdown...");
+#endif /* ENABLE_RETURN_MAIN */
+
+	/*
+	 *  Nios2依存の終了処理
+	 */
+	prc_terminate();
+
+#ifdef ENABLE_RETURN_MAIN
+	kerflg = FALSE;
+	except_nest_cnt = 0U;
+	nested_lock_os_int_cnt = 0U;
+	sus_all_cnt = 0U;
+	sus_all_cnt_ctx = 0U;
+	sus_os_cnt = 0U;
+	sus_os_cnt_ctx = 0U;
+
+	Asm("movia r2, _ostkpt");
+	Asm("ldw   sp, 0(r2)");
+	Asm("call  main");
+#endif /* ENABLE_RETURN_MAIN */
+
+	while (1) {
+	}
+}
+
+/*
+ *  ターゲット依存の文字出力
+ */
+void
+target_fput_log(char8 c)
+{
+	nios2_dev_putc_rom(c);
+}
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_config.h
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_config.h	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_config.h	(revision 295)
@@ -0,0 +1,103 @@
+/*
+ *  TOPPERS ATK2
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *      Automotive Kernel Version 2
+ *
+ *  Copyright (C) 2008-2015 by Center for Embedded Computing Systems
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2011-2015 by FUJI SOFT INCORPORATED, JAPAN
+ *  Copyright (C) 2011-2013 by Spansion LLC, USA
+ *  Copyright (C) 2011-2015 by NEC Communication Systems, Ltd., JAPAN
+ *  Copyright (C) 2011-2015 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
+ *  Copyright (C) 2011-2014 by Renesas Electronics Corporation, JAPAN
+ *  Copyright (C) 2011-2015 by Sunny Giken Inc., JAPAN
+ *  Copyright (C) 2011-2015 by TOSHIBA CORPORATION, JAPAN
+ *  Copyright (C) 2011-2015 by Witz Corporation
+ *  Copyright (C) 2014-2015 by AISIN COMCRUISE Co., Ltd., JAPAN
+ *  Copyright (C) 2014-2015 by eSOL Co.,Ltd., JAPAN
+ *  Copyright (C) 2014-2015 by SCSK Corporation, JAPAN
+ *
+ *  上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
+ *  ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
+ *  変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
+ *  (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
+ *      権表示，この利用条件および下記の無保証規定が，そのままの形でソー
+ *      スコード中に含まれていること．
+ *  (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
+ *      用できる形で再配布する場合には，再配布に伴うドキュメント（利用
+ *      者マニュアルなど）に，上記の著作権表示，この利用条件および下記
+ *      の無保証規定を掲載すること．
+ *  (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
+ *      用できない形で再配布する場合には，次のいずれかの条件を満たすこ
+ *      と．
+ *    (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
+ *        作権表示，この利用条件および下記の無保証規定を掲載すること．
+ *    (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
+ *        報告すること．
+ *  (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
+ *      害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
+ *      また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
+ *      由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
+ *      免責すること．
+ *
+ *  本ソフトウェアは，AUTOSAR（AUTomotive Open System ARchitecture）仕
+ *  様に基づいている．上記の許諾は，AUTOSARの知的財産権を許諾するもので
+ *  はない．AUTOSARは，AUTOSAR仕様に基づいたソフトウェアを商用目的で利
+ *  用する者に対して，AUTOSARパートナーになることを求めている．
+ *
+ *  本ソフトウェアは，無保証で提供されているものである．上記著作権者お
+ *  よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
+ *  に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
+ *  アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
+ *  の責任を負わない．
+ *
+ *  $Id: target_config.h 1801 2015-03-27 06:34:43Z t_ishikawa $
+ */
+
+/*
+ *		ターゲット依存モジュール（NIOS2_DEV用）
+ *
+ *  カーネルのターゲット依存部のインクルードファイル
+ *  kernel_impl.hのターゲット依存部の位置付けとなる
+ */
+
+#ifndef TOPPERS_TARGET_CONFIG_H
+#define TOPPERS_TARGET_CONFIG_H
+
+#include "nios2_system.h"
+
+/*
+ *  トレースログに関する設定
+ */
+#ifdef TOPPERS_ENABLE_TRACE
+#include "logtrace/trace_config.h"
+#endif /* TOPPERS_ENABLE_TRACE */
+
+#ifndef TOPPERS_MACRO_ONLY
+
+extern void target_hardware_initialize(void);
+
+/*
+ *  ターゲットシステム依存の初期化
+ */
+extern void target_initialize(void);
+
+/*
+ *  ターゲットシステムの終了
+ *  システムを終了する時に使う
+ */
+extern void target_exit(void) NoReturn;
+
+/*
+ *  文字列の出力
+ */
+extern void target_fput_str(const char8 *c);
+
+#endif /* TOPPERS_MACRO_ONLY */
+
+/*
+ *  プロセッサ依存モジュール（Nios2用）
+ */
+#include "nios2_gcc/prc_config.h"
+
+#endif /* TOPPERS_TARGET_CONFIG_H */
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_hw_counter.arxml
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_hw_counter.arxml	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_hw_counter.arxml	(revision 295)
@@ -0,0 +1,83 @@
+<?xml version="1.0" encoding="EUC-JP"?>
+<!-- Generated by ABREX Ver. 1.0.0 -->
+<AUTOSAR xmlns="http://autosar.org/schema/r4.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://autosar.org/schema/r4.0 AUTOSAR_4-0-3_STRICT.xsd">
+	<AR-PACKAGES>
+		<AR-PACKAGE>
+			<SHORT-NAME>Ecuc</SHORT-NAME>
+			<ELEMENTS>
+				<ECUC-MODULE-CONFIGURATION-VALUES>
+					<SHORT-NAME>Os</SHORT-NAME>
+					<DEFINITION-REF DEST="ECUC-MODULE-DEF">/AUTOSAR/EcucDefs/Os</DEFINITION-REF>
+					<ECUC-DEF-EDITION>4.2.0</ECUC-DEF-EDITION>
+					<IMPLEMENTATION-CONFIG-VARIANT>VARIANT-PRE-COMPILE</IMPLEMENTATION-CONFIG-VARIANT>
+					<CONTAINERS>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>OsInclude</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsInclude</DEFINITION-REF>
+							<PARAMETER-VALUES>
+								<ECUC-TEXTUAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-STRING-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsInclude/OsIncludeFileName</DEFINITION-REF>
+									<VALUE>target_hw_counter.h</VALUE>
+								</ECUC-TEXTUAL-PARAM-VALUE>
+							</PARAMETER-VALUES>
+						</ECUC-CONTAINER-VALUE>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>MAIN_HW_COUNTER</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsCounter</DEFINITION-REF>
+							<PARAMETER-VALUES>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>
+									<VALUE>536870911</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>
+									<VALUE>4000</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>
+									<VALUE>10</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsCounter/OsSecondsPerTick</DEFINITION-REF>
+									<VALUE>1.666666e-08</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+								<ECUC-TEXTUAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsCounter/OsCounterType</DEFINITION-REF>
+									<VALUE>HARDWARE</VALUE>
+								</ECUC-TEXTUAL-PARAM-VALUE>
+							</PARAMETER-VALUES>
+							<REFERENCE-VALUES>
+								<ECUC-REFERENCE-VALUE>
+									<DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/AUTOSAR/EcucDefs/Os/OsCounter/OsCounterIsrRef</DEFINITION-REF>
+									<VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Ecuc/Os/C2ISR_for_MAIN_HW_COUNTER</VALUE-REF>
+								</ECUC-REFERENCE-VALUE>
+							</REFERENCE-VALUES>
+						</ECUC-CONTAINER-VALUE>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>C2ISR_for_MAIN_HW_COUNTER</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsIsr</DEFINITION-REF>
+							<PARAMETER-VALUES>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsIsr/OsIsrInterruptNumber</DEFINITION-REF>
+									<VALUE>16</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsIsr/OsIsrInterruptPriority</DEFINITION-REF>
+									<VALUE>1</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsIsr/OsIsrStackSize</DEFINITION-REF>
+									<VALUE>592</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+								<ECUC-TEXTUAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsIsr/OsIsrCategory</DEFINITION-REF>
+									<VALUE>CATEGORY_2</VALUE>
+								</ECUC-TEXTUAL-PARAM-VALUE>
+							</PARAMETER-VALUES>
+						</ECUC-CONTAINER-VALUE>
+					</CONTAINERS>
+				</ECUC-MODULE-CONFIGURATION-VALUES>
+			</ELEMENTS>
+		</AR-PACKAGE>
+	</AR-PACKAGES>
+</AUTOSAR>
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_hw_counter.c
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_hw_counter.c	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_hw_counter.c	(revision 295)
@@ -0,0 +1,591 @@
+/*
+ *  TOPPERS ATK2
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *      Automotive Kernel Version 2
+ *
+ *  Copyright (C) 2011-2015 by Center for Embedded Computing Systems
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2011-2015 by FUJI SOFT INCORPORATED, JAPAN
+ *  Copyright (C) 2011-2013 by Spansion LLC, USA
+ *  Copyright (C) 2011-2015 by NEC Communication Systems, Ltd., JAPAN
+ *  Copyright (C) 2011-2015 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
+ *  Copyright (C) 2011-2014 by Renesas Electronics Corporation, JAPAN
+ *  Copyright (C) 2011-2015 by Sunny Giken Inc., JAPAN
+ *  Copyright (C) 2011-2015 by TOSHIBA CORPORATION, JAPAN
+ *  Copyright (C) 2011-2015 by Witz Corporation
+ *  Copyright (C) 2014-2015 by AISIN COMCRUISE Co., Ltd., JAPAN
+ *  Copyright (C) 2014-2015 by eSOL Co.,Ltd., JAPAN
+ *  Copyright (C) 2014-2015 by SCSK Corporation, JAPAN
+ *
+ *  上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
+ *  ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
+ *  変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
+ *  (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
+ *      権表示，この利用条件および下記の無保証規定が，そのままの形でソー
+ *      スコード中に含まれていること．
+ *  (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
+ *      用できる形で再配布する場合には，再配布に伴うドキュメント（利用
+ *      者マニュアルなど）に，上記の著作権表示，この利用条件および下記
+ *      の無保証規定を掲載すること．
+ *  (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
+ *      用できない形で再配布する場合には，次のいずれかの条件を満たすこ
+ *      と．
+ *    (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
+ *        作権表示，この利用条件および下記の無保証規定を掲載すること．
+ *    (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
+ *        報告すること．
+ *  (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
+ *      害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
+ *      また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
+ *      由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
+ *      免責すること．
+ *
+ *  本ソフトウェアは，AUTOSAR（AUTomotive Open System ARchitecture）仕
+ *  様に基づいている．上記の許諾は，AUTOSARの知的財産権を許諾するもので
+ *  はない．AUTOSARは，AUTOSAR仕様に基づいたソフトウェアを商用目的で利
+ *  用する者に対して，AUTOSARパートナーになることを求めている．
+ *
+ *  本ソフトウェアは，無保証で提供されているものである．上記著作権者お
+ *  よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
+ *  に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
+ *  アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
+ *  の責任を負わない．
+ *
+ *  $Id: target_hw_counter.c 1801 2015-03-27 06:34:43Z t_ishikawa $
+ */
+
+/*
+ *		以下ハードウェアカウンタプログラムのターゲット依存定義（NIOS2_DEV用）
+ *
+ *  使用するタイマ：
+ *    差分タイマ：目的の時間を設定する時の現在時間(現在値タイマ)
+ *              と次の満了時間との相対時間をカウントすることで
+ *              目的の絶対時間に満了したこととする
+ *              count mode:count down once
+ *
+ *    現在値タイマ：カウンタ周期分のベースタイマを実現
+ *              (絶対時間をカウント)
+ *              count mode:continuous count down
+ *
+ *    また上記のタイマは32bitのダウンカウンタタイマである
+ *
+ *  制御方針：
+ *
+ *   現在値タイマはユーザ定義カウンタ最大値2倍+1までカウントし，
+ *   周期タイマとして連続カウントダウンして，常に現在時刻を
+ *   取得する．割込み発生する必要がないため，割込みなしモード
+ *
+ *   差分タイマは，満了処理を行うため，割込みありモードで動く
+ *   アラームなどの満了点とタイマー1で示した現在時刻の差を
+ *   現在値タイマに設定する
+ *
+ *  ポイント：
+ *   満了処理は，現在時刻を影響しないため，現在値タイマを設けている
+ *
+ */
+#if defined(TOPPERS_NIOS2_DEV_2S180) || defined(TOPPERS_NIOS2_DEV_DE2_115) || defined(TOPPERS_NIOS2_DEV_DE0_NANO)
+
+#include "Os.h"
+#include "prc_sil.h"
+#include "target_hw_counter.h"
+
+/* 内部関数のプロトタイプ宣言 */
+static TickType get_curr_time(uint32 irq_no, TickType maxval);
+static void init_hwcounter(uint32 irq_no, TickType maxval, TimeType nspertick, TickRefType cycle);
+static void start_hwcounter(uint32 irq_no);
+static void stop_hwcounter(uint32 irq_no);
+static void set_hwcounter(uint32 irq_no, TickType exprtick, TickType maxval);
+static TickType get_hwcounter(uint32 irq_no, TickType maxval);
+static void cancel_hwcounter(uint32 irq_no);
+static void trigger_hwcounter(uint32 irq_no);
+static void int_clear_hwcounter(uint32 irq_no);
+static void int_cancel_hwcounter(uint32 irq_no);
+static void increment_hwcounter(uint32 irq_no);
+
+/*
+ *  ハードウェアカウンタ現在ティック値取得
+ *  ダウンカウンタタイマのため，変換が必要
+ */
+static TickType
+get_curr_time(uint32 irq_no, TickType maxval)
+{
+	TickType curr_time = 0U;
+
+	/* スナップレジスタに書き込むと値をホールドする */
+	sil_wrw_iop((void *) TIMER_SNAPL(irq_no + 1U), 0x00U);
+
+	/* タイマーからカウント値を読み込む */
+	curr_time = sil_rew_iop((void *) TIMER_SNAPL(irq_no + 1U));
+	curr_time |= sil_rew_iop((void *) TIMER_SNAPH(irq_no + 1U)) << 16U;
+
+	/* ダウンカウンタの為，現在チック値に変換 */
+	curr_time = maxval - curr_time;
+
+	return(curr_time);
+}
+
+/*
+ *  ハードウェアカウンタの初期化
+ */
+static void
+init_hwcounter(uint32 irq_no, TickType maxval, TimeType nspertick, TickRefType cycle)
+{
+	*cycle = maxval;
+
+	/* 差分タイマ停止 */
+	sil_wrw_iop((void *) TIMER_CONTROL(irq_no), TIMER_CONTROL_STOP);
+	/* 差分タイマタイムアウトステータスクリア */
+	sil_wrw_iop((void *) TIMER_STATUS(irq_no), 0x00U);
+
+	/* 現在値タイマ停止 */
+	sil_wrw_iop((void *) TIMER_CONTROL(irq_no + 1U), TIMER_CONTROL_STOP);
+	/* 現在値タイマタイムアウトステータスクリア */
+	sil_wrw_iop((void *) TIMER_STATUS(irq_no + 1U), 0x00U);
+
+	/* 現在値タイマカウンターセット 上位16bit */
+	sil_wrw_iop((void *) TIMER_PERIODH(irq_no + 1U), (maxval >> 16U));
+	/* 現在値タイマカウンターセット 下位16bit */
+	sil_wrw_iop((void *) TIMER_PERIODL(irq_no + 1U), (maxval & 0xffffU));
+}
+
+/*
+ *  ハードウェアカウンタの開始
+ */
+static void
+start_hwcounter(uint32 irq_no)
+{
+	/*
+	 *  現在値タイマ開始(continuous count down mode)
+	 *  割込み必要がないため，割込みなしモード
+	 */
+	sil_wrw_iop((void *) TIMER_CONTROL(irq_no + 1U), TIMER_CONTROL_CONT | TIMER_CONTROL_START);
+}
+
+/*
+ *  ハードウェアカウンタの停止
+ */
+static void
+stop_hwcounter(uint32 irq_no)
+{
+	/* 差分タイマ停止 */
+	sil_wrw_iop((void *) TIMER_CONTROL(irq_no), TIMER_CONTROL_STOP);
+
+	/* 差分タイマの割込み要求のクリア */
+	sil_wrw_iop((void *) TIMER_STATUS(irq_no), 0x00U);
+
+	/* 現在値タイマ停止 */
+	sil_wrw_iop((void *) TIMER_CONTROL(irq_no + 1U), TIMER_CONTROL_STOP);
+
+	/* 現在値タイマの割込み要求のクリア */
+	sil_wrw_iop((void *) TIMER_STATUS(irq_no + 1U), 0x00U);
+}
+
+/*
+ *  ハードウェアカウンタへの満了時間の設定
+ */
+static void
+set_hwcounter(uint32 irq_no, TickType exprtick, TickType maxval)
+{
+	TickType	curr_time;
+	TickType	value;
+
+	/* 差分タイマの割込み要求のクリア */
+	sil_wrw_iop((void *) TIMER_STATUS(irq_no), 0x00U);
+
+	/* 現在時刻の取得	*/
+	curr_time = get_curr_time(irq_no, maxval);
+
+	/* タイマに設定する値を算出	*/
+	if (exprtick >= curr_time) {
+		value = exprtick - curr_time;
+	}
+	else {
+		value = maxval - curr_time + exprtick + 1U;
+	}
+
+	/*
+	 *  タイマに0x00を設定し，割込み発生後，再度0を設定した場合，2回目の
+	 *  0x00設定後の割込みは発生しないので，0x00設定値を0x01に直して設定
+	 *  タイマにセットする値は，期待する周期のカウント値から-1する必要がある
+	 */
+	if (value <= 0x01U) {
+		value = 0x01U;
+	}
+	else {
+		value -= 1U;
+	}
+
+	/*
+	 *  差分タイマカウンターセット 上位16bit
+	 *  注意：下位bitより先に設定しないと，割込み2回発生する可能性がある
+	 */
+	sil_wrw_iop((void *) TIMER_PERIODH(irq_no), (value >> 16U));
+	/* 差分タイマカウンターセット 下位16bit */
+	sil_wrw_iop((void *) TIMER_PERIODL(irq_no), (value & 0xffffU));
+
+	/*
+	 *  差分タイマ開始(count down once mode)
+	 *  割込み必要のため，割込みモードあり
+	 */
+	sil_wrw_iop((void *) TIMER_CONTROL(irq_no), TIMER_CONTROL_ITO | TIMER_CONTROL_START);
+}
+
+/*
+ *  ハードウェアカウンタの現在時間の取得
+ */
+static TickType
+get_hwcounter(uint32 irq_no, TickType maxval)
+{
+	return(get_curr_time(irq_no, maxval));
+}
+
+/*
+ *  ハードウェアカウンタの設定された満了時間の取消
+ */
+static void
+cancel_hwcounter(uint32 irq_no)
+{
+	/* 差分タイマ停止 */
+	sil_wrw_iop((void *) TIMER_CONTROL(irq_no), TIMER_CONTROL_STOP);
+}
+
+/*
+ *  ハードウェアカウンタの強制割込み要求
+ */
+static void
+trigger_hwcounter(uint32 irq_no)
+{
+	/* 差分タイマ停止 */
+	sil_wrw_iop((void *) TIMER_CONTROL(irq_no), TIMER_CONTROL_STOP);
+
+	/* 差分タイマの割込み要求のクリア */
+	sil_wrw_iop((void *) TIMER_STATUS(irq_no), 0x00U);
+
+	/* 差分タイマカウンターに0x01をセットすることで，すぐ満了 */
+	sil_wrw_iop((void *) TIMER_PERIODH(irq_no), 0x00U);
+	sil_wrw_iop((void *) TIMER_PERIODL(irq_no), 0x01U);
+
+	/* 差分タイマ開始 */
+	sil_wrw_iop((void *) TIMER_CONTROL(irq_no), TIMER_CONTROL_ITO | TIMER_CONTROL_START);
+}
+
+/*
+ *  割込み要求のクリア
+ */
+static void
+int_clear_hwcounter(uint32 irq_no)
+{
+	/* 差分タイマの割込み要求のクリア */
+	sil_wrw_iop((void *) TIMER_STATUS(irq_no), 0x00U);
+}
+
+/*
+ *  割込み要求のキャンセル
+ *  ペンディングされている割込み要求をキャンセル
+ */
+static void
+int_cancel_hwcounter(uint32 irq_no)
+{
+	/* 差分タイマの割込み要求のクリア */
+	sil_wrw_iop((void *) TIMER_STATUS(irq_no), 0x00U);
+}
+
+/*
+ *  ハードウェアカウンタのインクリメント
+ */
+static void
+increment_hwcounter(uint32 irq_no)
+{
+	/* Nios2ターゲットは未サポート */
+	return;
+}
+
+/*
+ *  MAIN_HW_COUNTERの定義
+ */
+/* カウンタの最大値の2倍+1 */
+static TickType MAIN_HW_COUNTER_maxval;
+
+/*
+ *  ハードウェアカウンタの初期化
+ */
+void
+init_hwcounter_MAIN_HW_COUNTER(TickType maxval, TimeType nspertick)
+{
+	init_hwcounter(TIMER_0_IRQ, maxval, nspertick, &MAIN_HW_COUNTER_maxval);
+}
+
+/*
+ *  ハードウェアカウンタの開始
+ */
+void
+start_hwcounter_MAIN_HW_COUNTER(void)
+{
+	start_hwcounter(TIMER_0_IRQ);
+}
+
+/*
+ *  ハードウェアカウンタの停止
+ */
+void
+stop_hwcounter_MAIN_HW_COUNTER(void)
+{
+	stop_hwcounter(TIMER_0_IRQ);
+}
+
+/*
+ *  ハードウェアカウンタへの満了時間の設定
+ */
+void
+set_hwcounter_MAIN_HW_COUNTER(TickType exprtick)
+{
+	set_hwcounter(TIMER_0_IRQ, exprtick, MAIN_HW_COUNTER_maxval);
+}
+
+/*
+ *  ハードウェアカウンタの現在時間の取得
+ */
+TickType
+get_hwcounter_MAIN_HW_COUNTER(void)
+{
+	return(get_hwcounter(TIMER_0_IRQ, MAIN_HW_COUNTER_maxval));
+}
+
+/*
+ *  ハードウェアカウンタの設定された満了時間の取消
+ */
+void
+cancel_hwcounter_MAIN_HW_COUNTER(void)
+{
+	cancel_hwcounter(TIMER_0_IRQ);
+}
+
+/*
+ *  ハードウェアカウンタの強制割込み要求
+ */
+void
+trigger_hwcounter_MAIN_HW_COUNTER(void)
+{
+	trigger_hwcounter(TIMER_0_IRQ);
+}
+
+/*
+ *  ハードウェアカウンタの設定された満了時間の取消
+ */
+void
+int_clear_hwcounter_MAIN_HW_COUNTER(void)
+{
+	int_clear_hwcounter(TIMER_0_IRQ);
+}
+
+/*
+ *  ハードウェアカウンタの設定された満了時間の取消
+ */
+void
+int_cancel_hwcounter_MAIN_HW_COUNTER(void)
+{
+	int_cancel_hwcounter(TIMER_0_IRQ);
+}
+
+/*
+ *  ハードウェアカウンタのインクリメント
+ */
+void
+increment_hwcounter_MAIN_HW_COUNTER(void)
+{
+	increment_hwcounter(TIMER_0_IRQ);
+}
+
+/*
+ *  SUB_HW_COUNTER1Bの定義
+ */
+/* カウンタの最大値の2倍+1 */
+static TickType SUB_HW_COUNTER1_maxval;
+
+/*
+ *  ハードウェアカウンタの初期化
+ */
+void
+init_hwcounter_SUB_HW_COUNTER1(TickType maxval, TimeType nspertick)
+{
+	init_hwcounter(TIMER_2_IRQ, maxval, nspertick, &SUB_HW_COUNTER1_maxval);
+}
+
+/*
+ *  ハードウェアカウンタの開始
+ */
+void
+start_hwcounter_SUB_HW_COUNTER1(void)
+{
+	start_hwcounter(TIMER_2_IRQ);
+}
+
+/*
+ *  ハードウェアカウンタの停止
+ */
+void
+stop_hwcounter_SUB_HW_COUNTER1(void)
+{
+	stop_hwcounter(TIMER_2_IRQ);
+}
+
+/*
+ *  ハードウェアカウンタへの満了時間の設定
+ */
+void
+set_hwcounter_SUB_HW_COUNTER1(TickType exprtick)
+{
+	set_hwcounter(TIMER_2_IRQ, exprtick, SUB_HW_COUNTER1_maxval);
+}
+
+/*
+ *  ハードウェアカウンタの現在時間の取得
+ */
+TickType
+get_hwcounter_SUB_HW_COUNTER1(void)
+{
+	return(get_hwcounter(TIMER_2_IRQ, SUB_HW_COUNTER1_maxval));
+}
+
+/*
+ *  ハードウェアカウンタの設定された満了時間の取消
+ */
+void
+cancel_hwcounter_SUB_HW_COUNTER1(void)
+{
+	cancel_hwcounter(TIMER_2_IRQ);
+}
+
+/*
+ *  ハードウェアカウンタの強制割込み要求
+ */
+void
+trigger_hwcounter_SUB_HW_COUNTER1(void)
+{
+	trigger_hwcounter(TIMER_2_IRQ);
+}
+
+/*
+ *  ハードウェアカウンタの設定された満了時間の取消
+ */
+void
+int_clear_hwcounter_SUB_HW_COUNTER1(void)
+{
+	int_clear_hwcounter(TIMER_2_IRQ);
+}
+
+/*
+ *  ハードウェアカウンタの設定された満了時間の取消
+ */
+void
+int_cancel_hwcounter_SUB_HW_COUNTER1(void)
+{
+	int_cancel_hwcounter(TIMER_2_IRQ);
+}
+
+/*
+ *  ハードウェアカウンタのインクリメント
+ */
+void
+increment_hwcounter_SUB_HW_COUNTER1(void)
+{
+	increment_hwcounter(TIMER_2_IRQ);
+}
+
+/*
+ *  SUB_HW_COUNTER2の定義
+ */
+/* カウンタの最大値の2倍+1 */
+static TickType SUB_HW_COUNTER2_maxval;
+
+/*
+ *  ハードウェアカウンタの初期化
+ */
+void
+init_hwcounter_SUB_HW_COUNTER2(TickType maxval, TimeType nspertick)
+{
+	init_hwcounter(TIMER_4_IRQ, maxval, nspertick, &SUB_HW_COUNTER2_maxval);
+}
+
+/*
+ *  ハードウェアカウンタの開始
+ */
+void
+start_hwcounter_SUB_HW_COUNTER2(void)
+{
+	start_hwcounter(TIMER_4_IRQ);
+}
+
+/*
+ *  ハードウェアカウンタの停止
+ */
+void
+stop_hwcounter_SUB_HW_COUNTER2(void)
+{
+	stop_hwcounter(TIMER_4_IRQ);
+}
+
+/*
+ *  ハードウェアカウンタへの満了時間の設定
+ */
+void
+set_hwcounter_SUB_HW_COUNTER2(TickType exprtick)
+{
+	set_hwcounter(TIMER_4_IRQ, exprtick, SUB_HW_COUNTER2_maxval);
+}
+
+/*
+ *  ハードウェアカウンタの現在時間の取得
+ */
+TickType
+get_hwcounter_SUB_HW_COUNTER2(void)
+{
+	return(get_hwcounter(TIMER_4_IRQ, SUB_HW_COUNTER2_maxval));
+}
+
+/*
+ *  ハードウェアカウンタの設定された満了時間の取消
+ */
+void
+cancel_hwcounter_SUB_HW_COUNTER2(void)
+{
+	cancel_hwcounter(TIMER_4_IRQ);
+}
+
+/*
+ *  ハードウェアカウンタの強制割込み要求
+ */
+void
+trigger_hwcounter_SUB_HW_COUNTER2(void)
+{
+	trigger_hwcounter(TIMER_4_IRQ);
+}
+
+/*
+ *  ハードウェアカウンタの設定された満了時間の取消
+ */
+void
+int_clear_hwcounter_SUB_HW_COUNTER2(void)
+{
+	int_clear_hwcounter(TIMER_4_IRQ);
+}
+
+/*
+ *  ハードウェアカウンタの設定された満了時間の取消
+ */
+void
+int_cancel_hwcounter_SUB_HW_COUNTER2(void)
+{
+	int_cancel_hwcounter(TIMER_4_IRQ);
+}
+
+/*
+ *  ハードウェアカウンタのインクリメント
+ */
+void
+increment_hwcounter_SUB_HW_COUNTER2(void)
+{
+	increment_hwcounter(TIMER_4_IRQ);
+}
+
+#endif /* defined(TOPPERS_NIOS2_DEV_2S180) || defined(TOPPERS_NIOS2_DEV_DE2_115) */
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_hw_counter.h
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_hw_counter.h	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_hw_counter.h	(revision 295)
@@ -0,0 +1,205 @@
+/*
+ *  TOPPERS ATK2
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *      Automotive Kernel Version 2
+ *
+ *  Copyright (C) 2008-2015 by Center for Embedded Computing Systems
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2011-2015 by FUJI SOFT INCORPORATED, JAPAN
+ *  Copyright (C) 2011-2013 by Spansion LLC, USA
+ *  Copyright (C) 2011-2015 by NEC Communication Systems, Ltd., JAPAN
+ *  Copyright (C) 2011-2015 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
+ *  Copyright (C) 2011-2014 by Renesas Electronics Corporation, JAPAN
+ *  Copyright (C) 2011-2015 by Sunny Giken Inc., JAPAN
+ *  Copyright (C) 2011-2015 by TOSHIBA CORPORATION, JAPAN
+ *  Copyright (C) 2011-2015 by Witz Corporation
+ *  Copyright (C) 2014-2015 by AISIN COMCRUISE Co., Ltd., JAPAN
+ *  Copyright (C) 2014-2015 by eSOL Co.,Ltd., JAPAN
+ *  Copyright (C) 2014-2015 by SCSK Corporation, JAPAN
+ *
+ *  上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
+ *  ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
+ *  変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
+ *  (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
+ *      権表示，この利用条件および下記の無保証規定が，そのままの形でソー
+ *      スコード中に含まれていること．
+ *  (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
+ *      用できる形で再配布する場合には，再配布に伴うドキュメント（利用
+ *      者マニュアルなど）に，上記の著作権表示，この利用条件および下記
+ *      の無保証規定を掲載すること．
+ *  (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
+ *      用できない形で再配布する場合には，次のいずれかの条件を満たすこ
+ *      と．
+ *    (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
+ *        作権表示，この利用条件および下記の無保証規定を掲載すること．
+ *    (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
+ *        報告すること．
+ *  (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
+ *      害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
+ *      また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
+ *      由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
+ *      免責すること．
+ *
+ *  本ソフトウェアは，AUTOSAR（AUTomotive Open System ARchitecture）仕
+ *  様に基づいている．上記の許諾は，AUTOSARの知的財産権を許諾するもので
+ *  はない．AUTOSARは，AUTOSAR仕様に基づいたソフトウェアを商用目的で利
+ *  用する者に対して，AUTOSARパートナーになることを求めている．
+ *
+ *  本ソフトウェアは，無保証で提供されているものである．上記著作権者お
+ *  よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
+ *  に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
+ *  アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
+ *  の責任を負わない．
+ *
+ *  $Id: target_hw_counter.h 1801 2015-03-27 06:34:43Z t_ishikawa $
+ */
+
+/*
+ *		ハードウェアカウンタのターゲット依存定義（NIOS2_DEV用）
+ */
+
+#ifndef TOPPERS_TARGET_HW_COUNTER_H
+#define TOPPERS_TARGET_HW_COUNTER_H
+
+/*
+ *  カウンタ最大値
+ */
+#define MAX_TIMER_CNT		((uint32) 0xFFFFFFFF)
+
+/*
+ *  カウンタ周期最大値
+ */
+#define MAX_CNT_CYCLE		((uint32) 0x7FFFFFFF)
+
+/*
+ *  タイマハードウェア依存のベース定義
+ */
+#ifdef TOPPERS_NIOS2_DEV_2S180
+
+/*
+ *  タイマークロック周波数（Hz）50MHz
+ */
+#define TIMER_CLOCK_HZ		((uint32) 50000000)
+
+/*
+ *  NIOS2_DEV_2S180 用の定義割込み番号
+ */
+#define TIMER_0_IRQ			UINT_C(16)
+#define TIMER_1_IRQ			UINT_C(17)
+#define TIMER_2_IRQ			UINT_C(18)
+#define TIMER_3_IRQ			UINT_C(19)
+#define TIMER_4_IRQ			UINT_C(20)
+#define TIMER_5_IRQ			UINT_C(21)
+#define TIMER_6_IRQ			UINT_C(22)
+#define TIMER_7_IRQ			UINT_C(23)
+#define TIMER_8_IRQ			UINT_C(24)
+#define TIMER_9_IRQ			UINT_C(25)
+#define TIMER_10_IRQ		UINT_C(26)
+#define TIMER_11_IRQ		UINT_C(27)
+#define TIMER_12_IRQ		UINT_C(28)
+#define TIMER_13_IRQ		UINT_C(29)
+#define TIMER_14_IRQ		UINT_C(30)
+#define TIMER_15_IRQ		UINT_C(31)
+
+/*
+ *  NIOS2_DEV_2S180 用の定義タイマレジスタベース
+ */
+#define TIMER_BASE(INTNO)	(UINT_C(0x01001020) + (UINT_C(0x20) * ((INTNO) - UINT_C(16))))
+
+#elif defined(TOPPERS_NIOS2_DEV_DE2_115) || defined(TOPPERS_NIOS2_DEV_DE0_NANO)
+
+/*
+ *  タイマークロック周波数（Hz）60MHz
+ */
+#define TIMER_CLOCK_HZ		((uint32) 60000000)
+
+/*
+ *  NIOS2_DEV_DE2_115 用の定義割込み番号
+ */
+#define TIMER_0_IRQ			UINT_C(16)
+#define TIMER_1_IRQ			UINT_C(17)
+#define TIMER_2_IRQ			UINT_C(18)
+#define TIMER_3_IRQ			UINT_C(19)
+#define TIMER_4_IRQ			UINT_C(20)
+#define TIMER_5_IRQ			UINT_C(21)
+#define TIMER_6_IRQ			UINT_C(22)
+#define TIMER_7_IRQ			UINT_C(23)
+#define TIMER_8_IRQ			UINT_C(24)
+#define TIMER_9_IRQ			UINT_C(25)
+#define TIMER_10_IRQ		UINT_C(26)
+#define TIMER_11_IRQ		UINT_C(27)
+#define TIMER_12_IRQ		UINT_C(28)
+#define TIMER_13_IRQ		UINT_C(29)
+#define TIMER_14_IRQ		UINT_C(30)
+#define TIMER_15_IRQ		UINT_C(31)
+
+/*
+ *  NIOS2_DEV_DE2_115 用の定義タイマレジスタベース
+ */
+#define TIMER_BASE(INTNO)	(UINT_C(0x08000000) + (UINT_C(0x00000020) * (INTNO)))
+
+#else /* TOPPERS_NIOS2_DEV_2S180/TOPPERS_NIOS2_DEV_DE2_115 */
+
+/* それ以外のターゲット定義 */
+#endif /* TOPPERS_NIOS2_DEV_2S180/TOPPERS_NIOS2_DEV_DE2_115 */
+
+/*
+ *  タイマcontrolレジスタのビット定義
+ */
+#define TIMER_CONTROL_ITO		(UINT_C(0x00000001))
+#define TIMER_CONTROL_CONT		(UINT_C(0x00000002))
+#define TIMER_CONTROL_START		(UINT_C(0x00000004))
+#define TIMER_CONTROL_STOP		(UINT_C(0x00000008))
+
+/*
+ *  TIMER関連レジスタ定義
+ */
+#define TIMER_STATUS(INTNO)		(TIMER_BASE(INTNO) + UINT_C(0x00000000))
+#define TIMER_CONTROL(INTNO)	(TIMER_BASE(INTNO) + UINT_C(0x00000004))
+#define TIMER_PERIODL(INTNO)	(TIMER_BASE(INTNO) + UINT_C(0x00000008))
+#define TIMER_PERIODH(INTNO)	(TIMER_BASE(INTNO) + UINT_C(0x0000000C))
+#define TIMER_SNAPL(INTNO)		(TIMER_BASE(INTNO) + UINT_C(0x00000010))
+#define TIMER_SNAPH(INTNO)		(TIMER_BASE(INTNO) + UINT_C(0x00000014))
+
+/* MAIN_HW_COUNTERの定義 */
+extern void init_hwcounter_MAIN_HW_COUNTER(TickType maxval, TimeType nspertick);
+extern void start_hwcounter_MAIN_HW_COUNTER(void);
+extern void stop_hwcounter_MAIN_HW_COUNTER(void);
+extern void set_hwcounter_MAIN_HW_COUNTER(TickType exprtick);
+extern TickType get_hwcounter_MAIN_HW_COUNTER(void);
+extern void cancel_hwcounter_MAIN_HW_COUNTER(void);
+extern void trigger_hwcounter_MAIN_HW_COUNTER(void);
+extern void int_clear_hwcounter_MAIN_HW_COUNTER(void);
+extern void int_cancel_hwcounter_MAIN_HW_COUNTER(void);
+extern void increment_hwcounter_MAIN_HW_COUNTER(void);
+
+/* SUB_HW_COUNTER1の定義 */
+extern void init_hwcounter_SUB_HW_COUNTER1(TickType maxval, TimeType nspertick);
+extern void start_hwcounter_SUB_HW_COUNTER1(void);
+extern void stop_hwcounter_SUB_HW_COUNTER1(void);
+extern void set_hwcounter_SUB_HW_COUNTER1(TickType exprtick);
+extern TickType get_hwcounter_SUB_HW_COUNTER1(void);
+extern void cancel_hwcounter_SUB_HW_COUNTER1(void);
+extern void trigger_hwcounter_SUB_HW_COUNTER1(void);
+extern void int_clear_hwcounter_SUB_HW_COUNTER1(void);
+extern void int_cancel_hwcounter_SUB_HW_COUNTER1(void);
+extern void increment_hwcounter_SUB_HW_COUNTER1(void);
+
+/* SUB_HW_COUNTER2の定義 */
+extern void init_hwcounter_SUB_HW_COUNTER2(TickType maxval, TimeType nspertick);
+extern void start_hwcounter_SUB_HW_COUNTER2(void);
+extern void stop_hwcounter_SUB_HW_COUNTER2(void);
+extern void set_hwcounter_SUB_HW_COUNTER2(TickType exprtick);
+extern TickType get_hwcounter_SUB_HW_COUNTER2(void);
+extern void cancel_hwcounter_SUB_HW_COUNTER2(void);
+extern void trigger_hwcounter_SUB_HW_COUNTER2(void);
+extern void int_clear_hwcounter_SUB_HW_COUNTER2(void);
+extern void int_cancel_hwcounter_SUB_HW_COUNTER2(void);
+extern void increment_hwcounter_SUB_HW_COUNTER2(void);
+
+/*
+ *  10msと一致するティック値(サンプルプログラム用)
+ */
+#define TICK_FOR_10MS	TIMER_CLOCK_HZ / 100
+
+#endif /* TOPPERS_TARGET_HW_COUNTER_H */
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_hw_counter.yaml
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_hw_counter.yaml	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_hw_counter.yaml	(revision 295)
@@ -0,0 +1,103 @@
+#
+#  TOPPERS ATK2
+#      Toyohashi Open Platform for Embedded Real-Time Systems
+#      Automotive Kernel Version 2
+#
+#  Copyright (C) 2013-2015 by Center for Embedded Computing Systems
+#              Graduate School of Information Science, Nagoya Univ., JAPAN
+#  Copyright (C) 2013-2015 by FUJI SOFT INCORPORATED, JAPAN
+#  Copyright (C) 2013-2015 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
+#  Copyright (C) 2013-2014 by Renesas Electronics Corporation, JAPAN
+#  Copyright (C) 2013-2015 by Sunny Giken Inc., JAPAN
+#  Copyright (C) 2013-2015 by TOSHIBA CORPORATION, JAPAN
+#  Copyright (C) 2013-2015 by Witz Corporation
+#  Copyright (C) 2014-2015 by AISIN COMCRUISE Co., Ltd., JAPAN
+#  Copyright (C) 2014-2015 by eSOL Co.,Ltd., JAPAN
+#  Copyright (C) 2014-2015 by NEC Communication Systems, Ltd., JAPAN
+#  Copyright (C) 2014-2015 by SCSK Corporation, JAPAN
+#
+#  上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
+#  ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
+#  変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
+#  (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
+#      権表示，この利用条件および下記の無保証規定が，そのままの形でソー
+#      スコード中に含まれていること．
+#  (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
+#      用できる形で再配布する場合には，再配布に伴うドキュメント（利用
+#      者マニュアルなど）に，上記の著作権表示，この利用条件および下記
+#      の無保証規定を掲載すること．
+#  (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
+#      用できない形で再配布する場合には，次のいずれかの条件を満たすこ
+#      と．
+#    (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
+#        作権表示，この利用条件および下記の無保証規定を掲載すること．
+#    (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
+#        報告すること．
+#  (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
+#      害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
+#      また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
+#      由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
+#      免責すること．
+#
+#  本ソフトウェアは，AUTOSAR（AUTomotive Open System ARchitecture）仕
+#  様に基づいている．上記の許諾は，AUTOSARの知的財産権を許諾するもので
+#  はない．AUTOSARは，AUTOSAR仕様に基づいたソフトウェアを商用目的で利
+#  用する者に対して，AUTOSARパートナーになることを求めている．
+#
+#  本ソフトウェアは，無保証で提供されているものである．上記著作権者お
+#  よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
+#  に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
+#  アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
+#  の責任を負わない．
+#
+#  $Id: target_hw_counter.yaml 1801 2015-03-27 06:34:43Z t_ishikawa $
+#
+
+Ecuc:
+  Os:
+    OsInclude:
+      OsIncludeFileName: target_hw_counter.h
+    MAIN_HW_COUNTER:
+      DefinitionRef: OsCounter
+      OsCounterMaxAllowedValue: 0x1FFFFFFF
+      OsCounterMinCycle: 4000
+      OsCounterTicksPerBase: 10
+      OsSecondsPerTick: 1.666666e-08  # 1.0/TIMER_CLOCK_HZ
+      OsCounterType: HARDWARE
+      OsCounterIsrRef: /Ecuc/Os/C2ISR_for_MAIN_HW_COUNTER
+    C2ISR_for_MAIN_HW_COUNTER:
+      DefinitionRef: OsIsr
+      OsIsrInterruptNumber: 16  # TIMER_0_IRQ
+      OsIsrInterruptPriority: 1
+      OsIsrStackSize: 0x250
+      OsIsrCategory: CATEGORY_2
+
+# 以下，アプリケーションに応じて必要であれば使用する
+#    SUB_HW_COUNTER1:
+#      DefinitionRef: OsCounter
+#      OsCounterMaxAllowedValue: 0x1FFFFFFF
+#      OsCounterMinCycle: 4000
+#      OsCounterTicksPerBase: 10
+#      OsSecondsPerTick: 1.666666e-08  # 1.0/TIMER_CLOCK_HZ
+#      OsCounterType: HARDWARE
+#      OsCounterIsrRef: /Ecuc/Os/C2ISR_for_SUB_HW_COUNTER1
+#    C2ISR_for_SUB_HW_COUNTER1:
+#      DefinitionRef: OsIsr
+#      OsIsrInterruptNumber: 18  # TIMER_2_IRQ
+#      OsIsrInterruptPriority: 1
+#      OsIsrStackSize: 0x250
+#      OsIsrCategory: CATEGORY_2
+#    SUB_HW_COUNTER2:
+#      DefinitionRef: OsCounter
+#      OsCounterMaxAllowedValue: 0x1FFFFFFF
+#      OsCounterMinCycle: 4000
+#      OsCounterTicksPerBase: 10
+#      OsSecondsPerTick: 1.666666e-08  # 1.0/TIMER_CLOCK_HZ
+#      OsCounterType: HARDWARE
+#      OsCounterIsrRef: /Ecuc/Os/C2ISR_for_SUB_HW_COUNTER2
+#    C2ISR_for_SUB_HW_COUNTER2:
+#      DefinitionRef: OsIsr
+#      OsIsrInterruptNumber: 20  # TIMER_4_IRQ
+#      OsIsrInterruptPriority: 1
+#      OsIsrStackSize: 0x250
+#      OsIsrCategory: CATEGORY_2
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_kernel.h
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_kernel.h	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_kernel.h	(revision 295)
@@ -0,0 +1,84 @@
+/*
+ *  TOPPERS ATK2
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *      Automotive Kernel Version 2
+ *
+ *  Copyright (C) 2008-2015 by Center for Embedded Computing Systems
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2011-2015 by FUJI SOFT INCORPORATED, JAPAN
+ *  Copyright (C) 2011-2013 by Spansion LLC, USA
+ *  Copyright (C) 2011-2015 by NEC Communication Systems, Ltd., JAPAN
+ *  Copyright (C) 2011-2015 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
+ *  Copyright (C) 2011-2014 by Renesas Electronics Corporation, JAPAN
+ *  Copyright (C) 2011-2015 by Sunny Giken Inc., JAPAN
+ *  Copyright (C) 2011-2015 by TOSHIBA CORPORATION, JAPAN
+ *  Copyright (C) 2011-2015 by Witz Corporation
+ *  Copyright (C) 2014-2015 by AISIN COMCRUISE Co., Ltd., JAPAN
+ *  Copyright (C) 2014-2015 by eSOL Co.,Ltd., JAPAN
+ *  Copyright (C) 2014-2015 by SCSK Corporation, JAPAN
+ *
+ *  上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
+ *  ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
+ *  変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
+ *  (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
+ *      権表示，この利用条件および下記の無保証規定が，そのままの形でソー
+ *      スコード中に含まれていること．
+ *  (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
+ *      用できる形で再配布する場合には，再配布に伴うドキュメント（利用
+ *      者マニュアルなど）に，上記の著作権表示，この利用条件および下記
+ *      の無保証規定を掲載すること．
+ *  (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
+ *      用できない形で再配布する場合には，次のいずれかの条件を満たすこ
+ *      と．
+ *    (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
+ *        作権表示，この利用条件および下記の無保証規定を掲載すること．
+ *    (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
+ *        報告すること．
+ *  (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
+ *      害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
+ *      また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
+ *      由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
+ *      免責すること．
+ *
+ *  本ソフトウェアは，AUTOSAR（AUTomotive Open System ARchitecture）仕
+ *  様に基づいている．上記の許諾は，AUTOSARの知的財産権を許諾するもので
+ *  はない．AUTOSARは，AUTOSAR仕様に基づいたソフトウェアを商用目的で利
+ *  用する者に対して，AUTOSARパートナーになることを求めている．
+ *
+ *  本ソフトウェアは，無保証で提供されているものである．上記著作権者お
+ *  よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
+ *  に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
+ *  アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
+ *  の責任を負わない．
+ *
+ *  $Id: target_kernel.h 1801 2015-03-27 06:34:43Z t_ishikawa $
+ */
+
+/*
+ *		Os.hのターゲット依存部（NIOS2_DEV用）
+ *
+ *  このインクルードファイルは，Os.hでインクルードされる
+ *  他のファイルから直接インクルードすることはない
+ */
+
+#ifndef TOPPERS_TARGET_KERNEL_H
+#define TOPPERS_TARGET_KERNEL_H
+
+/* チェック用タスクスタックサイズの最小値の定義 */
+#define TARGET_MIN_STKSZ	196
+
+/* 非タスクコンテキスト用のスタック最小値の定義 */
+#define MINIMUM_OSTKSZ	256
+
+/* 各スタックサイズのデフォルト値の定義*/
+#define DEFAULT_TASKSTKSZ	(1024U) /* 1K bytes */
+#define DEFAULT_ISRSTKSZ	(1024U) /* 1K bytes */
+#define DEFAULT_HOOKSTKSZ	(1024U) /* 1K bytes */
+#define DEFAULT_OSSTKSZ		(8192U) /* 8K bytes */
+
+/*
+ *  プロセッサで共通な定義
+ */
+#include "nios2_gcc/prc_kernel.h"
+
+#endif /* TOPPERS_TARGET_KERNEL_H */
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_offset.tf
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_offset.tf	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_offset.tf	(revision 295)
@@ -0,0 +1,69 @@
+$
+$  TOPPERS ATK2
+$      Toyohashi Open Platform for Embedded Real-Time Systems
+$      Automotive Kernel Version 2
+$
+$  Copyright (C) 2011-2015 by Center for Embedded Computing Systems
+$              Graduate School of Information Science, Nagoya Univ., JAPAN
+$  Copyright (C) 2011-2015 by FUJI SOFT INCORPORATED, JAPAN
+$  Copyright (C) 2011-2013 by Spansion LLC, USA
+$  Copyright (C) 2011-2015 by NEC Communication Systems, Ltd., JAPAN
+$  Copyright (C) 2011-2015 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
+$  Copyright (C) 2011-2014 by Renesas Electronics Corporation, JAPAN
+$  Copyright (C) 2011-2015 by Sunny Giken Inc., JAPAN
+$  Copyright (C) 2011-2015 by TOSHIBA CORPORATION, JAPAN
+$  Copyright (C) 2011-2015 by Witz Corporation
+$  Copyright (C) 2014-2015 by AISIN COMCRUISE Co., Ltd., JAPAN
+$  Copyright (C) 2014-2015 by eSOL Co.,Ltd., JAPAN
+$  Copyright (C) 2014-2015 by SCSK Corporation, JAPAN
+$
+$  上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
+$  ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
+$  変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
+$  (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
+$      権表示，この利用条件および下記の無保証規定が，そのままの形でソー
+$      スコード中に含まれていること．
+$  (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
+$      用できる形で再配布する場合には，再配布に伴うドキュメント（利用
+$      者マニュアルなど）に，上記の著作権表示，この利用条件および下記
+$      の無保証規定を掲載すること．
+$  (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
+$      用できない形で再配布する場合には，次のいずれかの条件を満たすこ
+$      と．
+$    (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
+$        作権表示，この利用条件および下記の無保証規定を掲載すること．
+$    (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
+$        報告すること．
+$  (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
+$      害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
+$      また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
+$      由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
+$      免責すること．
+$
+$  本ソフトウェアは，AUTOSAR（AUTomotive Open System ARchitecture）仕
+$  様に基づいている．上記の許諾は，AUTOSARの知的財産権を許諾するもので
+$  はない．AUTOSARは，AUTOSAR仕様に基づいたソフトウェアを商用目的で利
+$  用する者に対して，AUTOSARパートナーになることを求めている．
+$
+$  本ソフトウェアは，無保証で提供されているものである．上記著作権者お
+$  よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
+$  に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
+$  アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
+$  の責任を負わない．
+$
+$  $Id: target_offset.tf 1801 2015-03-27 06:34:43Z t_ishikawa $
+$
+
+$
+$       オフセットファイル生成用テンプレートファイル（NIOS2_DEV用）
+$
+
+$
+$  標準テンプレートファイルのインクルード
+$
+$INCLUDE "kernel/genoffset.tf"$
+
+$
+$  コア依存テンプレートのインクルード（Nios2用）
+$
+$INCLUDE "nios2_gcc/prc_offset.tf"$
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_serial.arxml
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_serial.arxml	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_serial.arxml	(revision 295)
@@ -0,0 +1,29 @@
+<?xml version="1.0" encoding="EUC-JP"?>
+<!-- Generated by ABREX Ver. 1.0.0 -->
+<AUTOSAR xmlns="http://autosar.org/schema/r4.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://autosar.org/schema/r4.0 AUTOSAR_4-0-3_STRICT.xsd">
+	<AR-PACKAGES>
+		<AR-PACKAGE>
+			<SHORT-NAME>Ecuc</SHORT-NAME>
+			<ELEMENTS>
+				<ECUC-MODULE-CONFIGURATION-VALUES>
+					<SHORT-NAME>Os</SHORT-NAME>
+					<DEFINITION-REF DEST="ECUC-MODULE-DEF">/AUTOSAR/EcucDefs/Os</DEFINITION-REF>
+					<ECUC-DEF-EDITION>4.2.0</ECUC-DEF-EDITION>
+					<IMPLEMENTATION-CONFIG-VARIANT>VARIANT-PRE-COMPILE</IMPLEMENTATION-CONFIG-VARIANT>
+					<CONTAINERS>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>OsInclude</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsInclude</DEFINITION-REF>
+							<PARAMETER-VALUES>
+								<ECUC-TEXTUAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-STRING-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsInclude/OsIncludeFileName</DEFINITION-REF>
+									<VALUE>target_serial.h</VALUE>
+								</ECUC-TEXTUAL-PARAM-VALUE>
+							</PARAMETER-VALUES>
+						</ECUC-CONTAINER-VALUE>
+					</CONTAINERS>
+				</ECUC-MODULE-CONFIGURATION-VALUES>
+			</ELEMENTS>
+		</AR-PACKAGE>
+	</AR-PACKAGES>
+</AUTOSAR>
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_serial.h
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_serial.h	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_serial.h	(revision 295)
@@ -0,0 +1,117 @@
+/*
+ *  TOPPERS ATK2
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *      Automotive Kernel Version 2
+ *
+ *  Copyright (C) 2008-2015 by Center for Embedded Computing Systems
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2011-2015 by FUJI SOFT INCORPORATED, JAPAN
+ *  Copyright (C) 2011-2013 by Spansion LLC, USA
+ *  Copyright (C) 2011-2015 by NEC Communication Systems, Ltd., JAPAN
+ *  Copyright (C) 2011-2015 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
+ *  Copyright (C) 2011-2014 by Renesas Electronics Corporation, JAPAN
+ *  Copyright (C) 2011-2015 by Sunny Giken Inc., JAPAN
+ *  Copyright (C) 2011-2015 by TOSHIBA CORPORATION, JAPAN
+ *  Copyright (C) 2011-2015 by Witz Corporation
+ *  Copyright (C) 2014-2015 by AISIN COMCRUISE Co., Ltd., JAPAN
+ *  Copyright (C) 2014-2015 by eSOL Co.,Ltd., JAPAN
+ *  Copyright (C) 2014-2015 by SCSK Corporation, JAPAN
+ *
+ *  上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
+ *  ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
+ *  変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
+ *  (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
+ *      権表示，この利用条件および下記の無保証規定が，そのままの形でソー
+ *      スコード中に含まれていること．
+ *  (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
+ *      用できる形で再配布する場合には，再配布に伴うドキュメント（利用
+ *      者マニュアルなど）に，上記の著作権表示，この利用条件および下記
+ *      の無保証規定を掲載すること．
+ *  (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
+ *      用できない形で再配布する場合には，次のいずれかの条件を満たすこ
+ *      と．
+ *    (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
+ *        作権表示，この利用条件および下記の無保証規定を掲載すること．
+ *    (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
+ *        報告すること．
+ *  (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
+ *      害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
+ *      また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
+ *      由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
+ *      免責すること．
+ *
+ *  本ソフトウェアは，AUTOSAR（AUTomotive Open System ARchitecture）仕
+ *  様に基づいている．上記の許諾は，AUTOSARの知的財産権を許諾するもので
+ *  はない．AUTOSARは，AUTOSAR仕様に基づいたソフトウェアを商用目的で利
+ *  用する者に対して，AUTOSARパートナーになることを求めている．
+ *
+ *  本ソフトウェアは，無保証で提供されているものである．上記著作権者お
+ *  よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
+ *  に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
+ *  アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
+ *  の責任を負わない．
+ *
+ *  $Id: target_serial.h 1801 2015-03-27 06:34:43Z t_ishikawa $
+ */
+
+/*
+ *		シリアルI/Oデバイス（SIO）ドライバ（NIOS2_DEV用）
+ */
+
+#ifndef TOPPERS_TARGET_SERIAL_H
+#define TOPPERS_TARGET_SERIAL_H
+
+#include "nios2_system.h"
+
+/*
+ *  SIOの割込みハンドラのベクタ番号
+ */
+#ifdef USE_UART
+
+#define INTNO_SIO	(UART_PORT1_INT)        /* 割込み番号 */
+#define INTPRI_SIO	2                       /* 割込み優先度 */
+
+/*
+ *  プロセッサ依存モジュール（UART用）
+ */
+#include "nios2_gcc/uart.h"
+
+#ifndef UART_BAUDRATE
+#define UART_BAUDRATE	921600
+#endif
+
+/*
+ *  DIVISORレジスタに設定する値
+ */
+#if   UART_BAUDRATE == 115200
+#define UART_DIVISOR_VALUE	UINT_C(868)
+#elif UART_BAUDRATE == 230400
+#define UART_DIVISOR_VALUE	UINT_C(434)
+#elif UART_BAUDRATE == 460800
+#define UART_DIVISOR_VALUE	UINT_C(217)
+#elif UART_BAUDRATE == 921600
+#define UART_DIVISOR_VALUE	UINT_C(108) /* 108 or 109 */
+#else
+#error "UART_BAUDRATE" is invalid.
+#endif
+
+LOCAL_INLINE void
+uart_set_baudrate(void)
+{
+	sil_wrw_iop((void *) (UART_PORT1_BASE + UART_DIVISOR_OFFSET), UART_DIVISOR_VALUE);
+}
+
+
+#else /* USE_UART */
+
+#define INTNO_SIO	(JTAG_UART_PORT1_INT)   /* 割込み番号 */
+#define INTPRI_SIO	2                       /* 割込み優先度 */
+
+/*
+ *  プロセッサ依存モジュール（JTAG UART用）
+ */
+#include "nios2_gcc/jtag_uart.h"
+
+#endif /* USE_UART */
+
+#endif /* TOPPERS_TARGET_SERIAL_H */
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_serial.yaml
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_serial.yaml	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_serial.yaml	(revision 295)
@@ -0,0 +1,59 @@
+#
+#  TOPPERS ATK2
+#      Toyohashi Open Platform for Embedded Real-Time Systems
+#      Automotive Kernel Version 2
+#
+#  Copyright (C) 2013-2015 by Center for Embedded Computing Systems
+#              Graduate School of Information Science, Nagoya Univ., JAPAN
+#  Copyright (C) 2013-2015 by FUJI SOFT INCORPORATED, JAPAN
+#  Copyright (C) 2013-2015 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
+#  Copyright (C) 2013-2014 by Renesas Electronics Corporation, JAPAN
+#  Copyright (C) 2013-2015 by Sunny Giken Inc., JAPAN
+#  Copyright (C) 2013-2015 by TOSHIBA CORPORATION, JAPAN
+#  Copyright (C) 2013-2015 by Witz Corporation
+#  Copyright (C) 2014-2015 by AISIN COMCRUISE Co., Ltd., JAPAN
+#  Copyright (C) 2014-2015 by eSOL Co.,Ltd., JAPAN
+#  Copyright (C) 2014-2015 by NEC Communication Systems, Ltd., JAPAN
+#  Copyright (C) 2014-2015 by SCSK Corporation, JAPAN
+#
+#  上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
+#  ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
+#  変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
+#  (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
+#      権表示，この利用条件および下記の無保証規定が，そのままの形でソー
+#      スコード中に含まれていること．
+#  (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
+#      用できる形で再配布する場合には，再配布に伴うドキュメント（利用
+#      者マニュアルなど）に，上記の著作権表示，この利用条件および下記
+#      の無保証規定を掲載すること．
+#  (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
+#      用できない形で再配布する場合には，次のいずれかの条件を満たすこ
+#      と．
+#    (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
+#        作権表示，この利用条件および下記の無保証規定を掲載すること．
+#    (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
+#        報告すること．
+#  (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
+#      害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
+#      また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
+#      由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
+#      免責すること．
+#
+#  本ソフトウェアは，AUTOSAR（AUTomotive Open System ARchitecture）仕
+#  様に基づいている．上記の許諾は，AUTOSARの知的財産権を許諾するもので
+#  はない．AUTOSARは，AUTOSAR仕様に基づいたソフトウェアを商用目的で利
+#  用する者に対して，AUTOSARパートナーになることを求めている．
+#
+#  本ソフトウェアは，無保証で提供されているものである．上記著作権者お
+#  よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
+#  に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
+#  アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
+#  の責任を負わない．
+#
+#  $Id: target_serial.yaml 1801 2015-03-27 06:34:43Z t_ishikawa $
+#
+
+Ecuc:
+  Os:
+    OsInclude:
+      OsIncludeFileName: target_serial.h
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_sysmod.h
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_sysmod.h	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_sysmod.h	(revision 295)
@@ -0,0 +1,78 @@
+/*
+ *  TOPPERS ATK2
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *      Automotive Kernel Version 2
+ *
+ *  Copyright (C) 2008-2015 by Center for Embedded Computing Systems
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2011-2015 by FUJI SOFT INCORPORATED, JAPAN
+ *  Copyright (C) 2011-2013 by Spansion LLC, USA
+ *  Copyright (C) 2011-2015 by NEC Communication Systems, Ltd., JAPAN
+ *  Copyright (C) 2011-2015 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
+ *  Copyright (C) 2011-2014 by Renesas Electronics Corporation, JAPAN
+ *  Copyright (C) 2011-2015 by Sunny Giken Inc., JAPAN
+ *  Copyright (C) 2011-2015 by TOSHIBA CORPORATION, JAPAN
+ *  Copyright (C) 2011-2015 by Witz Corporation
+ *  Copyright (C) 2014-2015 by AISIN COMCRUISE Co., Ltd., JAPAN
+ *  Copyright (C) 2014-2015 by eSOL Co.,Ltd., JAPAN
+ *  Copyright (C) 2014-2015 by SCSK Corporation, JAPAN
+ *
+ *  上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
+ *  ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
+ *  変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
+ *  (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
+ *      権表示，この利用条件および下記の無保証規定が，そのままの形でソー
+ *      スコード中に含まれていること．
+ *  (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
+ *      用できる形で再配布する場合には，再配布に伴うドキュメント（利用
+ *      者マニュアルなど）に，上記の著作権表示，この利用条件および下記
+ *      の無保証規定を掲載すること．
+ *  (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
+ *      用できない形で再配布する場合には，次のいずれかの条件を満たすこ
+ *      と．
+ *    (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
+ *        作権表示，この利用条件および下記の無保証規定を掲載すること．
+ *    (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
+ *        報告すること．
+ *  (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
+ *      害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
+ *      また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
+ *      由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
+ *      免責すること．
+ *
+ *  本ソフトウェアは，AUTOSAR（AUTomotive Open System ARchitecture）仕
+ *  様に基づいている．上記の許諾は，AUTOSARの知的財産権を許諾するもので
+ *  はない．AUTOSARは，AUTOSAR仕様に基づいたソフトウェアを商用目的で利
+ *  用する者に対して，AUTOSARパートナーになることを求めている．
+ *
+ *  本ソフトウェアは，無保証で提供されているものである．上記著作権者お
+ *  よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
+ *  に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
+ *  アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
+ *  の責任を負わない．
+ *
+ *  $Id: target_sysmod.h 1801 2015-03-27 06:34:43Z t_ishikawa $
+ */
+
+/*
+ *		システムモジュールのターゲット依存部（NIOS2_DEV用）
+ *
+ *  システムモジュールのターゲット依存部のインクルードファイル
+ *  このファイルの内容は，コンポーネント記述ファイルに記述され，
+ *  このファイルは無くなる見込み
+ */
+#ifndef TOPPERS_TARGET_SYSMOD_H
+#define TOPPERS_TARGET_SYSMOD_H
+
+#include "nios2_system.h"
+#include "nios2_gcc/prc_sil.h"
+
+/*
+ *  システムログの低レベル出力のための文字出力
+ *
+ *  ターゲット依存の方法で，文字cを表示/出力/保存する
+ */
+extern void target_fput_log(char8 c);
+
+
+#endif /* TOPPERS_TARGET_SYSMOD_H */
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_test.arxml
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_test.arxml	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_test.arxml	(revision 295)
@@ -0,0 +1,47 @@
+<?xml version="1.0" encoding="EUC-JP"?>
+<!-- Generated by ABREX Ver. 1.0.0 -->
+<AUTOSAR xmlns="http://autosar.org/schema/r4.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://autosar.org/schema/r4.0 AUTOSAR_4-0-3_STRICT.xsd">
+	<AR-PACKAGES>
+		<AR-PACKAGE>
+			<SHORT-NAME>Ecuc</SHORT-NAME>
+			<ELEMENTS>
+				<ECUC-MODULE-CONFIGURATION-VALUES>
+					<SHORT-NAME>Os</SHORT-NAME>
+					<DEFINITION-REF DEST="ECUC-MODULE-DEF">/AUTOSAR/EcucDefs/Os</DEFINITION-REF>
+					<ECUC-DEF-EDITION>4.2.0</ECUC-DEF-EDITION>
+					<IMPLEMENTATION-CONFIG-VARIANT>VARIANT-PRE-COMPILE</IMPLEMENTATION-CONFIG-VARIANT>
+					<CONTAINERS>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>OsInclude</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsInclude</DEFINITION-REF>
+							<PARAMETER-VALUES>
+								<ECUC-TEXTUAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-STRING-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsInclude/OsIncludeFileName</DEFINITION-REF>
+									<VALUE>target_test.h</VALUE>
+								</ECUC-TEXTUAL-PARAM-VALUE>
+							</PARAMETER-VALUES>
+						</ECUC-CONTAINER-VALUE>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>SmpC1ISR</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsIsr</DEFINITION-REF>
+							<PARAMETER-VALUES>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsIsr/OsIsrInterruptNumber</DEFINITION-REF>
+									<VALUE>TIMER_5_IRQ</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+								<ECUC-NUMERICAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsIsr/OsIsrInterruptPriority</DEFINITION-REF>
+									<VALUE>8</VALUE>
+								</ECUC-NUMERICAL-PARAM-VALUE>
+								<ECUC-TEXTUAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsIsr/OsIsrCategory</DEFINITION-REF>
+									<VALUE>CATEGORY_1</VALUE>
+								</ECUC-TEXTUAL-PARAM-VALUE>
+							</PARAMETER-VALUES>
+						</ECUC-CONTAINER-VALUE>
+					</CONTAINERS>
+				</ECUC-MODULE-CONFIGURATION-VALUES>
+			</ELEMENTS>
+		</AR-PACKAGE>
+	</AR-PACKAGES>
+</AUTOSAR>
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_test.c
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_test.c	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_test.c	(revision 295)
@@ -0,0 +1,81 @@
+/*
+ *  TOPPERS ATK2
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *      Automotive Kernel Version 2
+ *
+ *  Copyright (C) 2011-2015 by Center for Embedded Computing Systems
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2011-2015 by FUJI SOFT INCORPORATED, JAPAN
+ *  Copyright (C) 2011-2013 by Spansion LLC, USA
+ *  Copyright (C) 2011-2015 by NEC Communication Systems, Ltd., JAPAN
+ *  Copyright (C) 2011-2015 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
+ *  Copyright (C) 2011-2014 by Renesas Electronics Corporation, JAPAN
+ *  Copyright (C) 2011-2015 by Sunny Giken Inc., JAPAN
+ *  Copyright (C) 2011-2015 by TOSHIBA CORPORATION, JAPAN
+ *  Copyright (C) 2011-2015 by Witz Corporation
+ *  Copyright (C) 2014-2015 by AISIN COMCRUISE Co., Ltd., JAPAN
+ *  Copyright (C) 2014-2015 by eSOL Co.,Ltd., JAPAN
+ *  Copyright (C) 2014-2015 by SCSK Corporation, JAPAN
+ *
+ *  上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
+ *  ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
+ *  変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
+ *  (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
+ *      権表示，この利用条件および下記の無保証規定が，そのままの形でソー
+ *      スコード中に含まれていること．
+ *  (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
+ *      用できる形で再配布する場合には，再配布に伴うドキュメント（利用
+ *      者マニュアルなど）に，上記の著作権表示，この利用条件および下記
+ *      の無保証規定を掲載すること．
+ *  (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
+ *      用できない形で再配布する場合には，次のいずれかの条件を満たすこ
+ *      と．
+ *    (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
+ *        作権表示，この利用条件および下記の無保証規定を掲載すること．
+ *    (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
+ *        報告すること．
+ *  (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
+ *      害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
+ *      また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
+ *      由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
+ *      免責すること．
+ *
+ *  本ソフトウェアは，AUTOSAR（AUTomotive Open System ARchitecture）仕
+ *  様に基づいている．上記の許諾は，AUTOSARの知的財産権を許諾するもので
+ *  はない．AUTOSARは，AUTOSAR仕様に基づいたソフトウェアを商用目的で利
+ *  用する者に対して，AUTOSARパートナーになることを求めている．
+ *
+ *  本ソフトウェアは，無保証で提供されているものである．上記著作権者お
+ *  よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
+ *  に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
+ *  アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
+ *  の責任を負わない．
+ *
+ *  $Id: target_test.c 1801 2015-03-27 06:34:43Z t_ishikawa $
+ */
+
+#if defined(TOPPERS_NIOS2_DEV_2S180) || defined(TOPPERS_NIOS2_DEV_DE2_115)
+
+#include "Os.h"
+#include "t_syslog.h"
+#include "target_hw_counter.h"
+
+/*
+ *  C1ISRのためのタイマ割り込み発生
+ */
+void
+trigger_hwcounter_SmpC1ISR(void)
+{
+	trigger_hwcounter(TIMER_5_IRQ);
+}
+
+/*
+ *  C1ISRのサンプルから呼び出すC関数
+ */
+void
+c1isr_syslog(void)
+{
+	syslog(LOG_INFO, "TIMER_5_IRQ");
+}
+
+#endif /* defined(TOPPERS_NIOS2_DEV_2S180) || defined(TOPPERS_NIOS2_DEV_DE2_115) */
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_test.h
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_test.h	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_test.h	(revision 295)
@@ -0,0 +1,81 @@
+/*
+ *  TOPPERS ATK2
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *      Automotive Kernel Version 2
+ *
+ *  Copyright (C) 2008-2015 by Center for Embedded Computing Systems
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2011-2015 by FUJI SOFT INCORPORATED, JAPAN
+ *  Copyright (C) 2011-2013 by Spansion LLC, USA
+ *  Copyright (C) 2011-2015 by NEC Communication Systems, Ltd., JAPAN
+ *  Copyright (C) 2011-2015 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
+ *  Copyright (C) 2011-2014 by Renesas Electronics Corporation, JAPAN
+ *  Copyright (C) 2011-2015 by Sunny Giken Inc., JAPAN
+ *  Copyright (C) 2011-2015 by TOSHIBA CORPORATION, JAPAN
+ *  Copyright (C) 2011-2015 by Witz Corporation
+ *  Copyright (C) 2014-2015 by AISIN COMCRUISE Co., Ltd., JAPAN
+ *  Copyright (C) 2014-2015 by eSOL Co.,Ltd., JAPAN
+ *  Copyright (C) 2014-2015 by SCSK Corporation, JAPAN
+ *
+ *  上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
+ *  ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
+ *  変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
+ *  (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
+ *      権表示，この利用条件および下記の無保証規定が，そのままの形でソー
+ *      スコード中に含まれていること．
+ *  (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
+ *      用できる形で再配布する場合には，再配布に伴うドキュメント（利用
+ *      者マニュアルなど）に，上記の著作権表示，この利用条件および下記
+ *      の無保証規定を掲載すること．
+ *  (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
+ *      用できない形で再配布する場合には，次のいずれかの条件を満たすこ
+ *      と．
+ *    (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
+ *        作権表示，この利用条件および下記の無保証規定を掲載すること．
+ *    (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
+ *        報告すること．
+ *  (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
+ *      害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
+ *      また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
+ *      由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
+ *      免責すること．
+ *
+ *  本ソフトウェアは，AUTOSAR（AUTomotive Open System ARchitecture）仕
+ *  様に基づいている．上記の許諾は，AUTOSARの知的財産権を許諾するもので
+ *  はない．AUTOSARは，AUTOSAR仕様に基づいたソフトウェアを商用目的で利
+ *  用する者に対して，AUTOSARパートナーになることを求めている．
+ *
+ *  本ソフトウェアは，無保証で提供されているものである．上記著作権者お
+ *  よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
+ *  に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
+ *  アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
+ *  の責任を負わない．
+ *
+ *  $Id: target_test.h 1801 2015-03-27 06:34:43Z t_ishikawa $
+ */
+
+/*
+ *		テストプログラムのターゲット依存定義（NIOS2_DEV用）
+ */
+
+#ifndef TOPPERS_TARGET_TEST_H
+#define TOPPERS_TARGET_TEST_H
+
+/*
+ *  sample1で使用する例外
+ */
+#define RAISE_CPU_EXCEPTION	Asm("div zero, zero, zero")
+
+/*
+ *  sample1で使用するアラームの周期（約1秒）
+ */
+#define COUNTER_MIN_CYCLE	((uint32) 60000000)
+
+#ifndef TOPPERS_MACRO_ONLY
+
+extern void trigger_hwcounter_SmpC1ISR(void);
+extern void c1isr_syslog(void);
+
+#endif /* TOPPERS_MACRO_ONLY */
+
+#endif /* TOPPERS_TARGET_TEST_H */
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_test.yaml
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_test.yaml	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_test.yaml	(revision 295)
@@ -0,0 +1,64 @@
+#
+#  TOPPERS ATK2
+#      Toyohashi Open Platform for Embedded Real-Time Systems
+#      Automotive Kernel Version 2
+#
+#  Copyright (C) 2013-2015 by Center for Embedded Computing Systems
+#              Graduate School of Information Science, Nagoya Univ., JAPAN
+#  Copyright (C) 2013-2015 by FUJI SOFT INCORPORATED, JAPAN
+#  Copyright (C) 2013-2015 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
+#  Copyright (C) 2013-2014 by Renesas Electronics Corporation, JAPAN
+#  Copyright (C) 2013-2015 by Sunny Giken Inc., JAPAN
+#  Copyright (C) 2013-2015 by TOSHIBA CORPORATION, JAPAN
+#  Copyright (C) 2013-2015 by Witz Corporation
+#  Copyright (C) 2014-2015 by AISIN COMCRUISE Co., Ltd., JAPAN
+#  Copyright (C) 2014-2015 by eSOL Co.,Ltd., JAPAN
+#  Copyright (C) 2014-2015 by NEC Communication Systems, Ltd., JAPAN
+#  Copyright (C) 2014-2015 by SCSK Corporation, JAPAN
+#
+#  上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
+#  ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
+#  変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
+#  (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
+#      権表示，この利用条件および下記の無保証規定が，そのままの形でソー
+#      スコード中に含まれていること．
+#  (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
+#      用できる形で再配布する場合には，再配布に伴うドキュメント（利用
+#      者マニュアルなど）に，上記の著作権表示，この利用条件および下記
+#      の無保証規定を掲載すること．
+#  (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
+#      用できない形で再配布する場合には，次のいずれかの条件を満たすこ
+#      と．
+#    (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
+#        作権表示，この利用条件および下記の無保証規定を掲載すること．
+#    (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
+#        報告すること．
+#  (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
+#      害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
+#      また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
+#      由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
+#      免責すること．
+#
+#  本ソフトウェアは，AUTOSAR（AUTomotive Open System ARchitecture）仕
+#  様に基づいている．上記の許諾は，AUTOSARの知的財産権を許諾するもので
+#  はない．AUTOSARは，AUTOSAR仕様に基づいたソフトウェアを商用目的で利
+#  用する者に対して，AUTOSARパートナーになることを求めている．
+#
+#  本ソフトウェアは，無保証で提供されているものである．上記著作権者お
+#  よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
+#  に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
+#  アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
+#  の責任を負わない．
+#
+#  $Id: target_test.yaml 1801 2015-03-27 06:34:43Z t_ishikawa $
+#
+
+Ecuc:
+  Os:
+    OsInclude:
+      OsIncludeFileName: target_test.h
+    SmpC1ISR:
+      DefinitionRef: OsIsr
+      OsIsrInterruptNumber: TIMER_5_IRQ
+      OsIsrInterruptPriority: 8
+      OsIsrCategory: CATEGORY_1
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_timer.arxml
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_timer.arxml	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_timer.arxml	(revision 295)
@@ -0,0 +1,29 @@
+<?xml version="1.0" encoding="EUC-JP"?>
+<!-- Generated by ABREX Ver. 1.0.0 -->
+<AUTOSAR xmlns="http://autosar.org/schema/r4.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://autosar.org/schema/r4.0 AUTOSAR_4-0-3_STRICT.xsd">
+	<AR-PACKAGES>
+		<AR-PACKAGE>
+			<SHORT-NAME>Ecuc</SHORT-NAME>
+			<ELEMENTS>
+				<ECUC-MODULE-CONFIGURATION-VALUES>
+					<SHORT-NAME>Os</SHORT-NAME>
+					<DEFINITION-REF DEST="ECUC-MODULE-DEF">/AUTOSAR/EcucDefs/Os</DEFINITION-REF>
+					<ECUC-DEF-EDITION>4.2.0</ECUC-DEF-EDITION>
+					<IMPLEMENTATION-CONFIG-VARIANT>VARIANT-PRE-COMPILE</IMPLEMENTATION-CONFIG-VARIANT>
+					<CONTAINERS>
+						<ECUC-CONTAINER-VALUE>
+							<SHORT-NAME>OsInclude</SHORT-NAME>
+							<DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/AUTOSAR/EcucDefs/Os/OsInclude</DEFINITION-REF>
+							<PARAMETER-VALUES>
+								<ECUC-TEXTUAL-PARAM-VALUE>
+									<DEFINITION-REF DEST="ECUC-STRING-PARAM-DEF">/AUTOSAR/EcucDefs/Os/OsInclude/OsIncludeFileName</DEFINITION-REF>
+									<VALUE>target_timer.h</VALUE>
+								</ECUC-TEXTUAL-PARAM-VALUE>
+							</PARAMETER-VALUES>
+						</ECUC-CONTAINER-VALUE>
+					</CONTAINERS>
+				</ECUC-MODULE-CONFIGURATION-VALUES>
+			</ELEMENTS>
+		</AR-PACKAGE>
+	</AR-PACKAGES>
+</AUTOSAR>
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_timer.h
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_timer.h	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_timer.h	(revision 295)
@@ -0,0 +1,107 @@
+/*
+ *  TOPPERS ATK2
+ *      Toyohashi Open Platform for Embedded Real-Time Systems
+ *      Automotive Kernel Version 2
+ *
+ *  Copyright (C) 2008-2015 by Center for Embedded Computing Systems
+ *              Graduate School of Information Science, Nagoya Univ., JAPAN
+ *  Copyright (C) 2011-2015 by FUJI SOFT INCORPORATED, JAPAN
+ *  Copyright (C) 2011-2013 by Spansion LLC, USA
+ *  Copyright (C) 2011-2015 by NEC Communication Systems, Ltd., JAPAN
+ *  Copyright (C) 2011-2015 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
+ *  Copyright (C) 2011-2014 by Renesas Electronics Corporation, JAPAN
+ *  Copyright (C) 2011-2015 by Sunny Giken Inc., JAPAN
+ *  Copyright (C) 2011-2015 by TOSHIBA CORPORATION, JAPAN
+ *  Copyright (C) 2011-2015 by Witz Corporation
+ *  Copyright (C) 2014-2015 by AISIN COMCRUISE Co., Ltd., JAPAN
+ *  Copyright (C) 2014-2015 by eSOL Co.,Ltd., JAPAN
+ *  Copyright (C) 2014-2015 by SCSK Corporation, JAPAN
+ *
+ *  上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
+ *  ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
+ *  変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
+ *  (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
+ *      権表示，この利用条件および下記の無保証規定が，そのままの形でソー
+ *      スコード中に含まれていること．
+ *  (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
+ *      用できる形で再配布する場合には，再配布に伴うドキュメント（利用
+ *      者マニュアルなど）に，上記の著作権表示，この利用条件および下記
+ *      の無保証規定を掲載すること．
+ *  (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
+ *      用できない形で再配布する場合には，次のいずれかの条件を満たすこ
+ *      と．
+ *    (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
+ *        作権表示，この利用条件および下記の無保証規定を掲載すること．
+ *    (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
+ *        報告すること．
+ *  (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
+ *      害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
+ *      また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
+ *      由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
+ *      免責すること．
+ *
+ *  本ソフトウェアは，AUTOSAR（AUTomotive Open System ARchitecture）仕
+ *  様に基づいている．上記の許諾は，AUTOSARの知的財産権を許諾するもので
+ *  はない．AUTOSARは，AUTOSAR仕様に基づいたソフトウェアを商用目的で利
+ *  用する者に対して，AUTOSARパートナーになることを求めている．
+ *
+ *  本ソフトウェアは，無保証で提供されているものである．上記著作権者お
+ *  よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
+ *  に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
+ *  アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
+ *  の責任を負わない．
+ *
+ *  $Id: target_timer.h 1801 2015-03-27 06:34:43Z t_ishikawa $
+ */
+
+/*
+ *		タイマドライバ
+ */
+
+#ifndef TOPPERS_TARGET_TIMER_H
+#define TOPPERS_TARGET_TIMER_H
+
+#include "nios2_system.h"
+
+/*
+ *  タイマ割込みハンドラ登録のための定数
+ */
+#define INTNO_TIMER		(SYS_CLK_TIMER_INT) /* 割込み番号 */
+#define INTPRI_TIMER	5                   /* 割込み優先度 */
+
+/*
+ *  プロセッサ依存部で定義する
+ */
+#include "nios2_gcc/avalon_timer.h"
+
+/*
+ *  キャッシュパージ(性能評価用)
+ */
+LOCAL_INLINE void
+cache_flash(void)
+{
+	Asm("movui r5, 4096");
+	Asm("ichache_loop:");
+	Asm("initi r5");
+	Asm("addi r5, r5, -32");
+	Asm("bgt r5, zero, ichache_loop");
+}
+
+/*
+ *  100ナノ秒単位で性能測定する
+ *  (MEASURE_100_NANOをdefineする)
+ */
+#ifdef MEASURE_100_NANO
+#define HIST_GET_TIM(p_time)	*p_time = (HISTTIM) get_tim_100ntime()
+#endif /* MEASURE_100_NANO */
+
+/*
+ *  性能評価前にキャッシュパージとタイマ初期化を行う
+ */
+#define HIST_BM_HOOK()			   \
+	do {						   \
+		cache_flash();			   \
+		target_timer_initialize(); \
+	} while (0)
+
+#endif /* TOPPERS_TARGET_TIMER_H */
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_timer.yaml
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_timer.yaml	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_timer.yaml	(revision 295)
@@ -0,0 +1,59 @@
+#
+#  TOPPERS ATK2
+#      Toyohashi Open Platform for Embedded Real-Time Systems
+#      Automotive Kernel Version 2
+#
+#  Copyright (C) 2013-2015 by Center for Embedded Computing Systems
+#              Graduate School of Information Science, Nagoya Univ., JAPAN
+#  Copyright (C) 2013-2015 by FUJI SOFT INCORPORATED, JAPAN
+#  Copyright (C) 2013-2015 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
+#  Copyright (C) 2013-2014 by Renesas Electronics Corporation, JAPAN
+#  Copyright (C) 2013-2015 by Sunny Giken Inc., JAPAN
+#  Copyright (C) 2013-2015 by TOSHIBA CORPORATION, JAPAN
+#  Copyright (C) 2013-2015 by Witz Corporation
+#  Copyright (C) 2014-2015 by AISIN COMCRUISE Co., Ltd., JAPAN
+#  Copyright (C) 2014-2015 by eSOL Co.,Ltd., JAPAN
+#  Copyright (C) 2014-2015 by NEC Communication Systems, Ltd., JAPAN
+#  Copyright (C) 2014-2015 by SCSK Corporation, JAPAN
+#
+#  上記著作権者は，以下の(1)〜(4)の条件を満たす場合に限り，本ソフトウェ
+#  ア（本ソフトウェアを改変したものを含む．以下同じ）を使用・複製・改
+#  変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
+#  (1) 本ソフトウェアをソースコードの形で利用する場合には，上記の著作
+#      権表示，この利用条件および下記の無保証規定が，そのままの形でソー
+#      スコード中に含まれていること．
+#  (2) 本ソフトウェアを，ライブラリ形式など，他のソフトウェア開発に使
+#      用できる形で再配布する場合には，再配布に伴うドキュメント（利用
+#      者マニュアルなど）に，上記の著作権表示，この利用条件および下記
+#      の無保証規定を掲載すること．
+#  (3) 本ソフトウェアを，機器に組み込むなど，他のソフトウェア開発に使
+#      用できない形で再配布する場合には，次のいずれかの条件を満たすこ
+#      と．
+#    (a) 再配布に伴うドキュメント（利用者マニュアルなど）に，上記の著
+#        作権表示，この利用条件および下記の無保証規定を掲載すること．
+#    (b) 再配布の形態を，別に定める方法によって，TOPPERSプロジェクトに
+#        報告すること．
+#  (4) 本ソフトウェアの利用により直接的または間接的に生じるいかなる損
+#      害からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
+#      また，本ソフトウェアのユーザまたはエンドユーザからのいかなる理
+#      由に基づく請求からも，上記著作権者およびTOPPERSプロジェクトを
+#      免責すること．
+#
+#  本ソフトウェアは，AUTOSAR（AUTomotive Open System ARchitecture）仕
+#  様に基づいている．上記の許諾は，AUTOSARの知的財産権を許諾するもので
+#  はない．AUTOSARは，AUTOSAR仕様に基づいたソフトウェアを商用目的で利
+#  用する者に対して，AUTOSARパートナーになることを求めている．
+#
+#  本ソフトウェアは，無保証で提供されているものである．上記著作権者お
+#  よびTOPPERSプロジェクトは，本ソフトウェアに関して，特定の使用目的
+#  に対する適合性も含めて，いかなる保証も行わない．また，本ソフトウェ
+#  アの利用により直接的または間接的に生じたいかなる損害に関しても，そ
+#  の責任を負わない．
+#
+#  $Id: target_timer.yaml 1801 2015-03-27 06:34:43Z t_ishikawa $
+#
+
+Ecuc:
+  Os:
+    OsInclude:
+      OsIncludeFileName: target_timer.h
Index: /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_user.txt
===================================================================
--- /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_user.txt	(revision 295)
+++ /rc_os_nios2/trunk/atk2-sc1_1.3.2/target/nios2_dev_gcc/target_user.txt	(revision 295)
@@ -0,0 +1,540 @@
+
+		TOPPERS/ATK2-SC1
+        ＜Nios2_Devターゲット依存部マニュアル＞
+
+このドキュメントはNios2_Devターゲット依存部の情報を記述したものである．
+
+----------------------------------------------------------------------
+TOPPERS ATK2
+    Toyohashi Open Platform for Embedded Real-Time Systems
+    Automotive Kernel Version 2
+
+Copyright (C) 2011-2015 by Center for Embedded Computing Systems
+            Graduate School of Information Science, Nagoya Univ., JAPAN
+Copyright (C) 2011-2015 by FUJI SOFT INCORPORATED, JAPAN
+Copyright (C) 2011-2013 by Spansion LLC, USA
+Copyright (C) 2011-2015 by NEC Communication Systems, Ltd., JAPAN
+Copyright (C) 2011-2015 by Panasonic Advanced Technology Development Co., Ltd., JAPAN
+Copyright (C) 2011-2014 by Renesas Electronics Corporation, JAPAN
+Copyright (C) 2011-2015 by Sunny Giken Inc., JAPAN
+Copyright (C) 2011-2015 by TOSHIBA CORPORATION, JAPAN
+Copyright (C) 2011-2015 by Witz Corporation
+Copyright (C) 2014-2015 by AISIN COMCRUISE Co., Ltd., JAPAN
+Copyright (C) 2014-2015 by eSOL Co.,Ltd., JAPAN
+Copyright (C) 2014-2015 by SCSK Corporation, JAPAN
+
+上記著作権者は，以下の (1)〜(3)の条件を満たす場合に限り，本ドキュメ
+ント（本ドキュメントを改変したものを含む．以下同じ）を使用・複製・改
+変・再配布（以下，利用と呼ぶ）することを無償で許諾する．
+(1) 本ドキュメントを利用する場合には，上記の著作権表示，この利用条件
+    および下記の無保証規定が，そのままの形でドキュメント中に含まれて
+    いること．
+(2) 本ドキュメントを改変する場合には，ドキュメントを改変した旨の記述
+    を，改変後のドキュメント中に含めること．ただし，改変後のドキュメ
+    ントが，TOPPERSプロジェクト指定の開発成果物である場合には，この限
+    りではない．
+(3) 本ドキュメントの利用により直接的または間接的に生じるいかなる損害
+    からも，上記著作権者およびTOPPERSプロジェクトを免責すること．また，
+    本ドキュメントのユーザまたはエンドユーザからのいかなる理由に基づ
+    く請求からも，上記著作権者およびTOPPERSプロジェクトを免責すること．
+
+本ドキュメントは，AUTOSAR（AUTomotive Open System ARchitecture）仕様
+に基づいている．上記の許諾は，AUTOSARの知的財産権を許諾するものではな
+い．AUTOSARは，AUTOSAR仕様に基づいたソフトウェアを商用目的で利用する
+者に対して，AUTOSARパートナーになることを求めている．
+
+本ドキュメントは，無保証で提供されているものである．上記著作権者およ
+びTOPPERSプロジェクトは，本ドキュメントに関して，特定の使用目的に対す
+る適合性も含めて，いかなる保証も行わない．また，本ドキュメントの利用
+により直接的または間接的に生じたいかなる損害に関しても，その責任を負
+わない．
+
+$Id: target_user.txt 1801 2015-03-27 06:34:43Z t_ishikawa $
+----------------------------------------------------------------------
+○概要
+
+Nios2_Devターゲット依存部（Nios2_Dev依存部）は，Altera社のNios2プロセ
+ッサを搭載した評価ボードをサポートしている．標準では，Altera社製の以下
+のターゲットボードをサポートしている．
+
+  ・Nios2 Cyclone IV 開発，教育用キット(NIOS2_DEV_DE2_115)
+  ・Nios2 開発キット Stratix プロフェッショナルエディション
+    (NIOS2_DEV_2S180)
+
+本依存部をベースとして，メモリマップやデバイスのベースアドレスや割込み
+番号を変更することにより，他のターゲットボードを容易にサポートすること
+が可能である．
+
+○開発環境と動作確認バージョン
+
+動作確認を行った開発環境は次の通りである．
+
+・Nios2 Cyclone IV 開発，教育用キット(NIOS2_DEV_DE2_115)
+  ・QuartusII    : 11.0sp1
+  ・GCC          : 4.1.2
+
+QuartusII は次のURLからダウンロードできる（ユーザ登録が必要）．
+	https://www.altera.com/jp/download/dnl-index.jsp
+	※11.0sp1を選択してダウンロード可能
+	※Cyclone IV E Familyをインストールする
+
+QuartusII をインストールすると，GCCなどの開発ツールもインストールされ，
+FPGAのコンフィギュレーションファイル(sofファイル)などを作成できる．sof
+ファイルの作成方法については，後述の「FPGAコンフィギュレーションファイ
+ル(sofファイル)の作成方法」を参照のこと．
+
+なお，QuartusII ウェブ・エディションでは使用範囲に制限があるが，ATK2カー
+ネルを動作可能であることを確認している．
+
+○ ターゲット定義事項の規定
+
+● データ型に関する規定
+
+ターゲット依存のデータ型のサイズは次の通り．
+	void *			32ビット
+	sintptr			32ビット
+	uintptr			32ビット
+	char8			8ビット
+	uint8			8ビット
+	sint8			8ビット
+	uint16			16ビット
+	sint16			16ビット
+	uint32			32ビット
+	sint32			32ビット
+	uint64			64ビット
+	sint64			64ビット
+	float32			32ビット
+	float64			64ビット
+
+● 割込み処理に関する規定
+    ・割込み優先度の段階数（TNUM_INTPRIの値），その設定方法
+        デフォルトでは，TNUM_INTPRI=64としている．（prc.tf）
+        変更する場合は，prc.tfでTMIN_INTPRI定義を修正する．
+
+    ・制限事項と拡張（ターゲット定義で使用できる割込み属性）サポートし
+        ない
+        
+    ・デフォルトの割込みハンドラ（default_int_handler）の有無と処理内容
+        prc_user.txtの「未登録の割込み」を参照
+
+● C1ISRの割込みに関する規定
+	・prc_user.txtの「C1ISRの扱い」を参照
+
+● CPU例外処理に関する規定
+	・カーネル内のCPU例外出入口処理で起こる可能性のあるCPU例外
+        CPUアドレスエラー
+
+● 性能評価用システム時刻の参照に関する規定
+	・get_tim_utimeのサポートの有無，その制限事項
+        サポート
+
+● その他
+    ・その他の制限事項
+    ・その他の拡張機能
+
+○ カーネルの起動／終了処理に関する情報
+	・用意しているスタートアップモジュールの処理内容
+	  ハードウェアバージョンの確認
+	  avalonタイマーの起動
+	・スタートアップモジュールからhardware_init_hookを呼び出している
+	  場合，hardware_init_hookを呼出すときにメモリのBSS領域はまだ
+	  クリアしていないので，BSS領域変数のデフォルト値を使用できない．
+	  スタック(sp)及びグローバルポインタ（gp）は使用出来る
+
+○ メモリマップ
+    ・デフォルトのメモリマップ，その変更方法
+      メモリマップ詳細に関しては，リンカースクリプトnios2_dev_2s180.ld，
+      nios2_dev_de2_115.ld，nios2_dev_2s180_sdram.ldを参照
+
+○ タイマドライバ関連の情報
+    ・タイムティックの周期，その変更方法
+        デフォルトでは，1[msec]周期に定義されている．
+	    変更するには，マクロTIMER_CLOCKの定義を変更すること．
+	      定義場所：nios2_system.h
+        
+    ・使用するリソース（タイマ）
+        SYS_CLK_TIMER_BASEを使用している．
+
+	・タイマ割込みの割込み優先度の変更方法
+	    マクロINTPRI_TIMERの定義を変更する．
+	    デフォルトではINTPRI_TIMER=5としている．
+	      定義場所：target/nios2_dev_gcc/target_timer.h
+
+○ シリアルインタフェースドライバの情報
+    ・使用するリソース（SIOコントローラ）として JTAG UART か UART かを
+	  選択できる．デフォルトは JTAG UART を選択している．
+
+	・UARTを用いる場合の通信パラメータ
+	    ・ボーレート：115200bps
+	    ・ビット数：8ビット
+	    ・パリティの有無：なし
+	    ・ストップビット：1
+
+○ シリアルインタフェースの選択方法
+
+Nios2 依存部で使うシリアルインタフェースとして， JTAG UART と UART の
+どちらを使うかは Makefile.target にある SERIAL_UART マクロを以下のよう
+に編集することで選択できる．
+
+	・JTAG UART を使う場合（デフォルト）
+		SERIAL_UART = false
+	・UART を使う場合
+		SERIAL_UART = true
+
+○ nios2_dev_de2_115のシリアルポート
+
+nios2_dev_de2_115では，UARTは3つのポートから1つを選択できる．デフォル
+トはポート1となっているが，以下のようにベースアドレスと割込み番号を変
+更することで，別のポートを使うことができる．
+
+	・ポート1（JP5, デフォルト）
+	  ベースアドレス：0x02000d00
+	  割込み番号：3
+	・ポート2（JP5）
+	  ベースアドレス：0x02000d40
+	  割込み番号：4
+	・ポート3（J6, RS-232）
+	  ベースアドレス：0x08000440
+	  割込み番号：7
+
+ポート1とポート2については，次のようにJP5ピンに接続する．ポート1とポー
+ト2の信号レベルは3.3Vで，動作確認はOLIMEX社のUSB-SERIAL-CABLE-Fを使用
+している．括弧内の色は，USB-SERIAL-CABLE-Fのケーブルの色を示している．
+
+	・ポート1（デフォルト）
+	  Rx （緑）：Ａ
+	  Tx （赤）：Ｂ
+	  GND（青）：Ｃ
+	・ポート2
+	  Rx （緑）：Ｄ
+	  Tx （赤）：Ｅ
+	  GND（青）：Ｆ
+
+	・JP5ピンの接続
+	 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 ９ ７ ５ ３ １
+	--------------------------------------------------------------
+	|・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Ｅ Ｂ |
+	|・ ・ ・ ・ ・ Ｆ ・ ・ ・ ・ ・ ・ ・ ・ Ｃ ・ ・ ・ Ｄ Ａ |
+	--------------------------------------------------------------
+	                       【↓JP8側↓】
+
+○ システム構築手順
+
+    ユーザーズマニュアルの「クイックスタートガイド」を参照
+
+○FPGAコンフィギュレーションファイル(sofファイル)の作成方法
+
+NIOS2_DEV_DE2_115の場合について，FPGAコンフィギュレーションファイル
+(sofファイル)の作成方法を説明する．必要なファイル群は以下の通りである．
+
+  ・NIOS2_DEV_DE2_115に付属のSYSTEM CDの
+    DE2_115_demonstrations/DE2_115_NIOS_DEVICE_LED ディレクトリ
+  ・sopcファイル
+    target/nios2_dev_gcc/fpga_design/DE2_115_SOPC.sopc
+     ・Altera DE2_115 Development and Education Board 
+       (NIOS2_DEV_DE2_115) 用ファイル
+  ・パッチファイル
+    target/nios2_dev_gcc/fpga_design/de2_115_patch_for_atk2.diff
+  ・sysverディレクトリ
+    arch/nios2_gcc/sysver/
+  ・cancディレクトリ
+    target/nios2_dev_gcc/fpga_design/canc
+
+※cancディレクトリにはOpenCores canプロジェクトのIPを基にNIOS2_Devターゲット
+で使用できるように修正した．canプロジェクトのライセンスはLGPL v2.1となって
+いる．OpenCoresについてはcanc/hdl/README.txtファイルを参照．
+
+DE2_115_NIOS_DEVICE_LED ディレクトリ内に，その他のファイルを置く．ディ
+レクトリ構造は次のようになる．DE2_115_SOPC.sopcファイルについては，既
+存のファイルがあるので上書きする．
+
+  DE2_115_NIOS_DEVICE_LED/
+  	sysver/						arch/nios2_gcc/からコピー
+  	canc/						target/nios2_dev_gcc/fpga_design/からコピー
+  	*/							SYSTEM CDからコピーしたディレクトリ
+  	de2_115_patch_for_atk2.diff	target/nios2_dev_gcc/fpga_design/からコピー
+  	DE2_115_SOPC.sopc			target/nios2_dev_gcc/fpga_design/からコピー
+  	*							SYSTEM CDからコピーしたファイル
+
+次に，DE2_115_NIOS_DEVICE_LED.qsf ファイルと DE2_115_NIOS_DEVICE_LED.v 
+ファイルにパッチを当てる．DE2_115_NIOS_DEVICE_LED ディレクトリで以下の
+コマンドを実行することでパッチを当てることができる．
+
+	% patch -p1 < de2_115_patch_for_atk2.diff
+
+最後に，Nios II XX Command Shell (XXはバージョン) を使い，
+DE2_115_NIOS_DEVICE_LED ディレクトリで以下のコマンドを実行すると，ATK2
+カーネルが動作するsofファイルが生成される．
+
+	% sopc_builder --generate
+	% quartus_cmd DE2_115_NIOS_DEVICE_LED.qpf -c DE2_115_NIOS_DEVICE_LED.qpf
+
+sofファイルの名前は，インストールしたQuartusIIのエディションによって以
+下の名前になる．
+
+  ・ウェブ・エディション
+    DE2_115_NIOS_DEVICE_LED_time_limited.sof
+  ・サブスクリプション・エディション
+    DE2_115_NIOS_DEVICE_LED.sof
+
+QuartusIIに含まれるProgrammerによって，sofファイルを使用してFPGAのハー
+ドウェアを構成する．
+
+
+○ビルド方法
+
+ビルド時には，ターゲットボードを指定する必要がある．具体的には，
+Makefile.target にあるBOARDマクロを以下のいずれかに設定する．
+
+  ・nios2_dev_de2_115
+    ・Nios2 Cyclone IV 開発，教育用キット
+      (NIOS2_DEV_DE2_115) 指定．
+  ・nios2_dev_2c180
+    ・Nios2 開発キット Stratix プロフェッショナルエディション
+     (NIOS2_DEV_2S180) 指定．
+
+○実行方法
+
+●コンソール
+
+文字出力を JTAG UART により出力するため，文字出力用のコンソールを開き，
+コンソールで以下のコマンドを実行する．UARTを用いる場合は，不要である．
+
+nios2-terminal.exe --cable=USB-Blaster
+
+●gdbサーバー
+
+gdbサーバーを実行する．新しいコンソールを開き，次のコマンド
+を実行する．[port]はポート番号で，1234以上を指定する．
+
+nios2-gdb-server.exe -r --cable=USB-Blaster --tcpport=[port]
+
+●gdb
+
+デバッグ用のgdbを起動する．デバッグ用のコンソールを開き，ビルドしたデ
+ィレクトリに移動して，次のコマンドを実行する．
+
+nios2-elf-gdb atk2-sc1.exe
+
+まず，gdbのコマンドラインで，次のコマンドを実行して gdbサーバーに接続
+する
+
+(gdb)target remote localhost:[port]
+Remote debugging using localhost:[port]
+0x00000000 in ?? ()
+(gdb)
+
+ファイルをロードする．
+
+(gdb)load
+
+ロードを終了した後，実行を開始する．
+
+(gdb)continue
+
+●Makefileによる実行
+
+上記の実機の実行は，make により実行できる．用意されているコマンドは次
+の通りである．
+
+ ・make run
+   ・FPGAによる実行．
+
+ ・make db
+   ・FPGAによるデバッグ
+   ・ターミナルとgdb-serverとgdbを起動する．
+   ※make dbは，ターゲット依存部に用意しているgdb.iniを使用しているの
+     で，デバッグ環境に合わせて（ポート番号など）変更しても良い．
+
+○ HWバージョンのチェック
+
+Nios2はFPGA向けのプロセッサであるため，ハードウェア構成を容易に変更す
+ることが可能である．そのため，動作確認を行ったハードウェアのバージョン
+を起動時にチェックする．
+
+ハードウェアのバージョンは，sysverと呼ばれるペリフェラルによって管理す
+る．sysverには，以下の8個のレジスタが用意されており，そのうち，3個のレ
+ジスタをバージョン管理に用いる．
+
+・SYSVER_MAJOR_VAR : メジャーバージョン
+・SYSVER_MINOR_VAR : マイナーバージョン
+・SYSVER_NUM_CORE  : コア数
+
+ハードウェアを変更して，以前のソフトウェアがそのままでは動作しない場合
+には，メジャーバージョンをアップする．ソフトウェアの変更が必要ないバー
+ジョンアップの場合は，マイナーバージョンを上げることとする．
+
+○ 他のターゲットボードへの移植
+
+サポートしているターゲットボード以外のターゲットボードをサポートするた
+めには，以下の項目を設定する必要がある．
+
+●コンパイルオプションとCライブラリ（Makefile.target）
+
+Nios2 にハードウェア除算器等やを追加して，カーネルでこれらを使用するよ
+うにコンパイルするためには，COPTSにコンパイルオプションを指定する必要が
+ある．
+
+●タイマ関連
+
+◎ベースアドレス（nios2_system.h）
+
+#define  SYS_CLK_TIMER_BASE xxx
+
+◎タイマクロック（nios2_system.h）
+
+タイマ値の内部表現とミリ秒単位との変換を指定する．
+
+#define TIMER_CLOCK     xxxx
+
+◎割込み関連（nios2_system.h）
+
+#define SYS_CLK_TIMER_INT   xxx
+
+●シリアルインタフェース関連
+
+Nios2 依存部のシリアルインタフェースドライバは，1ポートをサポートして
+おり，JTAG UART もしくは UART を用いる．
+
+◎コンパイル/リンク指定（Makefile.target）
+
+Makefile.target の SERIAL_UART マクロにより，jtag_uart.o もしくは 
+uart.o が SYSMOD_COBJS に追加される． SERIAL_UART マクロについては，
+「シリアルインタフェースの選択方法」を参照のこと．
+
+◎ベースアドレス（nios2_system.h）
+
+・JTAG UART の場合
+  #define JTAG_UART_PORT1_BASE xxx
+・UART の場合
+  #define UART_PORT1_BASE      xxx
+
+◎割込み番号（nios2_system.h）
+
+・JTAG UART の場合
+  #define JTAG_UART_PORT1_INT  xxx
+・UART の場合
+  #define UART_PORT1_INT       xxx
+
+●カーネル低レベル出力用UART関連
+
+カーネル低レベル出力用UARTは，上記のシリアルインタフェースを用いる．
+
+●リンカスクリプト（Makefile.target）
+
+ターゲット依存部部でリンカスクリプトを用意して，Makefile.target で，
+LDSCRIPT に指定する．
+
+●ベクタ割込みコントローラベースアドレスの定義（nios2_system.h）
+
+#define VIC_BASE   xx
+
+●ベクタ割込み最大数の定義（nios2_system.h）
+
+#define VIC_INT_NUM   xx
+
+●キャッシュサイズ（nios2_system.h）
+
+インストラクションキャッシュとデータキャッシュのサイズとラインサイズを
+指定する．
+
+#define NIOS2_ICACHE_SIZE       xxx  /* 命令キャッシュサイズ         */
+#define NIOS2_ICACHE_LINE_SIZE  xxx  /* 命令キャッシュラインサイズ   */
+#define NIOS2_DCACHE_SIZE       xxx  /* データキャッシュサイズ       */
+#define NIOS2_DCACHE_LINE_SIZE  xxx  /* データキャッシュラインサイズ */
+
+●システムバージョンレジスタ(sysver)
+
+#define SYSVER_BASE  xxx /* ベースアドレス */
+#define TNUM_HWCORE  1   /* コア数 */
+#define MAJOR_VAR    xxx /* メジャーバージョン */
+
+○ ハードウェアカウンタ
+・de2_115で動作確認した．
+・1個のカウンタに2つのタイマを使用している．
+	差分タイマ：目的の時間を設定する時の現在時間(現在値タイマ)と次の満
+	了時間との相対時間をカウントすることで目的の絶対時間に満了したこと
+	とする.
+		count mode:count down once
+	現在値タイマ：カウンタ周期分のベースタイマを実現(絶対時間をカウント)
+		count mode:continuous count down
+・de2_115で使用できるカウンタ(コンフィギュレーション時指定できるカウン
+  タ名と割込み番号)情報
+  (1)カウンタ名：MAIN_HW_COUNTER
+		差分タイマ：TIMER_0_IRQ    （16）
+		現在値タイマ：TIMER_1_IRQ    （17）
+		1ティック当たりの秒数：1/TIMER_CLOCK_HZ (※)
+
+  (2)カウンタ名：SUB_HW_COUNTER1
+		差分タイマ：TIMER_2_IRQ    （18）
+		現在値タイマ：TIMER_3_IRQ    （19）
+		1ティック当たりの秒数：1/TIMER_CLOCK_HZ (※)
+
+  (3)カウンタ名：SUB_HW_COUNTER2
+		差分タイマ：TIMER_4_IRQ    （20）
+		現在値タイマ：TIMER_5_IRQ    （21）
+		1ティック当たりの秒数：1/TIMER_CLOCK_HZ (※)
+
+	※TIMER_CLOCK_HZはボード毎に定義される
+
+○割込みコントローラ
+・sample1.arxmlでC1ISRのサンプルを使用する場合，
+  (1)sample1.arxmlコンフィギュレーションファイルに，target_test.arxml
+    をインクルードする．
+  (2)../configure -T nios2_dev_gcc -U target_test.o の様に，Makefileに
+     target_test.oを追加する．
+  (3)MakefileでAPPL_ASMOBJS = SmpC1ISR.oを設定する
+
+○その他注意点
+テストなどの目的で，OS終了後StartOS()の呼出し元（main関数）に戻りたい
+場合，ENABLE_RETURN_MAINマクロを定義することで，実現できる．現状の実装
+では，カーネルテスト時に1つのバイナリで複数回OSを起動する機能をOSで実
+現したい要望を満たしている．
+
+
+○変更履歴
+
+2015/03/30
+・トレースログを有効化する設定をターゲット依存部のMakefileから
+　削除
+・sample1のために，target_test.hで，sample1で使用するハードウェア
+　カウンタから約1秒でアラームを起動するために，約1秒に相当する
+　ハードウェアカウンタのティック値をCOUNTER_MIN_CYCLEマクロに定義
+・タイマカウンタにセットする値を実際のティック値-1に修正
+
+2014/02/19
+・fpga_design/canc
+  ・cancディレクトリをarchから移動．
+・de2_115_patch_for_atk2.diff
+  ・cancを追加したdiffファイルに更新．
+・FPGAコンフィギュレーションファイル(sofファイル)の作成方法を更新．
+
+2014/01/23
+・target_test.c|h|cfg|arxml
+  ・ハードウェアカウンタに関する実装をtarget_hw_counter.c|h|cfg|arxmlへ移動
+
+2014/01/10
+・静的APIファイルを削除
+
+2013/10/11
+・target_config.c
+  ・OS起動前に参照される変数の初期化対応
+
+2013/06/28
+・target_config.c
+  ・target_exit() で target_timer_terminate() を呼び出さないよう変更．
+
+2013/03/29
+	・MISRAルール対応により，一部ソースコードを修正した
+
+	・Nios2において，UARTのボーレートを変更可能に修正した
+		- UART_BAUDRATEマクロにより変更可能（target_serial.h参照）
+
+	・その他の修正．
+		- ソースコード上のコメント修正
+		- Nios2において，テスト用タイマの周波数が間違っていたので修正した
+
+2013/01/31
+	一般向けのリリース
+
+以上．
Index: /rc_os_nios2/trunk/sbxbt_ps3_140113.patch
===================================================================
--- /rc_os_nios2/trunk/sbxbt_ps3_140113.patch	(revision 295)
+++ /rc_os_nios2/trunk/sbxbt_ps3_140113.patch	(revision 295)
@@ -0,0 +1,44 @@
+diff -r sbxbt_ps3_140113_org/btstack/config.h sbxbt_ps3_140113/btstack/config.h
+4,6c4,6
+< #define	ENABLE_LOG_DEBUG
+< #define	ENABLE_LOG_INFO
+< #define	ENABLE_LOG_ERROR
+---
+> //#define	ENABLE_LOG_DEBUG
+> //#define	ENABLE_LOG_INFO
+> //#define	ENABLE_LOG_ERROR
+diff -r sbxbt_ps3_140113_org/Common/uart1.c sbxbt_ps3_140113/Common/uart1.c
+78c78
+< #define	RXBUFSIZ			16
+---
+> #define	RXBUFSIZ			16*100
+diff -r sbxbt_ps3_140113_org/global.h sbxbt_ps3_140113/global.h
+30c30
+< 	#define BAUDRATE1				2400		//UART1{[[g
+---
+> 	#define BAUDRATE1				115200		//UART1{[[g
+117,120c117,128
+< // Configure U1RX - put on pin 3 (RP23)
+< #define	u1rx_setup()		(RPINR18bits.U1RXR = 23)
+< // Configure U1TX - put on pin 2 (RP22)
+< #define u1tx_setup()		(RPOR11bits.RP22R = 3)
+---
+> //// Configure U1RX - put on pin 3 (RP23)
+> //#define	u1rx_setup()		(RPINR18bits.U1RXR = 23)
+> 
+> // Configure U1RX - put on pin 22(PGFC1) (RP1)  board pin 5
+> #define	u1rx_setup()		(RPINR18bits.U1RXR = 1)
+> 
+> //// Configure U1TX - put on pin 2 (RP22)
+> //#define u1tx_setup()		(RPOR11bits.RP22R = 3)
+> 
+> // Configure U1TX - put on pin 21(PGFD1) (RP0)  board pin 4
+> #define u1tx_setup()		(RPOR0bits.RP0R = 3)
+> 
+diff -r sbxbt_ps3_140113_org/main.c sbxbt_ps3_140113/main.c
+44c44
+< char							lineBuffer[50];
+---
+> char							lineBuffer[50*10];
+sbxbt_ps3_140113/output ã®ã¿ã«å­å¨: sbxbt_ps3.map
+sbxbt_ps3_140113 ã®ã¿ã«å­å¨: PS3-um-2.pdf
