[101] | 1 | /*
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| 2 | * TOPPERS ECHONET Lite Communication Middleware
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| 3 | *
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| 4 | * Copyright (C) 2014 Cores Co., Ltd. Japan
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| 5 | *
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| 6 | * ãLì ÒÍCȺÌ(1)`(4)Ìðð½·êÉÀèC{\tgEF
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| 7 | * Ai{\tgEFAðüϵ½àÌðÜÞDȺ¯¶jðgpE¡»Eü
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| 8 | * ÏEÄzziȺCpÆÄÔj·é±Æð³Åø·éD
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| 9 | * (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
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| 10 | * \¦C±Ìpð¨æѺL̳ÛØKèªC»ÌÜÜÌ`Å\[
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| 11 | * XR[hÉÜÜêÄ¢é±ÆD
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| 12 | * (2) {\tgEFAðCCu`®ÈÇC¼Ì\tgEFAJÉg
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| 13 | * pÅ«é`ÅÄzz·éêÉÍCÄzzɺ¤hL
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| 14 | gip
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| 15 | * Ò}j
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| 16 | AÈÇjÉCãLÌì \¦C±Ìpð¨æѺL
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| 17 | * ̳ÛØKèðfÚ·é±ÆD
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| 18 | * (3) {\tgEFAðC@íÉgÝÞÈÇC¼Ì\tgEFAJÉg
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| 19 | * pÅ«È¢`ÅÄzz·éêÉÍCÌ¢¸ê©Ìðð½·±
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| 20 | * ÆD
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| 21 | * (a) Äzzɺ¤hL
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| 22 | gipÒ}j
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| 23 | AÈÇjÉCãLÌ
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| 24 | * ì \¦C±Ìpð¨æѺL̳ÛØKèðfÚ·é±ÆD
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| 25 | * (b) ÄzzÌ`ÔðCÊÉèßéû@ÉæÁÄCTOPPERSvWFNgÉ
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| 26 | * ñ·é±ÆD
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| 27 | * (4) {\tgEFAÌpÉæè¼ÚIܽÍÔÚIɶ¶é¢©Èé¹
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| 28 | * Q©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆD
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| 29 | * ܽC{\tgEFAÌ[UܽÍGh[U©çÌ¢©Èé
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| 30 | * RÉîÿ©çàCãLì Ò¨æÑTOPPERSvWFNgð
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| 31 | * ÆÓ·é±ÆD
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| 32 | *
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| 33 | * {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì Ò¨
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| 34 | * æÑTOPPERSvWFNgÍC{\tgEFAÉÖµÄCÁèÌgpÚI
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| 35 | * ÉηéK«àÜßÄC¢©ÈéÛØàsíÈ¢DܽC{\tgEF
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| 36 | * AÌpÉæè¼ÚIܽÍÔÚIɶ¶½¢©Èé¹QÉÖµÄàC»
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| 37 | * ÌÓCðíÈ¢D
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| 38 | *
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| 39 | * @(#) $Id: data_flash.c 101 2015-06-02 15:37:23Z coas-nagasima $
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| 40 | */
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| 41 |
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| 42 | /*
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| 43 | * TvvO(1)Ì{Ì
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| 44 | */
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| 45 |
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| 46 | #include <kernel.h>
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| 47 | #include <t_syslog.h>
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| 48 | #include <sil.h>
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| 49 | #include "data_flash.h"
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| 50 | #ifdef __RX
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| 51 | #include "rx630_ccrx/rx630.h"
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| 52 | #else
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| 53 | #include "rx630_msvc/rx630.h"
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| 54 | #endif
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| 55 | #include "grsakura.h"
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| 56 |
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| 57 | #define FLASH_FWEPROR_ADDR ( ( volatile uint8_t __evenaccess * )0x0008C296 )
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| 58 |
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| 59 | #define FLASH_FMODR_ADDR ( ( volatile uint8_t __evenaccess * )0x007FC402 )
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| 60 | #define FLASH_FMODR_FRDMD_BIT ( 0x01U << 4U )
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| 61 |
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| 62 | #define FLASH_DFLRE0_ADDR ( ( volatile uint16_t __evenaccess * )0x007FC440 )
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| 63 | #define FLASH_DFLRE1_ADDR ( ( volatile uint16_t __evenaccess * )0x007FC442 )
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| 64 | #define FLASH_DFLWE0_ADDR ( ( volatile uint16_t __evenaccess * )0x007FC450 )
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| 65 | #define FLASH_DFLWE1_ADDR ( ( volatile uint16_t __evenaccess * )0x007FC452 )
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| 66 | #define FLASH_FCURAME_ADDR ( ( volatile uint16_t __evenaccess * )0x007FC454 )
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| 67 |
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| 68 | #define FLASH_FASTAT_ADDR ( ( volatile uint8_t __evenaccess * )0x007FC410 )
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| 69 | #define FLASH_FASTAT_DFLWPE_BIT ( 0x01U << 0 )
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| 70 | #define FLASH_FASTAT_DFLRPE_BIT ( 0x01U << 1 )
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| 71 | #define FLASH_FASTAT_DFLAE_BIT ( 0x01U << 3 )
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| 72 | #define FLASH_FASTAT_CMDLK_BIT ( 0x01U << 4 )
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| 73 | #define FLASH_FASTAT_ROMAE_BIT ( 0x01U << 7 )
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| 74 |
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| 75 | #define FLASH_FENTRYR_ADDR ( ( volatile uint16_t __evenaccess * )0x007FFFB2 )
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| 76 | #define FLASH_FENTRYR_FENRTY0_BIT ( 0x0001U << 0U )
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| 77 | #define FLASH_FENTRYR_FENRTY1_BIT ( 0x0001U << 1U )
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| 78 | #define FLASH_FENTRYR_FENRTY2_BIT ( 0x0001U << 2U )
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| 79 | #define FLASH_FENTRYR_FENRTY3_BIT ( 0x0001U << 3U )
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| 80 | #define FLASH_FENTRYR_FENTRYD_BIT ( 0x0001U << 7U )
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| 81 |
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| 82 | #define FLASH_FRESETR_ADDR ( ( volatile uint16_t __evenaccess * )0x007FFFB6 )
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| 83 | #define FLASH_FRESETR_FRESET_BIT ( 0x0001U << 0 )
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| 84 |
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| 85 | #define FLASH_DFLBCCNT_ADDR ( ( volatile uint16_t __evenaccess * )0x007FFFCA )
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| 86 | #define FLASH_DFLBCCNT_BCSIZE_BIT ( 0x0001U << 15U )
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| 87 | #define FLASH_DFLBCCNT_BCADR_OFFSET ( 0U )
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| 88 | #define FLASH_DFLBCCNT_BCADR_MASK ( 0x7FFU << FLASH_DFLBCCNT_BCADR_OFFSET )
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| 89 |
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| 90 | #define FLASH_DFLBCSTAT_ADDR ( ( volatile uint16_t __evenaccess * )0x007FFFCE )
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| 91 | #define FLASH_DFLBCSTAT_BCST_BIT ( 0x0001U << 0U )
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| 92 |
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| 93 | #define FLASH_FSTATR0_ADDR ( ( volatile uint8_t __evenaccess * )0x007FFFB0 )
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| 94 | #define FLASH_FSTATR0_PRGSPD_BIT ( 0x01U << 0 )
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| 95 | #define FLASH_FSTATR0_ERSSPD_BIT ( 0x01U << 1 )
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| 96 | #define FLASH_FSTATR0_SUSRDY_BIT ( 0x01U << 3 )
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| 97 | #define FLASH_FSTATR0_PRGERR_BIT ( 0x01U << 4 )
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| 98 | #define FLASH_FSTATR0_ERSERR_BIT ( 0x01U << 5 )
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| 99 | #define FLASH_FSTATR0_ILGLERR_BIT ( 0x01U << 6 )
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| 100 | #define FLASH_FSTATR0_FRDY_BIT ( 0x01U << 7 )
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| 101 |
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| 102 | #define FLASH_PCKAR_ADDR ( ( volatile uint16_t __evenaccess * )0x007FFFE8 )
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| 103 |
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| 104 | #define DATA_FLASH_BLOCK_SIZE 32
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| 105 | #ifndef _MSC_VER
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| 106 | #define DATA_FLASH_BASE_ADDR 0x00100000
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| 107 | #define FCU_FIRMWARE_ADDR 0xFEFFE000
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| 108 | #define FCU_RAM_ADDR 0x007F8000
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| 109 | #else
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| 110 | uint8_t DATA_FLASH_BASE_ADDR[DATA_FLASH_BLOCK_SIZE * 1024];
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| 111 | uint8_t FCU_FIRMWARE_ADDR[0x2000];
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| 112 | uint8_t FCU_RAM_ADDR[0x2000];
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| 113 | #endif
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| 114 |
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| 115 | static void fcu_init();
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| 116 | static void fcu_copy_firm();
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| 117 | static bool_t fcu_notify_clock();
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| 118 | static void fcu_read_mode();
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| 119 | static void fcu_pe_mode();
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| 120 | static bool_t fcu_write(int blockno, void *data);
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| 121 | static bool_t fcu_erase(int blockno);
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| 122 | static bool_t fcu_check_blank(int blockno);
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| 123 | static bool_t fcu_check_valid(int blockno);
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| 124 | static bool_t fcu_check_frdy(int tWAIT);
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| 125 | static bool_t fcu_check_error();
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| 126 |
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| 127 | ER data_flash_init()
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| 128 | {
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| 129 | ER ret;
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| 130 |
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| 131 | /* E2f[^tbV
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| 132 | ÌÇÝÝÂ */
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| 133 | sil_wrh_mem(FLASH_DFLRE0_ADDR, 0x2DFF);
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| 134 | sil_wrh_mem(FLASH_DFLRE1_ADDR, 0xD2FF);
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| 135 | /* E2f[^tbV
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| 136 | Ì«ÝÂ */
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| 137 | sil_wrh_mem(FLASH_DFLWE0_ADDR, 0x1EFF);
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| 138 | sil_wrh_mem(FLASH_DFLWE1_ADDR, 0xE1FF);
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| 139 |
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| 140 | /* tE16K = 240ms*/
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| 141 | fcu_check_frdy(240000);
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| 142 |
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| 143 | /* G[mF */
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| 144 | fcu_check_error();
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| 145 |
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| 146 | /* FCUt@[EFAÌRs[ */
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| 147 | fcu_copy_firm();
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| 148 |
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| 149 | /* P/E[hÚs */
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| 150 | fcu_pe_mode();
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| 151 |
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| 152 | /* P/E m[}[hÚs */
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| 153 | *((uint8_t *)DATA_FLASH_BASE_ADDR) = 0xFF;
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| 154 |
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| 155 | /* G[mF */
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| 156 | fcu_check_error();
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| 157 |
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| 158 | /* üÓNbNÊmR}hs */
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| 159 | ret = fcu_notify_clock();
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| 160 |
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| 161 | /* [h[hÚs */
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| 162 | fcu_read_mode();
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| 163 |
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| 164 | return ret ? E_OK : E_SYS;
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| 165 | }
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| 166 |
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| 167 | ER data_flash_read(int blockno, void *data)
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| 168 | {
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| 169 | uint16_t *wa, *end;
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| 170 | uint16_t *dst = (uint16_t *)data;
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| 171 |
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| 172 | /* P/E[hÚs */
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| 173 | fcu_pe_mode();
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| 174 |
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| 175 | /* Løf[^`FbN */
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| 176 | if(!fcu_check_valid(blockno)){
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| 177 | /* [h[hÚs */
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| 178 | fcu_read_mode();
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| 179 | return E_OBJ;
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| 180 | }
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| 181 |
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| 182 | /* [h[hÚs */
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| 183 | fcu_read_mode();
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| 184 |
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| 185 | wa = (uint16_t *)(DATA_FLASH_BLOCK_SIZE * blockno + (intptr_t)DATA_FLASH_BASE_ADDR);
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| 186 | end = &wa[DATA_FLASH_BLOCK_SIZE/sizeof(uint16_t)];
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| 187 |
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| 188 | /* ÇÝoµ */
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| 189 | for(; wa < end; wa++, dst++){
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| 190 | *dst = *wa;
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| 191 | }
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| 192 |
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| 193 | return E_OK;
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| 194 | }
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| 195 |
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| 196 | ER data_flash_write(int blockno, void *data)
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| 197 | {
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| 198 | bool_t ret = true;
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| 199 |
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| 200 | /* P/E[hÚs */
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| 201 | fcu_pe_mode();
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| 202 |
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| 203 | /* uN`FbN */
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| 204 | if(!fcu_check_blank(blockno)){
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| 205 | /* uNÅÈ¢ÈçubNÁ */
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| 206 | ret = fcu_erase(blockno);
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| 207 | if(!ret)
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| 208 | syslog(LOG_DEBUG, "fcu_erase() result = %d", ret);
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| 209 | }
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| 210 |
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| 211 | if(ret){
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| 212 | /* «Ý */
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| 213 | ret = fcu_write(blockno, data);
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| 214 | if(!ret)
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| 215 | syslog(LOG_DEBUG, "fcu_write() result = %d", ret);
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| 216 | }
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| 217 |
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| 218 | /* [h[hÚs */
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| 219 | fcu_read_mode();
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| 220 |
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| 221 | return ret ? E_OK : E_SYS;
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| 222 | }
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| 223 |
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| 224 | static void fcu_copy_firm()
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| 225 | {
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| 226 | unsigned int *src, *dst, *end;
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| 227 |
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| 228 | /* [h[hÚs */
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| 229 | if(sil_reh_mem(FLASH_FENTRYR_ADDR) != 0)
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| 230 | sil_wrh_mem(FLASH_FENTRYR_ADDR, 0xAA00);
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| 231 |
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| 232 | /* FCU RAMANZXÂ */
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| 233 | sil_wrh_mem(FLASH_FCURAME_ADDR, 0xC401);
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| 234 |
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| 235 | /* FCUt@[EFAðFCU RAMÉRs[ */
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| 236 | src = (unsigned int *)FCU_FIRMWARE_ADDR;
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| 237 | dst = (unsigned int *)FCU_RAM_ADDR;
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| 238 | end = &dst[0x2000 / sizeof(unsigned int)];
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| 239 | for(; dst < end; dst++, src++)
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| 240 | *dst = *src;
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| 241 | }
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| 242 |
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| 243 | static bool_t fcu_notify_clock()
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| 244 | {
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| 245 | volatile uint8_t *ra;
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| 246 | volatile uint16_t *wa;
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| 247 |
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| 248 | ra = (volatile uint8_t *)(DATA_FLASH_BASE_ADDR);
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| 249 | wa = (volatile uint16_t *)ra;
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| 250 |
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| 251 | /* ügðÝè */
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| 252 | sil_wrh_mem(FLASH_PCKAR_ADDR, 48/*FREQ_PCLK / 1000*/);
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| 253 |
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| 254 | /* üÓNbNÊmR}hs */
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| 255 | *ra = 0xE9;
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| 256 | *ra = 0x03;
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| 257 | *wa = 0x0F0F;
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| 258 | *wa = 0x0F0F;
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| 259 | *wa = 0x0F0F;
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| 260 | *ra = 0xD0;
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| 261 |
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| 262 | /* 120Ês */
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| 263 | fcu_check_frdy(120);
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| 264 |
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| 265 | /* G[mF */
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| 266 | return !fcu_check_error();
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| 267 | }
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| 268 |
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| 269 | /*
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| 270 | * [h[hÚs
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| 271 | */
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| 272 | static void fcu_read_mode()
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| 273 | {
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| 274 | int i;
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| 275 |
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| 276 | for(;;){
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| 277 | for(i = 0; i < 1000; i++){
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| 278 | sil_wrh_mem(FLASH_FENTRYR_ADDR, 0xAA00);
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| 279 |
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| 280 | if(sil_reh_mem(FLASH_FENTRYR_ADDR) != 0)
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| 281 | continue;
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| 282 |
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| 283 | sil_wrb_mem(FLASH_FWEPROR_ADDR, 0x02);
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| 284 | return;
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| 285 | }
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| 286 |
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| 287 | syslog(LOG_WARNING, "fcu_read_mode");
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| 288 | }
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| 289 | }
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| 290 |
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| 291 | /*
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| 292 | * P/E[hÚs
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| 293 | */
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| 294 | static void fcu_pe_mode()
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| 295 | {
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| 296 | sil_wrh_mem(FLASH_FENTRYR_ADDR, 0xAA80);
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| 297 | sil_wrb_mem(FLASH_FWEPROR_ADDR, 0x01);
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| 298 | }
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| 299 |
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| 300 | static bool_t fcu_write(int blockno, void *data)
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| 301 | {
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| 302 | volatile uint8_t *ra;
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| 303 | volatile uint16_t *wa, *end;
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| 304 | uint16_t *src = (uint16_t *)data;
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| 305 |
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| 306 | ra = (volatile uint8_t *)(DATA_FLASH_BLOCK_SIZE * blockno + (intptr_t)DATA_FLASH_BASE_ADDR);
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| 307 | end = (volatile uint16_t *)(((intptr_t)ra) + DATA_FLASH_BLOCK_SIZE);
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| 308 |
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| 309 | for(wa = (volatile uint16_t *)ra; wa < end; wa++, src++)
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| 310 | {
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| 311 | /* vOR}hs */
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| 312 | *ra = 0xE8;
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| 313 | *ra = 0x01;
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| 314 | *wa = *src;
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| 315 | *ra = 0xD0;
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| 316 |
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| 317 | /* 2ms~1.1 */
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| 318 | fcu_check_frdy(2200);
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| 319 |
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| 320 | /* G[mF */
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| 321 | if(fcu_check_error())
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| 322 | return false;
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| 323 | }
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| 324 |
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| 325 | return true;
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| 326 | }
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| 327 |
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| 328 | static bool_t fcu_erase(int blockno)
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| 329 | {
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| 330 | volatile uint8_t *ra;
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| 331 |
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| 332 | ra = (volatile uint8_t *)(DATA_FLASH_BLOCK_SIZE * blockno + (intptr_t)DATA_FLASH_BASE_ADDR);
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| 333 |
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| 334 | /* C[XR}hs */
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| 335 | *ra = 0x20;
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| 336 | *ra = 0xD0;
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| 337 |
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| 338 | /* 20ms~1.1 */
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| 339 | fcu_check_frdy(22000);
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| 340 |
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| 341 | /* G[mF */
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| 342 | return !fcu_check_error();
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| 343 | }
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| 344 |
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| 345 | static bool_t fcu_check_blank(int blockno)
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| 346 | {
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| 347 | volatile uint8_t *ra;
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| 348 | volatile uint16_t *wa, *end;
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| 349 |
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| 350 | sil_wrb_mem(FLASH_FMODR_ADDR, sil_reb_mem(FLASH_FMODR_ADDR) | FLASH_FMODR_FRDMD_BIT);
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| 351 |
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| 352 | wa = (volatile uint16_t *)(DATA_FLASH_BLOCK_SIZE * blockno + (intptr_t)DATA_FLASH_BASE_ADDR);
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| 353 | end = (volatile uint16_t *)(((intptr_t)wa) + DATA_FLASH_BLOCK_SIZE);
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| 354 |
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| 355 | for(; wa < end; wa++)
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| 356 | {
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| 357 | sil_wrh_mem(FLASH_DFLBCCNT_ADDR, (((intptr_t)wa) & FLASH_DFLBCCNT_BCADR_MASK) << FLASH_DFLBCCNT_BCADR_OFFSET);
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| 358 |
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| 359 | ra = (volatile uint8_t *)wa;
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| 360 | *ra = 0x71;
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| 361 | *ra = 0xD0;
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| 362 |
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| 363 | /* 30Ês~1.1 */
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| 364 | fcu_check_frdy(33);
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| 365 |
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| 366 | /* G[mF */
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| 367 | if(fcu_check_error())
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| 368 | return false;
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| 369 |
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| 370 | /* uNmF */
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| 371 | if((sil_reh_mem(FLASH_DFLBCSTAT_ADDR) & FLASH_DFLBCSTAT_BCST_BIT) != 0)
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| 372 | return false;
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| 373 | }
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| 374 |
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| 375 | return true;
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| 376 | }
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| 377 |
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| 378 | static bool_t fcu_check_valid(int blockno)
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| 379 | {
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| 380 | volatile uint8_t *ra;
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| 381 | volatile uint16_t *wa, *end;
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| 382 |
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| 383 | sil_wrb_mem(FLASH_FMODR_ADDR, sil_reb_mem(FLASH_FMODR_ADDR) | FLASH_FMODR_FRDMD_BIT);
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| 384 |
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| 385 | wa = (volatile uint16_t *)(DATA_FLASH_BLOCK_SIZE * blockno + (intptr_t)DATA_FLASH_BASE_ADDR);
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| 386 | end = (volatile uint16_t *)(((intptr_t)wa) + DATA_FLASH_BLOCK_SIZE);
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| 387 |
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| 388 | for(; wa < end; wa++)
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| 389 | {
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| 390 | sil_wrh_mem(FLASH_DFLBCCNT_ADDR, (((intptr_t)wa) & FLASH_DFLBCCNT_BCADR_MASK) << FLASH_DFLBCCNT_BCADR_OFFSET);
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| 391 |
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| 392 | ra = (volatile uint8_t *)wa;
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| 393 | *ra = 0x71;
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| 394 | *ra = 0xD0;
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| 395 |
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| 396 | /* 30Ês~1.1 */
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| 397 | fcu_check_frdy(33);
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| 398 |
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| 399 | /* G[mF */
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| 400 | if(fcu_check_error())
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| 401 | return false;
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| 402 |
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| 403 | /* uNmF */
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| 404 | if((sil_reh_mem(FLASH_DFLBCSTAT_ADDR) & FLASH_DFLBCSTAT_BCST_BIT) == 0)
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| 405 | return false;
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| 406 | }
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| 407 |
|
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| 408 | return true;
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| 409 | }
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| 410 |
|
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| 411 | static bool_t fcu_check_error()
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| 412 | {
|
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| 413 | uint8_t status;
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| 414 |
|
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| 415 | status = sil_reb_mem(FLASH_FSTATR0_ADDR);
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| 416 |
|
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| 417 | if((status & (FLASH_FSTATR0_ILGLERR_BIT | FLASH_FSTATR0_ERSERR_BIT | FLASH_FSTATR0_PRGERR_BIT)) == 0)
|
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| 418 | return false;
|
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| 419 |
|
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| 420 | if((status & FLASH_FSTATR0_ILGLERR_BIT) != 0){
|
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| 421 | if(sil_reb_mem(FLASH_FASTAT_ADDR) != 0x10){
|
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| 422 | sil_wrb_mem(FLASH_FASTAT_ADDR, 0x10);
|
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| 423 | }
|
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| 424 |
|
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| 425 | /* Xe[^XNAR}hs */
|
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| 426 | *((uint8_t *)DATA_FLASH_BASE_ADDR) = 0x50;
|
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| 427 | }
|
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| 428 |
|
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| 429 | syslog(LOG_WARNING, "fcu_check_error %02x", status);
|
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| 430 |
|
---|
| 431 | return true;
|
---|
| 432 | }
|
---|
| 433 |
|
---|
| 434 | static bool_t fcu_check_frdy(int tWAIT)
|
---|
| 435 | {
|
---|
| 436 | int i, j;
|
---|
| 437 |
|
---|
| 438 | for(i = 0; i < tWAIT; i++){
|
---|
| 439 | /* õ®¹ÈçI¹ */
|
---|
| 440 | if((sil_reb_mem(FLASH_FSTATR0_ADDR) & FLASH_FSTATR0_FRDY_BIT) != 0)
|
---|
| 441 | return true;
|
---|
| 442 |
|
---|
| 443 | /* 1Ês? */
|
---|
| 444 | for(j = 0; j < 100; j++);
|
---|
| 445 | }
|
---|
| 446 |
|
---|
| 447 | syslog(LOG_WARNING, "fcu_check_frdy timeout");
|
---|
| 448 |
|
---|
| 449 | /* FCUú» */
|
---|
| 450 | fcu_init();
|
---|
| 451 |
|
---|
| 452 | return false;
|
---|
| 453 | }
|
---|
| 454 |
|
---|
| 455 | static void fcu_init()
|
---|
| 456 | {
|
---|
| 457 | int j;
|
---|
| 458 |
|
---|
| 459 | sil_wrh_mem(FLASH_FRESETR_ADDR, 0xCC01);
|
---|
| 460 |
|
---|
| 461 | // 200Ês? */
|
---|
| 462 | for(j = 0; j < 20000; j++);
|
---|
| 463 |
|
---|
| 464 | sil_wrh_mem(FLASH_FRESETR_ADDR, 0xCC00);
|
---|
| 465 | }
|
---|