1 | /*
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2 | mcp_can_dfs.h
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3 | 2012 Copyright (c) Seeed Technology Inc. All right reserved.
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4 |
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5 | Author:Loovee
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6 | Contributor: Cory J. Fowler
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7 | 2014-1-16
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8 |
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9 | This library is free software; you can redistribute it and/or
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10 | modify it under the terms of the GNU Lesser General Public
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11 | License as published by the Free Software Foundation; either
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12 | version 2.1 of the License, or (at your option) any later version.
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13 |
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14 | This library is distributed in the hope that it will be useful,
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15 | but WITHOUT ANY WARRANTY; without even the implied warranty of
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16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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17 | Lesser General Public License for more details.
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18 |
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19 | You should have received a copy of the GNU Lesser General Public
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20 | License along with this library; if not, write to the Free Software
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21 | Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-
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22 | 1301 USA
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23 | */
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24 | #ifndef _MCP2515DFS_H_
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25 | #define _MCP2515DFS_H_
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26 |
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27 | #include <Arduino.h>
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28 | #include <SPI.h>
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29 | #include <inttypes.h>
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30 |
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31 | #ifndef INT32U
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32 | #define INT32U unsigned long
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33 | #endif
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34 |
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35 | #ifndef INT8U
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36 | #define INT8U byte
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37 | #endif
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38 |
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39 | // if print debug information
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40 | #define DEBUG_MODE 0
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41 |
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42 | #define MCP_RXB0 0
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43 | #define MCP_RXB1 1
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44 | #define MCP_TXB0 0
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45 | #define MCP_TXB1 1
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46 | #define MCP_TXB2 2
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47 | #define MCP_RXM0 0
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48 | #define MCP_RXM1 1
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49 | #define MCP_RXF0 0
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50 | #define MCP_RXF1 1
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51 | #define MCP_RXF2 2
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52 | #define MCP_RXF3 3
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53 | #define MCP_RXF4 4
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54 | #define MCP_RXF5 5
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55 |
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56 | /*
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57 | * Begin mt
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58 | */
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59 | #define TIMEOUTVALUE 50
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60 | #define MCP_SIDH 0
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61 | #define MCP_SIDL 1
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62 | #define MCP_EID8 2
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63 | #define MCP_EID0 3
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64 |
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65 | #define MCP_TXB_EXIDE_M 0x08 /* In TXBnSIDL */
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66 | #define MCP_DLC_MASK 0x0F /* 4 LSBits */
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67 | #define MCP_RTR_MASK 0x40 /* (1<<6) Bit 6 */
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68 |
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69 | #define MCP_RXB_RX_ANY 0x60
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70 | #define MCP_RXB_RX_EXT 0x40
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71 | #define MCP_RXB_RX_STD 0x20
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72 | #define MCP_RXB_RX_STDEXT 0x00
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73 | #define MCP_RXB_RX_MASK 0x60
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74 | #define MCP_RXB_BUKT_MASK (1<<2)
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75 |
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76 | /*
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77 | ** Bits in the TXBnCTRL registers.
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78 | */
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79 | #define MCP_TXB_TXBUFE_M 0x80
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80 | #define MCP_TXB_ABTF_M 0x40
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81 | #define MCP_TXB_MLOA_M 0x20
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82 | #define MCP_TXB_TXERR_M 0x10
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83 | #define MCP_TXB_TXREQ_M 0x08
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84 | #define MCP_TXB_TXIE_M 0x04
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85 | #define MCP_TXB_TXP10_M 0x03
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86 |
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87 | #define MCP_TXB_RTR_M 0x40 /* In TXBnDLC */
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88 | #define MCP_RXB_IDE_M 0x08 /* In RXBnSIDL */
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89 | #define MCP_RXB_RTR_M 0x40 /* In RXBnDLC */
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90 |
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91 | #define MCP_STAT_RXIF_MASK (0x03)
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92 | #define MCP_STAT_RX0IF (1<<0)
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93 | #define MCP_STAT_RX1IF (1<<1)
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94 |
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95 | #define MCP_STAT_TX0IF (1<<3)
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96 | #define MCP_STAT_TX1IF (1<<5)
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97 | #define MCP_STAT_TX2IF (1<<7)
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98 |
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99 | #define MCP_STAT_TX0REQ (1<<2)
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100 | #define MCP_STAT_TX1REQ (1<<4)
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101 | #define MCP_STAT_TX2REQ (1<<6)
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102 |
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103 | #define MCP_EFLG_RX1OVR (1<<7)
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104 | #define MCP_EFLG_RX0OVR (1<<6)
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105 | #define MCP_EFLG_TXBO (1<<5)
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106 | #define MCP_EFLG_TXEP (1<<4)
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107 | #define MCP_EFLG_RXEP (1<<3)
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108 | #define MCP_EFLG_TXWAR (1<<2)
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109 | #define MCP_EFLG_RXWAR (1<<1)
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110 | #define MCP_EFLG_EWARN (1<<0)
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111 | #define MCP_EFLG_ERRORMASK (0xF8) /* 5 MS-Bits */
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112 |
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113 |
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114 | /*
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115 | * Define MCP2515 register addresses
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116 | */
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117 |
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118 | #define MCP_RXF0SIDH 0x00
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119 | #define MCP_RXF0SIDL 0x01
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120 | #define MCP_RXF0EID8 0x02
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121 | #define MCP_RXF0EID0 0x03
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122 | #define MCP_RXF1SIDH 0x04
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123 | #define MCP_RXF1SIDL 0x05
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124 | #define MCP_RXF1EID8 0x06
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125 | #define MCP_RXF1EID0 0x07
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126 | #define MCP_RXF2SIDH 0x08
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127 | #define MCP_RXF2SIDL 0x09
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128 | #define MCP_RXF2EID8 0x0A
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129 | #define MCP_RXF2EID0 0x0B
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130 | #define MCP_CANSTAT 0x0E
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131 | #define MCP_CANCTRL 0x0F
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132 | #define MCP_RXF3SIDH 0x10
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133 | #define MCP_RXF3SIDL 0x11
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134 | #define MCP_RXF3EID8 0x12
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135 | #define MCP_RXF3EID0 0x13
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136 | #define MCP_RXF4SIDH 0x14
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137 | #define MCP_RXF4SIDL 0x15
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138 | #define MCP_RXF4EID8 0x16
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139 | #define MCP_RXF4EID0 0x17
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140 | #define MCP_RXF5SIDH 0x18
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141 | #define MCP_RXF5SIDL 0x19
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142 | #define MCP_RXF5EID8 0x1A
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143 | #define MCP_RXF5EID0 0x1B
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144 | #define MCP_TEC 0x1C
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145 | #define MCP_REC 0x1D
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146 | #define MCP_RXM0SIDH 0x20
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147 | #define MCP_RXM0SIDL 0x21
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148 | #define MCP_RXM0EID8 0x22
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149 | #define MCP_RXM0EID0 0x23
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150 | #define MCP_RXM1SIDH 0x24
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151 | #define MCP_RXM1SIDL 0x25
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152 | #define MCP_RXM1EID8 0x26
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153 | #define MCP_RXM1EID0 0x27
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154 | #define MCP_CNF3 0x28
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155 | #define MCP_CNF2 0x29
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156 | #define MCP_CNF1 0x2A
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157 | #define MCP_CANINTE 0x2B
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158 | #define MCP_CANINTF 0x2C
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159 | #define MCP_EFLG 0x2D
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160 | #define MCP_TXB0CTRL 0x30
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161 | #define MCP_TXB1CTRL 0x40
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162 | #define MCP_TXB2CTRL 0x50
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163 | #define MCP_RXB0CTRL 0x60
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164 | #define MCP_RXB0SIDH 0x61
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165 | #define MCP_RXB1CTRL 0x70
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166 | #define MCP_RXB1SIDH 0x71
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167 |
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168 |
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169 | #define MCP_TX_INT 0x1C // Enable all transmit interrup ts
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170 | #define MCP_TX01_INT 0x0C // Enable TXB0 and TXB1 interru pts
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171 | #define MCP_RX_INT 0x03 // Enable receive interrupts
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172 | #define MCP_NO_INT 0x00 // Disable all interrupts
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173 |
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174 | #define MCP_TX01_MASK 0x14
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175 | #define MCP_TX_MASK 0x54
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176 |
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177 | /*
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178 | * Define SPI Instruction Set
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179 | */
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180 |
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181 | #define MCP_WRITE 0x02
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182 |
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183 | #define MCP_READ 0x03
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184 |
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185 | #define MCP_BITMOD 0x05
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186 |
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187 | #define MCP_LOAD_TX0 0x40
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188 | #define MCP_LOAD_TX1 0x42
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189 | #define MCP_LOAD_TX2 0x44
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190 |
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191 | #define MCP_RTS_TX0 0x81
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192 | #define MCP_RTS_TX1 0x82
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193 | #define MCP_RTS_TX2 0x84
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194 | #define MCP_RTS_ALL 0x87
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195 |
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196 | #define MCP_READ_RX0 0x90
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197 | #define MCP_READ_RX1 0x94
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198 |
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199 | #define MCP_READ_STATUS 0xA0
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200 |
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201 | #define MCP_RX_STATUS 0xB0
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202 |
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203 | #define MCP_RESET 0xC0
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204 |
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205 |
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206 | /*
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207 | * CANCTRL Register Values
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208 | */
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209 |
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210 | #define MODE_NORMAL 0x00
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211 | #define MODE_SLEEP 0x20
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212 | #define MODE_LOOPBACK 0x40
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213 | #define MODE_LISTENONLY 0x60
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214 | #define MODE_CONFIG 0x80
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215 | #define MODE_POWERUP 0xE0
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216 | #define MODE_MASK 0xE0
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217 | #define ABORT_TX 0x10
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218 | #define MODE_ONESHOT 0x08
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219 | #define CLKOUT_ENABLE 0x04
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220 | #define CLKOUT_DISABLE 0x00
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221 | #define CLKOUT_PS1 0x00
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222 | #define CLKOUT_PS2 0x01
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223 | #define CLKOUT_PS4 0x02
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224 | #define CLKOUT_PS8 0x03
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225 |
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226 |
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227 | /*
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228 | * CNF1 Register Values
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229 | */
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230 |
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231 | #define SJW1 0x00
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232 | #define SJW2 0x40
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233 | #define SJW3 0x80
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234 | #define SJW4 0xC0
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235 |
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236 |
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237 | /*
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238 | * CNF2 Register Values
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239 | */
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240 |
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241 | #define BTLMODE 0x80
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242 | #define SAMPLE_1X 0x00
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243 | #define SAMPLE_3X 0x40
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244 |
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245 |
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246 | /*
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247 | * CNF3 Register Values
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248 | */
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249 |
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250 | #define SOF_ENABLE 0x80
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251 | #define SOF_DISABLE 0x00
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252 | #define WAKFIL_ENABLE 0x40
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253 | #define WAKFIL_DISABLE 0x00
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254 |
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255 |
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256 | /*
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257 | * CANINTF Register Bits
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258 | */
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259 |
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260 | #define MCP_RX0IF 0x01
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261 | #define MCP_RX1IF 0x02
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262 | #define MCP_TX0IF 0x04
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263 | #define MCP_TX1IF 0x08
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264 | #define MCP_TX2IF 0x10
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265 | #define MCP_ERRIF 0x20
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266 | #define MCP_WAKIF 0x40
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267 | #define MCP_MERRF 0x80
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268 |
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269 | /*
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270 | * speed 16M
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271 | */
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272 | #define MCP_16MHz_1000kBPS_CFG1 (0x00)
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273 | #define MCP_16MHz_1000kBPS_CFG2 (0xD0)
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274 | #define MCP_16MHz_1000kBPS_CFG3 (0x82)
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275 |
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276 | #define MCP_16MHz_500kBPS_CFG1 (0x00)
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277 | #define MCP_16MHz_500kBPS_CFG2 (0xF0)
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278 | #define MCP_16MHz_500kBPS_CFG3 (0x86)
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279 |
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280 | #define MCP_16MHz_250kBPS_CFG1 (0x41)
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281 | #define MCP_16MHz_250kBPS_CFG2 (0xF1)
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282 | #define MCP_16MHz_250kBPS_CFG3 (0x85)
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283 |
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284 | #define MCP_16MHz_200kBPS_CFG1 (0x01)
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285 | #define MCP_16MHz_200kBPS_CFG2 (0xFA)
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286 | #define MCP_16MHz_200kBPS_CFG3 (0x87)
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287 |
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288 | #define MCP_16MHz_125kBPS_CFG1 (0x03)
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289 | #define MCP_16MHz_125kBPS_CFG2 (0xF0)
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290 | #define MCP_16MHz_125kBPS_CFG3 (0x86)
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291 |
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292 | #define MCP_16MHz_100kBPS_CFG1 (0x03)
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293 | #define MCP_16MHz_100kBPS_CFG2 (0xFA)
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294 | #define MCP_16MHz_100kBPS_CFG3 (0x87)
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295 |
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296 | /*
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297 | #define MCP_16MHz_100kBPS_CFG1 (0x03)
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298 | #define MCP_16MHz_100kBPS_CFG2 (0xBA)
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299 | #define MCP_16MHz_100kBPS_CFG3 (0x07)
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300 | */
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301 |
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302 | #define MCP_16MHz_95kBPS_CFG1 (0x03)
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303 | #define MCP_16MHz_95kBPS_CFG2 (0xAD)
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304 | #define MCP_16MHz_95kBPS_CFG3 (0x07)
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305 |
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306 | #define MCP_16MHz_83k3BPS_CFG1 (0x03)
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307 | #define MCP_16MHz_83k3BPS_CFG2 (0xBE)
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308 | #define MCP_16MHz_83k3BPS_CFG3 (0x07)
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309 |
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310 | #define MCP_16MHz_80kBPS_CFG1 (0x03)
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311 | #define MCP_16MHz_80kBPS_CFG2 (0xFF)
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312 | #define MCP_16MHz_80kBPS_CFG3 (0x87)
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313 |
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314 | #define MCP_16MHz_50kBPS_CFG1 (0x07)
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315 | #define MCP_16MHz_50kBPS_CFG2 (0xFA)
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316 | #define MCP_16MHz_50kBPS_CFG3 (0x87)
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317 |
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318 | #define MCP_16MHz_40kBPS_CFG1 (0x07)
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319 | #define MCP_16MHz_40kBPS_CFG2 (0xFF)
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320 | #define MCP_16MHz_40kBPS_CFG3 (0x87)
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321 |
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322 | #define MCP_16MHz_33kBPS_CFG1 (0x09)
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323 | #define MCP_16MHz_33kBPS_CFG2 (0xBE)
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324 | #define MCP_16MHz_33kBPS_CFG3 (0x07)
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325 |
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326 | #define MCP_16MHz_31k25BPS_CFG1 (0x0F)
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327 | #define MCP_16MHz_31k25BPS_CFG2 (0xF1)
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328 | #define MCP_16MHz_31k25BPS_CFG3 (0x85)
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329 |
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330 | #define MCP_16MHz_20kBPS_CFG1 (0x0F)
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331 | #define MCP_16MHz_20kBPS_CFG2 (0xFF)
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332 | #define MCP_16MHz_20kBPS_CFG3 (0x87)
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333 |
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334 | #define MCP_16MHz_10kBPS_CFG1 (0x1F)
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335 | #define MCP_16MHz_10kBPS_CFG2 (0xFF)
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336 | #define MCP_16MHz_10kBPS_CFG3 (0x87)
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337 |
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338 | #define MCP_16MHz_5kBPS_CFG1 (0x3F)
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339 | #define MCP_16MHz_5kBPS_CFG2 (0xFF)
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340 | #define MCP_16MHz_5kBPS_CFG3 (0x87)
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341 |
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342 |
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343 |
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344 | #define MCPDEBUG (0)
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345 | #define MCPDEBUG_TXBUF (0)
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346 | #define MCP_N_TXBUFFERS (3)
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347 |
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348 | #define MCP_RXBUF_0 (MCP_RXB0SIDH)
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349 | #define MCP_RXBUF_1 (MCP_RXB1SIDH)
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350 |
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351 | //#define SPICS 10
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352 | #define MCP2515_SELECT() digitalWrite(SPICS, LOW)
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353 | #define MCP2515_UNSELECT() digitalWrite(SPICS, HIGH)
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354 |
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355 | #define MCP2515_OK (0)
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356 | #define MCP2515_FAIL (1)
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357 | #define MCP_ALLTXBUSY (2)
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358 |
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359 | #define CANDEBUG 1
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360 |
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361 | #define CANUSELOOP 0
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362 |
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363 | #define CANSENDTIMEOUT (200) /* milliseconds */
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364 |
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365 | /*
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366 | * initial value of gCANAutoProcess
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367 | */
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368 | #define CANAUTOPROCESS (1)
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369 | #define CANAUTOON (1)
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370 | #define CANAUTOOFF (0)
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371 |
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372 | #define CAN_STDID (0)
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373 | #define CAN_EXTID (1)
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374 |
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375 | #define CANDEFAULTIDENT (0x55CC)
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376 | #define CANDEFAULTIDENTEXT (CAN_EXTID)
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377 |
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378 | #define CAN_5KBPS 1
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379 | #define CAN_10KBPS 2
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380 | #define CAN_20KBPS 3
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381 | #define CAN_31K25BPS 4
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382 | #define CAN_33KBPS 5
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383 | #define CAN_40KBPS 6
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384 | #define CAN_50KBPS 7
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385 | #define CAN_80KBPS 8
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386 | #define CAN_83K3BPS 9
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387 | #define CAN_95KBPS 10
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388 | #define CAN_100KBPS 11
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389 | #define CAN_125KBPS 12
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390 | #define CAN_200KBPS 13
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391 | #define CAN_250KBPS 14
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392 | #define CAN_500KBPS 15
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393 | #define CAN_1000KBPS 16
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394 |
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395 | #define CAN_OK (0)
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396 | #define CAN_FAILINIT (1)
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397 | #define CAN_FAILTX (2)
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398 | #define CAN_MSGAVAIL (3)
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399 | #define CAN_NOMSG (4)
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400 | #define CAN_SENDWAIT (5)
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401 | #define CAN_NOSENDWAIT (6)
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402 | #define CAN_CTRLERROR (7)
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403 | #define CAN_GETTXBFTIMEOUT (8)
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404 | #define CAN_SENDMSGTIMEOUT (9)
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405 | #define CAN_FAIL (0xff)
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406 |
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407 | #define CAN_MAX_CHAR_IN_MESSAGE (8)
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408 |
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409 | #endif
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410 | /*********************************************************************************************************
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411 | END FILE
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412 | *********************************************************************************************************/
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