1 | /**
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2 | * \file
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3 | *
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4 | * \brief Header file for SAMD21J15A
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5 | *
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6 | * Copyright (c) 2014 Atmel Corporation. All rights reserved.
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7 | *
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8 | * \asf_license_start
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9 | *
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10 | * \page License
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11 | *
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12 | * Redistribution and use in source and binary forms, with or without
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13 | * modification, are permitted provided that the following conditions are met:
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14 | *
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15 | * 1. Redistributions of source code must retain the above copyright notice,
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16 | * this list of conditions and the following disclaimer.
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17 | *
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18 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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19 | * this list of conditions and the following disclaimer in the documentation
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20 | * and/or other materials provided with the distribution.
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21 | *
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22 | * 3. The name of Atmel may not be used to endorse or promote products derived
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23 | * from this software without specific prior written permission.
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24 | *
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25 | * 4. This software may only be redistributed and used in connection with an
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26 | * Atmel microcontroller product.
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27 | *
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28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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38 | * POSSIBILITY OF SUCH DAMAGE.
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39 | *
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40 | * \asf_license_stop
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41 | *
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42 | */
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43 |
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44 | #ifndef _SAMD21J15A_
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45 | #define _SAMD21J15A_
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46 |
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47 | /**
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48 | * \ingroup SAMD21_definitions
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49 | * \addtogroup SAMD21J15A_definitions SAMD21J15A definitions
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50 | * This file defines all structures and symbols for SAMD21J15A:
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51 | * - registers and bitfields
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52 | * - peripheral base address
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53 | * - peripheral ID
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54 | * - PIO definitions
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55 | */
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56 | /*@{*/
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57 |
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58 | #ifdef __cplusplus
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59 | extern "C" {
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60 | #endif
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61 |
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62 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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63 | #include <stdint.h>
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64 | #ifndef __cplusplus
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65 | typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
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66 | typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
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67 | typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
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68 | #else
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69 | typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
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70 | typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
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71 | typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
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72 | #endif
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73 | typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
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74 | typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
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75 | typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
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76 | typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
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77 | typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
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78 | typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
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79 | #define CAST(type, value) ((type *)(value))
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80 | #define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
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81 | #else
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82 | #define CAST(type, value) (value)
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83 | #define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
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84 | #endif
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85 |
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86 | /* ************************************************************************** */
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87 | /** CMSIS DEFINITIONS FOR SAMD21J15A */
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88 | /* ************************************************************************** */
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89 | /** \defgroup SAMD21J15A_cmsis CMSIS Definitions */
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90 | /*@{*/
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91 |
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92 | /** Interrupt Number Definition */
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93 | typedef enum IRQn
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94 | {
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95 | /****** Cortex-M0+ Processor Exceptions Numbers *******************************/
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96 | NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
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97 | HardFault_IRQn = -13, /**< 3 Cortex-M0+ Hard Fault Interrupt */
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98 | SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
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99 | PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
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100 | SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
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101 | /****** SAMD21J15A-specific Interrupt Numbers ***********************/
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102 | PM_IRQn = 0, /**< 0 SAMD21J15A Power Manager (PM) */
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103 | SYSCTRL_IRQn = 1, /**< 1 SAMD21J15A System Control (SYSCTRL) */
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104 | WDT_IRQn = 2, /**< 2 SAMD21J15A Watchdog Timer (WDT) */
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105 | RTC_IRQn = 3, /**< 3 SAMD21J15A Real-Time Counter (RTC) */
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106 | EIC_IRQn = 4, /**< 4 SAMD21J15A External Interrupt Controller (EIC) */
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107 | NVMCTRL_IRQn = 5, /**< 5 SAMD21J15A Non-Volatile Memory Controller (NVMCTRL) */
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108 | DMAC_IRQn = 6, /**< 6 SAMD21J15A Direct Memory Access Controller (DMAC) */
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109 | USB_IRQn = 7, /**< 7 SAMD21J15A Universal Serial Bus (USB) */
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110 | EVSYS_IRQn = 8, /**< 8 SAMD21J15A Event System Interface (EVSYS) */
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111 | SERCOM0_IRQn = 9, /**< 9 SAMD21J15A Serial Communication Interface 0 (SERCOM0) */
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112 | SERCOM1_IRQn = 10, /**< 10 SAMD21J15A Serial Communication Interface 1 (SERCOM1) */
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113 | SERCOM2_IRQn = 11, /**< 11 SAMD21J15A Serial Communication Interface 2 (SERCOM2) */
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114 | SERCOM3_IRQn = 12, /**< 12 SAMD21J15A Serial Communication Interface 3 (SERCOM3) */
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115 | SERCOM4_IRQn = 13, /**< 13 SAMD21J15A Serial Communication Interface 4 (SERCOM4) */
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116 | SERCOM5_IRQn = 14, /**< 14 SAMD21J15A Serial Communication Interface 5 (SERCOM5) */
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117 | TCC0_IRQn = 15, /**< 15 SAMD21J15A Timer Counter Control 0 (TCC0) */
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118 | TCC1_IRQn = 16, /**< 16 SAMD21J15A Timer Counter Control 1 (TCC1) */
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119 | TCC2_IRQn = 17, /**< 17 SAMD21J15A Timer Counter Control 2 (TCC2) */
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120 | TC3_IRQn = 18, /**< 18 SAMD21J15A Basic Timer Counter 3 (TC3) */
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121 | TC4_IRQn = 19, /**< 19 SAMD21J15A Basic Timer Counter 4 (TC4) */
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122 | TC5_IRQn = 20, /**< 20 SAMD21J15A Basic Timer Counter 5 (TC5) */
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123 | TC6_IRQn = 21, /**< 21 SAMD21J15A Basic Timer Counter 6 (TC6) */
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124 | TC7_IRQn = 22, /**< 22 SAMD21J15A Basic Timer Counter 7 (TC7) */
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125 | ADC_IRQn = 23, /**< 23 SAMD21J15A Analog Digital Converter (ADC) */
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126 | AC_IRQn = 24, /**< 24 SAMD21J15A Analog Comparators (AC) */
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127 | DAC_IRQn = 25, /**< 25 SAMD21J15A Digital Analog Converter (DAC) */
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128 | PTC_IRQn = 26, /**< 26 SAMD21J15A Peripheral Touch Controller (PTC) */
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129 | I2S_IRQn = 27, /**< 27 SAMD21J15A Inter-IC Sound Interface (I2S) */
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130 |
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131 | PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
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132 | } IRQn_Type;
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133 |
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134 | typedef struct _DeviceVectors
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135 | {
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136 | /* Stack pointer */
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137 | void* pvStack;
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138 |
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139 | /* Cortex-M handlers */
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140 | void* pfnReset_Handler;
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141 | void* pfnNMI_Handler;
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142 | void* pfnHardFault_Handler;
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143 | void* pfnReservedM12;
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144 | void* pfnReservedM11;
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145 | void* pfnReservedM10;
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146 | void* pfnReservedM9;
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147 | void* pfnReservedM8;
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148 | void* pfnReservedM7;
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149 | void* pfnReservedM6;
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150 | void* pfnSVC_Handler;
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151 | void* pfnReservedM4;
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152 | void* pfnReservedM3;
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153 | void* pfnPendSV_Handler;
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154 | void* pfnSysTick_Handler;
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155 |
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156 | /* Peripheral handlers */
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157 | void* pfnPM_Handler; /* 0 Power Manager */
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158 | void* pfnSYSCTRL_Handler; /* 1 System Control */
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159 | void* pfnWDT_Handler; /* 2 Watchdog Timer */
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160 | void* pfnRTC_Handler; /* 3 Real-Time Counter */
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161 | void* pfnEIC_Handler; /* 4 External Interrupt Controller */
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162 | void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
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163 | void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
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164 | void* pfnUSB_Handler; /* 7 Universal Serial Bus */
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165 | void* pfnEVSYS_Handler; /* 8 Event System Interface */
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166 | void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
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167 | void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
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168 | void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
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169 | void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
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170 | void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
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171 | void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
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172 | void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
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173 | void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
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174 | void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
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175 | void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
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176 | void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
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177 | void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
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178 | void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
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179 | void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
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180 | void* pfnADC_Handler; /* 23 Analog Digital Converter */
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181 | void* pfnAC_Handler; /* 24 Analog Comparators */
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182 | void* pfnDAC_Handler; /* 25 Digital Analog Converter */
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183 | void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
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184 | void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
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185 | } DeviceVectors;
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186 |
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187 | /* Cortex-M0+ processor handlers */
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188 | void Reset_Handler ( void );
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189 | void NMI_Handler ( void );
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190 | void HardFault_Handler ( void );
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191 | void SVC_Handler ( void );
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192 | void PendSV_Handler ( void );
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193 | void SysTick_Handler ( void );
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194 |
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195 | /* Peripherals handlers */
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196 | void PM_Handler ( void );
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197 | void SYSCTRL_Handler ( void );
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198 | void WDT_Handler ( void );
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199 | void RTC_Handler ( void );
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200 | void EIC_Handler ( void );
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201 | void NVMCTRL_Handler ( void );
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202 | void DMAC_Handler ( void );
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203 | void USB_Handler ( void );
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204 | void EVSYS_Handler ( void );
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205 | void SERCOM0_Handler ( void );
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206 | void SERCOM1_Handler ( void );
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207 | void SERCOM2_Handler ( void );
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208 | void SERCOM3_Handler ( void );
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209 | void SERCOM4_Handler ( void );
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210 | void SERCOM5_Handler ( void );
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211 | void TCC0_Handler ( void );
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212 | void TCC1_Handler ( void );
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213 | void TCC2_Handler ( void );
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214 | void TC3_Handler ( void );
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215 | void TC4_Handler ( void );
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216 | void TC5_Handler ( void );
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217 | void TC6_Handler ( void );
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218 | void TC7_Handler ( void );
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219 | void ADC_Handler ( void );
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220 | void AC_Handler ( void );
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221 | void DAC_Handler ( void );
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222 | void PTC_Handler ( void );
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223 | void I2S_Handler ( void );
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224 |
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225 | /*
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226 | * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
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227 | */
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228 |
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229 | #define LITTLE_ENDIAN 1
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230 | #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
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231 | #define __MPU_PRESENT 0 /*!< MPU present or not */
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232 | #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
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233 | #define __VTOR_PRESENT 1 /*!< VTOR present or not */
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234 | #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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235 |
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236 | /**
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237 | * \brief CMSIS includes
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238 | */
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239 |
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240 | #include <core_cm0plus.h>
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241 | #if !defined DONT_USE_CMSIS_INIT
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242 | #include "system_samd21.h"
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243 | #endif /* DONT_USE_CMSIS_INIT */
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244 |
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245 | /*@}*/
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246 |
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247 | /* ************************************************************************** */
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248 | /** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J15A */
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249 | /* ************************************************************************** */
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250 | /** \defgroup SAMD21J15A_api Peripheral Software API */
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251 | /*@{*/
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252 |
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253 | #include "component/ac.h"
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254 | #include "component/adc.h"
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255 | #include "component/dac.h"
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256 | #include "component/dmac.h"
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257 | #include "component/dsu.h"
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258 | #include "component/eic.h"
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259 | #include "component/evsys.h"
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260 | #include "component/gclk.h"
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261 | #include "component/i2s.h"
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262 | #include "component/mtb.h"
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263 | #include "component/nvmctrl.h"
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264 | #include "component/pac.h"
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265 | #include "component/pm.h"
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266 | #include "component/port.h"
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267 | #include "component/rtc.h"
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268 | #include "component/sercom.h"
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269 | #include "component/sysctrl.h"
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270 | #include "component/tc.h"
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271 | #include "component/tcc.h"
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272 | #include "component/usb.h"
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273 | #include "component/wdt.h"
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274 | /*@}*/
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275 |
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276 | /* ************************************************************************** */
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277 | /** REGISTERS ACCESS DEFINITIONS FOR SAMD21J15A */
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278 | /* ************************************************************************** */
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279 | /** \defgroup SAMD21J15A_reg Registers Access Definitions */
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280 | /*@{*/
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281 |
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282 | #include "instance/ac.h"
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283 | #include "instance/adc.h"
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284 | #include "instance/dac.h"
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285 | #include "instance/dmac.h"
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286 | #include "instance/dsu.h"
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287 | #include "instance/eic.h"
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288 | #include "instance/evsys.h"
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289 | #include "instance/gclk.h"
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290 | #include "instance/i2s.h"
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291 | #include "instance/mtb.h"
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292 | #include "instance/nvmctrl.h"
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293 | #include "instance/pac0.h"
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294 | #include "instance/pac1.h"
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295 | #include "instance/pac2.h"
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296 | #include "instance/pm.h"
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297 | #include "instance/port.h"
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298 | #include "instance/rtc.h"
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299 | #include "instance/sercom0.h"
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300 | #include "instance/sercom1.h"
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301 | #include "instance/sercom2.h"
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302 | #include "instance/sercom3.h"
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303 | #include "instance/sercom4.h"
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304 | #include "instance/sercom5.h"
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305 | #include "instance/sysctrl.h"
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306 | #include "instance/tc3.h"
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307 | #include "instance/tc4.h"
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308 | #include "instance/tc5.h"
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309 | #include "instance/tc6.h"
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310 | #include "instance/tc7.h"
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311 | #include "instance/tcc0.h"
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312 | #include "instance/tcc1.h"
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313 | #include "instance/tcc2.h"
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314 | #include "instance/usb.h"
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315 | #include "instance/wdt.h"
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316 | /*@}*/
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317 |
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318 | /* ************************************************************************** */
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319 | /** PERIPHERAL ID DEFINITIONS FOR SAMD21J15A */
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320 | /* ************************************************************************** */
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321 | /** \defgroup SAMD21J15A_id Peripheral Ids Definitions */
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322 | /*@{*/
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323 |
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324 | // Peripheral instances on HPB0 bridge
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325 | #define ID_PAC0 0 /**< \brief Peripheral Access Controller PAC (PAC0) */
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326 | #define ID_PM 1 /**< \brief Power Manager (PM) */
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327 | #define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
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328 | #define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
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329 | #define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
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330 | #define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
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331 | #define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
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332 |
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333 | // Peripheral instances on HPB1 bridge
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334 | #define ID_PAC1 32 /**< \brief Peripheral Access Controller PAC (PAC1) */
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335 | #define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
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336 | #define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
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337 | #define ID_PORT 35 /**< \brief Port Module (PORT) */
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338 | #define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
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339 | #define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
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340 | #define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
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341 |
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342 | // Peripheral instances on HPB2 bridge
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343 | #define ID_PAC2 64 /**< \brief Peripheral Access Controller PAC (PAC2) */
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344 | #define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
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345 | #define ID_SERCOM0 66 /**< \brief Serial Communication Interface SERCOM (SERCOM0) */
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346 | #define ID_SERCOM1 67 /**< \brief Serial Communication Interface SERCOM (SERCOM1) */
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347 | #define ID_SERCOM2 68 /**< \brief Serial Communication Interface SERCOM (SERCOM2) */
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348 | #define ID_SERCOM3 69 /**< \brief Serial Communication Interface SERCOM (SERCOM3) */
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349 | #define ID_SERCOM4 70 /**< \brief Serial Communication Interface SERCOM (SERCOM4) */
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350 | #define ID_SERCOM5 71 /**< \brief Serial Communication Interface SERCOM (SERCOM5) */
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351 | #define ID_TCC0 72 /**< \brief Timer Counter Control TCC (TCC0) */
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352 | #define ID_TCC1 73 /**< \brief Timer Counter Control TCC (TCC1) */
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353 | #define ID_TCC2 74 /**< \brief Timer Counter Control TCC (TCC2) */
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354 | #define ID_TC3 75 /**< \brief Basic Timer Counter TC (TC3) */
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355 | #define ID_TC4 76 /**< \brief Basic Timer Counter TC (TC4) */
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356 | #define ID_TC5 77 /**< \brief Basic Timer Counter TC (TC5) */
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357 | #define ID_TC6 78 /**< \brief Basic Timer Counter TC (TC6) */
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358 | #define ID_TC7 79 /**< \brief Basic Timer Counter TC (TC7) */
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359 | #define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
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360 | #define ID_AC 81 /**< \brief Analog Comparators (AC) */
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361 | #define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
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362 | #define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
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363 | #define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
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364 |
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365 | #define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
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366 | /*@}*/
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367 |
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368 | /* ************************************************************************** */
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369 | /** BASE ADDRESS DEFINITIONS FOR SAMD21J15A */
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370 | /* ************************************************************************** */
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371 | /** \defgroup SAMD21J15A_base Peripheral Base Address Definitions */
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372 | /*@{*/
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373 |
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374 | #if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
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375 | #define AC (0x42004400U) /**< \brief (AC) APB Base Address */
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376 | #define ADC (0x42004000U) /**< \brief (ADC) APB Base Address */
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377 | #define DAC (0x42004800U) /**< \brief (DAC) APB Base Address */
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378 | #define DMAC (0x41004800U) /**< \brief (DMAC) APB Base Address */
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379 | #define DSU (0x41002000U) /**< \brief (DSU) APB Base Address */
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380 | #define EIC (0x40001800U) /**< \brief (EIC) APB Base Address */
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381 | #define EVSYS (0x42000400U) /**< \brief (EVSYS) APB Base Address */
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382 | #define GCLK (0x40000C00U) /**< \brief (GCLK) APB Base Address */
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383 | #define I2S (0x42005000U) /**< \brief (I2S) APB Base Address */
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384 | #define MTB (0x41006000U) /**< \brief (MTB) APB Base Address */
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385 | #define NVMCTRL (0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
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386 | #define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
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387 | #define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
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388 | #define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
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389 | #define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
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390 | #define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
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391 | #define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
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392 | #define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
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393 | #define PAC0 (0x40000000U) /**< \brief (PAC0) APB Base Address */
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394 | #define PAC1 (0x41000000U) /**< \brief (PAC1) APB Base Address */
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395 | #define PAC2 (0x42000000U) /**< \brief (PAC2) APB Base Address */
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396 | #define PM (0x40000400U) /**< \brief (PM) APB Base Address */
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397 | #define PORT (0x41004400U) /**< \brief (PORT) APB Base Address */
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398 | #define PORT_IOBUS (0x60000000U) /**< \brief (PORT) IOBUS Base Address */
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399 | #define RTC (0x40001400U) /**< \brief (RTC) APB Base Address */
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400 | #define SERCOM0 (0x42000800U) /**< \brief (SERCOM0) APB Base Address */
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401 | #define SERCOM1 (0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
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402 | #define SERCOM2 (0x42001000U) /**< \brief (SERCOM2) APB Base Address */
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403 | #define SERCOM3 (0x42001400U) /**< \brief (SERCOM3) APB Base Address */
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404 | #define SERCOM4 (0x42001800U) /**< \brief (SERCOM4) APB Base Address */
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405 | #define SERCOM5 (0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
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406 | #define SYSCTRL (0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
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407 | #define TC3 (0x42002C00U) /**< \brief (TC3) APB Base Address */
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408 | #define TC4 (0x42003000U) /**< \brief (TC4) APB Base Address */
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409 | #define TC5 (0x42003400U) /**< \brief (TC5) APB Base Address */
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410 | #define TC6 (0x42003800U) /**< \brief (TC6) APB Base Address */
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411 | #define TC7 (0x42003C00U) /**< \brief (TC7) APB Base Address */
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412 | #define TCC0 (0x42002000U) /**< \brief (TCC0) APB Base Address */
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413 | #define TCC1 (0x42002400U) /**< \brief (TCC1) APB Base Address */
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414 | #define TCC2 (0x42002800U) /**< \brief (TCC2) APB Base Address */
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415 | #define USB (0x41005000U) /**< \brief (USB) APB Base Address */
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416 | #define WDT (0x40001000U) /**< \brief (WDT) APB Base Address */
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417 | #else
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418 | #define AC ((Ac *)0x42004400U) /**< \brief (AC) APB Base Address */
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419 | #define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
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420 | #define AC_INSTS { AC } /**< \brief (AC) Instances List */
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421 |
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422 | #define ADC ((Adc *)0x42004000U) /**< \brief (ADC) APB Base Address */
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423 | #define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
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424 | #define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
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425 |
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426 | #define DAC ((Dac *)0x42004800U) /**< \brief (DAC) APB Base Address */
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427 | #define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
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428 | #define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
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429 |
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430 | #define DMAC ((Dmac *)0x41004800U) /**< \brief (DMAC) APB Base Address */
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431 | #define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
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432 | #define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
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433 |
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434 | #define DSU ((Dsu *)0x41002000U) /**< \brief (DSU) APB Base Address */
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435 | #define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
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436 | #define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
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437 |
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438 | #define EIC ((Eic *)0x40001800U) /**< \brief (EIC) APB Base Address */
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439 | #define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
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440 | #define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
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441 |
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442 | #define EVSYS ((Evsys *)0x42000400U) /**< \brief (EVSYS) APB Base Address */
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443 | #define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
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444 | #define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
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445 |
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446 | #define GCLK ((Gclk *)0x40000C00U) /**< \brief (GCLK) APB Base Address */
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447 | #define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
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448 | #define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
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449 |
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450 | #define I2S ((I2s *)0x42005000U) /**< \brief (I2S) APB Base Address */
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451 | #define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
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452 | #define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
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453 |
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454 | #define MTB ((Mtb *)0x41006000U) /**< \brief (MTB) APB Base Address */
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455 | #define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
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456 | #define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
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457 |
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458 | #define NVMCTRL ((Nvmctrl *)0x41004000U) /**< \brief (NVMCTRL) APB Base Address */
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459 | #define NVMCTRL_CAL (0x00800000U) /**< \brief (NVMCTRL) CAL Base Address */
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460 | #define NVMCTRL_LOCKBIT (0x00802000U) /**< \brief (NVMCTRL) LOCKBIT Base Address */
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461 | #define NVMCTRL_OTP1 (0x00806000U) /**< \brief (NVMCTRL) OTP1 Base Address */
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462 | #define NVMCTRL_OTP2 (0x00806008U) /**< \brief (NVMCTRL) OTP2 Base Address */
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463 | #define NVMCTRL_OTP4 (0x00806020U) /**< \brief (NVMCTRL) OTP4 Base Address */
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464 | #define NVMCTRL_TEMP_LOG (0x00806030U) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
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465 | #define NVMCTRL_USER (0x00804000U) /**< \brief (NVMCTRL) USER Base Address */
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466 | #define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
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467 | #define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
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468 |
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469 | #define PAC0 ((Pac *)0x40000000U) /**< \brief (PAC0) APB Base Address */
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470 | #define PAC1 ((Pac *)0x41000000U) /**< \brief (PAC1) APB Base Address */
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471 | #define PAC2 ((Pac *)0x42000000U) /**< \brief (PAC2) APB Base Address */
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472 | #define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
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473 | #define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
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474 |
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475 | #define PM ((Pm *)0x40000400U) /**< \brief (PM) APB Base Address */
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476 | #define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
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477 | #define PM_INSTS { PM } /**< \brief (PM) Instances List */
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478 |
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479 | #define PORT ((Port *)0x41004400U) /**< \brief (PORT) APB Base Address */
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480 | #define PORT_IOBUS ((Port *)0x60000000U) /**< \brief (PORT) IOBUS Base Address */
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481 | #define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
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482 | #define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
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483 |
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484 | #define PTC_GCLK_ID 34
|
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485 | #define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
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486 | #define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
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487 |
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488 | #define RTC ((Rtc *)0x40001400U) /**< \brief (RTC) APB Base Address */
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489 | #define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
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490 | #define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
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491 |
|
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492 | #define SERCOM0 ((Sercom *)0x42000800U) /**< \brief (SERCOM0) APB Base Address */
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493 | #define SERCOM1 ((Sercom *)0x42000C00U) /**< \brief (SERCOM1) APB Base Address */
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494 | #define SERCOM2 ((Sercom *)0x42001000U) /**< \brief (SERCOM2) APB Base Address */
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---|
495 | #define SERCOM3 ((Sercom *)0x42001400U) /**< \brief (SERCOM3) APB Base Address */
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496 | #define SERCOM4 ((Sercom *)0x42001800U) /**< \brief (SERCOM4) APB Base Address */
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497 | #define SERCOM5 ((Sercom *)0x42001C00U) /**< \brief (SERCOM5) APB Base Address */
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498 | #define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
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499 | #define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
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500 |
|
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501 | #define SYSCTRL ((Sysctrl *)0x40000800U) /**< \brief (SYSCTRL) APB Base Address */
|
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502 | #define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
|
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503 | #define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
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504 |
|
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505 | #define TC3 ((Tc *)0x42002C00U) /**< \brief (TC3) APB Base Address */
|
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506 | #define TC4 ((Tc *)0x42003000U) /**< \brief (TC4) APB Base Address */
|
---|
507 | #define TC5 ((Tc *)0x42003400U) /**< \brief (TC5) APB Base Address */
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508 | #define TC6 ((Tc *)0x42003800U) /**< \brief (TC6) APB Base Address */
|
---|
509 | #define TC7 ((Tc *)0x42003C00U) /**< \brief (TC7) APB Base Address */
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510 | #define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
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511 | #define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
|
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512 |
|
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513 | #define TCC0 ((Tcc *)0x42002000U) /**< \brief (TCC0) APB Base Address */
|
---|
514 | #define TCC1 ((Tcc *)0x42002400U) /**< \brief (TCC1) APB Base Address */
|
---|
515 | #define TCC2 ((Tcc *)0x42002800U) /**< \brief (TCC2) APB Base Address */
|
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516 | #define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
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---|
517 | #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
|
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518 |
|
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519 | #define USB ((Usb *)0x41005000U) /**< \brief (USB) APB Base Address */
|
---|
520 | #define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
|
---|
521 | #define USB_INSTS { USB } /**< \brief (USB) Instances List */
|
---|
522 |
|
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523 | #define WDT ((Wdt *)0x40001000U) /**< \brief (WDT) APB Base Address */
|
---|
524 | #define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
|
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525 | #define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
|
---|
526 |
|
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527 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
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528 | /*@}*/
|
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529 |
|
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530 | /* ************************************************************************** */
|
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531 | /** PORT DEFINITIONS FOR SAMD21J15A */
|
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532 | /* ************************************************************************** */
|
---|
533 | /** \defgroup SAMD21J15A_port PORT Definitions */
|
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534 | /*@{*/
|
---|
535 |
|
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536 | #include "pio/samd21j15a.h"
|
---|
537 | /*@}*/
|
---|
538 |
|
---|
539 | /* ************************************************************************** */
|
---|
540 | /** MEMORY MAPPING DEFINITIONS FOR SAMD21J15A */
|
---|
541 | /* ************************************************************************** */
|
---|
542 |
|
---|
543 | #define FLASH_SIZE 0x8000 /* 32 kB */
|
---|
544 | #define FLASH_PAGE_SIZE 64
|
---|
545 | #define FLASH_NB_OF_PAGES 512
|
---|
546 | #define FLASH_USER_PAGE_SIZE 64
|
---|
547 | #define HMCRAMC0_SIZE 0x1000 /* 4 kB */
|
---|
548 | #define FLASH_ADDR (0x00000000U) /**< FLASH base address */
|
---|
549 | #define FLASH_USER_PAGE_ADDR (0x00800000U) /**< FLASH_USER_PAGE base address */
|
---|
550 | #define HMCRAMC0_ADDR (0x20000000U) /**< HMCRAMC0 base address */
|
---|
551 |
|
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552 | #define DSU_DID_RESETVALUE 0x10010003
|
---|
553 | #define PORT_GROUPS 2
|
---|
554 |
|
---|
555 | /* ************************************************************************** */
|
---|
556 | /** ELECTRICAL DEFINITIONS FOR SAMD21J15A */
|
---|
557 | /* ************************************************************************** */
|
---|
558 |
|
---|
559 |
|
---|
560 | #ifdef __cplusplus
|
---|
561 | }
|
---|
562 | #endif
|
---|
563 |
|
---|
564 | /*@}*/
|
---|
565 |
|
---|
566 | #endif /* SAMD21J15A_H */
|
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