1 | /**
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2 | * \file
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3 | *
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4 | * \brief Instance description for TCC1
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5 | *
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6 | * Copyright (c) 2014 Atmel Corporation. All rights reserved.
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7 | *
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8 | * \asf_license_start
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9 | *
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10 | * \page License
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11 | *
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12 | * Redistribution and use in source and binary forms, with or without
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13 | * modification, are permitted provided that the following conditions are met:
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14 | *
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15 | * 1. Redistributions of source code must retain the above copyright notice,
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16 | * this list of conditions and the following disclaimer.
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17 | *
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18 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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19 | * this list of conditions and the following disclaimer in the documentation
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20 | * and/or other materials provided with the distribution.
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21 | *
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22 | * 3. The name of Atmel may not be used to endorse or promote products derived
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23 | * from this software without specific prior written permission.
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24 | *
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25 | * 4. This software may only be redistributed and used in connection with an
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26 | * Atmel microcontroller product.
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27 | *
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28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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38 | * POSSIBILITY OF SUCH DAMAGE.
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39 | *
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40 | * \asf_license_stop
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41 | *
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42 | */
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43 |
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44 | #ifndef _SAMD21_TCC1_INSTANCE_
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45 | #define _SAMD21_TCC1_INSTANCE_
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46 |
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47 | /* ========== Register definition for TCC1 peripheral ========== */
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48 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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49 | #define REG_TCC1_CTRLA (0x42002400U) /**< \brief (TCC1) Control A */
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50 | #define REG_TCC1_CTRLBCLR (0x42002404U) /**< \brief (TCC1) Control B Clear */
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51 | #define REG_TCC1_CTRLBSET (0x42002405U) /**< \brief (TCC1) Control B Set */
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52 | #define REG_TCC1_SYNCBUSY (0x42002408U) /**< \brief (TCC1) Synchronization Busy */
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53 | #define REG_TCC1_FCTRLA (0x4200240CU) /**< \brief (TCC1) Recoverable FaultA Configuration */
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54 | #define REG_TCC1_FCTRLB (0x42002410U) /**< \brief (TCC1) Recoverable FaultB Configuration */
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55 | #define REG_TCC1_DRVCTRL (0x42002418U) /**< \brief (TCC1) Driver Configuration */
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56 | #define REG_TCC1_DBGCTRL (0x4200241EU) /**< \brief (TCC1) Debug Control */
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57 | #define REG_TCC1_EVCTRL (0x42002420U) /**< \brief (TCC1) Event Control */
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58 | #define REG_TCC1_INTENCLR (0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */
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59 | #define REG_TCC1_INTENSET (0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */
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60 | #define REG_TCC1_INTFLAG (0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */
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61 | #define REG_TCC1_STATUS (0x42002430U) /**< \brief (TCC1) Status */
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62 | #define REG_TCC1_COUNT (0x42002434U) /**< \brief (TCC1) Count */
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63 | #define REG_TCC1_PATT (0x42002438U) /**< \brief (TCC1) Pattern */
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64 | #define REG_TCC1_WAVE (0x4200243CU) /**< \brief (TCC1) Waveform Control */
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65 | #define REG_TCC1_PER (0x42002440U) /**< \brief (TCC1) Period */
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66 | #define REG_TCC1_CC0 (0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */
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67 | #define REG_TCC1_CC1 (0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */
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68 | #define REG_TCC1_PATTB (0x42002464U) /**< \brief (TCC1) Pattern Buffer */
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69 | #define REG_TCC1_WAVEB (0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */
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70 | #define REG_TCC1_PERB (0x4200246CU) /**< \brief (TCC1) Period Buffer */
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71 | #define REG_TCC1_CCB0 (0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */
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72 | #define REG_TCC1_CCB1 (0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */
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73 | #else
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74 | #define REG_TCC1_CTRLA (*(RwReg *)0x42002400U) /**< \brief (TCC1) Control A */
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75 | #define REG_TCC1_CTRLBCLR (*(RwReg8 *)0x42002404U) /**< \brief (TCC1) Control B Clear */
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76 | #define REG_TCC1_CTRLBSET (*(RwReg8 *)0x42002405U) /**< \brief (TCC1) Control B Set */
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77 | #define REG_TCC1_SYNCBUSY (*(RoReg *)0x42002408U) /**< \brief (TCC1) Synchronization Busy */
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78 | #define REG_TCC1_FCTRLA (*(RwReg *)0x4200240CU) /**< \brief (TCC1) Recoverable FaultA Configuration */
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79 | #define REG_TCC1_FCTRLB (*(RwReg *)0x42002410U) /**< \brief (TCC1) Recoverable FaultB Configuration */
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80 | #define REG_TCC1_DRVCTRL (*(RwReg *)0x42002418U) /**< \brief (TCC1) Driver Configuration */
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81 | #define REG_TCC1_DBGCTRL (*(RwReg8 *)0x4200241EU) /**< \brief (TCC1) Debug Control */
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82 | #define REG_TCC1_EVCTRL (*(RwReg *)0x42002420U) /**< \brief (TCC1) Event Control */
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83 | #define REG_TCC1_INTENCLR (*(RwReg *)0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */
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84 | #define REG_TCC1_INTENSET (*(RwReg *)0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */
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85 | #define REG_TCC1_INTFLAG (*(RwReg *)0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */
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86 | #define REG_TCC1_STATUS (*(RwReg *)0x42002430U) /**< \brief (TCC1) Status */
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87 | #define REG_TCC1_COUNT (*(RwReg *)0x42002434U) /**< \brief (TCC1) Count */
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88 | #define REG_TCC1_PATT (*(RwReg16*)0x42002438U) /**< \brief (TCC1) Pattern */
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89 | #define REG_TCC1_WAVE (*(RwReg *)0x4200243CU) /**< \brief (TCC1) Waveform Control */
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90 | #define REG_TCC1_PER (*(RwReg *)0x42002440U) /**< \brief (TCC1) Period */
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91 | #define REG_TCC1_CC0 (*(RwReg *)0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */
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92 | #define REG_TCC1_CC1 (*(RwReg *)0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */
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93 | #define REG_TCC1_PATTB (*(RwReg16*)0x42002464U) /**< \brief (TCC1) Pattern Buffer */
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94 | #define REG_TCC1_WAVEB (*(RwReg *)0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */
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95 | #define REG_TCC1_PERB (*(RwReg *)0x4200246CU) /**< \brief (TCC1) Period Buffer */
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96 | #define REG_TCC1_CCB0 (*(RwReg *)0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */
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97 | #define REG_TCC1_CCB1 (*(RwReg *)0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */
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98 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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99 |
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100 | /* ========== Instance parameters for TCC1 peripheral ========== */
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101 | #define TCC1_CC_NUM 2
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102 | #define TCC1_DITHERING 1
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103 | #define TCC1_DMAC_ID_MC_0 19
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104 | #define TCC1_DMAC_ID_MC_1 20
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105 | #define TCC1_DMAC_ID_MC_LSB 19
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106 | #define TCC1_DMAC_ID_MC_MSB 20
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107 | #define TCC1_DMAC_ID_MC_SIZE 2
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108 | #define TCC1_DMAC_ID_OVF 18
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109 | #define TCC1_DTI 0
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110 | #define TCC1_EXT (TCC1_DITHERING*16+TCC1_PG*8+TCC1_SWAP*4+TCC1_DTI*2+TCC1_OTMX*1)
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111 | #define TCC1_GCLK_ID 26
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112 | #define TCC1_MASTER 1
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113 | #define TCC1_OTMX 0
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114 | #define TCC1_OW_NUM 4
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115 | #define TCC1_PG 1
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116 | #define TCC1_SIZE 24
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117 | #define TCC1_SWAP 0
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118 |
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119 | #endif /* _SAMD21_TCC1_INSTANCE_ */
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