source: rtos_arduino/trunk/arduino_lib/hardware/tools/CMSIS/Device/ATMEL/samd21/include/instance/tcc1.h@ 136

Last change on this file since 136 was 136, checked in by ertl-honda, 8 years ago

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1/**
2 * \file
3 *
4 * \brief Instance description for TCC1
5 *
6 * Copyright (c) 2014 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 *
42 */
43
44#ifndef _SAMD21_TCC1_INSTANCE_
45#define _SAMD21_TCC1_INSTANCE_
46
47/* ========== Register definition for TCC1 peripheral ========== */
48#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
49#define REG_TCC1_CTRLA (0x42002400U) /**< \brief (TCC1) Control A */
50#define REG_TCC1_CTRLBCLR (0x42002404U) /**< \brief (TCC1) Control B Clear */
51#define REG_TCC1_CTRLBSET (0x42002405U) /**< \brief (TCC1) Control B Set */
52#define REG_TCC1_SYNCBUSY (0x42002408U) /**< \brief (TCC1) Synchronization Busy */
53#define REG_TCC1_FCTRLA (0x4200240CU) /**< \brief (TCC1) Recoverable FaultA Configuration */
54#define REG_TCC1_FCTRLB (0x42002410U) /**< \brief (TCC1) Recoverable FaultB Configuration */
55#define REG_TCC1_DRVCTRL (0x42002418U) /**< \brief (TCC1) Driver Configuration */
56#define REG_TCC1_DBGCTRL (0x4200241EU) /**< \brief (TCC1) Debug Control */
57#define REG_TCC1_EVCTRL (0x42002420U) /**< \brief (TCC1) Event Control */
58#define REG_TCC1_INTENCLR (0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */
59#define REG_TCC1_INTENSET (0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */
60#define REG_TCC1_INTFLAG (0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */
61#define REG_TCC1_STATUS (0x42002430U) /**< \brief (TCC1) Status */
62#define REG_TCC1_COUNT (0x42002434U) /**< \brief (TCC1) Count */
63#define REG_TCC1_PATT (0x42002438U) /**< \brief (TCC1) Pattern */
64#define REG_TCC1_WAVE (0x4200243CU) /**< \brief (TCC1) Waveform Control */
65#define REG_TCC1_PER (0x42002440U) /**< \brief (TCC1) Period */
66#define REG_TCC1_CC0 (0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */
67#define REG_TCC1_CC1 (0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */
68#define REG_TCC1_PATTB (0x42002464U) /**< \brief (TCC1) Pattern Buffer */
69#define REG_TCC1_WAVEB (0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */
70#define REG_TCC1_PERB (0x4200246CU) /**< \brief (TCC1) Period Buffer */
71#define REG_TCC1_CCB0 (0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */
72#define REG_TCC1_CCB1 (0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */
73#else
74#define REG_TCC1_CTRLA (*(RwReg *)0x42002400U) /**< \brief (TCC1) Control A */
75#define REG_TCC1_CTRLBCLR (*(RwReg8 *)0x42002404U) /**< \brief (TCC1) Control B Clear */
76#define REG_TCC1_CTRLBSET (*(RwReg8 *)0x42002405U) /**< \brief (TCC1) Control B Set */
77#define REG_TCC1_SYNCBUSY (*(RoReg *)0x42002408U) /**< \brief (TCC1) Synchronization Busy */
78#define REG_TCC1_FCTRLA (*(RwReg *)0x4200240CU) /**< \brief (TCC1) Recoverable FaultA Configuration */
79#define REG_TCC1_FCTRLB (*(RwReg *)0x42002410U) /**< \brief (TCC1) Recoverable FaultB Configuration */
80#define REG_TCC1_DRVCTRL (*(RwReg *)0x42002418U) /**< \brief (TCC1) Driver Configuration */
81#define REG_TCC1_DBGCTRL (*(RwReg8 *)0x4200241EU) /**< \brief (TCC1) Debug Control */
82#define REG_TCC1_EVCTRL (*(RwReg *)0x42002420U) /**< \brief (TCC1) Event Control */
83#define REG_TCC1_INTENCLR (*(RwReg *)0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */
84#define REG_TCC1_INTENSET (*(RwReg *)0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */
85#define REG_TCC1_INTFLAG (*(RwReg *)0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */
86#define REG_TCC1_STATUS (*(RwReg *)0x42002430U) /**< \brief (TCC1) Status */
87#define REG_TCC1_COUNT (*(RwReg *)0x42002434U) /**< \brief (TCC1) Count */
88#define REG_TCC1_PATT (*(RwReg16*)0x42002438U) /**< \brief (TCC1) Pattern */
89#define REG_TCC1_WAVE (*(RwReg *)0x4200243CU) /**< \brief (TCC1) Waveform Control */
90#define REG_TCC1_PER (*(RwReg *)0x42002440U) /**< \brief (TCC1) Period */
91#define REG_TCC1_CC0 (*(RwReg *)0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */
92#define REG_TCC1_CC1 (*(RwReg *)0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */
93#define REG_TCC1_PATTB (*(RwReg16*)0x42002464U) /**< \brief (TCC1) Pattern Buffer */
94#define REG_TCC1_WAVEB (*(RwReg *)0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */
95#define REG_TCC1_PERB (*(RwReg *)0x4200246CU) /**< \brief (TCC1) Period Buffer */
96#define REG_TCC1_CCB0 (*(RwReg *)0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */
97#define REG_TCC1_CCB1 (*(RwReg *)0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */
98#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
99
100/* ========== Instance parameters for TCC1 peripheral ========== */
101#define TCC1_CC_NUM 2
102#define TCC1_DITHERING 1
103#define TCC1_DMAC_ID_MC_0 19
104#define TCC1_DMAC_ID_MC_1 20
105#define TCC1_DMAC_ID_MC_LSB 19
106#define TCC1_DMAC_ID_MC_MSB 20
107#define TCC1_DMAC_ID_MC_SIZE 2
108#define TCC1_DMAC_ID_OVF 18
109#define TCC1_DTI 0
110#define TCC1_EXT (TCC1_DITHERING*16+TCC1_PG*8+TCC1_SWAP*4+TCC1_DTI*2+TCC1_OTMX*1)
111#define TCC1_GCLK_ID 26
112#define TCC1_MASTER 1
113#define TCC1_OTMX 0
114#define TCC1_OW_NUM 4
115#define TCC1_PG 1
116#define TCC1_SIZE 24
117#define TCC1_SWAP 0
118
119#endif /* _SAMD21_TCC1_INSTANCE_ */
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