[136] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Instance description for TCC0
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| 5 | *
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| 6 | * Copyright (c) 2014 Atmel Corporation. All rights reserved.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * Redistribution and use in source and binary forms, with or without
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| 13 | * modification, are permitted provided that the following conditions are met:
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| 14 | *
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| 15 | * 1. Redistributions of source code must retain the above copyright notice,
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| 16 | * this list of conditions and the following disclaimer.
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| 17 | *
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| 18 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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| 19 | * this list of conditions and the following disclaimer in the documentation
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| 20 | * and/or other materials provided with the distribution.
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| 21 | *
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| 22 | * 3. The name of Atmel may not be used to endorse or promote products derived
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| 23 | * from this software without specific prior written permission.
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| 24 | *
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| 25 | * 4. This software may only be redistributed and used in connection with an
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| 26 | * Atmel microcontroller product.
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| 27 | *
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| 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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| 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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| 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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| 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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| 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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| 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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| 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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| 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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| 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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| 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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| 38 | * POSSIBILITY OF SUCH DAMAGE.
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| 39 | *
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| 40 | * \asf_license_stop
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| 41 | *
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| 42 | */
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| 43 |
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| 44 | #ifndef _SAMD21_TCC0_INSTANCE_
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| 45 | #define _SAMD21_TCC0_INSTANCE_
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| 46 |
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| 47 | /* ========== Register definition for TCC0 peripheral ========== */
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| 48 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 49 | #define REG_TCC0_CTRLA (0x42002000U) /**< \brief (TCC0) Control A */
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| 50 | #define REG_TCC0_CTRLBCLR (0x42002004U) /**< \brief (TCC0) Control B Clear */
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| 51 | #define REG_TCC0_CTRLBSET (0x42002005U) /**< \brief (TCC0) Control B Set */
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| 52 | #define REG_TCC0_SYNCBUSY (0x42002008U) /**< \brief (TCC0) Synchronization Busy */
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| 53 | #define REG_TCC0_FCTRLA (0x4200200CU) /**< \brief (TCC0) Recoverable FaultA Configuration */
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| 54 | #define REG_TCC0_FCTRLB (0x42002010U) /**< \brief (TCC0) Recoverable FaultB Configuration */
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| 55 | #define REG_TCC0_WEXCTRL (0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */
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| 56 | #define REG_TCC0_DRVCTRL (0x42002018U) /**< \brief (TCC0) Driver Configuration */
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| 57 | #define REG_TCC0_DBGCTRL (0x4200201EU) /**< \brief (TCC0) Debug Control */
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| 58 | #define REG_TCC0_EVCTRL (0x42002020U) /**< \brief (TCC0) Event Control */
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| 59 | #define REG_TCC0_INTENCLR (0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */
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| 60 | #define REG_TCC0_INTENSET (0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */
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| 61 | #define REG_TCC0_INTFLAG (0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */
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| 62 | #define REG_TCC0_STATUS (0x42002030U) /**< \brief (TCC0) Status */
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| 63 | #define REG_TCC0_COUNT (0x42002034U) /**< \brief (TCC0) Count */
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| 64 | #define REG_TCC0_PATT (0x42002038U) /**< \brief (TCC0) Pattern */
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| 65 | #define REG_TCC0_WAVE (0x4200203CU) /**< \brief (TCC0) Waveform Control */
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| 66 | #define REG_TCC0_PER (0x42002040U) /**< \brief (TCC0) Period */
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| 67 | #define REG_TCC0_CC0 (0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */
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| 68 | #define REG_TCC0_CC1 (0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */
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| 69 | #define REG_TCC0_CC2 (0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */
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| 70 | #define REG_TCC0_CC3 (0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */
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| 71 | #define REG_TCC0_PATTB (0x42002064U) /**< \brief (TCC0) Pattern Buffer */
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| 72 | #define REG_TCC0_WAVEB (0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */
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| 73 | #define REG_TCC0_PERB (0x4200206CU) /**< \brief (TCC0) Period Buffer */
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| 74 | #define REG_TCC0_CCB0 (0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */
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| 75 | #define REG_TCC0_CCB1 (0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */
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| 76 | #define REG_TCC0_CCB2 (0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */
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| 77 | #define REG_TCC0_CCB3 (0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */
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| 78 | #else
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| 79 | #define REG_TCC0_CTRLA (*(RwReg *)0x42002000U) /**< \brief (TCC0) Control A */
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| 80 | #define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x42002004U) /**< \brief (TCC0) Control B Clear */
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| 81 | #define REG_TCC0_CTRLBSET (*(RwReg8 *)0x42002005U) /**< \brief (TCC0) Control B Set */
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| 82 | #define REG_TCC0_SYNCBUSY (*(RoReg *)0x42002008U) /**< \brief (TCC0) Synchronization Busy */
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| 83 | #define REG_TCC0_FCTRLA (*(RwReg *)0x4200200CU) /**< \brief (TCC0) Recoverable FaultA Configuration */
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| 84 | #define REG_TCC0_FCTRLB (*(RwReg *)0x42002010U) /**< \brief (TCC0) Recoverable FaultB Configuration */
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| 85 | #define REG_TCC0_WEXCTRL (*(RwReg *)0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */
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| 86 | #define REG_TCC0_DRVCTRL (*(RwReg *)0x42002018U) /**< \brief (TCC0) Driver Configuration */
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| 87 | #define REG_TCC0_DBGCTRL (*(RwReg8 *)0x4200201EU) /**< \brief (TCC0) Debug Control */
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| 88 | #define REG_TCC0_EVCTRL (*(RwReg *)0x42002020U) /**< \brief (TCC0) Event Control */
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| 89 | #define REG_TCC0_INTENCLR (*(RwReg *)0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */
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| 90 | #define REG_TCC0_INTENSET (*(RwReg *)0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */
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| 91 | #define REG_TCC0_INTFLAG (*(RwReg *)0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */
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| 92 | #define REG_TCC0_STATUS (*(RwReg *)0x42002030U) /**< \brief (TCC0) Status */
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| 93 | #define REG_TCC0_COUNT (*(RwReg *)0x42002034U) /**< \brief (TCC0) Count */
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| 94 | #define REG_TCC0_PATT (*(RwReg16*)0x42002038U) /**< \brief (TCC0) Pattern */
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| 95 | #define REG_TCC0_WAVE (*(RwReg *)0x4200203CU) /**< \brief (TCC0) Waveform Control */
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| 96 | #define REG_TCC0_PER (*(RwReg *)0x42002040U) /**< \brief (TCC0) Period */
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| 97 | #define REG_TCC0_CC0 (*(RwReg *)0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */
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| 98 | #define REG_TCC0_CC1 (*(RwReg *)0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */
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| 99 | #define REG_TCC0_CC2 (*(RwReg *)0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */
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| 100 | #define REG_TCC0_CC3 (*(RwReg *)0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */
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| 101 | #define REG_TCC0_PATTB (*(RwReg16*)0x42002064U) /**< \brief (TCC0) Pattern Buffer */
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| 102 | #define REG_TCC0_WAVEB (*(RwReg *)0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */
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| 103 | #define REG_TCC0_PERB (*(RwReg *)0x4200206CU) /**< \brief (TCC0) Period Buffer */
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| 104 | #define REG_TCC0_CCB0 (*(RwReg *)0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */
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| 105 | #define REG_TCC0_CCB1 (*(RwReg *)0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */
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| 106 | #define REG_TCC0_CCB2 (*(RwReg *)0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */
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| 107 | #define REG_TCC0_CCB3 (*(RwReg *)0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */
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| 108 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 109 |
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| 110 | /* ========== Instance parameters for TCC0 peripheral ========== */
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| 111 | #define TCC0_CC_NUM 4
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| 112 | #define TCC0_DITHERING 1
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| 113 | #define TCC0_DMAC_ID_MC_0 14
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| 114 | #define TCC0_DMAC_ID_MC_1 15
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| 115 | #define TCC0_DMAC_ID_MC_2 16
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| 116 | #define TCC0_DMAC_ID_MC_3 17
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| 117 | #define TCC0_DMAC_ID_MC_LSB 14
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| 118 | #define TCC0_DMAC_ID_MC_MSB 17
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| 119 | #define TCC0_DMAC_ID_MC_SIZE 4
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| 120 | #define TCC0_DMAC_ID_OVF 13
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| 121 | #define TCC0_DTI 1
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| 122 | #define TCC0_EXT (TCC0_DITHERING*16+TCC0_PG*8+TCC0_SWAP*4+TCC0_DTI*2+TCC0_OTMX*1)
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| 123 | #define TCC0_GCLK_ID 26
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| 124 | #define TCC0_MASTER 0
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| 125 | #define TCC0_OTMX 1
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| 126 | #define TCC0_OW_NUM 8
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| 127 | #define TCC0_PG 1
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| 128 | #define TCC0_SIZE 24
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| 129 | #define TCC0_SWAP 1
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| 130 |
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| 131 | #endif /* _SAMD21_TCC0_INSTANCE_ */
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