[136] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for TC
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| 5 | *
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| 6 | * Copyright (c) 2014 Atmel Corporation. All rights reserved.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * Redistribution and use in source and binary forms, with or without
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| 13 | * modification, are permitted provided that the following conditions are met:
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| 14 | *
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| 15 | * 1. Redistributions of source code must retain the above copyright notice,
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| 16 | * this list of conditions and the following disclaimer.
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| 17 | *
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| 18 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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| 19 | * this list of conditions and the following disclaimer in the documentation
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| 20 | * and/or other materials provided with the distribution.
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| 21 | *
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| 22 | * 3. The name of Atmel may not be used to endorse or promote products derived
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| 23 | * from this software without specific prior written permission.
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| 24 | *
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| 25 | * 4. This software may only be redistributed and used in connection with an
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| 26 | * Atmel microcontroller product.
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| 27 | *
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| 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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| 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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| 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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| 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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| 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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| 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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| 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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| 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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| 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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| 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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| 38 | * POSSIBILITY OF SUCH DAMAGE.
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| 39 | *
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| 40 | * \asf_license_stop
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| 41 | *
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| 42 | */
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| 43 |
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| 44 | #ifndef _SAMD21_TC_COMPONENT_
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| 45 | #define _SAMD21_TC_COMPONENT_
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| 46 |
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| 47 | /* ========================================================================== */
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| 48 | /** SOFTWARE API DEFINITION FOR TC */
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| 49 | /* ========================================================================== */
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| 50 | /** \addtogroup SAMD21_TC Basic Timer Counter */
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| 51 | /*@{*/
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| 52 |
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| 53 | #define TC_U2212
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| 54 | #define REV_TC 0x121
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| 55 |
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| 56 | /* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */
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| 57 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 58 | typedef union {
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| 59 | struct {
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| 60 | uint16_t SWRST:1; /*!< bit: 0 Software Reset */
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| 61 | uint16_t ENABLE:1; /*!< bit: 1 Enable */
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| 62 | uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */
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| 63 | uint16_t :1; /*!< bit: 4 Reserved */
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| 64 | uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */
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| 65 | uint16_t :1; /*!< bit: 7 Reserved */
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| 66 | uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
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| 67 | uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
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| 68 | uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */
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| 69 | uint16_t :2; /*!< bit: 14..15 Reserved */
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| 70 | } bit; /*!< Structure used for bit access */
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| 71 | uint16_t reg; /*!< Type used for register access */
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| 72 | } TC_CTRLA_Type;
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| 73 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 74 |
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| 75 | #define TC_CTRLA_OFFSET 0x00 /**< \brief (TC_CTRLA offset) Control A */
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| 76 | #define TC_CTRLA_RESETVALUE 0x0000 /**< \brief (TC_CTRLA reset_value) Control A */
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| 77 |
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| 78 | #define TC_CTRLA_SWRST_Pos 0 /**< \brief (TC_CTRLA) Software Reset */
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| 79 | #define TC_CTRLA_SWRST (0x1u << TC_CTRLA_SWRST_Pos)
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| 80 | #define TC_CTRLA_ENABLE_Pos 1 /**< \brief (TC_CTRLA) Enable */
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| 81 | #define TC_CTRLA_ENABLE (0x1u << TC_CTRLA_ENABLE_Pos)
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| 82 | #define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) TC Mode */
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| 83 | #define TC_CTRLA_MODE_Msk (0x3u << TC_CTRLA_MODE_Pos)
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| 84 | #define TC_CTRLA_MODE(value) ((TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos)))
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| 85 | #define TC_CTRLA_MODE_COUNT16_Val 0x0u /**< \brief (TC_CTRLA) Counter in 16-bit mode */
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| 86 | #define TC_CTRLA_MODE_COUNT8_Val 0x1u /**< \brief (TC_CTRLA) Counter in 8-bit mode */
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| 87 | #define TC_CTRLA_MODE_COUNT32_Val 0x2u /**< \brief (TC_CTRLA) Counter in 32-bit mode */
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| 88 | #define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos)
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| 89 | #define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos)
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| 90 | #define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos)
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| 91 | #define TC_CTRLA_WAVEGEN_Pos 5 /**< \brief (TC_CTRLA) Waveform Generation Operation */
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| 92 | #define TC_CTRLA_WAVEGEN_Msk (0x3u << TC_CTRLA_WAVEGEN_Pos)
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| 93 | #define TC_CTRLA_WAVEGEN(value) ((TC_CTRLA_WAVEGEN_Msk & ((value) << TC_CTRLA_WAVEGEN_Pos)))
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| 94 | #define TC_CTRLA_WAVEGEN_NFRQ_Val 0x0u /**< \brief (TC_CTRLA) */
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| 95 | #define TC_CTRLA_WAVEGEN_MFRQ_Val 0x1u /**< \brief (TC_CTRLA) */
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| 96 | #define TC_CTRLA_WAVEGEN_NPWM_Val 0x2u /**< \brief (TC_CTRLA) */
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| 97 | #define TC_CTRLA_WAVEGEN_MPWM_Val 0x3u /**< \brief (TC_CTRLA) */
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| 98 | #define TC_CTRLA_WAVEGEN_NFRQ (TC_CTRLA_WAVEGEN_NFRQ_Val << TC_CTRLA_WAVEGEN_Pos)
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| 99 | #define TC_CTRLA_WAVEGEN_MFRQ (TC_CTRLA_WAVEGEN_MFRQ_Val << TC_CTRLA_WAVEGEN_Pos)
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| 100 | #define TC_CTRLA_WAVEGEN_NPWM (TC_CTRLA_WAVEGEN_NPWM_Val << TC_CTRLA_WAVEGEN_Pos)
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| 101 | #define TC_CTRLA_WAVEGEN_MPWM (TC_CTRLA_WAVEGEN_MPWM_Val << TC_CTRLA_WAVEGEN_Pos)
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| 102 | #define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */
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| 103 | #define TC_CTRLA_PRESCALER_Msk (0x7u << TC_CTRLA_PRESCALER_Pos)
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| 104 | #define TC_CTRLA_PRESCALER(value) ((TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos)))
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| 105 | #define TC_CTRLA_PRESCALER_DIV1_Val 0x0u /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */
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| 106 | #define TC_CTRLA_PRESCALER_DIV2_Val 0x1u /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */
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| 107 | #define TC_CTRLA_PRESCALER_DIV4_Val 0x2u /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */
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| 108 | #define TC_CTRLA_PRESCALER_DIV8_Val 0x3u /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */
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| 109 | #define TC_CTRLA_PRESCALER_DIV16_Val 0x4u /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */
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| 110 | #define TC_CTRLA_PRESCALER_DIV64_Val 0x5u /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */
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| 111 | #define TC_CTRLA_PRESCALER_DIV256_Val 0x6u /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */
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| 112 | #define TC_CTRLA_PRESCALER_DIV1024_Val 0x7u /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */
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| 113 | #define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos)
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| 114 | #define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos)
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| 115 | #define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos)
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| 116 | #define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos)
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| 117 | #define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos)
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| 118 | #define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos)
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| 119 | #define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos)
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| 120 | #define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos)
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| 121 | #define TC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TC_CTRLA) Run in Standby */
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| 122 | #define TC_CTRLA_RUNSTDBY (0x1u << TC_CTRLA_RUNSTDBY_Pos)
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| 123 | #define TC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */
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| 124 | #define TC_CTRLA_PRESCSYNC_Msk (0x3u << TC_CTRLA_PRESCSYNC_Pos)
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| 125 | #define TC_CTRLA_PRESCSYNC(value) ((TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos)))
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| 126 | #define TC_CTRLA_PRESCSYNC_GCLK_Val 0x0u /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */
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| 127 | #define TC_CTRLA_PRESCSYNC_PRESC_Val 0x1u /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */
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| 128 | #define TC_CTRLA_PRESCSYNC_RESYNC_Val 0x2u /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock. Reset the prescaler counter */
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| 129 | #define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos)
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| 130 | #define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos)
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| 131 | #define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos)
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| 132 | #define TC_CTRLA_MASK 0x3F6Fu /**< \brief (TC_CTRLA) MASK Register */
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| 133 |
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| 134 | /* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */
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| 135 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 136 | typedef union {
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| 137 | struct {
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| 138 | uint16_t ADDR:5; /*!< bit: 0.. 4 Address */
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| 139 | uint16_t :9; /*!< bit: 5..13 Reserved */
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| 140 | uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
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| 141 | uint16_t RREQ:1; /*!< bit: 15 Read Request */
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| 142 | } bit; /*!< Structure used for bit access */
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| 143 | uint16_t reg; /*!< Type used for register access */
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| 144 | } TC_READREQ_Type;
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| 145 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 146 |
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| 147 | #define TC_READREQ_OFFSET 0x02 /**< \brief (TC_READREQ offset) Read Request */
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| 148 | #define TC_READREQ_RESETVALUE 0x0000 /**< \brief (TC_READREQ reset_value) Read Request */
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| 149 |
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| 150 | #define TC_READREQ_ADDR_Pos 0 /**< \brief (TC_READREQ) Address */
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| 151 | #define TC_READREQ_ADDR_Msk (0x1Fu << TC_READREQ_ADDR_Pos)
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| 152 | #define TC_READREQ_ADDR(value) ((TC_READREQ_ADDR_Msk & ((value) << TC_READREQ_ADDR_Pos)))
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| 153 | #define TC_READREQ_RCONT_Pos 14 /**< \brief (TC_READREQ) Read Continuously */
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| 154 | #define TC_READREQ_RCONT (0x1u << TC_READREQ_RCONT_Pos)
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| 155 | #define TC_READREQ_RREQ_Pos 15 /**< \brief (TC_READREQ) Read Request */
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| 156 | #define TC_READREQ_RREQ (0x1u << TC_READREQ_RREQ_Pos)
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| 157 | #define TC_READREQ_MASK 0xC01Fu /**< \brief (TC_READREQ) MASK Register */
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| 158 |
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| 159 | /* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */
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| 160 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 161 | typedef union {
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| 162 | struct {
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| 163 | uint8_t DIR:1; /*!< bit: 0 Counter Direction */
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| 164 | uint8_t :1; /*!< bit: 1 Reserved */
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| 165 | uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
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| 166 | uint8_t :3; /*!< bit: 3.. 5 Reserved */
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| 167 | uint8_t CMD:2; /*!< bit: 6.. 7 Command */
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| 168 | } bit; /*!< Structure used for bit access */
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| 169 | uint8_t reg; /*!< Type used for register access */
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| 170 | } TC_CTRLBCLR_Type;
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| 171 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 172 |
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| 173 | #define TC_CTRLBCLR_OFFSET 0x04 /**< \brief (TC_CTRLBCLR offset) Control B Clear */
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| 174 | #define TC_CTRLBCLR_RESETVALUE 0x02 /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */
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| 175 |
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| 176 | #define TC_CTRLBCLR_DIR_Pos 0 /**< \brief (TC_CTRLBCLR) Counter Direction */
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| 177 | #define TC_CTRLBCLR_DIR (0x1u << TC_CTRLBCLR_DIR_Pos)
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| 178 | #define TC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TC_CTRLBCLR) One-Shot */
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| 179 | #define TC_CTRLBCLR_ONESHOT (0x1u << TC_CTRLBCLR_ONESHOT_Pos)
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| 180 | #define TC_CTRLBCLR_CMD_Pos 6 /**< \brief (TC_CTRLBCLR) Command */
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| 181 | #define TC_CTRLBCLR_CMD_Msk (0x3u << TC_CTRLBCLR_CMD_Pos)
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| 182 | #define TC_CTRLBCLR_CMD(value) ((TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos)))
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| 183 | #define TC_CTRLBCLR_CMD_NONE_Val 0x0u /**< \brief (TC_CTRLBCLR) No action */
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| 184 | #define TC_CTRLBCLR_CMD_RETRIGGER_Val 0x1u /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */
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| 185 | #define TC_CTRLBCLR_CMD_STOP_Val 0x2u /**< \brief (TC_CTRLBCLR) Force a stop */
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| 186 | #define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos)
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| 187 | #define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos)
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| 188 | #define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos)
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| 189 | #define TC_CTRLBCLR_MASK 0xC5u /**< \brief (TC_CTRLBCLR) MASK Register */
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| 190 |
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| 191 | /* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */
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| 192 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 193 | typedef union {
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| 194 | struct {
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| 195 | uint8_t DIR:1; /*!< bit: 0 Counter Direction */
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| 196 | uint8_t :1; /*!< bit: 1 Reserved */
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| 197 | uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
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| 198 | uint8_t :3; /*!< bit: 3.. 5 Reserved */
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| 199 | uint8_t CMD:2; /*!< bit: 6.. 7 Command */
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| 200 | } bit; /*!< Structure used for bit access */
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| 201 | uint8_t reg; /*!< Type used for register access */
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| 202 | } TC_CTRLBSET_Type;
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| 203 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 204 |
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| 205 | #define TC_CTRLBSET_OFFSET 0x05 /**< \brief (TC_CTRLBSET offset) Control B Set */
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| 206 | #define TC_CTRLBSET_RESETVALUE 0x00 /**< \brief (TC_CTRLBSET reset_value) Control B Set */
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| 207 |
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| 208 | #define TC_CTRLBSET_DIR_Pos 0 /**< \brief (TC_CTRLBSET) Counter Direction */
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| 209 | #define TC_CTRLBSET_DIR (0x1u << TC_CTRLBSET_DIR_Pos)
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| 210 | #define TC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TC_CTRLBSET) One-Shot */
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| 211 | #define TC_CTRLBSET_ONESHOT (0x1u << TC_CTRLBSET_ONESHOT_Pos)
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| 212 | #define TC_CTRLBSET_CMD_Pos 6 /**< \brief (TC_CTRLBSET) Command */
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| 213 | #define TC_CTRLBSET_CMD_Msk (0x3u << TC_CTRLBSET_CMD_Pos)
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| 214 | #define TC_CTRLBSET_CMD(value) ((TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos)))
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| 215 | #define TC_CTRLBSET_CMD_NONE_Val 0x0u /**< \brief (TC_CTRLBSET) No action */
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| 216 | #define TC_CTRLBSET_CMD_RETRIGGER_Val 0x1u /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */
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| 217 | #define TC_CTRLBSET_CMD_STOP_Val 0x2u /**< \brief (TC_CTRLBSET) Force a stop */
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| 218 | #define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos)
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| 219 | #define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos)
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| 220 | #define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos)
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| 221 | #define TC_CTRLBSET_MASK 0xC5u /**< \brief (TC_CTRLBSET) MASK Register */
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| 222 |
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| 223 | /* -------- TC_CTRLC : (TC Offset: 0x06) (R/W 8) Control C -------- */
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| 224 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 225 | typedef union {
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| 226 | struct {
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| 227 | uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */
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| 228 | uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */
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| 229 | uint8_t :2; /*!< bit: 2.. 3 Reserved */
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| 230 | uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */
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| 231 | uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */
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| 232 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
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| 233 | } bit; /*!< Structure used for bit access */
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| 234 | struct {
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| 235 | uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */
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| 236 | uint8_t :2; /*!< bit: 2.. 3 Reserved */
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| 237 | uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */
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| 238 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
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| 239 | } vec; /*!< Structure used for vec access */
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| 240 | uint8_t reg; /*!< Type used for register access */
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| 241 | } TC_CTRLC_Type;
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| 242 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 243 |
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| 244 | #define TC_CTRLC_OFFSET 0x06 /**< \brief (TC_CTRLC offset) Control C */
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| 245 | #define TC_CTRLC_RESETVALUE 0x00 /**< \brief (TC_CTRLC reset_value) Control C */
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| 246 |
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| 247 | #define TC_CTRLC_INVEN0_Pos 0 /**< \brief (TC_CTRLC) Output Waveform 0 Invert Enable */
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| 248 | #define TC_CTRLC_INVEN0 (1 << TC_CTRLC_INVEN0_Pos)
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| 249 | #define TC_CTRLC_INVEN1_Pos 1 /**< \brief (TC_CTRLC) Output Waveform 1 Invert Enable */
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| 250 | #define TC_CTRLC_INVEN1 (1 << TC_CTRLC_INVEN1_Pos)
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| 251 | #define TC_CTRLC_INVEN_Pos 0 /**< \brief (TC_CTRLC) Output Waveform x Invert Enable */
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| 252 | #define TC_CTRLC_INVEN_Msk (0x3u << TC_CTRLC_INVEN_Pos)
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| 253 | #define TC_CTRLC_INVEN(value) ((TC_CTRLC_INVEN_Msk & ((value) << TC_CTRLC_INVEN_Pos)))
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| 254 | #define TC_CTRLC_CPTEN0_Pos 4 /**< \brief (TC_CTRLC) Capture Channel 0 Enable */
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| 255 | #define TC_CTRLC_CPTEN0 (1 << TC_CTRLC_CPTEN0_Pos)
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| 256 | #define TC_CTRLC_CPTEN1_Pos 5 /**< \brief (TC_CTRLC) Capture Channel 1 Enable */
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| 257 | #define TC_CTRLC_CPTEN1 (1 << TC_CTRLC_CPTEN1_Pos)
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| 258 | #define TC_CTRLC_CPTEN_Pos 4 /**< \brief (TC_CTRLC) Capture Channel x Enable */
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| 259 | #define TC_CTRLC_CPTEN_Msk (0x3u << TC_CTRLC_CPTEN_Pos)
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| 260 | #define TC_CTRLC_CPTEN(value) ((TC_CTRLC_CPTEN_Msk & ((value) << TC_CTRLC_CPTEN_Pos)))
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| 261 | #define TC_CTRLC_MASK 0x33u /**< \brief (TC_CTRLC) MASK Register */
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| 262 |
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| 263 | /* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */
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| 264 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 265 | typedef union {
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| 266 | struct {
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| 267 | uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */
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| 268 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
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| 269 | } bit; /*!< Structure used for bit access */
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| 270 | uint8_t reg; /*!< Type used for register access */
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| 271 | } TC_DBGCTRL_Type;
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| 272 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 273 |
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| 274 | #define TC_DBGCTRL_OFFSET 0x08 /**< \brief (TC_DBGCTRL offset) Debug Control */
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| 275 | #define TC_DBGCTRL_RESETVALUE 0x00 /**< \brief (TC_DBGCTRL reset_value) Debug Control */
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| 276 |
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| 277 | #define TC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TC_DBGCTRL) Debug Run Mode */
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| 278 | #define TC_DBGCTRL_DBGRUN (0x1u << TC_DBGCTRL_DBGRUN_Pos)
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| 279 | #define TC_DBGCTRL_MASK 0x01u /**< \brief (TC_DBGCTRL) MASK Register */
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| 280 |
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| 281 | /* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */
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| 282 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 283 | typedef union {
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| 284 | struct {
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| 285 | uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */
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| 286 | uint16_t :1; /*!< bit: 3 Reserved */
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| 287 | uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */
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| 288 | uint16_t TCEI:1; /*!< bit: 5 TC Event Input */
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| 289 | uint16_t :2; /*!< bit: 6.. 7 Reserved */
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| 290 | uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */
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| 291 | uint16_t :3; /*!< bit: 9..11 Reserved */
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| 292 | uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */
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| 293 | uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */
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| 294 | uint16_t :2; /*!< bit: 14..15 Reserved */
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| 295 | } bit; /*!< Structure used for bit access */
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| 296 | struct {
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| 297 | uint16_t :12; /*!< bit: 0..11 Reserved */
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| 298 | uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */
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| 299 | uint16_t :2; /*!< bit: 14..15 Reserved */
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| 300 | } vec; /*!< Structure used for vec access */
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| 301 | uint16_t reg; /*!< Type used for register access */
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| 302 | } TC_EVCTRL_Type;
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| 303 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 304 |
|
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| 305 | #define TC_EVCTRL_OFFSET 0x0A /**< \brief (TC_EVCTRL offset) Event Control */
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| 306 | #define TC_EVCTRL_RESETVALUE 0x0000 /**< \brief (TC_EVCTRL reset_value) Event Control */
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| 307 |
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| 308 | #define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */
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| 309 | #define TC_EVCTRL_EVACT_Msk (0x7u << TC_EVCTRL_EVACT_Pos)
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| 310 | #define TC_EVCTRL_EVACT(value) ((TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos)))
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| 311 | #define TC_EVCTRL_EVACT_OFF_Val 0x0u /**< \brief (TC_EVCTRL) Event action disabled */
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| 312 | #define TC_EVCTRL_EVACT_RETRIGGER_Val 0x1u /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */
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| 313 | #define TC_EVCTRL_EVACT_COUNT_Val 0x2u /**< \brief (TC_EVCTRL) Count on event */
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| 314 | #define TC_EVCTRL_EVACT_START_Val 0x3u /**< \brief (TC_EVCTRL) Start TC on event */
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| 315 | #define TC_EVCTRL_EVACT_PPW_Val 0x5u /**< \brief (TC_EVCTRL) Period captured in CC0, pulse width in CC1 */
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| 316 | #define TC_EVCTRL_EVACT_PWP_Val 0x6u /**< \brief (TC_EVCTRL) Period captured in CC1, pulse width in CC0 */
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| 317 | #define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos)
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| 318 | #define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos)
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| 319 | #define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos)
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| 320 | #define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos)
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| 321 | #define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos)
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| 322 | #define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos)
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| 323 | #define TC_EVCTRL_TCINV_Pos 4 /**< \brief (TC_EVCTRL) TC Inverted Event Input */
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| 324 | #define TC_EVCTRL_TCINV (0x1u << TC_EVCTRL_TCINV_Pos)
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| 325 | #define TC_EVCTRL_TCEI_Pos 5 /**< \brief (TC_EVCTRL) TC Event Input */
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| 326 | #define TC_EVCTRL_TCEI (0x1u << TC_EVCTRL_TCEI_Pos)
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| 327 | #define TC_EVCTRL_OVFEO_Pos 8 /**< \brief (TC_EVCTRL) Overflow/Underflow Event Output Enable */
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| 328 | #define TC_EVCTRL_OVFEO (0x1u << TC_EVCTRL_OVFEO_Pos)
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| 329 | #define TC_EVCTRL_MCEO0_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
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| 330 | #define TC_EVCTRL_MCEO0 (1 << TC_EVCTRL_MCEO0_Pos)
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| 331 | #define TC_EVCTRL_MCEO1_Pos 13 /**< \brief (TC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
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| 332 | #define TC_EVCTRL_MCEO1 (1 << TC_EVCTRL_MCEO1_Pos)
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| 333 | #define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel x Event Output Enable */
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| 334 | #define TC_EVCTRL_MCEO_Msk (0x3u << TC_EVCTRL_MCEO_Pos)
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| 335 | #define TC_EVCTRL_MCEO(value) ((TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos)))
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| 336 | #define TC_EVCTRL_MASK 0x3137u /**< \brief (TC_EVCTRL) MASK Register */
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| 337 |
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| 338 | /* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
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| 339 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
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| 340 | typedef union {
|
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| 341 | struct {
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| 342 | uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
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| 343 | uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
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| 344 | uint8_t :1; /*!< bit: 2 Reserved */
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| 345 | uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
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| 346 | uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
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| 347 | uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
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| 348 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
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| 349 | } bit; /*!< Structure used for bit access */
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| 350 | struct {
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| 351 | uint8_t :4; /*!< bit: 0.. 3 Reserved */
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| 352 | uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
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| 353 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
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| 354 | } vec; /*!< Structure used for vec access */
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| 355 | uint8_t reg; /*!< Type used for register access */
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| 356 | } TC_INTENCLR_Type;
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| 357 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
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| 358 |
|
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| 359 | #define TC_INTENCLR_OFFSET 0x0C /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */
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| 360 | #define TC_INTENCLR_RESETVALUE 0x00 /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */
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| 361 |
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| 362 | #define TC_INTENCLR_OVF_Pos 0 /**< \brief (TC_INTENCLR) Overflow Interrupt Enable */
|
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| 363 | #define TC_INTENCLR_OVF (0x1u << TC_INTENCLR_OVF_Pos)
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| 364 | #define TC_INTENCLR_ERR_Pos 1 /**< \brief (TC_INTENCLR) Error Interrupt Enable */
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| 365 | #define TC_INTENCLR_ERR (0x1u << TC_INTENCLR_ERR_Pos)
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| 366 | #define TC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (TC_INTENCLR) Synchronization Ready Interrupt Enable */
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| 367 | #define TC_INTENCLR_SYNCRDY (0x1u << TC_INTENCLR_SYNCRDY_Pos)
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| 368 | #define TC_INTENCLR_MC0_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
|
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| 369 | #define TC_INTENCLR_MC0 (1 << TC_INTENCLR_MC0_Pos)
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| 370 | #define TC_INTENCLR_MC1_Pos 5 /**< \brief (TC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
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| 371 | #define TC_INTENCLR_MC1 (1 << TC_INTENCLR_MC1_Pos)
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| 372 | #define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel x Interrupt Enable */
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| 373 | #define TC_INTENCLR_MC_Msk (0x3u << TC_INTENCLR_MC_Pos)
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| 374 | #define TC_INTENCLR_MC(value) ((TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos)))
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| 375 | #define TC_INTENCLR_MASK 0x3Bu /**< \brief (TC_INTENCLR) MASK Register */
|
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| 376 |
|
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| 377 | /* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */
|
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| 378 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
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| 379 | typedef union {
|
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| 380 | struct {
|
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| 381 | uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
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| 382 | uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
|
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| 383 | uint8_t :1; /*!< bit: 2 Reserved */
|
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| 384 | uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
|
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| 385 | uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
|
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| 386 | uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
|
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| 387 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
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| 388 | } bit; /*!< Structure used for bit access */
|
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| 389 | struct {
|
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| 390 | uint8_t :4; /*!< bit: 0.. 3 Reserved */
|
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| 391 | uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
|
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| 392 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
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| 393 | } vec; /*!< Structure used for vec access */
|
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| 394 | uint8_t reg; /*!< Type used for register access */
|
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| 395 | } TC_INTENSET_Type;
|
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| 396 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
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| 397 |
|
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| 398 | #define TC_INTENSET_OFFSET 0x0D /**< \brief (TC_INTENSET offset) Interrupt Enable Set */
|
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| 399 | #define TC_INTENSET_RESETVALUE 0x00 /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */
|
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| 400 |
|
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| 401 | #define TC_INTENSET_OVF_Pos 0 /**< \brief (TC_INTENSET) Overflow Interrupt Enable */
|
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| 402 | #define TC_INTENSET_OVF (0x1u << TC_INTENSET_OVF_Pos)
|
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| 403 | #define TC_INTENSET_ERR_Pos 1 /**< \brief (TC_INTENSET) Error Interrupt Enable */
|
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| 404 | #define TC_INTENSET_ERR (0x1u << TC_INTENSET_ERR_Pos)
|
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| 405 | #define TC_INTENSET_SYNCRDY_Pos 3 /**< \brief (TC_INTENSET) Synchronization Ready Interrupt Enable */
|
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| 406 | #define TC_INTENSET_SYNCRDY (0x1u << TC_INTENSET_SYNCRDY_Pos)
|
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| 407 | #define TC_INTENSET_MC0_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
|
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| 408 | #define TC_INTENSET_MC0 (1 << TC_INTENSET_MC0_Pos)
|
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| 409 | #define TC_INTENSET_MC1_Pos 5 /**< \brief (TC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
|
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| 410 | #define TC_INTENSET_MC1 (1 << TC_INTENSET_MC1_Pos)
|
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| 411 | #define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel x Interrupt Enable */
|
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| 412 | #define TC_INTENSET_MC_Msk (0x3u << TC_INTENSET_MC_Pos)
|
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| 413 | #define TC_INTENSET_MC(value) ((TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos)))
|
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| 414 | #define TC_INTENSET_MASK 0x3Bu /**< \brief (TC_INTENSET) MASK Register */
|
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| 415 |
|
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| 416 | /* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */
|
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| 417 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 418 | typedef union {
|
---|
| 419 | struct {
|
---|
| 420 | uint8_t OVF:1; /*!< bit: 0 Overflow */
|
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| 421 | uint8_t ERR:1; /*!< bit: 1 Error */
|
---|
| 422 | uint8_t :1; /*!< bit: 2 Reserved */
|
---|
| 423 | uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
|
---|
| 424 | uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */
|
---|
| 425 | uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */
|
---|
| 426 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
---|
| 427 | } bit; /*!< Structure used for bit access */
|
---|
| 428 | struct {
|
---|
| 429 | uint8_t :4; /*!< bit: 0.. 3 Reserved */
|
---|
| 430 | uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */
|
---|
| 431 | uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
---|
| 432 | } vec; /*!< Structure used for vec access */
|
---|
| 433 | uint8_t reg; /*!< Type used for register access */
|
---|
| 434 | } TC_INTFLAG_Type;
|
---|
| 435 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 436 |
|
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| 437 | #define TC_INTFLAG_OFFSET 0x0E /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */
|
---|
| 438 | #define TC_INTFLAG_RESETVALUE 0x00 /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */
|
---|
| 439 |
|
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| 440 | #define TC_INTFLAG_OVF_Pos 0 /**< \brief (TC_INTFLAG) Overflow */
|
---|
| 441 | #define TC_INTFLAG_OVF (0x1u << TC_INTFLAG_OVF_Pos)
|
---|
| 442 | #define TC_INTFLAG_ERR_Pos 1 /**< \brief (TC_INTFLAG) Error */
|
---|
| 443 | #define TC_INTFLAG_ERR (0x1u << TC_INTFLAG_ERR_Pos)
|
---|
| 444 | #define TC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (TC_INTFLAG) Synchronization Ready */
|
---|
| 445 | #define TC_INTFLAG_SYNCRDY (0x1u << TC_INTFLAG_SYNCRDY_Pos)
|
---|
| 446 | #define TC_INTFLAG_MC0_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel 0 */
|
---|
| 447 | #define TC_INTFLAG_MC0 (1 << TC_INTFLAG_MC0_Pos)
|
---|
| 448 | #define TC_INTFLAG_MC1_Pos 5 /**< \brief (TC_INTFLAG) Match or Capture Channel 1 */
|
---|
| 449 | #define TC_INTFLAG_MC1 (1 << TC_INTFLAG_MC1_Pos)
|
---|
| 450 | #define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel x */
|
---|
| 451 | #define TC_INTFLAG_MC_Msk (0x3u << TC_INTFLAG_MC_Pos)
|
---|
| 452 | #define TC_INTFLAG_MC(value) ((TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos)))
|
---|
| 453 | #define TC_INTFLAG_MASK 0x3Bu /**< \brief (TC_INTFLAG) MASK Register */
|
---|
| 454 |
|
---|
| 455 | /* -------- TC_STATUS : (TC Offset: 0x0F) (R/ 8) Status -------- */
|
---|
| 456 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 457 | typedef union {
|
---|
| 458 | struct {
|
---|
| 459 | uint8_t :3; /*!< bit: 0.. 2 Reserved */
|
---|
| 460 | uint8_t STOP:1; /*!< bit: 3 Stop */
|
---|
| 461 | uint8_t SLAVE:1; /*!< bit: 4 Slave */
|
---|
| 462 | uint8_t :2; /*!< bit: 5.. 6 Reserved */
|
---|
| 463 | uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
|
---|
| 464 | } bit; /*!< Structure used for bit access */
|
---|
| 465 | uint8_t reg; /*!< Type used for register access */
|
---|
| 466 | } TC_STATUS_Type;
|
---|
| 467 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 468 |
|
---|
| 469 | #define TC_STATUS_OFFSET 0x0F /**< \brief (TC_STATUS offset) Status */
|
---|
| 470 | #define TC_STATUS_RESETVALUE 0x08 /**< \brief (TC_STATUS reset_value) Status */
|
---|
| 471 |
|
---|
| 472 | #define TC_STATUS_STOP_Pos 3 /**< \brief (TC_STATUS) Stop */
|
---|
| 473 | #define TC_STATUS_STOP (0x1u << TC_STATUS_STOP_Pos)
|
---|
| 474 | #define TC_STATUS_SLAVE_Pos 4 /**< \brief (TC_STATUS) Slave */
|
---|
| 475 | #define TC_STATUS_SLAVE (0x1u << TC_STATUS_SLAVE_Pos)
|
---|
| 476 | #define TC_STATUS_SYNCBUSY_Pos 7 /**< \brief (TC_STATUS) Synchronization Busy */
|
---|
| 477 | #define TC_STATUS_SYNCBUSY (0x1u << TC_STATUS_SYNCBUSY_Pos)
|
---|
| 478 | #define TC_STATUS_MASK 0x98u /**< \brief (TC_STATUS) MASK Register */
|
---|
| 479 |
|
---|
| 480 | /* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */
|
---|
| 481 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 482 | typedef union {
|
---|
| 483 | struct {
|
---|
| 484 | uint16_t COUNT:16; /*!< bit: 0..15 Count Value */
|
---|
| 485 | } bit; /*!< Structure used for bit access */
|
---|
| 486 | uint16_t reg; /*!< Type used for register access */
|
---|
| 487 | } TC_COUNT16_COUNT_Type;
|
---|
| 488 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 489 |
|
---|
| 490 | #define TC_COUNT16_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Counter Value */
|
---|
| 491 | #define TC_COUNT16_COUNT_RESETVALUE 0x0000 /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Counter Value */
|
---|
| 492 |
|
---|
| 493 | #define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Count Value */
|
---|
| 494 | #define TC_COUNT16_COUNT_COUNT_Msk (0xFFFFu << TC_COUNT16_COUNT_COUNT_Pos)
|
---|
| 495 | #define TC_COUNT16_COUNT_COUNT(value) ((TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos)))
|
---|
| 496 | #define TC_COUNT16_COUNT_MASK 0xFFFFu /**< \brief (TC_COUNT16_COUNT) MASK Register */
|
---|
| 497 |
|
---|
| 498 | /* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */
|
---|
| 499 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 500 | typedef union {
|
---|
| 501 | struct {
|
---|
| 502 | uint32_t COUNT:32; /*!< bit: 0..31 Count Value */
|
---|
| 503 | } bit; /*!< Structure used for bit access */
|
---|
| 504 | uint32_t reg; /*!< Type used for register access */
|
---|
| 505 | } TC_COUNT32_COUNT_Type;
|
---|
| 506 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 507 |
|
---|
| 508 | #define TC_COUNT32_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Counter Value */
|
---|
| 509 | #define TC_COUNT32_COUNT_RESETVALUE 0x00000000 /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Counter Value */
|
---|
| 510 |
|
---|
| 511 | #define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Count Value */
|
---|
| 512 | #define TC_COUNT32_COUNT_COUNT_Msk (0xFFFFFFFFu << TC_COUNT32_COUNT_COUNT_Pos)
|
---|
| 513 | #define TC_COUNT32_COUNT_COUNT(value) ((TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos)))
|
---|
| 514 | #define TC_COUNT32_COUNT_MASK 0xFFFFFFFFu /**< \brief (TC_COUNT32_COUNT) MASK Register */
|
---|
| 515 |
|
---|
| 516 | /* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 COUNT8 Counter Value -------- */
|
---|
| 517 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 518 | typedef union {
|
---|
| 519 | struct {
|
---|
| 520 | uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */
|
---|
| 521 | } bit; /*!< Structure used for bit access */
|
---|
| 522 | uint8_t reg; /*!< Type used for register access */
|
---|
| 523 | } TC_COUNT8_COUNT_Type;
|
---|
| 524 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
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| 525 |
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| 526 | #define TC_COUNT8_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Counter Value */
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| 527 | #define TC_COUNT8_COUNT_RESETVALUE 0x00 /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Counter Value */
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| 528 |
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| 529 | #define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */
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| 530 | #define TC_COUNT8_COUNT_COUNT_Msk (0xFFu << TC_COUNT8_COUNT_COUNT_Pos)
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| 531 | #define TC_COUNT8_COUNT_COUNT(value) ((TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos)))
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| 532 | #define TC_COUNT8_COUNT_MASK 0xFFu /**< \brief (TC_COUNT8_COUNT) MASK Register */
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| 533 |
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| 534 | /* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Period Value -------- */
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| 535 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 536 | typedef union {
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| 537 | struct {
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| 538 | uint8_t PER:8; /*!< bit: 0.. 7 Period Value */
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| 539 | } bit; /*!< Structure used for bit access */
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| 540 | uint8_t reg; /*!< Type used for register access */
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| 541 | } TC_COUNT8_PER_Type;
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| 542 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 543 |
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| 544 | #define TC_COUNT8_PER_OFFSET 0x14 /**< \brief (TC_COUNT8_PER offset) COUNT8 Period Value */
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| 545 | #define TC_COUNT8_PER_RESETVALUE 0xFF /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period Value */
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| 546 |
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| 547 | #define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */
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| 548 | #define TC_COUNT8_PER_PER_Msk (0xFFu << TC_COUNT8_PER_PER_Pos)
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| 549 | #define TC_COUNT8_PER_PER(value) ((TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos)))
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| 550 | #define TC_COUNT8_PER_MASK 0xFFu /**< \brief (TC_COUNT8_PER) MASK Register */
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| 551 |
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| 552 | /* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */
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| 553 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 554 | typedef union {
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| 555 | struct {
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| 556 | uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */
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| 557 | } bit; /*!< Structure used for bit access */
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| 558 | uint16_t reg; /*!< Type used for register access */
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| 559 | } TC_COUNT16_CC_Type;
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| 560 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 561 |
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| 562 | #define TC_COUNT16_CC_OFFSET 0x18 /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare/Capture */
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| 563 | #define TC_COUNT16_CC_RESETVALUE 0x0000 /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare/Capture */
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| 564 |
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| 565 | #define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Compare/Capture Value */
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| 566 | #define TC_COUNT16_CC_CC_Msk (0xFFFFu << TC_COUNT16_CC_CC_Pos)
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| 567 | #define TC_COUNT16_CC_CC(value) ((TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos)))
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| 568 | #define TC_COUNT16_CC_MASK 0xFFFFu /**< \brief (TC_COUNT16_CC) MASK Register */
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| 569 |
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| 570 | /* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */
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| 571 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 572 | typedef union {
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| 573 | struct {
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| 574 | uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */
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| 575 | } bit; /*!< Structure used for bit access */
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| 576 | uint32_t reg; /*!< Type used for register access */
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| 577 | } TC_COUNT32_CC_Type;
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| 578 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
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| 579 |
|
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| 580 | #define TC_COUNT32_CC_OFFSET 0x18 /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare/Capture */
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| 581 | #define TC_COUNT32_CC_RESETVALUE 0x00000000 /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare/Capture */
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| 582 |
|
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| 583 | #define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Compare/Capture Value */
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| 584 | #define TC_COUNT32_CC_CC_Msk (0xFFFFFFFFu << TC_COUNT32_CC_CC_Pos)
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| 585 | #define TC_COUNT32_CC_CC(value) ((TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos)))
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| 586 | #define TC_COUNT32_CC_MASK 0xFFFFFFFFu /**< \brief (TC_COUNT32_CC) MASK Register */
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| 587 |
|
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| 588 | /* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 COUNT8 Compare/Capture -------- */
|
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| 589 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
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| 590 | typedef union {
|
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| 591 | struct {
|
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| 592 | uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */
|
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| 593 | } bit; /*!< Structure used for bit access */
|
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| 594 | uint8_t reg; /*!< Type used for register access */
|
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| 595 | } TC_COUNT8_CC_Type;
|
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| 596 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
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| 597 |
|
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| 598 | #define TC_COUNT8_CC_OFFSET 0x18 /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare/Capture */
|
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| 599 | #define TC_COUNT8_CC_RESETVALUE 0x00 /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare/Capture */
|
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| 600 |
|
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| 601 | #define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Compare/Capture Value */
|
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| 602 | #define TC_COUNT8_CC_CC_Msk (0xFFu << TC_COUNT8_CC_CC_Pos)
|
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| 603 | #define TC_COUNT8_CC_CC(value) ((TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos)))
|
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| 604 | #define TC_COUNT8_CC_MASK 0xFFu /**< \brief (TC_COUNT8_CC) MASK Register */
|
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| 605 |
|
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| 606 | /** \brief TC_COUNT8 hardware registers */
|
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| 607 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 608 | typedef struct { /* 8-bit Counter Mode */
|
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| 609 | __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
|
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| 610 | __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
|
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| 611 | __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
|
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| 612 | __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
|
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| 613 | __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
|
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| 614 | RoReg8 Reserved1[0x1];
|
---|
| 615 | __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
|
---|
| 616 | RoReg8 Reserved2[0x1];
|
---|
| 617 | __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
|
---|
| 618 | __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
|
---|
| 619 | __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
|
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| 620 | __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
|
---|
| 621 | __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
|
---|
| 622 | __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */
|
---|
| 623 | RoReg8 Reserved3[0x3];
|
---|
| 624 | __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */
|
---|
| 625 | RoReg8 Reserved4[0x3];
|
---|
| 626 | __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */
|
---|
| 627 | } TcCount8;
|
---|
| 628 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 629 |
|
---|
| 630 | /** \brief TC_COUNT16 hardware registers */
|
---|
| 631 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 632 | typedef struct { /* 16-bit Counter Mode */
|
---|
| 633 | __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
|
---|
| 634 | __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
|
---|
| 635 | __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
|
---|
| 636 | __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
|
---|
| 637 | __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
|
---|
| 638 | RoReg8 Reserved1[0x1];
|
---|
| 639 | __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
|
---|
| 640 | RoReg8 Reserved2[0x1];
|
---|
| 641 | __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
|
---|
| 642 | __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
|
---|
| 643 | __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
|
---|
| 644 | __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
|
---|
| 645 | __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
|
---|
| 646 | __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */
|
---|
| 647 | RoReg8 Reserved3[0x6];
|
---|
| 648 | __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */
|
---|
| 649 | } TcCount16;
|
---|
| 650 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 651 |
|
---|
| 652 | /** \brief TC_COUNT32 hardware registers */
|
---|
| 653 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 654 | typedef struct { /* 32-bit Counter Mode */
|
---|
| 655 | __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
|
---|
| 656 | __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
|
---|
| 657 | __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
|
---|
| 658 | __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
|
---|
| 659 | __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
|
---|
| 660 | RoReg8 Reserved1[0x1];
|
---|
| 661 | __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
|
---|
| 662 | RoReg8 Reserved2[0x1];
|
---|
| 663 | __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
|
---|
| 664 | __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
|
---|
| 665 | __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
|
---|
| 666 | __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
|
---|
| 667 | __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
|
---|
| 668 | __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */
|
---|
| 669 | RoReg8 Reserved3[0x4];
|
---|
| 670 | __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */
|
---|
| 671 | } TcCount32;
|
---|
| 672 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 673 |
|
---|
| 674 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 675 | typedef union {
|
---|
| 676 | TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */
|
---|
| 677 | TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */
|
---|
| 678 | TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */
|
---|
| 679 | } Tc;
|
---|
| 680 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 681 |
|
---|
| 682 | /*@}*/
|
---|
| 683 |
|
---|
| 684 | #endif /* _SAMD21_TC_COMPONENT_ */
|
---|