source: rtos_arduino/trunk/arduino_lib/hardware/tools/CMSIS/Device/ATMEL/samd21/include/component/evsys.h@ 136

Last change on this file since 136 was 136, checked in by ertl-honda, 8 years ago

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1/**
2 * \file
3 *
4 * \brief Component description for EVSYS
5 *
6 * Copyright (c) 2014 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 *
42 */
43
44#ifndef _SAMD21_EVSYS_COMPONENT_
45#define _SAMD21_EVSYS_COMPONENT_
46
47/* ========================================================================== */
48/** SOFTWARE API DEFINITION FOR EVSYS */
49/* ========================================================================== */
50/** \addtogroup SAMD21_EVSYS Event System Interface */
51/*@{*/
52
53#define EVSYS_U2208
54#define REV_EVSYS 0x101
55
56/* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W 8) Control -------- */
57#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
58typedef union {
59 struct {
60 uint8_t SWRST:1; /*!< bit: 0 Software Reset */
61 uint8_t :3; /*!< bit: 1.. 3 Reserved */
62 uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */
63 uint8_t :3; /*!< bit: 5.. 7 Reserved */
64 } bit; /*!< Structure used for bit access */
65 uint8_t reg; /*!< Type used for register access */
66} EVSYS_CTRL_Type;
67#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
68
69#define EVSYS_CTRL_OFFSET 0x00 /**< \brief (EVSYS_CTRL offset) Control */
70#define EVSYS_CTRL_RESETVALUE 0x00 /**< \brief (EVSYS_CTRL reset_value) Control */
71
72#define EVSYS_CTRL_SWRST_Pos 0 /**< \brief (EVSYS_CTRL) Software Reset */
73#define EVSYS_CTRL_SWRST (0x1u << EVSYS_CTRL_SWRST_Pos)
74#define EVSYS_CTRL_GCLKREQ_Pos 4 /**< \brief (EVSYS_CTRL) Generic Clock Requests */
75#define EVSYS_CTRL_GCLKREQ (0x1u << EVSYS_CTRL_GCLKREQ_Pos)
76#define EVSYS_CTRL_MASK 0x11u /**< \brief (EVSYS_CTRL) MASK Register */
77
78/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
79#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
80typedef union {
81 struct {
82 uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */
83 uint32_t :4; /*!< bit: 4.. 7 Reserved */
84 uint32_t SWEVT:1; /*!< bit: 8 Software Event */
85 uint32_t :7; /*!< bit: 9..15 Reserved */
86 uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */
87 uint32_t :1; /*!< bit: 23 Reserved */
88 uint32_t PATH:2; /*!< bit: 24..25 Path Selection */
89 uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */
90 uint32_t :4; /*!< bit: 28..31 Reserved */
91 } bit; /*!< Structure used for bit access */
92 uint32_t reg; /*!< Type used for register access */
93} EVSYS_CHANNEL_Type;
94#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
95
96#define EVSYS_CHANNEL_OFFSET 0x04 /**< \brief (EVSYS_CHANNEL offset) Channel */
97#define EVSYS_CHANNEL_RESETVALUE 0x00000000 /**< \brief (EVSYS_CHANNEL reset_value) Channel */
98
99#define EVSYS_CHANNEL_CHANNEL_Pos 0 /**< \brief (EVSYS_CHANNEL) Channel Selection */
100#define EVSYS_CHANNEL_CHANNEL_Msk (0xFu << EVSYS_CHANNEL_CHANNEL_Pos)
101#define EVSYS_CHANNEL_CHANNEL(value) ((EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos)))
102#define EVSYS_CHANNEL_SWEVT_Pos 8 /**< \brief (EVSYS_CHANNEL) Software Event */
103#define EVSYS_CHANNEL_SWEVT (0x1u << EVSYS_CHANNEL_SWEVT_Pos)
104#define EVSYS_CHANNEL_EVGEN_Pos 16 /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
105#define EVSYS_CHANNEL_EVGEN_Msk (0x7Fu << EVSYS_CHANNEL_EVGEN_Pos)
106#define EVSYS_CHANNEL_EVGEN(value) ((EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos)))
107#define EVSYS_CHANNEL_PATH_Pos 24 /**< \brief (EVSYS_CHANNEL) Path Selection */
108#define EVSYS_CHANNEL_PATH_Msk (0x3u << EVSYS_CHANNEL_PATH_Pos)
109#define EVSYS_CHANNEL_PATH(value) ((EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos)))
110#define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val 0x0u /**< \brief (EVSYS_CHANNEL) Synchronous path */
111#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val 0x1u /**< \brief (EVSYS_CHANNEL) Resynchronized path */
112#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val 0x2u /**< \brief (EVSYS_CHANNEL) Asynchronous path */
113#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
114#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
115#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
116#define EVSYS_CHANNEL_EDGSEL_Pos 26 /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
117#define EVSYS_CHANNEL_EDGSEL_Msk (0x3u << EVSYS_CHANNEL_EDGSEL_Pos)
118#define EVSYS_CHANNEL_EDGSEL(value) ((EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos)))
119#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val 0x0u /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
120#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val 0x1u /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
121#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val 0x2u /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
122#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val 0x3u /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
123#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
124#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
125#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
126#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
127#define EVSYS_CHANNEL_MASK 0x0F7F010Fu /**< \brief (EVSYS_CHANNEL) MASK Register */
128
129/* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
130#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
131typedef union {
132 struct {
133 uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */
134 uint16_t :3; /*!< bit: 5.. 7 Reserved */
135 uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */
136 uint16_t :3; /*!< bit: 13..15 Reserved */
137 } bit; /*!< Structure used for bit access */
138 uint16_t reg; /*!< Type used for register access */
139} EVSYS_USER_Type;
140#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
141
142#define EVSYS_USER_OFFSET 0x08 /**< \brief (EVSYS_USER offset) User Multiplexer */
143#define EVSYS_USER_RESETVALUE 0x0000 /**< \brief (EVSYS_USER reset_value) User Multiplexer */
144
145#define EVSYS_USER_USER_Pos 0 /**< \brief (EVSYS_USER) User Multiplexer Selection */
146#define EVSYS_USER_USER_Msk (0x1Fu << EVSYS_USER_USER_Pos)
147#define EVSYS_USER_USER(value) ((EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos)))
148#define EVSYS_USER_CHANNEL_Pos 8 /**< \brief (EVSYS_USER) Channel Event Selection */
149#define EVSYS_USER_CHANNEL_Msk (0x1Fu << EVSYS_USER_CHANNEL_Pos)
150#define EVSYS_USER_CHANNEL(value) ((EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos)))
151#define EVSYS_USER_CHANNEL_0_Val 0x0u /**< \brief (EVSYS_USER) No Channel Output Selected */
152#define EVSYS_USER_CHANNEL_0 (EVSYS_USER_CHANNEL_0_Val << EVSYS_USER_CHANNEL_Pos)
153#define EVSYS_USER_MASK 0x1F1Fu /**< \brief (EVSYS_USER) MASK Register */
154
155/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */
156#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
157typedef union {
158 struct {
159 uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */
160 uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */
161 uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */
162 uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
163 uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
164 uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
165 uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
166 uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
167 uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */
168 uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */
169 uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */
170 uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */
171 uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */
172 uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */
173 uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */
174 uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */
175 uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */
176 uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */
177 uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */
178 uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */
179 uint32_t :4; /*!< bit: 20..23 Reserved */
180 uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */
181 uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */
182 uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */
183 uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */
184 uint32_t :4; /*!< bit: 28..31 Reserved */
185 } bit; /*!< Structure used for bit access */
186 struct {
187 uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */
188 uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */
189 uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */
190 uint32_t :4; /*!< bit: 20..23 Reserved */
191 uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */
192 uint32_t :4; /*!< bit: 28..31 Reserved */
193 } vec; /*!< Structure used for vec access */
194 uint32_t reg; /*!< Type used for register access */
195} EVSYS_CHSTATUS_Type;
196#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
197
198#define EVSYS_CHSTATUS_OFFSET 0x0C /**< \brief (EVSYS_CHSTATUS offset) Channel Status */
199#define EVSYS_CHSTATUS_RESETVALUE 0x000F00FF /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */
200
201#define EVSYS_CHSTATUS_USRRDY0_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */
202#define EVSYS_CHSTATUS_USRRDY0 (1 << EVSYS_CHSTATUS_USRRDY0_Pos)
203#define EVSYS_CHSTATUS_USRRDY1_Pos 1 /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */
204#define EVSYS_CHSTATUS_USRRDY1 (1 << EVSYS_CHSTATUS_USRRDY1_Pos)
205#define EVSYS_CHSTATUS_USRRDY2_Pos 2 /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */
206#define EVSYS_CHSTATUS_USRRDY2 (1 << EVSYS_CHSTATUS_USRRDY2_Pos)
207#define EVSYS_CHSTATUS_USRRDY3_Pos 3 /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */
208#define EVSYS_CHSTATUS_USRRDY3 (1 << EVSYS_CHSTATUS_USRRDY3_Pos)
209#define EVSYS_CHSTATUS_USRRDY4_Pos 4 /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */
210#define EVSYS_CHSTATUS_USRRDY4 (1 << EVSYS_CHSTATUS_USRRDY4_Pos)
211#define EVSYS_CHSTATUS_USRRDY5_Pos 5 /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */
212#define EVSYS_CHSTATUS_USRRDY5 (1 << EVSYS_CHSTATUS_USRRDY5_Pos)
213#define EVSYS_CHSTATUS_USRRDY6_Pos 6 /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */
214#define EVSYS_CHSTATUS_USRRDY6 (1 << EVSYS_CHSTATUS_USRRDY6_Pos)
215#define EVSYS_CHSTATUS_USRRDY7_Pos 7 /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */
216#define EVSYS_CHSTATUS_USRRDY7 (1 << EVSYS_CHSTATUS_USRRDY7_Pos)
217#define EVSYS_CHSTATUS_USRRDY_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */
218#define EVSYS_CHSTATUS_USRRDY_Msk (0xFFu << EVSYS_CHSTATUS_USRRDY_Pos)
219#define EVSYS_CHSTATUS_USRRDY(value) ((EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos)))
220#define EVSYS_CHSTATUS_CHBUSY0_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */
221#define EVSYS_CHSTATUS_CHBUSY0 (1 << EVSYS_CHSTATUS_CHBUSY0_Pos)
222#define EVSYS_CHSTATUS_CHBUSY1_Pos 9 /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */
223#define EVSYS_CHSTATUS_CHBUSY1 (1 << EVSYS_CHSTATUS_CHBUSY1_Pos)
224#define EVSYS_CHSTATUS_CHBUSY2_Pos 10 /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */
225#define EVSYS_CHSTATUS_CHBUSY2 (1 << EVSYS_CHSTATUS_CHBUSY2_Pos)
226#define EVSYS_CHSTATUS_CHBUSY3_Pos 11 /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */
227#define EVSYS_CHSTATUS_CHBUSY3 (1 << EVSYS_CHSTATUS_CHBUSY3_Pos)
228#define EVSYS_CHSTATUS_CHBUSY4_Pos 12 /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */
229#define EVSYS_CHSTATUS_CHBUSY4 (1 << EVSYS_CHSTATUS_CHBUSY4_Pos)
230#define EVSYS_CHSTATUS_CHBUSY5_Pos 13 /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */
231#define EVSYS_CHSTATUS_CHBUSY5 (1 << EVSYS_CHSTATUS_CHBUSY5_Pos)
232#define EVSYS_CHSTATUS_CHBUSY6_Pos 14 /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */
233#define EVSYS_CHSTATUS_CHBUSY6 (1 << EVSYS_CHSTATUS_CHBUSY6_Pos)
234#define EVSYS_CHSTATUS_CHBUSY7_Pos 15 /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */
235#define EVSYS_CHSTATUS_CHBUSY7 (1 << EVSYS_CHSTATUS_CHBUSY7_Pos)
236#define EVSYS_CHSTATUS_CHBUSY_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel x Busy */
237#define EVSYS_CHSTATUS_CHBUSY_Msk (0xFFu << EVSYS_CHSTATUS_CHBUSY_Pos)
238#define EVSYS_CHSTATUS_CHBUSY(value) ((EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos)))
239#define EVSYS_CHSTATUS_USRRDY8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */
240#define EVSYS_CHSTATUS_USRRDY8 (1 << EVSYS_CHSTATUS_USRRDY8_Pos)
241#define EVSYS_CHSTATUS_USRRDY9_Pos 17 /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */
242#define EVSYS_CHSTATUS_USRRDY9 (1 << EVSYS_CHSTATUS_USRRDY9_Pos)
243#define EVSYS_CHSTATUS_USRRDY10_Pos 18 /**< \brief (EVSYS_CHSTATUS) Channel 10 User Ready */
244#define EVSYS_CHSTATUS_USRRDY10 (1 << EVSYS_CHSTATUS_USRRDY10_Pos)
245#define EVSYS_CHSTATUS_USRRDY11_Pos 19 /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */
246#define EVSYS_CHSTATUS_USRRDY11 (1 << EVSYS_CHSTATUS_USRRDY11_Pos)
247#define EVSYS_CHSTATUS_USRRDYp8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel x+8 User Ready */
248#define EVSYS_CHSTATUS_USRRDYp8_Msk (0xFu << EVSYS_CHSTATUS_USRRDYp8_Pos)
249#define EVSYS_CHSTATUS_USRRDYp8(value) ((EVSYS_CHSTATUS_USRRDYp8_Msk & ((value) << EVSYS_CHSTATUS_USRRDYp8_Pos)))
250#define EVSYS_CHSTATUS_CHBUSY8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */
251#define EVSYS_CHSTATUS_CHBUSY8 (1 << EVSYS_CHSTATUS_CHBUSY8_Pos)
252#define EVSYS_CHSTATUS_CHBUSY9_Pos 25 /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */
253#define EVSYS_CHSTATUS_CHBUSY9 (1 << EVSYS_CHSTATUS_CHBUSY9_Pos)
254#define EVSYS_CHSTATUS_CHBUSY10_Pos 26 /**< \brief (EVSYS_CHSTATUS) Channel 10 Busy */
255#define EVSYS_CHSTATUS_CHBUSY10 (1 << EVSYS_CHSTATUS_CHBUSY10_Pos)
256#define EVSYS_CHSTATUS_CHBUSY11_Pos 27 /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */
257#define EVSYS_CHSTATUS_CHBUSY11 (1 << EVSYS_CHSTATUS_CHBUSY11_Pos)
258#define EVSYS_CHSTATUS_CHBUSYp8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel x+8 Busy */
259#define EVSYS_CHSTATUS_CHBUSYp8_Msk (0xFu << EVSYS_CHSTATUS_CHBUSYp8_Pos)
260#define EVSYS_CHSTATUS_CHBUSYp8(value) ((EVSYS_CHSTATUS_CHBUSYp8_Msk & ((value) << EVSYS_CHSTATUS_CHBUSYp8_Pos)))
261#define EVSYS_CHSTATUS_MASK 0x0F0FFFFFu /**< \brief (EVSYS_CHSTATUS) MASK Register */
262
263/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
264#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
265typedef union {
266 struct {
267 uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
268 uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
269 uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
270 uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
271 uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
272 uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
273 uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
274 uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
275 uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
276 uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
277 uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
278 uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
279 uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
280 uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
281 uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
282 uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
283 uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
284 uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
285 uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
286 uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
287 uint32_t :4; /*!< bit: 20..23 Reserved */
288 uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
289 uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
290 uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
291 uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
292 uint32_t :4; /*!< bit: 28..31 Reserved */
293 } bit; /*!< Structure used for bit access */
294 struct {
295 uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
296 uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
297 uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
298 uint32_t :4; /*!< bit: 20..23 Reserved */
299 uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
300 uint32_t :4; /*!< bit: 28..31 Reserved */
301 } vec; /*!< Structure used for vec access */
302 uint32_t reg; /*!< Type used for register access */
303} EVSYS_INTENCLR_Type;
304#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
305
306#define EVSYS_INTENCLR_OFFSET 0x10 /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */
307#define EVSYS_INTENCLR_RESETVALUE 0x00000000 /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */
308
309#define EVSYS_INTENCLR_OVR0_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */
310#define EVSYS_INTENCLR_OVR0 (1 << EVSYS_INTENCLR_OVR0_Pos)
311#define EVSYS_INTENCLR_OVR1_Pos 1 /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */
312#define EVSYS_INTENCLR_OVR1 (1 << EVSYS_INTENCLR_OVR1_Pos)
313#define EVSYS_INTENCLR_OVR2_Pos 2 /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */
314#define EVSYS_INTENCLR_OVR2 (1 << EVSYS_INTENCLR_OVR2_Pos)
315#define EVSYS_INTENCLR_OVR3_Pos 3 /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */
316#define EVSYS_INTENCLR_OVR3 (1 << EVSYS_INTENCLR_OVR3_Pos)
317#define EVSYS_INTENCLR_OVR4_Pos 4 /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */
318#define EVSYS_INTENCLR_OVR4 (1 << EVSYS_INTENCLR_OVR4_Pos)
319#define EVSYS_INTENCLR_OVR5_Pos 5 /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */
320#define EVSYS_INTENCLR_OVR5 (1 << EVSYS_INTENCLR_OVR5_Pos)
321#define EVSYS_INTENCLR_OVR6_Pos 6 /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */
322#define EVSYS_INTENCLR_OVR6 (1 << EVSYS_INTENCLR_OVR6_Pos)
323#define EVSYS_INTENCLR_OVR7_Pos 7 /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */
324#define EVSYS_INTENCLR_OVR7 (1 << EVSYS_INTENCLR_OVR7_Pos)
325#define EVSYS_INTENCLR_OVR_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */
326#define EVSYS_INTENCLR_OVR_Msk (0xFFu << EVSYS_INTENCLR_OVR_Pos)
327#define EVSYS_INTENCLR_OVR(value) ((EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos)))
328#define EVSYS_INTENCLR_EVD0_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */
329#define EVSYS_INTENCLR_EVD0 (1 << EVSYS_INTENCLR_EVD0_Pos)
330#define EVSYS_INTENCLR_EVD1_Pos 9 /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */
331#define EVSYS_INTENCLR_EVD1 (1 << EVSYS_INTENCLR_EVD1_Pos)
332#define EVSYS_INTENCLR_EVD2_Pos 10 /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */
333#define EVSYS_INTENCLR_EVD2 (1 << EVSYS_INTENCLR_EVD2_Pos)
334#define EVSYS_INTENCLR_EVD3_Pos 11 /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */
335#define EVSYS_INTENCLR_EVD3 (1 << EVSYS_INTENCLR_EVD3_Pos)
336#define EVSYS_INTENCLR_EVD4_Pos 12 /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */
337#define EVSYS_INTENCLR_EVD4 (1 << EVSYS_INTENCLR_EVD4_Pos)
338#define EVSYS_INTENCLR_EVD5_Pos 13 /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */
339#define EVSYS_INTENCLR_EVD5 (1 << EVSYS_INTENCLR_EVD5_Pos)
340#define EVSYS_INTENCLR_EVD6_Pos 14 /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */
341#define EVSYS_INTENCLR_EVD6 (1 << EVSYS_INTENCLR_EVD6_Pos)
342#define EVSYS_INTENCLR_EVD7_Pos 15 /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */
343#define EVSYS_INTENCLR_EVD7 (1 << EVSYS_INTENCLR_EVD7_Pos)
344#define EVSYS_INTENCLR_EVD_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */
345#define EVSYS_INTENCLR_EVD_Msk (0xFFu << EVSYS_INTENCLR_EVD_Pos)
346#define EVSYS_INTENCLR_EVD(value) ((EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos)))
347#define EVSYS_INTENCLR_OVR8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */
348#define EVSYS_INTENCLR_OVR8 (1 << EVSYS_INTENCLR_OVR8_Pos)
349#define EVSYS_INTENCLR_OVR9_Pos 17 /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */
350#define EVSYS_INTENCLR_OVR9 (1 << EVSYS_INTENCLR_OVR9_Pos)
351#define EVSYS_INTENCLR_OVR10_Pos 18 /**< \brief (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable */
352#define EVSYS_INTENCLR_OVR10 (1 << EVSYS_INTENCLR_OVR10_Pos)
353#define EVSYS_INTENCLR_OVR11_Pos 19 /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */
354#define EVSYS_INTENCLR_OVR11 (1 << EVSYS_INTENCLR_OVR11_Pos)
355#define EVSYS_INTENCLR_OVRp8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel x+8 Overrun Interrupt Enable */
356#define EVSYS_INTENCLR_OVRp8_Msk (0xFu << EVSYS_INTENCLR_OVRp8_Pos)
357#define EVSYS_INTENCLR_OVRp8(value) ((EVSYS_INTENCLR_OVRp8_Msk & ((value) << EVSYS_INTENCLR_OVRp8_Pos)))
358#define EVSYS_INTENCLR_EVD8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */
359#define EVSYS_INTENCLR_EVD8 (1 << EVSYS_INTENCLR_EVD8_Pos)
360#define EVSYS_INTENCLR_EVD9_Pos 25 /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */
361#define EVSYS_INTENCLR_EVD9 (1 << EVSYS_INTENCLR_EVD9_Pos)
362#define EVSYS_INTENCLR_EVD10_Pos 26 /**< \brief (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable */
363#define EVSYS_INTENCLR_EVD10 (1 << EVSYS_INTENCLR_EVD10_Pos)
364#define EVSYS_INTENCLR_EVD11_Pos 27 /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */
365#define EVSYS_INTENCLR_EVD11 (1 << EVSYS_INTENCLR_EVD11_Pos)
366#define EVSYS_INTENCLR_EVDp8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel x+8 Event Detection Interrupt Enable */
367#define EVSYS_INTENCLR_EVDp8_Msk (0xFu << EVSYS_INTENCLR_EVDp8_Pos)
368#define EVSYS_INTENCLR_EVDp8(value) ((EVSYS_INTENCLR_EVDp8_Msk & ((value) << EVSYS_INTENCLR_EVDp8_Pos)))
369#define EVSYS_INTENCLR_MASK 0x0F0FFFFFu /**< \brief (EVSYS_INTENCLR) MASK Register */
370
371/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
372#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
373typedef union {
374 struct {
375 uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
376 uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
377 uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
378 uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
379 uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
380 uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
381 uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
382 uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
383 uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
384 uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
385 uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
386 uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
387 uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
388 uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
389 uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
390 uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
391 uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
392 uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
393 uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
394 uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
395 uint32_t :4; /*!< bit: 20..23 Reserved */
396 uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
397 uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
398 uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
399 uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
400 uint32_t :4; /*!< bit: 28..31 Reserved */
401 } bit; /*!< Structure used for bit access */
402 struct {
403 uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
404 uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
405 uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
406 uint32_t :4; /*!< bit: 20..23 Reserved */
407 uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
408 uint32_t :4; /*!< bit: 28..31 Reserved */
409 } vec; /*!< Structure used for vec access */
410 uint32_t reg; /*!< Type used for register access */
411} EVSYS_INTENSET_Type;
412#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
413
414#define EVSYS_INTENSET_OFFSET 0x14 /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */
415#define EVSYS_INTENSET_RESETVALUE 0x00000000 /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */
416
417#define EVSYS_INTENSET_OVR0_Pos 0 /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */
418#define EVSYS_INTENSET_OVR0 (1 << EVSYS_INTENSET_OVR0_Pos)
419#define EVSYS_INTENSET_OVR1_Pos 1 /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */
420#define EVSYS_INTENSET_OVR1 (1 << EVSYS_INTENSET_OVR1_Pos)
421#define EVSYS_INTENSET_OVR2_Pos 2 /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */
422#define EVSYS_INTENSET_OVR2 (1 << EVSYS_INTENSET_OVR2_Pos)
423#define EVSYS_INTENSET_OVR3_Pos 3 /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */
424#define EVSYS_INTENSET_OVR3 (1 << EVSYS_INTENSET_OVR3_Pos)
425#define EVSYS_INTENSET_OVR4_Pos 4 /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */
426#define EVSYS_INTENSET_OVR4 (1 << EVSYS_INTENSET_OVR4_Pos)
427#define EVSYS_INTENSET_OVR5_Pos 5 /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */
428#define EVSYS_INTENSET_OVR5 (1 << EVSYS_INTENSET_OVR5_Pos)
429#define EVSYS_INTENSET_OVR6_Pos 6 /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */
430#define EVSYS_INTENSET_OVR6 (1 << EVSYS_INTENSET_OVR6_Pos)
431#define EVSYS_INTENSET_OVR7_Pos 7 /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */
432#define EVSYS_INTENSET_OVR7 (1 << EVSYS_INTENSET_OVR7_Pos)
433#define EVSYS_INTENSET_OVR_Pos 0 /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */
434#define EVSYS_INTENSET_OVR_Msk (0xFFu << EVSYS_INTENSET_OVR_Pos)
435#define EVSYS_INTENSET_OVR(value) ((EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos)))
436#define EVSYS_INTENSET_EVD0_Pos 8 /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */
437#define EVSYS_INTENSET_EVD0 (1 << EVSYS_INTENSET_EVD0_Pos)
438#define EVSYS_INTENSET_EVD1_Pos 9 /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */
439#define EVSYS_INTENSET_EVD1 (1 << EVSYS_INTENSET_EVD1_Pos)
440#define EVSYS_INTENSET_EVD2_Pos 10 /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */
441#define EVSYS_INTENSET_EVD2 (1 << EVSYS_INTENSET_EVD2_Pos)
442#define EVSYS_INTENSET_EVD3_Pos 11 /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */
443#define EVSYS_INTENSET_EVD3 (1 << EVSYS_INTENSET_EVD3_Pos)
444#define EVSYS_INTENSET_EVD4_Pos 12 /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */
445#define EVSYS_INTENSET_EVD4 (1 << EVSYS_INTENSET_EVD4_Pos)
446#define EVSYS_INTENSET_EVD5_Pos 13 /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */
447#define EVSYS_INTENSET_EVD5 (1 << EVSYS_INTENSET_EVD5_Pos)
448#define EVSYS_INTENSET_EVD6_Pos 14 /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */
449#define EVSYS_INTENSET_EVD6 (1 << EVSYS_INTENSET_EVD6_Pos)
450#define EVSYS_INTENSET_EVD7_Pos 15 /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */
451#define EVSYS_INTENSET_EVD7 (1 << EVSYS_INTENSET_EVD7_Pos)
452#define EVSYS_INTENSET_EVD_Pos 8 /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */
453#define EVSYS_INTENSET_EVD_Msk (0xFFu << EVSYS_INTENSET_EVD_Pos)
454#define EVSYS_INTENSET_EVD(value) ((EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos)))
455#define EVSYS_INTENSET_OVR8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */
456#define EVSYS_INTENSET_OVR8 (1 << EVSYS_INTENSET_OVR8_Pos)
457#define EVSYS_INTENSET_OVR9_Pos 17 /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */
458#define EVSYS_INTENSET_OVR9 (1 << EVSYS_INTENSET_OVR9_Pos)
459#define EVSYS_INTENSET_OVR10_Pos 18 /**< \brief (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable */
460#define EVSYS_INTENSET_OVR10 (1 << EVSYS_INTENSET_OVR10_Pos)
461#define EVSYS_INTENSET_OVR11_Pos 19 /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */
462#define EVSYS_INTENSET_OVR11 (1 << EVSYS_INTENSET_OVR11_Pos)
463#define EVSYS_INTENSET_OVRp8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel x+8 Overrun Interrupt Enable */
464#define EVSYS_INTENSET_OVRp8_Msk (0xFu << EVSYS_INTENSET_OVRp8_Pos)
465#define EVSYS_INTENSET_OVRp8(value) ((EVSYS_INTENSET_OVRp8_Msk & ((value) << EVSYS_INTENSET_OVRp8_Pos)))
466#define EVSYS_INTENSET_EVD8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */
467#define EVSYS_INTENSET_EVD8 (1 << EVSYS_INTENSET_EVD8_Pos)
468#define EVSYS_INTENSET_EVD9_Pos 25 /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */
469#define EVSYS_INTENSET_EVD9 (1 << EVSYS_INTENSET_EVD9_Pos)
470#define EVSYS_INTENSET_EVD10_Pos 26 /**< \brief (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable */
471#define EVSYS_INTENSET_EVD10 (1 << EVSYS_INTENSET_EVD10_Pos)
472#define EVSYS_INTENSET_EVD11_Pos 27 /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */
473#define EVSYS_INTENSET_EVD11 (1 << EVSYS_INTENSET_EVD11_Pos)
474#define EVSYS_INTENSET_EVDp8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel x+8 Event Detection Interrupt Enable */
475#define EVSYS_INTENSET_EVDp8_Msk (0xFu << EVSYS_INTENSET_EVDp8_Pos)
476#define EVSYS_INTENSET_EVDp8(value) ((EVSYS_INTENSET_EVDp8_Msk & ((value) << EVSYS_INTENSET_EVDp8_Pos)))
477#define EVSYS_INTENSET_MASK 0x0F0FFFFFu /**< \brief (EVSYS_INTENSET) MASK Register */
478
479/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
480#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
481typedef union {
482 struct {
483 uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
484 uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
485 uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
486 uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
487 uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
488 uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
489 uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
490 uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
491 uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
492 uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
493 uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
494 uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
495 uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
496 uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
497 uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
498 uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
499 uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
500 uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
501 uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
502 uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
503 uint32_t :4; /*!< bit: 20..23 Reserved */
504 uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
505 uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
506 uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
507 uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
508 uint32_t :4; /*!< bit: 28..31 Reserved */
509 } bit; /*!< Structure used for bit access */
510 struct {
511 uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
512 uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
513 uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
514 uint32_t :4; /*!< bit: 20..23 Reserved */
515 uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
516 uint32_t :4; /*!< bit: 28..31 Reserved */
517 } vec; /*!< Structure used for vec access */
518 uint32_t reg; /*!< Type used for register access */
519} EVSYS_INTFLAG_Type;
520#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
521
522#define EVSYS_INTFLAG_OFFSET 0x18 /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */
523#define EVSYS_INTFLAG_RESETVALUE 0x00000000 /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */
524
525#define EVSYS_INTFLAG_OVR0_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */
526#define EVSYS_INTFLAG_OVR0 (1 << EVSYS_INTFLAG_OVR0_Pos)
527#define EVSYS_INTFLAG_OVR1_Pos 1 /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */
528#define EVSYS_INTFLAG_OVR1 (1 << EVSYS_INTFLAG_OVR1_Pos)
529#define EVSYS_INTFLAG_OVR2_Pos 2 /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */
530#define EVSYS_INTFLAG_OVR2 (1 << EVSYS_INTFLAG_OVR2_Pos)
531#define EVSYS_INTFLAG_OVR3_Pos 3 /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */
532#define EVSYS_INTFLAG_OVR3 (1 << EVSYS_INTFLAG_OVR3_Pos)
533#define EVSYS_INTFLAG_OVR4_Pos 4 /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */
534#define EVSYS_INTFLAG_OVR4 (1 << EVSYS_INTFLAG_OVR4_Pos)
535#define EVSYS_INTFLAG_OVR5_Pos 5 /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */
536#define EVSYS_INTFLAG_OVR5 (1 << EVSYS_INTFLAG_OVR5_Pos)
537#define EVSYS_INTFLAG_OVR6_Pos 6 /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */
538#define EVSYS_INTFLAG_OVR6 (1 << EVSYS_INTFLAG_OVR6_Pos)
539#define EVSYS_INTFLAG_OVR7_Pos 7 /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */
540#define EVSYS_INTFLAG_OVR7 (1 << EVSYS_INTFLAG_OVR7_Pos)
541#define EVSYS_INTFLAG_OVR_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel x Overrun */
542#define EVSYS_INTFLAG_OVR_Msk (0xFFu << EVSYS_INTFLAG_OVR_Pos)
543#define EVSYS_INTFLAG_OVR(value) ((EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos)))
544#define EVSYS_INTFLAG_EVD0_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */
545#define EVSYS_INTFLAG_EVD0 (1 << EVSYS_INTFLAG_EVD0_Pos)
546#define EVSYS_INTFLAG_EVD1_Pos 9 /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */
547#define EVSYS_INTFLAG_EVD1 (1 << EVSYS_INTFLAG_EVD1_Pos)
548#define EVSYS_INTFLAG_EVD2_Pos 10 /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */
549#define EVSYS_INTFLAG_EVD2 (1 << EVSYS_INTFLAG_EVD2_Pos)
550#define EVSYS_INTFLAG_EVD3_Pos 11 /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */
551#define EVSYS_INTFLAG_EVD3 (1 << EVSYS_INTFLAG_EVD3_Pos)
552#define EVSYS_INTFLAG_EVD4_Pos 12 /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */
553#define EVSYS_INTFLAG_EVD4 (1 << EVSYS_INTFLAG_EVD4_Pos)
554#define EVSYS_INTFLAG_EVD5_Pos 13 /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */
555#define EVSYS_INTFLAG_EVD5 (1 << EVSYS_INTFLAG_EVD5_Pos)
556#define EVSYS_INTFLAG_EVD6_Pos 14 /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */
557#define EVSYS_INTFLAG_EVD6 (1 << EVSYS_INTFLAG_EVD6_Pos)
558#define EVSYS_INTFLAG_EVD7_Pos 15 /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */
559#define EVSYS_INTFLAG_EVD7 (1 << EVSYS_INTFLAG_EVD7_Pos)
560#define EVSYS_INTFLAG_EVD_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */
561#define EVSYS_INTFLAG_EVD_Msk (0xFFu << EVSYS_INTFLAG_EVD_Pos)
562#define EVSYS_INTFLAG_EVD(value) ((EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos)))
563#define EVSYS_INTFLAG_OVR8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */
564#define EVSYS_INTFLAG_OVR8 (1 << EVSYS_INTFLAG_OVR8_Pos)
565#define EVSYS_INTFLAG_OVR9_Pos 17 /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */
566#define EVSYS_INTFLAG_OVR9 (1 << EVSYS_INTFLAG_OVR9_Pos)
567#define EVSYS_INTFLAG_OVR10_Pos 18 /**< \brief (EVSYS_INTFLAG) Channel 10 Overrun */
568#define EVSYS_INTFLAG_OVR10 (1 << EVSYS_INTFLAG_OVR10_Pos)
569#define EVSYS_INTFLAG_OVR11_Pos 19 /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */
570#define EVSYS_INTFLAG_OVR11 (1 << EVSYS_INTFLAG_OVR11_Pos)
571#define EVSYS_INTFLAG_OVRp8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel x+8 Overrun */
572#define EVSYS_INTFLAG_OVRp8_Msk (0xFu << EVSYS_INTFLAG_OVRp8_Pos)
573#define EVSYS_INTFLAG_OVRp8(value) ((EVSYS_INTFLAG_OVRp8_Msk & ((value) << EVSYS_INTFLAG_OVRp8_Pos)))
574#define EVSYS_INTFLAG_EVD8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */
575#define EVSYS_INTFLAG_EVD8 (1 << EVSYS_INTFLAG_EVD8_Pos)
576#define EVSYS_INTFLAG_EVD9_Pos 25 /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */
577#define EVSYS_INTFLAG_EVD9 (1 << EVSYS_INTFLAG_EVD9_Pos)
578#define EVSYS_INTFLAG_EVD10_Pos 26 /**< \brief (EVSYS_INTFLAG) Channel 10 Event Detection */
579#define EVSYS_INTFLAG_EVD10 (1 << EVSYS_INTFLAG_EVD10_Pos)
580#define EVSYS_INTFLAG_EVD11_Pos 27 /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */
581#define EVSYS_INTFLAG_EVD11 (1 << EVSYS_INTFLAG_EVD11_Pos)
582#define EVSYS_INTFLAG_EVDp8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel x+8 Event Detection */
583#define EVSYS_INTFLAG_EVDp8_Msk (0xFu << EVSYS_INTFLAG_EVDp8_Pos)
584#define EVSYS_INTFLAG_EVDp8(value) ((EVSYS_INTFLAG_EVDp8_Msk & ((value) << EVSYS_INTFLAG_EVDp8_Pos)))
585#define EVSYS_INTFLAG_MASK 0x0F0FFFFFu /**< \brief (EVSYS_INTFLAG) MASK Register */
586
587/** \brief EVSYS hardware registers */
588#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
589typedef struct {
590 __O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */
591 RoReg8 Reserved1[0x3];
592 __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */
593 __IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
594 RoReg8 Reserved2[0x2];
595 __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */
596 __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
597 __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
598 __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
599} Evsys;
600#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
601
602/*@}*/
603
604#endif /* _SAMD21_EVSYS_COMPONENT_ */
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