1 | /**
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2 | * \file
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3 | *
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4 | * \brief Component description for EIC
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5 | *
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6 | * Copyright (c) 2014 Atmel Corporation. All rights reserved.
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7 | *
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8 | * \asf_license_start
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9 | *
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10 | * \page License
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11 | *
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12 | * Redistribution and use in source and binary forms, with or without
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13 | * modification, are permitted provided that the following conditions are met:
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14 | *
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15 | * 1. Redistributions of source code must retain the above copyright notice,
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16 | * this list of conditions and the following disclaimer.
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17 | *
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18 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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19 | * this list of conditions and the following disclaimer in the documentation
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20 | * and/or other materials provided with the distribution.
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21 | *
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22 | * 3. The name of Atmel may not be used to endorse or promote products derived
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23 | * from this software without specific prior written permission.
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24 | *
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25 | * 4. This software may only be redistributed and used in connection with an
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26 | * Atmel microcontroller product.
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27 | *
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28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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38 | * POSSIBILITY OF SUCH DAMAGE.
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39 | *
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40 | * \asf_license_stop
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41 | *
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42 | */
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43 |
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44 | #ifndef _SAMD21_EIC_COMPONENT_
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45 | #define _SAMD21_EIC_COMPONENT_
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46 |
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47 | /* ========================================================================== */
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48 | /** SOFTWARE API DEFINITION FOR EIC */
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49 | /* ========================================================================== */
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50 | /** \addtogroup SAMD21_EIC External Interrupt Controller */
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51 | /*@{*/
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52 |
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53 | #define EIC_U2217
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54 | #define REV_EIC 0x101
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55 |
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56 | /* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W 8) Control -------- */
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57 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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58 | typedef union {
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59 | struct {
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60 | uint8_t SWRST:1; /*!< bit: 0 Software Reset */
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61 | uint8_t ENABLE:1; /*!< bit: 1 Enable */
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62 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
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63 | } bit; /*!< Structure used for bit access */
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64 | uint8_t reg; /*!< Type used for register access */
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65 | } EIC_CTRL_Type;
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66 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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67 |
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68 | #define EIC_CTRL_OFFSET 0x00 /**< \brief (EIC_CTRL offset) Control */
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69 | #define EIC_CTRL_RESETVALUE 0x00 /**< \brief (EIC_CTRL reset_value) Control */
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70 |
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71 | #define EIC_CTRL_SWRST_Pos 0 /**< \brief (EIC_CTRL) Software Reset */
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72 | #define EIC_CTRL_SWRST (0x1u << EIC_CTRL_SWRST_Pos)
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73 | #define EIC_CTRL_ENABLE_Pos 1 /**< \brief (EIC_CTRL) Enable */
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74 | #define EIC_CTRL_ENABLE (0x1u << EIC_CTRL_ENABLE_Pos)
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75 | #define EIC_CTRL_MASK 0x03u /**< \brief (EIC_CTRL) MASK Register */
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76 |
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77 | /* -------- EIC_STATUS : (EIC Offset: 0x01) (R/ 8) Status -------- */
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78 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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79 | typedef union {
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80 | struct {
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81 | uint8_t :7; /*!< bit: 0.. 6 Reserved */
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82 | uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
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83 | } bit; /*!< Structure used for bit access */
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84 | uint8_t reg; /*!< Type used for register access */
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85 | } EIC_STATUS_Type;
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86 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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87 |
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88 | #define EIC_STATUS_OFFSET 0x01 /**< \brief (EIC_STATUS offset) Status */
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89 | #define EIC_STATUS_RESETVALUE 0x00 /**< \brief (EIC_STATUS reset_value) Status */
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90 |
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91 | #define EIC_STATUS_SYNCBUSY_Pos 7 /**< \brief (EIC_STATUS) Synchronization Busy */
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92 | #define EIC_STATUS_SYNCBUSY (0x1u << EIC_STATUS_SYNCBUSY_Pos)
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93 | #define EIC_STATUS_MASK 0x80u /**< \brief (EIC_STATUS) MASK Register */
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94 |
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95 | /* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W 8) Non-Maskable Interrupt Control -------- */
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96 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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97 | typedef union {
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98 | struct {
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99 | uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */
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100 | uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
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101 | uint8_t :4; /*!< bit: 4.. 7 Reserved */
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102 | } bit; /*!< Structure used for bit access */
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103 | uint8_t reg; /*!< Type used for register access */
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104 | } EIC_NMICTRL_Type;
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105 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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106 |
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107 | #define EIC_NMICTRL_OFFSET 0x02 /**< \brief (EIC_NMICTRL offset) Non-Maskable Interrupt Control */
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108 | #define EIC_NMICTRL_RESETVALUE 0x00 /**< \brief (EIC_NMICTRL reset_value) Non-Maskable Interrupt Control */
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109 |
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110 | #define EIC_NMICTRL_NMISENSE_Pos 0 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense */
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111 | #define EIC_NMICTRL_NMISENSE_Msk (0x7u << EIC_NMICTRL_NMISENSE_Pos)
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112 | #define EIC_NMICTRL_NMISENSE(value) ((EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos)))
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113 | #define EIC_NMICTRL_NMISENSE_NONE_Val 0x0u /**< \brief (EIC_NMICTRL) No detection */
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114 | #define EIC_NMICTRL_NMISENSE_RISE_Val 0x1u /**< \brief (EIC_NMICTRL) Rising-edge detection */
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115 | #define EIC_NMICTRL_NMISENSE_FALL_Val 0x2u /**< \brief (EIC_NMICTRL) Falling-edge detection */
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116 | #define EIC_NMICTRL_NMISENSE_BOTH_Val 0x3u /**< \brief (EIC_NMICTRL) Both-edges detection */
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117 | #define EIC_NMICTRL_NMISENSE_HIGH_Val 0x4u /**< \brief (EIC_NMICTRL) High-level detection */
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118 | #define EIC_NMICTRL_NMISENSE_LOW_Val 0x5u /**< \brief (EIC_NMICTRL) Low-level detection */
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119 | #define EIC_NMICTRL_NMISENSE_NONE (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos)
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120 | #define EIC_NMICTRL_NMISENSE_RISE (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos)
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121 | #define EIC_NMICTRL_NMISENSE_FALL (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos)
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122 | #define EIC_NMICTRL_NMISENSE_BOTH (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos)
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123 | #define EIC_NMICTRL_NMISENSE_HIGH (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos)
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124 | #define EIC_NMICTRL_NMISENSE_LOW (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos)
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125 | #define EIC_NMICTRL_NMIFILTEN_Pos 3 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable */
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126 | #define EIC_NMICTRL_NMIFILTEN (0x1u << EIC_NMICTRL_NMIFILTEN_Pos)
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127 | #define EIC_NMICTRL_MASK 0x0Fu /**< \brief (EIC_NMICTRL) MASK Register */
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128 |
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129 | /* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W 8) Non-Maskable Interrupt Flag Status and Clear -------- */
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130 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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131 | typedef union {
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132 | struct {
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133 | uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
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134 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
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135 | } bit; /*!< Structure used for bit access */
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136 | uint8_t reg; /*!< Type used for register access */
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137 | } EIC_NMIFLAG_Type;
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138 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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139 |
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140 | #define EIC_NMIFLAG_OFFSET 0x03 /**< \brief (EIC_NMIFLAG offset) Non-Maskable Interrupt Flag Status and Clear */
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141 | #define EIC_NMIFLAG_RESETVALUE 0x00 /**< \brief (EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear */
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142 |
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143 | #define EIC_NMIFLAG_NMI_Pos 0 /**< \brief (EIC_NMIFLAG) Non-Maskable Interrupt */
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144 | #define EIC_NMIFLAG_NMI (0x1u << EIC_NMIFLAG_NMI_Pos)
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145 | #define EIC_NMIFLAG_MASK 0x01u /**< \brief (EIC_NMIFLAG) MASK Register */
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146 |
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147 | /* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */
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148 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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149 | typedef union {
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150 | struct {
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151 | uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */
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152 | uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */
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153 | uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */
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154 | uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */
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155 | uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */
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156 | uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */
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157 | uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */
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158 | uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */
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159 | uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */
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160 | uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */
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161 | uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */
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162 | uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */
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163 | uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */
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164 | uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */
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165 | uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */
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166 | uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */
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167 | uint32_t :16; /*!< bit: 16..31 Reserved */
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168 | } bit; /*!< Structure used for bit access */
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169 | struct {
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170 | uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */
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171 | uint32_t :16; /*!< bit: 16..31 Reserved */
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172 | } vec; /*!< Structure used for vec access */
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173 | uint32_t reg; /*!< Type used for register access */
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174 | } EIC_EVCTRL_Type;
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175 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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176 |
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177 | #define EIC_EVCTRL_OFFSET 0x04 /**< \brief (EIC_EVCTRL offset) Event Control */
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178 | #define EIC_EVCTRL_RESETVALUE 0x00000000 /**< \brief (EIC_EVCTRL reset_value) Event Control */
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179 |
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180 | #define EIC_EVCTRL_EXTINTEO0_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt 0 Event Output Enable */
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181 | #define EIC_EVCTRL_EXTINTEO0 (1 << EIC_EVCTRL_EXTINTEO0_Pos)
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182 | #define EIC_EVCTRL_EXTINTEO1_Pos 1 /**< \brief (EIC_EVCTRL) External Interrupt 1 Event Output Enable */
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183 | #define EIC_EVCTRL_EXTINTEO1 (1 << EIC_EVCTRL_EXTINTEO1_Pos)
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184 | #define EIC_EVCTRL_EXTINTEO2_Pos 2 /**< \brief (EIC_EVCTRL) External Interrupt 2 Event Output Enable */
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185 | #define EIC_EVCTRL_EXTINTEO2 (1 << EIC_EVCTRL_EXTINTEO2_Pos)
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186 | #define EIC_EVCTRL_EXTINTEO3_Pos 3 /**< \brief (EIC_EVCTRL) External Interrupt 3 Event Output Enable */
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187 | #define EIC_EVCTRL_EXTINTEO3 (1 << EIC_EVCTRL_EXTINTEO3_Pos)
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188 | #define EIC_EVCTRL_EXTINTEO4_Pos 4 /**< \brief (EIC_EVCTRL) External Interrupt 4 Event Output Enable */
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189 | #define EIC_EVCTRL_EXTINTEO4 (1 << EIC_EVCTRL_EXTINTEO4_Pos)
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190 | #define EIC_EVCTRL_EXTINTEO5_Pos 5 /**< \brief (EIC_EVCTRL) External Interrupt 5 Event Output Enable */
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191 | #define EIC_EVCTRL_EXTINTEO5 (1 << EIC_EVCTRL_EXTINTEO5_Pos)
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192 | #define EIC_EVCTRL_EXTINTEO6_Pos 6 /**< \brief (EIC_EVCTRL) External Interrupt 6 Event Output Enable */
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193 | #define EIC_EVCTRL_EXTINTEO6 (1 << EIC_EVCTRL_EXTINTEO6_Pos)
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194 | #define EIC_EVCTRL_EXTINTEO7_Pos 7 /**< \brief (EIC_EVCTRL) External Interrupt 7 Event Output Enable */
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195 | #define EIC_EVCTRL_EXTINTEO7 (1 << EIC_EVCTRL_EXTINTEO7_Pos)
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196 | #define EIC_EVCTRL_EXTINTEO8_Pos 8 /**< \brief (EIC_EVCTRL) External Interrupt 8 Event Output Enable */
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197 | #define EIC_EVCTRL_EXTINTEO8 (1 << EIC_EVCTRL_EXTINTEO8_Pos)
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198 | #define EIC_EVCTRL_EXTINTEO9_Pos 9 /**< \brief (EIC_EVCTRL) External Interrupt 9 Event Output Enable */
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199 | #define EIC_EVCTRL_EXTINTEO9 (1 << EIC_EVCTRL_EXTINTEO9_Pos)
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200 | #define EIC_EVCTRL_EXTINTEO10_Pos 10 /**< \brief (EIC_EVCTRL) External Interrupt 10 Event Output Enable */
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201 | #define EIC_EVCTRL_EXTINTEO10 (1 << EIC_EVCTRL_EXTINTEO10_Pos)
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202 | #define EIC_EVCTRL_EXTINTEO11_Pos 11 /**< \brief (EIC_EVCTRL) External Interrupt 11 Event Output Enable */
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203 | #define EIC_EVCTRL_EXTINTEO11 (1 << EIC_EVCTRL_EXTINTEO11_Pos)
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204 | #define EIC_EVCTRL_EXTINTEO12_Pos 12 /**< \brief (EIC_EVCTRL) External Interrupt 12 Event Output Enable */
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205 | #define EIC_EVCTRL_EXTINTEO12 (1 << EIC_EVCTRL_EXTINTEO12_Pos)
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206 | #define EIC_EVCTRL_EXTINTEO13_Pos 13 /**< \brief (EIC_EVCTRL) External Interrupt 13 Event Output Enable */
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207 | #define EIC_EVCTRL_EXTINTEO13 (1 << EIC_EVCTRL_EXTINTEO13_Pos)
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208 | #define EIC_EVCTRL_EXTINTEO14_Pos 14 /**< \brief (EIC_EVCTRL) External Interrupt 14 Event Output Enable */
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209 | #define EIC_EVCTRL_EXTINTEO14 (1 << EIC_EVCTRL_EXTINTEO14_Pos)
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210 | #define EIC_EVCTRL_EXTINTEO15_Pos 15 /**< \brief (EIC_EVCTRL) External Interrupt 15 Event Output Enable */
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211 | #define EIC_EVCTRL_EXTINTEO15 (1 << EIC_EVCTRL_EXTINTEO15_Pos)
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212 | #define EIC_EVCTRL_EXTINTEO_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt x Event Output Enable */
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213 | #define EIC_EVCTRL_EXTINTEO_Msk (0xFFFFu << EIC_EVCTRL_EXTINTEO_Pos)
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214 | #define EIC_EVCTRL_EXTINTEO(value) ((EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos)))
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215 | #define EIC_EVCTRL_MASK 0x0000FFFFu /**< \brief (EIC_EVCTRL) MASK Register */
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216 |
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217 | /* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */
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218 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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219 | typedef union {
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220 | struct {
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221 | uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
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222 | uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
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223 | uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
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224 | uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
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225 | uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
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226 | uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
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227 | uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
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228 | uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
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229 | uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
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230 | uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
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231 | uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
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232 | uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
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233 | uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
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234 | uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
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235 | uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
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236 | uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
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237 | uint32_t :16; /*!< bit: 16..31 Reserved */
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238 | } bit; /*!< Structure used for bit access */
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239 | struct {
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240 | uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
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241 | uint32_t :16; /*!< bit: 16..31 Reserved */
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242 | } vec; /*!< Structure used for vec access */
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243 | uint32_t reg; /*!< Type used for register access */
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244 | } EIC_INTENCLR_Type;
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245 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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246 |
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247 | #define EIC_INTENCLR_OFFSET 0x08 /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */
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248 | #define EIC_INTENCLR_RESETVALUE 0x00000000 /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */
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249 |
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250 | #define EIC_INTENCLR_EXTINT0_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt 0 Enable */
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251 | #define EIC_INTENCLR_EXTINT0 (1 << EIC_INTENCLR_EXTINT0_Pos)
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252 | #define EIC_INTENCLR_EXTINT1_Pos 1 /**< \brief (EIC_INTENCLR) External Interrupt 1 Enable */
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253 | #define EIC_INTENCLR_EXTINT1 (1 << EIC_INTENCLR_EXTINT1_Pos)
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254 | #define EIC_INTENCLR_EXTINT2_Pos 2 /**< \brief (EIC_INTENCLR) External Interrupt 2 Enable */
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255 | #define EIC_INTENCLR_EXTINT2 (1 << EIC_INTENCLR_EXTINT2_Pos)
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256 | #define EIC_INTENCLR_EXTINT3_Pos 3 /**< \brief (EIC_INTENCLR) External Interrupt 3 Enable */
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257 | #define EIC_INTENCLR_EXTINT3 (1 << EIC_INTENCLR_EXTINT3_Pos)
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258 | #define EIC_INTENCLR_EXTINT4_Pos 4 /**< \brief (EIC_INTENCLR) External Interrupt 4 Enable */
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259 | #define EIC_INTENCLR_EXTINT4 (1 << EIC_INTENCLR_EXTINT4_Pos)
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260 | #define EIC_INTENCLR_EXTINT5_Pos 5 /**< \brief (EIC_INTENCLR) External Interrupt 5 Enable */
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261 | #define EIC_INTENCLR_EXTINT5 (1 << EIC_INTENCLR_EXTINT5_Pos)
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262 | #define EIC_INTENCLR_EXTINT6_Pos 6 /**< \brief (EIC_INTENCLR) External Interrupt 6 Enable */
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263 | #define EIC_INTENCLR_EXTINT6 (1 << EIC_INTENCLR_EXTINT6_Pos)
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264 | #define EIC_INTENCLR_EXTINT7_Pos 7 /**< \brief (EIC_INTENCLR) External Interrupt 7 Enable */
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265 | #define EIC_INTENCLR_EXTINT7 (1 << EIC_INTENCLR_EXTINT7_Pos)
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266 | #define EIC_INTENCLR_EXTINT8_Pos 8 /**< \brief (EIC_INTENCLR) External Interrupt 8 Enable */
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267 | #define EIC_INTENCLR_EXTINT8 (1 << EIC_INTENCLR_EXTINT8_Pos)
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268 | #define EIC_INTENCLR_EXTINT9_Pos 9 /**< \brief (EIC_INTENCLR) External Interrupt 9 Enable */
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269 | #define EIC_INTENCLR_EXTINT9 (1 << EIC_INTENCLR_EXTINT9_Pos)
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270 | #define EIC_INTENCLR_EXTINT10_Pos 10 /**< \brief (EIC_INTENCLR) External Interrupt 10 Enable */
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271 | #define EIC_INTENCLR_EXTINT10 (1 << EIC_INTENCLR_EXTINT10_Pos)
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272 | #define EIC_INTENCLR_EXTINT11_Pos 11 /**< \brief (EIC_INTENCLR) External Interrupt 11 Enable */
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273 | #define EIC_INTENCLR_EXTINT11 (1 << EIC_INTENCLR_EXTINT11_Pos)
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274 | #define EIC_INTENCLR_EXTINT12_Pos 12 /**< \brief (EIC_INTENCLR) External Interrupt 12 Enable */
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275 | #define EIC_INTENCLR_EXTINT12 (1 << EIC_INTENCLR_EXTINT12_Pos)
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276 | #define EIC_INTENCLR_EXTINT13_Pos 13 /**< \brief (EIC_INTENCLR) External Interrupt 13 Enable */
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277 | #define EIC_INTENCLR_EXTINT13 (1 << EIC_INTENCLR_EXTINT13_Pos)
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278 | #define EIC_INTENCLR_EXTINT14_Pos 14 /**< \brief (EIC_INTENCLR) External Interrupt 14 Enable */
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279 | #define EIC_INTENCLR_EXTINT14 (1 << EIC_INTENCLR_EXTINT14_Pos)
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280 | #define EIC_INTENCLR_EXTINT15_Pos 15 /**< \brief (EIC_INTENCLR) External Interrupt 15 Enable */
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281 | #define EIC_INTENCLR_EXTINT15 (1 << EIC_INTENCLR_EXTINT15_Pos)
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282 | #define EIC_INTENCLR_EXTINT_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt x Enable */
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283 | #define EIC_INTENCLR_EXTINT_Msk (0xFFFFu << EIC_INTENCLR_EXTINT_Pos)
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284 | #define EIC_INTENCLR_EXTINT(value) ((EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos)))
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285 | #define EIC_INTENCLR_MASK 0x0000FFFFu /**< \brief (EIC_INTENCLR) MASK Register */
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286 |
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287 | /* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */
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288 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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289 | typedef union {
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290 | struct {
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291 | uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
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292 | uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
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293 | uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
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294 | uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
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295 | uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
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296 | uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
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297 | uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
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298 | uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
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299 | uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
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300 | uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
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301 | uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
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302 | uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
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303 | uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
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304 | uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
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305 | uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
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306 | uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
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307 | uint32_t :16; /*!< bit: 16..31 Reserved */
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308 | } bit; /*!< Structure used for bit access */
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309 | struct {
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310 | uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
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311 | uint32_t :16; /*!< bit: 16..31 Reserved */
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312 | } vec; /*!< Structure used for vec access */
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313 | uint32_t reg; /*!< Type used for register access */
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314 | } EIC_INTENSET_Type;
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315 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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316 |
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317 | #define EIC_INTENSET_OFFSET 0x0C /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */
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318 | #define EIC_INTENSET_RESETVALUE 0x00000000 /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */
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319 |
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320 | #define EIC_INTENSET_EXTINT0_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt 0 Enable */
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321 | #define EIC_INTENSET_EXTINT0 (1 << EIC_INTENSET_EXTINT0_Pos)
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322 | #define EIC_INTENSET_EXTINT1_Pos 1 /**< \brief (EIC_INTENSET) External Interrupt 1 Enable */
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323 | #define EIC_INTENSET_EXTINT1 (1 << EIC_INTENSET_EXTINT1_Pos)
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324 | #define EIC_INTENSET_EXTINT2_Pos 2 /**< \brief (EIC_INTENSET) External Interrupt 2 Enable */
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325 | #define EIC_INTENSET_EXTINT2 (1 << EIC_INTENSET_EXTINT2_Pos)
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326 | #define EIC_INTENSET_EXTINT3_Pos 3 /**< \brief (EIC_INTENSET) External Interrupt 3 Enable */
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327 | #define EIC_INTENSET_EXTINT3 (1 << EIC_INTENSET_EXTINT3_Pos)
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328 | #define EIC_INTENSET_EXTINT4_Pos 4 /**< \brief (EIC_INTENSET) External Interrupt 4 Enable */
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329 | #define EIC_INTENSET_EXTINT4 (1 << EIC_INTENSET_EXTINT4_Pos)
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330 | #define EIC_INTENSET_EXTINT5_Pos 5 /**< \brief (EIC_INTENSET) External Interrupt 5 Enable */
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331 | #define EIC_INTENSET_EXTINT5 (1 << EIC_INTENSET_EXTINT5_Pos)
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332 | #define EIC_INTENSET_EXTINT6_Pos 6 /**< \brief (EIC_INTENSET) External Interrupt 6 Enable */
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333 | #define EIC_INTENSET_EXTINT6 (1 << EIC_INTENSET_EXTINT6_Pos)
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334 | #define EIC_INTENSET_EXTINT7_Pos 7 /**< \brief (EIC_INTENSET) External Interrupt 7 Enable */
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335 | #define EIC_INTENSET_EXTINT7 (1 << EIC_INTENSET_EXTINT7_Pos)
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336 | #define EIC_INTENSET_EXTINT8_Pos 8 /**< \brief (EIC_INTENSET) External Interrupt 8 Enable */
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337 | #define EIC_INTENSET_EXTINT8 (1 << EIC_INTENSET_EXTINT8_Pos)
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338 | #define EIC_INTENSET_EXTINT9_Pos 9 /**< \brief (EIC_INTENSET) External Interrupt 9 Enable */
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339 | #define EIC_INTENSET_EXTINT9 (1 << EIC_INTENSET_EXTINT9_Pos)
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340 | #define EIC_INTENSET_EXTINT10_Pos 10 /**< \brief (EIC_INTENSET) External Interrupt 10 Enable */
|
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341 | #define EIC_INTENSET_EXTINT10 (1 << EIC_INTENSET_EXTINT10_Pos)
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342 | #define EIC_INTENSET_EXTINT11_Pos 11 /**< \brief (EIC_INTENSET) External Interrupt 11 Enable */
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343 | #define EIC_INTENSET_EXTINT11 (1 << EIC_INTENSET_EXTINT11_Pos)
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344 | #define EIC_INTENSET_EXTINT12_Pos 12 /**< \brief (EIC_INTENSET) External Interrupt 12 Enable */
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345 | #define EIC_INTENSET_EXTINT12 (1 << EIC_INTENSET_EXTINT12_Pos)
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346 | #define EIC_INTENSET_EXTINT13_Pos 13 /**< \brief (EIC_INTENSET) External Interrupt 13 Enable */
|
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347 | #define EIC_INTENSET_EXTINT13 (1 << EIC_INTENSET_EXTINT13_Pos)
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348 | #define EIC_INTENSET_EXTINT14_Pos 14 /**< \brief (EIC_INTENSET) External Interrupt 14 Enable */
|
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349 | #define EIC_INTENSET_EXTINT14 (1 << EIC_INTENSET_EXTINT14_Pos)
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350 | #define EIC_INTENSET_EXTINT15_Pos 15 /**< \brief (EIC_INTENSET) External Interrupt 15 Enable */
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351 | #define EIC_INTENSET_EXTINT15 (1 << EIC_INTENSET_EXTINT15_Pos)
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352 | #define EIC_INTENSET_EXTINT_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt x Enable */
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353 | #define EIC_INTENSET_EXTINT_Msk (0xFFFFu << EIC_INTENSET_EXTINT_Pos)
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354 | #define EIC_INTENSET_EXTINT(value) ((EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos)))
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355 | #define EIC_INTENSET_MASK 0x0000FFFFu /**< \brief (EIC_INTENSET) MASK Register */
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356 |
|
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357 | /* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */
|
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358 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
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359 | typedef union {
|
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360 | struct {
|
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361 | uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */
|
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362 | uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */
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363 | uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */
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364 | uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */
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365 | uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */
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366 | uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */
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367 | uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */
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368 | uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */
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369 | uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */
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370 | uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */
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371 | uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */
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372 | uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */
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373 | uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */
|
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374 | uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */
|
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375 | uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */
|
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376 | uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */
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377 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
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378 | } bit; /*!< Structure used for bit access */
|
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379 | struct {
|
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380 | uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */
|
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381 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
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382 | } vec; /*!< Structure used for vec access */
|
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383 | uint32_t reg; /*!< Type used for register access */
|
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384 | } EIC_INTFLAG_Type;
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385 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
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386 |
|
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387 | #define EIC_INTFLAG_OFFSET 0x10 /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */
|
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388 | #define EIC_INTFLAG_RESETVALUE 0x00000000 /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */
|
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389 |
|
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390 | #define EIC_INTFLAG_EXTINT0_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt 0 */
|
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391 | #define EIC_INTFLAG_EXTINT0 (1 << EIC_INTFLAG_EXTINT0_Pos)
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392 | #define EIC_INTFLAG_EXTINT1_Pos 1 /**< \brief (EIC_INTFLAG) External Interrupt 1 */
|
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393 | #define EIC_INTFLAG_EXTINT1 (1 << EIC_INTFLAG_EXTINT1_Pos)
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394 | #define EIC_INTFLAG_EXTINT2_Pos 2 /**< \brief (EIC_INTFLAG) External Interrupt 2 */
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395 | #define EIC_INTFLAG_EXTINT2 (1 << EIC_INTFLAG_EXTINT2_Pos)
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396 | #define EIC_INTFLAG_EXTINT3_Pos 3 /**< \brief (EIC_INTFLAG) External Interrupt 3 */
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397 | #define EIC_INTFLAG_EXTINT3 (1 << EIC_INTFLAG_EXTINT3_Pos)
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398 | #define EIC_INTFLAG_EXTINT4_Pos 4 /**< \brief (EIC_INTFLAG) External Interrupt 4 */
|
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399 | #define EIC_INTFLAG_EXTINT4 (1 << EIC_INTFLAG_EXTINT4_Pos)
|
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400 | #define EIC_INTFLAG_EXTINT5_Pos 5 /**< \brief (EIC_INTFLAG) External Interrupt 5 */
|
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401 | #define EIC_INTFLAG_EXTINT5 (1 << EIC_INTFLAG_EXTINT5_Pos)
|
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402 | #define EIC_INTFLAG_EXTINT6_Pos 6 /**< \brief (EIC_INTFLAG) External Interrupt 6 */
|
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403 | #define EIC_INTFLAG_EXTINT6 (1 << EIC_INTFLAG_EXTINT6_Pos)
|
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404 | #define EIC_INTFLAG_EXTINT7_Pos 7 /**< \brief (EIC_INTFLAG) External Interrupt 7 */
|
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405 | #define EIC_INTFLAG_EXTINT7 (1 << EIC_INTFLAG_EXTINT7_Pos)
|
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406 | #define EIC_INTFLAG_EXTINT8_Pos 8 /**< \brief (EIC_INTFLAG) External Interrupt 8 */
|
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407 | #define EIC_INTFLAG_EXTINT8 (1 << EIC_INTFLAG_EXTINT8_Pos)
|
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408 | #define EIC_INTFLAG_EXTINT9_Pos 9 /**< \brief (EIC_INTFLAG) External Interrupt 9 */
|
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409 | #define EIC_INTFLAG_EXTINT9 (1 << EIC_INTFLAG_EXTINT9_Pos)
|
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410 | #define EIC_INTFLAG_EXTINT10_Pos 10 /**< \brief (EIC_INTFLAG) External Interrupt 10 */
|
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411 | #define EIC_INTFLAG_EXTINT10 (1 << EIC_INTFLAG_EXTINT10_Pos)
|
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412 | #define EIC_INTFLAG_EXTINT11_Pos 11 /**< \brief (EIC_INTFLAG) External Interrupt 11 */
|
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413 | #define EIC_INTFLAG_EXTINT11 (1 << EIC_INTFLAG_EXTINT11_Pos)
|
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414 | #define EIC_INTFLAG_EXTINT12_Pos 12 /**< \brief (EIC_INTFLAG) External Interrupt 12 */
|
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415 | #define EIC_INTFLAG_EXTINT12 (1 << EIC_INTFLAG_EXTINT12_Pos)
|
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416 | #define EIC_INTFLAG_EXTINT13_Pos 13 /**< \brief (EIC_INTFLAG) External Interrupt 13 */
|
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417 | #define EIC_INTFLAG_EXTINT13 (1 << EIC_INTFLAG_EXTINT13_Pos)
|
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418 | #define EIC_INTFLAG_EXTINT14_Pos 14 /**< \brief (EIC_INTFLAG) External Interrupt 14 */
|
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419 | #define EIC_INTFLAG_EXTINT14 (1 << EIC_INTFLAG_EXTINT14_Pos)
|
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420 | #define EIC_INTFLAG_EXTINT15_Pos 15 /**< \brief (EIC_INTFLAG) External Interrupt 15 */
|
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421 | #define EIC_INTFLAG_EXTINT15 (1 << EIC_INTFLAG_EXTINT15_Pos)
|
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422 | #define EIC_INTFLAG_EXTINT_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt x */
|
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423 | #define EIC_INTFLAG_EXTINT_Msk (0xFFFFu << EIC_INTFLAG_EXTINT_Pos)
|
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424 | #define EIC_INTFLAG_EXTINT(value) ((EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos)))
|
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425 | #define EIC_INTFLAG_MASK 0x0000FFFFu /**< \brief (EIC_INTFLAG) MASK Register */
|
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426 |
|
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427 | /* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */
|
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428 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
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429 | typedef union {
|
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430 | struct {
|
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431 | uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */
|
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432 | uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */
|
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433 | uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */
|
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434 | uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */
|
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435 | uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */
|
---|
436 | uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */
|
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437 | uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */
|
---|
438 | uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */
|
---|
439 | uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */
|
---|
440 | uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */
|
---|
441 | uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */
|
---|
442 | uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */
|
---|
443 | uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */
|
---|
444 | uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */
|
---|
445 | uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */
|
---|
446 | uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */
|
---|
447 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
---|
448 | } bit; /*!< Structure used for bit access */
|
---|
449 | struct {
|
---|
450 | uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */
|
---|
451 | uint32_t :16; /*!< bit: 16..31 Reserved */
|
---|
452 | } vec; /*!< Structure used for vec access */
|
---|
453 | uint32_t reg; /*!< Type used for register access */
|
---|
454 | } EIC_WAKEUP_Type;
|
---|
455 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
456 |
|
---|
457 | #define EIC_WAKEUP_OFFSET 0x14 /**< \brief (EIC_WAKEUP offset) Wake-Up Enable */
|
---|
458 | #define EIC_WAKEUP_RESETVALUE 0x00000000 /**< \brief (EIC_WAKEUP reset_value) Wake-Up Enable */
|
---|
459 |
|
---|
460 | #define EIC_WAKEUP_WAKEUPEN0_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt 0 Wake-up Enable */
|
---|
461 | #define EIC_WAKEUP_WAKEUPEN0 (1 << EIC_WAKEUP_WAKEUPEN0_Pos)
|
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462 | #define EIC_WAKEUP_WAKEUPEN1_Pos 1 /**< \brief (EIC_WAKEUP) External Interrupt 1 Wake-up Enable */
|
---|
463 | #define EIC_WAKEUP_WAKEUPEN1 (1 << EIC_WAKEUP_WAKEUPEN1_Pos)
|
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464 | #define EIC_WAKEUP_WAKEUPEN2_Pos 2 /**< \brief (EIC_WAKEUP) External Interrupt 2 Wake-up Enable */
|
---|
465 | #define EIC_WAKEUP_WAKEUPEN2 (1 << EIC_WAKEUP_WAKEUPEN2_Pos)
|
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466 | #define EIC_WAKEUP_WAKEUPEN3_Pos 3 /**< \brief (EIC_WAKEUP) External Interrupt 3 Wake-up Enable */
|
---|
467 | #define EIC_WAKEUP_WAKEUPEN3 (1 << EIC_WAKEUP_WAKEUPEN3_Pos)
|
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468 | #define EIC_WAKEUP_WAKEUPEN4_Pos 4 /**< \brief (EIC_WAKEUP) External Interrupt 4 Wake-up Enable */
|
---|
469 | #define EIC_WAKEUP_WAKEUPEN4 (1 << EIC_WAKEUP_WAKEUPEN4_Pos)
|
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470 | #define EIC_WAKEUP_WAKEUPEN5_Pos 5 /**< \brief (EIC_WAKEUP) External Interrupt 5 Wake-up Enable */
|
---|
471 | #define EIC_WAKEUP_WAKEUPEN5 (1 << EIC_WAKEUP_WAKEUPEN5_Pos)
|
---|
472 | #define EIC_WAKEUP_WAKEUPEN6_Pos 6 /**< \brief (EIC_WAKEUP) External Interrupt 6 Wake-up Enable */
|
---|
473 | #define EIC_WAKEUP_WAKEUPEN6 (1 << EIC_WAKEUP_WAKEUPEN6_Pos)
|
---|
474 | #define EIC_WAKEUP_WAKEUPEN7_Pos 7 /**< \brief (EIC_WAKEUP) External Interrupt 7 Wake-up Enable */
|
---|
475 | #define EIC_WAKEUP_WAKEUPEN7 (1 << EIC_WAKEUP_WAKEUPEN7_Pos)
|
---|
476 | #define EIC_WAKEUP_WAKEUPEN8_Pos 8 /**< \brief (EIC_WAKEUP) External Interrupt 8 Wake-up Enable */
|
---|
477 | #define EIC_WAKEUP_WAKEUPEN8 (1 << EIC_WAKEUP_WAKEUPEN8_Pos)
|
---|
478 | #define EIC_WAKEUP_WAKEUPEN9_Pos 9 /**< \brief (EIC_WAKEUP) External Interrupt 9 Wake-up Enable */
|
---|
479 | #define EIC_WAKEUP_WAKEUPEN9 (1 << EIC_WAKEUP_WAKEUPEN9_Pos)
|
---|
480 | #define EIC_WAKEUP_WAKEUPEN10_Pos 10 /**< \brief (EIC_WAKEUP) External Interrupt 10 Wake-up Enable */
|
---|
481 | #define EIC_WAKEUP_WAKEUPEN10 (1 << EIC_WAKEUP_WAKEUPEN10_Pos)
|
---|
482 | #define EIC_WAKEUP_WAKEUPEN11_Pos 11 /**< \brief (EIC_WAKEUP) External Interrupt 11 Wake-up Enable */
|
---|
483 | #define EIC_WAKEUP_WAKEUPEN11 (1 << EIC_WAKEUP_WAKEUPEN11_Pos)
|
---|
484 | #define EIC_WAKEUP_WAKEUPEN12_Pos 12 /**< \brief (EIC_WAKEUP) External Interrupt 12 Wake-up Enable */
|
---|
485 | #define EIC_WAKEUP_WAKEUPEN12 (1 << EIC_WAKEUP_WAKEUPEN12_Pos)
|
---|
486 | #define EIC_WAKEUP_WAKEUPEN13_Pos 13 /**< \brief (EIC_WAKEUP) External Interrupt 13 Wake-up Enable */
|
---|
487 | #define EIC_WAKEUP_WAKEUPEN13 (1 << EIC_WAKEUP_WAKEUPEN13_Pos)
|
---|
488 | #define EIC_WAKEUP_WAKEUPEN14_Pos 14 /**< \brief (EIC_WAKEUP) External Interrupt 14 Wake-up Enable */
|
---|
489 | #define EIC_WAKEUP_WAKEUPEN14 (1 << EIC_WAKEUP_WAKEUPEN14_Pos)
|
---|
490 | #define EIC_WAKEUP_WAKEUPEN15_Pos 15 /**< \brief (EIC_WAKEUP) External Interrupt 15 Wake-up Enable */
|
---|
491 | #define EIC_WAKEUP_WAKEUPEN15 (1 << EIC_WAKEUP_WAKEUPEN15_Pos)
|
---|
492 | #define EIC_WAKEUP_WAKEUPEN_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt x Wake-up Enable */
|
---|
493 | #define EIC_WAKEUP_WAKEUPEN_Msk (0xFFFFu << EIC_WAKEUP_WAKEUPEN_Pos)
|
---|
494 | #define EIC_WAKEUP_WAKEUPEN(value) ((EIC_WAKEUP_WAKEUPEN_Msk & ((value) << EIC_WAKEUP_WAKEUPEN_Pos)))
|
---|
495 | #define EIC_WAKEUP_MASK 0x0000FFFFu /**< \brief (EIC_WAKEUP) MASK Register */
|
---|
496 |
|
---|
497 | /* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */
|
---|
498 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
499 | typedef union {
|
---|
500 | struct {
|
---|
501 | uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */
|
---|
502 | uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */
|
---|
503 | uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */
|
---|
504 | uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */
|
---|
505 | uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */
|
---|
506 | uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */
|
---|
507 | uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */
|
---|
508 | uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */
|
---|
509 | uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */
|
---|
510 | uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */
|
---|
511 | uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */
|
---|
512 | uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */
|
---|
513 | uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */
|
---|
514 | uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */
|
---|
515 | uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */
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516 | uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */
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517 | } bit; /*!< Structure used for bit access */
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518 | uint32_t reg; /*!< Type used for register access */
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519 | } EIC_CONFIG_Type;
|
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520 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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521 |
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522 | #define EIC_CONFIG_OFFSET 0x18 /**< \brief (EIC_CONFIG offset) Configuration n */
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523 | #define EIC_CONFIG_RESETVALUE 0x00000000 /**< \brief (EIC_CONFIG reset_value) Configuration n */
|
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524 |
|
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525 | #define EIC_CONFIG_SENSE0_Pos 0 /**< \brief (EIC_CONFIG) Input Sense 0 Configuration */
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526 | #define EIC_CONFIG_SENSE0_Msk (0x7u << EIC_CONFIG_SENSE0_Pos)
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527 | #define EIC_CONFIG_SENSE0(value) ((EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos)))
|
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528 | #define EIC_CONFIG_SENSE0_NONE_Val 0x0u /**< \brief (EIC_CONFIG) No detection */
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529 | #define EIC_CONFIG_SENSE0_RISE_Val 0x1u /**< \brief (EIC_CONFIG) Rising-edge detection */
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530 | #define EIC_CONFIG_SENSE0_FALL_Val 0x2u /**< \brief (EIC_CONFIG) Falling-edge detection */
|
---|
531 | #define EIC_CONFIG_SENSE0_BOTH_Val 0x3u /**< \brief (EIC_CONFIG) Both-edges detection */
|
---|
532 | #define EIC_CONFIG_SENSE0_HIGH_Val 0x4u /**< \brief (EIC_CONFIG) High-level detection */
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533 | #define EIC_CONFIG_SENSE0_LOW_Val 0x5u /**< \brief (EIC_CONFIG) Low-level detection */
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534 | #define EIC_CONFIG_SENSE0_NONE (EIC_CONFIG_SENSE0_NONE_Val << EIC_CONFIG_SENSE0_Pos)
|
---|
535 | #define EIC_CONFIG_SENSE0_RISE (EIC_CONFIG_SENSE0_RISE_Val << EIC_CONFIG_SENSE0_Pos)
|
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536 | #define EIC_CONFIG_SENSE0_FALL (EIC_CONFIG_SENSE0_FALL_Val << EIC_CONFIG_SENSE0_Pos)
|
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537 | #define EIC_CONFIG_SENSE0_BOTH (EIC_CONFIG_SENSE0_BOTH_Val << EIC_CONFIG_SENSE0_Pos)
|
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538 | #define EIC_CONFIG_SENSE0_HIGH (EIC_CONFIG_SENSE0_HIGH_Val << EIC_CONFIG_SENSE0_Pos)
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539 | #define EIC_CONFIG_SENSE0_LOW (EIC_CONFIG_SENSE0_LOW_Val << EIC_CONFIG_SENSE0_Pos)
|
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540 | #define EIC_CONFIG_FILTEN0_Pos 3 /**< \brief (EIC_CONFIG) Filter 0 Enable */
|
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541 | #define EIC_CONFIG_FILTEN0 (0x1u << EIC_CONFIG_FILTEN0_Pos)
|
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542 | #define EIC_CONFIG_SENSE1_Pos 4 /**< \brief (EIC_CONFIG) Input Sense 1 Configuration */
|
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543 | #define EIC_CONFIG_SENSE1_Msk (0x7u << EIC_CONFIG_SENSE1_Pos)
|
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544 | #define EIC_CONFIG_SENSE1(value) ((EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos)))
|
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545 | #define EIC_CONFIG_SENSE1_NONE_Val 0x0u /**< \brief (EIC_CONFIG) No detection */
|
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546 | #define EIC_CONFIG_SENSE1_RISE_Val 0x1u /**< \brief (EIC_CONFIG) Rising edge detection */
|
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547 | #define EIC_CONFIG_SENSE1_FALL_Val 0x2u /**< \brief (EIC_CONFIG) Falling edge detection */
|
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548 | #define EIC_CONFIG_SENSE1_BOTH_Val 0x3u /**< \brief (EIC_CONFIG) Both edges detection */
|
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549 | #define EIC_CONFIG_SENSE1_HIGH_Val 0x4u /**< \brief (EIC_CONFIG) High level detection */
|
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550 | #define EIC_CONFIG_SENSE1_LOW_Val 0x5u /**< \brief (EIC_CONFIG) Low level detection */
|
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551 | #define EIC_CONFIG_SENSE1_NONE (EIC_CONFIG_SENSE1_NONE_Val << EIC_CONFIG_SENSE1_Pos)
|
---|
552 | #define EIC_CONFIG_SENSE1_RISE (EIC_CONFIG_SENSE1_RISE_Val << EIC_CONFIG_SENSE1_Pos)
|
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553 | #define EIC_CONFIG_SENSE1_FALL (EIC_CONFIG_SENSE1_FALL_Val << EIC_CONFIG_SENSE1_Pos)
|
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554 | #define EIC_CONFIG_SENSE1_BOTH (EIC_CONFIG_SENSE1_BOTH_Val << EIC_CONFIG_SENSE1_Pos)
|
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555 | #define EIC_CONFIG_SENSE1_HIGH (EIC_CONFIG_SENSE1_HIGH_Val << EIC_CONFIG_SENSE1_Pos)
|
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556 | #define EIC_CONFIG_SENSE1_LOW (EIC_CONFIG_SENSE1_LOW_Val << EIC_CONFIG_SENSE1_Pos)
|
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557 | #define EIC_CONFIG_FILTEN1_Pos 7 /**< \brief (EIC_CONFIG) Filter 1 Enable */
|
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558 | #define EIC_CONFIG_FILTEN1 (0x1u << EIC_CONFIG_FILTEN1_Pos)
|
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559 | #define EIC_CONFIG_SENSE2_Pos 8 /**< \brief (EIC_CONFIG) Input Sense 2 Configuration */
|
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560 | #define EIC_CONFIG_SENSE2_Msk (0x7u << EIC_CONFIG_SENSE2_Pos)
|
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561 | #define EIC_CONFIG_SENSE2(value) ((EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos)))
|
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562 | #define EIC_CONFIG_SENSE2_NONE_Val 0x0u /**< \brief (EIC_CONFIG) No detection */
|
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563 | #define EIC_CONFIG_SENSE2_RISE_Val 0x1u /**< \brief (EIC_CONFIG) Rising edge detection */
|
---|
564 | #define EIC_CONFIG_SENSE2_FALL_Val 0x2u /**< \brief (EIC_CONFIG) Falling edge detection */
|
---|
565 | #define EIC_CONFIG_SENSE2_BOTH_Val 0x3u /**< \brief (EIC_CONFIG) Both edges detection */
|
---|
566 | #define EIC_CONFIG_SENSE2_HIGH_Val 0x4u /**< \brief (EIC_CONFIG) High level detection */
|
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567 | #define EIC_CONFIG_SENSE2_LOW_Val 0x5u /**< \brief (EIC_CONFIG) Low level detection */
|
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568 | #define EIC_CONFIG_SENSE2_NONE (EIC_CONFIG_SENSE2_NONE_Val << EIC_CONFIG_SENSE2_Pos)
|
---|
569 | #define EIC_CONFIG_SENSE2_RISE (EIC_CONFIG_SENSE2_RISE_Val << EIC_CONFIG_SENSE2_Pos)
|
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570 | #define EIC_CONFIG_SENSE2_FALL (EIC_CONFIG_SENSE2_FALL_Val << EIC_CONFIG_SENSE2_Pos)
|
---|
571 | #define EIC_CONFIG_SENSE2_BOTH (EIC_CONFIG_SENSE2_BOTH_Val << EIC_CONFIG_SENSE2_Pos)
|
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572 | #define EIC_CONFIG_SENSE2_HIGH (EIC_CONFIG_SENSE2_HIGH_Val << EIC_CONFIG_SENSE2_Pos)
|
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573 | #define EIC_CONFIG_SENSE2_LOW (EIC_CONFIG_SENSE2_LOW_Val << EIC_CONFIG_SENSE2_Pos)
|
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574 | #define EIC_CONFIG_FILTEN2_Pos 11 /**< \brief (EIC_CONFIG) Filter 2 Enable */
|
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575 | #define EIC_CONFIG_FILTEN2 (0x1u << EIC_CONFIG_FILTEN2_Pos)
|
---|
576 | #define EIC_CONFIG_SENSE3_Pos 12 /**< \brief (EIC_CONFIG) Input Sense 3 Configuration */
|
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577 | #define EIC_CONFIG_SENSE3_Msk (0x7u << EIC_CONFIG_SENSE3_Pos)
|
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578 | #define EIC_CONFIG_SENSE3(value) ((EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos)))
|
---|
579 | #define EIC_CONFIG_SENSE3_NONE_Val 0x0u /**< \brief (EIC_CONFIG) No detection */
|
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580 | #define EIC_CONFIG_SENSE3_RISE_Val 0x1u /**< \brief (EIC_CONFIG) Rising edge detection */
|
---|
581 | #define EIC_CONFIG_SENSE3_FALL_Val 0x2u /**< \brief (EIC_CONFIG) Falling edge detection */
|
---|
582 | #define EIC_CONFIG_SENSE3_BOTH_Val 0x3u /**< \brief (EIC_CONFIG) Both edges detection */
|
---|
583 | #define EIC_CONFIG_SENSE3_HIGH_Val 0x4u /**< \brief (EIC_CONFIG) High level detection */
|
---|
584 | #define EIC_CONFIG_SENSE3_LOW_Val 0x5u /**< \brief (EIC_CONFIG) Low level detection */
|
---|
585 | #define EIC_CONFIG_SENSE3_NONE (EIC_CONFIG_SENSE3_NONE_Val << EIC_CONFIG_SENSE3_Pos)
|
---|
586 | #define EIC_CONFIG_SENSE3_RISE (EIC_CONFIG_SENSE3_RISE_Val << EIC_CONFIG_SENSE3_Pos)
|
---|
587 | #define EIC_CONFIG_SENSE3_FALL (EIC_CONFIG_SENSE3_FALL_Val << EIC_CONFIG_SENSE3_Pos)
|
---|
588 | #define EIC_CONFIG_SENSE3_BOTH (EIC_CONFIG_SENSE3_BOTH_Val << EIC_CONFIG_SENSE3_Pos)
|
---|
589 | #define EIC_CONFIG_SENSE3_HIGH (EIC_CONFIG_SENSE3_HIGH_Val << EIC_CONFIG_SENSE3_Pos)
|
---|
590 | #define EIC_CONFIG_SENSE3_LOW (EIC_CONFIG_SENSE3_LOW_Val << EIC_CONFIG_SENSE3_Pos)
|
---|
591 | #define EIC_CONFIG_FILTEN3_Pos 15 /**< \brief (EIC_CONFIG) Filter 3 Enable */
|
---|
592 | #define EIC_CONFIG_FILTEN3 (0x1u << EIC_CONFIG_FILTEN3_Pos)
|
---|
593 | #define EIC_CONFIG_SENSE4_Pos 16 /**< \brief (EIC_CONFIG) Input Sense 4 Configuration */
|
---|
594 | #define EIC_CONFIG_SENSE4_Msk (0x7u << EIC_CONFIG_SENSE4_Pos)
|
---|
595 | #define EIC_CONFIG_SENSE4(value) ((EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos)))
|
---|
596 | #define EIC_CONFIG_SENSE4_NONE_Val 0x0u /**< \brief (EIC_CONFIG) No detection */
|
---|
597 | #define EIC_CONFIG_SENSE4_RISE_Val 0x1u /**< \brief (EIC_CONFIG) Rising edge detection */
|
---|
598 | #define EIC_CONFIG_SENSE4_FALL_Val 0x2u /**< \brief (EIC_CONFIG) Falling edge detection */
|
---|
599 | #define EIC_CONFIG_SENSE4_BOTH_Val 0x3u /**< \brief (EIC_CONFIG) Both edges detection */
|
---|
600 | #define EIC_CONFIG_SENSE4_HIGH_Val 0x4u /**< \brief (EIC_CONFIG) High level detection */
|
---|
601 | #define EIC_CONFIG_SENSE4_LOW_Val 0x5u /**< \brief (EIC_CONFIG) Low level detection */
|
---|
602 | #define EIC_CONFIG_SENSE4_NONE (EIC_CONFIG_SENSE4_NONE_Val << EIC_CONFIG_SENSE4_Pos)
|
---|
603 | #define EIC_CONFIG_SENSE4_RISE (EIC_CONFIG_SENSE4_RISE_Val << EIC_CONFIG_SENSE4_Pos)
|
---|
604 | #define EIC_CONFIG_SENSE4_FALL (EIC_CONFIG_SENSE4_FALL_Val << EIC_CONFIG_SENSE4_Pos)
|
---|
605 | #define EIC_CONFIG_SENSE4_BOTH (EIC_CONFIG_SENSE4_BOTH_Val << EIC_CONFIG_SENSE4_Pos)
|
---|
606 | #define EIC_CONFIG_SENSE4_HIGH (EIC_CONFIG_SENSE4_HIGH_Val << EIC_CONFIG_SENSE4_Pos)
|
---|
607 | #define EIC_CONFIG_SENSE4_LOW (EIC_CONFIG_SENSE4_LOW_Val << EIC_CONFIG_SENSE4_Pos)
|
---|
608 | #define EIC_CONFIG_FILTEN4_Pos 19 /**< \brief (EIC_CONFIG) Filter 4 Enable */
|
---|
609 | #define EIC_CONFIG_FILTEN4 (0x1u << EIC_CONFIG_FILTEN4_Pos)
|
---|
610 | #define EIC_CONFIG_SENSE5_Pos 20 /**< \brief (EIC_CONFIG) Input Sense 5 Configuration */
|
---|
611 | #define EIC_CONFIG_SENSE5_Msk (0x7u << EIC_CONFIG_SENSE5_Pos)
|
---|
612 | #define EIC_CONFIG_SENSE5(value) ((EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos)))
|
---|
613 | #define EIC_CONFIG_SENSE5_NONE_Val 0x0u /**< \brief (EIC_CONFIG) No detection */
|
---|
614 | #define EIC_CONFIG_SENSE5_RISE_Val 0x1u /**< \brief (EIC_CONFIG) Rising edge detection */
|
---|
615 | #define EIC_CONFIG_SENSE5_FALL_Val 0x2u /**< \brief (EIC_CONFIG) Falling edge detection */
|
---|
616 | #define EIC_CONFIG_SENSE5_BOTH_Val 0x3u /**< \brief (EIC_CONFIG) Both edges detection */
|
---|
617 | #define EIC_CONFIG_SENSE5_HIGH_Val 0x4u /**< \brief (EIC_CONFIG) High level detection */
|
---|
618 | #define EIC_CONFIG_SENSE5_LOW_Val 0x5u /**< \brief (EIC_CONFIG) Low level detection */
|
---|
619 | #define EIC_CONFIG_SENSE5_NONE (EIC_CONFIG_SENSE5_NONE_Val << EIC_CONFIG_SENSE5_Pos)
|
---|
620 | #define EIC_CONFIG_SENSE5_RISE (EIC_CONFIG_SENSE5_RISE_Val << EIC_CONFIG_SENSE5_Pos)
|
---|
621 | #define EIC_CONFIG_SENSE5_FALL (EIC_CONFIG_SENSE5_FALL_Val << EIC_CONFIG_SENSE5_Pos)
|
---|
622 | #define EIC_CONFIG_SENSE5_BOTH (EIC_CONFIG_SENSE5_BOTH_Val << EIC_CONFIG_SENSE5_Pos)
|
---|
623 | #define EIC_CONFIG_SENSE5_HIGH (EIC_CONFIG_SENSE5_HIGH_Val << EIC_CONFIG_SENSE5_Pos)
|
---|
624 | #define EIC_CONFIG_SENSE5_LOW (EIC_CONFIG_SENSE5_LOW_Val << EIC_CONFIG_SENSE5_Pos)
|
---|
625 | #define EIC_CONFIG_FILTEN5_Pos 23 /**< \brief (EIC_CONFIG) Filter 5 Enable */
|
---|
626 | #define EIC_CONFIG_FILTEN5 (0x1u << EIC_CONFIG_FILTEN5_Pos)
|
---|
627 | #define EIC_CONFIG_SENSE6_Pos 24 /**< \brief (EIC_CONFIG) Input Sense 6 Configuration */
|
---|
628 | #define EIC_CONFIG_SENSE6_Msk (0x7u << EIC_CONFIG_SENSE6_Pos)
|
---|
629 | #define EIC_CONFIG_SENSE6(value) ((EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos)))
|
---|
630 | #define EIC_CONFIG_SENSE6_NONE_Val 0x0u /**< \brief (EIC_CONFIG) No detection */
|
---|
631 | #define EIC_CONFIG_SENSE6_RISE_Val 0x1u /**< \brief (EIC_CONFIG) Rising edge detection */
|
---|
632 | #define EIC_CONFIG_SENSE6_FALL_Val 0x2u /**< \brief (EIC_CONFIG) Falling edge detection */
|
---|
633 | #define EIC_CONFIG_SENSE6_BOTH_Val 0x3u /**< \brief (EIC_CONFIG) Both edges detection */
|
---|
634 | #define EIC_CONFIG_SENSE6_HIGH_Val 0x4u /**< \brief (EIC_CONFIG) High level detection */
|
---|
635 | #define EIC_CONFIG_SENSE6_LOW_Val 0x5u /**< \brief (EIC_CONFIG) Low level detection */
|
---|
636 | #define EIC_CONFIG_SENSE6_NONE (EIC_CONFIG_SENSE6_NONE_Val << EIC_CONFIG_SENSE6_Pos)
|
---|
637 | #define EIC_CONFIG_SENSE6_RISE (EIC_CONFIG_SENSE6_RISE_Val << EIC_CONFIG_SENSE6_Pos)
|
---|
638 | #define EIC_CONFIG_SENSE6_FALL (EIC_CONFIG_SENSE6_FALL_Val << EIC_CONFIG_SENSE6_Pos)
|
---|
639 | #define EIC_CONFIG_SENSE6_BOTH (EIC_CONFIG_SENSE6_BOTH_Val << EIC_CONFIG_SENSE6_Pos)
|
---|
640 | #define EIC_CONFIG_SENSE6_HIGH (EIC_CONFIG_SENSE6_HIGH_Val << EIC_CONFIG_SENSE6_Pos)
|
---|
641 | #define EIC_CONFIG_SENSE6_LOW (EIC_CONFIG_SENSE6_LOW_Val << EIC_CONFIG_SENSE6_Pos)
|
---|
642 | #define EIC_CONFIG_FILTEN6_Pos 27 /**< \brief (EIC_CONFIG) Filter 6 Enable */
|
---|
643 | #define EIC_CONFIG_FILTEN6 (0x1u << EIC_CONFIG_FILTEN6_Pos)
|
---|
644 | #define EIC_CONFIG_SENSE7_Pos 28 /**< \brief (EIC_CONFIG) Input Sense 7 Configuration */
|
---|
645 | #define EIC_CONFIG_SENSE7_Msk (0x7u << EIC_CONFIG_SENSE7_Pos)
|
---|
646 | #define EIC_CONFIG_SENSE7(value) ((EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos)))
|
---|
647 | #define EIC_CONFIG_SENSE7_NONE_Val 0x0u /**< \brief (EIC_CONFIG) No detection */
|
---|
648 | #define EIC_CONFIG_SENSE7_RISE_Val 0x1u /**< \brief (EIC_CONFIG) Rising edge detection */
|
---|
649 | #define EIC_CONFIG_SENSE7_FALL_Val 0x2u /**< \brief (EIC_CONFIG) Falling edge detection */
|
---|
650 | #define EIC_CONFIG_SENSE7_BOTH_Val 0x3u /**< \brief (EIC_CONFIG) Both edges detection */
|
---|
651 | #define EIC_CONFIG_SENSE7_HIGH_Val 0x4u /**< \brief (EIC_CONFIG) High level detection */
|
---|
652 | #define EIC_CONFIG_SENSE7_LOW_Val 0x5u /**< \brief (EIC_CONFIG) Low level detection */
|
---|
653 | #define EIC_CONFIG_SENSE7_NONE (EIC_CONFIG_SENSE7_NONE_Val << EIC_CONFIG_SENSE7_Pos)
|
---|
654 | #define EIC_CONFIG_SENSE7_RISE (EIC_CONFIG_SENSE7_RISE_Val << EIC_CONFIG_SENSE7_Pos)
|
---|
655 | #define EIC_CONFIG_SENSE7_FALL (EIC_CONFIG_SENSE7_FALL_Val << EIC_CONFIG_SENSE7_Pos)
|
---|
656 | #define EIC_CONFIG_SENSE7_BOTH (EIC_CONFIG_SENSE7_BOTH_Val << EIC_CONFIG_SENSE7_Pos)
|
---|
657 | #define EIC_CONFIG_SENSE7_HIGH (EIC_CONFIG_SENSE7_HIGH_Val << EIC_CONFIG_SENSE7_Pos)
|
---|
658 | #define EIC_CONFIG_SENSE7_LOW (EIC_CONFIG_SENSE7_LOW_Val << EIC_CONFIG_SENSE7_Pos)
|
---|
659 | #define EIC_CONFIG_FILTEN7_Pos 31 /**< \brief (EIC_CONFIG) Filter 7 Enable */
|
---|
660 | #define EIC_CONFIG_FILTEN7 (0x1u << EIC_CONFIG_FILTEN7_Pos)
|
---|
661 | #define EIC_CONFIG_MASK 0xFFFFFFFFu /**< \brief (EIC_CONFIG) MASK Register */
|
---|
662 |
|
---|
663 | /** \brief EIC hardware registers */
|
---|
664 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
665 | typedef struct {
|
---|
666 | __IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
|
---|
667 | __I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */
|
---|
668 | __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */
|
---|
669 | __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */
|
---|
670 | __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */
|
---|
671 | __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
|
---|
672 | __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
|
---|
673 | __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
|
---|
674 | __IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
|
---|
675 | __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */
|
---|
676 | } Eic;
|
---|
677 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
678 |
|
---|
679 | /*@}*/
|
---|
680 |
|
---|
681 | #endif /* _SAMD21_EIC_COMPONENT_ */
|
---|