[136] | 1 | /**
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| 2 | * \file
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| 3 | *
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| 4 | * \brief Component description for DMAC
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| 5 | *
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| 6 | * Copyright (c) 2014 Atmel Corporation. All rights reserved.
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| 7 | *
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| 8 | * \asf_license_start
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| 9 | *
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| 10 | * \page License
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| 11 | *
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| 12 | * Redistribution and use in source and binary forms, with or without
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| 13 | * modification, are permitted provided that the following conditions are met:
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| 14 | *
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| 15 | * 1. Redistributions of source code must retain the above copyright notice,
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| 16 | * this list of conditions and the following disclaimer.
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| 17 | *
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| 18 | * 2. Redistributions in binary form must reproduce the above copyright notice,
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| 19 | * this list of conditions and the following disclaimer in the documentation
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| 20 | * and/or other materials provided with the distribution.
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| 21 | *
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| 22 | * 3. The name of Atmel may not be used to endorse or promote products derived
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| 23 | * from this software without specific prior written permission.
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| 24 | *
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| 25 | * 4. This software may only be redistributed and used in connection with an
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| 26 | * Atmel microcontroller product.
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| 27 | *
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| 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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| 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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| 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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| 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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| 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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| 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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| 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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| 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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| 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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| 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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| 38 | * POSSIBILITY OF SUCH DAMAGE.
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| 39 | *
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| 40 | * \asf_license_stop
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| 41 | *
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| 42 | */
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| 43 |
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| 44 | #ifndef _SAMD21_DMAC_COMPONENT_
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| 45 | #define _SAMD21_DMAC_COMPONENT_
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| 46 |
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| 47 | /* ========================================================================== */
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| 48 | /** SOFTWARE API DEFINITION FOR DMAC */
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| 49 | /* ========================================================================== */
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| 50 | /** \addtogroup SAMD21_DMAC Direct Memory Access Controller */
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| 51 | /*@{*/
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| 52 |
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| 53 | #define DMAC_U2223
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| 54 | #define REV_DMAC 0x100
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| 55 |
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| 56 | /* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
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| 57 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 58 | typedef union {
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| 59 | struct {
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| 60 | uint16_t SWRST:1; /*!< bit: 0 Software Reset */
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| 61 | uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
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| 62 | uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */
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| 63 | uint16_t :5; /*!< bit: 3.. 7 Reserved */
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| 64 | uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
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| 65 | uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
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| 66 | uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
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| 67 | uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
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| 68 | uint16_t :4; /*!< bit: 12..15 Reserved */
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| 69 | } bit; /*!< Structure used for bit access */
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| 70 | struct {
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| 71 | uint16_t :8; /*!< bit: 0.. 7 Reserved */
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| 72 | uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
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| 73 | uint16_t :4; /*!< bit: 12..15 Reserved */
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| 74 | } vec; /*!< Structure used for vec access */
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| 75 | uint16_t reg; /*!< Type used for register access */
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| 76 | } DMAC_CTRL_Type;
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| 77 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 78 |
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| 79 | #define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */
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| 80 | #define DMAC_CTRL_RESETVALUE 0x0000 /**< \brief (DMAC_CTRL reset_value) Control */
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| 81 |
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| 82 | #define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */
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| 83 | #define DMAC_CTRL_SWRST (0x1u << DMAC_CTRL_SWRST_Pos)
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| 84 | #define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */
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| 85 | #define DMAC_CTRL_DMAENABLE (0x1u << DMAC_CTRL_DMAENABLE_Pos)
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| 86 | #define DMAC_CTRL_CRCENABLE_Pos 2 /**< \brief (DMAC_CTRL) CRC Enable */
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| 87 | #define DMAC_CTRL_CRCENABLE (0x1u << DMAC_CTRL_CRCENABLE_Pos)
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| 88 | #define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */
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| 89 | #define DMAC_CTRL_LVLEN0 (1 << DMAC_CTRL_LVLEN0_Pos)
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| 90 | #define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */
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| 91 | #define DMAC_CTRL_LVLEN1 (1 << DMAC_CTRL_LVLEN1_Pos)
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| 92 | #define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */
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| 93 | #define DMAC_CTRL_LVLEN2 (1 << DMAC_CTRL_LVLEN2_Pos)
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| 94 | #define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */
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| 95 | #define DMAC_CTRL_LVLEN3 (1 << DMAC_CTRL_LVLEN3_Pos)
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| 96 | #define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */
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| 97 | #define DMAC_CTRL_LVLEN_Msk (0xFu << DMAC_CTRL_LVLEN_Pos)
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| 98 | #define DMAC_CTRL_LVLEN(value) ((DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)))
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| 99 | #define DMAC_CTRL_MASK 0x0F07u /**< \brief (DMAC_CTRL) MASK Register */
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| 100 |
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| 101 | /* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
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| 102 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 103 | typedef union {
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| 104 | struct {
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| 105 | uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
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| 106 | uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
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| 107 | uint16_t :4; /*!< bit: 4.. 7 Reserved */
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| 108 | uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
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| 109 | uint16_t :2; /*!< bit: 14..15 Reserved */
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| 110 | } bit; /*!< Structure used for bit access */
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| 111 | uint16_t reg; /*!< Type used for register access */
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| 112 | } DMAC_CRCCTRL_Type;
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| 113 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 114 |
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| 115 | #define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */
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| 116 | #define DMAC_CRCCTRL_RESETVALUE 0x0000 /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */
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| 117 |
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| 118 | #define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */
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| 119 | #define DMAC_CRCCTRL_CRCBEATSIZE_Msk (0x3u << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
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| 120 | #define DMAC_CRCCTRL_CRCBEATSIZE(value) ((DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)))
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| 121 | #define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val 0x0u /**< \brief (DMAC_CRCCTRL) Byte bus access */
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| 122 | #define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val 0x1u /**< \brief (DMAC_CRCCTRL) Half-word bus access */
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| 123 | #define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val 0x2u /**< \brief (DMAC_CRCCTRL) Word bus access */
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| 124 | #define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
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| 125 | #define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
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| 126 | #define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
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| 127 | #define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */
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| 128 | #define DMAC_CRCCTRL_CRCPOLY_Msk (0x3u << DMAC_CRCCTRL_CRCPOLY_Pos)
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| 129 | #define DMAC_CRCCTRL_CRCPOLY(value) ((DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)))
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| 130 | #define DMAC_CRCCTRL_CRCPOLY_CRC16_Val 0x0u /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */
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| 131 | #define DMAC_CRCCTRL_CRCPOLY_CRC32_Val 0x1u /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */
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| 132 | #define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
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| 133 | #define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
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| 134 | #define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */
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| 135 | #define DMAC_CRCCTRL_CRCSRC_Msk (0x3Fu << DMAC_CRCCTRL_CRCSRC_Pos)
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| 136 | #define DMAC_CRCCTRL_CRCSRC(value) ((DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)))
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| 137 | #define DMAC_CRCCTRL_CRCSRC_NOACT_Val 0x0u /**< \brief (DMAC_CRCCTRL) No action */
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| 138 | #define DMAC_CRCCTRL_CRCSRC_IO_Val 0x1u /**< \brief (DMAC_CRCCTRL) I/O interface */
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| 139 | #define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos)
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| 140 | #define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos)
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| 141 | #define DMAC_CRCCTRL_MASK 0x3F0Fu /**< \brief (DMAC_CRCCTRL) MASK Register */
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| 142 |
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| 143 | /* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
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| 144 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 145 | typedef union {
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| 146 | struct {
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| 147 | uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
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| 148 | } bit; /*!< Structure used for bit access */
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| 149 | uint32_t reg; /*!< Type used for register access */
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| 150 | } DMAC_CRCDATAIN_Type;
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| 151 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 152 |
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| 153 | #define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */
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| 154 | #define DMAC_CRCDATAIN_RESETVALUE 0x00000000 /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */
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| 155 |
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| 156 | #define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */
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| 157 | #define DMAC_CRCDATAIN_CRCDATAIN_Msk (0xFFFFFFFFu << DMAC_CRCDATAIN_CRCDATAIN_Pos)
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| 158 | #define DMAC_CRCDATAIN_CRCDATAIN(value) ((DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)))
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| 159 | #define DMAC_CRCDATAIN_MASK 0xFFFFFFFFu /**< \brief (DMAC_CRCDATAIN) MASK Register */
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| 160 |
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| 161 | /* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
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| 162 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 163 | typedef union {
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| 164 | struct {
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| 165 | uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
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| 166 | } bit; /*!< Structure used for bit access */
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| 167 | uint32_t reg; /*!< Type used for register access */
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| 168 | } DMAC_CRCCHKSUM_Type;
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| 169 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 170 |
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| 171 | #define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */
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| 172 | #define DMAC_CRCCHKSUM_RESETVALUE 0x00000000 /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */
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| 173 |
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| 174 | #define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */
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| 175 | #define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (0xFFFFFFFFu << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)
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| 176 | #define DMAC_CRCCHKSUM_CRCCHKSUM(value) ((DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)))
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| 177 | #define DMAC_CRCCHKSUM_MASK 0xFFFFFFFFu /**< \brief (DMAC_CRCCHKSUM) MASK Register */
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| 178 |
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| 179 | /* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */
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| 180 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 181 | typedef union {
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| 182 | struct {
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| 183 | uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
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| 184 | uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
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| 185 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
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| 186 | } bit; /*!< Structure used for bit access */
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| 187 | uint8_t reg; /*!< Type used for register access */
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| 188 | } DMAC_CRCSTATUS_Type;
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| 189 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 190 |
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| 191 | #define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */
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| 192 | #define DMAC_CRCSTATUS_RESETVALUE 0x00 /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */
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| 193 |
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| 194 | #define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */
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| 195 | #define DMAC_CRCSTATUS_CRCBUSY (0x1u << DMAC_CRCSTATUS_CRCBUSY_Pos)
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| 196 | #define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */
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| 197 | #define DMAC_CRCSTATUS_CRCZERO (0x1u << DMAC_CRCSTATUS_CRCZERO_Pos)
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| 198 | #define DMAC_CRCSTATUS_MASK 0x03u /**< \brief (DMAC_CRCSTATUS) MASK Register */
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| 199 |
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| 200 | /* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */
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| 201 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 202 | typedef union {
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| 203 | struct {
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| 204 | uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
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| 205 | uint8_t :7; /*!< bit: 1.. 7 Reserved */
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| 206 | } bit; /*!< Structure used for bit access */
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| 207 | uint8_t reg; /*!< Type used for register access */
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| 208 | } DMAC_DBGCTRL_Type;
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| 209 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 210 |
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| 211 | #define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */
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| 212 | #define DMAC_DBGCTRL_RESETVALUE 0x00 /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */
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| 213 |
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| 214 | #define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */
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| 215 | #define DMAC_DBGCTRL_DBGRUN (0x1u << DMAC_DBGCTRL_DBGRUN_Pos)
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| 216 | #define DMAC_DBGCTRL_MASK 0x01u /**< \brief (DMAC_DBGCTRL) MASK Register */
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| 217 |
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| 218 | /* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
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| 219 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 220 | typedef union {
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| 221 | struct {
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| 222 | uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
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| 223 | uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
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| 224 | uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
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| 225 | uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
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| 226 | uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
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| 227 | uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
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| 228 | uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
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| 229 | uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
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| 230 | uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
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| 231 | uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
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| 232 | uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
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| 233 | uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
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| 234 | uint32_t :20; /*!< bit: 12..31 Reserved */
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| 235 | } bit; /*!< Structure used for bit access */
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| 236 | struct {
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| 237 | uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */
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| 238 | uint32_t :20; /*!< bit: 12..31 Reserved */
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| 239 | } vec; /*!< Structure used for vec access */
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| 240 | uint32_t reg; /*!< Type used for register access */
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| 241 | } DMAC_SWTRIGCTRL_Type;
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| 242 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 243 |
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| 244 | #define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */
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| 245 | #define DMAC_SWTRIGCTRL_RESETVALUE 0x00000000 /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */
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| 246 |
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| 247 | #define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */
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| 248 | #define DMAC_SWTRIGCTRL_SWTRIG0 (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos)
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| 249 | #define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */
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| 250 | #define DMAC_SWTRIGCTRL_SWTRIG1 (1 << DMAC_SWTRIGCTRL_SWTRIG1_Pos)
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| 251 | #define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */
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| 252 | #define DMAC_SWTRIGCTRL_SWTRIG2 (1 << DMAC_SWTRIGCTRL_SWTRIG2_Pos)
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| 253 | #define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */
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| 254 | #define DMAC_SWTRIGCTRL_SWTRIG3 (1 << DMAC_SWTRIGCTRL_SWTRIG3_Pos)
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| 255 | #define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */
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| 256 | #define DMAC_SWTRIGCTRL_SWTRIG4 (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos)
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| 257 | #define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */
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| 258 | #define DMAC_SWTRIGCTRL_SWTRIG5 (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos)
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| 259 | #define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */
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| 260 | #define DMAC_SWTRIGCTRL_SWTRIG6 (1 << DMAC_SWTRIGCTRL_SWTRIG6_Pos)
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| 261 | #define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */
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| 262 | #define DMAC_SWTRIGCTRL_SWTRIG7 (1 << DMAC_SWTRIGCTRL_SWTRIG7_Pos)
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| 263 | #define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */
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| 264 | #define DMAC_SWTRIGCTRL_SWTRIG8 (1 << DMAC_SWTRIGCTRL_SWTRIG8_Pos)
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| 265 | #define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */
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| 266 | #define DMAC_SWTRIGCTRL_SWTRIG9 (1 << DMAC_SWTRIGCTRL_SWTRIG9_Pos)
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| 267 | #define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */
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| 268 | #define DMAC_SWTRIGCTRL_SWTRIG10 (1 << DMAC_SWTRIGCTRL_SWTRIG10_Pos)
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| 269 | #define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */
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| 270 | #define DMAC_SWTRIGCTRL_SWTRIG11 (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos)
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| 271 | #define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */
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| 272 | #define DMAC_SWTRIGCTRL_SWTRIG_Msk (0xFFFu << DMAC_SWTRIGCTRL_SWTRIG_Pos)
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| 273 | #define DMAC_SWTRIGCTRL_SWTRIG(value) ((DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)))
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| 274 | #define DMAC_SWTRIGCTRL_MASK 0x00000FFFu /**< \brief (DMAC_SWTRIGCTRL) MASK Register */
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| 275 |
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| 276 | /* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
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| 277 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 278 | typedef union {
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| 279 | struct {
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| 280 | uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */
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| 281 | uint32_t :3; /*!< bit: 4.. 6 Reserved */
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| 282 | uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
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| 283 | uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */
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| 284 | uint32_t :3; /*!< bit: 12..14 Reserved */
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| 285 | uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
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| 286 | uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */
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| 287 | uint32_t :3; /*!< bit: 20..22 Reserved */
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| 288 | uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
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| 289 | uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */
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| 290 | uint32_t :3; /*!< bit: 28..30 Reserved */
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| 291 | uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
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| 292 | } bit; /*!< Structure used for bit access */
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| 293 | uint32_t reg; /*!< Type used for register access */
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| 294 | } DMAC_PRICTRL0_Type;
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| 295 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 296 |
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| 297 | #define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */
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| 298 | #define DMAC_PRICTRL0_RESETVALUE 0x00000000 /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */
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| 299 |
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| 300 | #define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */
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| 301 | #define DMAC_PRICTRL0_LVLPRI0_Msk (0xFu << DMAC_PRICTRL0_LVLPRI0_Pos)
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| 302 | #define DMAC_PRICTRL0_LVLPRI0(value) ((DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)))
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| 303 | #define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */
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| 304 | #define DMAC_PRICTRL0_RRLVLEN0 (0x1u << DMAC_PRICTRL0_RRLVLEN0_Pos)
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| 305 | #define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */
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| 306 | #define DMAC_PRICTRL0_LVLPRI1_Msk (0xFu << DMAC_PRICTRL0_LVLPRI1_Pos)
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| 307 | #define DMAC_PRICTRL0_LVLPRI1(value) ((DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)))
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| 308 | #define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */
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| 309 | #define DMAC_PRICTRL0_RRLVLEN1 (0x1u << DMAC_PRICTRL0_RRLVLEN1_Pos)
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| 310 | #define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */
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| 311 | #define DMAC_PRICTRL0_LVLPRI2_Msk (0xFu << DMAC_PRICTRL0_LVLPRI2_Pos)
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| 312 | #define DMAC_PRICTRL0_LVLPRI2(value) ((DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)))
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| 313 | #define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */
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| 314 | #define DMAC_PRICTRL0_RRLVLEN2 (0x1u << DMAC_PRICTRL0_RRLVLEN2_Pos)
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| 315 | #define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */
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| 316 | #define DMAC_PRICTRL0_LVLPRI3_Msk (0xFu << DMAC_PRICTRL0_LVLPRI3_Pos)
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| 317 | #define DMAC_PRICTRL0_LVLPRI3(value) ((DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)))
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| 318 | #define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */
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| 319 | #define DMAC_PRICTRL0_RRLVLEN3 (0x1u << DMAC_PRICTRL0_RRLVLEN3_Pos)
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| 320 | #define DMAC_PRICTRL0_MASK 0x8F8F8F8Fu /**< \brief (DMAC_PRICTRL0) MASK Register */
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| 321 |
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| 322 | /* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
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| 323 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
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| 324 | typedef union {
|
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| 325 | struct {
|
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| 326 | uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
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| 327 | uint16_t :4; /*!< bit: 4.. 7 Reserved */
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| 328 | uint16_t TERR:1; /*!< bit: 8 Transfer Error */
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| 329 | uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
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| 330 | uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
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| 331 | uint16_t :2; /*!< bit: 11..12 Reserved */
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| 332 | uint16_t FERR:1; /*!< bit: 13 Fetch Error */
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| 333 | uint16_t BUSY:1; /*!< bit: 14 Busy */
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| 334 | uint16_t PEND:1; /*!< bit: 15 Pending */
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| 335 | } bit; /*!< Structure used for bit access */
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| 336 | uint16_t reg; /*!< Type used for register access */
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| 337 | } DMAC_INTPEND_Type;
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| 338 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
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| 339 |
|
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| 340 | #define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */
|
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| 341 | #define DMAC_INTPEND_RESETVALUE 0x0000 /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */
|
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| 342 |
|
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| 343 | #define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */
|
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| 344 | #define DMAC_INTPEND_ID_Msk (0xFu << DMAC_INTPEND_ID_Pos)
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| 345 | #define DMAC_INTPEND_ID(value) ((DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)))
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| 346 | #define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */
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| 347 | #define DMAC_INTPEND_TERR (0x1u << DMAC_INTPEND_TERR_Pos)
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| 348 | #define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */
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| 349 | #define DMAC_INTPEND_TCMPL (0x1u << DMAC_INTPEND_TCMPL_Pos)
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| 350 | #define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */
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| 351 | #define DMAC_INTPEND_SUSP (0x1u << DMAC_INTPEND_SUSP_Pos)
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| 352 | #define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */
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| 353 | #define DMAC_INTPEND_FERR (0x1u << DMAC_INTPEND_FERR_Pos)
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| 354 | #define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */
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| 355 | #define DMAC_INTPEND_BUSY (0x1u << DMAC_INTPEND_BUSY_Pos)
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| 356 | #define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */
|
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| 357 | #define DMAC_INTPEND_PEND (0x1u << DMAC_INTPEND_PEND_Pos)
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| 358 | #define DMAC_INTPEND_MASK 0xE70Fu /**< \brief (DMAC_INTPEND) MASK Register */
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| 359 |
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| 360 | /* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */
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| 361 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
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| 362 | typedef union {
|
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| 363 | struct {
|
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| 364 | uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
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| 365 | uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
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| 366 | uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
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| 367 | uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
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| 368 | uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
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| 369 | uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
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| 370 | uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
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| 371 | uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
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| 372 | uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
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| 373 | uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
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| 374 | uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
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| 375 | uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
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| 376 | uint32_t :20; /*!< bit: 12..31 Reserved */
|
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| 377 | } bit; /*!< Structure used for bit access */
|
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| 378 | struct {
|
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| 379 | uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
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| 380 | uint32_t :20; /*!< bit: 12..31 Reserved */
|
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| 381 | } vec; /*!< Structure used for vec access */
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| 382 | uint32_t reg; /*!< Type used for register access */
|
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| 383 | } DMAC_INTSTATUS_Type;
|
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| 384 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
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| 385 |
|
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| 386 | #define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */
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| 387 | #define DMAC_INTSTATUS_RESETVALUE 0x00000000 /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */
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| 388 |
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| 389 | #define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */
|
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| 390 | #define DMAC_INTSTATUS_CHINT0 (1 << DMAC_INTSTATUS_CHINT0_Pos)
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| 391 | #define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */
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| 392 | #define DMAC_INTSTATUS_CHINT1 (1 << DMAC_INTSTATUS_CHINT1_Pos)
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| 393 | #define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */
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| 394 | #define DMAC_INTSTATUS_CHINT2 (1 << DMAC_INTSTATUS_CHINT2_Pos)
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| 395 | #define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */
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| 396 | #define DMAC_INTSTATUS_CHINT3 (1 << DMAC_INTSTATUS_CHINT3_Pos)
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| 397 | #define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */
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| 398 | #define DMAC_INTSTATUS_CHINT4 (1 << DMAC_INTSTATUS_CHINT4_Pos)
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| 399 | #define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */
|
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| 400 | #define DMAC_INTSTATUS_CHINT5 (1 << DMAC_INTSTATUS_CHINT5_Pos)
|
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| 401 | #define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */
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| 402 | #define DMAC_INTSTATUS_CHINT6 (1 << DMAC_INTSTATUS_CHINT6_Pos)
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| 403 | #define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */
|
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| 404 | #define DMAC_INTSTATUS_CHINT7 (1 << DMAC_INTSTATUS_CHINT7_Pos)
|
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| 405 | #define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */
|
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| 406 | #define DMAC_INTSTATUS_CHINT8 (1 << DMAC_INTSTATUS_CHINT8_Pos)
|
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| 407 | #define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */
|
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| 408 | #define DMAC_INTSTATUS_CHINT9 (1 << DMAC_INTSTATUS_CHINT9_Pos)
|
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| 409 | #define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */
|
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| 410 | #define DMAC_INTSTATUS_CHINT10 (1 << DMAC_INTSTATUS_CHINT10_Pos)
|
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| 411 | #define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */
|
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| 412 | #define DMAC_INTSTATUS_CHINT11 (1 << DMAC_INTSTATUS_CHINT11_Pos)
|
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| 413 | #define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */
|
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| 414 | #define DMAC_INTSTATUS_CHINT_Msk (0xFFFu << DMAC_INTSTATUS_CHINT_Pos)
|
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| 415 | #define DMAC_INTSTATUS_CHINT(value) ((DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)))
|
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| 416 | #define DMAC_INTSTATUS_MASK 0x00000FFFu /**< \brief (DMAC_INTSTATUS) MASK Register */
|
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| 417 |
|
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| 418 | /* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */
|
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| 419 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 420 | typedef union {
|
---|
| 421 | struct {
|
---|
| 422 | uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
|
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| 423 | uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
|
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| 424 | uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
|
---|
| 425 | uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
|
---|
| 426 | uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
|
---|
| 427 | uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
|
---|
| 428 | uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
|
---|
| 429 | uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
|
---|
| 430 | uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
|
---|
| 431 | uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
|
---|
| 432 | uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
|
---|
| 433 | uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
|
---|
| 434 | uint32_t :20; /*!< bit: 12..31 Reserved */
|
---|
| 435 | } bit; /*!< Structure used for bit access */
|
---|
| 436 | struct {
|
---|
| 437 | uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
|
---|
| 438 | uint32_t :20; /*!< bit: 12..31 Reserved */
|
---|
| 439 | } vec; /*!< Structure used for vec access */
|
---|
| 440 | uint32_t reg; /*!< Type used for register access */
|
---|
| 441 | } DMAC_BUSYCH_Type;
|
---|
| 442 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 443 |
|
---|
| 444 | #define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */
|
---|
| 445 | #define DMAC_BUSYCH_RESETVALUE 0x00000000 /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */
|
---|
| 446 |
|
---|
| 447 | #define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */
|
---|
| 448 | #define DMAC_BUSYCH_BUSYCH0 (1 << DMAC_BUSYCH_BUSYCH0_Pos)
|
---|
| 449 | #define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */
|
---|
| 450 | #define DMAC_BUSYCH_BUSYCH1 (1 << DMAC_BUSYCH_BUSYCH1_Pos)
|
---|
| 451 | #define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */
|
---|
| 452 | #define DMAC_BUSYCH_BUSYCH2 (1 << DMAC_BUSYCH_BUSYCH2_Pos)
|
---|
| 453 | #define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */
|
---|
| 454 | #define DMAC_BUSYCH_BUSYCH3 (1 << DMAC_BUSYCH_BUSYCH3_Pos)
|
---|
| 455 | #define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */
|
---|
| 456 | #define DMAC_BUSYCH_BUSYCH4 (1 << DMAC_BUSYCH_BUSYCH4_Pos)
|
---|
| 457 | #define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */
|
---|
| 458 | #define DMAC_BUSYCH_BUSYCH5 (1 << DMAC_BUSYCH_BUSYCH5_Pos)
|
---|
| 459 | #define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */
|
---|
| 460 | #define DMAC_BUSYCH_BUSYCH6 (1 << DMAC_BUSYCH_BUSYCH6_Pos)
|
---|
| 461 | #define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */
|
---|
| 462 | #define DMAC_BUSYCH_BUSYCH7 (1 << DMAC_BUSYCH_BUSYCH7_Pos)
|
---|
| 463 | #define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */
|
---|
| 464 | #define DMAC_BUSYCH_BUSYCH8 (1 << DMAC_BUSYCH_BUSYCH8_Pos)
|
---|
| 465 | #define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */
|
---|
| 466 | #define DMAC_BUSYCH_BUSYCH9 (1 << DMAC_BUSYCH_BUSYCH9_Pos)
|
---|
| 467 | #define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */
|
---|
| 468 | #define DMAC_BUSYCH_BUSYCH10 (1 << DMAC_BUSYCH_BUSYCH10_Pos)
|
---|
| 469 | #define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */
|
---|
| 470 | #define DMAC_BUSYCH_BUSYCH11 (1 << DMAC_BUSYCH_BUSYCH11_Pos)
|
---|
| 471 | #define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */
|
---|
| 472 | #define DMAC_BUSYCH_BUSYCH_Msk (0xFFFu << DMAC_BUSYCH_BUSYCH_Pos)
|
---|
| 473 | #define DMAC_BUSYCH_BUSYCH(value) ((DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)))
|
---|
| 474 | #define DMAC_BUSYCH_MASK 0x00000FFFu /**< \brief (DMAC_BUSYCH) MASK Register */
|
---|
| 475 |
|
---|
| 476 | /* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */
|
---|
| 477 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 478 | typedef union {
|
---|
| 479 | struct {
|
---|
| 480 | uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
|
---|
| 481 | uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
|
---|
| 482 | uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
|
---|
| 483 | uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
|
---|
| 484 | uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
|
---|
| 485 | uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
|
---|
| 486 | uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
|
---|
| 487 | uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
|
---|
| 488 | uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
|
---|
| 489 | uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
|
---|
| 490 | uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
|
---|
| 491 | uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
|
---|
| 492 | uint32_t :20; /*!< bit: 12..31 Reserved */
|
---|
| 493 | } bit; /*!< Structure used for bit access */
|
---|
| 494 | struct {
|
---|
| 495 | uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */
|
---|
| 496 | uint32_t :20; /*!< bit: 12..31 Reserved */
|
---|
| 497 | } vec; /*!< Structure used for vec access */
|
---|
| 498 | uint32_t reg; /*!< Type used for register access */
|
---|
| 499 | } DMAC_PENDCH_Type;
|
---|
| 500 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 501 |
|
---|
| 502 | #define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */
|
---|
| 503 | #define DMAC_PENDCH_RESETVALUE 0x00000000 /**< \brief (DMAC_PENDCH reset_value) Pending Channels */
|
---|
| 504 |
|
---|
| 505 | #define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */
|
---|
| 506 | #define DMAC_PENDCH_PENDCH0 (1 << DMAC_PENDCH_PENDCH0_Pos)
|
---|
| 507 | #define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */
|
---|
| 508 | #define DMAC_PENDCH_PENDCH1 (1 << DMAC_PENDCH_PENDCH1_Pos)
|
---|
| 509 | #define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */
|
---|
| 510 | #define DMAC_PENDCH_PENDCH2 (1 << DMAC_PENDCH_PENDCH2_Pos)
|
---|
| 511 | #define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */
|
---|
| 512 | #define DMAC_PENDCH_PENDCH3 (1 << DMAC_PENDCH_PENDCH3_Pos)
|
---|
| 513 | #define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */
|
---|
| 514 | #define DMAC_PENDCH_PENDCH4 (1 << DMAC_PENDCH_PENDCH4_Pos)
|
---|
| 515 | #define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */
|
---|
| 516 | #define DMAC_PENDCH_PENDCH5 (1 << DMAC_PENDCH_PENDCH5_Pos)
|
---|
| 517 | #define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */
|
---|
| 518 | #define DMAC_PENDCH_PENDCH6 (1 << DMAC_PENDCH_PENDCH6_Pos)
|
---|
| 519 | #define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */
|
---|
| 520 | #define DMAC_PENDCH_PENDCH7 (1 << DMAC_PENDCH_PENDCH7_Pos)
|
---|
| 521 | #define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */
|
---|
| 522 | #define DMAC_PENDCH_PENDCH8 (1 << DMAC_PENDCH_PENDCH8_Pos)
|
---|
| 523 | #define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */
|
---|
| 524 | #define DMAC_PENDCH_PENDCH9 (1 << DMAC_PENDCH_PENDCH9_Pos)
|
---|
| 525 | #define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */
|
---|
| 526 | #define DMAC_PENDCH_PENDCH10 (1 << DMAC_PENDCH_PENDCH10_Pos)
|
---|
| 527 | #define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */
|
---|
| 528 | #define DMAC_PENDCH_PENDCH11 (1 << DMAC_PENDCH_PENDCH11_Pos)
|
---|
| 529 | #define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */
|
---|
| 530 | #define DMAC_PENDCH_PENDCH_Msk (0xFFFu << DMAC_PENDCH_PENDCH_Pos)
|
---|
| 531 | #define DMAC_PENDCH_PENDCH(value) ((DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)))
|
---|
| 532 | #define DMAC_PENDCH_MASK 0x00000FFFu /**< \brief (DMAC_PENDCH) MASK Register */
|
---|
| 533 |
|
---|
| 534 | /* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */
|
---|
| 535 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 536 | typedef union {
|
---|
| 537 | struct {
|
---|
| 538 | uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
|
---|
| 539 | uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
|
---|
| 540 | uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
|
---|
| 541 | uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
|
---|
| 542 | uint32_t :4; /*!< bit: 4.. 7 Reserved */
|
---|
| 543 | uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
|
---|
| 544 | uint32_t :2; /*!< bit: 13..14 Reserved */
|
---|
| 545 | uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
|
---|
| 546 | uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
|
---|
| 547 | } bit; /*!< Structure used for bit access */
|
---|
| 548 | struct {
|
---|
| 549 | uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
|
---|
| 550 | uint32_t :28; /*!< bit: 4..31 Reserved */
|
---|
| 551 | } vec; /*!< Structure used for vec access */
|
---|
| 552 | uint32_t reg; /*!< Type used for register access */
|
---|
| 553 | } DMAC_ACTIVE_Type;
|
---|
| 554 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 555 |
|
---|
| 556 | #define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */
|
---|
| 557 | #define DMAC_ACTIVE_RESETVALUE 0x00000000 /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */
|
---|
| 558 |
|
---|
| 559 | #define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */
|
---|
| 560 | #define DMAC_ACTIVE_LVLEX0 (1 << DMAC_ACTIVE_LVLEX0_Pos)
|
---|
| 561 | #define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */
|
---|
| 562 | #define DMAC_ACTIVE_LVLEX1 (1 << DMAC_ACTIVE_LVLEX1_Pos)
|
---|
| 563 | #define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */
|
---|
| 564 | #define DMAC_ACTIVE_LVLEX2 (1 << DMAC_ACTIVE_LVLEX2_Pos)
|
---|
| 565 | #define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */
|
---|
| 566 | #define DMAC_ACTIVE_LVLEX3 (1 << DMAC_ACTIVE_LVLEX3_Pos)
|
---|
| 567 | #define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */
|
---|
| 568 | #define DMAC_ACTIVE_LVLEX_Msk (0xFu << DMAC_ACTIVE_LVLEX_Pos)
|
---|
| 569 | #define DMAC_ACTIVE_LVLEX(value) ((DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)))
|
---|
| 570 | #define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */
|
---|
| 571 | #define DMAC_ACTIVE_ID_Msk (0x1Fu << DMAC_ACTIVE_ID_Pos)
|
---|
| 572 | #define DMAC_ACTIVE_ID(value) ((DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)))
|
---|
| 573 | #define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */
|
---|
| 574 | #define DMAC_ACTIVE_ABUSY (0x1u << DMAC_ACTIVE_ABUSY_Pos)
|
---|
| 575 | #define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */
|
---|
| 576 | #define DMAC_ACTIVE_BTCNT_Msk (0xFFFFu << DMAC_ACTIVE_BTCNT_Pos)
|
---|
| 577 | #define DMAC_ACTIVE_BTCNT(value) ((DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)))
|
---|
| 578 | #define DMAC_ACTIVE_MASK 0xFFFF9F0Fu /**< \brief (DMAC_ACTIVE) MASK Register */
|
---|
| 579 |
|
---|
| 580 | /* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
|
---|
| 581 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 582 | typedef union {
|
---|
| 583 | struct {
|
---|
| 584 | uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
|
---|
| 585 | } bit; /*!< Structure used for bit access */
|
---|
| 586 | uint32_t reg; /*!< Type used for register access */
|
---|
| 587 | } DMAC_BASEADDR_Type;
|
---|
| 588 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 589 |
|
---|
| 590 | #define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */
|
---|
| 591 | #define DMAC_BASEADDR_RESETVALUE 0x00000000 /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */
|
---|
| 592 |
|
---|
| 593 | #define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */
|
---|
| 594 | #define DMAC_BASEADDR_BASEADDR_Msk (0xFFFFFFFFu << DMAC_BASEADDR_BASEADDR_Pos)
|
---|
| 595 | #define DMAC_BASEADDR_BASEADDR(value) ((DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)))
|
---|
| 596 | #define DMAC_BASEADDR_MASK 0xFFFFFFFFu /**< \brief (DMAC_BASEADDR) MASK Register */
|
---|
| 597 |
|
---|
| 598 | /* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
|
---|
| 599 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 600 | typedef union {
|
---|
| 601 | struct {
|
---|
| 602 | uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
|
---|
| 603 | } bit; /*!< Structure used for bit access */
|
---|
| 604 | uint32_t reg; /*!< Type used for register access */
|
---|
| 605 | } DMAC_WRBADDR_Type;
|
---|
| 606 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 607 |
|
---|
| 608 | #define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */
|
---|
| 609 | #define DMAC_WRBADDR_RESETVALUE 0x00000000 /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */
|
---|
| 610 |
|
---|
| 611 | #define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */
|
---|
| 612 | #define DMAC_WRBADDR_WRBADDR_Msk (0xFFFFFFFFu << DMAC_WRBADDR_WRBADDR_Pos)
|
---|
| 613 | #define DMAC_WRBADDR_WRBADDR(value) ((DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)))
|
---|
| 614 | #define DMAC_WRBADDR_MASK 0xFFFFFFFFu /**< \brief (DMAC_WRBADDR) MASK Register */
|
---|
| 615 |
|
---|
| 616 | /* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */
|
---|
| 617 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 618 | typedef union {
|
---|
| 619 | struct {
|
---|
| 620 | uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */
|
---|
| 621 | uint8_t :4; /*!< bit: 4.. 7 Reserved */
|
---|
| 622 | } bit; /*!< Structure used for bit access */
|
---|
| 623 | uint8_t reg; /*!< Type used for register access */
|
---|
| 624 | } DMAC_CHID_Type;
|
---|
| 625 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 626 |
|
---|
| 627 | #define DMAC_CHID_OFFSET 0x3F /**< \brief (DMAC_CHID offset) Channel ID */
|
---|
| 628 | #define DMAC_CHID_RESETVALUE 0x00 /**< \brief (DMAC_CHID reset_value) Channel ID */
|
---|
| 629 |
|
---|
| 630 | #define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */
|
---|
| 631 | #define DMAC_CHID_ID_Msk (0xFu << DMAC_CHID_ID_Pos)
|
---|
| 632 | #define DMAC_CHID_ID(value) ((DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos)))
|
---|
| 633 | #define DMAC_CHID_MASK 0x0Fu /**< \brief (DMAC_CHID) MASK Register */
|
---|
| 634 |
|
---|
| 635 | /* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */
|
---|
| 636 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 637 | typedef union {
|
---|
| 638 | struct {
|
---|
| 639 | uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */
|
---|
| 640 | uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */
|
---|
| 641 | uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
---|
| 642 | } bit; /*!< Structure used for bit access */
|
---|
| 643 | uint8_t reg; /*!< Type used for register access */
|
---|
| 644 | } DMAC_CHCTRLA_Type;
|
---|
| 645 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 646 |
|
---|
| 647 | #define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel Control A */
|
---|
| 648 | #define DMAC_CHCTRLA_RESETVALUE 0x00 /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */
|
---|
| 649 |
|
---|
| 650 | #define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */
|
---|
| 651 | #define DMAC_CHCTRLA_SWRST (0x1u << DMAC_CHCTRLA_SWRST_Pos)
|
---|
| 652 | #define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */
|
---|
| 653 | #define DMAC_CHCTRLA_ENABLE (0x1u << DMAC_CHCTRLA_ENABLE_Pos)
|
---|
| 654 | #define DMAC_CHCTRLA_MASK 0x03u /**< \brief (DMAC_CHCTRLA) MASK Register */
|
---|
| 655 |
|
---|
| 656 | /* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */
|
---|
| 657 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 658 | typedef union {
|
---|
| 659 | struct {
|
---|
| 660 | uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */
|
---|
| 661 | uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */
|
---|
| 662 | uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */
|
---|
| 663 | uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */
|
---|
| 664 | uint32_t :1; /*!< bit: 7 Reserved */
|
---|
| 665 | uint32_t TRIGSRC:6; /*!< bit: 8..13 Peripheral Trigger Source */
|
---|
| 666 | uint32_t :8; /*!< bit: 14..21 Reserved */
|
---|
| 667 | uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */
|
---|
| 668 | uint32_t CMD:2; /*!< bit: 24..25 Software Command */
|
---|
| 669 | uint32_t :6; /*!< bit: 26..31 Reserved */
|
---|
| 670 | } bit; /*!< Structure used for bit access */
|
---|
| 671 | uint32_t reg; /*!< Type used for register access */
|
---|
| 672 | } DMAC_CHCTRLB_Type;
|
---|
| 673 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 674 |
|
---|
| 675 | #define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel Control B */
|
---|
| 676 | #define DMAC_CHCTRLB_RESETVALUE 0x00000000 /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */
|
---|
| 677 |
|
---|
| 678 | #define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */
|
---|
| 679 | #define DMAC_CHCTRLB_EVACT_Msk (0x7u << DMAC_CHCTRLB_EVACT_Pos)
|
---|
| 680 | #define DMAC_CHCTRLB_EVACT(value) ((DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos)))
|
---|
| 681 | #define DMAC_CHCTRLB_EVACT_NOACT_Val 0x0u /**< \brief (DMAC_CHCTRLB) No action */
|
---|
| 682 | #define DMAC_CHCTRLB_EVACT_TRIG_Val 0x1u /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */
|
---|
| 683 | #define DMAC_CHCTRLB_EVACT_CTRIG_Val 0x2u /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */
|
---|
| 684 | #define DMAC_CHCTRLB_EVACT_CBLOCK_Val 0x3u /**< \brief (DMAC_CHCTRLB) Conditional block transfer */
|
---|
| 685 | #define DMAC_CHCTRLB_EVACT_SUSPEND_Val 0x4u /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
|
---|
| 686 | #define DMAC_CHCTRLB_EVACT_RESUME_Val 0x5u /**< \brief (DMAC_CHCTRLB) Channel resume operation */
|
---|
| 687 | #define DMAC_CHCTRLB_EVACT_SSKIP_Val 0x6u /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */
|
---|
| 688 | #define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos)
|
---|
| 689 | #define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos)
|
---|
| 690 | #define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos)
|
---|
| 691 | #define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos)
|
---|
| 692 | #define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos)
|
---|
| 693 | #define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos)
|
---|
| 694 | #define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos)
|
---|
| 695 | #define DMAC_CHCTRLB_EVIE_Pos 3 /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */
|
---|
| 696 | #define DMAC_CHCTRLB_EVIE (0x1u << DMAC_CHCTRLB_EVIE_Pos)
|
---|
| 697 | #define DMAC_CHCTRLB_EVOE_Pos 4 /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */
|
---|
| 698 | #define DMAC_CHCTRLB_EVOE (0x1u << DMAC_CHCTRLB_EVOE_Pos)
|
---|
| 699 | #define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */
|
---|
| 700 | #define DMAC_CHCTRLB_LVL_Msk (0x3u << DMAC_CHCTRLB_LVL_Pos)
|
---|
| 701 | #define DMAC_CHCTRLB_LVL(value) ((DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos)))
|
---|
| 702 | #define DMAC_CHCTRLB_LVL_LVL0_Val 0x0u /**< \brief (DMAC_CHCTRLB) Channel Priority Level 0 */
|
---|
| 703 | #define DMAC_CHCTRLB_LVL_LVL1_Val 0x1u /**< \brief (DMAC_CHCTRLB) Channel Priority Level 1 */
|
---|
| 704 | #define DMAC_CHCTRLB_LVL_LVL2_Val 0x2u /**< \brief (DMAC_CHCTRLB) Channel Priority Level 2 */
|
---|
| 705 | #define DMAC_CHCTRLB_LVL_LVL3_Val 0x3u /**< \brief (DMAC_CHCTRLB) Channel Priority Level 3 */
|
---|
| 706 | #define DMAC_CHCTRLB_LVL_LVL0 (DMAC_CHCTRLB_LVL_LVL0_Val << DMAC_CHCTRLB_LVL_Pos)
|
---|
| 707 | #define DMAC_CHCTRLB_LVL_LVL1 (DMAC_CHCTRLB_LVL_LVL1_Val << DMAC_CHCTRLB_LVL_Pos)
|
---|
| 708 | #define DMAC_CHCTRLB_LVL_LVL2 (DMAC_CHCTRLB_LVL_LVL2_Val << DMAC_CHCTRLB_LVL_Pos)
|
---|
| 709 | #define DMAC_CHCTRLB_LVL_LVL3 (DMAC_CHCTRLB_LVL_LVL3_Val << DMAC_CHCTRLB_LVL_Pos)
|
---|
| 710 | #define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Peripheral Trigger Source */
|
---|
| 711 | #define DMAC_CHCTRLB_TRIGSRC_Msk (0x3Fu << DMAC_CHCTRLB_TRIGSRC_Pos)
|
---|
| 712 | #define DMAC_CHCTRLB_TRIGSRC(value) ((DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos)))
|
---|
| 713 | #define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val 0x0u /**< \brief (DMAC_CHCTRLB) Only software/event triggers */
|
---|
| 714 | #define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos)
|
---|
| 715 | #define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */
|
---|
| 716 | #define DMAC_CHCTRLB_TRIGACT_Msk (0x3u << DMAC_CHCTRLB_TRIGACT_Pos)
|
---|
| 717 | #define DMAC_CHCTRLB_TRIGACT(value) ((DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos)))
|
---|
| 718 | #define DMAC_CHCTRLB_TRIGACT_BLOCK_Val 0x0u /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */
|
---|
| 719 | #define DMAC_CHCTRLB_TRIGACT_BEAT_Val 0x2u /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */
|
---|
| 720 | #define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val 0x3u /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */
|
---|
| 721 | #define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos)
|
---|
| 722 | #define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos)
|
---|
| 723 | #define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos)
|
---|
| 724 | #define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */
|
---|
| 725 | #define DMAC_CHCTRLB_CMD_Msk (0x3u << DMAC_CHCTRLB_CMD_Pos)
|
---|
| 726 | #define DMAC_CHCTRLB_CMD(value) ((DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)))
|
---|
| 727 | #define DMAC_CHCTRLB_CMD_NOACT_Val 0x0u /**< \brief (DMAC_CHCTRLB) No action */
|
---|
| 728 | #define DMAC_CHCTRLB_CMD_SUSPEND_Val 0x1u /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
|
---|
| 729 | #define DMAC_CHCTRLB_CMD_RESUME_Val 0x2u /**< \brief (DMAC_CHCTRLB) Channel resume operation */
|
---|
| 730 | #define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos)
|
---|
| 731 | #define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos)
|
---|
| 732 | #define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos)
|
---|
| 733 | #define DMAC_CHCTRLB_MASK 0x03C03F7Fu /**< \brief (DMAC_CHCTRLB) MASK Register */
|
---|
| 734 |
|
---|
| 735 | /* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */
|
---|
| 736 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 737 | typedef union {
|
---|
| 738 | struct {
|
---|
| 739 | uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */
|
---|
| 740 | uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */
|
---|
| 741 | uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
|
---|
| 742 | uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
---|
| 743 | } bit; /*!< Structure used for bit access */
|
---|
| 744 | uint8_t reg; /*!< Type used for register access */
|
---|
| 745 | } DMAC_CHINTENCLR_Type;
|
---|
| 746 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 747 |
|
---|
| 748 | #define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */
|
---|
| 749 | #define DMAC_CHINTENCLR_RESETVALUE 0x00 /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */
|
---|
| 750 |
|
---|
| 751 | #define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Transfer Error Interrupt Enable */
|
---|
| 752 | #define DMAC_CHINTENCLR_TERR (0x1u << DMAC_CHINTENCLR_TERR_Pos)
|
---|
| 753 | #define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Transfer Complete Interrupt Enable */
|
---|
| 754 | #define DMAC_CHINTENCLR_TCMPL (0x1u << DMAC_CHINTENCLR_TCMPL_Pos)
|
---|
| 755 | #define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */
|
---|
| 756 | #define DMAC_CHINTENCLR_SUSP (0x1u << DMAC_CHINTENCLR_SUSP_Pos)
|
---|
| 757 | #define DMAC_CHINTENCLR_MASK 0x07u /**< \brief (DMAC_CHINTENCLR) MASK Register */
|
---|
| 758 |
|
---|
| 759 | /* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */
|
---|
| 760 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 761 | typedef union {
|
---|
| 762 | struct {
|
---|
| 763 | uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */
|
---|
| 764 | uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */
|
---|
| 765 | uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
|
---|
| 766 | uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
---|
| 767 | } bit; /*!< Structure used for bit access */
|
---|
| 768 | uint8_t reg; /*!< Type used for register access */
|
---|
| 769 | } DMAC_CHINTENSET_Type;
|
---|
| 770 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 771 |
|
---|
| 772 | #define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */
|
---|
| 773 | #define DMAC_CHINTENSET_RESETVALUE 0x00 /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */
|
---|
| 774 |
|
---|
| 775 | #define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Transfer Error Interrupt Enable */
|
---|
| 776 | #define DMAC_CHINTENSET_TERR (0x1u << DMAC_CHINTENSET_TERR_Pos)
|
---|
| 777 | #define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Transfer Complete Interrupt Enable */
|
---|
| 778 | #define DMAC_CHINTENSET_TCMPL (0x1u << DMAC_CHINTENSET_TCMPL_Pos)
|
---|
| 779 | #define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */
|
---|
| 780 | #define DMAC_CHINTENSET_SUSP (0x1u << DMAC_CHINTENSET_SUSP_Pos)
|
---|
| 781 | #define DMAC_CHINTENSET_MASK 0x07u /**< \brief (DMAC_CHINTENSET) MASK Register */
|
---|
| 782 |
|
---|
| 783 | /* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */
|
---|
| 784 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 785 | typedef union {
|
---|
| 786 | struct {
|
---|
| 787 | uint8_t TERR:1; /*!< bit: 0 Transfer Error */
|
---|
| 788 | uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete */
|
---|
| 789 | uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
|
---|
| 790 | uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
---|
| 791 | } bit; /*!< Structure used for bit access */
|
---|
| 792 | uint8_t reg; /*!< Type used for register access */
|
---|
| 793 | } DMAC_CHINTFLAG_Type;
|
---|
| 794 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 795 |
|
---|
| 796 | #define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */
|
---|
| 797 | #define DMAC_CHINTFLAG_RESETVALUE 0x00 /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */
|
---|
| 798 |
|
---|
| 799 | #define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Transfer Error */
|
---|
| 800 | #define DMAC_CHINTFLAG_TERR (0x1u << DMAC_CHINTFLAG_TERR_Pos)
|
---|
| 801 | #define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Transfer Complete */
|
---|
| 802 | #define DMAC_CHINTFLAG_TCMPL (0x1u << DMAC_CHINTFLAG_TCMPL_Pos)
|
---|
| 803 | #define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */
|
---|
| 804 | #define DMAC_CHINTFLAG_SUSP (0x1u << DMAC_CHINTFLAG_SUSP_Pos)
|
---|
| 805 | #define DMAC_CHINTFLAG_MASK 0x07u /**< \brief (DMAC_CHINTFLAG) MASK Register */
|
---|
| 806 |
|
---|
| 807 | /* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */
|
---|
| 808 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 809 | typedef union {
|
---|
| 810 | struct {
|
---|
| 811 | uint8_t PEND:1; /*!< bit: 0 Channel Pending */
|
---|
| 812 | uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
|
---|
| 813 | uint8_t FERR:1; /*!< bit: 2 Fetch Error */
|
---|
| 814 | uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
---|
| 815 | } bit; /*!< Structure used for bit access */
|
---|
| 816 | uint8_t reg; /*!< Type used for register access */
|
---|
| 817 | } DMAC_CHSTATUS_Type;
|
---|
| 818 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 819 |
|
---|
| 820 | #define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel Status */
|
---|
| 821 | #define DMAC_CHSTATUS_RESETVALUE 0x00 /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */
|
---|
| 822 |
|
---|
| 823 | #define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */
|
---|
| 824 | #define DMAC_CHSTATUS_PEND (0x1u << DMAC_CHSTATUS_PEND_Pos)
|
---|
| 825 | #define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */
|
---|
| 826 | #define DMAC_CHSTATUS_BUSY (0x1u << DMAC_CHSTATUS_BUSY_Pos)
|
---|
| 827 | #define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Fetch Error */
|
---|
| 828 | #define DMAC_CHSTATUS_FERR (0x1u << DMAC_CHSTATUS_FERR_Pos)
|
---|
| 829 | #define DMAC_CHSTATUS_MASK 0x07u /**< \brief (DMAC_CHSTATUS) MASK Register */
|
---|
| 830 |
|
---|
| 831 | /* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
|
---|
| 832 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 833 | typedef union {
|
---|
| 834 | struct {
|
---|
| 835 | uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
|
---|
| 836 | uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */
|
---|
| 837 | uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
|
---|
| 838 | uint16_t :3; /*!< bit: 5.. 7 Reserved */
|
---|
| 839 | uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
|
---|
| 840 | uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
|
---|
| 841 | uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
|
---|
| 842 | uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
|
---|
| 843 | uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
|
---|
| 844 | } bit; /*!< Structure used for bit access */
|
---|
| 845 | uint16_t reg; /*!< Type used for register access */
|
---|
| 846 | } DMAC_BTCTRL_Type;
|
---|
| 847 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 848 |
|
---|
| 849 | #define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */
|
---|
| 850 |
|
---|
| 851 | #define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */
|
---|
| 852 | #define DMAC_BTCTRL_VALID (0x1u << DMAC_BTCTRL_VALID_Pos)
|
---|
| 853 | #define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */
|
---|
| 854 | #define DMAC_BTCTRL_EVOSEL_Msk (0x3u << DMAC_BTCTRL_EVOSEL_Pos)
|
---|
| 855 | #define DMAC_BTCTRL_EVOSEL(value) ((DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)))
|
---|
| 856 | #define DMAC_BTCTRL_EVOSEL_DISABLE_Val 0x0u /**< \brief (DMAC_BTCTRL) Event generation disabled */
|
---|
| 857 | #define DMAC_BTCTRL_EVOSEL_BLOCK_Val 0x1u /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */
|
---|
| 858 | #define DMAC_BTCTRL_EVOSEL_BEAT_Val 0x3u /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */
|
---|
| 859 | #define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos)
|
---|
| 860 | #define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos)
|
---|
| 861 | #define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos)
|
---|
| 862 | #define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */
|
---|
| 863 | #define DMAC_BTCTRL_BLOCKACT_Msk (0x3u << DMAC_BTCTRL_BLOCKACT_Pos)
|
---|
| 864 | #define DMAC_BTCTRL_BLOCKACT(value) ((DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)))
|
---|
| 865 | #define DMAC_BTCTRL_BLOCKACT_NOACT_Val 0x0u /**< \brief (DMAC_BTCTRL) No action */
|
---|
| 866 | #define DMAC_BTCTRL_BLOCKACT_INT_Val 0x1u /**< \brief (DMAC_BTCTRL) Channel in normal operation and block interrupt */
|
---|
| 867 | #define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val 0x2u /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */
|
---|
| 868 | #define DMAC_BTCTRL_BLOCKACT_BOTH_Val 0x3u /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */
|
---|
| 869 | #define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
|
---|
| 870 | #define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
|
---|
| 871 | #define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos)
|
---|
| 872 | #define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos)
|
---|
| 873 | #define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */
|
---|
| 874 | #define DMAC_BTCTRL_BEATSIZE_Msk (0x3u << DMAC_BTCTRL_BEATSIZE_Pos)
|
---|
| 875 | #define DMAC_BTCTRL_BEATSIZE(value) ((DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)))
|
---|
| 876 | #define DMAC_BTCTRL_BEATSIZE_BYTE_Val 0x0u /**< \brief (DMAC_BTCTRL) 8-bit access */
|
---|
| 877 | #define DMAC_BTCTRL_BEATSIZE_HWORD_Val 0x1u /**< \brief (DMAC_BTCTRL) 16-bit access */
|
---|
| 878 | #define DMAC_BTCTRL_BEATSIZE_WORD_Val 0x2u /**< \brief (DMAC_BTCTRL) 32-bit access */
|
---|
| 879 | #define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos)
|
---|
| 880 | #define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
|
---|
| 881 | #define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
|
---|
| 882 | #define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */
|
---|
| 883 | #define DMAC_BTCTRL_SRCINC (0x1u << DMAC_BTCTRL_SRCINC_Pos)
|
---|
| 884 | #define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */
|
---|
| 885 | #define DMAC_BTCTRL_DSTINC (0x1u << DMAC_BTCTRL_DSTINC_Pos)
|
---|
| 886 | #define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */
|
---|
| 887 | #define DMAC_BTCTRL_STEPSEL (0x1u << DMAC_BTCTRL_STEPSEL_Pos)
|
---|
| 888 | #define DMAC_BTCTRL_STEPSEL_DST_Val 0x0u /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */
|
---|
| 889 | #define DMAC_BTCTRL_STEPSEL_SRC_Val 0x1u /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */
|
---|
| 890 | #define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos)
|
---|
| 891 | #define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos)
|
---|
| 892 | #define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */
|
---|
| 893 | #define DMAC_BTCTRL_STEPSIZE_Msk (0x7u << DMAC_BTCTRL_STEPSIZE_Pos)
|
---|
| 894 | #define DMAC_BTCTRL_STEPSIZE(value) ((DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)))
|
---|
| 895 | #define DMAC_BTCTRL_STEPSIZE_X1_Val 0x0u /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 1 */
|
---|
| 896 | #define DMAC_BTCTRL_STEPSIZE_X2_Val 0x1u /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 2 */
|
---|
| 897 | #define DMAC_BTCTRL_STEPSIZE_X4_Val 0x2u /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 4 */
|
---|
| 898 | #define DMAC_BTCTRL_STEPSIZE_X8_Val 0x3u /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 8 */
|
---|
| 899 | #define DMAC_BTCTRL_STEPSIZE_X16_Val 0x4u /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 16 */
|
---|
| 900 | #define DMAC_BTCTRL_STEPSIZE_X32_Val 0x5u /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 32 */
|
---|
| 901 | #define DMAC_BTCTRL_STEPSIZE_X64_Val 0x6u /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 64 */
|
---|
| 902 | #define DMAC_BTCTRL_STEPSIZE_X128_Val 0x7u /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 128 */
|
---|
| 903 | #define DMAC_BTCTRL_STEPSIZE_X1 (DMAC_BTCTRL_STEPSIZE_X1_Val << DMAC_BTCTRL_STEPSIZE_Pos)
|
---|
| 904 | #define DMAC_BTCTRL_STEPSIZE_X2 (DMAC_BTCTRL_STEPSIZE_X2_Val << DMAC_BTCTRL_STEPSIZE_Pos)
|
---|
| 905 | #define DMAC_BTCTRL_STEPSIZE_X4 (DMAC_BTCTRL_STEPSIZE_X4_Val << DMAC_BTCTRL_STEPSIZE_Pos)
|
---|
| 906 | #define DMAC_BTCTRL_STEPSIZE_X8 (DMAC_BTCTRL_STEPSIZE_X8_Val << DMAC_BTCTRL_STEPSIZE_Pos)
|
---|
| 907 | #define DMAC_BTCTRL_STEPSIZE_X16 (DMAC_BTCTRL_STEPSIZE_X16_Val << DMAC_BTCTRL_STEPSIZE_Pos)
|
---|
| 908 | #define DMAC_BTCTRL_STEPSIZE_X32 (DMAC_BTCTRL_STEPSIZE_X32_Val << DMAC_BTCTRL_STEPSIZE_Pos)
|
---|
| 909 | #define DMAC_BTCTRL_STEPSIZE_X64 (DMAC_BTCTRL_STEPSIZE_X64_Val << DMAC_BTCTRL_STEPSIZE_Pos)
|
---|
| 910 | #define DMAC_BTCTRL_STEPSIZE_X128 (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos)
|
---|
| 911 | #define DMAC_BTCTRL_MASK 0xFF1Fu /**< \brief (DMAC_BTCTRL) MASK Register */
|
---|
| 912 |
|
---|
| 913 | /* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
|
---|
| 914 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 915 | typedef union {
|
---|
| 916 | struct {
|
---|
| 917 | uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */
|
---|
| 918 | } bit; /*!< Structure used for bit access */
|
---|
| 919 | uint16_t reg; /*!< Type used for register access */
|
---|
| 920 | } DMAC_BTCNT_Type;
|
---|
| 921 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 922 |
|
---|
| 923 | #define DMAC_BTCNT_OFFSET 0x02 /**< \brief (DMAC_BTCNT offset) Block Transfer Count */
|
---|
| 924 |
|
---|
| 925 | #define DMAC_BTCNT_BTCNT_Pos 0 /**< \brief (DMAC_BTCNT) Block Transfer Count */
|
---|
| 926 | #define DMAC_BTCNT_BTCNT_Msk (0xFFFFu << DMAC_BTCNT_BTCNT_Pos)
|
---|
| 927 | #define DMAC_BTCNT_BTCNT(value) ((DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos)))
|
---|
| 928 | #define DMAC_BTCNT_MASK 0xFFFFu /**< \brief (DMAC_BTCNT) MASK Register */
|
---|
| 929 |
|
---|
| 930 | /* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Transfer Source Address -------- */
|
---|
| 931 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 932 | typedef union {
|
---|
| 933 | struct {
|
---|
| 934 | uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */
|
---|
| 935 | } bit; /*!< Structure used for bit access */
|
---|
| 936 | uint32_t reg; /*!< Type used for register access */
|
---|
| 937 | } DMAC_SRCADDR_Type;
|
---|
| 938 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 939 |
|
---|
| 940 | #define DMAC_SRCADDR_OFFSET 0x04 /**< \brief (DMAC_SRCADDR offset) Transfer Source Address */
|
---|
| 941 |
|
---|
| 942 | #define DMAC_SRCADDR_SRCADDR_Pos 0 /**< \brief (DMAC_SRCADDR) Transfer Source Address */
|
---|
| 943 | #define DMAC_SRCADDR_SRCADDR_Msk (0xFFFFFFFFu << DMAC_SRCADDR_SRCADDR_Pos)
|
---|
| 944 | #define DMAC_SRCADDR_SRCADDR(value) ((DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos)))
|
---|
| 945 | #define DMAC_SRCADDR_MASK 0xFFFFFFFFu /**< \brief (DMAC_SRCADDR) MASK Register */
|
---|
| 946 |
|
---|
| 947 | /* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Transfer Destination Address -------- */
|
---|
| 948 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 949 | typedef union {
|
---|
| 950 | struct {
|
---|
| 951 | uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */
|
---|
| 952 | } bit; /*!< Structure used for bit access */
|
---|
| 953 | uint32_t reg; /*!< Type used for register access */
|
---|
| 954 | } DMAC_DSTADDR_Type;
|
---|
| 955 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
---|
| 956 |
|
---|
| 957 | #define DMAC_DSTADDR_OFFSET 0x08 /**< \brief (DMAC_DSTADDR offset) Transfer Destination Address */
|
---|
| 958 |
|
---|
| 959 | #define DMAC_DSTADDR_DSTADDR_Pos 0 /**< \brief (DMAC_DSTADDR) Transfer Destination Address */
|
---|
| 960 | #define DMAC_DSTADDR_DSTADDR_Msk (0xFFFFFFFFu << DMAC_DSTADDR_DSTADDR_Pos)
|
---|
| 961 | #define DMAC_DSTADDR_DSTADDR(value) ((DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos)))
|
---|
| 962 | #define DMAC_DSTADDR_MASK 0xFFFFFFFFu /**< \brief (DMAC_DSTADDR) MASK Register */
|
---|
| 963 |
|
---|
| 964 | /* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
|
---|
| 965 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
---|
| 966 | typedef union {
|
---|
| 967 | struct {
|
---|
| 968 | uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */
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| 969 | } bit; /*!< Structure used for bit access */
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| 970 | uint32_t reg; /*!< Type used for register access */
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| 971 | } DMAC_DESCADDR_Type;
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| 972 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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| 973 |
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| 974 | #define DMAC_DESCADDR_OFFSET 0x0C /**< \brief (DMAC_DESCADDR offset) Next Descriptor Address */
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| 975 |
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| 976 | #define DMAC_DESCADDR_DESCADDR_Pos 0 /**< \brief (DMAC_DESCADDR) Next Descriptor Address */
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| 977 | #define DMAC_DESCADDR_DESCADDR_Msk (0xFFFFFFFFu << DMAC_DESCADDR_DESCADDR_Pos)
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| 978 | #define DMAC_DESCADDR_DESCADDR(value) ((DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos)))
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| 979 | #define DMAC_DESCADDR_MASK 0xFFFFFFFFu /**< \brief (DMAC_DESCADDR) MASK Register */
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| 980 |
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| 981 | /** \brief DMAC APB hardware registers */
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| 982 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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| 983 | typedef struct {
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| 984 | __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */
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| 985 | __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */
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| 986 | __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
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| 987 | __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
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| 988 | __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */
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| 989 | __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */
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| 990 | RoReg8 Reserved1[0x2];
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| 991 | __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
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| 992 | __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
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| 993 | RoReg8 Reserved2[0x8];
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| 994 | __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
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| 995 | RoReg8 Reserved3[0x2];
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| 996 | __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */
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| 997 | __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */
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| 998 | __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */
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| 999 | __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */
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| 1000 | __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
|
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| 1001 | __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
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| 1002 | RoReg8 Reserved4[0x3];
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| 1003 | __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */
|
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| 1004 | __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */
|
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| 1005 | RoReg8 Reserved5[0x3];
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| 1006 | __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */
|
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| 1007 | RoReg8 Reserved6[0x4];
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| 1008 | __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */
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| 1009 | __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */
|
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| 1010 | __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */
|
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| 1011 | __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */
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| 1012 | } Dmac;
|
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| 1013 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
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| 1014 |
|
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| 1015 | /** \brief DMAC Descriptor SRAM registers */
|
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| 1016 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
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| 1017 | typedef struct {
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| 1018 | __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
|
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| 1019 | __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
|
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| 1020 | __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Transfer Source Address */
|
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| 1021 | __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Transfer Destination Address */
|
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| 1022 | __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
|
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| 1023 | } DmacDescriptor
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| 1024 | #ifdef __GNUC__
|
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| 1025 | __attribute__ ((aligned (8)))
|
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| 1026 | #endif
|
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| 1027 | ;
|
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| 1028 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
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| 1029 | #define SECTION_DMAC_DESCRIPTOR
|
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| 1030 |
|
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| 1031 | /*@}*/
|
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| 1032 |
|
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| 1033 | #endif /* _SAMD21_DMAC_COMPONENT_ */
|
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