source: rtos_arduino/trunk/arduino_lib/hardware/tools/CMSIS/CMSIS/Include/core_sc300.h@ 136

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1/**************************************************************************//**
2 * @file core_sc300.h
3 * @brief CMSIS SC300 Core Peripheral Access Layer Header File
4 * @version V3.30
5 * @date 24. February 2014
6 *
7 * @note
8 *
9 ******************************************************************************/
10/* Copyright (c) 2009 - 2014 ARM LIMITED
11
12 All rights reserved.
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 - Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 - Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 - Neither the name of ARM nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23 *
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ---------------------------------------------------------------------------*/
36
37
38#if defined ( __ICCARM__ )
39 #pragma system_include /* treat file as system include file for MISRA check */
40#endif
41
42#ifndef __CORE_SC300_H_GENERIC
43#define __CORE_SC300_H_GENERIC
44
45#ifdef __cplusplus
46 extern "C" {
47#endif
48
49/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
50 CMSIS violates the following MISRA-C:2004 rules:
51
52 \li Required Rule 8.5, object/function definition in header file.<br>
53 Function definitions in header files are used to allow 'inlining'.
54
55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
56 Unions are used for effective representation of core registers.
57
58 \li Advisory Rule 19.7, Function-like macro defined.<br>
59 Function-like macros are used to allow more efficient code.
60 */
61
62
63/*******************************************************************************
64 * CMSIS definitions
65 ******************************************************************************/
66/** \ingroup SC3000
67 @{
68 */
69
70/* CMSIS SC300 definitions */
71#define __SC300_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
72#define __SC300_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
73#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
74 __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
75
76#define __CORTEX_SC (300) /*!< Cortex secure core */
77
78
79#if defined ( __CC_ARM )
80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
82 #define __STATIC_INLINE static __inline
83
84#elif defined ( __GNUC__ )
85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
87 #define __STATIC_INLINE static inline
88
89#elif defined ( __ICCARM__ )
90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
92 #define __STATIC_INLINE static inline
93
94#elif defined ( __TMS470__ )
95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
96 #define __STATIC_INLINE static inline
97
98#elif defined ( __TASKING__ )
99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
101 #define __STATIC_INLINE static inline
102
103#elif defined ( __CSMC__ ) /* Cosmic */
104 #define __packed
105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
107 #define __STATIC_INLINE static inline
108
109#endif
110
111/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
112*/
113#define __FPU_USED 0
114
115#if defined ( __CC_ARM )
116 #if defined __TARGET_FPU_VFP
117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
118 #endif
119
120#elif defined ( __GNUC__ )
121 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
122 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
123 #endif
124
125#elif defined ( __ICCARM__ )
126 #if defined __ARMVFP__
127 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
128 #endif
129
130#elif defined ( __TMS470__ )
131 #if defined __TI__VFP_SUPPORT____
132 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
133 #endif
134
135#elif defined ( __TASKING__ )
136 #if defined __FPU_VFP__
137 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
138 #endif
139
140#elif defined ( __CSMC__ ) /* Cosmic */
141 #if ( __CSMC__ & 0x400) // FPU present for parser
142 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
143 #endif
144#endif
145
146#include <stdint.h> /* standard types definitions */
147#include <core_cmInstr.h> /* Core Instruction Access */
148#include <core_cmFunc.h> /* Core Function Access */
149
150#endif /* __CORE_SC300_H_GENERIC */
151
152#ifndef __CMSIS_GENERIC
153
154#ifndef __CORE_SC300_H_DEPENDANT
155#define __CORE_SC300_H_DEPENDANT
156
157/* check device defines and use defaults */
158#if defined __CHECK_DEVICE_DEFINES
159 #ifndef __SC300_REV
160 #define __SC300_REV 0x0000
161 #warning "__SC300_REV not defined in device header file; using default!"
162 #endif
163
164 #ifndef __MPU_PRESENT
165 #define __MPU_PRESENT 0
166 #warning "__MPU_PRESENT not defined in device header file; using default!"
167 #endif
168
169 #ifndef __NVIC_PRIO_BITS
170 #define __NVIC_PRIO_BITS 4
171 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
172 #endif
173
174 #ifndef __Vendor_SysTickConfig
175 #define __Vendor_SysTickConfig 0
176 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
177 #endif
178#endif
179
180/* IO definitions (access restrictions to peripheral registers) */
181/**
182 \defgroup CMSIS_glob_defs CMSIS Global Defines
183
184 <strong>IO Type Qualifiers</strong> are used
185 \li to specify the access to peripheral variables.
186 \li for automatic generation of peripheral register debug information.
187*/
188#ifdef __cplusplus
189 #define __I volatile /*!< Defines 'read only' permissions */
190#else
191 #define __I volatile const /*!< Defines 'read only' permissions */
192#endif
193#define __O volatile /*!< Defines 'write only' permissions */
194#define __IO volatile /*!< Defines 'read / write' permissions */
195
196/*@} end of group SC300 */
197
198
199
200/*******************************************************************************
201 * Register Abstraction
202 Core Register contain:
203 - Core Register
204 - Core NVIC Register
205 - Core SCB Register
206 - Core SysTick Register
207 - Core Debug Register
208 - Core MPU Register
209 ******************************************************************************/
210/** \defgroup CMSIS_core_register Defines and Type Definitions
211 \brief Type definitions and defines for Cortex-M processor based devices.
212*/
213
214/** \ingroup CMSIS_core_register
215 \defgroup CMSIS_CORE Status and Control Registers
216 \brief Core Register type definitions.
217 @{
218 */
219
220/** \brief Union type to access the Application Program Status Register (APSR).
221 */
222typedef union
223{
224 struct
225 {
226#if (__CORTEX_M != 0x04)
227 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
228#else
229 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
230 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
231 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
232#endif
233 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
234 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
235 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
236 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
237 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
238 } b; /*!< Structure used for bit access */
239 uint32_t w; /*!< Type used for word access */
240} APSR_Type;
241
242
243/** \brief Union type to access the Interrupt Program Status Register (IPSR).
244 */
245typedef union
246{
247 struct
248 {
249 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
250 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
251 } b; /*!< Structure used for bit access */
252 uint32_t w; /*!< Type used for word access */
253} IPSR_Type;
254
255
256/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
257 */
258typedef union
259{
260 struct
261 {
262 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
263#if (__CORTEX_M != 0x04)
264 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
265#else
266 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
267 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
268 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
269#endif
270 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
271 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
272 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
273 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
274 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
275 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
276 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
277 } b; /*!< Structure used for bit access */
278 uint32_t w; /*!< Type used for word access */
279} xPSR_Type;
280
281
282/** \brief Union type to access the Control Registers (CONTROL).
283 */
284typedef union
285{
286 struct
287 {
288 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
289 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
290 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
291 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
292 } b; /*!< Structure used for bit access */
293 uint32_t w; /*!< Type used for word access */
294} CONTROL_Type;
295
296/*@} end of group CMSIS_CORE */
297
298
299/** \ingroup CMSIS_core_register
300 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
301 \brief Type definitions for the NVIC Registers
302 @{
303 */
304
305/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
306 */
307typedef struct
308{
309 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
310 uint32_t RESERVED0[24];
311 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
312 uint32_t RSERVED1[24];
313 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
314 uint32_t RESERVED2[24];
315 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
316 uint32_t RESERVED3[24];
317 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
318 uint32_t RESERVED4[56];
319 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
320 uint32_t RESERVED5[644];
321 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
322} NVIC_Type;
323
324/* Software Triggered Interrupt Register Definitions */
325#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
326#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
327
328/*@} end of group CMSIS_NVIC */
329
330
331/** \ingroup CMSIS_core_register
332 \defgroup CMSIS_SCB System Control Block (SCB)
333 \brief Type definitions for the System Control Block Registers
334 @{
335 */
336
337/** \brief Structure type to access the System Control Block (SCB).
338 */
339typedef struct
340{
341 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
342 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
343 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
344 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
345 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
346 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
347 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
348 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
349 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
350 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
351 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
352 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
353 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
354 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
355 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
356 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
357 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
358 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
359 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
360 uint32_t RESERVED0[5];
361 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
362} SCB_Type;
363
364/* SCB CPUID Register Definitions */
365#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
366#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
367
368#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
369#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
370
371#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
372#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
373
374#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
375#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
376
377#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
378#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
379
380/* SCB Interrupt Control State Register Definitions */
381#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
382#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
383
384#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
385#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
386
387#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
388#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
389
390#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
391#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
392
393#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
394#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
395
396#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
397#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
398
399#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
400#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
401
402#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
403#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
404
405#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
406#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
407
408#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
409#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
410
411/* SCB Vector Table Offset Register Definitions */
412#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
413#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
414
415#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
416#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
417
418/* SCB Application Interrupt and Reset Control Register Definitions */
419#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
420#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
421
422#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
423#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
424
425#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
426#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
427
428#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
429#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
430
431#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
432#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
433
434#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
435#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
436
437#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
438#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
439
440/* SCB System Control Register Definitions */
441#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
442#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
443
444#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
445#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
446
447#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
448#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
449
450/* SCB Configuration Control Register Definitions */
451#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
452#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
453
454#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
455#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
456
457#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
458#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
459
460#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
461#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
462
463#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
464#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
465
466#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
467#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
468
469/* SCB System Handler Control and State Register Definitions */
470#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
471#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
472
473#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
474#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
475
476#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
477#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
478
479#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
480#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
481
482#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
483#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
484
485#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
486#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
487
488#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
489#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
490
491#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
492#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
493
494#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
495#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
496
497#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
498#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
499
500#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
501#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
502
503#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
504#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
505
506#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
507#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
508
509#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
510#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
511
512/* SCB Configurable Fault Status Registers Definitions */
513#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
514#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
515
516#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
517#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
518
519#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
520#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
521
522/* SCB Hard Fault Status Registers Definitions */
523#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
524#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
525
526#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
527#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
528
529#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
530#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
531
532/* SCB Debug Fault Status Register Definitions */
533#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
534#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
535
536#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
537#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
538
539#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
540#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
541
542#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
543#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
544
545#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
546#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
547
548/*@} end of group CMSIS_SCB */
549
550
551/** \ingroup CMSIS_core_register
552 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
553 \brief Type definitions for the System Control and ID Register not in the SCB
554 @{
555 */
556
557/** \brief Structure type to access the System Control and ID Register not in the SCB.
558 */
559typedef struct
560{
561 uint32_t RESERVED0[1];
562 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
563 uint32_t RESERVED1[1];
564} SCnSCB_Type;
565
566/* Interrupt Controller Type Register Definitions */
567#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
568#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
569
570/*@} end of group CMSIS_SCnotSCB */
571
572
573/** \ingroup CMSIS_core_register
574 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
575 \brief Type definitions for the System Timer Registers.
576 @{
577 */
578
579/** \brief Structure type to access the System Timer (SysTick).
580 */
581typedef struct
582{
583 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
584 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
585 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
586 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
587} SysTick_Type;
588
589/* SysTick Control / Status Register Definitions */
590#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
591#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
592
593#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
594#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
595
596#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
597#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
598
599#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
600#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
601
602/* SysTick Reload Register Definitions */
603#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
604#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
605
606/* SysTick Current Register Definitions */
607#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
608#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
609
610/* SysTick Calibration Register Definitions */
611#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
612#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
613
614#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
615#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
616
617#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
618#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
619
620/*@} end of group CMSIS_SysTick */
621
622
623/** \ingroup CMSIS_core_register
624 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
625 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
626 @{
627 */
628
629/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
630 */
631typedef struct
632{
633 __O union
634 {
635 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
636 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
637 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
638 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
639 uint32_t RESERVED0[864];
640 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
641 uint32_t RESERVED1[15];
642 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
643 uint32_t RESERVED2[15];
644 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
645 uint32_t RESERVED3[29];
646 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
647 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
648 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
649 uint32_t RESERVED4[43];
650 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
651 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
652 uint32_t RESERVED5[6];
653 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
654 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
655 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
656 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
657 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
658 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
659 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
660 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
661 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
662 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
663 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
664 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
665} ITM_Type;
666
667/* ITM Trace Privilege Register Definitions */
668#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
669#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
670
671/* ITM Trace Control Register Definitions */
672#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
673#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
674
675#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
676#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
677
678#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
679#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
680
681#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
682#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
683
684#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
685#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
686
687#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
688#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
689
690#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
691#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
692
693#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
694#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
695
696#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
697#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
698
699/* ITM Integration Write Register Definitions */
700#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
701#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
702
703/* ITM Integration Read Register Definitions */
704#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
705#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
706
707/* ITM Integration Mode Control Register Definitions */
708#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
709#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
710
711/* ITM Lock Status Register Definitions */
712#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
713#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
714
715#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
716#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
717
718#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
719#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
720
721/*@}*/ /* end of group CMSIS_ITM */
722
723
724/** \ingroup CMSIS_core_register
725 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
726 \brief Type definitions for the Data Watchpoint and Trace (DWT)
727 @{
728 */
729
730/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
731 */
732typedef struct
733{
734 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
735 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
736 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
737 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
738 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
739 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
740 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
741 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
742 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
743 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
744 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
745 uint32_t RESERVED0[1];
746 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
747 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
748 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
749 uint32_t RESERVED1[1];
750 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
751 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
752 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
753 uint32_t RESERVED2[1];
754 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
755 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
756 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
757} DWT_Type;
758
759/* DWT Control Register Definitions */
760#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
761#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
762
763#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
764#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
765
766#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
767#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
768
769#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
770#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
771
772#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
773#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
774
775#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
776#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
777
778#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
779#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
780
781#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
782#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
783
784#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
785#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
786
787#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
788#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
789
790#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
791#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
792
793#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
794#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
795
796#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
797#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
798
799#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
800#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
801
802#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
803#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
804
805#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
806#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
807
808#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
809#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
810
811#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
812#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
813
814/* DWT CPI Count Register Definitions */
815#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
816#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
817
818/* DWT Exception Overhead Count Register Definitions */
819#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
820#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
821
822/* DWT Sleep Count Register Definitions */
823#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
824#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
825
826/* DWT LSU Count Register Definitions */
827#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
828#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
829
830/* DWT Folded-instruction Count Register Definitions */
831#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
832#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
833
834/* DWT Comparator Mask Register Definitions */
835#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
836#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
837
838/* DWT Comparator Function Register Definitions */
839#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
840#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
841
842#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
843#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
844
845#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
846#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
847
848#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
849#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
850
851#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
852#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
853
854#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
855#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
856
857#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
858#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
859
860#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
861#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
862
863#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
864#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
865
866/*@}*/ /* end of group CMSIS_DWT */
867
868
869/** \ingroup CMSIS_core_register
870 \defgroup CMSIS_TPI Trace Port Interface (TPI)
871 \brief Type definitions for the Trace Port Interface (TPI)
872 @{
873 */
874
875/** \brief Structure type to access the Trace Port Interface Register (TPI).
876 */
877typedef struct
878{
879 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
880 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
881 uint32_t RESERVED0[2];
882 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
883 uint32_t RESERVED1[55];
884 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
885 uint32_t RESERVED2[131];
886 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
887 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
888 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
889 uint32_t RESERVED3[759];
890 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
891 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
892 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
893 uint32_t RESERVED4[1];
894 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
895 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
896 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
897 uint32_t RESERVED5[39];
898 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
899 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
900 uint32_t RESERVED7[8];
901 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
902 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
903} TPI_Type;
904
905/* TPI Asynchronous Clock Prescaler Register Definitions */
906#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
907#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
908
909/* TPI Selected Pin Protocol Register Definitions */
910#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
911#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
912
913/* TPI Formatter and Flush Status Register Definitions */
914#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
915#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
916
917#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
918#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
919
920#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
921#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
922
923#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
924#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
925
926/* TPI Formatter and Flush Control Register Definitions */
927#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
928#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
929
930#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
931#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
932
933/* TPI TRIGGER Register Definitions */
934#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
935#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
936
937/* TPI Integration ETM Data Register Definitions (FIFO0) */
938#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
939#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
940
941#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
942#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
943
944#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
945#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
946
947#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
948#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
949
950#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
951#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
952
953#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
954#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
955
956#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
957#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
958
959/* TPI ITATBCTR2 Register Definitions */
960#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
961#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
962
963/* TPI Integration ITM Data Register Definitions (FIFO1) */
964#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
965#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
966
967#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
968#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
969
970#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
971#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
972
973#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
974#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
975
976#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
977#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
978
979#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
980#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
981
982#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
983#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
984
985/* TPI ITATBCTR0 Register Definitions */
986#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
987#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
988
989/* TPI Integration Mode Control Register Definitions */
990#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
991#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
992
993/* TPI DEVID Register Definitions */
994#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
995#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
996
997#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
998#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
999
1000#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
1001#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1002
1003#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
1004#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
1005
1006#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
1007#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1008
1009#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
1010#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
1011
1012/* TPI DEVTYPE Register Definitions */
1013#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
1014#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
1015
1016#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
1017#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1018
1019/*@}*/ /* end of group CMSIS_TPI */
1020
1021
1022#if (__MPU_PRESENT == 1)
1023/** \ingroup CMSIS_core_register
1024 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1025 \brief Type definitions for the Memory Protection Unit (MPU)
1026 @{
1027 */
1028
1029/** \brief Structure type to access the Memory Protection Unit (MPU).
1030 */
1031typedef struct
1032{
1033 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1034 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1035 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1036 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1037 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1038 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1039 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1040 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1041 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1042 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1043 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1044} MPU_Type;
1045
1046/* MPU Type Register */
1047#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
1048#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1049
1050#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
1051#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1052
1053#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
1054#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
1055
1056/* MPU Control Register */
1057#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
1058#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1059
1060#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
1061#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1062
1063#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
1064#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
1065
1066/* MPU Region Number Register */
1067#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
1068#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
1069
1070/* MPU Region Base Address Register */
1071#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
1072#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1073
1074#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
1075#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1076
1077#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
1078#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
1079
1080/* MPU Region Attribute and Size Register */
1081#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
1082#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1083
1084#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
1085#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1086
1087#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
1088#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1089
1090#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
1091#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1092
1093#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
1094#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1095
1096#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
1097#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1098
1099#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
1100#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1101
1102#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
1103#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1104
1105#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
1106#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1107
1108#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
1109#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
1110
1111/*@} end of group CMSIS_MPU */
1112#endif
1113
1114
1115/** \ingroup CMSIS_core_register
1116 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1117 \brief Type definitions for the Core Debug Registers
1118 @{
1119 */
1120
1121/** \brief Structure type to access the Core Debug Register (CoreDebug).
1122 */
1123typedef struct
1124{
1125 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1126 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1127 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1128 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1129} CoreDebug_Type;
1130
1131/* Debug Halting Control and Status Register */
1132#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
1133#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1134
1135#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
1136#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1137
1138#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1139#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1140
1141#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
1142#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1143
1144#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
1145#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1146
1147#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
1148#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1149
1150#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
1151#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1152
1153#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1154#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1155
1156#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
1157#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1158
1159#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
1160#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1161
1162#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
1163#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1164
1165#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1166#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1167
1168/* Debug Core Register Selector Register */
1169#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
1170#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1171
1172#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
1173#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
1174
1175/* Debug Exception and Monitor Control Register */
1176#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
1177#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1178
1179#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
1180#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1181
1182#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
1183#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1184
1185#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
1186#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1187
1188#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
1189#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1190
1191#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
1192#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1193
1194#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
1195#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1196
1197#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
1198#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1199
1200#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
1201#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1202
1203#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
1204#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1205
1206#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1207#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1208
1209#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
1210#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1211
1212#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
1213#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1214
1215/*@} end of group CMSIS_CoreDebug */
1216
1217
1218/** \ingroup CMSIS_core_register
1219 \defgroup CMSIS_core_base Core Definitions
1220 \brief Definitions for base addresses, unions, and structures.
1221 @{
1222 */
1223
1224/* Memory mapping of Cortex-M3 Hardware */
1225#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1226#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1227#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1228#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1229#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1230#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1231#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1232#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1233
1234#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1235#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1236#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1237#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1238#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1239#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1240#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1241#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1242
1243#if (__MPU_PRESENT == 1)
1244 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1245 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1246#endif
1247
1248/*@} */
1249
1250
1251
1252/*******************************************************************************
1253 * Hardware Abstraction Layer
1254 Core Function Interface contains:
1255 - Core NVIC Functions
1256 - Core SysTick Functions
1257 - Core Debug Functions
1258 - Core Register Access Functions
1259 ******************************************************************************/
1260/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1261*/
1262
1263
1264
1265/* ########################## NVIC functions #################################### */
1266/** \ingroup CMSIS_Core_FunctionInterface
1267 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1268 \brief Functions that manage interrupts and exceptions via the NVIC.
1269 @{
1270 */
1271
1272/** \brief Set Priority Grouping
1273
1274 The function sets the priority grouping field using the required unlock sequence.
1275 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1276 Only values from 0..7 are used.
1277 In case of a conflict between priority grouping and available
1278 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1279
1280 \param [in] PriorityGroup Priority grouping field.
1281 */
1282__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1283{
1284 uint32_t reg_value;
1285 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
1286
1287 reg_value = SCB->AIRCR; /* read old register configuration */
1288 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
1289 reg_value = (reg_value |
1290 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1291 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
1292 SCB->AIRCR = reg_value;
1293}
1294
1295
1296/** \brief Get Priority Grouping
1297
1298 The function reads the priority grouping field from the NVIC Interrupt Controller.
1299
1300 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1301 */
1302__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1303{
1304 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
1305}
1306
1307
1308/** \brief Enable External Interrupt
1309
1310 The function enables a device-specific interrupt in the NVIC interrupt controller.
1311
1312 \param [in] IRQn External interrupt number. Value cannot be negative.
1313 */
1314__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1315{
1316 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
1317}
1318
1319
1320/** \brief Disable External Interrupt
1321
1322 The function disables a device-specific interrupt in the NVIC interrupt controller.
1323
1324 \param [in] IRQn External interrupt number. Value cannot be negative.
1325 */
1326__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1327{
1328 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
1329}
1330
1331
1332/** \brief Get Pending Interrupt
1333
1334 The function reads the pending register in the NVIC and returns the pending bit
1335 for the specified interrupt.
1336
1337 \param [in] IRQn Interrupt number.
1338
1339 \return 0 Interrupt status is not pending.
1340 \return 1 Interrupt status is pending.
1341 */
1342__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1343{
1344 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
1345}
1346
1347
1348/** \brief Set Pending Interrupt
1349
1350 The function sets the pending bit of an external interrupt.
1351
1352 \param [in] IRQn Interrupt number. Value cannot be negative.
1353 */
1354__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1355{
1356 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
1357}
1358
1359
1360/** \brief Clear Pending Interrupt
1361
1362 The function clears the pending bit of an external interrupt.
1363
1364 \param [in] IRQn External interrupt number. Value cannot be negative.
1365 */
1366__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1367{
1368 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
1369}
1370
1371
1372/** \brief Get Active Interrupt
1373
1374 The function reads the active register in NVIC and returns the active bit.
1375
1376 \param [in] IRQn Interrupt number.
1377
1378 \return 0 Interrupt status is not active.
1379 \return 1 Interrupt status is active.
1380 */
1381__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1382{
1383 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
1384}
1385
1386
1387/** \brief Set Interrupt Priority
1388
1389 The function sets the priority of an interrupt.
1390
1391 \note The priority cannot be set for every core interrupt.
1392
1393 \param [in] IRQn Interrupt number.
1394 \param [in] priority Priority to set.
1395 */
1396__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1397{
1398 if(IRQn < 0) {
1399 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
1400 else {
1401 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
1402}
1403
1404
1405/** \brief Get Interrupt Priority
1406
1407 The function reads the priority of an interrupt. The interrupt
1408 number can be positive to specify an external (device specific)
1409 interrupt, or negative to specify an internal (core) interrupt.
1410
1411
1412 \param [in] IRQn Interrupt number.
1413 \return Interrupt Priority. Value is aligned automatically to the implemented
1414 priority bits of the microcontroller.
1415 */
1416__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1417{
1418
1419 if(IRQn < 0) {
1420 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
1421 else {
1422 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
1423}
1424
1425
1426/** \brief Encode Priority
1427
1428 The function encodes the priority for an interrupt with the given priority group,
1429 preemptive priority value, and subpriority value.
1430 In case of a conflict between priority grouping and available
1431 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
1432
1433 \param [in] PriorityGroup Used priority group.
1434 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1435 \param [in] SubPriority Subpriority value (starting from 0).
1436 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1437 */
1438__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1439{
1440 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1441 uint32_t PreemptPriorityBits;
1442 uint32_t SubPriorityBits;
1443
1444 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1445 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1446
1447 return (
1448 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
1449 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
1450 );
1451}
1452
1453
1454/** \brief Decode Priority
1455
1456 The function decodes an interrupt priority value with a given priority group to
1457 preemptive priority value and subpriority value.
1458 In case of a conflict between priority grouping and available
1459 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
1460
1461 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1462 \param [in] PriorityGroup Used priority group.
1463 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1464 \param [out] pSubPriority Subpriority value (starting from 0).
1465 */
1466__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1467{
1468 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1469 uint32_t PreemptPriorityBits;
1470 uint32_t SubPriorityBits;
1471
1472 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1473 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1474
1475 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
1476 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
1477}
1478
1479
1480/** \brief System Reset
1481
1482 The function initiates a system reset request to reset the MCU.
1483 */
1484__STATIC_INLINE void NVIC_SystemReset(void)
1485{
1486 __DSB(); /* Ensure all outstanding memory accesses included
1487 buffered write are completed before reset */
1488 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1489 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1490 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
1491 __DSB(); /* Ensure completion of memory access */
1492 while(1); /* wait until reset */
1493}
1494
1495/*@} end of CMSIS_Core_NVICFunctions */
1496
1497
1498
1499/* ################################## SysTick function ############################################ */
1500/** \ingroup CMSIS_Core_FunctionInterface
1501 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1502 \brief Functions that configure the System.
1503 @{
1504 */
1505
1506#if (__Vendor_SysTickConfig == 0)
1507
1508/** \brief System Tick Configuration
1509
1510 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
1511 Counter is in free running mode to generate periodic interrupts.
1512
1513 \param [in] ticks Number of ticks between two interrupts.
1514
1515 \return 0 Function succeeded.
1516 \return 1 Function failed.
1517
1518 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1519 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1520 must contain a vendor-specific implementation of this function.
1521
1522 */
1523__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1524{
1525 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
1526
1527 SysTick->LOAD = ticks - 1; /* set reload register */
1528 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
1529 SysTick->VAL = 0; /* Load the SysTick Counter Value */
1530 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1531 SysTick_CTRL_TICKINT_Msk |
1532 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1533 return (0); /* Function successful */
1534}
1535
1536#endif
1537
1538/*@} end of CMSIS_Core_SysTickFunctions */
1539
1540
1541
1542/* ##################################### Debug In/Output function ########################################### */
1543/** \ingroup CMSIS_Core_FunctionInterface
1544 \defgroup CMSIS_core_DebugFunctions ITM Functions
1545 \brief Functions that access the ITM debug interface.
1546 @{
1547 */
1548
1549extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
1550#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
1551
1552
1553/** \brief ITM Send Character
1554
1555 The function transmits a character via the ITM channel 0, and
1556 \li Just returns when no debugger is connected that has booked the output.
1557 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
1558
1559 \param [in] ch Character to transmit.
1560
1561 \returns Character to transmit.
1562 */
1563__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1564{
1565 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
1566 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
1567 {
1568 while (ITM->PORT[0].u32 == 0);
1569 ITM->PORT[0].u8 = (uint8_t) ch;
1570 }
1571 return (ch);
1572}
1573
1574
1575/** \brief ITM Receive Character
1576
1577 The function inputs a character via the external variable \ref ITM_RxBuffer.
1578
1579 \return Received character.
1580 \return -1 No character pending.
1581 */
1582__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
1583 int32_t ch = -1; /* no character available */
1584
1585 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
1586 ch = ITM_RxBuffer;
1587 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1588 }
1589
1590 return (ch);
1591}
1592
1593
1594/** \brief ITM Check Character
1595
1596 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
1597
1598 \return 0 No character available.
1599 \return 1 Character available.
1600 */
1601__STATIC_INLINE int32_t ITM_CheckChar (void) {
1602
1603 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
1604 return (0); /* no character available */
1605 } else {
1606 return (1); /* character available */
1607 }
1608}
1609
1610/*@} end of CMSIS_core_DebugFunctions */
1611
1612#endif /* __CORE_SC300_H_DEPENDANT */
1613
1614#ifdef __cplusplus
1615}
1616#endif
1617
1618#endif /* __CMSIS_GENERIC */
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