[128] | 1 | //////////////////////////////////////////////////////////////////////
|
---|
| 2 | //// ////
|
---|
| 3 | //// can_registers.v ////
|
---|
| 4 | //// ////
|
---|
| 5 | //// ////
|
---|
| 6 | //// This file is part of the CAN Protocol Controller ////
|
---|
| 7 | //// http://www.opencores.org/projects/can/ ////
|
---|
| 8 | //// ////
|
---|
| 9 | //// ////
|
---|
| 10 | //// Author(s): ////
|
---|
| 11 | //// Igor Mohor ////
|
---|
| 12 | //// igorm@opencores.org ////
|
---|
| 13 | //// ////
|
---|
| 14 | //// ////
|
---|
| 15 | //// All additional information is available in the README.txt ////
|
---|
| 16 | //// file. ////
|
---|
| 17 | //// ////
|
---|
| 18 | //////////////////////////////////////////////////////////////////////
|
---|
| 19 | //// ////
|
---|
| 20 | //// Copyright (C) 2002, 2003 Authors ////
|
---|
| 21 | //// ////
|
---|
| 22 | //// This source file may be used and distributed without ////
|
---|
| 23 | //// restriction provided that this copyright statement is not ////
|
---|
| 24 | //// removed from the file and that any derivative work contains ////
|
---|
| 25 | //// the original copyright notice and the associated disclaimer. ////
|
---|
| 26 | //// ////
|
---|
| 27 | //// This source file is free software; you can redistribute it ////
|
---|
| 28 | //// and/or modify it under the terms of the GNU Lesser General ////
|
---|
| 29 | //// Public License as published by the Free Software Foundation; ////
|
---|
| 30 | //// either version 2.1 of the License, or (at your option) any ////
|
---|
| 31 | //// later version. ////
|
---|
| 32 | //// ////
|
---|
| 33 | //// This source is distributed in the hope that it will be ////
|
---|
| 34 | //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
---|
| 35 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
---|
| 36 | //// PURPOSE. See the GNU Lesser General Public License for more ////
|
---|
| 37 | //// details. ////
|
---|
| 38 | //// ////
|
---|
| 39 | //// You should have received a copy of the GNU Lesser General ////
|
---|
| 40 | //// Public License along with this source; if not, download it ////
|
---|
| 41 | //// from http://www.opencores.org/lgpl.shtml ////
|
---|
| 42 | //// ////
|
---|
| 43 | //// The CAN protocol is developed by Robert Bosch GmbH and ////
|
---|
| 44 | //// protected by patents. Anybody who wants to implement this ////
|
---|
| 45 | //// CAN IP core on silicon has to obtain a CAN protocol license ////
|
---|
| 46 | //// from Bosch. ////
|
---|
| 47 | //// ////
|
---|
| 48 | //////////////////////////////////////////////////////////////////////
|
---|
| 49 | //
|
---|
| 50 | // CVS Revision History
|
---|
| 51 | //
|
---|
| 52 | // $Log: can_registers.v,v $
|
---|
| 53 | // Revision 1.35 2004/11/30 15:08:26 igorm
|
---|
| 54 | // irq is cleared after the release_buffer command. This bug was entered with
|
---|
| 55 | // changes for the edge triggered interrupts.
|
---|
| 56 | //
|
---|
| 57 | // Revision 1.34 2004/11/18 12:39:43 igorm
|
---|
| 58 | // Fixes for compatibility after the SW reset.
|
---|
| 59 | //
|
---|
| 60 | // Revision 1.33 2004/10/25 11:44:38 igorm
|
---|
| 61 | // Interrupt is always cleared for one clock after the irq register is read.
|
---|
| 62 | // This fixes problems when CPU is using IRQs that are edge triggered.
|
---|
| 63 | //
|
---|
| 64 | // Revision 1.32 2004/05/12 15:58:41 igorm
|
---|
| 65 | // Core improved to pass all tests with the Bosch VHDL Reference system.
|
---|
| 66 | //
|
---|
| 67 | // Revision 1.31 2003/09/25 18:55:49 mohor
|
---|
| 68 | // Synchronization changed, error counters fixed.
|
---|
| 69 | //
|
---|
| 70 | // Revision 1.30 2003/07/16 15:19:34 mohor
|
---|
| 71 | // Fixed according to the linter.
|
---|
| 72 | // Case statement for data_out joined.
|
---|
| 73 | //
|
---|
| 74 | // Revision 1.29 2003/07/10 01:59:04 tadejm
|
---|
| 75 | // Synchronization fixed. In some strange cases it didn't work according to
|
---|
| 76 | // the VHDL reference model.
|
---|
| 77 | //
|
---|
| 78 | // Revision 1.28 2003/07/07 11:21:37 mohor
|
---|
| 79 | // Little fixes (to fix warnings).
|
---|
| 80 | //
|
---|
| 81 | // Revision 1.27 2003/06/22 09:43:03 mohor
|
---|
| 82 | // synthesi full_case parallel_case fixed.
|
---|
| 83 | //
|
---|
| 84 | // Revision 1.26 2003/06/22 01:33:14 mohor
|
---|
| 85 | // clkout is clk/2 after the reset.
|
---|
| 86 | //
|
---|
| 87 | // Revision 1.25 2003/06/21 12:16:30 mohor
|
---|
| 88 | // paralel_case and full_case compiler directives added to case statements.
|
---|
| 89 | //
|
---|
| 90 | // Revision 1.24 2003/06/09 11:22:54 mohor
|
---|
| 91 | // data_out is already registered in the can_top.v file.
|
---|
| 92 | //
|
---|
| 93 | // Revision 1.23 2003/04/15 15:31:24 mohor
|
---|
| 94 | // Some features are supported in extended mode only (listen_only_mode...).
|
---|
| 95 | //
|
---|
| 96 | // Revision 1.22 2003/03/20 16:58:50 mohor
|
---|
| 97 | // unix.
|
---|
| 98 | //
|
---|
| 99 | // Revision 1.20 2003/03/11 16:31:05 mohor
|
---|
| 100 | // Mux used for clkout to avoid "gated clocks warning".
|
---|
| 101 | //
|
---|
| 102 | // Revision 1.19 2003/03/10 17:34:25 mohor
|
---|
| 103 | // Doubled declarations removed.
|
---|
| 104 | //
|
---|
| 105 | // Revision 1.18 2003/03/01 22:52:11 mohor
|
---|
| 106 | // Data is latched on read.
|
---|
| 107 | //
|
---|
| 108 | // Revision 1.17 2003/02/19 15:09:02 mohor
|
---|
| 109 | // Incomplete sensitivity list fixed.
|
---|
| 110 | //
|
---|
| 111 | // Revision 1.16 2003/02/19 14:44:03 mohor
|
---|
| 112 | // CAN core finished. Host interface added. Registers finished.
|
---|
| 113 | // Synchronization to the wishbone finished.
|
---|
| 114 | //
|
---|
| 115 | // Revision 1.15 2003/02/18 00:10:15 mohor
|
---|
| 116 | // Most of the registers added. Registers "arbitration lost capture", "error code
|
---|
| 117 | // capture" + few more still need to be added.
|
---|
| 118 | //
|
---|
| 119 | // Revision 1.14 2003/02/14 20:17:01 mohor
|
---|
| 120 | // Several registers added. Not finished, yet.
|
---|
| 121 | //
|
---|
| 122 | // Revision 1.13 2003/02/12 14:25:30 mohor
|
---|
| 123 | // abort_tx added.
|
---|
| 124 | //
|
---|
| 125 | // Revision 1.12 2003/02/11 00:56:06 mohor
|
---|
| 126 | // Wishbone interface added.
|
---|
| 127 | //
|
---|
| 128 | // Revision 1.11 2003/02/09 02:24:33 mohor
|
---|
| 129 | // Bosch license warning added. Error counters finished. Overload frames
|
---|
| 130 | // still need to be fixed.
|
---|
| 131 | //
|
---|
| 132 | // Revision 1.10 2003/01/31 01:13:38 mohor
|
---|
| 133 | // backup.
|
---|
| 134 | //
|
---|
| 135 | // Revision 1.9 2003/01/15 13:16:48 mohor
|
---|
| 136 | // When a frame with "remote request" is received, no data is stored
|
---|
| 137 | // to fifo, just the frame information (identifier, ...). Data length
|
---|
| 138 | // that is stored is the received data length and not the actual data
|
---|
| 139 | // length that is stored to fifo.
|
---|
| 140 | //
|
---|
| 141 | // Revision 1.8 2003/01/14 17:25:09 mohor
|
---|
| 142 | // Addresses corrected to decimal values (previously hex).
|
---|
| 143 | //
|
---|
| 144 | // Revision 1.7 2003/01/14 12:19:35 mohor
|
---|
| 145 | // rx_fifo is now working.
|
---|
| 146 | //
|
---|
| 147 | // Revision 1.6 2003/01/10 17:51:34 mohor
|
---|
| 148 | // Temporary version (backup).
|
---|
| 149 | //
|
---|
| 150 | // Revision 1.5 2003/01/09 14:46:58 mohor
|
---|
| 151 | // Temporary files (backup).
|
---|
| 152 | //
|
---|
| 153 | // Revision 1.4 2003/01/08 02:10:55 mohor
|
---|
| 154 | // Acceptance filter added.
|
---|
| 155 | //
|
---|
| 156 | // Revision 1.3 2002/12/27 00:12:52 mohor
|
---|
| 157 | // Header changed, testbench improved to send a frame (crc still missing).
|
---|
| 158 | //
|
---|
| 159 | // Revision 1.2 2002/12/26 16:00:34 mohor
|
---|
| 160 | // Testbench define file added. Clock divider register added.
|
---|
| 161 | //
|
---|
| 162 | // Revision 1.1.1.1 2002/12/20 16:39:21 mohor
|
---|
| 163 | // Initial
|
---|
| 164 | //
|
---|
| 165 | //
|
---|
| 166 | //
|
---|
| 167 |
|
---|
| 168 | // synopsys translate_off
|
---|
| 169 | `include "timescale.v"
|
---|
| 170 | // synopsys translate_on
|
---|
| 171 | `include "can_defines.v"
|
---|
| 172 |
|
---|
| 173 | module can_registers
|
---|
| 174 | (
|
---|
| 175 | clk,
|
---|
| 176 | rst,
|
---|
| 177 | cs,
|
---|
| 178 | we,
|
---|
| 179 | addr,
|
---|
| 180 | data_in,
|
---|
| 181 | data_out,
|
---|
| 182 | irq_n,
|
---|
| 183 |
|
---|
| 184 | sample_point,
|
---|
| 185 | transmitting,
|
---|
| 186 | set_reset_mode,
|
---|
| 187 | node_bus_off,
|
---|
| 188 | error_status,
|
---|
| 189 | rx_err_cnt,
|
---|
| 190 | tx_err_cnt,
|
---|
| 191 | transmit_status,
|
---|
| 192 | receive_status,
|
---|
| 193 | tx_successful,
|
---|
| 194 | need_to_tx,
|
---|
| 195 | overrun,
|
---|
| 196 | info_empty,
|
---|
| 197 | set_bus_error_irq,
|
---|
| 198 | set_arbitration_lost_irq,
|
---|
| 199 | arbitration_lost_capture,
|
---|
| 200 | node_error_passive,
|
---|
| 201 | node_error_active,
|
---|
| 202 | rx_message_counter,
|
---|
| 203 |
|
---|
| 204 |
|
---|
| 205 | /* Mode register */
|
---|
| 206 | reset_mode,
|
---|
| 207 | listen_only_mode,
|
---|
| 208 | acceptance_filter_mode,
|
---|
| 209 | self_test_mode,
|
---|
| 210 |
|
---|
| 211 |
|
---|
| 212 | /* Command register */
|
---|
| 213 | clear_data_overrun,
|
---|
| 214 | release_buffer,
|
---|
| 215 | abort_tx,
|
---|
| 216 | tx_request,
|
---|
| 217 | self_rx_request,
|
---|
| 218 | single_shot_transmission,
|
---|
| 219 | tx_state,
|
---|
| 220 | tx_state_q,
|
---|
| 221 | overload_request,
|
---|
| 222 | overload_frame,
|
---|
| 223 |
|
---|
| 224 | /* Arbitration Lost Capture Register */
|
---|
| 225 | read_arbitration_lost_capture_reg,
|
---|
| 226 |
|
---|
| 227 | /* Error Code Capture Register */
|
---|
| 228 | read_error_code_capture_reg,
|
---|
| 229 | error_capture_code,
|
---|
| 230 |
|
---|
| 231 | /* Bus Timing 0 register */
|
---|
| 232 | baud_r_presc,
|
---|
| 233 | sync_jump_width,
|
---|
| 234 |
|
---|
| 235 | /* Bus Timing 1 register */
|
---|
| 236 | time_segment1,
|
---|
| 237 | time_segment2,
|
---|
| 238 | triple_sampling,
|
---|
| 239 |
|
---|
| 240 | /* Error Warning Limit register */
|
---|
| 241 | error_warning_limit,
|
---|
| 242 |
|
---|
| 243 | /* Rx Error Counter register */
|
---|
| 244 | we_rx_err_cnt,
|
---|
| 245 |
|
---|
| 246 | /* Tx Error Counter register */
|
---|
| 247 | we_tx_err_cnt,
|
---|
| 248 |
|
---|
| 249 | /* Clock Divider register */
|
---|
| 250 | extended_mode,
|
---|
| 251 | clkout,
|
---|
| 252 |
|
---|
| 253 |
|
---|
| 254 | /* This section is for BASIC and EXTENDED mode */
|
---|
| 255 | /* Acceptance code register */
|
---|
| 256 | acceptance_code_0,
|
---|
| 257 |
|
---|
| 258 | /* Acceptance mask register */
|
---|
| 259 | acceptance_mask_0,
|
---|
| 260 | /* End: This section is for BASIC and EXTENDED mode */
|
---|
| 261 |
|
---|
| 262 | /* This section is for EXTENDED mode */
|
---|
| 263 | /* Acceptance code register */
|
---|
| 264 | acceptance_code_1,
|
---|
| 265 | acceptance_code_2,
|
---|
| 266 | acceptance_code_3,
|
---|
| 267 |
|
---|
| 268 | /* Acceptance mask register */
|
---|
| 269 | acceptance_mask_1,
|
---|
| 270 | acceptance_mask_2,
|
---|
| 271 | acceptance_mask_3,
|
---|
| 272 | /* End: This section is for EXTENDED mode */
|
---|
| 273 |
|
---|
| 274 | rx_dt,
|
---|
| 275 | rx_we,
|
---|
| 276 | /* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
|
---|
| 277 | tx_data_0,
|
---|
| 278 | tx_data_1,
|
---|
| 279 | tx_data_2,
|
---|
| 280 | tx_data_3,
|
---|
| 281 | tx_data_4,
|
---|
| 282 | tx_data_5,
|
---|
| 283 | tx_data_6,
|
---|
| 284 | tx_data_7,
|
---|
| 285 | tx_data_8,
|
---|
| 286 | tx_data_9,
|
---|
| 287 | tx_data_10,
|
---|
| 288 | tx_data_11,
|
---|
| 289 | tx_data_12
|
---|
| 290 | /* End: Tx data registers */
|
---|
| 291 |
|
---|
| 292 |
|
---|
| 293 |
|
---|
| 294 |
|
---|
| 295 | );
|
---|
| 296 |
|
---|
| 297 | parameter Tp = 1;
|
---|
| 298 | parameter TXMBOX_DEPTH = 1; /* 1(Min=2) - 4(Max=16) */
|
---|
| 299 | parameter RXMBOX_DEPTH = 1; /* 1(Min=2) - 5(Max=32) */
|
---|
| 300 | localparam TXMBOX_BITS = (TXMBOX_DEPTH > 4) ? 16 : (2**TXMBOX_DEPTH);
|
---|
| 301 | localparam RXMBOX_BITS = (RXMBOX_DEPTH > 5) ? 32 :(2**RXMBOX_DEPTH);
|
---|
| 302 |
|
---|
| 303 | input clk;
|
---|
| 304 | input rst;
|
---|
| 305 | input cs;
|
---|
| 306 | input we;
|
---|
| 307 | input [9:0] addr;
|
---|
| 308 | input [31:0] data_in;
|
---|
| 309 |
|
---|
| 310 | output [31:0] data_out;
|
---|
| 311 | reg [31:0] data_out;
|
---|
| 312 |
|
---|
| 313 | output irq_n;
|
---|
| 314 |
|
---|
| 315 | input sample_point;
|
---|
| 316 | input transmitting;
|
---|
| 317 | input set_reset_mode;
|
---|
| 318 | input node_bus_off;
|
---|
| 319 | input error_status;
|
---|
| 320 | input [7:0] rx_err_cnt;
|
---|
| 321 | input [7:0] tx_err_cnt;
|
---|
| 322 | input transmit_status;
|
---|
| 323 | input receive_status;
|
---|
| 324 | input tx_successful;
|
---|
| 325 | input need_to_tx;
|
---|
| 326 | input overrun;
|
---|
| 327 | input info_empty;
|
---|
| 328 | input set_bus_error_irq;
|
---|
| 329 | input set_arbitration_lost_irq;
|
---|
| 330 | input [4:0] arbitration_lost_capture;
|
---|
| 331 | input node_error_passive;
|
---|
| 332 | input node_error_active;
|
---|
| 333 | input [6:0] rx_message_counter;
|
---|
| 334 |
|
---|
| 335 |
|
---|
| 336 |
|
---|
| 337 | /* Mode register */
|
---|
| 338 | output reset_mode;
|
---|
| 339 | output listen_only_mode;
|
---|
| 340 | output acceptance_filter_mode;
|
---|
| 341 | output self_test_mode;
|
---|
| 342 |
|
---|
| 343 | /* Command register */
|
---|
| 344 | output clear_data_overrun;
|
---|
| 345 | output release_buffer;
|
---|
| 346 | output abort_tx;
|
---|
| 347 | output tx_request;
|
---|
| 348 | output self_rx_request;
|
---|
| 349 | output single_shot_transmission;
|
---|
| 350 | input tx_state;
|
---|
| 351 | input tx_state_q;
|
---|
| 352 | output overload_request;
|
---|
| 353 | input overload_frame;
|
---|
| 354 |
|
---|
| 355 |
|
---|
| 356 | /* Arbitration Lost Capture Register */
|
---|
| 357 | output read_arbitration_lost_capture_reg;
|
---|
| 358 |
|
---|
| 359 | /* Error Code Capture Register */
|
---|
| 360 | output read_error_code_capture_reg;
|
---|
| 361 | input [7:0] error_capture_code;
|
---|
| 362 |
|
---|
| 363 | /* Bus Timing 0 register */
|
---|
| 364 | output [5:0] baud_r_presc;
|
---|
| 365 | output [1:0] sync_jump_width;
|
---|
| 366 |
|
---|
| 367 |
|
---|
| 368 | /* Bus Timing 1 register */
|
---|
| 369 | output [3:0] time_segment1;
|
---|
| 370 | output [2:0] time_segment2;
|
---|
| 371 | output triple_sampling;
|
---|
| 372 |
|
---|
| 373 | /* Error Warning Limit register */
|
---|
| 374 | output [7:0] error_warning_limit;
|
---|
| 375 |
|
---|
| 376 | /* Rx Error Counter register */
|
---|
| 377 | output we_rx_err_cnt;
|
---|
| 378 |
|
---|
| 379 | /* Tx Error Counter register */
|
---|
| 380 | output we_tx_err_cnt;
|
---|
| 381 |
|
---|
| 382 | /* Clock Divider register */
|
---|
| 383 | output extended_mode;
|
---|
| 384 | output clkout;
|
---|
| 385 |
|
---|
| 386 |
|
---|
| 387 | /* This section is for BASIC and EXTENDED mode */
|
---|
| 388 | /* Acceptance code register */
|
---|
| 389 | output [7:0] acceptance_code_0;
|
---|
| 390 |
|
---|
| 391 | /* Acceptance mask register */
|
---|
| 392 | output [7:0] acceptance_mask_0;
|
---|
| 393 |
|
---|
| 394 | /* End: This section is for BASIC and EXTENDED mode */
|
---|
| 395 |
|
---|
| 396 |
|
---|
| 397 | /* This section is for EXTENDED mode */
|
---|
| 398 | /* Acceptance code register */
|
---|
| 399 | output [7:0] acceptance_code_1;
|
---|
| 400 | output [7:0] acceptance_code_2;
|
---|
| 401 | output [7:0] acceptance_code_3;
|
---|
| 402 |
|
---|
| 403 | /* Acceptance mask register */
|
---|
| 404 | output [7:0] acceptance_mask_1;
|
---|
| 405 | output [7:0] acceptance_mask_2;
|
---|
| 406 | output [7:0] acceptance_mask_3;
|
---|
| 407 |
|
---|
| 408 | /* End: This section is for EXTENDED mode */
|
---|
| 409 |
|
---|
| 410 |
|
---|
| 411 | input [127:0] rx_dt;
|
---|
| 412 | input rx_we;
|
---|
| 413 | /* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
|
---|
| 414 | output [7:0] tx_data_0;
|
---|
| 415 | output [7:0] tx_data_1;
|
---|
| 416 | output [7:0] tx_data_2;
|
---|
| 417 | output [7:0] tx_data_3;
|
---|
| 418 | output [7:0] tx_data_4;
|
---|
| 419 | output [7:0] tx_data_5;
|
---|
| 420 | output [7:0] tx_data_6;
|
---|
| 421 | output [7:0] tx_data_7;
|
---|
| 422 | output [7:0] tx_data_8;
|
---|
| 423 | output [7:0] tx_data_9;
|
---|
| 424 | output [7:0] tx_data_10;
|
---|
| 425 | output [7:0] tx_data_11;
|
---|
| 426 | output [7:0] tx_data_12;
|
---|
| 427 | /* End: Tx data registers */
|
---|
| 428 |
|
---|
| 429 |
|
---|
| 430 | reg [TXMBOX_BITS-1:0] transmit_cancel;
|
---|
| 431 | reg [RXMBOX_BITS-1:0] rxovrwrite;
|
---|
| 432 | //reg [15:0] transmit_cancel;
|
---|
| 433 | //reg [31:0] rxovrwrite;
|
---|
| 434 | reg tx_successful_q;
|
---|
| 435 | reg overrun_q;
|
---|
| 436 | reg overrun_status;
|
---|
| 437 | reg transmission_complete;
|
---|
| 438 | reg transmit_buffer_status_q;
|
---|
| 439 | reg receive_buffer_status;
|
---|
| 440 | reg error_status_q;
|
---|
| 441 | reg node_bus_off_q;
|
---|
| 442 | reg node_error_passive_q;
|
---|
| 443 | reg transmit_buffer_status;
|
---|
| 444 | reg single_shot_transmission;
|
---|
| 445 | reg self_rx_request;
|
---|
| 446 | reg irq_n;
|
---|
| 447 |
|
---|
| 448 | // Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
|
---|
| 449 | wire data_overrun_irq_en;
|
---|
| 450 | wire error_warning_irq_en;
|
---|
| 451 | wire transmit_irq_en;
|
---|
| 452 | wire receive_irq_en;
|
---|
| 453 |
|
---|
| 454 | wire [7:0] irq_reg;
|
---|
| 455 | wire irq;
|
---|
| 456 |
|
---|
| 457 | reg [TXMBOX_BITS-1:0] txreq;
|
---|
| 458 | reg [TXMBOX_BITS-1:0] txabort;
|
---|
| 459 | reg [TXMBOX_BITS-1:0] txcmp;
|
---|
| 460 | reg [RXMBOX_BITS-1:0] rxwait;
|
---|
| 461 | reg [RXMBOX_BITS-1:0] rxcmp;
|
---|
| 462 | reg [TXMBOX_BITS-1:0] rxselfreq;
|
---|
| 463 | //reg [15:0] txreq;
|
---|
| 464 | //reg [15:0] txabort;
|
---|
| 465 | //reg [15:0] txcmp;
|
---|
| 466 | //reg [31:0] rxwait;
|
---|
| 467 | //reg [31:0] rxcmp;
|
---|
| 468 | //reg [15:0] rxselfreq;
|
---|
| 469 |
|
---|
| 470 | // fsm
|
---|
| 471 | reg [1:0] state;
|
---|
| 472 | reg [2:0] st_sel_cnt;
|
---|
| 473 | parameter st_idle = 2'h0;
|
---|
| 474 | parameter st_sel = 2'h1;
|
---|
| 475 | parameter st_set = 2'h2;
|
---|
| 476 | parameter st_wait = 2'h3;
|
---|
| 477 | always @ (posedge clk or posedge rst)
|
---|
| 478 | begin
|
---|
| 479 | if (rst)
|
---|
| 480 | state <= st_idle;
|
---|
| 481 | else if (reset_mode)
|
---|
| 482 | state <=#Tp st_idle;
|
---|
| 483 | else case (state)
|
---|
| 484 | st_idle : if (|(txreq & ~txabort)) state <=#Tp st_sel;
|
---|
| 485 | st_sel : if (&st_sel_cnt) state <=#Tp st_set;
|
---|
| 486 | st_set : if ( need_to_tx) state <=#Tp st_wait;
|
---|
| 487 | st_wait : if (~need_to_tx) state <=#Tp st_idle;
|
---|
| 488 | endcase
|
---|
| 489 | end
|
---|
| 490 | always @ (posedge clk or posedge rst)
|
---|
| 491 | begin
|
---|
| 492 | if (rst)
|
---|
| 493 | st_sel_cnt <= 3'h0;
|
---|
| 494 | else if (state == st_sel)
|
---|
| 495 | st_sel_cnt <=#Tp st_sel_cnt +3'h1;
|
---|
| 496 | else
|
---|
| 497 | st_sel_cnt <=#Tp 3'h0;
|
---|
| 498 | end
|
---|
| 499 |
|
---|
| 500 |
|
---|
| 501 |
|
---|
| 502 | // sort tx data
|
---|
| 503 | wire [127:0] txdata [0:TXMBOX_BITS-1];
|
---|
| 504 | //wire [127:0] txdata [0:15];
|
---|
| 505 | reg [127:0] txtmp ;
|
---|
| 506 | reg [28:0] txid ;
|
---|
| 507 | reg txfmt ;
|
---|
| 508 | reg txrtr ;
|
---|
| 509 | reg [3:0] txdlc ;
|
---|
| 510 | reg [7:0] txdata1;
|
---|
| 511 | reg [7:0] txdata2;
|
---|
| 512 | reg [7:0] txdata3;
|
---|
| 513 | reg [7:0] txdata4;
|
---|
| 514 | reg [7:0] txdata5;
|
---|
| 515 | reg [7:0] txdata6;
|
---|
| 516 | reg [7:0] txdata7;
|
---|
| 517 | reg [7:0] txdata8;
|
---|
| 518 | reg [3:0] txmsgbox;
|
---|
| 519 | wire rxselfreq_en = rxselfreq[txmsgbox];
|
---|
| 520 |
|
---|
| 521 | always @ (*)
|
---|
| 522 | begin
|
---|
| 523 | txtmp = txdata[txmsgbox];
|
---|
| 524 | txfmt = txtmp[0*32+31];
|
---|
| 525 | txid = txtmp[0*32+28:0*32];
|
---|
| 526 | txrtr = txtmp[1*32+4];
|
---|
| 527 | txdlc = txtmp[1*32+3:1*32];
|
---|
| 528 | txdata1 = txtmp[2*32+0*8+7:2*32+0*8];
|
---|
| 529 | txdata2 = txtmp[2*32+1*8+7:2*32+1*8];
|
---|
| 530 | txdata3 = txtmp[2*32+2*8+7:2*32+2*8];
|
---|
| 531 | txdata4 = txtmp[2*32+3*8+7:2*32+3*8];
|
---|
| 532 | txdata5 = txtmp[3*32+0*8+7:3*32+0*8];
|
---|
| 533 | txdata6 = txtmp[3*32+1*8+7:3*32+1*8];
|
---|
| 534 | txdata7 = txtmp[3*32+2*8+7:3*32+2*8];
|
---|
| 535 | txdata8 = txtmp[3*32+3*8+7:3*32+3*8];
|
---|
| 536 | end
|
---|
| 537 |
|
---|
| 538 |
|
---|
| 539 | // latch tx data
|
---|
| 540 | wire we_txstart;
|
---|
| 541 | reg [7:0] tx_data_0;
|
---|
| 542 | reg [7:0] tx_data_1;
|
---|
| 543 | reg [7:0] tx_data_2;
|
---|
| 544 | reg [7:0] tx_data_3;
|
---|
| 545 | reg [7:0] tx_data_4;
|
---|
| 546 | reg [7:0] tx_data_5;
|
---|
| 547 | reg [7:0] tx_data_6;
|
---|
| 548 | reg [7:0] tx_data_7;
|
---|
| 549 | reg [7:0] tx_data_8;
|
---|
| 550 | reg [7:0] tx_data_9;
|
---|
| 551 | reg [7:0] tx_data_10;
|
---|
| 552 | reg [7:0] tx_data_11;
|
---|
| 553 | reg [7:0] tx_data_12;
|
---|
| 554 | always @ (posedge clk or posedge rst)
|
---|
| 555 | begin
|
---|
| 556 | if (rst)
|
---|
| 557 | begin
|
---|
| 558 | tx_data_0 <= 8'h0;
|
---|
| 559 | tx_data_1 <= 8'h0;
|
---|
| 560 | tx_data_2 <= 8'h0;
|
---|
| 561 | tx_data_3 <= 8'h0;
|
---|
| 562 | tx_data_4 <= 8'h0;
|
---|
| 563 | tx_data_5 <= 8'h0;
|
---|
| 564 | tx_data_6 <= 8'h0;
|
---|
| 565 | tx_data_7 <= 8'h0;
|
---|
| 566 | tx_data_8 <= 8'h0;
|
---|
| 567 | tx_data_9 <= 8'h0;
|
---|
| 568 | tx_data_10 <= 8'h0;
|
---|
| 569 | tx_data_11 <= 8'h0;
|
---|
| 570 | tx_data_12 <= 8'h0;
|
---|
| 571 | end
|
---|
| 572 | else if (we_txstart)
|
---|
| 573 | begin
|
---|
| 574 | if(~extended_mode)
|
---|
| 575 | begin
|
---|
| 576 | tx_data_0 <=#Tp txid[28:21];
|
---|
| 577 | tx_data_1 <=#Tp {txid[20:18],txrtr,txdlc};
|
---|
| 578 | tx_data_2 <=#Tp txdata1;
|
---|
| 579 | tx_data_3 <=#Tp txdata2;
|
---|
| 580 | tx_data_4 <=#Tp txdata3;
|
---|
| 581 | tx_data_5 <=#Tp txdata4;
|
---|
| 582 | tx_data_6 <=#Tp txdata5;
|
---|
| 583 | tx_data_7 <=#Tp txdata6;
|
---|
| 584 | tx_data_8 <=#Tp txdata7;
|
---|
| 585 | tx_data_9 <=#Tp txdata8;
|
---|
| 586 | tx_data_10 <=#Tp 8'h0;
|
---|
| 587 | tx_data_11 <=#Tp 8'h0;
|
---|
| 588 | tx_data_12 <=#Tp 8'h0;
|
---|
| 589 | end
|
---|
| 590 | else
|
---|
| 591 | begin
|
---|
| 592 | tx_data_0 <=#Tp {txfmt,txrtr,2'h0,txdlc};
|
---|
| 593 | tx_data_1 <=#Tp txid[28:21];
|
---|
| 594 | tx_data_2 <=#Tp (~txfmt)? {txid[20:18],5'h0}: txid[20:13];
|
---|
| 595 | tx_data_3 <=#Tp (~txfmt)? txdata1: txid[12:5];
|
---|
| 596 | tx_data_4 <=#Tp (~txfmt)? txdata2: {txid[4:0],3'h0};
|
---|
| 597 | tx_data_5 <=#Tp (~txfmt)? txdata3: txdata1;
|
---|
| 598 | tx_data_6 <=#Tp (~txfmt)? txdata4: txdata2;
|
---|
| 599 | tx_data_7 <=#Tp (~txfmt)? txdata5: txdata3;
|
---|
| 600 | tx_data_8 <=#Tp (~txfmt)? txdata6: txdata4;
|
---|
| 601 | tx_data_9 <=#Tp (~txfmt)? txdata7: txdata5;
|
---|
| 602 | tx_data_10 <=#Tp (~txfmt)? txdata8: txdata6;
|
---|
| 603 | tx_data_11 <=#Tp txdata7;
|
---|
| 604 | tx_data_12 <=#Tp txdata8;
|
---|
| 605 | end
|
---|
| 606 | end
|
---|
| 607 | end
|
---|
| 608 |
|
---|
| 609 |
|
---|
| 610 | // arbitration lost
|
---|
| 611 | reg [3:0] arbitration_lost_capture_mbox;
|
---|
| 612 | always @ (posedge clk or posedge rst)
|
---|
| 613 | begin
|
---|
| 614 | if (rst)
|
---|
| 615 | arbitration_lost_capture_mbox <= 4'h0;
|
---|
| 616 | else if (set_arbitration_lost_irq)
|
---|
| 617 | arbitration_lost_capture_mbox <=#Tp txmsgbox;
|
---|
| 618 | end
|
---|
| 619 |
|
---|
| 620 | // error capture
|
---|
| 621 | reg set_bus_error_irq_q;
|
---|
| 622 | always @ (posedge clk or posedge rst)
|
---|
| 623 | begin
|
---|
| 624 | if (rst)
|
---|
| 625 | set_bus_error_irq_q <= 1'h0;
|
---|
| 626 | else
|
---|
| 627 | set_bus_error_irq_q <=#Tp set_bus_error_irq;
|
---|
| 628 | end
|
---|
| 629 |
|
---|
| 630 | reg [3:0] error_capture_code_mbox;
|
---|
| 631 | always @ (posedge clk or posedge rst)
|
---|
| 632 | begin
|
---|
| 633 | if (rst)
|
---|
| 634 | error_capture_code_mbox <= 4'h0;
|
---|
| 635 | else if(set_bus_error_irq_q)
|
---|
| 636 | error_capture_code_mbox <=#Tp (error_capture_code[5])? 4'h0: txmsgbox;//0:tx error 1:rx error
|
---|
| 637 | end
|
---|
| 638 |
|
---|
| 639 |
|
---|
| 640 | wire we_mode = cs & we & (addr == 10'h0);
|
---|
| 641 | wire we_command = 0;
|
---|
| 642 | wire we_bus_timing_0 = cs & we & (addr == 10'h034) & reset_mode;
|
---|
| 643 | wire we_bus_timing_1 = cs & we & (addr == 10'h034) & reset_mode;
|
---|
| 644 | wire we_clock_divider_low = cs & we & (addr == 10'h034);
|
---|
| 645 | wire we_clock_divider_hi = we_clock_divider_low & reset_mode;
|
---|
| 646 |
|
---|
| 647 | wire we_txreq = cs & we & (addr == 10'h004);
|
---|
| 648 | wire we_txabort = cs & we & (addr == 10'h008);
|
---|
| 649 | wire we_txcmp = cs & we & (addr == 10'h00C);
|
---|
| 650 | wire we_txcancel = cs & we & (addr == 10'h010);
|
---|
| 651 | wire we_rxwait = cs & we & (addr == 10'h014);
|
---|
| 652 | wire we_rxcmp = cs & we & (addr == 10'h018);
|
---|
| 653 | wire we_rxselfreq= cs & we & (addr == 10'h020);
|
---|
| 654 |
|
---|
| 655 |
|
---|
| 656 | wire read = cs & (~we);
|
---|
| 657 | wire read_rxovrwrite = read & (addr == 10'h01C);
|
---|
| 658 | wire read_irq_reg = read & (addr == 10'h028);
|
---|
| 659 | assign read_arbitration_lost_capture_reg = read & extended_mode & (addr == 10'h040);
|
---|
| 660 | assign read_error_code_capture_reg = read & extended_mode & (addr == 10'h044);
|
---|
| 661 |
|
---|
| 662 | /* This section is for BASIC and EXTENDED mode */
|
---|
| 663 | wire we_acceptance_code_0 = cs & we & reset_mode & (addr == 10'h038);
|
---|
| 664 | wire we_acceptance_mask_0 = cs & we & reset_mode & (addr == 10'h03C);
|
---|
| 665 | wire we_datawin = cs & we & (addr == 10'h04C);
|
---|
| 666 | assign we_txstart = (state == st_set) & transmit_buffer_status;
|
---|
| 667 | /* End: This section is for BASIC and EXTENDED mode */
|
---|
| 668 |
|
---|
| 669 |
|
---|
| 670 | /* This section is for EXTENDED mode */
|
---|
| 671 | wire we_interrupt_enable = cs & we & (addr == 10'h02C) ;
|
---|
| 672 | wire we_irq_rxen = cs & we & (addr == 10'h030) ;
|
---|
| 673 | wire we_error_warning_limit = cs & we & (addr == 10'h048) & reset_mode ;
|
---|
| 674 | assign we_rx_err_cnt = cs & we & (addr == 10'h048) & reset_mode ;
|
---|
| 675 | assign we_tx_err_cnt = cs & we & (addr == 10'h048) & reset_mode ;
|
---|
| 676 | wire we_acceptance_code_1 = cs & we & (addr == 10'h038) & reset_mode ;
|
---|
| 677 | wire we_acceptance_code_2 = cs & we & (addr == 10'h038) & reset_mode ;
|
---|
| 678 | wire we_acceptance_code_3 = cs & we & (addr == 10'h038) & reset_mode ;
|
---|
| 679 | wire we_acceptance_mask_1 = cs & we & (addr == 10'h03C) & reset_mode ;
|
---|
| 680 | wire we_acceptance_mask_2 = cs & we & (addr == 10'h03C) & reset_mode ;
|
---|
| 681 | wire we_acceptance_mask_3 = cs & we & (addr == 10'h03C) & reset_mode ;
|
---|
| 682 | /* End: This section is for EXTENDED mode */
|
---|
| 683 |
|
---|
| 684 |
|
---|
| 685 |
|
---|
| 686 | always @ (posedge clk)
|
---|
| 687 | begin
|
---|
| 688 | tx_successful_q <=#Tp tx_successful;
|
---|
| 689 | overrun_q <=#Tp overrun;
|
---|
| 690 | transmit_buffer_status_q <=#Tp transmit_buffer_status;
|
---|
| 691 | error_status_q <=#Tp error_status;
|
---|
| 692 | node_bus_off_q <=#Tp node_bus_off;
|
---|
| 693 | node_error_passive_q <=#Tp node_error_passive;
|
---|
| 694 | end
|
---|
| 695 |
|
---|
| 696 |
|
---|
| 697 |
|
---|
| 698 | /* Mode register */
|
---|
| 699 | wire [0:0] mode;
|
---|
| 700 | wire [4:1] mode_basic;
|
---|
| 701 | wire [3:1] mode_ext;
|
---|
| 702 | wire receive_irq_en_basic;
|
---|
| 703 | wire transmit_irq_en_basic;
|
---|
| 704 | wire error_irq_en_basic;
|
---|
| 705 | wire overrun_irq_en_basic;
|
---|
| 706 |
|
---|
| 707 | can_register_asyn_syn #(1, 1'h1) MODE_REG0
|
---|
| 708 | ( .data_in(data_in[0]),
|
---|
| 709 | .data_out(mode[0]),
|
---|
| 710 | .we(we_mode),
|
---|
| 711 | .clk(clk),
|
---|
| 712 | .rst(rst),
|
---|
| 713 | .rst_sync(set_reset_mode)
|
---|
| 714 | );
|
---|
| 715 |
|
---|
| 716 | can_register_asyn #(4, 4'h0) MODE_REG_BASIC
|
---|
| 717 | ( .data_in(data_in[4:1]),
|
---|
| 718 | .data_out(mode_basic[4:1]),
|
---|
| 719 | .we(we_mode),
|
---|
| 720 | .clk(clk),
|
---|
| 721 | .rst(rst)
|
---|
| 722 | );
|
---|
| 723 |
|
---|
| 724 | can_register_asyn #(3, 3'h0) MODE_REG_EXT
|
---|
| 725 | ( .data_in(data_in[3:1]),
|
---|
| 726 | .data_out(mode_ext[3:1]),
|
---|
| 727 | .we(we_mode & reset_mode),
|
---|
| 728 | .clk(clk),
|
---|
| 729 | .rst(rst)
|
---|
| 730 | );
|
---|
| 731 |
|
---|
| 732 | assign reset_mode = mode[0];
|
---|
| 733 | assign listen_only_mode = extended_mode & mode_ext[1];
|
---|
| 734 | assign self_test_mode = extended_mode & mode_ext[2];
|
---|
| 735 | assign acceptance_filter_mode = extended_mode & mode_ext[3];
|
---|
| 736 |
|
---|
| 737 | assign receive_irq_en_basic = mode_basic[1];
|
---|
| 738 | assign transmit_irq_en_basic = mode_basic[2];
|
---|
| 739 | assign error_irq_en_basic = mode_basic[3];
|
---|
| 740 | assign overrun_irq_en_basic = mode_basic[4];
|
---|
| 741 | /* End Mode register */
|
---|
| 742 |
|
---|
| 743 |
|
---|
| 744 | /* Command register */
|
---|
| 745 | wire [4:0] command;
|
---|
| 746 | can_register_asyn_syn #(1, 1'h0) COMMAND_REG0
|
---|
| 747 | ( .data_in(~rxselfreq_en),
|
---|
| 748 | .data_out(command[0]),
|
---|
| 749 | .we(we_txstart),
|
---|
| 750 | .clk(clk),
|
---|
| 751 | .rst(rst),
|
---|
| 752 | .rst_sync(command[0] & sample_point | reset_mode)
|
---|
| 753 | );
|
---|
| 754 |
|
---|
| 755 | can_register_asyn_syn #(1, 1'h0) COMMAND_REG1
|
---|
| 756 | ( .data_in(1'h1),
|
---|
| 757 | .data_out(command[1]),
|
---|
| 758 | .we(we_txstart),
|
---|
| 759 | .clk(clk),
|
---|
| 760 | .rst(rst),
|
---|
| 761 | .rst_sync(sample_point & (tx_request | (abort_tx & ~transmitting)) | reset_mode)
|
---|
| 762 | );
|
---|
| 763 |
|
---|
| 764 | can_register_asyn_syn #(2, 2'h0) COMMAND_REG
|
---|
| 765 | ( .data_in(data_in[3:2]),
|
---|
| 766 | .data_out(command[3:2]),
|
---|
| 767 | .we(we_command),
|
---|
| 768 | .clk(clk),
|
---|
| 769 | .rst(rst),
|
---|
| 770 | .rst_sync(|command[3:2] | reset_mode)
|
---|
| 771 | );
|
---|
| 772 |
|
---|
| 773 | can_register_asyn_syn #(1, 1'h0) COMMAND_REG4
|
---|
| 774 | ( .data_in(rxselfreq_en),
|
---|
| 775 | .data_out(command[4]),
|
---|
| 776 | .we(we_txstart),
|
---|
| 777 | .clk(clk),
|
---|
| 778 | .rst(rst),
|
---|
| 779 | .rst_sync(command[4] & sample_point | reset_mode)
|
---|
| 780 | );
|
---|
| 781 |
|
---|
| 782 |
|
---|
| 783 | always @ (posedge clk or posedge rst)
|
---|
| 784 | begin
|
---|
| 785 | if (rst)
|
---|
| 786 | self_rx_request <= 1'b0;
|
---|
| 787 | else if (command[4] & (~command[0]))
|
---|
| 788 | self_rx_request <=#Tp 1'b1;
|
---|
| 789 | else if ((~tx_state) & tx_state_q)
|
---|
| 790 | self_rx_request <=#Tp 1'b0;
|
---|
| 791 | end
|
---|
| 792 |
|
---|
| 793 |
|
---|
| 794 | assign clear_data_overrun = command[3];
|
---|
| 795 | assign release_buffer = command[2];
|
---|
| 796 | assign tx_request = command[0] | command[4];
|
---|
| 797 | assign abort_tx = (state == st_wait) & txabort[txmsgbox] & (~tx_request);//command[1] & (~tx_request);
|
---|
| 798 |
|
---|
| 799 |
|
---|
| 800 | always @ (posedge clk or posedge rst)
|
---|
| 801 | begin
|
---|
| 802 | if (rst)
|
---|
| 803 | single_shot_transmission <= 1'b0;
|
---|
| 804 | // else if (tx_request & command[1] & sample_point)
|
---|
| 805 | else if (tx_request & sample_point)
|
---|
| 806 | single_shot_transmission <=#Tp 1'b1;
|
---|
| 807 | //else if ((~tx_state) & tx_state_q)
|
---|
| 808 | else if ((~tx_state) & tx_state_q | (abort_tx & (~transmitting)))
|
---|
| 809 | single_shot_transmission <=#Tp 1'b0;
|
---|
| 810 | end
|
---|
| 811 |
|
---|
| 812 |
|
---|
| 813 | /*
|
---|
| 814 | can_register_asyn_syn #(1, 1'h0) COMMAND_REG_OVERLOAD // Uncomment this to enable overload requests !!!
|
---|
| 815 | ( .data_in(data_in[5]),
|
---|
| 816 | .data_out(overload_request),
|
---|
| 817 | .we(we_command),
|
---|
| 818 | .clk(clk),
|
---|
| 819 | .rst(rst),
|
---|
| 820 | .rst_sync(overload_frame & ~overload_frame_q)
|
---|
| 821 | );
|
---|
| 822 |
|
---|
| 823 | reg overload_frame_q;
|
---|
| 824 |
|
---|
| 825 | always @ (posedge clk or posedge rst)
|
---|
| 826 | begin
|
---|
| 827 | if (rst)
|
---|
| 828 | overload_frame_q <= 1'b0;
|
---|
| 829 | else
|
---|
| 830 | overload_frame_q <=#Tp overload_frame;
|
---|
| 831 | end
|
---|
| 832 | */
|
---|
| 833 | assign overload_request = 0; // Overload requests are not supported, yet !!!
|
---|
| 834 |
|
---|
| 835 |
|
---|
| 836 |
|
---|
| 837 |
|
---|
| 838 |
|
---|
| 839 | /* End Command register */
|
---|
| 840 |
|
---|
| 841 |
|
---|
| 842 | /* Status register */
|
---|
| 843 |
|
---|
| 844 | wire [7:0] status;
|
---|
| 845 |
|
---|
| 846 | assign status[7] = node_bus_off;
|
---|
| 847 | assign status[6] = error_status;
|
---|
| 848 | assign status[5] = transmit_status;
|
---|
| 849 | assign status[4] = receive_status;
|
---|
| 850 | assign status[3] = transmission_complete;
|
---|
| 851 | assign status[2] = transmit_buffer_status;
|
---|
| 852 | assign status[1] = overrun_status;
|
---|
| 853 | assign status[0] = receive_buffer_status;
|
---|
| 854 |
|
---|
| 855 |
|
---|
| 856 |
|
---|
| 857 | always @ (posedge clk or posedge rst)
|
---|
| 858 | begin
|
---|
| 859 | if (rst)
|
---|
| 860 | transmission_complete <= 1'b1;
|
---|
| 861 | else if (tx_successful & (~tx_successful_q) | abort_tx)
|
---|
| 862 | transmission_complete <=#Tp 1'b1;
|
---|
| 863 | else if (tx_request)
|
---|
| 864 | transmission_complete <=#Tp 1'b0;
|
---|
| 865 | end
|
---|
| 866 |
|
---|
| 867 |
|
---|
| 868 | always @ (posedge clk or posedge rst)
|
---|
| 869 | begin
|
---|
| 870 | if (rst)
|
---|
| 871 | transmit_buffer_status <= 1'b1;
|
---|
| 872 | else if (tx_request)
|
---|
| 873 | transmit_buffer_status <=#Tp 1'b0;
|
---|
| 874 | else if (reset_mode || !need_to_tx)
|
---|
| 875 | transmit_buffer_status <=#Tp 1'b1;
|
---|
| 876 | end
|
---|
| 877 |
|
---|
| 878 |
|
---|
| 879 | always @ (posedge clk or posedge rst)
|
---|
| 880 | begin
|
---|
| 881 | if (rst)
|
---|
| 882 | overrun_status <= 1'b0;
|
---|
| 883 | else if (overrun & (~overrun_q))
|
---|
| 884 | overrun_status <=#Tp 1'b1;
|
---|
| 885 | else if (reset_mode || clear_data_overrun)
|
---|
| 886 | overrun_status <=#Tp 1'b0;
|
---|
| 887 | end
|
---|
| 888 |
|
---|
| 889 |
|
---|
| 890 | always @ (posedge clk or posedge rst)
|
---|
| 891 | begin
|
---|
| 892 | if (rst)
|
---|
| 893 | receive_buffer_status <= 1'b0;
|
---|
| 894 | else if (reset_mode || release_buffer)
|
---|
| 895 | receive_buffer_status <=#Tp 1'b0;
|
---|
| 896 | else if (~info_empty)
|
---|
| 897 | receive_buffer_status <=#Tp 1'b1;
|
---|
| 898 | end
|
---|
| 899 |
|
---|
| 900 | /* End Status register */
|
---|
| 901 |
|
---|
| 902 |
|
---|
| 903 | /* Interrupt Enable register (extended mode) */
|
---|
| 904 | wire [7:0] irq_en_ext;
|
---|
| 905 | wire [31:0] irq_rxen;
|
---|
| 906 | wire bus_error_irq_en;
|
---|
| 907 | wire arbitration_lost_irq_en;
|
---|
| 908 | wire error_passive_irq_en;
|
---|
| 909 | wire transmit_cancel_irq_en;
|
---|
| 910 | wire data_overrun_irq_en_ext;
|
---|
| 911 | wire error_warning_irq_en_ext;
|
---|
| 912 | wire transmit_irq_en_ext;
|
---|
| 913 | wire receive_irq_en_ext;
|
---|
| 914 |
|
---|
| 915 | can_register_asyn #(8, 8'h0) IRQ_EN_REG
|
---|
| 916 | ( .data_in(data_in[7:0]),
|
---|
| 917 | .data_out(irq_en_ext),
|
---|
| 918 | .we(we_interrupt_enable),
|
---|
| 919 | .clk(clk),
|
---|
| 920 | .rst(rst)
|
---|
| 921 | );
|
---|
| 922 |
|
---|
| 923 | can_register_asyn #(32, 32'h0) IRQ_RXEN_REG
|
---|
| 924 | ( .data_in(data_in),
|
---|
| 925 | .data_out(irq_rxen),
|
---|
| 926 | .we(we_irq_rxen),
|
---|
| 927 | .clk(clk),
|
---|
| 928 | .rst(rst)
|
---|
| 929 | );
|
---|
| 930 |
|
---|
| 931 |
|
---|
| 932 | assign bus_error_irq_en = extended_mode & irq_en_ext[7];
|
---|
| 933 | assign arbitration_lost_irq_en = extended_mode & irq_en_ext[6];
|
---|
| 934 | assign error_passive_irq_en = extended_mode & irq_en_ext[5];
|
---|
| 935 | assign transmit_cancel_irq_en = irq_en_ext[4];
|
---|
| 936 | assign data_overrun_irq_en_ext = irq_en_ext[3];
|
---|
| 937 | assign error_warning_irq_en_ext = irq_en_ext[2];
|
---|
| 938 | assign transmit_irq_en_ext = irq_en_ext[1];
|
---|
| 939 | assign receive_irq_en_ext = irq_en_ext[0];
|
---|
| 940 | /* End Bus Timing 0 register */
|
---|
| 941 |
|
---|
| 942 |
|
---|
| 943 | /* Bus Timing 0 register */
|
---|
| 944 | wire [7:0] bus_timing_0;
|
---|
| 945 | can_register_asyn #(8, 8'h0) BUS_TIMING_0_REG
|
---|
| 946 | ( .data_in(data_in[0*8+7:0*8]),
|
---|
| 947 | .data_out(bus_timing_0),
|
---|
| 948 | .we(we_bus_timing_0),
|
---|
| 949 | .clk(clk),
|
---|
| 950 | .rst(rst)
|
---|
| 951 | );
|
---|
| 952 |
|
---|
| 953 | assign baud_r_presc = bus_timing_0[5:0];
|
---|
| 954 | assign sync_jump_width = bus_timing_0[7:6];
|
---|
| 955 | /* End Bus Timing 0 register */
|
---|
| 956 |
|
---|
| 957 |
|
---|
| 958 | /* Bus Timing 1 register */
|
---|
| 959 | wire [7:0] bus_timing_1;
|
---|
| 960 | can_register_asyn #(8, 8'h0) BUS_TIMING_1_REG
|
---|
| 961 | ( .data_in(data_in[1*8+7:1*8]),
|
---|
| 962 | .data_out(bus_timing_1),
|
---|
| 963 | .we(we_bus_timing_1),
|
---|
| 964 | .clk(clk),
|
---|
| 965 | .rst(rst)
|
---|
| 966 | );
|
---|
| 967 |
|
---|
| 968 | assign time_segment1 = bus_timing_1[3:0];
|
---|
| 969 | assign time_segment2 = bus_timing_1[6:4];
|
---|
| 970 | assign triple_sampling = bus_timing_1[7];
|
---|
| 971 | /* End Bus Timing 1 register */
|
---|
| 972 |
|
---|
| 973 |
|
---|
| 974 | /* Error Warning Limit register */
|
---|
| 975 | can_register_asyn #(8, 8'd96) ERROR_WARNING_REG
|
---|
| 976 | ( .data_in(data_in[0*8+7:0*8]),
|
---|
| 977 | .data_out(error_warning_limit),
|
---|
| 978 | .we(we_error_warning_limit),
|
---|
| 979 | .clk(clk),
|
---|
| 980 | .rst(rst)
|
---|
| 981 | );
|
---|
| 982 | /* End Error Warning Limit register */
|
---|
| 983 |
|
---|
| 984 |
|
---|
| 985 |
|
---|
| 986 | /* Clock Divider register */
|
---|
| 987 | wire [7:0] clock_divider;
|
---|
| 988 | wire clock_off;
|
---|
| 989 | wire [2:0] cd;
|
---|
| 990 | reg [2:0] clkout_div;
|
---|
| 991 | reg [2:0] clkout_cnt;
|
---|
| 992 | reg clkout_tmp;
|
---|
| 993 |
|
---|
| 994 | can_register_asyn #(1, 1'h0) CLOCK_DIVIDER_REG_7
|
---|
| 995 | ( .data_in(data_in[3*8+7]),
|
---|
| 996 | .data_out(clock_divider[7]),
|
---|
| 997 | .we(we_clock_divider_hi),
|
---|
| 998 | .clk(clk),
|
---|
| 999 | .rst(rst)
|
---|
| 1000 | );
|
---|
| 1001 |
|
---|
| 1002 | assign clock_divider[6:4] = 3'h0;
|
---|
| 1003 |
|
---|
| 1004 | can_register_asyn #(1, 1'h0) CLOCK_DIVIDER_REG_3
|
---|
| 1005 | ( .data_in(data_in[3*8+3]),
|
---|
| 1006 | .data_out(clock_divider[3]),
|
---|
| 1007 | .we(we_clock_divider_hi),
|
---|
| 1008 | .clk(clk),
|
---|
| 1009 | .rst(rst)
|
---|
| 1010 | );
|
---|
| 1011 |
|
---|
| 1012 | can_register_asyn #(3, 3'h0) CLOCK_DIVIDER_REG_LOW
|
---|
| 1013 | ( .data_in(data_in[3*8+2:3*8]),
|
---|
| 1014 | .data_out(clock_divider[2:0]),
|
---|
| 1015 | .we(we_clock_divider_low),
|
---|
| 1016 | .clk(clk),
|
---|
| 1017 | .rst(rst)
|
---|
| 1018 | );
|
---|
| 1019 |
|
---|
| 1020 | assign extended_mode = clock_divider[7];
|
---|
| 1021 | assign clock_off = clock_divider[3];
|
---|
| 1022 | assign cd[2:0] = clock_divider[2:0];
|
---|
| 1023 |
|
---|
| 1024 |
|
---|
| 1025 |
|
---|
| 1026 | always @ (cd)
|
---|
| 1027 | begin
|
---|
| 1028 | case (cd) /* synthesis full_case parallel_case */
|
---|
| 1029 | 3'b000 : clkout_div = 3'd0;
|
---|
| 1030 | 3'b001 : clkout_div = 3'd1;
|
---|
| 1031 | 3'b010 : clkout_div = 3'd2;
|
---|
| 1032 | 3'b011 : clkout_div = 3'd3;
|
---|
| 1033 | 3'b100 : clkout_div = 3'd4;
|
---|
| 1034 | 3'b101 : clkout_div = 3'd5;
|
---|
| 1035 | 3'b110 : clkout_div = 3'd6;
|
---|
| 1036 | 3'b111 : clkout_div = 3'd0;
|
---|
| 1037 | endcase
|
---|
| 1038 | end
|
---|
| 1039 |
|
---|
| 1040 |
|
---|
| 1041 |
|
---|
| 1042 | always @ (posedge clk or posedge rst)
|
---|
| 1043 | begin
|
---|
| 1044 | if (rst)
|
---|
| 1045 | clkout_cnt <= 3'h0;
|
---|
| 1046 | else if (clkout_cnt == clkout_div)
|
---|
| 1047 | clkout_cnt <=#Tp 3'h0;
|
---|
| 1048 | else
|
---|
| 1049 | clkout_cnt <= clkout_cnt + 1'b1;
|
---|
| 1050 | end
|
---|
| 1051 |
|
---|
| 1052 |
|
---|
| 1053 |
|
---|
| 1054 | always @ (posedge clk or posedge rst)
|
---|
| 1055 | begin
|
---|
| 1056 | if (rst)
|
---|
| 1057 | clkout_tmp <= 1'b0;
|
---|
| 1058 | else if (clkout_cnt == clkout_div)
|
---|
| 1059 | clkout_tmp <=#Tp ~clkout_tmp;
|
---|
| 1060 | end
|
---|
| 1061 |
|
---|
| 1062 |
|
---|
| 1063 | assign clkout = clock_off ? 1'b1 : ((&cd)? clk : clkout_tmp);
|
---|
| 1064 |
|
---|
| 1065 |
|
---|
| 1066 |
|
---|
| 1067 | /* End Clock Divider register */
|
---|
| 1068 |
|
---|
| 1069 |
|
---|
| 1070 |
|
---|
| 1071 |
|
---|
| 1072 | /* This section is for BASIC and EXTENDED mode */
|
---|
| 1073 |
|
---|
| 1074 | /* Acceptance code register */
|
---|
| 1075 | can_register_asyn #(8, 8'h0) ACCEPTANCE_CODE_REG0
|
---|
| 1076 | ( .data_in(data_in[3*8+7:3*8]),
|
---|
| 1077 | .data_out(acceptance_code_0),
|
---|
| 1078 | .we(we_acceptance_code_0),
|
---|
| 1079 | .clk(clk),
|
---|
| 1080 | .rst(rst)
|
---|
| 1081 | );
|
---|
| 1082 | /* End: Acceptance code register */
|
---|
| 1083 |
|
---|
| 1084 |
|
---|
| 1085 | /* Acceptance mask register */
|
---|
| 1086 | can_register_asyn #(8, 8'h0) ACCEPTANCE_MASK_REG0
|
---|
| 1087 | ( .data_in(data_in[3*8+7:3*8]),
|
---|
| 1088 | .data_out(acceptance_mask_0),
|
---|
| 1089 | .we(we_acceptance_mask_0),
|
---|
| 1090 | .clk(clk),
|
---|
| 1091 | .rst(rst)
|
---|
| 1092 | );
|
---|
| 1093 | /* End: Acceptance mask register */
|
---|
| 1094 |
|
---|
| 1095 |
|
---|
| 1096 | /* Data window register */
|
---|
| 1097 | wire [RXMBOX_DEPTH-1:0] rxdatawin;
|
---|
| 1098 | //wire [4:0] rxdatawin;
|
---|
| 1099 | can_register_asyn #((RXMBOX_DEPTH), {(RXMBOX_DEPTH){1'h0}}) MODE_RXDATAWIN_REG
|
---|
| 1100 | //can_register_asyn #(5, 5'h0) MODE_RXDATAWIN_REG
|
---|
| 1101 | ( .data_in(data_in[(RXMBOX_DEPTH-1+16):16]),
|
---|
| 1102 | .data_out(rxdatawin),
|
---|
| 1103 | .we(we_datawin),
|
---|
| 1104 | .clk(clk),
|
---|
| 1105 | .rst(rst)
|
---|
| 1106 | );
|
---|
| 1107 | /* End: Data window register */
|
---|
| 1108 | /* End: This section is for BASIC and EXTENDED mode */
|
---|
| 1109 |
|
---|
| 1110 |
|
---|
| 1111 | /* Tx data register. */
|
---|
| 1112 | //parameter t = 16;
|
---|
| 1113 | wire [(TXMBOX_BITS)*4-1:0] we_txdata;
|
---|
| 1114 | wire [(TXMBOX_BITS)*128-1:0] txdata_reg;
|
---|
| 1115 | wire [(TXMBOX_BITS)*29+28:0] txdata_reg_id;
|
---|
| 1116 | reg [(TXMBOX_BITS)*34-1:0] txdata_ff;
|
---|
| 1117 | //wire [63:0] we_txdata;
|
---|
| 1118 | //wire [2047:0] txdata_reg;
|
---|
| 1119 | //wire [16*29+28:0] txdata_reg_id;
|
---|
| 1120 | //reg [16*34-1:0] txdata_ff;
|
---|
| 1121 | reg [ 8*34-1:0] rank_lvl1;
|
---|
| 1122 | reg [ 4*34-1:0] rank_lvl2;
|
---|
| 1123 | reg [ 2*34-1:0] rank_lvl3;
|
---|
| 1124 | wire [63:0] mboxnum;
|
---|
| 1125 |
|
---|
| 1126 | reg aleb1[7:0];
|
---|
| 1127 | reg aleb2[3:0];
|
---|
| 1128 | reg aleb3[1:0];
|
---|
| 1129 | reg aleb4;
|
---|
| 1130 |
|
---|
| 1131 | assign mboxnum = 64'hfedcba9876543210;
|
---|
| 1132 | generate
|
---|
| 1133 | genvar i,j;
|
---|
| 1134 | for (i=0; i<16; i=i+1) begin :txdata_i_reg
|
---|
| 1135 | for (j=0; j<4; j=j+1) begin :txdata_j_reg
|
---|
| 1136 | if (i < TXMBOX_BITS) begin
|
---|
| 1137 | assign we_txdata[i*4+j] = cs & we & ~txreq[i] & (addr[9:8] == 2'h1) & (addr[7:4] == i) & (addr[3:0] == (4'h4*j));
|
---|
| 1138 | can_register_asyn #(32, 32'h0) TXDATA_REG( .data_in(data_in), .data_out(txdata_reg[i*128+j*32+31:i*128+j*32]), .we(we_txdata[i*4+j]), .clk(clk), .rst(rst));
|
---|
| 1139 | end //for
|
---|
| 1140 | end //for
|
---|
| 1141 |
|
---|
| 1142 | if (i < TXMBOX_BITS) begin
|
---|
| 1143 | assign txdata[i] = txdata_reg[i*128+127:i*128];
|
---|
| 1144 |
|
---|
| 1145 | // arbiter
|
---|
| 1146 | assign txdata_reg_id[i*29+28:i*29] = (extended_mode & txdata_reg[i*128+31])? txdata_reg[i*128+28:i*128]: {txdata_reg[i*128+28:i*128+18],18'h0};
|
---|
| 1147 |
|
---|
| 1148 | always @ (posedge clk or posedge rst) begin
|
---|
| 1149 | if (rst) begin
|
---|
| 1150 | txdata_ff[i*34+33:i*34] <= 34'h0;
|
---|
| 1151 | end else if (~reset_mode & (state == st_idle) & |(txreq & ~txabort)) begin
|
---|
| 1152 | txdata_ff[i*34+33:i*34] <=#Tp {txreq[i] & ~txabort[i] , mboxnum[i*4+3:i*4] , txdata_reg_id[i*29+28:i*29]};
|
---|
| 1153 | end
|
---|
| 1154 | end
|
---|
| 1155 | end
|
---|
| 1156 |
|
---|
| 1157 | if(i<8) begin
|
---|
| 1158 | always @ (posedge clk) begin
|
---|
| 1159 | if (i >= (TXMBOX_BITS-1)) begin
|
---|
| 1160 | aleb1[i] <= 0;
|
---|
| 1161 | end else begin
|
---|
| 1162 | aleb1[i] <= (txdata_ff[2*i*34+28:2*i*34]<=txdata_ff[(2*i+1)*34+28:(2*i+1)*34]);
|
---|
| 1163 | end
|
---|
| 1164 | end
|
---|
| 1165 |
|
---|
| 1166 | always @ (posedge clk or posedge rst) begin
|
---|
| 1167 | if (i >= (TXMBOX_BITS-1)) begin
|
---|
| 1168 | rank_lvl1[i*34+33:i*34] <= #Tp 0;
|
---|
| 1169 | end else begin
|
---|
| 1170 | case({txdata_ff[(2*i+1)*34+33],txdata_ff[2*i*34+33]})
|
---|
| 1171 | 2'h0: rank_lvl1[i*34+33:i*34] <=#Tp txdata_ff[2*i*34+33:2*i*34];
|
---|
| 1172 | 2'h1: rank_lvl1[i*34+33:i*34] <=#Tp txdata_ff[2*i*34+33:2*i*34];
|
---|
| 1173 | 2'h2: rank_lvl1[i*34+33:i*34] <=#Tp txdata_ff[(2*i+1)*34+33:(2*i+1)*34];
|
---|
| 1174 | 2'h3: rank_lvl1[i*34+33:i*34] <=#Tp (aleb1[i])? txdata_ff[2*i*34+33:2*i*34]: txdata_ff[(2*i+1)*34+33:(2*i+1)*34];
|
---|
| 1175 | //(txdata_ff[2*i*34+28:2*i*34]<=txdata_ff[(2*i+1)*34+28:(2*i+1)*34])? txdata_ff[2*i*34+33:2*i*34]: txdata_ff[(2*i+1)*34+33:(2*i+1)*34];
|
---|
| 1176 | endcase
|
---|
| 1177 | end
|
---|
| 1178 | end
|
---|
| 1179 | end
|
---|
| 1180 |
|
---|
| 1181 | if(i<4) begin
|
---|
| 1182 | always @ (posedge clk) begin
|
---|
| 1183 | if (i >= (TXMBOX_BITS-1)) begin
|
---|
| 1184 | aleb2[i] <= 0;
|
---|
| 1185 | end else begin
|
---|
| 1186 | aleb2[i] <= (rank_lvl1[2*i*34+28:2*i*34]<=rank_lvl1[(2*i+1)*34+28:(2*i+1)*34]);
|
---|
| 1187 | end
|
---|
| 1188 | end
|
---|
| 1189 |
|
---|
| 1190 | always @ (posedge clk) begin
|
---|
| 1191 | if (i >= (TXMBOX_BITS-1)) begin
|
---|
| 1192 | rank_lvl2[i*34+33:i*34] <= #Tp 0;
|
---|
| 1193 | end else begin
|
---|
| 1194 | case({rank_lvl1[(2*i+1)*34+33],rank_lvl1[2*i*34+33]})
|
---|
| 1195 | 2'h0: rank_lvl2[i*34+33:i*34] <=#Tp rank_lvl1[2*i*34+33:2*i*34];
|
---|
| 1196 | 2'h1: rank_lvl2[i*34+33:i*34] <=#Tp rank_lvl1[2*i*34+33:2*i*34];
|
---|
| 1197 | 2'h2: rank_lvl2[i*34+33:i*34] <=#Tp rank_lvl1[(2*i+1)*34+33:(2*i+1)*34];
|
---|
| 1198 | 2'h3: rank_lvl2[i*34+33:i*34] <=#Tp (aleb2[i])? rank_lvl1[2*i*34+33:2*i*34]: rank_lvl1[(2*i+1)*34+33:(2*i+1)*34];//rank_lvl1[(2*i+1)*34+33:(2*i+1)*34];
|
---|
| 1199 | endcase
|
---|
| 1200 | end
|
---|
| 1201 | end
|
---|
| 1202 | end
|
---|
| 1203 |
|
---|
| 1204 | if(i<2) begin
|
---|
| 1205 | always @ (posedge clk or posedge rst) begin
|
---|
| 1206 | if (i >= (TXMBOX_BITS-1)) begin
|
---|
| 1207 | aleb3[i] <= 0;
|
---|
| 1208 | end else begin
|
---|
| 1209 | aleb3[i] <= (rank_lvl2[2*i*34+28:2*i*34]<=rank_lvl2[(2*i+1)*34+28:(2*i+1)*34]);
|
---|
| 1210 | end
|
---|
| 1211 | end
|
---|
| 1212 |
|
---|
| 1213 | always @ (posedge clk or posedge rst) begin
|
---|
| 1214 | if (i >= (TXMBOX_BITS-1)) begin
|
---|
| 1215 | rank_lvl3[i*34+33:i*34] <= #Tp 0;
|
---|
| 1216 | end else begin
|
---|
| 1217 | case({rank_lvl2[(2*i+1)*34+33],rank_lvl2[2*i*34+33]})
|
---|
| 1218 | 2'h0: rank_lvl3[i*34+33:i*34] <=#Tp rank_lvl2[2*i*34+33:2*i*34];
|
---|
| 1219 | 2'h1: rank_lvl3[i*34+33:i*34] <=#Tp rank_lvl2[2*i*34+33:2*i*34];
|
---|
| 1220 | 2'h2: rank_lvl3[i*34+33:i*34] <=#Tp rank_lvl2[(2*i+1)*34+33:(2*i+1)*34];
|
---|
| 1221 | 2'h3: rank_lvl3[i*34+33:i*34] <=#Tp (aleb3[i])? rank_lvl2[2*i*34+33:2*i*34]: rank_lvl2[(2*i+1)*34+33:(2*i+1)*34];//rank_lvl2[(2*i+1)*34+33:(2*i+1)*34];
|
---|
| 1222 | //(rank_lvl2[2*i*34+28:2*i*34]<=rank_lvl2[(2*i+1)*34+28:(2*i+1)*34])? rank_lvl2[2*i*34+33:2*i*34]: rank_lvl2[(2*i+1)*34+33:(2*i+1)*34];
|
---|
| 1223 | endcase
|
---|
| 1224 | end
|
---|
| 1225 | end
|
---|
| 1226 | end
|
---|
| 1227 |
|
---|
| 1228 | if(i<1) begin
|
---|
| 1229 | always @ (posedge clk or posedge rst) begin
|
---|
| 1230 | if (i >= (TXMBOX_BITS-1)) begin
|
---|
| 1231 | aleb4 <= 0;
|
---|
| 1232 | end else begin
|
---|
| 1233 | aleb4 <= (rank_lvl3[2*i*34+28:2*i*34]<=rank_lvl3[(2*i+1)*34+28:(2*i+1)*34]);
|
---|
| 1234 | end
|
---|
| 1235 | end
|
---|
| 1236 |
|
---|
| 1237 | always @ (posedge clk or posedge rst) begin
|
---|
| 1238 | case({rank_lvl3[(2*i+1)*34+33],rank_lvl3[2*i*34+33]})
|
---|
| 1239 | 2'h0: txmsgbox <=#Tp rank_lvl3[2*i*34+32:2*i*34+29];
|
---|
| 1240 | 2'h1: txmsgbox <=#Tp rank_lvl3[2*i*34+32:2*i*34+29];
|
---|
| 1241 | 2'h2: txmsgbox <=#Tp rank_lvl3[(2*i+1)*34+32:(2*i+1)*34+29];
|
---|
| 1242 | 2'h3: txmsgbox <=#Tp (aleb4)? rank_lvl3[2*i*34+32:2*i*34+29]: rank_lvl3[(2*i+1)*34+32:(2*i+1)*34+29];//rank_lvl3[(2*i+1)*34+32:(2*i+1)*34+29];
|
---|
| 1243 | //(rank_lvl3[2*i*34+28:2*i*34]<=rank_lvl3[(2*i+1)*34+28:(2*i+1)*34])? rank_lvl3[2*i*34+32:2*i*34+29]: rank_lvl3[(2*i+1)*34+32:(2*i+1)*34+29];
|
---|
| 1244 | endcase
|
---|
| 1245 | end
|
---|
| 1246 | end
|
---|
| 1247 |
|
---|
| 1248 | end //for
|
---|
| 1249 | endgenerate
|
---|
| 1250 |
|
---|
| 1251 |
|
---|
| 1252 |
|
---|
| 1253 | //generate
|
---|
| 1254 | // genvar i,j;
|
---|
| 1255 | // for (i=0; i<16; i=i+1) begin :txdata_i_reg
|
---|
| 1256 | // for (j=0; j<4; j=j+1) begin :txdata_j_reg
|
---|
| 1257 | // assign we_txdata[i*4+j] = cs & we & ~txreq[i] & (addr[9:8] == 2'h1) & (addr[7:4] == i) & (addr[3:0] == (4'h4*j));
|
---|
| 1258 | // can_register_asyn #(32, 32'h0) TXDATA_REG( .data_in(data_in), .data_out(txdata_reg[i*128+j*32+31:i*128+j*32]), .we(we_txdata[i*4+j]), .clk(clk), .rst(rst));
|
---|
| 1259 | // end //for
|
---|
| 1260 | // assign txdata[i] = txdata_reg[i*128+127:i*128];
|
---|
| 1261 | //
|
---|
| 1262 | //
|
---|
| 1263 | //
|
---|
| 1264 | // // arbiter
|
---|
| 1265 | // assign txdata_reg_id[i*29+28:i*29] = (extended_mode & txdata_reg[i*128+31])? txdata_reg[i*128+28:i*128]: {txdata_reg[i*128+28:i*128+18],18'h0};
|
---|
| 1266 | //
|
---|
| 1267 | // always @ (posedge clk or posedge rst)
|
---|
| 1268 | // begin
|
---|
| 1269 | // if (rst)
|
---|
| 1270 | // txdata_ff[i*34+33:i*34] <= 34'h0;
|
---|
| 1271 | // else if (~reset_mode & (state == st_idle) & |(txreq & ~txabort))
|
---|
| 1272 | // txdata_ff[i*34+33:i*34] <=#Tp {txreq[i] & ~txabort[i] , mboxnum[i*4+3:i*4] , txdata_reg_id[i*29+28:i*29]};
|
---|
| 1273 | // end
|
---|
| 1274 | //
|
---|
| 1275 | // if(i<8)begin
|
---|
| 1276 | //
|
---|
| 1277 | //
|
---|
| 1278 | //always @ (posedge clk) aleb1[i] <= (txdata_ff[2*i*34+28:2*i*34]<=txdata_ff[(2*i+1)*34+28:(2*i+1)*34]);
|
---|
| 1279 | //
|
---|
| 1280 | // begin
|
---|
| 1281 | // always @ (posedge clk or posedge rst)
|
---|
| 1282 | // begin
|
---|
| 1283 | // case({txdata_ff[(2*i+1)*34+33],txdata_ff[2*i*34+33]})
|
---|
| 1284 | // 2'h0: rank_lvl1[i*34+33:i*34] <=#Tp txdata_ff[2*i*34+33:2*i*34];
|
---|
| 1285 | // 2'h1: rank_lvl1[i*34+33:i*34] <=#Tp txdata_ff[2*i*34+33:2*i*34];
|
---|
| 1286 | // 2'h2: rank_lvl1[i*34+33:i*34] <=#Tp txdata_ff[(2*i+1)*34+33:(2*i+1)*34];
|
---|
| 1287 | // 2'h3: rank_lvl1[i*34+33:i*34] <=#Tp (aleb1[i])? txdata_ff[2*i*34+33:2*i*34]: txdata_ff[(2*i+1)*34+33:(2*i+1)*34];
|
---|
| 1288 | // //(txdata_ff[2*i*34+28:2*i*34]<=txdata_ff[(2*i+1)*34+28:(2*i+1)*34])? txdata_ff[2*i*34+33:2*i*34]: txdata_ff[(2*i+1)*34+33:(2*i+1)*34];
|
---|
| 1289 | // endcase
|
---|
| 1290 | // end
|
---|
| 1291 | // end
|
---|
| 1292 | //end
|
---|
| 1293 | // if(i<4)begin
|
---|
| 1294 | //
|
---|
| 1295 | //always @ (posedge clk) aleb2[i] <= (rank_lvl1[2*i*34+28:2*i*34]<=rank_lvl1[(2*i+1)*34+28:(2*i+1)*34]);
|
---|
| 1296 | //
|
---|
| 1297 | // begin
|
---|
| 1298 | // always @ (posedge clk or posedge rst)
|
---|
| 1299 | // begin
|
---|
| 1300 | // case({rank_lvl1[(2*i+1)*34+33],rank_lvl1[2*i*34+33]})
|
---|
| 1301 | // 2'h0: rank_lvl2[i*34+33:i*34] <=#Tp rank_lvl1[2*i*34+33:2*i*34];
|
---|
| 1302 | // 2'h1: rank_lvl2[i*34+33:i*34] <=#Tp rank_lvl1[2*i*34+33:2*i*34];
|
---|
| 1303 | // 2'h2: rank_lvl2[i*34+33:i*34] <=#Tp rank_lvl1[(2*i+1)*34+33:(2*i+1)*34];
|
---|
| 1304 | // 2'h3: rank_lvl2[i*34+33:i*34] <=#Tp (aleb2[i])? rank_lvl1[2*i*34+33:2*i*34]: rank_lvl1[(2*i+1)*34+33:(2*i+1)*34];//rank_lvl1[(2*i+1)*34+33:(2*i+1)*34];
|
---|
| 1305 | // //(rank_lvl1[2*i*34+28:2*i*34]<=rank_lvl1[(2*i+1)*34+28:(2*i+1)*34])? rank_lvl1[2*i*34+33:2*i*34]: rank_lvl1[(2*i+1)*34+33:(2*i+1)*34];
|
---|
| 1306 | // endcase
|
---|
| 1307 | // end
|
---|
| 1308 | // end
|
---|
| 1309 | //end
|
---|
| 1310 | // if(i<2)
|
---|
| 1311 | // begin
|
---|
| 1312 | //
|
---|
| 1313 | //always @ (posedge clk) aleb3[i] <= (rank_lvl2[2*i*34+28:2*i*34]<=rank_lvl2[(2*i+1)*34+28:(2*i+1)*34]);
|
---|
| 1314 | //
|
---|
| 1315 | //
|
---|
| 1316 | // always @ (posedge clk or posedge rst)
|
---|
| 1317 | // begin
|
---|
| 1318 | // case({rank_lvl2[(2*i+1)*34+33],rank_lvl2[2*i*34+33]})
|
---|
| 1319 | // 2'h0: rank_lvl3[i*34+33:i*34] <=#Tp rank_lvl2[2*i*34+33:2*i*34];
|
---|
| 1320 | // 2'h1: rank_lvl3[i*34+33:i*34] <=#Tp rank_lvl2[2*i*34+33:2*i*34];
|
---|
| 1321 | // 2'h2: rank_lvl3[i*34+33:i*34] <=#Tp rank_lvl2[(2*i+1)*34+33:(2*i+1)*34];
|
---|
| 1322 | // 2'h3: rank_lvl3[i*34+33:i*34] <=#Tp (aleb3[i])? rank_lvl2[2*i*34+33:2*i*34]: rank_lvl2[(2*i+1)*34+33:(2*i+1)*34];//rank_lvl2[(2*i+1)*34+33:(2*i+1)*34];
|
---|
| 1323 | // //(rank_lvl2[2*i*34+28:2*i*34]<=rank_lvl2[(2*i+1)*34+28:(2*i+1)*34])? rank_lvl2[2*i*34+33:2*i*34]: rank_lvl2[(2*i+1)*34+33:(2*i+1)*34];
|
---|
| 1324 | // endcase
|
---|
| 1325 | // end
|
---|
| 1326 | // end
|
---|
| 1327 | //
|
---|
| 1328 | //
|
---|
| 1329 | // if(i<1)
|
---|
| 1330 | // begin
|
---|
| 1331 | //
|
---|
| 1332 | //always @ (posedge clk) aleb4 <= (rank_lvl3[2*i*34+28:2*i*34]<=rank_lvl3[(2*i+1)*34+28:(2*i+1)*34]);
|
---|
| 1333 | //
|
---|
| 1334 | //
|
---|
| 1335 | // always @ (posedge clk or posedge rst)
|
---|
| 1336 | // begin
|
---|
| 1337 | // case({rank_lvl3[(2*i+1)*34+33],rank_lvl3[2*i*34+33]})
|
---|
| 1338 | // 2'h0: txmsgbox <=#Tp rank_lvl3[2*i*34+32:2*i*34+29];
|
---|
| 1339 | // 2'h1: txmsgbox <=#Tp rank_lvl3[2*i*34+32:2*i*34+29];
|
---|
| 1340 | // 2'h2: txmsgbox <=#Tp rank_lvl3[(2*i+1)*34+32:(2*i+1)*34+29];
|
---|
| 1341 | // 2'h3: txmsgbox <=#Tp (aleb4)? rank_lvl3[2*i*34+32:2*i*34+29]: rank_lvl3[(2*i+1)*34+32:(2*i+1)*34+29];//rank_lvl3[(2*i+1)*34+32:(2*i+1)*34+29];
|
---|
| 1342 | // //(rank_lvl3[2*i*34+28:2*i*34]<=rank_lvl3[(2*i+1)*34+28:(2*i+1)*34])? rank_lvl3[2*i*34+32:2*i*34+29]: rank_lvl3[(2*i+1)*34+32:(2*i+1)*34+29];
|
---|
| 1343 | // endcase
|
---|
| 1344 | // end
|
---|
| 1345 | // end
|
---|
| 1346 | //
|
---|
| 1347 | //
|
---|
| 1348 | // end //for
|
---|
| 1349 | //endgenerate
|
---|
| 1350 | ///* End: Tx data register. */
|
---|
| 1351 |
|
---|
| 1352 |
|
---|
| 1353 | /* Rx data register. */
|
---|
| 1354 | //parameter r = 32;
|
---|
| 1355 | wire [RXMBOX_BITS-1:0] rx_we_ff;
|
---|
| 1356 | wire [127:0] rxdata [0:RXMBOX_BITS-1];
|
---|
| 1357 | //wire [31:0] rx_we_ff;
|
---|
| 1358 | //wire [127:0] rxdata [0:31];
|
---|
| 1359 | wire [31:0] we_rxcode;
|
---|
| 1360 | wire [31:0] we_rxmask;
|
---|
| 1361 | wire [31:0] rxmask [0:RXMBOX_BITS-1];
|
---|
| 1362 | wire [31:0] rxcode [0:RXMBOX_BITS-1];
|
---|
| 1363 | //wire [31:0] rxmask [0:31];
|
---|
| 1364 | //wire [31:0] rxcode [0:31];
|
---|
| 1365 | wire [1023:0] rxmask_in; // XXX
|
---|
| 1366 | wire [1023:0] rxcode_in; // XXX
|
---|
| 1367 | generate
|
---|
| 1368 | genvar k;
|
---|
| 1369 | for (k=0; k<RXMBOX_BITS; k=k+1) begin :rxdata_reg
|
---|
| 1370 | // for (k=0; k<32; k=k+1) begin :rxdata_reg
|
---|
| 1371 | // can_register_asyn #(128, 128'h0) RXWRDATA_REG0( .data_in(rx_dt_ff), .data_out(rxdata[k]), .we(rx_we_ff[k]), .clk(clk), .rst(rst));
|
---|
| 1372 |
|
---|
| 1373 | assign we_rxcode[k] = cs & we & (addr == 10'h070) & (rxdatawin == k) & reset_mode;
|
---|
| 1374 | assign we_rxmask[k] = cs & we & (addr == 10'h074) & (rxdatawin == k) & reset_mode;
|
---|
| 1375 |
|
---|
| 1376 | can_register_asyn #(32, 32'h0) RXWRDATA_REG2( .data_in(data_in), .data_out(rxcode[k]), .we(we_rxcode[k]), .clk(clk), .rst(rst));
|
---|
| 1377 | can_register_asyn #(32, 32'h0) RXWRDATA_REG3( .data_in(data_in), .data_out(rxmask[k]), .we(we_rxmask[k]), .clk(clk), .rst(rst));
|
---|
| 1378 |
|
---|
| 1379 | assign rxmask_in[32*k+31:32*k] = rxmask[k];
|
---|
| 1380 | assign rxcode_in[32*k+31:32*k] = rxcode[k];
|
---|
| 1381 |
|
---|
| 1382 | end //for
|
---|
| 1383 | endgenerate
|
---|
| 1384 |
|
---|
| 1385 | wire [127:0] rxmsgdata;
|
---|
| 1386 | //can_rxmboxacf can_rxmboxacf(
|
---|
| 1387 | can_rxmboxacf #(.TXMBOX_DEPTH(TXMBOX_DEPTH), .RXMBOX_DEPTH(RXMBOX_DEPTH)) can_rxmboxacf(
|
---|
| 1388 | .clk(clk),
|
---|
| 1389 | .rst(rst),
|
---|
| 1390 | .sample_point(sample_point),
|
---|
| 1391 | .rxwait(rxwait),
|
---|
| 1392 | .rxcmp(rxcmp),
|
---|
| 1393 | .reset_mode(reset_mode),
|
---|
| 1394 | .acceptance_filter_mode(acceptance_filter_mode),
|
---|
| 1395 | .extended_mode(extended_mode),
|
---|
| 1396 | .rxcode(rxcode_in),
|
---|
| 1397 | .rxmask(rxmask_in),
|
---|
| 1398 | .rxdatawin(addr[(RXMBOX_DEPTH-1+4):4]),
|
---|
| 1399 | // .rxdatawin(addr[8:4]),
|
---|
| 1400 | .rx_dt(rx_dt),
|
---|
| 1401 | .rx_we(rx_we),
|
---|
| 1402 | .rxmsgdata(rxmsgdata),
|
---|
| 1403 | .rx_we_ff(rx_we_ff)
|
---|
| 1404 | );
|
---|
| 1405 | /* End: Rx data register. */
|
---|
| 1406 |
|
---|
| 1407 |
|
---|
| 1408 | /* Tx controll register. */
|
---|
| 1409 | generate
|
---|
| 1410 | genvar a;
|
---|
| 1411 | for (a=0; a<TXMBOX_BITS; a=a+1) begin :txsts_reg
|
---|
| 1412 | // for (a=0; a<16; a=a+1) begin :txsts_reg
|
---|
| 1413 |
|
---|
| 1414 |
|
---|
| 1415 | always @ (posedge clk or posedge rst)
|
---|
| 1416 | begin
|
---|
| 1417 | if (rst)
|
---|
| 1418 | txreq[a] <= 1'h0;
|
---|
| 1419 | else if (reset_mode)
|
---|
| 1420 | txreq[a] <=#Tp 1'h0;
|
---|
| 1421 | else if (we_txreq & data_in[a] & ~txreq[a])
|
---|
| 1422 | txreq[a] <=#Tp 1'h1;
|
---|
| 1423 | else if ((state == st_wait) & (txmsgbox == a) & tx_successful & (~tx_successful_q))
|
---|
| 1424 | txreq[a] <=#Tp 1'h0;
|
---|
| 1425 | else if (txabort[a])
|
---|
| 1426 | case(state)
|
---|
| 1427 | st_idle : txreq[a] <=#Tp 1'h0;
|
---|
| 1428 | st_sel : txreq[a] <=#Tp txreq[a];
|
---|
| 1429 | default : if (txmsgbox != a) txreq[a] <=#Tp 1'h0;
|
---|
| 1430 | endcase
|
---|
| 1431 | end
|
---|
| 1432 |
|
---|
| 1433 |
|
---|
| 1434 | always @ (posedge clk or posedge rst)
|
---|
| 1435 | begin
|
---|
| 1436 | if (rst)
|
---|
| 1437 | txabort[a] <= 1'h0;
|
---|
| 1438 | else if (reset_mode)
|
---|
| 1439 | txabort[a] <=#Tp 1'h0;
|
---|
| 1440 | else if (~txreq[a])
|
---|
| 1441 | txabort[a] <=#Tp 1'h0;
|
---|
| 1442 | else if (we_txabort & data_in[a] & txreq[a])
|
---|
| 1443 | txabort[a] <=#Tp 1'h1;
|
---|
| 1444 | end
|
---|
| 1445 |
|
---|
| 1446 |
|
---|
| 1447 | always @ (posedge clk or posedge rst)
|
---|
| 1448 | begin
|
---|
| 1449 | if (rst)
|
---|
| 1450 | transmit_cancel[a] <= 1'h0;
|
---|
| 1451 | else if (txreq[a] & txabort[a])
|
---|
| 1452 | case(state)
|
---|
| 1453 | st_idle : transmit_cancel[a] <=#Tp 1'h1;
|
---|
| 1454 | st_sel : transmit_cancel[a] <=#Tp transmit_cancel[a];
|
---|
| 1455 | default : if (txmsgbox != a) transmit_cancel[a] <=#Tp 1'h1;
|
---|
| 1456 | endcase
|
---|
| 1457 | else if (we_txcancel & data_in[a])
|
---|
| 1458 | transmit_cancel[a] <=#Tp 1'h0;
|
---|
| 1459 | end
|
---|
| 1460 |
|
---|
| 1461 |
|
---|
| 1462 | always @ (posedge clk or posedge rst)
|
---|
| 1463 | begin
|
---|
| 1464 | if (rst)
|
---|
| 1465 | txcmp[a] <= 1'h0;
|
---|
| 1466 | else if ((state == st_wait) & (txmsgbox == a) & tx_successful & (~tx_successful_q))
|
---|
| 1467 | txcmp[a] <=#Tp 1'h1;
|
---|
| 1468 | else if (we_txcmp & data_in[a])
|
---|
| 1469 | txcmp[a] <=#Tp 1'h0;
|
---|
| 1470 | end
|
---|
| 1471 |
|
---|
| 1472 |
|
---|
| 1473 | always @ (posedge clk or posedge rst)
|
---|
| 1474 | begin
|
---|
| 1475 | if (rst)
|
---|
| 1476 | rxselfreq[a] <= 1'h0;
|
---|
| 1477 | else if (we_rxselfreq)
|
---|
| 1478 | rxselfreq[a] <=#Tp data_in[a];
|
---|
| 1479 | end
|
---|
| 1480 |
|
---|
| 1481 |
|
---|
| 1482 | end //for
|
---|
| 1483 | endgenerate
|
---|
| 1484 | /* End: Tx controll register. */
|
---|
| 1485 |
|
---|
| 1486 |
|
---|
| 1487 | /* Rx controll register. */
|
---|
| 1488 | generate
|
---|
| 1489 | genvar b;
|
---|
| 1490 | for (b=0; b<RXMBOX_BITS; b=b+1) begin :rxsts_reg
|
---|
| 1491 | // for (b=0; b<32; b=b+1) begin :rxsts_reg
|
---|
| 1492 |
|
---|
| 1493 |
|
---|
| 1494 | always @ (posedge clk or posedge rst)
|
---|
| 1495 | begin
|
---|
| 1496 | if (rst)
|
---|
| 1497 | rxwait[b] <= 1'h0;
|
---|
| 1498 | else if (we_rxwait)
|
---|
| 1499 | rxwait[b] <=#Tp data_in[b];
|
---|
| 1500 | end
|
---|
| 1501 |
|
---|
| 1502 |
|
---|
| 1503 | always @ (posedge clk or posedge rst)
|
---|
| 1504 | begin
|
---|
| 1505 | if (rst)
|
---|
| 1506 | rxcmp[b] <= 1'h0;
|
---|
| 1507 | else if (rx_we_ff[b])
|
---|
| 1508 | rxcmp[b] <=#Tp 1'h1;
|
---|
| 1509 | else if (we_rxcmp & data_in[b])
|
---|
| 1510 | rxcmp[b] <=#Tp 1'h0;
|
---|
| 1511 | end
|
---|
| 1512 |
|
---|
| 1513 |
|
---|
| 1514 | always @ (posedge clk or posedge rst)
|
---|
| 1515 | begin
|
---|
| 1516 | if (rst)
|
---|
| 1517 | rxovrwrite[b] <= 1'h0;
|
---|
| 1518 | else if (rx_we_ff[b] & rxcmp[b])
|
---|
| 1519 | rxovrwrite[b] <=#Tp 1'h1;
|
---|
| 1520 | else if (read_rxovrwrite)
|
---|
| 1521 | rxovrwrite[b] <=#Tp 1'h0;
|
---|
| 1522 | end
|
---|
| 1523 |
|
---|
| 1524 |
|
---|
| 1525 | end //for
|
---|
| 1526 | endgenerate
|
---|
| 1527 | /* End: Rx controll register. */
|
---|
| 1528 |
|
---|
| 1529 |
|
---|
| 1530 | /* This section is for EXTENDED mode */
|
---|
| 1531 |
|
---|
| 1532 | /* Acceptance code register 1 */
|
---|
| 1533 | can_register_asyn #(8, 8'h0) ACCEPTANCE_CODE_REG1
|
---|
| 1534 | ( .data_in(data_in[2*8+7:2*8+0]),
|
---|
| 1535 | .data_out(acceptance_code_1),
|
---|
| 1536 | .we(we_acceptance_code_1),
|
---|
| 1537 | .clk(clk),
|
---|
| 1538 | .rst(rst)
|
---|
| 1539 | );
|
---|
| 1540 | /* End: Acceptance code register */
|
---|
| 1541 |
|
---|
| 1542 |
|
---|
| 1543 | /* Acceptance code register 2 */
|
---|
| 1544 | can_register_asyn #(8, 8'h0) ACCEPTANCE_CODE_REG2
|
---|
| 1545 | ( .data_in(data_in[1*8+7:1*8+0]),
|
---|
| 1546 | .data_out(acceptance_code_2),
|
---|
| 1547 | .we(we_acceptance_code_2),
|
---|
| 1548 | .clk(clk),
|
---|
| 1549 | .rst(rst)
|
---|
| 1550 | );
|
---|
| 1551 | /* End: Acceptance code register */
|
---|
| 1552 |
|
---|
| 1553 |
|
---|
| 1554 | /* Acceptance code register 3 */
|
---|
| 1555 | can_register_asyn #(8, 8'h0) ACCEPTANCE_CODE_REG3
|
---|
| 1556 | ( .data_in(data_in[0*8+7:0*8+0]),
|
---|
| 1557 | .data_out(acceptance_code_3),
|
---|
| 1558 | .we(we_acceptance_code_3),
|
---|
| 1559 | .clk(clk),
|
---|
| 1560 | .rst(rst)
|
---|
| 1561 | );
|
---|
| 1562 | /* End: Acceptance code register */
|
---|
| 1563 |
|
---|
| 1564 |
|
---|
| 1565 | /* Acceptance mask register 1 */
|
---|
| 1566 | can_register_asyn #(8, 8'h0) ACCEPTANCE_MASK_REG1
|
---|
| 1567 | ( .data_in(data_in[2*8+7:2*8+0]),
|
---|
| 1568 | .data_out(acceptance_mask_1),
|
---|
| 1569 | .we(we_acceptance_mask_1),
|
---|
| 1570 | .clk(clk),
|
---|
| 1571 | .rst(rst)
|
---|
| 1572 | );
|
---|
| 1573 | /* End: Acceptance code register */
|
---|
| 1574 |
|
---|
| 1575 |
|
---|
| 1576 | /* Acceptance mask register 2 */
|
---|
| 1577 | can_register_asyn #(8, 8'h0) ACCEPTANCE_MASK_REG2
|
---|
| 1578 | ( .data_in(data_in[1*8+7:1*8+0]),
|
---|
| 1579 | .data_out(acceptance_mask_2),
|
---|
| 1580 | .we(we_acceptance_mask_2),
|
---|
| 1581 | .clk(clk),
|
---|
| 1582 | .rst(rst)
|
---|
| 1583 | );
|
---|
| 1584 | /* End: Acceptance code register */
|
---|
| 1585 |
|
---|
| 1586 |
|
---|
| 1587 | /* Acceptance mask register 3 */
|
---|
| 1588 | can_register_asyn #(8, 8'h0) ACCEPTANCE_MASK_REG3
|
---|
| 1589 | ( .data_in(data_in[0*8+7:0*8+0]),
|
---|
| 1590 | .data_out(acceptance_mask_3),
|
---|
| 1591 | .we(we_acceptance_mask_3),
|
---|
| 1592 | .clk(clk),
|
---|
| 1593 | .rst(rst)
|
---|
| 1594 | );
|
---|
| 1595 | /* End: Acceptance code register */
|
---|
| 1596 |
|
---|
| 1597 |
|
---|
| 1598 | /* End: This section is for EXTENDED mode */
|
---|
| 1599 |
|
---|
| 1600 |
|
---|
| 1601 |
|
---|
| 1602 |
|
---|
| 1603 | // Selecting massage read data
|
---|
| 1604 | reg [127:0] txmsgdata;
|
---|
| 1605 | always @ (*)
|
---|
| 1606 | begin
|
---|
| 1607 | txmsgdata = txdata[addr[7:4]];
|
---|
| 1608 | end
|
---|
| 1609 |
|
---|
| 1610 | // Reading data from registers
|
---|
| 1611 | reg [31:0] data_out_reg;
|
---|
| 1612 | always @ (posedge clk or posedge rst)
|
---|
| 1613 | begin
|
---|
| 1614 | if (rst)
|
---|
| 1615 | data_out_reg <= 32'b0;
|
---|
| 1616 | else if(addr[9:8] == 2'h0)
|
---|
| 1617 | begin
|
---|
| 1618 | case(addr[7:0]) /* synthesis parallel_case */
|
---|
| 1619 | 8'h00 : data_out_reg <= {24'h0, 4'h0, mode_ext[3:1], mode[0]};
|
---|
| 1620 | 8'h04 : data_out_reg <= {16'h0, txreq};
|
---|
| 1621 | 8'h08 : data_out_reg <= {16'h0, txabort};
|
---|
| 1622 | 8'h0C : data_out_reg <= {16'h0, txcmp};
|
---|
| 1623 | 8'h10 : data_out_reg <= {16'h0, transmit_cancel};
|
---|
| 1624 | 8'h14 : data_out_reg <= rxwait;
|
---|
| 1625 | 8'h18 : data_out_reg <= rxcmp;
|
---|
| 1626 | 8'h1C : data_out_reg <= rxovrwrite;
|
---|
| 1627 | 8'h20 : data_out_reg <= {16'h0, rxselfreq};
|
---|
| 1628 | 8'h24 : data_out_reg <= {24'h0, status};
|
---|
| 1629 | 8'h28 : data_out_reg <= {24'h0, irq_reg};
|
---|
| 1630 | 8'h2C : data_out_reg <= {24'h0, irq_en_ext};
|
---|
| 1631 | 8'h30 : data_out_reg <= irq_rxen;
|
---|
| 1632 | 8'h34 : data_out_reg <= {clock_divider, 8'h0, bus_timing_1, bus_timing_0};
|
---|
| 1633 | 8'h38 : data_out_reg <= {acceptance_code_0, acceptance_code_1, acceptance_code_2, acceptance_code_3};
|
---|
| 1634 | 8'h3C : data_out_reg <= {acceptance_mask_0, acceptance_mask_1, acceptance_mask_2, acceptance_mask_3};
|
---|
| 1635 | 8'h40 : data_out_reg <= (extended_mode)? {8'h0, 4'h0, arbitration_lost_capture_mbox, 8'h0, 3'h0, arbitration_lost_capture[4:0]}: 32'h0;
|
---|
| 1636 | 8'h44 : data_out_reg <= (extended_mode)? {8'h0, 4'h0, error_capture_code_mbox, 8'h0, error_capture_code}: 32'h0;
|
---|
| 1637 | 8'h48 : data_out_reg <= {tx_err_cnt, rx_err_cnt, 8'h0, error_warning_limit};
|
---|
| 1638 | 8'h4C : data_out_reg <= {11'h0, rxdatawin, 16'h0};
|
---|
| 1639 | 8'h70 : data_out_reg <= rxcode[rxdatawin];
|
---|
| 1640 | 8'h74 : data_out_reg <= rxmask[rxdatawin];
|
---|
| 1641 | default : data_out_reg <= 32'h0; // the rest is read as 0
|
---|
| 1642 | endcase
|
---|
| 1643 | end
|
---|
| 1644 | else
|
---|
| 1645 | begin
|
---|
| 1646 | case(addr[3:2])
|
---|
| 1647 | 2'h0 : data_out_reg <= {txmsgdata[0*32+31], 2'h0, txmsgdata[0*32+28:0*32]};
|
---|
| 1648 | 2'h1 : data_out_reg <= {27'h0, txmsgdata[1*32+4:1*32]};
|
---|
| 1649 | 2'h2 : data_out_reg <= txmsgdata[2*32+31:2*32];
|
---|
| 1650 | 2'h3 : data_out_reg <= txmsgdata[3*32+31:3*32];
|
---|
| 1651 | endcase
|
---|
| 1652 | end
|
---|
| 1653 | end
|
---|
| 1654 | always @ ( * )
|
---|
| 1655 | begin
|
---|
| 1656 | if(~addr[9])
|
---|
| 1657 | data_out = data_out_reg;
|
---|
| 1658 | else
|
---|
| 1659 | case(addr[3:2])
|
---|
| 1660 | 2'h0 : data_out = {rxmsgdata[0*32+31], 2'h0, rxmsgdata[0*32+28:0*32]};
|
---|
| 1661 | 2'h1 : data_out = {27'h0, rxmsgdata[1*32+4:1*32]};
|
---|
| 1662 | 2'h2 : data_out = rxmsgdata[2*32+31:2*32];
|
---|
| 1663 | 2'h3 : data_out = rxmsgdata[3*32+31:3*32];
|
---|
| 1664 | endcase
|
---|
| 1665 | end
|
---|
| 1666 |
|
---|
| 1667 |
|
---|
| 1668 | // Some interrupts exist in basic mode and in extended mode. Since they are in different registers they need to be multiplexed.
|
---|
| 1669 | assign data_overrun_irq_en = data_overrun_irq_en_ext ;
|
---|
| 1670 | assign error_warning_irq_en = error_warning_irq_en_ext ;
|
---|
| 1671 | assign transmit_irq_en = transmit_irq_en_ext ;
|
---|
| 1672 | assign receive_irq_en = receive_irq_en_ext ;
|
---|
| 1673 |
|
---|
| 1674 |
|
---|
| 1675 | reg transmit_cancel_irq;
|
---|
| 1676 | always @ (posedge clk or posedge rst)
|
---|
| 1677 | begin
|
---|
| 1678 | if (rst)
|
---|
| 1679 | transmit_cancel_irq <= 1'b0;
|
---|
| 1680 | else if (we_txcancel)
|
---|
| 1681 | transmit_cancel_irq <=#Tp 1'b0;
|
---|
| 1682 | else if (|transmit_cancel & transmit_cancel_irq_en)
|
---|
| 1683 | transmit_cancel_irq <=#Tp 1'b1;
|
---|
| 1684 | // else if (reset_mode)
|
---|
| 1685 | else
|
---|
| 1686 | transmit_cancel_irq <=#Tp 1'b0;
|
---|
| 1687 | end
|
---|
| 1688 |
|
---|
| 1689 |
|
---|
| 1690 | reg data_overrun_irq;
|
---|
| 1691 | always @ (posedge clk or posedge rst)
|
---|
| 1692 | begin
|
---|
| 1693 | if (rst)
|
---|
| 1694 | data_overrun_irq <= 1'b0;
|
---|
| 1695 | else if (read_rxovrwrite)
|
---|
| 1696 | data_overrun_irq <=#Tp 1'b0;
|
---|
| 1697 | else if (|(rxovrwrite & irq_rxen) & data_overrun_irq_en)
|
---|
| 1698 | data_overrun_irq <=#Tp 1'b1;
|
---|
| 1699 | // else if (reset_mode)
|
---|
| 1700 | else
|
---|
| 1701 | data_overrun_irq <=#Tp 1'b0;
|
---|
| 1702 | end
|
---|
| 1703 |
|
---|
| 1704 |
|
---|
| 1705 | reg transmit_irq;
|
---|
| 1706 | always @ (posedge clk or posedge rst)
|
---|
| 1707 | begin
|
---|
| 1708 | if (rst)
|
---|
| 1709 | transmit_irq <= 1'b0;
|
---|
| 1710 | // else if (reset_mode || read_irq_reg)
|
---|
| 1711 | // transmit_irq <=#Tp 1'b0;
|
---|
| 1712 | // else if (transmit_buffer_status & (~transmit_buffer_status_q) & transmit_irq_en)
|
---|
| 1713 | // transmit_irq <=#Tp 1'b1; else if (reset_mode)
|
---|
| 1714 | else if (we_txcmp)
|
---|
| 1715 | transmit_irq <=#Tp 1'b0;
|
---|
| 1716 | else if (|txcmp & transmit_irq_en)
|
---|
| 1717 | transmit_irq <=#Tp 1'b1;
|
---|
| 1718 | else
|
---|
| 1719 | transmit_irq <=#Tp 1'b0;
|
---|
| 1720 | end
|
---|
| 1721 |
|
---|
| 1722 |
|
---|
| 1723 | reg receive_irq;
|
---|
| 1724 | always @ (posedge clk or posedge rst)
|
---|
| 1725 | begin
|
---|
| 1726 | if (rst)
|
---|
| 1727 | receive_irq <= 1'b0;
|
---|
| 1728 | else if (we_rxcmp)
|
---|
| 1729 | receive_irq <=#Tp 1'b0;
|
---|
| 1730 | else if (|(rxcmp & irq_rxen) & receive_irq_en)
|
---|
| 1731 | receive_irq <=#Tp 1'b1;
|
---|
| 1732 | // else if (reset_mode)
|
---|
| 1733 | else
|
---|
| 1734 | receive_irq <=#Tp 1'b0;
|
---|
| 1735 | end
|
---|
| 1736 |
|
---|
| 1737 |
|
---|
| 1738 | reg error_irq;
|
---|
| 1739 | always @ (posedge clk or posedge rst)
|
---|
| 1740 | begin
|
---|
| 1741 | if (rst)
|
---|
| 1742 | error_irq <= 1'b0;
|
---|
| 1743 | else if (((error_status ^ error_status_q) | (node_bus_off ^ node_bus_off_q)) & error_warning_irq_en)
|
---|
| 1744 | error_irq <=#Tp 1'b1;
|
---|
| 1745 | else if (read_irq_reg)
|
---|
| 1746 | error_irq <=#Tp 1'b0;
|
---|
| 1747 | end
|
---|
| 1748 |
|
---|
| 1749 |
|
---|
| 1750 | reg bus_error_irq;
|
---|
| 1751 | always @ (posedge clk or posedge rst)
|
---|
| 1752 | begin
|
---|
| 1753 | if (rst)
|
---|
| 1754 | bus_error_irq <= 1'b0;
|
---|
| 1755 | else if (set_bus_error_irq & bus_error_irq_en)
|
---|
| 1756 | bus_error_irq <=#Tp 1'b1;
|
---|
| 1757 | else if (reset_mode || read_irq_reg)
|
---|
| 1758 | bus_error_irq <=#Tp 1'b0;
|
---|
| 1759 | end
|
---|
| 1760 |
|
---|
| 1761 |
|
---|
| 1762 | reg arbitration_lost_irq;
|
---|
| 1763 | always @ (posedge clk or posedge rst)
|
---|
| 1764 | begin
|
---|
| 1765 | if (rst)
|
---|
| 1766 | arbitration_lost_irq <= 1'b0;
|
---|
| 1767 | else if (set_arbitration_lost_irq & arbitration_lost_irq_en)
|
---|
| 1768 | arbitration_lost_irq <=#Tp 1'b1;
|
---|
| 1769 | else if (reset_mode || read_irq_reg)
|
---|
| 1770 | arbitration_lost_irq <=#Tp 1'b0;
|
---|
| 1771 | end
|
---|
| 1772 |
|
---|
| 1773 |
|
---|
| 1774 |
|
---|
| 1775 | reg error_passive_irq;
|
---|
| 1776 | always @ (posedge clk or posedge rst)
|
---|
| 1777 | begin
|
---|
| 1778 | if (rst)
|
---|
| 1779 | error_passive_irq <= 1'b0;
|
---|
| 1780 | else if ((node_error_passive & (~node_error_passive_q) | (~node_error_passive) & node_error_passive_q & node_error_active) & error_passive_irq_en)
|
---|
| 1781 | error_passive_irq <=#Tp 1'b1;
|
---|
| 1782 | else if (reset_mode || read_irq_reg)
|
---|
| 1783 | error_passive_irq <=#Tp 1'b0;
|
---|
| 1784 | end
|
---|
| 1785 |
|
---|
| 1786 |
|
---|
| 1787 |
|
---|
| 1788 | assign irq_reg = {bus_error_irq, arbitration_lost_irq, error_passive_irq, transmit_cancel_irq, data_overrun_irq, error_irq, transmit_irq, receive_irq};
|
---|
| 1789 |
|
---|
| 1790 | assign irq = data_overrun_irq | transmit_irq | receive_irq | error_irq | bus_error_irq | arbitration_lost_irq | error_passive_irq | transmit_cancel_irq;
|
---|
| 1791 |
|
---|
| 1792 | wire irq_clr = we_txcancel | read_rxovrwrite | we_txcmp | we_rxcmp;
|
---|
| 1793 |
|
---|
| 1794 | always @ (posedge clk or posedge rst)
|
---|
| 1795 | begin
|
---|
| 1796 | if (rst)
|
---|
| 1797 | irq_n <= 1'b1;
|
---|
| 1798 | else if (read_irq_reg || release_buffer || irq_clr)
|
---|
| 1799 | irq_n <=#Tp 1'b1;
|
---|
| 1800 | else if (irq)
|
---|
| 1801 | irq_n <=#Tp 1'b0;
|
---|
| 1802 | end
|
---|
| 1803 |
|
---|
| 1804 |
|
---|
| 1805 |
|
---|
| 1806 | endmodule
|
---|
| 1807 |
|
---|