1 | //////////////////////////////////////////////////////////////////////
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2 | //// ////
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3 | //// can_bsp.v ////
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4 | //// ////
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5 | //// ////
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6 | //// This file is part of the CAN Protocol Controller ////
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7 | //// http://www.opencores.org/projects/can/ ////
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8 | //// ////
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9 | //// ////
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10 | //// Author(s): ////
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11 | //// Igor Mohor ////
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12 | //// igorm@opencores.org ////
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13 | //// ////
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14 | //// ////
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15 | //// All additional information is available in the README.txt ////
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16 | //// file. ////
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17 | //// ////
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18 | //////////////////////////////////////////////////////////////////////
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19 | //// ////
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20 | //// Copyright (C) 2002, 2003, 2004 Authors ////
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21 | //// ////
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22 | //// This source file may be used and distributed without ////
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23 | //// restriction provided that this copyright statement is not ////
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24 | //// removed from the file and that any derivative work contains ////
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25 | //// the original copyright notice and the associated disclaimer. ////
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26 | //// ////
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27 | //// This source file is free software; you can redistribute it ////
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28 | //// and/or modify it under the terms of the GNU Lesser General ////
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29 | //// Public License as published by the Free Software Foundation; ////
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30 | //// either version 2.1 of the License, or (at your option) any ////
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31 | //// later version. ////
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32 | //// ////
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33 | //// This source is distributed in the hope that it will be ////
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34 | //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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35 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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36 | //// PURPOSE. See the GNU Lesser General Public License for more ////
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37 | //// details. ////
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38 | //// ////
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39 | //// You should have received a copy of the GNU Lesser General ////
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40 | //// Public License along with this source; if not, download it ////
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41 | //// from http://www.opencores.org/lgpl.shtml ////
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42 | //// ////
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43 | //// The CAN protocol is developed by Robert Bosch GmbH and ////
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44 | //// protected by patents. Anybody who wants to implement this ////
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45 | //// CAN IP core on silicon has to obtain a CAN protocol license ////
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46 | //// from Bosch. ////
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47 | //// ////
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48 | //////////////////////////////////////////////////////////////////////
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49 | //
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50 | // CVS Revision History
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51 | //
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52 | // $Log: can_bsp.v,v $
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53 | // Revision 1.53 2004/11/22 19:18:03 igorm
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54 | // Arbitration capture register changed. SW reset (setting the reset_mode bit)
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55 | // doesn't work as HW reset.
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56 | //
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57 | // Revision 1.52 2004/11/18 12:39:21 igorm
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58 | // Fixes for compatibility after the SW reset.
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59 | //
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60 | // Revision 1.51 2004/11/15 18:23:21 igorm
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61 | // When CAN was reset by setting the reset_mode signal in mode register, it
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62 | // was possible that CAN was blocked for a short period of time. Problem
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63 | // occured very rarly.
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64 | //
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65 | // Revision 1.50 2004/10/27 18:51:36 igorm
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66 | // Fixed synchronization problem in real hardware when 0xf is used for TSEG1.
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67 | //
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68 | // Revision 1.49 2004/10/25 06:37:51 igorm
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69 | // Arbitration bug fixed.
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70 | //
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71 | // Revision 1.48 2004/05/12 15:58:41 igorm
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72 | // Core improved to pass all tests with the Bosch VHDL Reference system.
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73 | //
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74 | // Revision 1.47 2004/02/08 14:24:10 mohor
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75 | // Error counters changed.
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76 | //
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77 | // Revision 1.46 2003/10/17 05:55:20 markom
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78 | // mbist signals updated according to newest convention
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79 | //
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80 | // Revision 1.45 2003/09/30 21:14:33 mohor
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81 | // Error counters changed.
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82 | //
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83 | // Revision 1.44 2003/09/30 00:55:12 mohor
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84 | // Error counters fixed to be compatible with Bosch VHDL reference model.
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85 | // Small synchronization changes.
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86 | //
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87 | // Revision 1.43 2003/09/25 18:55:49 mohor
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88 | // Synchronization changed, error counters fixed.
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89 | //
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90 | // Revision 1.42 2003/08/29 07:01:14 mohor
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91 | // When detecting bus-free, signal bus_free_cnt_en was cleared to zero
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92 | // although the last sampled bit was zero instead of one.
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93 | //
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94 | // Revision 1.41 2003/07/18 15:23:31 tadejm
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95 | // Tx and rx length are limited to 8 bytes regardless to the DLC value.
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96 | //
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97 | // Revision 1.40 2003/07/16 15:10:17 mohor
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98 | // Fixed according to the linter.
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99 | //
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100 | // Revision 1.39 2003/07/16 13:12:46 mohor
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101 | // Fixed according to the linter.
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102 | //
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103 | // Revision 1.38 2003/07/10 01:59:04 tadejm
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104 | // Synchronization fixed. In some strange cases it didn't work according to
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105 | // the VHDL reference model.
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106 | //
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107 | // Revision 1.37 2003/07/07 11:21:37 mohor
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108 | // Little fixes (to fix warnings).
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109 | //
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110 | // Revision 1.36 2003/07/03 09:32:20 mohor
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111 | // Synchronization changed.
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112 | //
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113 | // Revision 1.35 2003/06/27 20:56:12 simons
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114 | // Virtual silicon ram instances added.
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115 | //
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116 | // Revision 1.34 2003/06/22 09:43:03 mohor
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117 | // synthesi full_case parallel_case fixed.
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118 | //
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119 | // Revision 1.33 2003/06/21 12:16:30 mohor
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120 | // paralel_case and full_case compiler directives added to case statements.
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121 | //
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122 | // Revision 1.32 2003/06/17 14:28:32 mohor
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123 | // Form error was detected when stuff bit occured at the end of crc.
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124 | //
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125 | // Revision 1.31 2003/06/16 14:31:29 tadejm
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126 | // Bit stuffing corrected when stuffing comes at the end of the crc.
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127 | //
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128 | // Revision 1.30 2003/06/16 13:57:58 mohor
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129 | // tx_point generated one clk earlier. rx_i registered. Data corrected when
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130 | // using extended mode.
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131 | //
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132 | // Revision 1.29 2003/06/11 14:21:35 mohor
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133 | // When switching to tx, sync stage is overjumped.
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134 | //
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135 | // Revision 1.28 2003/03/01 22:53:33 mohor
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136 | // Actel APA ram supported.
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137 | //
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138 | // Revision 1.27 2003/02/20 00:26:02 mohor
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139 | // When a dominant bit was detected at the third bit of the intermission and
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140 | // node had a message to transmit, bit_stuff error could occur. Fixed.
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141 | //
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142 | // Revision 1.26 2003/02/19 23:21:54 mohor
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143 | // When bit error occured while active error flag was transmitted, counter was
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144 | // not incremented.
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145 | //
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146 | // Revision 1.25 2003/02/19 14:44:03 mohor
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147 | // CAN core finished. Host interface added. Registers finished.
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148 | // Synchronization to the wishbone finished.
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149 | //
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150 | // Revision 1.24 2003/02/18 00:10:15 mohor
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151 | // Most of the registers added. Registers "arbitration lost capture", "error code
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152 | // capture" + few more still need to be added.
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153 | //
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154 | // Revision 1.23 2003/02/14 20:17:01 mohor
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155 | // Several registers added. Not finished, yet.
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156 | //
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157 | // Revision 1.22 2003/02/12 14:23:59 mohor
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158 | // abort_tx added. Bit destuff fixed.
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159 | //
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160 | // Revision 1.21 2003/02/11 00:56:06 mohor
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161 | // Wishbone interface added.
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162 | //
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163 | // Revision 1.20 2003/02/10 16:02:11 mohor
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164 | // CAN is working according to the specification. WB interface and more
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165 | // registers (status, IRQ, ...) needs to be added.
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166 | //
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167 | // Revision 1.19 2003/02/09 18:40:29 mohor
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168 | // Overload fixed. Hard synchronization also enabled at the last bit of
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169 | // interframe.
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170 | //
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171 | // Revision 1.18 2003/02/09 02:24:33 mohor
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172 | // Bosch license warning added. Error counters finished. Overload frames
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173 | // still need to be fixed.
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174 | //
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175 | // Revision 1.17 2003/02/04 17:24:41 mohor
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176 | // Backup.
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177 | //
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178 | // Revision 1.16 2003/02/04 14:34:52 mohor
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179 | // *** empty log message ***
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180 | //
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181 | // Revision 1.15 2003/01/31 01:13:37 mohor
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182 | // backup.
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183 | //
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184 | // Revision 1.14 2003/01/16 13:36:19 mohor
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185 | // Form error supported. When receiving messages, last bit of the end-of-frame
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186 | // does not generate form error. Receiver goes to the idle mode one bit sooner.
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187 | // (CAN specification ver 2.0, part B, page 57).
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188 | //
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189 | // Revision 1.13 2003/01/15 21:59:45 mohor
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190 | // Data is stored to fifo at the end of ack stage.
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191 | //
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192 | // Revision 1.12 2003/01/15 21:05:11 mohor
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193 | // CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).
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194 | //
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195 | // Revision 1.11 2003/01/15 14:40:23 mohor
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196 | // RX state machine fixed to receive "remote request" frames correctly.
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197 | // No data bytes are written to fifo when such frames are received.
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198 | //
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199 | // Revision 1.10 2003/01/15 13:16:47 mohor
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200 | // When a frame with "remote request" is received, no data is stored to
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201 | // fifo, just the frame information (identifier, ...). Data length that
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202 | // is stored is the received data length and not the actual data length
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203 | // that is stored to fifo.
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204 | //
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205 | // Revision 1.9 2003/01/14 12:19:35 mohor
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206 | // rx_fifo is now working.
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207 | //
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208 | // Revision 1.8 2003/01/10 17:51:33 mohor
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209 | // Temporary version (backup).
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210 | //
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211 | // Revision 1.7 2003/01/09 21:54:45 mohor
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212 | // rx fifo added. Not 100 % verified, yet.
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213 | //
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214 | // Revision 1.6 2003/01/09 14:46:58 mohor
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215 | // Temporary files (backup).
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216 | //
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217 | // Revision 1.5 2003/01/08 13:30:31 mohor
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218 | // Temp version.
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219 | //
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220 | // Revision 1.4 2003/01/08 02:10:53 mohor
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221 | // Acceptance filter added.
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222 | //
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223 | // Revision 1.3 2002/12/28 04:13:23 mohor
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224 | // Backup version.
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225 | //
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226 | // Revision 1.2 2002/12/27 00:12:52 mohor
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227 | // Header changed, testbench improved to send a frame (crc still missing).
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228 | //
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229 | // Revision 1.1.1.1 2002/12/20 16:39:21 mohor
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230 | // Initial
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231 | //
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232 | //
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233 | //
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234 |
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235 | // synopsys translate_off
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236 | `include "timescale.v"
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237 | // synopsys translate_on
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238 | `include "can_defines.v"
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239 |
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240 | module can_bsp
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241 | (
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242 | clk,
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243 | rst,
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244 |
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245 | sample_point,
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246 | sampled_bit,
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247 | sampled_bit_q,
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248 | tx_point,
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249 | hard_sync,
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250 |
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251 | addr,
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252 | data_in,
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253 | data_out,
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254 | fifo_selected,
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255 |
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256 |
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257 |
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258 | /* Mode register */
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259 | reset_mode,
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260 | listen_only_mode,
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261 | acceptance_filter_mode,
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262 | self_test_mode,
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263 |
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264 | /* Command register */
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265 | release_buffer,
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266 | tx_request,
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267 | abort_tx,
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268 | self_rx_request,
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269 | single_shot_transmission,
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270 | tx_state,
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271 | tx_state_q,
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272 | overload_request,
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273 | overload_frame,
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274 |
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275 | /* Arbitration Lost Capture Register */
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276 | read_arbitration_lost_capture_reg,
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277 |
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278 | /* Error Code Capture Register */
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279 | read_error_code_capture_reg,
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280 | error_capture_code,
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281 |
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282 | /* Error Warning Limit register */
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283 | error_warning_limit,
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284 |
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285 | /* Rx Error Counter register */
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286 | we_rx_err_cnt,
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287 |
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288 | /* Tx Error Counter register */
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289 | we_tx_err_cnt,
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290 |
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291 | /* Clock Divider register */
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292 | extended_mode,
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293 |
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294 | rx_idle,
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295 | transmitting,
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296 | transmitter,
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297 | go_rx_inter,
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298 | not_first_bit_of_inter,
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299 | rx_inter,
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300 | set_reset_mode,
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301 | node_bus_off,
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302 | error_status,
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303 | rx_err_cnt,
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304 | tx_err_cnt,
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305 | transmit_status,
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306 | receive_status,
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307 | tx_successful,
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308 | need_to_tx,
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309 | overrun,
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310 | info_empty,
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311 | set_bus_error_irq,
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312 | set_arbitration_lost_irq,
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313 | arbitration_lost_capture,
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314 | node_error_passive,
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315 | node_error_active,
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316 | rx_message_counter,
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317 |
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318 | /* This section is for BASIC and EXTENDED mode */
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319 | /* Acceptance code register */
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320 | acceptance_code_0,
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321 |
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322 | /* Acceptance mask register */
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323 | acceptance_mask_0,
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324 | /* End: This section is for BASIC and EXTENDED mode */
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325 |
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326 | /* This section is for EXTENDED mode */
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327 | /* Acceptance code register */
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328 | acceptance_code_1,
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329 | acceptance_code_2,
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330 | acceptance_code_3,
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331 |
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332 | /* Acceptance mask register */
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333 | acceptance_mask_1,
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334 | acceptance_mask_2,
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335 | acceptance_mask_3,
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336 | /* End: This section is for EXTENDED mode */
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337 |
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338 | /* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
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339 | tx_data_0,
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340 | tx_data_1,
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341 | tx_data_2,
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342 | tx_data_3,
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343 | tx_data_4,
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344 | tx_data_5,
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345 | tx_data_6,
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346 | tx_data_7,
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347 | tx_data_8,
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348 | tx_data_9,
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349 | tx_data_10,
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350 | tx_data_11,
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351 | tx_data_12,
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352 | /* End: Tx data registers */
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353 | rx_dt,
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354 | rx_we,
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355 |
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356 | /* Tx signal */
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357 | tx,
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358 | tx_next,
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359 | bus_off_on,
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360 |
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361 | go_overload_frame,
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362 | go_error_frame,
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363 | go_tx,
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364 | send_ack
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365 |
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366 | /* Bist */
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367 | `ifdef CAN_BIST
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368 | ,
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369 | mbist_si_i,
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370 | mbist_so_o,
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371 | mbist_ctrl_i
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372 | `endif
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373 | );
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374 |
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375 | parameter Tp = 1;
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376 |
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377 | input clk;
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378 | input rst;
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379 | input sample_point;
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380 | input sampled_bit;
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381 | input sampled_bit_q;
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382 | input tx_point;
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383 | input hard_sync;
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384 | input [7:0] addr;
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385 | input [31:0] data_in;
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386 | output [7:0] data_out;
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387 | input fifo_selected;
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388 |
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389 | input reset_mode;
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390 | input listen_only_mode;
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391 | input acceptance_filter_mode;
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392 | input extended_mode;
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393 | input self_test_mode;
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394 |
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395 | /* Command register */
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396 | input release_buffer;
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397 | input tx_request;
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398 | input abort_tx;
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399 | input self_rx_request;
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400 | input single_shot_transmission;
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401 | output tx_state;
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402 | output tx_state_q;
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403 | input overload_request; // When receiver is busy, it needs to send overload frame. Only 2 overload frames are allowed to
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404 | output overload_frame; // be send in a row. This is not implemented, yet, because host can not send an overload request.
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405 |
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406 | /* Arbitration Lost Capture Register */
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407 | input read_arbitration_lost_capture_reg;
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408 |
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409 | /* Error Code Capture Register */
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410 | input read_error_code_capture_reg;
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411 | output [7:0] error_capture_code;
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412 |
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413 | /* Error Warning Limit register */
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414 | input [7:0] error_warning_limit;
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415 |
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416 | /* Rx Error Counter register */
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417 | input we_rx_err_cnt;
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418 |
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419 | /* Tx Error Counter register */
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420 | input we_tx_err_cnt;
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421 |
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422 | output rx_idle;
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423 | output transmitting;
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424 | output transmitter;
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425 | output go_rx_inter;
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426 | output not_first_bit_of_inter;
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427 | output rx_inter;
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428 | output set_reset_mode;
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429 | output node_bus_off;
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430 | output error_status;
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431 | output [8:0] rx_err_cnt;
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432 | output [8:0] tx_err_cnt;
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433 | output transmit_status;
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434 | output receive_status;
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435 | output tx_successful;
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436 | output need_to_tx;
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437 | output overrun;
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438 | output info_empty;
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439 | output set_bus_error_irq;
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440 | output set_arbitration_lost_irq;
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441 | output [4:0] arbitration_lost_capture;
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442 | output node_error_passive;
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443 | output node_error_active;
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444 | output [6:0] rx_message_counter;
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445 |
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446 |
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447 | /* This section is for BASIC and EXTENDED mode */
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448 | /* Acceptance code register */
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449 | input [7:0] acceptance_code_0;
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450 |
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451 | /* Acceptance mask register */
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452 | input [7:0] acceptance_mask_0;
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453 |
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454 | /* End: This section is for BASIC and EXTENDED mode */
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455 |
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456 |
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457 | /* This section is for EXTENDED mode */
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458 | /* Acceptance code register */
|
---|
459 | input [7:0] acceptance_code_1;
|
---|
460 | input [7:0] acceptance_code_2;
|
---|
461 | input [7:0] acceptance_code_3;
|
---|
462 |
|
---|
463 | /* Acceptance mask register */
|
---|
464 | input [7:0] acceptance_mask_1;
|
---|
465 | input [7:0] acceptance_mask_2;
|
---|
466 | input [7:0] acceptance_mask_3;
|
---|
467 | /* End: This section is for EXTENDED mode */
|
---|
468 |
|
---|
469 | /* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
|
---|
470 | input [7:0] tx_data_0;
|
---|
471 | input [7:0] tx_data_1;
|
---|
472 | input [7:0] tx_data_2;
|
---|
473 | input [7:0] tx_data_3;
|
---|
474 | input [7:0] tx_data_4;
|
---|
475 | input [7:0] tx_data_5;
|
---|
476 | input [7:0] tx_data_6;
|
---|
477 | input [7:0] tx_data_7;
|
---|
478 | input [7:0] tx_data_8;
|
---|
479 | input [7:0] tx_data_9;
|
---|
480 | input [7:0] tx_data_10;
|
---|
481 | input [7:0] tx_data_11;
|
---|
482 | input [7:0] tx_data_12;
|
---|
483 | /* End: Tx data registers */
|
---|
484 | output [127:0] rx_dt;
|
---|
485 | output rx_we;
|
---|
486 |
|
---|
487 | /* Tx signal */
|
---|
488 | output tx;
|
---|
489 | output tx_next;
|
---|
490 | output bus_off_on;
|
---|
491 |
|
---|
492 | output go_overload_frame;
|
---|
493 | output go_error_frame;
|
---|
494 | output go_tx;
|
---|
495 | output send_ack;
|
---|
496 |
|
---|
497 | /* Bist */
|
---|
498 | `ifdef CAN_BIST
|
---|
499 | input mbist_si_i;
|
---|
500 | output mbist_so_o;
|
---|
501 | input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
|
---|
502 | `endif
|
---|
503 |
|
---|
504 | reg reset_mode_q;
|
---|
505 | reg [5:0] bit_cnt;
|
---|
506 |
|
---|
507 | reg [3:0] data_len;
|
---|
508 | reg [28:0] id;
|
---|
509 | reg [2:0] bit_stuff_cnt;
|
---|
510 | reg [2:0] bit_stuff_cnt_tx;
|
---|
511 | reg tx_point_q;
|
---|
512 |
|
---|
513 | reg rx_idle;
|
---|
514 | reg rx_id1;
|
---|
515 | reg rx_rtr1;
|
---|
516 | reg rx_ide;
|
---|
517 | reg rx_id2;
|
---|
518 | reg rx_rtr2;
|
---|
519 | reg rx_r1;
|
---|
520 | reg rx_r0;
|
---|
521 | reg rx_dlc;
|
---|
522 | reg rx_data;
|
---|
523 | reg rx_crc;
|
---|
524 | reg rx_crc_lim;
|
---|
525 | reg rx_ack;
|
---|
526 | reg rx_ack_lim;
|
---|
527 | reg rx_eof;
|
---|
528 | reg rx_inter;
|
---|
529 | reg go_early_tx_latched;
|
---|
530 |
|
---|
531 | reg rtr1;
|
---|
532 | reg ide;
|
---|
533 | reg rtr2;
|
---|
534 | reg [14:0] crc_in;
|
---|
535 |
|
---|
536 | reg [7:0] tmp_data;
|
---|
537 | reg [7:0] tmp_fifo [0:7];
|
---|
538 | reg write_data_to_tmp_fifo;
|
---|
539 | reg [2:0] byte_cnt;
|
---|
540 | reg bit_stuff_cnt_en;
|
---|
541 | reg crc_enable;
|
---|
542 |
|
---|
543 | reg [2:0] eof_cnt;
|
---|
544 | reg [2:0] passive_cnt;
|
---|
545 |
|
---|
546 | reg transmitting;
|
---|
547 |
|
---|
548 | reg error_frame;
|
---|
549 | reg enable_error_cnt2;
|
---|
550 | reg [2:0] error_cnt1;
|
---|
551 | reg [2:0] error_cnt2;
|
---|
552 | reg [2:0] delayed_dominant_cnt;
|
---|
553 | reg enable_overload_cnt2;
|
---|
554 | reg overload_frame;
|
---|
555 | reg overload_frame_blocked;
|
---|
556 | reg [1:0] overload_request_cnt;
|
---|
557 | reg [2:0] overload_cnt1;
|
---|
558 | reg [2:0] overload_cnt2;
|
---|
559 | reg tx;
|
---|
560 | reg crc_err;
|
---|
561 |
|
---|
562 | reg arbitration_lost;
|
---|
563 | reg arbitration_lost_q;
|
---|
564 | reg arbitration_field_d;
|
---|
565 | reg [4:0] arbitration_lost_capture;
|
---|
566 | reg [4:0] arbitration_cnt;
|
---|
567 | reg arbitration_blocked;
|
---|
568 | reg tx_q;
|
---|
569 |
|
---|
570 | reg need_to_tx; // When the CAN core has something to transmit and a dominant bit is sampled at the third bit
|
---|
571 | reg [3:0] data_cnt; // Counting the data bytes that are written to FIFO
|
---|
572 | reg [2:0] header_cnt; // Counting header length
|
---|
573 | reg wr_fifo; // Write data and header to 64-byte fifo
|
---|
574 | reg wr_fifo_q; // Write data and header to 64-byte fifo
|
---|
575 | reg [7:0] data_for_fifo;// Multiplexed data that is stored to 64-byte fifo
|
---|
576 |
|
---|
577 | reg [5:0] tx_pointer;
|
---|
578 | reg tx_bit;
|
---|
579 | reg tx_state;
|
---|
580 | reg tx_state_q;
|
---|
581 | reg transmitter;
|
---|
582 | reg finish_msg;
|
---|
583 |
|
---|
584 | reg [8:0] rx_err_cnt;
|
---|
585 | reg [8:0] tx_err_cnt;
|
---|
586 | reg [3:0] bus_free_cnt;
|
---|
587 | reg bus_free_cnt_en;
|
---|
588 | reg bus_free;
|
---|
589 | reg waiting_for_bus_free;
|
---|
590 |
|
---|
591 | reg node_error_passive;
|
---|
592 | reg node_bus_off;
|
---|
593 | reg node_bus_off_q;
|
---|
594 | reg ack_err_latched;
|
---|
595 | reg bit_err_latched;
|
---|
596 | reg stuff_err_latched;
|
---|
597 | reg form_err_latched;
|
---|
598 | reg rule3_exc1_1;
|
---|
599 | reg rule3_exc1_2;
|
---|
600 | reg suspend;
|
---|
601 | reg susp_cnt_en;
|
---|
602 | reg [2:0] susp_cnt;
|
---|
603 | reg error_flag_over_latched;
|
---|
604 |
|
---|
605 | reg [7:0] error_capture_code;
|
---|
606 | reg [7:6] error_capture_code_type;
|
---|
607 | reg error_capture_code_blocked;
|
---|
608 | reg tx_next;
|
---|
609 | reg first_compare_bit;
|
---|
610 |
|
---|
611 | reg [127:0] rx_dt;
|
---|
612 |
|
---|
613 |
|
---|
614 | wire [4:0] error_capture_code_segment;
|
---|
615 | wire error_capture_code_direction;
|
---|
616 |
|
---|
617 | wire bit_de_stuff;
|
---|
618 | wire bit_de_stuff_tx;
|
---|
619 |
|
---|
620 | wire rule5;
|
---|
621 |
|
---|
622 | /* Rx state machine */
|
---|
623 | wire go_rx_idle;
|
---|
624 | wire go_rx_id1;
|
---|
625 | wire go_rx_rtr1;
|
---|
626 | wire go_rx_ide;
|
---|
627 | wire go_rx_id2;
|
---|
628 | wire go_rx_rtr2;
|
---|
629 | wire go_rx_r1;
|
---|
630 | wire go_rx_r0;
|
---|
631 | wire go_rx_dlc;
|
---|
632 | wire go_rx_data;
|
---|
633 | wire go_rx_crc;
|
---|
634 | wire go_rx_crc_lim;
|
---|
635 | wire go_rx_ack;
|
---|
636 | wire go_rx_ack_lim;
|
---|
637 | wire go_rx_eof;
|
---|
638 | wire go_rx_inter;
|
---|
639 |
|
---|
640 | wire last_bit_of_inter;
|
---|
641 |
|
---|
642 | wire go_crc_enable;
|
---|
643 | wire rst_crc_enable;
|
---|
644 |
|
---|
645 | wire bit_de_stuff_set;
|
---|
646 | wire bit_de_stuff_reset;
|
---|
647 |
|
---|
648 | wire go_early_tx;
|
---|
649 |
|
---|
650 | wire [14:0] calculated_crc;
|
---|
651 | wire [15:0] r_calculated_crc;
|
---|
652 | wire remote_rq;
|
---|
653 | wire [3:0] limited_data_len;
|
---|
654 | wire form_err;
|
---|
655 |
|
---|
656 | wire error_frame_ended;
|
---|
657 | wire overload_frame_ended;
|
---|
658 | wire bit_err;
|
---|
659 | wire ack_err;
|
---|
660 | wire stuff_err;
|
---|
661 |
|
---|
662 | wire id_ok; // If received ID matches ID set in registers
|
---|
663 | wire no_byte0; // There is no byte 0 (RTR bit set to 1 or DLC field equal to 0). Signal used for acceptance filter.
|
---|
664 | wire no_byte1; // There is no byte 1 (RTR bit set to 1 or DLC field equal to 1). Signal used for acceptance filter.
|
---|
665 |
|
---|
666 | wire [2:0] header_len;
|
---|
667 | wire storing_header;
|
---|
668 | wire [3:0] limited_data_len_minus1;
|
---|
669 | wire reset_wr_fifo;
|
---|
670 | wire err;
|
---|
671 |
|
---|
672 | wire arbitration_field;
|
---|
673 |
|
---|
674 | wire [18:0] basic_chain;
|
---|
675 | wire [63:0] basic_chain_data;
|
---|
676 | wire [18:0] extended_chain_std;
|
---|
677 | wire [38:0] extended_chain_ext;
|
---|
678 | wire [63:0] extended_chain_data_std;
|
---|
679 | wire [63:0] extended_chain_data_ext;
|
---|
680 |
|
---|
681 | wire rst_tx_pointer;
|
---|
682 |
|
---|
683 | wire [7:0] r_tx_data_0;
|
---|
684 | wire [7:0] r_tx_data_1;
|
---|
685 | wire [7:0] r_tx_data_2;
|
---|
686 | wire [7:0] r_tx_data_3;
|
---|
687 | wire [7:0] r_tx_data_4;
|
---|
688 | wire [7:0] r_tx_data_5;
|
---|
689 | wire [7:0] r_tx_data_6;
|
---|
690 | wire [7:0] r_tx_data_7;
|
---|
691 | wire [7:0] r_tx_data_8;
|
---|
692 | wire [7:0] r_tx_data_9;
|
---|
693 | wire [7:0] r_tx_data_10;
|
---|
694 | wire [7:0] r_tx_data_11;
|
---|
695 | wire [7:0] r_tx_data_12;
|
---|
696 |
|
---|
697 | wire send_ack;
|
---|
698 | wire bit_err_exc1;
|
---|
699 | wire bit_err_exc2;
|
---|
700 | wire bit_err_exc3;
|
---|
701 | wire bit_err_exc4;
|
---|
702 | wire bit_err_exc5;
|
---|
703 | wire bit_err_exc6;
|
---|
704 | wire error_flag_over;
|
---|
705 | wire overload_flag_over;
|
---|
706 |
|
---|
707 | wire [5:0] limited_tx_cnt_ext;
|
---|
708 | wire [5:0] limited_tx_cnt_std;
|
---|
709 |
|
---|
710 | assign go_rx_idle = sample_point & sampled_bit & last_bit_of_inter | bus_free & (~node_bus_off);
|
---|
711 | assign go_rx_id1 = sample_point & (~sampled_bit) & (rx_idle | last_bit_of_inter);
|
---|
712 | assign go_rx_rtr1 = (~bit_de_stuff) & sample_point & rx_id1 & (bit_cnt[3:0] == 4'd10);
|
---|
713 | assign go_rx_ide = (~bit_de_stuff) & sample_point & rx_rtr1;
|
---|
714 | assign go_rx_id2 = (~bit_de_stuff) & sample_point & rx_ide & sampled_bit;
|
---|
715 | assign go_rx_rtr2 = (~bit_de_stuff) & sample_point & rx_id2 & (bit_cnt[4:0] == 5'd17);
|
---|
716 | assign go_rx_r1 = (~bit_de_stuff) & sample_point & rx_rtr2;
|
---|
717 | assign go_rx_r0 = (~bit_de_stuff) & sample_point & (rx_ide & (~sampled_bit) | rx_r1);
|
---|
718 | assign go_rx_dlc = (~bit_de_stuff) & sample_point & rx_r0;
|
---|
719 | assign go_rx_data = (~bit_de_stuff) & sample_point & rx_dlc & (bit_cnt[1:0] == 2'd3) & (sampled_bit | (|data_len[2:0])) & (~remote_rq);
|
---|
720 | assign go_rx_crc = (~bit_de_stuff) & sample_point & (rx_dlc & (bit_cnt[1:0] == 2'd3) & ((~sampled_bit) & (~(|data_len[2:0])) | remote_rq) |
|
---|
721 | rx_data & (bit_cnt[5:0] == ((limited_data_len<<3) - 1'b1))); // overflow works ok at max value (8<<3 = 64 = 0). 0-1 = 6'h3f
|
---|
722 | assign go_rx_crc_lim = (~bit_de_stuff) & sample_point & rx_crc & (bit_cnt[3:0] == 4'd14);
|
---|
723 | assign go_rx_ack = (~bit_de_stuff) & sample_point & rx_crc_lim;
|
---|
724 | assign go_rx_ack_lim = sample_point & rx_ack;
|
---|
725 | assign go_rx_eof = sample_point & rx_ack_lim;
|
---|
726 | assign go_rx_inter = ((sample_point & rx_eof & (eof_cnt == 3'd6)) | error_frame_ended | overload_frame_ended) & (~overload_request);
|
---|
727 |
|
---|
728 | assign go_error_frame = (form_err | stuff_err | bit_err | ack_err | (crc_err & go_rx_eof));
|
---|
729 | assign error_frame_ended = (error_cnt2 == 3'd7) & tx_point;
|
---|
730 | assign overload_frame_ended = (overload_cnt2 == 3'd7) & tx_point;
|
---|
731 |
|
---|
732 | assign go_overload_frame = ( sample_point & ((~sampled_bit) | overload_request) & (rx_eof & (~transmitter) & (eof_cnt == 3'd6) | error_frame_ended | overload_frame_ended) |
|
---|
733 | sample_point & (~sampled_bit) & rx_inter & (bit_cnt[1:0] < 2'd2) |
|
---|
734 | sample_point & (~sampled_bit) & ((error_cnt2 == 3'd7) | (overload_cnt2 == 3'd7))
|
---|
735 | )
|
---|
736 | & (~overload_frame_blocked)
|
---|
737 | ;
|
---|
738 |
|
---|
739 |
|
---|
740 | assign go_crc_enable = hard_sync | go_tx;
|
---|
741 | assign rst_crc_enable = go_rx_crc;
|
---|
742 |
|
---|
743 | assign bit_de_stuff_set = go_rx_id1 & (~go_error_frame);
|
---|
744 | assign bit_de_stuff_reset = go_rx_ack | go_error_frame | go_overload_frame;
|
---|
745 |
|
---|
746 | assign remote_rq = ((~ide) & rtr1) | (ide & rtr2);
|
---|
747 | assign limited_data_len = (data_len < 4'h8)? data_len : 4'h8;
|
---|
748 |
|
---|
749 | assign ack_err = rx_ack & sample_point & sampled_bit & tx_state & (~self_test_mode);
|
---|
750 | assign bit_err = (tx_state | error_frame | overload_frame | rx_ack) & sample_point & (tx != sampled_bit) & (~bit_err_exc1) & (~bit_err_exc2) & (~bit_err_exc3) & (~bit_err_exc4) & (~bit_err_exc5) & (~bit_err_exc6) & (~reset_mode);
|
---|
751 | assign bit_err_exc1 = tx_state & arbitration_field & tx;
|
---|
752 | assign bit_err_exc2 = rx_ack & tx;
|
---|
753 | assign bit_err_exc3 = error_frame & node_error_passive & (error_cnt1 < 3'd7);
|
---|
754 | assign bit_err_exc4 = (error_frame & (error_cnt1 == 3'd7) & (~enable_error_cnt2)) | (overload_frame & (overload_cnt1 == 3'd7) & (~enable_overload_cnt2));
|
---|
755 | assign bit_err_exc5 = (error_frame & (error_cnt2 == 3'd7)) | (overload_frame & (overload_cnt2 == 3'd7));
|
---|
756 | assign bit_err_exc6 = (eof_cnt == 3'd6) & rx_eof & (~transmitter);
|
---|
757 |
|
---|
758 | assign arbitration_field = rx_id1 | rx_rtr1 | rx_ide | rx_id2 | rx_rtr2;
|
---|
759 |
|
---|
760 | assign last_bit_of_inter = rx_inter & (bit_cnt[1:0] == 2'd2);
|
---|
761 | assign not_first_bit_of_inter = rx_inter & (bit_cnt[1:0] != 2'd0);
|
---|
762 |
|
---|
763 |
|
---|
764 | // Rx idle state
|
---|
765 | always @ (posedge clk or posedge rst)
|
---|
766 | begin
|
---|
767 | if (rst)
|
---|
768 | rx_idle <= 1'b0;
|
---|
769 | else if (go_rx_id1 | go_error_frame)
|
---|
770 | rx_idle <=#Tp 1'b0;
|
---|
771 | else if (go_rx_idle)
|
---|
772 | rx_idle <=#Tp 1'b1;
|
---|
773 | end
|
---|
774 |
|
---|
775 |
|
---|
776 | // Rx id1 state
|
---|
777 | always @ (posedge clk or posedge rst)
|
---|
778 | begin
|
---|
779 | if (rst)
|
---|
780 | rx_id1 <= 1'b0;
|
---|
781 | else if (go_rx_rtr1 | go_error_frame)
|
---|
782 | rx_id1 <=#Tp 1'b0;
|
---|
783 | else if (go_rx_id1)
|
---|
784 | rx_id1 <=#Tp 1'b1;
|
---|
785 | end
|
---|
786 |
|
---|
787 |
|
---|
788 | // Rx rtr1 state
|
---|
789 | always @ (posedge clk or posedge rst)
|
---|
790 | begin
|
---|
791 | if (rst)
|
---|
792 | rx_rtr1 <= 1'b0;
|
---|
793 | else if (go_rx_ide | go_error_frame)
|
---|
794 | rx_rtr1 <=#Tp 1'b0;
|
---|
795 | else if (go_rx_rtr1)
|
---|
796 | rx_rtr1 <=#Tp 1'b1;
|
---|
797 | end
|
---|
798 |
|
---|
799 |
|
---|
800 | // Rx ide state
|
---|
801 | always @ (posedge clk or posedge rst)
|
---|
802 | begin
|
---|
803 | if (rst)
|
---|
804 | rx_ide <= 1'b0;
|
---|
805 | else if (go_rx_r0 | go_rx_id2 | go_error_frame)
|
---|
806 | rx_ide <=#Tp 1'b0;
|
---|
807 | else if (go_rx_ide)
|
---|
808 | rx_ide <=#Tp 1'b1;
|
---|
809 | end
|
---|
810 |
|
---|
811 |
|
---|
812 | // Rx id2 state
|
---|
813 | always @ (posedge clk or posedge rst)
|
---|
814 | begin
|
---|
815 | if (rst)
|
---|
816 | rx_id2 <= 1'b0;
|
---|
817 | else if (go_rx_rtr2 | go_error_frame)
|
---|
818 | rx_id2 <=#Tp 1'b0;
|
---|
819 | else if (go_rx_id2)
|
---|
820 | rx_id2 <=#Tp 1'b1;
|
---|
821 | end
|
---|
822 |
|
---|
823 |
|
---|
824 | // Rx rtr2 state
|
---|
825 | always @ (posedge clk or posedge rst)
|
---|
826 | begin
|
---|
827 | if (rst)
|
---|
828 | rx_rtr2 <= 1'b0;
|
---|
829 | else if (go_rx_r1 | go_error_frame)
|
---|
830 | rx_rtr2 <=#Tp 1'b0;
|
---|
831 | else if (go_rx_rtr2)
|
---|
832 | rx_rtr2 <=#Tp 1'b1;
|
---|
833 | end
|
---|
834 |
|
---|
835 |
|
---|
836 | // Rx r0 state
|
---|
837 | always @ (posedge clk or posedge rst)
|
---|
838 | begin
|
---|
839 | if (rst)
|
---|
840 | rx_r1 <= 1'b0;
|
---|
841 | else if (go_rx_r0 | go_error_frame)
|
---|
842 | rx_r1 <=#Tp 1'b0;
|
---|
843 | else if (go_rx_r1)
|
---|
844 | rx_r1 <=#Tp 1'b1;
|
---|
845 | end
|
---|
846 |
|
---|
847 |
|
---|
848 | // Rx r0 state
|
---|
849 | always @ (posedge clk or posedge rst)
|
---|
850 | begin
|
---|
851 | if (rst)
|
---|
852 | rx_r0 <= 1'b0;
|
---|
853 | else if (go_rx_dlc | go_error_frame)
|
---|
854 | rx_r0 <=#Tp 1'b0;
|
---|
855 | else if (go_rx_r0)
|
---|
856 | rx_r0 <=#Tp 1'b1;
|
---|
857 | end
|
---|
858 |
|
---|
859 |
|
---|
860 | // Rx dlc state
|
---|
861 | always @ (posedge clk or posedge rst)
|
---|
862 | begin
|
---|
863 | if (rst)
|
---|
864 | rx_dlc <= 1'b0;
|
---|
865 | else if (go_rx_data | go_rx_crc | go_error_frame)
|
---|
866 | rx_dlc <=#Tp 1'b0;
|
---|
867 | else if (go_rx_dlc)
|
---|
868 | rx_dlc <=#Tp 1'b1;
|
---|
869 | end
|
---|
870 |
|
---|
871 |
|
---|
872 | // Rx data state
|
---|
873 | always @ (posedge clk or posedge rst)
|
---|
874 | begin
|
---|
875 | if (rst)
|
---|
876 | rx_data <= 1'b0;
|
---|
877 | else if (go_rx_crc | go_error_frame)
|
---|
878 | rx_data <=#Tp 1'b0;
|
---|
879 | else if (go_rx_data)
|
---|
880 | rx_data <=#Tp 1'b1;
|
---|
881 | end
|
---|
882 |
|
---|
883 |
|
---|
884 | // Rx crc state
|
---|
885 | always @ (posedge clk or posedge rst)
|
---|
886 | begin
|
---|
887 | if (rst)
|
---|
888 | rx_crc <= 1'b0;
|
---|
889 | else if (go_rx_crc_lim | go_error_frame)
|
---|
890 | rx_crc <=#Tp 1'b0;
|
---|
891 | else if (go_rx_crc)
|
---|
892 | rx_crc <=#Tp 1'b1;
|
---|
893 | end
|
---|
894 |
|
---|
895 |
|
---|
896 | // Rx crc delimiter state
|
---|
897 | always @ (posedge clk or posedge rst)
|
---|
898 | begin
|
---|
899 | if (rst)
|
---|
900 | rx_crc_lim <= 1'b0;
|
---|
901 | else if (go_rx_ack | go_error_frame)
|
---|
902 | rx_crc_lim <=#Tp 1'b0;
|
---|
903 | else if (go_rx_crc_lim)
|
---|
904 | rx_crc_lim <=#Tp 1'b1;
|
---|
905 | end
|
---|
906 |
|
---|
907 |
|
---|
908 | // Rx ack state
|
---|
909 | always @ (posedge clk or posedge rst)
|
---|
910 | begin
|
---|
911 | if (rst)
|
---|
912 | rx_ack <= 1'b0;
|
---|
913 | else if (go_rx_ack_lim | go_error_frame)
|
---|
914 | rx_ack <=#Tp 1'b0;
|
---|
915 | else if (go_rx_ack)
|
---|
916 | rx_ack <=#Tp 1'b1;
|
---|
917 | end
|
---|
918 |
|
---|
919 |
|
---|
920 | // Rx ack delimiter state
|
---|
921 | always @ (posedge clk or posedge rst)
|
---|
922 | begin
|
---|
923 | if (rst)
|
---|
924 | rx_ack_lim <= 1'b0;
|
---|
925 | else if (go_rx_eof | go_error_frame)
|
---|
926 | rx_ack_lim <=#Tp 1'b0;
|
---|
927 | else if (go_rx_ack_lim)
|
---|
928 | rx_ack_lim <=#Tp 1'b1;
|
---|
929 | end
|
---|
930 |
|
---|
931 |
|
---|
932 | // Rx eof state
|
---|
933 | always @ (posedge clk or posedge rst)
|
---|
934 | begin
|
---|
935 | if (rst)
|
---|
936 | rx_eof <= 1'b0;
|
---|
937 | else if (go_rx_inter | go_error_frame | go_overload_frame)
|
---|
938 | rx_eof <=#Tp 1'b0;
|
---|
939 | else if (go_rx_eof)
|
---|
940 | rx_eof <=#Tp 1'b1;
|
---|
941 | end
|
---|
942 |
|
---|
943 |
|
---|
944 |
|
---|
945 | // Interframe space
|
---|
946 | always @ (posedge clk or posedge rst)
|
---|
947 | begin
|
---|
948 | if (rst)
|
---|
949 | rx_inter <= 1'b0;
|
---|
950 | else if (go_rx_idle | go_rx_id1 | go_overload_frame | go_error_frame)
|
---|
951 | rx_inter <=#Tp 1'b0;
|
---|
952 | else if (go_rx_inter)
|
---|
953 | rx_inter <=#Tp 1'b1;
|
---|
954 | end
|
---|
955 |
|
---|
956 |
|
---|
957 | // ID register
|
---|
958 | always @ (posedge clk or posedge rst)
|
---|
959 | begin
|
---|
960 | if (rst)
|
---|
961 | id <= 29'h0;
|
---|
962 | else if (sample_point & (rx_id1 | rx_id2) & (~bit_de_stuff))
|
---|
963 | id <=#Tp {id[27:0], sampled_bit};
|
---|
964 | end
|
---|
965 |
|
---|
966 |
|
---|
967 | // rtr1 bit
|
---|
968 | always @ (posedge clk or posedge rst)
|
---|
969 | begin
|
---|
970 | if (rst)
|
---|
971 | rtr1 <= 1'b0;
|
---|
972 | else if (sample_point & rx_rtr1 & (~bit_de_stuff))
|
---|
973 | rtr1 <=#Tp sampled_bit;
|
---|
974 | end
|
---|
975 |
|
---|
976 |
|
---|
977 | // rtr2 bit
|
---|
978 | always @ (posedge clk or posedge rst)
|
---|
979 | begin
|
---|
980 | if (rst)
|
---|
981 | rtr2 <= 1'b0;
|
---|
982 | else if (sample_point & rx_rtr2 & (~bit_de_stuff))
|
---|
983 | rtr2 <=#Tp sampled_bit;
|
---|
984 | end
|
---|
985 |
|
---|
986 |
|
---|
987 | // ide bit
|
---|
988 | always @ (posedge clk or posedge rst)
|
---|
989 | begin
|
---|
990 | if (rst)
|
---|
991 | ide <= 1'b0;
|
---|
992 | else if (sample_point & rx_ide & (~bit_de_stuff))
|
---|
993 | ide <=#Tp sampled_bit;
|
---|
994 | end
|
---|
995 |
|
---|
996 |
|
---|
997 | // Data length
|
---|
998 | always @ (posedge clk or posedge rst)
|
---|
999 | begin
|
---|
1000 | if (rst)
|
---|
1001 | data_len <= 4'b0;
|
---|
1002 | else if (sample_point & rx_dlc & (~bit_de_stuff))
|
---|
1003 | data_len <=#Tp {data_len[2:0], sampled_bit};
|
---|
1004 | end
|
---|
1005 |
|
---|
1006 |
|
---|
1007 | // Data
|
---|
1008 | always @ (posedge clk or posedge rst)
|
---|
1009 | begin
|
---|
1010 | if (rst)
|
---|
1011 | tmp_data <= 8'h0;
|
---|
1012 | else if (sample_point & rx_data & (~bit_de_stuff))
|
---|
1013 | tmp_data <=#Tp {tmp_data[6:0], sampled_bit};
|
---|
1014 | end
|
---|
1015 |
|
---|
1016 |
|
---|
1017 | always @ (posedge clk or posedge rst)
|
---|
1018 | begin
|
---|
1019 | if (rst)
|
---|
1020 | write_data_to_tmp_fifo <= 1'b0;
|
---|
1021 | else if (sample_point & rx_data & (~bit_de_stuff) & (&bit_cnt[2:0]))
|
---|
1022 | write_data_to_tmp_fifo <=#Tp 1'b1;
|
---|
1023 | else
|
---|
1024 | write_data_to_tmp_fifo <=#Tp 1'b0;
|
---|
1025 | end
|
---|
1026 |
|
---|
1027 |
|
---|
1028 | always @ (posedge clk or posedge rst)
|
---|
1029 | begin
|
---|
1030 | if (rst)
|
---|
1031 | byte_cnt <= 3'h0;
|
---|
1032 | else if (write_data_to_tmp_fifo)
|
---|
1033 | byte_cnt <=#Tp byte_cnt + 1'b1;
|
---|
1034 | else if (sample_point & go_rx_crc_lim)
|
---|
1035 | byte_cnt <=#Tp 3'h0;
|
---|
1036 | end
|
---|
1037 |
|
---|
1038 |
|
---|
1039 | //always @ (posedge clk)
|
---|
1040 | always @ (posedge clk or posedge rst)
|
---|
1041 | begin
|
---|
1042 | if(rst)
|
---|
1043 | begin
|
---|
1044 | tmp_fifo[0] <= 8'h0;
|
---|
1045 | tmp_fifo[1] <= 8'h0;
|
---|
1046 | tmp_fifo[2] <= 8'h0;
|
---|
1047 | tmp_fifo[3] <= 8'h0;
|
---|
1048 | tmp_fifo[4] <= 8'h0;
|
---|
1049 | tmp_fifo[5] <= 8'h0;
|
---|
1050 | tmp_fifo[6] <= 8'h0;
|
---|
1051 | tmp_fifo[7] <= 8'h0;
|
---|
1052 | end
|
---|
1053 | else if (write_data_to_tmp_fifo)
|
---|
1054 | tmp_fifo[byte_cnt] <=#Tp tmp_data;
|
---|
1055 | end
|
---|
1056 |
|
---|
1057 |
|
---|
1058 |
|
---|
1059 | // CRC
|
---|
1060 | always @ (posedge clk or posedge rst)
|
---|
1061 | begin
|
---|
1062 | if (rst)
|
---|
1063 | crc_in <= 15'h0;
|
---|
1064 | else if (sample_point & rx_crc & (~bit_de_stuff))
|
---|
1065 | crc_in <=#Tp {crc_in[13:0], sampled_bit};
|
---|
1066 | end
|
---|
1067 |
|
---|
1068 |
|
---|
1069 | // bit_cnt
|
---|
1070 | always @ (posedge clk or posedge rst)
|
---|
1071 | begin
|
---|
1072 | if (rst)
|
---|
1073 | bit_cnt <= 6'd0;
|
---|
1074 | else if (go_rx_id1 | go_rx_id2 | go_rx_dlc | go_rx_data | go_rx_crc |
|
---|
1075 | go_rx_ack | go_rx_eof | go_rx_inter | go_error_frame | go_overload_frame)
|
---|
1076 | bit_cnt <=#Tp 6'd0;
|
---|
1077 | else if (sample_point & (~bit_de_stuff))
|
---|
1078 | bit_cnt <=#Tp bit_cnt + 1'b1;
|
---|
1079 | end
|
---|
1080 |
|
---|
1081 |
|
---|
1082 | // eof_cnt
|
---|
1083 | always @ (posedge clk or posedge rst)
|
---|
1084 | begin
|
---|
1085 | if (rst)
|
---|
1086 | eof_cnt <= 3'd0;
|
---|
1087 | else if (sample_point)
|
---|
1088 | begin
|
---|
1089 | if (go_rx_inter | go_error_frame | go_overload_frame)
|
---|
1090 | eof_cnt <=#Tp 3'd0;
|
---|
1091 | else if (rx_eof)
|
---|
1092 | eof_cnt <=#Tp eof_cnt + 1'b1;
|
---|
1093 | end
|
---|
1094 | end
|
---|
1095 |
|
---|
1096 |
|
---|
1097 | // Enabling bit de-stuffing
|
---|
1098 | always @ (posedge clk or posedge rst)
|
---|
1099 | begin
|
---|
1100 | if (rst)
|
---|
1101 | bit_stuff_cnt_en <= 1'b0;
|
---|
1102 | else if (bit_de_stuff_set)
|
---|
1103 | bit_stuff_cnt_en <=#Tp 1'b1;
|
---|
1104 | else if (bit_de_stuff_reset)
|
---|
1105 | bit_stuff_cnt_en <=#Tp 1'b0;
|
---|
1106 | end
|
---|
1107 |
|
---|
1108 |
|
---|
1109 | // bit_stuff_cnt
|
---|
1110 | always @ (posedge clk or posedge rst)
|
---|
1111 | begin
|
---|
1112 | if (rst)
|
---|
1113 | bit_stuff_cnt <= 3'h1;
|
---|
1114 | else if (bit_de_stuff_reset)
|
---|
1115 | bit_stuff_cnt <=#Tp 3'h1;
|
---|
1116 | else if (sample_point & bit_stuff_cnt_en)
|
---|
1117 | begin
|
---|
1118 | if (bit_stuff_cnt == 3'h5)
|
---|
1119 | bit_stuff_cnt <=#Tp 3'h1;
|
---|
1120 | else if (sampled_bit == sampled_bit_q)
|
---|
1121 | bit_stuff_cnt <=#Tp bit_stuff_cnt + 1'b1;
|
---|
1122 | else
|
---|
1123 | bit_stuff_cnt <=#Tp 3'h1;
|
---|
1124 | end
|
---|
1125 | end
|
---|
1126 |
|
---|
1127 |
|
---|
1128 | // bit_stuff_cnt_tx
|
---|
1129 | always @ (posedge clk or posedge rst)
|
---|
1130 | begin
|
---|
1131 | if (rst)
|
---|
1132 | bit_stuff_cnt_tx <= 3'h1;
|
---|
1133 | else if (reset_mode || bit_de_stuff_reset)
|
---|
1134 | bit_stuff_cnt_tx <=#Tp 3'h1;
|
---|
1135 | else if (tx_point_q & bit_stuff_cnt_en)
|
---|
1136 | begin
|
---|
1137 | if (bit_stuff_cnt_tx == 3'h5)
|
---|
1138 | bit_stuff_cnt_tx <=#Tp 3'h1;
|
---|
1139 | else if (tx == tx_q)
|
---|
1140 | bit_stuff_cnt_tx <=#Tp bit_stuff_cnt_tx + 1'b1;
|
---|
1141 | else
|
---|
1142 | bit_stuff_cnt_tx <=#Tp 3'h1;
|
---|
1143 | end
|
---|
1144 | end
|
---|
1145 |
|
---|
1146 |
|
---|
1147 | assign bit_de_stuff = bit_stuff_cnt == 3'h5;
|
---|
1148 | assign bit_de_stuff_tx = bit_stuff_cnt_tx == 3'h5;
|
---|
1149 |
|
---|
1150 |
|
---|
1151 |
|
---|
1152 | // stuff_err
|
---|
1153 | assign stuff_err = sample_point & bit_stuff_cnt_en & bit_de_stuff & (sampled_bit == sampled_bit_q);
|
---|
1154 |
|
---|
1155 |
|
---|
1156 |
|
---|
1157 | // Generating delayed signals
|
---|
1158 | always @ (posedge clk or posedge rst)
|
---|
1159 | begin
|
---|
1160 | if (rst)
|
---|
1161 | begin
|
---|
1162 | reset_mode_q <=#Tp 1'b0;
|
---|
1163 | node_bus_off_q <=#Tp 1'b0;
|
---|
1164 | end
|
---|
1165 | else
|
---|
1166 | begin
|
---|
1167 | reset_mode_q <=#Tp reset_mode;
|
---|
1168 | node_bus_off_q <=#Tp node_bus_off;
|
---|
1169 | end
|
---|
1170 | end
|
---|
1171 |
|
---|
1172 |
|
---|
1173 |
|
---|
1174 | always @ (posedge clk or posedge rst)
|
---|
1175 | begin
|
---|
1176 | if (rst)
|
---|
1177 | crc_enable <= 1'b0;
|
---|
1178 | else if (rst_crc_enable)
|
---|
1179 | crc_enable <=#Tp 1'b0;
|
---|
1180 | else if (go_crc_enable)
|
---|
1181 | crc_enable <=#Tp 1'b1;
|
---|
1182 | end
|
---|
1183 |
|
---|
1184 |
|
---|
1185 | // CRC error generation
|
---|
1186 | always @ (posedge clk or posedge rst)
|
---|
1187 | begin
|
---|
1188 | if (rst)
|
---|
1189 | crc_err <= 1'b0;
|
---|
1190 | else if (reset_mode | error_frame_ended)
|
---|
1191 | crc_err <=#Tp 1'b0;
|
---|
1192 | else if (go_rx_ack)
|
---|
1193 | crc_err <=#Tp crc_in != calculated_crc;
|
---|
1194 | end
|
---|
1195 |
|
---|
1196 |
|
---|
1197 | // Conditions for form error
|
---|
1198 | assign form_err = sample_point & ( ((~bit_de_stuff) & rx_crc_lim & (~sampled_bit) ) |
|
---|
1199 | ( rx_ack_lim & (~sampled_bit) ) |
|
---|
1200 | ((eof_cnt < 3'd6)& rx_eof & (~sampled_bit) & (~transmitter) ) |
|
---|
1201 | ( & rx_eof & (~sampled_bit) & transmitter )
|
---|
1202 | );
|
---|
1203 |
|
---|
1204 |
|
---|
1205 | always @ (posedge clk or posedge rst)
|
---|
1206 | begin
|
---|
1207 | if (rst)
|
---|
1208 | ack_err_latched <= 1'b0;
|
---|
1209 | else if (reset_mode | error_frame_ended | go_overload_frame)
|
---|
1210 | ack_err_latched <=#Tp 1'b0;
|
---|
1211 | else if (ack_err)
|
---|
1212 | ack_err_latched <=#Tp 1'b1;
|
---|
1213 | end
|
---|
1214 |
|
---|
1215 |
|
---|
1216 | always @ (posedge clk or posedge rst)
|
---|
1217 | begin
|
---|
1218 | if (rst)
|
---|
1219 | bit_err_latched <= 1'b0;
|
---|
1220 | else if (reset_mode | error_frame_ended | go_overload_frame)
|
---|
1221 | bit_err_latched <=#Tp 1'b0;
|
---|
1222 | else if (bit_err)
|
---|
1223 | bit_err_latched <=#Tp 1'b1;
|
---|
1224 | end
|
---|
1225 |
|
---|
1226 |
|
---|
1227 |
|
---|
1228 | // Rule 5 (Fault confinement).
|
---|
1229 | assign rule5 = bit_err & ( (~node_error_passive) & error_frame & (error_cnt1 < 3'd7)
|
---|
1230 | |
|
---|
1231 | overload_frame & (overload_cnt1 < 3'd7)
|
---|
1232 | );
|
---|
1233 |
|
---|
1234 | // Rule 3 exception 1 - first part (Fault confinement).
|
---|
1235 | always @ (posedge clk or posedge rst)
|
---|
1236 | begin
|
---|
1237 | if (rst)
|
---|
1238 | rule3_exc1_1 <= 1'b0;
|
---|
1239 | else if (error_flag_over | rule3_exc1_2)
|
---|
1240 | rule3_exc1_1 <=#Tp 1'b0;
|
---|
1241 | else if (transmitter & node_error_passive & ack_err)
|
---|
1242 | rule3_exc1_1 <=#Tp 1'b1;
|
---|
1243 | end
|
---|
1244 |
|
---|
1245 |
|
---|
1246 | // Rule 3 exception 1 - second part (Fault confinement).
|
---|
1247 | always @ (posedge clk or posedge rst)
|
---|
1248 | begin
|
---|
1249 | if (rst)
|
---|
1250 | rule3_exc1_2 <= 1'b0;
|
---|
1251 | else if (go_error_frame | rule3_exc1_2)
|
---|
1252 | rule3_exc1_2 <=#Tp 1'b0;
|
---|
1253 | else if (rule3_exc1_1 & (error_cnt1 < 3'd7) & sample_point & (~sampled_bit))
|
---|
1254 | rule3_exc1_2 <=#Tp 1'b1;
|
---|
1255 | end
|
---|
1256 |
|
---|
1257 |
|
---|
1258 | always @ (posedge clk or posedge rst)
|
---|
1259 | begin
|
---|
1260 | if (rst)
|
---|
1261 | stuff_err_latched <= 1'b0;
|
---|
1262 | else if (reset_mode | error_frame_ended | go_overload_frame)
|
---|
1263 | stuff_err_latched <=#Tp 1'b0;
|
---|
1264 | else if (stuff_err)
|
---|
1265 | stuff_err_latched <=#Tp 1'b1;
|
---|
1266 | end
|
---|
1267 |
|
---|
1268 |
|
---|
1269 |
|
---|
1270 | always @ (posedge clk or posedge rst)
|
---|
1271 | begin
|
---|
1272 | if (rst)
|
---|
1273 | form_err_latched <= 1'b0;
|
---|
1274 | else if (reset_mode | error_frame_ended | go_overload_frame)
|
---|
1275 | form_err_latched <=#Tp 1'b0;
|
---|
1276 | else if (form_err)
|
---|
1277 | form_err_latched <=#Tp 1'b1;
|
---|
1278 | end
|
---|
1279 |
|
---|
1280 |
|
---|
1281 |
|
---|
1282 | // Instantiation of the RX CRC module
|
---|
1283 | can_crc i_can_crc_rx
|
---|
1284 | (
|
---|
1285 | .clk(clk),
|
---|
1286 | .data(sampled_bit),
|
---|
1287 | .enable(crc_enable & sample_point & (~bit_de_stuff)),
|
---|
1288 | .initialize(go_crc_enable),
|
---|
1289 | .crc(calculated_crc)
|
---|
1290 | );
|
---|
1291 |
|
---|
1292 |
|
---|
1293 |
|
---|
1294 |
|
---|
1295 | assign no_byte0 = rtr1 | (data_len<4'h1);
|
---|
1296 | assign no_byte1 = rtr1 | (data_len<4'h2);
|
---|
1297 |
|
---|
1298 | can_acf i_can_acf
|
---|
1299 | (
|
---|
1300 | .clk(clk),
|
---|
1301 | .rst(rst),
|
---|
1302 |
|
---|
1303 | .id(id),
|
---|
1304 |
|
---|
1305 | /* Mode register */
|
---|
1306 | .reset_mode(reset_mode),
|
---|
1307 | .acceptance_filter_mode(acceptance_filter_mode),
|
---|
1308 |
|
---|
1309 | // Clock Divider register
|
---|
1310 | .extended_mode(extended_mode),
|
---|
1311 |
|
---|
1312 | /* This section is for BASIC and EXTENDED mode */
|
---|
1313 | /* Acceptance code register */
|
---|
1314 | .acceptance_code_0(acceptance_code_0),
|
---|
1315 |
|
---|
1316 | /* Acceptance mask register */
|
---|
1317 | .acceptance_mask_0(acceptance_mask_0),
|
---|
1318 | /* End: This section is for BASIC and EXTENDED mode */
|
---|
1319 |
|
---|
1320 | /* This section is for EXTENDED mode */
|
---|
1321 | /* Acceptance code register */
|
---|
1322 | .acceptance_code_1(acceptance_code_1),
|
---|
1323 | .acceptance_code_2(acceptance_code_2),
|
---|
1324 | .acceptance_code_3(acceptance_code_3),
|
---|
1325 |
|
---|
1326 | /* Acceptance mask register */
|
---|
1327 | .acceptance_mask_1(acceptance_mask_1),
|
---|
1328 | .acceptance_mask_2(acceptance_mask_2),
|
---|
1329 | .acceptance_mask_3(acceptance_mask_3),
|
---|
1330 | /* End: This section is for EXTENDED mode */
|
---|
1331 |
|
---|
1332 | .go_rx_crc_lim(go_rx_crc_lim),
|
---|
1333 | .go_rx_inter(go_rx_inter),
|
---|
1334 | .go_error_frame(go_error_frame),
|
---|
1335 |
|
---|
1336 | .data0(tmp_fifo[0]),
|
---|
1337 | .data1(tmp_fifo[1]),
|
---|
1338 | .rtr1(rtr1),
|
---|
1339 | .rtr2(rtr2),
|
---|
1340 | .ide(ide),
|
---|
1341 | .no_byte0(no_byte0),
|
---|
1342 | .no_byte1(no_byte1),
|
---|
1343 |
|
---|
1344 | .id_ok(id_ok)
|
---|
1345 |
|
---|
1346 | );
|
---|
1347 |
|
---|
1348 |
|
---|
1349 |
|
---|
1350 |
|
---|
1351 | assign header_len[2:0] = extended_mode ? (ide? (3'h5) : (3'h3)) : 3'h2;
|
---|
1352 | assign storing_header = header_cnt < header_len;
|
---|
1353 | assign limited_data_len_minus1[3:0] = remote_rq? 4'hf : ((data_len < 4'h8)? (data_len -1'b1) : 4'h7); // - 1 because counter counts from 0
|
---|
1354 | assign reset_wr_fifo = (data_cnt == (limited_data_len_minus1 + {1'b0, header_len})) || reset_mode;
|
---|
1355 |
|
---|
1356 | assign err = form_err | stuff_err | bit_err | ack_err | form_err_latched | stuff_err_latched | bit_err_latched | ack_err_latched | crc_err;
|
---|
1357 |
|
---|
1358 |
|
---|
1359 |
|
---|
1360 | // Write enable signal for 64-byte rx fifo
|
---|
1361 | always @ (posedge clk or posedge rst)
|
---|
1362 | begin
|
---|
1363 | if (rst)
|
---|
1364 | wr_fifo <= 1'b0;
|
---|
1365 | else if (reset_wr_fifo)
|
---|
1366 | wr_fifo <=#Tp 1'b0;
|
---|
1367 | else if (go_rx_inter & id_ok & (~error_frame_ended) & ((~tx_state) | self_rx_request))
|
---|
1368 | wr_fifo <=#Tp 1'b1;
|
---|
1369 | end
|
---|
1370 |
|
---|
1371 |
|
---|
1372 | // Header counter. Header length depends on the mode of operation and frame format.
|
---|
1373 | always @ (posedge clk or posedge rst)
|
---|
1374 | begin
|
---|
1375 | if (rst)
|
---|
1376 | header_cnt <= 3'h0;
|
---|
1377 | else if (reset_wr_fifo)
|
---|
1378 | header_cnt <=#Tp 3'h0;
|
---|
1379 | else if (wr_fifo & storing_header)
|
---|
1380 | header_cnt <=#Tp header_cnt + 1'h1;
|
---|
1381 | end
|
---|
1382 |
|
---|
1383 |
|
---|
1384 | // Data counter. Length of the data is limited to 8 bytes.
|
---|
1385 | always @ (posedge clk or posedge rst)
|
---|
1386 | begin
|
---|
1387 | if (rst)
|
---|
1388 | data_cnt <= 4'h0;
|
---|
1389 | else if (reset_wr_fifo)
|
---|
1390 | data_cnt <=#Tp 4'h0;
|
---|
1391 | else if (wr_fifo)
|
---|
1392 | data_cnt <=#Tp data_cnt + 4'h1;
|
---|
1393 | end
|
---|
1394 |
|
---|
1395 |
|
---|
1396 | // Multiplexing data that is stored to 64-byte fifo depends on the mode of operation and frame format
|
---|
1397 | always @ (extended_mode or ide or data_cnt or header_cnt or header_len or
|
---|
1398 | storing_header or id or rtr1 or rtr2 or data_len or
|
---|
1399 | tmp_fifo[0] or tmp_fifo[2] or tmp_fifo[4] or tmp_fifo[6] or
|
---|
1400 | tmp_fifo[1] or tmp_fifo[3] or tmp_fifo[5] or tmp_fifo[7])
|
---|
1401 | begin
|
---|
1402 | casex ({storing_header, extended_mode, ide, header_cnt}) /* synthesis parallel_case */
|
---|
1403 | 6'b1_1_1_000 : data_for_fifo = {1'b1, rtr2, 2'h0, data_len}; // extended mode, extended format header
|
---|
1404 | 6'b1_1_1_001 : data_for_fifo = id[28:21]; // extended mode, extended format header
|
---|
1405 | 6'b1_1_1_010 : data_for_fifo = id[20:13]; // extended mode, extended format header
|
---|
1406 | 6'b1_1_1_011 : data_for_fifo = id[12:5]; // extended mode, extended format header
|
---|
1407 | 6'b1_1_1_100 : data_for_fifo = {id[4:0], 3'h0}; // extended mode, extended format header
|
---|
1408 | 6'b1_1_0_000 : data_for_fifo = {1'b0, rtr1, 2'h0, data_len}; // extended mode, standard format header
|
---|
1409 | 6'b1_1_0_001 : data_for_fifo = id[10:3]; // extended mode, standard format header
|
---|
1410 | 6'b1_1_0_010 : data_for_fifo = {id[2:0], rtr1, 4'h0}; // extended mode, standard format header
|
---|
1411 | 6'b1_0_x_000 : data_for_fifo = id[10:3]; // normal mode header
|
---|
1412 | 6'b1_0_x_001 : data_for_fifo = {id[2:0], rtr1, data_len}; // normal mode header
|
---|
1413 | default : data_for_fifo = tmp_fifo[data_cnt - {1'b0, header_len}]; // data
|
---|
1414 | endcase
|
---|
1415 | end
|
---|
1416 |
|
---|
1417 |
|
---|
1418 | assign rx_we = (~wr_fifo) & wr_fifo_q;
|
---|
1419 |
|
---|
1420 | // Delayed write signal
|
---|
1421 | always @ (posedge clk or posedge rst)
|
---|
1422 | begin
|
---|
1423 | if (rst)
|
---|
1424 | wr_fifo_q <=#Tp 1'b0;
|
---|
1425 | else if (reset_mode)
|
---|
1426 | wr_fifo_q <=#Tp 1'b0;
|
---|
1427 | else
|
---|
1428 | wr_fifo_q <=#Tp wr_fifo;
|
---|
1429 | end
|
---|
1430 |
|
---|
1431 | wire [28:0] rxid;
|
---|
1432 | wire rxfmt = (extended_mode&ide)? 1'h1: 1'h0;
|
---|
1433 | wire rxrtr = (extended_mode&ide)? rtr2: rtr1;
|
---|
1434 | assign rxid = (extended_mode&ide)? id: {id[10:0],18'h0};
|
---|
1435 | always @ (posedge clk or posedge rst)
|
---|
1436 | begin
|
---|
1437 | if (rst)
|
---|
1438 | begin
|
---|
1439 | rx_dt <= 128'h0;
|
---|
1440 | end
|
---|
1441 | else if (wr_fifo)
|
---|
1442 | begin
|
---|
1443 | rx_dt[0*32+31:0*32+00] <= {rxfmt, 2'h0, rxid};
|
---|
1444 | rx_dt[1*32+31:1*32+00] <= {24'h0, 3'h0, rxrtr, data_len};
|
---|
1445 | rx_dt[2*32+31:2*32+00] <= {tmp_fifo[3], tmp_fifo[2], tmp_fifo[1], tmp_fifo[0]};
|
---|
1446 | rx_dt[3*32+31:3*32+00] <= {tmp_fifo[7], tmp_fifo[6], tmp_fifo[5], tmp_fifo[4]};
|
---|
1447 | end
|
---|
1448 | end
|
---|
1449 |
|
---|
1450 |
|
---|
1451 | // Instantiation of the RX fifo module
|
---|
1452 | can_fifo i_can_fifo
|
---|
1453 | (
|
---|
1454 | .clk(clk),
|
---|
1455 | .rst(rst),
|
---|
1456 |
|
---|
1457 | .wr(1'h0),
|
---|
1458 |
|
---|
1459 | .data_in(data_for_fifo),
|
---|
1460 | .addr(addr[5:0]),
|
---|
1461 | .data_out(data_out),
|
---|
1462 | .fifo_selected(fifo_selected),
|
---|
1463 |
|
---|
1464 | .reset_mode(reset_mode),
|
---|
1465 | .release_buffer(release_buffer),
|
---|
1466 | .extended_mode(extended_mode),
|
---|
1467 | .overrun(overrun),
|
---|
1468 | .info_empty(info_empty),
|
---|
1469 | .info_cnt(rx_message_counter)
|
---|
1470 |
|
---|
1471 | `ifdef CAN_BIST
|
---|
1472 | ,
|
---|
1473 | .mbist_si_i(mbist_si_i),
|
---|
1474 | .mbist_so_o(mbist_so_o),
|
---|
1475 | .mbist_ctrl_i(mbist_ctrl_i)
|
---|
1476 | `endif
|
---|
1477 | );
|
---|
1478 |
|
---|
1479 |
|
---|
1480 | // Transmitting error frame.
|
---|
1481 | always @ (posedge clk or posedge rst)
|
---|
1482 | begin
|
---|
1483 | if (rst)
|
---|
1484 | error_frame <= 1'b0;
|
---|
1485 | // else if (reset_mode || error_frame_ended || go_overload_frame)
|
---|
1486 | else if (set_reset_mode || error_frame_ended || go_overload_frame)
|
---|
1487 | error_frame <=#Tp 1'b0;
|
---|
1488 | else if (go_error_frame)
|
---|
1489 | error_frame <=#Tp 1'b1;
|
---|
1490 | end
|
---|
1491 |
|
---|
1492 |
|
---|
1493 |
|
---|
1494 | always @ (posedge clk or posedge rst)
|
---|
1495 | begin
|
---|
1496 | if (rst)
|
---|
1497 | error_cnt1 <= 3'd0;
|
---|
1498 | else if (error_frame_ended | go_error_frame | go_overload_frame)
|
---|
1499 | error_cnt1 <=#Tp 3'd0;
|
---|
1500 | else if (error_frame & tx_point & (error_cnt1 < 3'd7))
|
---|
1501 | error_cnt1 <=#Tp error_cnt1 + 1'b1;
|
---|
1502 | end
|
---|
1503 |
|
---|
1504 |
|
---|
1505 |
|
---|
1506 | assign error_flag_over = ((~node_error_passive) & sample_point & (error_cnt1 == 3'd7) | node_error_passive & sample_point & (passive_cnt == 3'h6)) & (~enable_error_cnt2);
|
---|
1507 |
|
---|
1508 |
|
---|
1509 | always @ (posedge clk or posedge rst)
|
---|
1510 | begin
|
---|
1511 | if (rst)
|
---|
1512 | error_flag_over_latched <= 1'b0;
|
---|
1513 | else if (error_frame_ended | go_error_frame | go_overload_frame)
|
---|
1514 | error_flag_over_latched <=#Tp 1'b0;
|
---|
1515 | else if (error_flag_over)
|
---|
1516 | error_flag_over_latched <=#Tp 1'b1;
|
---|
1517 | end
|
---|
1518 |
|
---|
1519 |
|
---|
1520 | always @ (posedge clk or posedge rst)
|
---|
1521 | begin
|
---|
1522 | if (rst)
|
---|
1523 | enable_error_cnt2 <= 1'b0;
|
---|
1524 | else if (error_frame_ended | go_error_frame | go_overload_frame)
|
---|
1525 | enable_error_cnt2 <=#Tp 1'b0;
|
---|
1526 | else if (error_frame & (error_flag_over & sampled_bit))
|
---|
1527 | enable_error_cnt2 <=#Tp 1'b1;
|
---|
1528 | end
|
---|
1529 |
|
---|
1530 |
|
---|
1531 | always @ (posedge clk or posedge rst)
|
---|
1532 | begin
|
---|
1533 | if (rst)
|
---|
1534 | error_cnt2 <= 3'd0;
|
---|
1535 | else if (error_frame_ended | go_error_frame | go_overload_frame)
|
---|
1536 | error_cnt2 <=#Tp 3'd0;
|
---|
1537 | else if (enable_error_cnt2 & tx_point)
|
---|
1538 | error_cnt2 <=#Tp error_cnt2 + 1'b1;
|
---|
1539 | end
|
---|
1540 |
|
---|
1541 |
|
---|
1542 | always @ (posedge clk or posedge rst)
|
---|
1543 | begin
|
---|
1544 | if (rst)
|
---|
1545 | delayed_dominant_cnt <= 3'h0;
|
---|
1546 | else if (enable_error_cnt2 | go_error_frame | enable_overload_cnt2 | go_overload_frame)
|
---|
1547 | delayed_dominant_cnt <=#Tp 3'h0;
|
---|
1548 | else if (sample_point & (~sampled_bit) & ((error_cnt1 == 3'd7) | (overload_cnt1 == 3'd7)))
|
---|
1549 | delayed_dominant_cnt <=#Tp delayed_dominant_cnt + 1'b1;
|
---|
1550 | end
|
---|
1551 |
|
---|
1552 |
|
---|
1553 | // passive_cnt
|
---|
1554 | always @ (posedge clk or posedge rst)
|
---|
1555 | begin
|
---|
1556 | if (rst)
|
---|
1557 | passive_cnt <= 3'h1;
|
---|
1558 | else if (error_frame_ended | go_error_frame | go_overload_frame | first_compare_bit)
|
---|
1559 | passive_cnt <=#Tp 3'h1;
|
---|
1560 | else if (sample_point & (passive_cnt < 3'h6))
|
---|
1561 | begin
|
---|
1562 | if (error_frame & (~enable_error_cnt2) & (sampled_bit == sampled_bit_q))
|
---|
1563 | passive_cnt <=#Tp passive_cnt + 1'b1;
|
---|
1564 | else
|
---|
1565 | passive_cnt <=#Tp 3'h1;
|
---|
1566 | end
|
---|
1567 | end
|
---|
1568 |
|
---|
1569 |
|
---|
1570 | // When comparing 6 equal bits, first is always equal
|
---|
1571 | always @ (posedge clk or posedge rst)
|
---|
1572 | begin
|
---|
1573 | if (rst)
|
---|
1574 | first_compare_bit <= 1'b0;
|
---|
1575 | else if (go_error_frame)
|
---|
1576 | first_compare_bit <=#Tp 1'b1;
|
---|
1577 | else if (sample_point)
|
---|
1578 | first_compare_bit <= 1'b0;
|
---|
1579 | end
|
---|
1580 |
|
---|
1581 |
|
---|
1582 | // Transmitting overload frame.
|
---|
1583 | always @ (posedge clk or posedge rst)
|
---|
1584 | begin
|
---|
1585 | if (rst)
|
---|
1586 | overload_frame <= 1'b0;
|
---|
1587 | else if (overload_frame_ended | go_error_frame)
|
---|
1588 | overload_frame <=#Tp 1'b0;
|
---|
1589 | else if (go_overload_frame)
|
---|
1590 | overload_frame <=#Tp 1'b1;
|
---|
1591 | end
|
---|
1592 |
|
---|
1593 |
|
---|
1594 | always @ (posedge clk or posedge rst)
|
---|
1595 | begin
|
---|
1596 | if (rst)
|
---|
1597 | overload_cnt1 <= 3'd0;
|
---|
1598 | else if (overload_frame_ended | go_error_frame | go_overload_frame)
|
---|
1599 | overload_cnt1 <=#Tp 3'd0;
|
---|
1600 | else if (overload_frame & tx_point & (overload_cnt1 < 3'd7))
|
---|
1601 | overload_cnt1 <=#Tp overload_cnt1 + 1'b1;
|
---|
1602 | end
|
---|
1603 |
|
---|
1604 |
|
---|
1605 | assign overload_flag_over = sample_point & (overload_cnt1 == 3'd7) & (~enable_overload_cnt2);
|
---|
1606 |
|
---|
1607 |
|
---|
1608 | always @ (posedge clk or posedge rst)
|
---|
1609 | begin
|
---|
1610 | if (rst)
|
---|
1611 | enable_overload_cnt2 <= 1'b0;
|
---|
1612 | else if (overload_frame_ended | go_error_frame | go_overload_frame)
|
---|
1613 | enable_overload_cnt2 <=#Tp 1'b0;
|
---|
1614 | else if (overload_frame & (overload_flag_over & sampled_bit))
|
---|
1615 | enable_overload_cnt2 <=#Tp 1'b1;
|
---|
1616 | end
|
---|
1617 |
|
---|
1618 |
|
---|
1619 | always @ (posedge clk or posedge rst)
|
---|
1620 | begin
|
---|
1621 | if (rst)
|
---|
1622 | overload_cnt2 <= 3'd0;
|
---|
1623 | else if (overload_frame_ended | go_error_frame | go_overload_frame)
|
---|
1624 | overload_cnt2 <=#Tp 3'd0;
|
---|
1625 | else if (enable_overload_cnt2 & tx_point)
|
---|
1626 | overload_cnt2 <=#Tp overload_cnt2 + 1'b1;
|
---|
1627 | end
|
---|
1628 |
|
---|
1629 |
|
---|
1630 | always @ (posedge clk or posedge rst)
|
---|
1631 | begin
|
---|
1632 | if (rst)
|
---|
1633 | overload_request_cnt <= 2'b0;
|
---|
1634 | else if (go_error_frame | go_rx_id1)
|
---|
1635 | overload_request_cnt <=#Tp 2'b0;
|
---|
1636 | else if (overload_request & overload_frame)
|
---|
1637 | overload_request_cnt <=#Tp overload_request_cnt + 1'b1;
|
---|
1638 | end
|
---|
1639 |
|
---|
1640 |
|
---|
1641 | always @ (posedge clk or posedge rst)
|
---|
1642 | begin
|
---|
1643 | if (rst)
|
---|
1644 | overload_frame_blocked <= 1'b0;
|
---|
1645 | else if (go_error_frame | go_rx_id1)
|
---|
1646 | overload_frame_blocked <=#Tp 1'b0;
|
---|
1647 | else if (overload_request & overload_frame & overload_request_cnt == 2'h2) // This is a second sequential overload_request
|
---|
1648 | overload_frame_blocked <=#Tp 1'b1;
|
---|
1649 | end
|
---|
1650 |
|
---|
1651 |
|
---|
1652 | assign send_ack = (~tx_state) & rx_ack & (~err) & (~listen_only_mode);
|
---|
1653 |
|
---|
1654 |
|
---|
1655 |
|
---|
1656 | always @ (reset_mode or node_bus_off or tx_state or go_tx or bit_de_stuff_tx or tx_bit or tx_q or
|
---|
1657 | send_ack or go_overload_frame or overload_frame or overload_cnt1 or
|
---|
1658 | go_error_frame or error_frame or error_cnt1 or node_error_passive)
|
---|
1659 | begin
|
---|
1660 | if (reset_mode | node_bus_off) // Reset or node_bus_off
|
---|
1661 | tx_next = 1'b1;
|
---|
1662 | else
|
---|
1663 | begin
|
---|
1664 | if (go_error_frame | error_frame) // Transmitting error frame
|
---|
1665 | begin
|
---|
1666 | if (error_cnt1 < 3'd6)
|
---|
1667 | begin
|
---|
1668 | if (node_error_passive)
|
---|
1669 | tx_next = 1'b1;
|
---|
1670 | else
|
---|
1671 | tx_next = 1'b0;
|
---|
1672 | end
|
---|
1673 | else
|
---|
1674 | tx_next = 1'b1;
|
---|
1675 | end
|
---|
1676 | else if (go_overload_frame | overload_frame) // Transmitting overload frame
|
---|
1677 | begin
|
---|
1678 | if (overload_cnt1 < 3'd6)
|
---|
1679 | tx_next = 1'b0;
|
---|
1680 | else
|
---|
1681 | tx_next = 1'b1;
|
---|
1682 | end
|
---|
1683 | else if (go_tx | tx_state) // Transmitting message
|
---|
1684 | tx_next = ((~bit_de_stuff_tx) & tx_bit) | (bit_de_stuff_tx & (~tx_q));
|
---|
1685 | else if (send_ack) // Acknowledge
|
---|
1686 | tx_next = 1'b0;
|
---|
1687 | else
|
---|
1688 | tx_next = 1'b1;
|
---|
1689 | end
|
---|
1690 | end
|
---|
1691 |
|
---|
1692 |
|
---|
1693 | always @ (posedge clk or posedge rst)
|
---|
1694 | begin
|
---|
1695 | if (rst)
|
---|
1696 | tx <= 1'b1;
|
---|
1697 | else if (reset_mode)
|
---|
1698 | tx <= 1'b1;
|
---|
1699 | else if (tx_point)
|
---|
1700 | tx <=#Tp tx_next;
|
---|
1701 | end
|
---|
1702 |
|
---|
1703 |
|
---|
1704 | always @ (posedge clk or posedge rst)
|
---|
1705 | begin
|
---|
1706 | if (rst)
|
---|
1707 | tx_q <=#Tp 1'b0;
|
---|
1708 | else if (reset_mode)
|
---|
1709 | tx_q <=#Tp 1'b0;
|
---|
1710 | else if (tx_point)
|
---|
1711 | tx_q <=#Tp tx & (~go_early_tx_latched);
|
---|
1712 | end
|
---|
1713 |
|
---|
1714 |
|
---|
1715 | /* Delayed tx point */
|
---|
1716 | always @ (posedge clk or posedge rst)
|
---|
1717 | begin
|
---|
1718 | if (rst)
|
---|
1719 | tx_point_q <=#Tp 1'b0;
|
---|
1720 | else if (reset_mode)
|
---|
1721 | tx_point_q <=#Tp 1'b0;
|
---|
1722 | else
|
---|
1723 | tx_point_q <=#Tp tx_point;
|
---|
1724 | end
|
---|
1725 |
|
---|
1726 |
|
---|
1727 | /* Changing bit order from [7:0] to [0:7] */
|
---|
1728 | can_ibo i_ibo_tx_data_0 (.di(tx_data_0), .do(r_tx_data_0));
|
---|
1729 | can_ibo i_ibo_tx_data_1 (.di(tx_data_1), .do(r_tx_data_1));
|
---|
1730 | can_ibo i_ibo_tx_data_2 (.di(tx_data_2), .do(r_tx_data_2));
|
---|
1731 | can_ibo i_ibo_tx_data_3 (.di(tx_data_3), .do(r_tx_data_3));
|
---|
1732 | can_ibo i_ibo_tx_data_4 (.di(tx_data_4), .do(r_tx_data_4));
|
---|
1733 | can_ibo i_ibo_tx_data_5 (.di(tx_data_5), .do(r_tx_data_5));
|
---|
1734 | can_ibo i_ibo_tx_data_6 (.di(tx_data_6), .do(r_tx_data_6));
|
---|
1735 | can_ibo i_ibo_tx_data_7 (.di(tx_data_7), .do(r_tx_data_7));
|
---|
1736 | can_ibo i_ibo_tx_data_8 (.di(tx_data_8), .do(r_tx_data_8));
|
---|
1737 | can_ibo i_ibo_tx_data_9 (.di(tx_data_9), .do(r_tx_data_9));
|
---|
1738 | can_ibo i_ibo_tx_data_10 (.di(tx_data_10), .do(r_tx_data_10));
|
---|
1739 | can_ibo i_ibo_tx_data_11 (.di(tx_data_11), .do(r_tx_data_11));
|
---|
1740 | can_ibo i_ibo_tx_data_12 (.di(tx_data_12), .do(r_tx_data_12));
|
---|
1741 |
|
---|
1742 | /* Changing bit order from [14:0] to [0:14] */
|
---|
1743 | can_ibo i_calculated_crc0 (.di(calculated_crc[14:7]), .do(r_calculated_crc[7:0]));
|
---|
1744 | can_ibo i_calculated_crc1 (.di({calculated_crc[6:0], 1'b0}), .do(r_calculated_crc[15:8]));
|
---|
1745 |
|
---|
1746 |
|
---|
1747 | assign basic_chain = {r_tx_data_1[7:4], 2'h0, r_tx_data_1[3:0], r_tx_data_0[7:0], 1'b0};
|
---|
1748 | assign basic_chain_data = {r_tx_data_9, r_tx_data_8, r_tx_data_7, r_tx_data_6, r_tx_data_5, r_tx_data_4, r_tx_data_3, r_tx_data_2};
|
---|
1749 | assign extended_chain_std = {r_tx_data_0[7:4], 2'h0, r_tx_data_0[1], r_tx_data_2[2:0], r_tx_data_1[7:0], 1'b0};
|
---|
1750 | assign extended_chain_ext = {r_tx_data_0[7:4], 2'h0, r_tx_data_0[1], r_tx_data_4[4:0], r_tx_data_3[7:0], r_tx_data_2[7:3], 1'b1, 1'b1, r_tx_data_2[2:0], r_tx_data_1[7:0], 1'b0};
|
---|
1751 | assign extended_chain_data_std = {r_tx_data_10, r_tx_data_9, r_tx_data_8, r_tx_data_7, r_tx_data_6, r_tx_data_5, r_tx_data_4, r_tx_data_3};
|
---|
1752 | assign extended_chain_data_ext = {r_tx_data_12, r_tx_data_11, r_tx_data_10, r_tx_data_9, r_tx_data_8, r_tx_data_7, r_tx_data_6, r_tx_data_5};
|
---|
1753 |
|
---|
1754 | always @ (extended_mode or rx_data or tx_pointer or extended_chain_data_std or extended_chain_data_ext or rx_crc or r_calculated_crc or
|
---|
1755 | r_tx_data_0 or extended_chain_ext or extended_chain_std or basic_chain_data or basic_chain or
|
---|
1756 | finish_msg)
|
---|
1757 | begin
|
---|
1758 | if (extended_mode)
|
---|
1759 | begin
|
---|
1760 | if (rx_data) // data stage
|
---|
1761 | if (r_tx_data_0[0]) // Extended frame
|
---|
1762 | tx_bit = extended_chain_data_ext[tx_pointer];
|
---|
1763 | else
|
---|
1764 | tx_bit = extended_chain_data_std[tx_pointer];
|
---|
1765 | else if (rx_crc)
|
---|
1766 | tx_bit = r_calculated_crc[tx_pointer];
|
---|
1767 | else if (finish_msg)
|
---|
1768 | tx_bit = 1'b1;
|
---|
1769 | else
|
---|
1770 | begin
|
---|
1771 | if (r_tx_data_0[0]) // Extended frame
|
---|
1772 | tx_bit = extended_chain_ext[tx_pointer];
|
---|
1773 | else
|
---|
1774 | tx_bit = extended_chain_std[tx_pointer];
|
---|
1775 | end
|
---|
1776 | end
|
---|
1777 | else // Basic mode
|
---|
1778 | begin
|
---|
1779 | if (rx_data) // data stage
|
---|
1780 | tx_bit = basic_chain_data[tx_pointer];
|
---|
1781 | else if (rx_crc)
|
---|
1782 | tx_bit = r_calculated_crc[tx_pointer];
|
---|
1783 | else if (finish_msg)
|
---|
1784 | tx_bit = 1'b1;
|
---|
1785 | else
|
---|
1786 | tx_bit = basic_chain[tx_pointer];
|
---|
1787 | end
|
---|
1788 | end
|
---|
1789 |
|
---|
1790 |
|
---|
1791 | assign limited_tx_cnt_ext = tx_data_0[3] ? 6'h3f : ((tx_data_0[2:0] <<3) - 1'b1);
|
---|
1792 | assign limited_tx_cnt_std = tx_data_1[3] ? 6'h3f : ((tx_data_1[2:0] <<3) - 1'b1);
|
---|
1793 |
|
---|
1794 | assign rst_tx_pointer = ((~bit_de_stuff_tx) & tx_point & (~rx_data) & extended_mode & r_tx_data_0[0] & tx_pointer == 6'd38 ) | // arbitration + control for extended format
|
---|
1795 | ((~bit_de_stuff_tx) & tx_point & (~rx_data) & extended_mode & (~r_tx_data_0[0]) & tx_pointer == 6'd18 ) | // arbitration + control for extended format
|
---|
1796 | ((~bit_de_stuff_tx) & tx_point & (~rx_data) & (~extended_mode) & tx_pointer == 6'd18 ) | // arbitration + control for standard format
|
---|
1797 | ((~bit_de_stuff_tx) & tx_point & rx_data & extended_mode & tx_pointer == limited_tx_cnt_ext) | // data (overflow is OK here)
|
---|
1798 | ((~bit_de_stuff_tx) & tx_point & rx_data & (~extended_mode) & tx_pointer == limited_tx_cnt_std) | // data (overflow is OK here)
|
---|
1799 | ( tx_point & rx_crc_lim ) | // crc
|
---|
1800 | (go_rx_idle ) | // at the end
|
---|
1801 | (reset_mode ) |
|
---|
1802 | (overload_frame ) |
|
---|
1803 | (error_frame ) ;
|
---|
1804 |
|
---|
1805 | always @ (posedge clk or posedge rst)
|
---|
1806 | begin
|
---|
1807 | if (rst)
|
---|
1808 | tx_pointer <= 6'h0;
|
---|
1809 | else if (rst_tx_pointer)
|
---|
1810 | tx_pointer <=#Tp 6'h0;
|
---|
1811 | else if (go_early_tx | (tx_point & (tx_state | go_tx) & (~bit_de_stuff_tx)))
|
---|
1812 | tx_pointer <=#Tp tx_pointer + 1'b1;
|
---|
1813 | end
|
---|
1814 |
|
---|
1815 |
|
---|
1816 | assign tx_successful = transmitter & go_rx_inter & (~go_error_frame) & (~error_frame_ended) & (~overload_frame_ended) & (~arbitration_lost);
|
---|
1817 |
|
---|
1818 |
|
---|
1819 | always @ (posedge clk or posedge rst)
|
---|
1820 | begin
|
---|
1821 | if (rst)
|
---|
1822 | need_to_tx <= 1'b0;
|
---|
1823 | else if (tx_successful | reset_mode | (abort_tx & (~transmitting)) | ((~tx_state) & tx_state_q & single_shot_transmission))
|
---|
1824 | need_to_tx <=#Tp 1'h0;
|
---|
1825 | else if (tx_request & sample_point)
|
---|
1826 | need_to_tx <=#Tp 1'b1;
|
---|
1827 | end
|
---|
1828 |
|
---|
1829 |
|
---|
1830 |
|
---|
1831 | assign go_early_tx = (~listen_only_mode) & need_to_tx & (~tx_state) & (~suspend | (susp_cnt == 3'h7)) & sample_point & (~sampled_bit) & (rx_idle | last_bit_of_inter);
|
---|
1832 | assign go_tx = (~listen_only_mode) & need_to_tx & (~tx_state) & (~suspend | (sample_point & (susp_cnt == 3'h7))) & (go_early_tx | rx_idle);
|
---|
1833 |
|
---|
1834 | // go_early_tx latched (for proper bit_de_stuff generation)
|
---|
1835 | always @ (posedge clk or posedge rst)
|
---|
1836 | begin
|
---|
1837 | if (rst)
|
---|
1838 | go_early_tx_latched <= 1'b0;
|
---|
1839 | else if (reset_mode || tx_point)
|
---|
1840 | go_early_tx_latched <=#Tp 1'b0;
|
---|
1841 | else if (go_early_tx)
|
---|
1842 | go_early_tx_latched <=#Tp 1'b1;
|
---|
1843 | end
|
---|
1844 |
|
---|
1845 |
|
---|
1846 |
|
---|
1847 | // Tx state
|
---|
1848 | always @ (posedge clk or posedge rst)
|
---|
1849 | begin
|
---|
1850 | if (rst)
|
---|
1851 | tx_state <= 1'b0;
|
---|
1852 | else if (reset_mode | go_rx_inter | error_frame | arbitration_lost)
|
---|
1853 | tx_state <=#Tp 1'b0;
|
---|
1854 | else if (go_tx)
|
---|
1855 | tx_state <=#Tp 1'b1;
|
---|
1856 | end
|
---|
1857 |
|
---|
1858 | always @ (posedge clk or posedge rst)
|
---|
1859 | begin
|
---|
1860 | if (rst)
|
---|
1861 | tx_state_q <=#Tp 1'b0;
|
---|
1862 | else if (reset_mode)
|
---|
1863 | tx_state_q <=#Tp 1'b0;
|
---|
1864 | else
|
---|
1865 | tx_state_q <=#Tp tx_state;
|
---|
1866 | end
|
---|
1867 |
|
---|
1868 |
|
---|
1869 |
|
---|
1870 | // Node is a transmitter
|
---|
1871 | always @ (posedge clk or posedge rst)
|
---|
1872 | begin
|
---|
1873 | if (rst)
|
---|
1874 | transmitter <= 1'b0;
|
---|
1875 | else if (go_tx)
|
---|
1876 | transmitter <=#Tp 1'b1;
|
---|
1877 | else if (reset_mode | go_rx_idle | suspend & go_rx_id1)
|
---|
1878 | transmitter <=#Tp 1'b0;
|
---|
1879 | end
|
---|
1880 |
|
---|
1881 |
|
---|
1882 |
|
---|
1883 | // Signal "transmitting" signals that the core is a transmitting (message, error frame or overload frame). No synchronization is done meanwhile.
|
---|
1884 | // Node might be both transmitter or receiver (sending error or overload frame)
|
---|
1885 | always @ (posedge clk or posedge rst)
|
---|
1886 | begin
|
---|
1887 | if (rst)
|
---|
1888 | transmitting <= 1'b0;
|
---|
1889 | else if (go_error_frame | go_overload_frame | go_tx | send_ack)
|
---|
1890 | transmitting <=#Tp 1'b1;
|
---|
1891 | else if (reset_mode | go_rx_idle | (go_rx_id1 & (~tx_state)) | (arbitration_lost & tx_state))
|
---|
1892 | transmitting <=#Tp 1'b0;
|
---|
1893 | end
|
---|
1894 |
|
---|
1895 |
|
---|
1896 | always @ (posedge clk or posedge rst)
|
---|
1897 | begin
|
---|
1898 | if (rst)
|
---|
1899 | suspend <= 1'b0;
|
---|
1900 | else if (reset_mode | (sample_point & (susp_cnt == 3'h7)))
|
---|
1901 | suspend <=#Tp 1'b0;
|
---|
1902 | else if (not_first_bit_of_inter & transmitter & node_error_passive)
|
---|
1903 | suspend <=#Tp 1'b1;
|
---|
1904 | end
|
---|
1905 |
|
---|
1906 |
|
---|
1907 | always @ (posedge clk or posedge rst)
|
---|
1908 | begin
|
---|
1909 | if (rst)
|
---|
1910 | susp_cnt_en <= 1'b0;
|
---|
1911 | else if (reset_mode | (sample_point & (susp_cnt == 3'h7)))
|
---|
1912 | susp_cnt_en <=#Tp 1'b0;
|
---|
1913 | else if (suspend & sample_point & last_bit_of_inter)
|
---|
1914 | susp_cnt_en <=#Tp 1'b1;
|
---|
1915 | end
|
---|
1916 |
|
---|
1917 |
|
---|
1918 | always @ (posedge clk or posedge rst)
|
---|
1919 | begin
|
---|
1920 | if (rst)
|
---|
1921 | susp_cnt <= 3'h0;
|
---|
1922 | else if (reset_mode | (sample_point & (susp_cnt == 3'h7)))
|
---|
1923 | susp_cnt <=#Tp 3'h0;
|
---|
1924 | else if (susp_cnt_en & sample_point)
|
---|
1925 | susp_cnt <=#Tp susp_cnt + 1'b1;
|
---|
1926 | end
|
---|
1927 |
|
---|
1928 |
|
---|
1929 | always @ (posedge clk or posedge rst)
|
---|
1930 | begin
|
---|
1931 | if (rst)
|
---|
1932 | finish_msg <= 1'b0;
|
---|
1933 | else if (go_rx_idle | go_rx_id1 | error_frame | reset_mode)
|
---|
1934 | finish_msg <=#Tp 1'b0;
|
---|
1935 | else if (go_rx_crc_lim)
|
---|
1936 | finish_msg <=#Tp 1'b1;
|
---|
1937 | end
|
---|
1938 |
|
---|
1939 |
|
---|
1940 | always @ (posedge clk or posedge rst)
|
---|
1941 | begin
|
---|
1942 | if (rst)
|
---|
1943 | arbitration_lost <= 1'b0;
|
---|
1944 | else if (go_rx_idle | error_frame_ended)
|
---|
1945 | arbitration_lost <=#Tp 1'b0;
|
---|
1946 | else if (transmitter & sample_point & tx & arbitration_field & ~sampled_bit)
|
---|
1947 | arbitration_lost <=#Tp 1'b1;
|
---|
1948 | end
|
---|
1949 |
|
---|
1950 |
|
---|
1951 | always @ (posedge clk or posedge rst)
|
---|
1952 | begin
|
---|
1953 | if (rst)
|
---|
1954 | arbitration_lost_q <=#Tp 1'b0;
|
---|
1955 | else
|
---|
1956 | arbitration_lost_q <=#Tp arbitration_lost;
|
---|
1957 | end
|
---|
1958 |
|
---|
1959 |
|
---|
1960 | always @ (posedge clk or posedge rst)
|
---|
1961 | begin
|
---|
1962 | if (rst)
|
---|
1963 | arbitration_field_d <=#Tp 1'b0;
|
---|
1964 | else if (sample_point)
|
---|
1965 | arbitration_field_d <=#Tp arbitration_field;
|
---|
1966 | end
|
---|
1967 |
|
---|
1968 |
|
---|
1969 | assign set_arbitration_lost_irq = arbitration_lost & (~arbitration_lost_q) & (~arbitration_blocked);
|
---|
1970 |
|
---|
1971 |
|
---|
1972 | always @ (posedge clk or posedge rst)
|
---|
1973 | begin
|
---|
1974 | if (rst)
|
---|
1975 | arbitration_cnt <= 5'h0;
|
---|
1976 | else if (sample_point && !bit_de_stuff)
|
---|
1977 | if (arbitration_field_d)
|
---|
1978 | arbitration_cnt <=#Tp arbitration_cnt + 1'b1;
|
---|
1979 | else
|
---|
1980 | arbitration_cnt <=#Tp 5'h0;
|
---|
1981 | end
|
---|
1982 |
|
---|
1983 |
|
---|
1984 | always @ (posedge clk or posedge rst)
|
---|
1985 | begin
|
---|
1986 | if (rst)
|
---|
1987 | arbitration_lost_capture <= 5'h0;
|
---|
1988 | else if (set_arbitration_lost_irq)
|
---|
1989 | arbitration_lost_capture <=#Tp arbitration_cnt;
|
---|
1990 | end
|
---|
1991 |
|
---|
1992 |
|
---|
1993 | always @ (posedge clk or posedge rst)
|
---|
1994 | begin
|
---|
1995 | if (rst)
|
---|
1996 | arbitration_blocked <= 1'b0;
|
---|
1997 | else if (read_arbitration_lost_capture_reg)
|
---|
1998 | arbitration_blocked <=#Tp 1'b0;
|
---|
1999 | else if (set_arbitration_lost_irq)
|
---|
2000 | arbitration_blocked <=#Tp 1'b1;
|
---|
2001 | end
|
---|
2002 |
|
---|
2003 |
|
---|
2004 | always @ (posedge clk or posedge rst)
|
---|
2005 | begin
|
---|
2006 | if (rst)
|
---|
2007 | rx_err_cnt <= 9'h0;
|
---|
2008 | else if (we_rx_err_cnt & (~node_bus_off))
|
---|
2009 | rx_err_cnt <=#Tp {1'b0, data_in[23:16]};
|
---|
2010 | else if (set_reset_mode)
|
---|
2011 | rx_err_cnt <=#Tp 9'h0;
|
---|
2012 | else
|
---|
2013 | begin
|
---|
2014 | if ((~listen_only_mode) & (~transmitter | arbitration_lost))
|
---|
2015 | begin
|
---|
2016 | if (go_rx_ack_lim & (~go_error_frame) & (~crc_err) & (rx_err_cnt > 9'h0))
|
---|
2017 | begin
|
---|
2018 | if (rx_err_cnt > 9'd127)
|
---|
2019 | rx_err_cnt <=#Tp 9'd127;
|
---|
2020 | else
|
---|
2021 | rx_err_cnt <=#Tp rx_err_cnt - 1'b1;
|
---|
2022 | end
|
---|
2023 | else if (rx_err_cnt < 9'd128)
|
---|
2024 | begin
|
---|
2025 | if (go_error_frame & (~rule5)) // 1 (rule 5 is just the opposite then rule 1 exception
|
---|
2026 | rx_err_cnt <=#Tp rx_err_cnt + 1'b1;
|
---|
2027 | else if ( (error_flag_over & (~error_flag_over_latched) & sample_point & (~sampled_bit) & (error_cnt1 == 3'd7) ) | // 2
|
---|
2028 | (go_error_frame & rule5 ) | // 5
|
---|
2029 | (sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7) ) // 6
|
---|
2030 | )
|
---|
2031 | rx_err_cnt <=#Tp rx_err_cnt + 4'h8;
|
---|
2032 | end
|
---|
2033 | end
|
---|
2034 | end
|
---|
2035 | end
|
---|
2036 |
|
---|
2037 |
|
---|
2038 | always @ (posedge clk or posedge rst)
|
---|
2039 | begin
|
---|
2040 | if (rst)
|
---|
2041 | tx_err_cnt <= 9'h0;
|
---|
2042 | else if (we_tx_err_cnt)
|
---|
2043 | tx_err_cnt <=#Tp {1'b0, data_in[31:24]};
|
---|
2044 | else
|
---|
2045 | begin
|
---|
2046 | if (set_reset_mode)
|
---|
2047 | tx_err_cnt <=#Tp 9'd128;
|
---|
2048 | else if ((tx_err_cnt > 9'd0) & (tx_successful | bus_free))
|
---|
2049 | tx_err_cnt <=#Tp tx_err_cnt - 1'h1;
|
---|
2050 | else if (transmitter & (~arbitration_lost))
|
---|
2051 | begin
|
---|
2052 | if ( (sample_point & (~sampled_bit) & (delayed_dominant_cnt == 3'h7) ) | // 6
|
---|
2053 | (go_error_frame & rule5 ) | // 4 (rule 5 is the same as rule 4)
|
---|
2054 | (go_error_frame & (~(transmitter & node_error_passive & ack_err)) & (~(transmitter & stuff_err &
|
---|
2055 | arbitration_field & sample_point & tx & (~sampled_bit))) ) | // 3
|
---|
2056 | (error_frame & rule3_exc1_2 ) // 3
|
---|
2057 | )
|
---|
2058 | tx_err_cnt <=#Tp tx_err_cnt + 4'h8;
|
---|
2059 | end
|
---|
2060 | end
|
---|
2061 | end
|
---|
2062 |
|
---|
2063 |
|
---|
2064 | always @ (posedge clk or posedge rst)
|
---|
2065 | begin
|
---|
2066 | if (rst)
|
---|
2067 | node_error_passive <= 1'b0;
|
---|
2068 | else if ((rx_err_cnt < 128) & (tx_err_cnt < 9'd128))
|
---|
2069 | node_error_passive <=#Tp 1'b0;
|
---|
2070 | else if (((rx_err_cnt >= 128) | (tx_err_cnt >= 9'd128)) & (error_frame_ended | go_error_frame | (~reset_mode) & reset_mode_q) & (~node_bus_off))
|
---|
2071 | node_error_passive <=#Tp 1'b1;
|
---|
2072 | end
|
---|
2073 |
|
---|
2074 |
|
---|
2075 | assign node_error_active = ~(node_error_passive | node_bus_off);
|
---|
2076 |
|
---|
2077 |
|
---|
2078 | always @ (posedge clk or posedge rst)
|
---|
2079 | begin
|
---|
2080 | if (rst)
|
---|
2081 | node_bus_off <= 1'b0;
|
---|
2082 | else if ((rx_err_cnt == 9'h0) & (tx_err_cnt == 9'd0) & (~reset_mode) | (we_tx_err_cnt & (data_in[31:24] < 8'd255)))
|
---|
2083 | node_bus_off <=#Tp 1'b0;
|
---|
2084 | else if ((tx_err_cnt >= 9'd256) | (we_tx_err_cnt & (data_in[31:24] == 8'd255)))
|
---|
2085 | node_bus_off <=#Tp 1'b1;
|
---|
2086 | end
|
---|
2087 |
|
---|
2088 |
|
---|
2089 |
|
---|
2090 | always @ (posedge clk or posedge rst)
|
---|
2091 | begin
|
---|
2092 | if (rst)
|
---|
2093 | bus_free_cnt <= 4'h0;
|
---|
2094 | else if (sample_point)
|
---|
2095 | begin
|
---|
2096 | if (sampled_bit & bus_free_cnt_en & (bus_free_cnt < 4'd10))
|
---|
2097 | bus_free_cnt <=#Tp bus_free_cnt + 1'b1;
|
---|
2098 | else
|
---|
2099 | bus_free_cnt <=#Tp 4'h0;
|
---|
2100 | end
|
---|
2101 | end
|
---|
2102 |
|
---|
2103 |
|
---|
2104 | always @ (posedge clk or posedge rst)
|
---|
2105 | begin
|
---|
2106 | if (rst)
|
---|
2107 | bus_free_cnt_en <= 1'b0;
|
---|
2108 | else if ((~reset_mode) & reset_mode_q | node_bus_off_q & (~reset_mode))
|
---|
2109 | bus_free_cnt_en <=#Tp 1'b1;
|
---|
2110 | else if (sample_point & sampled_bit & (bus_free_cnt==4'd10) & (~node_bus_off))
|
---|
2111 | bus_free_cnt_en <=#Tp 1'b0;
|
---|
2112 | end
|
---|
2113 |
|
---|
2114 |
|
---|
2115 | always @ (posedge clk or posedge rst)
|
---|
2116 | begin
|
---|
2117 | if (rst)
|
---|
2118 | bus_free <= 1'b0;
|
---|
2119 | else if (sample_point & sampled_bit & (bus_free_cnt==4'd10) && waiting_for_bus_free)
|
---|
2120 | bus_free <=#Tp 1'b1;
|
---|
2121 | else
|
---|
2122 | bus_free <=#Tp 1'b0;
|
---|
2123 | end
|
---|
2124 |
|
---|
2125 |
|
---|
2126 | always @ (posedge clk or posedge rst)
|
---|
2127 | begin
|
---|
2128 | if (rst)
|
---|
2129 | waiting_for_bus_free <= 1'b1;
|
---|
2130 | else if (bus_free & (~node_bus_off))
|
---|
2131 | waiting_for_bus_free <=#Tp 1'b0;
|
---|
2132 | else if (node_bus_off_q & (~reset_mode))
|
---|
2133 | waiting_for_bus_free <=#Tp 1'b1;
|
---|
2134 | end
|
---|
2135 |
|
---|
2136 |
|
---|
2137 | assign bus_off_on = ~node_bus_off;
|
---|
2138 |
|
---|
2139 | assign set_reset_mode = node_bus_off & (~node_bus_off_q);
|
---|
2140 | assign error_status = extended_mode? ((rx_err_cnt >= error_warning_limit) | (tx_err_cnt >= error_warning_limit)) :
|
---|
2141 | ((rx_err_cnt >= 9'd96) | (tx_err_cnt >= 9'd96)) ;
|
---|
2142 |
|
---|
2143 | assign transmit_status = transmitting || (extended_mode && waiting_for_bus_free);
|
---|
2144 | assign receive_status = extended_mode ? (waiting_for_bus_free || (!rx_idle) && (!transmitting)) :
|
---|
2145 | ((!waiting_for_bus_free) && (!rx_idle) && (!transmitting));
|
---|
2146 |
|
---|
2147 | /* Error code capture register */
|
---|
2148 | always @ (posedge clk or posedge rst)
|
---|
2149 | begin
|
---|
2150 | if (rst)
|
---|
2151 | error_capture_code <= 8'h0;
|
---|
2152 | else if (read_error_code_capture_reg)
|
---|
2153 | error_capture_code <=#Tp 8'h0;
|
---|
2154 | else if (set_bus_error_irq)
|
---|
2155 | error_capture_code <=#Tp {error_capture_code_type[7:6], error_capture_code_direction, error_capture_code_segment[4:0]};
|
---|
2156 | end
|
---|
2157 |
|
---|
2158 |
|
---|
2159 |
|
---|
2160 | assign error_capture_code_segment[0] = rx_idle | rx_ide | (rx_id2 & (bit_cnt<6'd13)) | rx_r1 | rx_r0 | rx_dlc | rx_ack | rx_ack_lim | error_frame & node_error_active;
|
---|
2161 | assign error_capture_code_segment[1] = rx_idle | rx_id1 | rx_id2 | rx_dlc | rx_data | rx_ack_lim | rx_eof | rx_inter | error_frame & node_error_passive;
|
---|
2162 | assign error_capture_code_segment[2] = (rx_id1 & (bit_cnt>6'd7)) | rx_rtr1 | rx_ide | rx_id2 | rx_rtr2 | rx_r1 | error_frame & node_error_passive | overload_frame;
|
---|
2163 | assign error_capture_code_segment[3] = (rx_id2 & (bit_cnt>6'd4)) | rx_rtr2 | rx_r1 | rx_r0 | rx_dlc | rx_data | rx_crc | rx_crc_lim | rx_ack | rx_ack_lim | rx_eof | overload_frame;
|
---|
2164 | assign error_capture_code_segment[4] = rx_crc_lim | rx_ack | rx_ack_lim | rx_eof | rx_inter | error_frame | overload_frame;
|
---|
2165 | assign error_capture_code_direction = ~transmitting;
|
---|
2166 |
|
---|
2167 |
|
---|
2168 | always @ (bit_err or form_err or stuff_err)
|
---|
2169 | begin
|
---|
2170 | if (bit_err)
|
---|
2171 | error_capture_code_type[7:6] = 2'b00;
|
---|
2172 | else if (form_err)
|
---|
2173 | error_capture_code_type[7:6] = 2'b01;
|
---|
2174 | else if (stuff_err)
|
---|
2175 | error_capture_code_type[7:6] = 2'b10;
|
---|
2176 | else
|
---|
2177 | error_capture_code_type[7:6] = 2'b11;
|
---|
2178 | end
|
---|
2179 |
|
---|
2180 |
|
---|
2181 | assign set_bus_error_irq = go_error_frame & (~error_capture_code_blocked);
|
---|
2182 |
|
---|
2183 |
|
---|
2184 | always @ (posedge clk or posedge rst)
|
---|
2185 | begin
|
---|
2186 | if (rst)
|
---|
2187 | error_capture_code_blocked <= 1'b0;
|
---|
2188 | else if (read_error_code_capture_reg)
|
---|
2189 | error_capture_code_blocked <=#Tp 1'b0;
|
---|
2190 | else if (set_bus_error_irq)
|
---|
2191 | error_capture_code_blocked <=#Tp 1'b1;
|
---|
2192 | end
|
---|
2193 |
|
---|
2194 |
|
---|
2195 | endmodule
|
---|
2196 |
|
---|