1 | // --------------------------------------------------------------------
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2 | // Copyright (c) 2011 by Terasic Technologies Inc.
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3 | // --------------------------------------------------------------------
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4 | //
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5 | // Permission:
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6 | //
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7 | // Terasic grants permission to use and modify this code for use
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8 | // in synthesis for all Terasic Development Boards and Altera Development
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9 | // Kits made by Terasic. Other use of this code, including the selling
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10 | // ,duplication, or modification of any portion is strictly prohibited.
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11 | //
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12 | // Disclaimer:
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13 | //
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14 | // This VHDL/Verilog or C/C++ source code is intended as a design reference
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15 | // which illustrates how these types of functions can be implemented.
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16 | // It is the user's responsibility to verify their design for
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17 | // consistency and functionality through the use of formal
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18 | // verification methods. Terasic provides no warranty regarding the use
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19 | // or functionality of this code.
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20 | //
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21 | // --------------------------------------------------------------------
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22 | //
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23 | // Terasic Technologies Inc
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24 | // E. Rd Sec. 1. JhuBei City,
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25 | // HsinChu County, Taiwan
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26 | // 302
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27 | //
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28 | // web: http://www.terasic.com/
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29 | // email: support@terasic.com
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30 | //
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31 | // --------------------------------------------------------------------
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32 |
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33 | module DE0_Nano(
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34 |
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35 | //////////// CLOCK //////////
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36 | CLOCK_50,
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37 |
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38 | //////////// LED //////////
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39 | LED,
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40 |
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41 | //////////// KEY //////////
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42 | KEY,
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43 |
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44 | //////////// SW //////////
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45 | SW,
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46 |
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47 | //////////// SDRAM //////////
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48 | DRAM_ADDR,
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49 | DRAM_BA,
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50 | DRAM_CAS_N,
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51 | DRAM_CKE,
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52 | DRAM_CLK,
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53 | DRAM_CS_N,
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54 | DRAM_DQ,
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55 | DRAM_DQM,
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56 | DRAM_RAS_N,
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57 | DRAM_WE_N,
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58 |
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59 | //////////// ECPS //////////
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60 | EPCS_ASDO,
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61 | EPCS_DATA0,
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62 | EPCS_DCLK,
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63 | EPCS_NCSO,
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64 |
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65 | //////////// Accelerometer and EEPROM //////////
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66 | G_SENSOR_CS_N,
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67 | G_SENSOR_INT,
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68 | I2C_SCLK,
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69 | I2C_SDAT,
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70 |
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71 | //////////// ADC //////////
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72 | ADC_CS_N,
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73 | ADC_SADDR,
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74 | ADC_SCLK,
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75 | ADC_SDAT,
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76 |
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77 | //////////// 2x13 GPIO Header //////////
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78 | GPIO_2,
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79 | GPIO_2_IN,
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80 |
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81 | //////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
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82 | GPIO_0,
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83 | GPIO_0_IN,
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84 |
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85 | //////////// GPIO_1, GPIO_1 connect to GPIO Default //////////
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86 | GPIO_1,
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87 | GPIO_1_IN
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88 | );
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89 |
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90 | //=======================================================
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91 | // PARAMETER declarations
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92 | //=======================================================
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93 |
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94 |
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95 | //=======================================================
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96 | // PORT declarations
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97 | //=======================================================
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98 |
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99 | //////////// CLOCK //////////
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100 | input CLOCK_50;
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101 |
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102 | //////////// LED //////////
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103 | output [7:0] LED;
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104 |
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105 | //////////// KEY //////////
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106 | input [1:0] KEY;
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107 |
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108 | //////////// SW //////////
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109 | input [3:0] SW;
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110 |
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111 | //////////// SDRAM //////////
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112 | output [12:0] DRAM_ADDR;
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113 | output [1:0] DRAM_BA;
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114 | output DRAM_CAS_N;
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115 | output DRAM_CKE;
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116 | output DRAM_CLK;
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117 | output DRAM_CS_N;
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118 | inout [15:0] DRAM_DQ;
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119 | output [1:0] DRAM_DQM;
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120 | output DRAM_RAS_N;
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121 | output DRAM_WE_N;
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122 |
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123 | //////////// EPCS //////////
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124 | output EPCS_ASDO;
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125 | input EPCS_DATA0;
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126 | output EPCS_DCLK;
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127 | output EPCS_NCSO;
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128 |
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129 | //////////// Accelerometer and EEPROM //////////
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130 | output G_SENSOR_CS_N;
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131 | input G_SENSOR_INT;
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132 | output I2C_SCLK;
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133 | inout I2C_SDAT;
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134 |
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135 | //////////// ADC //////////
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136 | output ADC_CS_N;
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137 | output ADC_SADDR;
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138 | output ADC_SCLK;
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139 | input ADC_SDAT;
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140 |
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141 | //////////// 2x13 GPIO Header //////////
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142 | inout [12:0] GPIO_2;
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143 | input [2:0] GPIO_2_IN;
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144 |
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145 | //////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
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146 | inout [33:0] GPIO_0;
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147 | input [1:0] GPIO_0_IN;
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148 |
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149 | //////////// GPIO_1, GPIO_1 connect to GPIO Default //////////
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150 | inout [33:0] GPIO_1;
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151 | input [1:0] GPIO_1_IN;
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152 |
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153 |
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154 | //=======================================================
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155 | // REG/WIRE declarations
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156 | //=======================================================
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157 | wire reset_n;
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158 | wire select_i2c_clk;
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159 | wire i2c_clk;
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160 | wire spi_clk;
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161 |
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162 |
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163 |
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164 | //=======================================================
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165 | // Structural coding
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166 | //=======================================================
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167 |
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168 | assign reset_n = 1'b1;
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169 |
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170 | DE0_Nano_SOPC DE0_Nano_SOPC_inst(
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171 | // 1) global signals:
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172 | .altpll_io(),
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173 | .altpll_sdram(DRAM_CLK),
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174 | .altpll_sys(),
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175 | .clk_50(CLOCK_50),
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176 | // .clk_50_clk_in_reset_reset_n(reset_n),
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177 | .clk_50_clk_in_reset_reset_n(KEY[0]),
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178 |
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179 | // the_select_i2c_clk
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180 | .out_port_from_the_select_i2c_clk(select_i2c_clk),
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181 |
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182 |
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183 | // the_adc_spi_read
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184 | .SPI_CLK_from_the_adc_spi_read(ADC_SCLK),
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185 | .SPI_CS_n_from_the_adc_spi_read(ADC_CS_N),
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186 | .SPI_IN_to_the_adc_spi_read(ADC_SDAT),
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187 | .SPI_OUT_from_the_adc_spi_read(ADC_SADDR),
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188 |
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189 |
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190 | // the_altpll_0
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191 | .locked_from_the_altpll_0(),
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192 | .phasedone_from_the_altpll_0(),
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193 |
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194 | // the_epcs
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195 | .data0_to_the_epcs(EPCS_DATA0),
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196 | .dclk_from_the_epcs(EPCS_DCLK),
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197 | .sce_from_the_epcs(EPCS_NCSO),
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198 | .sdo_from_the_epcs(EPCS_ASDO),
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199 |
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200 |
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201 | // the_gsensor_spi
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202 | .SPI_CS_n_from_the_gsensor_spi(G_SENSOR_CS_N),
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203 | .SPI_SCLK_from_the_gsensor_spi(spi_clk),
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204 | .SPI_SDIO_to_and_from_the_gsensor_spi(I2C_SDAT),
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205 |
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206 |
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207 | // the_g_sensor_int
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208 | .in_port_to_the_g_sensor_int(G_SENSOR_INT),
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209 |
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210 | // the_i2c_scl
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211 | .out_port_from_the_i2c_scl(i2c_clk),
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212 |
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213 | // the_i2c_sda
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214 | .bidir_port_to_and_from_the_i2c_sda(I2C_SDAT),
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215 |
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216 | // the_key
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217 | .in_port_to_the_key(KEY),
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218 |
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219 | // the_led
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220 | .out_port_from_the_led(LED),
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221 |
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222 | // the_sdram
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223 | .zs_addr_from_the_sdram(DRAM_ADDR),
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224 | .zs_ba_from_the_sdram(DRAM_BA),
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225 | .zs_cas_n_from_the_sdram(DRAM_CAS_N),
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226 | .zs_cke_from_the_sdram(DRAM_CKE),
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227 | .zs_cs_n_from_the_sdram(DRAM_CS_N),
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228 | .zs_dq_to_and_from_the_sdram(DRAM_DQ),
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229 | .zs_dqm_from_the_sdram(DRAM_DQM),
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230 | .zs_ras_n_from_the_sdram(DRAM_RAS_N),
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231 | .zs_we_n_from_the_sdram(DRAM_WE_N),
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232 |
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233 | // the_can_top_0-ch1
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234 | .can_top_0_conduit_end_rx_i(GPIO_2[2]),
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235 | .can_top_0_conduit_end_tx_o(GPIO_2[0]),
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236 |
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237 | // the_can_top_1-ch2
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238 | // .can_top_0_conduit_end_rx_i(GPIO_2[6]),
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239 | // .can_top_0_conduit_end_tx_o(GPIO_2[4]),
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240 |
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241 | // UART-ch1
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242 | .uart_0_external_connection_rxd(GPIO_2[12]),
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243 | .uart_0_external_connection_txd(GPIO_2[10]),
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244 |
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245 | // UART-ch2
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246 | // .uart_1_external_connection_rxd(GPIO_2[3]),
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247 | // .uart_1_external_connection_txd(GPIO_2[1]),
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248 | // .uart_1_external_connection_rxd(GPIO_0[24]),
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249 | // .uart_1_external_connection_txd(GPIO_0[25]),
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250 | .uart_1_external_connection_rxd(GPIO_1[2]),
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251 | .uart_1_external_connection_txd(GPIO_1[3]),
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252 |
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253 | // .pio_0_external_connection_export(GPIO_0[7:0]),
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254 | // .pio_0_external_connection_export(GPIO_1[15:8]),
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255 | .pio_0_external_connection_export(GPIO_1[31:24]),
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256 |
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257 | .multi_pwm_0_conduit_end_pwm1(GPIO_0[2]),
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258 | .multi_pwm_0_conduit_end_pwm2(GPIO_0[3]),
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259 | .multi_pwm_0_conduit_end_pwm3(GPIO_0[4]),
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260 | .multi_pwm_0_conduit_end_pwm4(GPIO_0[5]),
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261 | .multi_pwm_0_conduit_end_pwm5(GPIO_0[6]),
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262 | .multi_pwm_0_conduit_end_pwm6(GPIO_0[7]),
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263 |
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264 | // the_sw
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265 | .in_port_to_the_sw(SW)
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266 | );
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267 |
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268 |
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269 | assign I2C_SCLK = (select_i2c_clk)?i2c_clk:spi_clk;
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270 |
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271 | endmodule
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