source: azure_iot_hub_f767zi/trunk/asp_baseplatform/pdic/stm32f7xx/phyreg.h@ 457

Last change on this file since 457 was 457, checked in by coas-nagasima, 4 years ago

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1
2#ifndef _PHY_REG_
3#define _PHY_REG_
4
5#include <target_syssvc.h>
6
7/* Generic MII registers */
8#define MII_BMCR 0x00 /* Basic mode control register */
9#define MII_BMSR 0x01 /* Basic mode status register */
10#define MII_PHYSID1 0x02 /* PHYS ID 1 */
11#define MII_PHYSID2 0x03 /* PHYS ID 2 */
12#define MII_ADVERTISE 0x04 /* Advertisement control reg */
13#define MII_LPA 0x05 /* Link partner ability reg */
14#define MII_EXPANSION 0x06 /* Expansion register */
15#define MII_CTRL1000 0x09 /* 1000BASE-T control */
16#define MII_STAT1000 0x0a /* 1000BASE-T status */
17#define MII_ESTATUS 0x0f /* Extended Status */
18#define MII_SPECIFICCR 0x10 /* Specific control register */
19#define MII_DCOUNTER 0x12 /* Disconnect counter */
20#define MII_FCSCOUNTER 0x13 /* False carrier counter */
21#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
22#define MII_RERRCOUNTER 0x15 /* Receive error counter */
23#define MII_SREVISION 0x16 /* Silicon revision */
24#define MII_RESV1 0x17 /* Reserved... */
25#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
26#define MII_PHYADDR 0x19 /* PHY address */
27#define MII_RESV2 0x1a /* Reserved... */
28#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
29#define MII_NCONFIG 0x1c /* Network interface config */
30
31/* Basic mode control register. */
32#define BMCR_RESV 0x003f /* Unused... */
33#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
34#define BMCR_CTST 0x0080 /* Collision test */
35#define BMCR_FULLDPLX 0x0100 /* Full duplex */
36#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
37#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
38#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
39#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
40#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
41#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
42#define BMCR_RESET 0x8000 /* Reset the DP83840 */
43#define BMCR_SPEED10 0x0000 /* Select 10Mbps */
44
45/* Basic mode status register. */
46#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
47#define BMSR_JCD 0x0002 /* Jabber detected */
48#define BMSR_LSTATUS 0x0004 /* Link status */
49#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
50#define BMSR_RFAULT 0x0010 /* Remote fault detected */
51#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
52#define BMSR_RESV 0x00c0 /* Unused... */
53#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
54#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
55#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
56#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
57#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
58#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
59#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
60#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
61
62/* Advertisement control register. */
63#define ADVERTISE_SLCT 0x001f /* Selector bits */
64#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
65#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
66#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
67#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
68#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
69#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
70#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
71#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
72#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
73#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
74#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
75#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
76#define ADVERTISE_RESV 0x1000 /* Unused... */
77#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
78#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
79#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
80
81/* 1000BASE-T Control register */
82#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
83#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
84
85/* Link partner ability register. */
86#define LPA_SLCT 0x001f /* Same as advertise selector */
87#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
88#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
89#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
90#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
91#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
92#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
93#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
94#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym */
95#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
96#define LPA_PAUSE_CAP 0x0400 /* Can pause */
97#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
98#define LPA_RESV 0x1000 /* Unused... */
99#define LPA_RFAULT 0x2000 /* Link partner faulted */
100#define LPA_LPACK 0x4000 /* Link partner acked us */
101#define LPA_NPAGE 0x8000 /* Next page bit */
102
103#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
104#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
105
106/* 1000BASE-T Status register */
107#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */
108#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */
109#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */
110#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */
111
112/* Expansion register for auto-negotiation. */
113#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
114#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */
115#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
116#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */
117#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
118#define EXPANSION_RESV 0xffe0 /* Unused... */
119
120#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
121#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
122
123/* Specific control register */
124#define SPECIFICCR_CROSS_MASK 0x0060 /* Crossover mode mask */
125#define SPECIFICCR_CROSS_MDI 0x0000 /* Manual MDI configuration */
126#define SPECIFICCR_CROSS_MDIX 0x0020 /* Manual MDIX configuration */
127#define SPECIFICCR_CROSS_AUTO 0x0060 /* Enable automatic crossover */
128#define SPECIFICCR_INT_DISABLE 0x1000 /* Interrupt Disable */
129
130/* Externded PHY Specific Control Register */
131#define NWAYTEST_RGMII_RTC 0x0080 /* RGMII Receive Timing Control */
132#define NWAYTEST_RGMII_TTC 0x0002 /* RGMII Transmit Timing Control */
133
134#endif /* _PHY_REG_ */
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