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test_cpuexc11.c@ 61

Last change on this file since 61 was 61, checked in by ertl-honda, 11 years ago
ASP for EWARM のコミット．
File size: 6.7 KB

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1	/*
2	* TOPPERS Software
3	* Toyohashi Open Platform for Embedded Real-Time Systems
4	*
5	* Copyright (C) 2007-2009 by Embedded and Real-Time Systems Laboratory
6	* Graduate School of Information Science, Nagoya Univ., JAPAN
7	*
8	* ãLì ÒÍCÈºÌ(1)`(4)Ìðð½·êÉÀèC{\tgEF
9	* Ai{\tgEFAðüÏµ½àÌðÜÞDÈº¯¶jðgpE¡»Eü
10	* ÏEÄzziÈºCpÆÄÔj·é±Æð³Åø·éD
11	* (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
12	* \¦C±Ìpð¨æÑºLÌ³ÛØKèªC»ÌÜÜÌ`Å\[
13	* XR[hÉÜÜêÄ¢é±ÆD
14	* (2) {\tgEFAðCCu`®ÈÇC¼Ì\tgEFAJÉg
15	* pÅ«é`ÅÄzz·éêÉÍCÄzzÉº¤hL
16	gip
17	* Ò}j
18	AÈÇjÉCãLÌì \¦C±Ìpð¨æÑºL
19	* Ì³ÛØKèðfÚ·é±ÆD
20	* (3) {\tgEFAðC@íÉgÝÞÈÇC¼Ì\tgEFAJÉg
21	* pÅ«È¢`ÅÄzz·éêÉÍCÌ¢¸ê©Ìðð½·±
22	* ÆD
23	* (a) ÄzzÉº¤hL
24	gipÒ}j
25	AÈÇjÉCãLÌ
26	* ì \¦C±Ìpð¨æÑºLÌ³ÛØKèðfÚ·é±ÆD
27	* (b) ÄzzÌ`ÔðCÊÉèßéû@ÉæÁÄCTOPPERSvWFNgÉ
28	* ñ·é±ÆD
29	* (4) {\tgEFAÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶é¢©Èé¹
30	* Q©çàCãLì Ò¨æÑTOPPERSvWFNgðÆÓ·é±ÆD
31	* Ü½C{\tgEFAÌ[UÜ½ÍGh[U©çÌ¢©Èé
32	* RÉîÃ¿©çàCãLì Ò¨æÑTOPPERSvWFNgð
33	* ÆÓ·é±ÆD
34	*
35	* {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì Ò¨
36	* æÑTOPPERSvWFNgÍC{\tgEFAÉÖµÄCÁèÌgpÚI
37	* ÉÎ·éK«àÜßÄC¢©ÈéÛØàsíÈ¢DÜ½C{\tgEF
38	* AÌpÉæè¼ÚIÜ½ÍÔÚIÉ¶¶½¢©Èé¹QÉÖµÄàC»
39	* ÌÓCðíÈ¢D
40	*
41	* @(#) $Id: test_cpuexc11.c 2005 2010-12-31 04:20:08Z ertl-hiro $
42	*/
43
44	/*
45	* CPUáOÌeXg(11)
46	*
47	* yeXgÌÚIz
48	*
49	* ÝDæx}XNTIPM_ENAALLCfBXpb`ÂóÔC^XNáO
50	* ÂóÔÅ¶µ½CPUáOÉ¨¯éVXeóÔÌeXgD^XNØ·¦É
51	* æèJo[Å«é±ÆàeXg·éD
52	*
53	* yeXgÚz
54	*
55	* ¢¸êàCÝDæx}XNTIPM_ENAALLCfBXpb`ÂóÔC^
56	* XNáOÂóÔÅ¶µ½CPUáOÉ¨¢ÄC
57	*
58	* (A) CPUáOnhÀsJnÉCPUbNtOªÏ»µÈ¢±Æ
59	* (B) CPUáOnhÀsJnÉÝDæx}XNªÏ»µÈ¢±Æ
60	* ICPUáOnhÅÝDæx}XNðÇßÈ¢½ßCeXgÅ
61	* «È¢D
62	* (C) CPUáOnhÀsJnÉfBXpb`Ö~tOªÏ»µÈ¢±Æ
63	* (D) CPUáOnhÀsJnÉ^XNáOÖ~tOªÏ»µÈ¢±Æ
64	* (E) CPUáOnh^[ÉCPUbNtOª³Éßé±Æ
65	* (F) CPUáOnh^[ÉÝDæx}XNª³Éßé±Æ
66	* (G) CPUáOnh^[ÉfBXpb`Ö~tOªÏ»µÈ¢±Æ
67	* (H) CPUáOnh^[É^XNáOÖ~tOªÏ»µÈ¢±Æ
68	* (I) xsns_xpnªfalseðÔ·±Æ
69	* (J) xsns_dpnªfalseðÔ·±Æ
70	* (K) ^XNØ·¦ÉæéJo[ªÅ«é±Æ
71	* (L) ^XNáOÉæéJo[ªÅ«é±Æ
72	*
73	* ygp\[Xz
74	*
75	* TASK1: TA_ACTCDæxC^XNáO[`o^
76	* TASK2: TA_NULLCDæx
77	* CPUEXC1: TA_NULL
78	*
79	* yeXgV[PXz
80	*
81	* == TASK1iDæxC1ñÚj==
82	* 1: óÔÌ`FbN
83	* ena_tex()
84	* 2: óÔÌ`FbN
85	* RAISE_CPU_EXCEPTION
86	* == CPUEXC1i1ñÚj==
87	* 3: óÔÌ`FbN ... (A)(C)(D)
88	* xsns_xpn() == false ... (I)
89	* xsns_dpn() == false ... (J)
90	* 4: iact_tsk(TASK2)
91	* iloc_cpu()
92	* ^[
93	* == TASK2iDæxj==
94	* 5: óÔÌ`FbN ... (E)(F)(G)(H)
95	* 6: ter_tsk(TASK1) ... (K)
96	* 7: act_tsk(TASK1) ... (K)
97	* 8: ext_tsk()
98	* == TASK1iDæxC2ñÚj==
99	* 9: óÔÌ`FbN ... (K)
100	* ena_tex()
101	* 10: óÔÌ`FbN
102	* RAISE_CPU_EXCEPTION
103	* == CPUEXC1i2ñÚj==
104	* 11: óÔÌ`FbN ... (A)(C)(D)
105	* xsns_xpn() == false ... (I)
106	* xsns_dpn() == false ... (J)
107	* 12: iras_tex(TASK1, 1U)
108	* iloc_cpu()
109	* ^[
110	* == TASK1Ì^XNáO[` ==
111	* 13: óÔÌ`FbN ... (E)(F)(G)(H)
112	* 14: act_tsk(TASK1) ... (L)
113	* 15: ext_tsk() ... (L)
114	* == TASK1iDæxC3ñÚj==
115	* 16: óÔÌ`FbN ... (L)
116	* 17: eXgI¹
117	*/
118
119	#include <kernel.h>
120	#include <test_lib.h>
121	#include <t_syslog.h>
122	#include "kernel_cfg.h"
123	#include "test_cpuexc.h"
124
125	int_t task1_count = 0;
126
127	void
128	task1(intptr_t exinf)
129	{
130	ER ercd;
131
132	switch (++task1_count) {
133	case 1:
134	check_point(1);
135	check_state(false, false, TIPM_ENAALL, false, false, true);
136	ercd = ena_tex();
137	check_ercd(ercd, E_OK);
138
139	check_point(2);
140	check_state(false, false, TIPM_ENAALL, false, false, false);
141	RAISE_CPU_EXCEPTION;
142
143	check_point(0);
144	break;
145
146	case 2:
147	check_point(9);
148	check_state(false, false, TIPM_ENAALL, false, false, true);
149	ercd = ena_tex();
150	check_ercd(ercd, E_OK);
151
152	check_point(10);
153	check_state(false, false, TIPM_ENAALL, false, false, false);
154	RAISE_CPU_EXCEPTION;
155
156	check_point(0);
157	break;
158
159	case 3:
160	check_point(16);
161	check_state(false, false, TIPM_ENAALL, false, false, true);
162
163	check_finish(17);
164	break;
165
166	default:
167	check_point(0);
168	break;
169	}
170	}
171
172	void
173	tex_task1(TEXPTN texptn, intptr_t exinf)
174	{
175	ER ercd;
176
177	check_point(13);
178	check_state(false, false, TIPM_ENAALL, false, false, true);
179
180	check_point(14);
181	ercd = act_tsk(TASK1);
182	check_ercd(ercd, E_OK);
183
184	check_point(15);
185	ercd = ext_tsk();
186	check_ercd(ercd, E_OK);
187
188	check_point(0);
189	}
190
191	void
192	task2(intptr_t exinf)
193	{
194	ER ercd;
195
196	check_point(5);
197	check_state(false, false, TIPM_ENAALL, false, false, true);
198
199	check_point(6);
200	ercd = ter_tsk(TASK1);
201	check_ercd(ercd, E_OK);
202
203	check_point(7);
204	ercd = act_tsk(TASK1);
205	check_ercd(ercd, E_OK);
206
207	check_point(8);
208	ercd = ext_tsk();
209	check_ercd(ercd, E_OK);
210
211	check_point(0);
212	}
213
214	void
215	alarm1_handler(intptr_t exinf)
216	{
217	check_point(0);
218	}
219
220	int_t cpuexc_count = 0;
221
222	void
223	cpuexc_handler(void *p_excinf)
224	{
225	ER ercd;
226
227	switch (++cpuexc_count) {
228	case 1:
229	check_point(3);
230	check_state_i(true, false, false, true, false);
231	check_assert(xsns_xpn(p_excinf) == false);
232	check_assert(xsns_dpn(p_excinf) == false);
233
234	check_point(4);
235	ercd = iact_tsk(TASK2);
236	check_ercd(ercd, E_OK);
237	ercd = iloc_cpu();
238	check_ercd(ercd, E_OK);
239	break;
240
241	case 2:
242	check_point(11);
243	check_state_i(true, false, false, true, false);
244	check_assert(xsns_xpn(p_excinf) == false);
245	check_assert(xsns_dpn(p_excinf) == false);
246
247	check_point(12);
248	ercd = iras_tex(TASK1, 1U);
249	check_ercd(ercd, E_OK);
250	ercd = iloc_cpu();
251	check_ercd(ercd, E_OK);
252	break;
253
254	default:
255	check_point(0);
256	break;
257	}
258	}

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source: asp_ewarm/asp-1.7.0/test/test_cpuexc11.c@ 61

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