1 | /*
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2 | * TOPPERS/JSP Kernel
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3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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4 | * Just Standard Profile Kernel
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5 | *
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6 | * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
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7 | * Toyohashi Univ. of Technology, JAPAN
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8 | * Copyright (C) 2005-2007 by Embedded and Real-Time Systems Laboratory
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9 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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10 | *
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11 | * ãLì ÒÍCFree Software Foundation ÉæÁÄö\³êÄ¢é
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12 | * GNU General Public License Ì Version 2 ÉLq³êÄ¢éð©CÈ
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13 | * ºÌ(1)`(4)Ìðð½·êÉÀèC{\tgEFAi{\tgEF
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14 | * Aðüϵ½àÌðÜÞDȺ¯¶jðgpE¡»EüÏEÄzziȺC
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15 | * pÆÄÔj·é±Æð³Åø·éD
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16 | * (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
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17 | * \¦C±Ìpð¨æѺL̳ÛØKèªC»ÌÜÜÌ`Å\[
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18 | * XR[hÉÜÜêÄ¢é±ÆD
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19 | * (2) {\tgEFAðÄpÂ\ÈoCiR[hiP[^uIu
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20 | * WFNgt@CâCuÈÇjÌ`Åp·éêÉÍCp
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21 | * ɺ¤hL
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22 | gipÒ}j
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23 | AÈÇjÉCãLÌì \¦C
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24 | * ±Ìpð¨æѺL̳ÛØKèðfÚ·é±ÆD
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25 | * (3) {\tgEFAðÄpsÂ\ÈoCiR[hÌ`ܽÍ@íÉg
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26 | * Ýñ¾`Åp·éêÉÍCÌ¢¸ê©Ìðð½·±ÆD
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27 | * (a) pɺ¤hL
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28 | gipÒ}j
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29 | AÈÇjÉCãLÌì
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30 | * \¦C±Ìpð¨æѺL̳ÛØKèðfÚ·é±ÆD
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31 | * (b) pÌ`ÔðCÊÉèßéû@ÉæÁÄCãLì ÒÉñ·é
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32 | * ±ÆD
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33 | * (4) {\tgEFAÌpÉæè¼ÚIܽÍÔÚIɶ¶é¢©Èé¹
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34 | * Q©çàCãLì ÒðÆÓ·é±ÆD
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35 | *
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36 | * {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì ÒÍC
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37 | * {\tgEFAÉÖµÄC»ÌKpÂ\«àÜßÄC¢©ÈéÛØàsí
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38 | * È¢DܽC{\tgEFAÌpÉæè¼ÚIܽÍÔÚIɶ¶½¢
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39 | * ©Èé¹QÉÖµÄàC»ÌÓCðíÈ¢D
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40 | *
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41 | */
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42 | #ifndef TOPPERS_CQ_STARM_H
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43 | #define TOPPERS_CQ_STARM_H
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44 |
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45 | #include <sil.h>
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46 |
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47 | /*
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48 | * CORTEX-M3 CPUÌ˶ÌCN[h
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49 | */
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50 | #include "arm_m_iccarm/arm_m.h"
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51 |
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52 | /*
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53 | * VXeNbNÌè`iUqüg8MHzj
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54 | */
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55 | #define HSE_CLOCK (8000000)
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56 | #define SYS_CLOCK (HSE_CLOCK * 3)
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57 | #define PCLK1_CLOCK (HSE_CLOCK * 3)
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58 | #define PCLK2_CLOCK (HSE_CLOCK * 3)
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59 |
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60 | /*
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61 | * ÝÔÌÅål
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62 | */
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63 | #define TMAX_INTNO (16 + 60)
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64 |
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65 | /*
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66 | * ÝDæxÌrbg
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67 | */
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68 | #define TBITW_IPRI 4
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69 |
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70 | /*
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71 | * ÝDæxrbgÌTuDæxÌrbg
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72 | */
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73 | #define TBITW_SUBIPRI 0
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74 |
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75 | /*
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76 | * ÝxN^Ôè`
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77 | */
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78 | #define IRQ_VECTOR_USART1 (16 + 37)
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79 |
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80 |
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81 | /* STM32F10XÌytFWX^è` */
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82 | #define PERIPH_REG_BASE (0x40000000UL)
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83 | #define SRAM_BASE (0x20000000UL)
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84 |
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85 | #define APB1_PERIPH (PERIPH_REG_BASE)
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86 | #define APB2_PERIPH (PERIPH_REG_BASE + 0x10000)
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87 | #define AHB_PERIPH (PERIPH_REG_BASE + 0x20000)
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88 |
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89 | /* BUS:APB1 */
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90 | #define TIM2_BASE (APB1_PERIPH)
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91 | #define TIM3_BASE (APB1_PERIPH + 0x400)
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92 | #define TIM4_BASE (APB1_PERIPH + 0x800)
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93 | #define TIM6_BASE (APB1_PERIPH + 0x1000)
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94 | #define TIM7_BASE (APB1_PERIPH + 0x1400)
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95 | #define RTC_BASE (APB1_PERIPH + 0x2800)
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96 | #define WWDG_BASE (APB1_PERIPH + 0x2C00)
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97 | #define IWDG_BASE (APB1_PERIPH + 0x3000)
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98 | #define SPI2_BASE (APB1_PERIPH + 0x3800)
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99 | #define USART2_BASE (APB1_PERIPH + 0x4400)
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100 | #define USART3_BASE (APB1_PERIPH + 0x4800)
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101 | #define I2C1_BASE (APB1_PERIPH + 0x5400)
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102 | #define I2C2_BASE (APB1_PERIPH + 0x5800)
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103 | #define BKP_BASE (APB1_PERIPH + 0x6C00)
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104 | #define PWR_BASE (APB1_PERIPH + 0x7000)
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105 | #define DAC_BASE (APB1_PERIPH + 0x7400)
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106 | #define CEC_BASE (APB1_PERIPH + 0x7800)
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107 |
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108 | /* BUS:APB2 */
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109 | #define AFIO_BASE (APB2_PERIPH)
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110 | #define EXTI_BASE (APB2_PERIPH + 0x400)
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111 | #define GPIOA_BASE (APB2_PERIPH + 0x800)
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112 | #define GPIOB_BASE (APB2_PERIPH + 0xC00)
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113 | #define GPIOC_BASE (APB2_PERIPH + 0x1000)
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114 | #define GPIOD_BASE (APB2_PERIPH + 0x1400)
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115 | #define GPIOE_BASE (APB2_PERIPH + 0x1800)
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116 | #define ADC1_BASE (APB2_PERIPH + 0x2400)
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117 | #define TIM1_BASE (APB2_PERIPH + 0x2C00)
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118 | #define SPI1_BASE (APB2_PERIPH + 0x3000)
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119 | #define USART1_BASE (APB2_PERIPH + 0x3800)
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120 | #define TIM15_BASE (APB2_PERIPH + 0x4000)
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121 | #define TIM16_BASE (APB2_PERIPH + 0x4400)
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122 | #define TIM17_BASE (APB2_PERIPH + 0x4800)
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123 |
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124 | /* BUS:AHB */
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125 | #define DMA_BASE (AHB_PERIPH)
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126 | #define RCC_BASE (AHB_PERIPH + 0x1000)
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127 | #define FLASH_BASE (AHB_PERIPH + 0x2000)
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128 | #define CRC_BASE (AHB_PERIPH + 0x3000)
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129 |
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130 | /* System Control space */
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131 | #define SCS_BASE (0xE000E000)
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132 | #define SYSTM_BASE (SCS_BASE + 0x0010)
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133 | #define NVIC_BASE (SCS_BASE + 0x0100)
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134 | #define SYSCB_BASE (SCS_BASE + 0x0D00)
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135 |
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136 | /* RCC */
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137 | #define RCC_CR (RCC_BASE)
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138 | #define RCC_CFGR (RCC_BASE + 0x04)
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139 | #define RCC_CIR (RCC_BASE + 0x08)
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140 | #define RCC_APB2RSTR (RCC_BASE + 0x0C)
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141 | #define RCC_APB1RSTR (RCC_BASE + 0x10)
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142 | #define RCC_AHBENR (RCC_BASE + 0x14)
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143 | #define RCC_APB2ENR (RCC_BASE + 0x18)
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144 | #define RCC_APB1ENR (RCC_BASE + 0x1C)
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145 | #define RCC_BDCR (RCC_BASE + 0x20)
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146 | #define RCC_CSR (RCC_BASE + 0x24)
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147 | #define RCC_CFGR2 (RCC_BASE + 0x2C)
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148 |
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149 | /* NVIC */
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150 | #define NVIC_ENAVLE_REG(ch) (NVIC_BASE + ((ch) >> 5))
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151 | #define NVIC_DISABLE_REG(ch) (NVIC_BASE + 0x80 + ((ch) >> 5))
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152 | #define NVIC_SET_PEND_REG(ch) (NVIC_BASE + 0x100 + ((ch) >> 5))
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153 | #define NVIC_CLEAR_PEND_REG(ch) (NVIC_BASE + 0x180 + ((ch) >> 5))
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154 | #define NVIC_ACTIVE_REG(ch) (NVIC_BASE + 0x200 + ((ch) >> 5))
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155 | #define NVIC_PRIO_REG(ch) (NVIC_BASE + 0x300 + ((ch) >> 2))
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156 |
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157 | /* GPIOx */
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158 | #define GPIO_CRL(x) (x)
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159 | #define GPIO_CRH(x) ((x) + 0x04)
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160 | #define GPIO_IDR(x) ((x) + 0x08)
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161 | #define GPIO_ODR(x) ((x) + 0x0C)
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162 | #define GPIO_BSRR(x) ((x) + 0x10)
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163 | #define GPIO_BRR(x) ((x) + 0x14)
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164 | #define GPIO_LCKR(x) ((x) + 0x18)
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165 |
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166 | /* AFIO */
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167 | #define AFIO_EVCR (AFIO_BASE)
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168 | #define AFIO_MAPR (AFIO_BASE + 0x04)
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169 | #define AFIO_EXTICR1 (AFIO_BASE + 0x08)
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170 | #define AFIO_EXTICR2 (AFIO_BASE + 0x0C)
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171 | #define AFIO_EXTICR3 (AFIO_BASE + 0x10)
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172 | #define AFIO_EXTICR4 (AFIO_BASE + 0x14)
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173 | #define AFIO_MAPR2 (AFIO_BASE + 0x0C)
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174 |
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175 | /* FLASH */
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176 | #define FLASH_ACR (FLASH_BASE)
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177 |
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178 | /* RCCWX^è` */
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179 | #define CR_PLL_RDY (0x02000000)
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180 | #define CR_PLL_ON (0x01000000)
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181 | #define CR_HSE_RDY (0x00020000)
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182 | #define CR_HSE_ON (0x00010000)
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183 | #define CR_HSI_RDY (0x00000002)
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184 | #define CR_HSI_ON (0x00000001)
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185 | #define CFGR_PLLMUL_MASK (0x003C0000)
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186 | #define CFGR_PLL_XTPRE (0x00020000)
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187 | #define CFGR_PLL_SRC (0x00010000)
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188 | #define CFGR_HPRE_MASK (0x000000F0)
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189 | #define CFGR_PPRE2_MASK (0x00003800)
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190 | #define CFGR_PPRE1_MASK (0x00000700)
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191 | #define CFGR_SWS_MASK (0x0000000C)
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192 | #define CFGR_SW_MASK (0x00000003)
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193 | #define CFGR_SW_PLL (0x02)
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194 | #define APB2ENR_ADC3_EN (0x8000)
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195 | #define APB2ENR_USART1_EN (0x4000)
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196 | #define APB2ENR_TIM8_EN (0x2000)
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197 | #define APB2ENR_SPI1_EN (0x1000)
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198 | #define APB2ENR_TIM1_EN (0x0800)
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199 | #define APB2ENR_ADC2_EN (0x0400)
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200 | #define APB2ENR_ADC1_EN (0x0200)
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201 | #define APB2ENR_IOPG_EN (0x0100)
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202 | #define APB2ENR_IOPF_EN (0x0080)
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203 | #define APB2ENR_IOPE_EN (0x0040)
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204 | #define APB2ENR_IOPD_EN (0x0020)
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205 | #define APB2ENR_IOPC_EN (0x0010)
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206 | #define APB2ENR_IOPB_EN (0x0008)
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207 | #define APB2ENR_IOPA_EN (0x0004)
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208 | #define APB2ENR_AFIO_EN (0x0001)
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209 | #define AHBENR_SDIO_EN (0x0400)
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210 | #define AHBENR_FSMC_EN (0x0100)
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211 | #define AHBENR_CRCE_EN (0x0040)
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212 | #define AHBENR_FLITF_EN (0x0010)
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213 | #define AHBENR_SRAM_EN (0x0004)
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214 | #define AHBENR_DMA_EN (0x0001)
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215 |
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216 | /* FLASHWX^è` */
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217 | #define ACR_LATENCY_MASK (0x07)
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218 | #define ACR_LATENCY_ZERO (0x00)
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219 | #define ACR_LATENCY_ONE (0x01)
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220 | #define ACR_LATENCY_TWO (0x02)
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221 |
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222 | /* GPIOxWX^è` */
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223 | #define CNF_IN_ANALOG (0x00)
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224 | #define CNF_IN_FLOATING (0x01)
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225 | #define CNF_IN_PULL (0x02)
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226 | #define CNF_OUT_GP_PP (0x00)
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227 | #define CNF_OUT_GP_OD (0x01)
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228 | #define CNF_OUT_AF_PP (0x02)
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229 | #define CNF_OUT_AF_OD (0x03)
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230 | #define MODE_INPUT (0x00)
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231 | #define MODE_OUTPUT_10MHZ (0x01)
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232 | #define MODE_OUTPUT_2MHZ (0x02)
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233 | #define MODE_OUTPUT_50MHZ (0x03)
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234 |
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235 | #define CR_MODE_MASK(x) (0x03 << ((x) << 2))
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236 | #define CR_CNF_MASK(x) (0x0C << ((x) << 2))
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237 | #define CR_MODE(x,v) (((v) & 0x03) << ((x) << 2))
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238 | #define CR_CNF(x,v) ((((v) << 2) & 0x0C) << ((x) << 2))
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239 |
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240 | #ifndef TOPPERS_MACRO_ONLY
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241 |
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242 | #endif /* TOPPERS_MACRO_ONLY */
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243 | #endif /* TOPPERS_CQ_STARM_H */
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