1 | /*
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2 | * TOPPERS/JSP Kernel
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3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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4 | * Just Standard Profile Kernel
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5 | *
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6 | * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
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7 | * Toyohashi Univ. of Technology, JAPAN
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8 | * Copyright (C) 2005-2007 by Embedded and Real-Time Systems Laboratory
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9 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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10 | *
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11 | * ãLì ÒÍCFree Software Foundation ÉæÁÄö\³êÄ¢é
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12 | * GNU General Public License Ì Version 2 ÉLq³êÄ¢éð©CÈ
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13 | * ºÌ(1)`(4)Ìðð½·êÉÀèC{\tgEFAi{\tgEF
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14 | * Aðüϵ½àÌðÜÞDȺ¯¶jðgpE¡»EüÏEÄzziȺC
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15 | * pÆÄÔj·é±Æð³Åø·éD
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16 | * (1) {\tgEFAð\[XR[hÌ`Åp·éêÉÍCãLÌì
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17 | * \¦C±Ìpð¨æѺL̳ÛØKèªC»ÌÜÜÌ`Å\[
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18 | * XR[hÉÜÜêÄ¢é±ÆD
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19 | * (2) {\tgEFAðÄpÂ\ÈoCiR[hiP[^uIu
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20 | * WFNgt@CâCuÈÇjÌ`Åp·éêÉÍCp
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21 | * ɺ¤hL
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22 | gipÒ}j
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23 | AÈÇjÉCãLÌì \¦C
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24 | * ±Ìpð¨æѺL̳ÛØKèðfÚ·é±ÆD
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25 | * (3) {\tgEFAðÄpsÂ\ÈoCiR[hÌ`ܽÍ@íÉg
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26 | * Ýñ¾`Åp·éêÉÍCÌ¢¸ê©Ìðð½·±ÆD
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27 | * (a) pɺ¤hL
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28 | gipÒ}j
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29 | AÈÇjÉCãLÌì
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30 | * \¦C±Ìpð¨æѺL̳ÛØKèðfÚ·é±ÆD
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31 | * (b) pÌ`ÔðCÊÉèßéû@ÉæÁÄCãLì ÒÉñ·é
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32 | * ±ÆD
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33 | * (4) {\tgEFAÌpÉæè¼ÚIܽÍÔÚIɶ¶é¢©Èé¹
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34 | * Q©çàCãLì ÒðÆÓ·é±ÆD
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35 | *
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36 | * {\tgEFAÍC³ÛØÅñ³êÄ¢éàÌÅ éDãLì ÒÍC
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37 | * {\tgEFAÉÖµÄC»ÌKpÂ\«àÜßÄC¢©ÈéÛØàsí
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38 | * È¢DܽC{\tgEFAÌpÉæè¼ÚIܽÍÔÚIɶ¶½¢
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39 | * ©Èé¹QÉÖµÄàC»ÌÓCðíÈ¢D
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40 | *
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41 | */
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42 | #ifndef TOPPERS_CQ_STARM_H
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43 | #define TOPPERS_CQ_STARM_H
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44 |
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45 | #include <sil.h>
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46 |
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47 | /*
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48 | * CORTEX-M3 CPUÌ˶ÌCN[h
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49 | */
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50 | #include "arm_m_iccarm/arm_m.h"
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51 |
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52 | /*
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53 | * VXeNbNÌè`
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54 | */
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55 | #define BUS_CLOCK (60000000)
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56 | #define SYS_CLOCK (120000000)
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57 | #define FLASH_CLOCK (20000000)
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58 | #define DDR_CLOCK (150000000)
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59 |
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60 | /*
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61 | * ÝÔÌÅål
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62 | */
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63 | #define TMAX_INTNO (16 + 105)
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64 |
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65 | /*
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66 | * ÝDæxÌrbg
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67 | */
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68 | #define TBITW_IPRI 4
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69 |
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70 | /*
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71 | * ÝDæxrbgÌTuDæxÌrbg
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72 | */
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73 | #define TBITW_SUBIPRI 0
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74 |
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75 | /*
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76 | * ÝxN^Ôè`
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77 | */
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78 | #define IRQ_VECTOR_USART2 (16 + 49)
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79 |
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80 |
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81 | /* ytFWX^è` */
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82 | #define PERIPH_REG_BASE (0x40000000UL)
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83 | #define SRAM_BASE (0x1FFF0000UL)
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84 |
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85 |
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86 | #define SIM_BASE (PERIPH_REG_BASE + 0x47000)
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87 | #define PORTA_BASE (PERIPH_REG_BASE + 0x49000)
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88 | #define PORTE_BASE (PERIPH_REG_BASE + 0x4D000)
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89 | #define WDOG_BASE (PERIPH_REG_BASE + 0x52000)
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90 | #define MCG_BASE (PERIPH_REG_BASE + 0x64000)
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91 | #define UART2_BASE (PERIPH_REG_BASE + 0x6C000)
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92 | #define PMC_BASE (PERIPH_REG_BASE + 0x7D000)
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93 | #define GPIOA_BASE (PERIPH_REG_BASE + 0xFF000)
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94 |
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95 |
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96 | /* System Control space */
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97 | #define SCS_BASE (0xE000E000)
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98 | #define SYSTM_BASE (SCS_BASE + 0x0010)
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99 | #define NVIC_BASE (SCS_BASE + 0x0100)
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100 | #define SYSCB_BASE (SCS_BASE + 0x0D00)
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101 |
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102 | /* WDOG */
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103 | #define WDOG_STCTRTLH (WDOG_BASE + 0x00)
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104 | #define WDOG_UNLOCK (WDOG_BASE + 0x0E)
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105 |
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106 | /* SIM */
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107 | #define SIM_SCGC4 (SIM_BASE + 0x1034)
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108 | #define SIM_SCGC5 (SIM_BASE + 0x1038)
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109 | #define SIM_CLKDIV1 (SIM_BASE + 0x1044)
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110 |
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111 | /* PMC */
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112 | #define PMC_REGSC (PMC_BASE + 0x02)
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113 |
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114 | /* PORT_A */
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115 | #define PORTA_PCR10 (PORTA_BASE + 0x28)
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116 | #define PORTA_PCR11 (PORTA_BASE + 0x2C)
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117 | #define PORTA_PCR28 (PORTA_BASE + 0x70)
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118 | #define PORTA_PCR29 (PORTA_BASE + 0x74)
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119 |
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120 | /* PORT_E */
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121 | #define PORTE_PCR16 (PORTE_BASE + 0x40)
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122 | #define PORTE_PCR17 (PORTE_BASE + 0x44)
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123 |
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124 | /* GPIO_A */
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125 | #define GPIOA_PSOR (GPIOA_BASE + 0x04)
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126 | #define GPIOA_PCOR (GPIOA_BASE + 0x08)
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127 | #define GPIOA_PTOR (GPIOA_BASE + 0x0C)
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128 | #define GPIOA_PDDR (GPIOA_BASE + 0x14)
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129 |
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130 | /* MCG */
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131 | #define MCG_C1 (MCG_BASE + 0x00)
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132 | #define MCG_C2 (MCG_BASE + 0x01)
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133 | #define MCG_C5 (MCG_BASE + 0x04)
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134 | #define MCG_C6 (MCG_BASE + 0x05)
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135 | #define MCG_S (MCG_BASE + 0x06)
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136 | #define MCG_C11 (MCG_BASE + 0x10)
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137 | #define MCG_C12 (MCG_BASE + 0x11)
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138 | #define MCG_S2 (MCG_BASE + 0x12)
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139 |
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140 | /* UART2 */
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141 | #define UART2_BDH (UART2_BASE + 0x00)
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142 | #define UART2_BDL (UART2_BASE + 0x01)
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143 | #define UART2_C1 (UART2_BASE +0x02)
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144 | #define UART2_C2 (UART2_BASE + 0x03)
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145 | #define UART2_S1 (UART2_BASE + 0x04)
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146 | #define UART2_D (UART2_BASE + 0x07)
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147 | #define UART2_C4 (UART2_BASE + 0x0A)
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148 |
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149 | /* SCB */
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150 | #define SCB_VTOR (SYSCB_BASE + 0x08)
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151 | #define SCB_AIRCR (SYSCB_BASE + 0x0C)
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152 | #define SCB_SHPR3 (SYSCB_BASE + 0x20)
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153 |
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154 | /* NVIC */
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155 | #define NVIC_ENAVLE_REG(ch) (NVIC_BASE + ((ch) >> 5))
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156 | #define NVIC_DISABLE_REG(ch) (NVIC_BASE + 0x80 + ((ch) >> 5))
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157 | #define NVIC_SET_PEND_REG(ch) (NVIC_BASE + 0x100 + ((ch) >> 5))
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158 | #define NVIC_CLEAR_PEND_REG(ch) (NVIC_BASE + 0x180 + ((ch) >> 5))
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159 | #define NVIC_ACTIVE_REG(ch) (NVIC_BASE + 0x200 + ((ch) >> 5))
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160 | #define NVIC_PRIO_REG(ch) (NVIC_BASE + 0x300 + ((ch) >> 2))
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161 | #define NVIC_STIR (NVIC_BASE+0xE00)
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162 |
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163 |
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164 | #ifndef TOPPERS_MACRO_ONLY
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165 |
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166 | #endif /* TOPPERS_MACRO_ONLY */
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167 | #endif /* TOPPERS_CQ_STARM_H */
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