1 | /*
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2 | * TOPPERS/ASP Kernel
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3 | * Toyohashi Open Platform for Embedded Real-Time Systems/
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4 | * Advanced Standard Profile Kernel
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5 | *
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6 | * Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
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7 | * Toyohashi Univ. of Technology, JAPAN
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8 | * Copyright (C) 2005-2014 by Embedded and Real-Time Systems Laboratory
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9 | * Graduate School of Information Science, Nagoya Univ., JAPAN
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10 | *
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11 | * ä¸è¨èä½æ¨©è
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12 | ã¯ï¼ä»¥ä¸ã®(1)ã(4)ã®æ¡ä»¶ãæºããå ´åã«éãï¼æ¬ã½ããã¦ã§
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13 | * ã¢ï¼æ¬ã½ããã¦ã§ã¢ãæ¹å¤ãããã®ãå«ãï¼ä»¥ä¸åãï¼ã使ç¨ã»è¤è£½ã»æ¹
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14 | * å¤ã»åé
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15 | å¸ï¼ä»¥ä¸ï¼å©ç¨ã¨å¼ã¶ï¼ãããã¨ãç¡åã§è¨±è«¾ããï¼
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16 | * (1) æ¬ã½ããã¦ã§ã¢ãã½ã¼ã¹ã³ã¼ãã®å½¢ã§å©ç¨ããå ´åã«ã¯ï¼ä¸è¨ã®èä½
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17 | * 権表示ï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãï¼ãã®ã¾ã¾ã®å½¢ã§ã½ã¼
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18 | * ã¹ã³ã¼ãä¸ã«å«ã¾ãã¦ãããã¨ï¼
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19 | * (2) æ¬ã½ããã¦ã§ã¢ãï¼ã©ã¤ãã©ãªå½¢å¼ãªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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20 | * ç¨ã§ããå½¢ã§åé
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21 | å¸ããå ´åã«ã¯ï¼åé
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22 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨
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23 | * è
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24 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®èä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨
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25 | * ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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26 | * (3) æ¬ã½ããã¦ã§ã¢ãï¼æ©å¨ã«çµã¿è¾¼ããªã©ï¼ä»ã®ã½ããã¦ã§ã¢éçºã«ä½¿
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27 | * ç¨ã§ããªãå½¢ã§åé
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28 | å¸ããå ´åã«ã¯ï¼æ¬¡ã®ããããã®æ¡ä»¶ãæºããã
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29 | * ã¨ï¼
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30 | * (a) åé
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31 | å¸ã«ä¼´ãããã¥ã¡ã³ãï¼å©ç¨è
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32 | ããã¥ã¢ã«ãªã©ï¼ã«ï¼ä¸è¨ã®è
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33 | * ä½æ¨©è¡¨ç¤ºï¼ãã®å©ç¨æ¡ä»¶ããã³ä¸è¨ã®ç¡ä¿è¨¼è¦å®ãæ²è¼ãããã¨ï¼
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34 | * (b) åé
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35 | å¸ã®å½¢æ
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36 | ãï¼å¥ã«å®ããæ¹æ³ã«ãã£ã¦ï¼TOPPERSããã¸ã§ã¯ãã«
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37 | * å ±åãããã¨ï¼
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38 | * (4) æ¬ã½ããã¦ã§ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ
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39 | * 害ãããï¼ä¸è¨èä½æ¨©è
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40 | ããã³TOPPERSããã¸ã§ã¯ããå
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41 | 責ãããã¨ï¼
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42 | * ã¾ãï¼æ¬ã½ããã¦ã§ã¢ã®ã¦ã¼ã¶ã¾ãã¯ã¨ã³ãã¦ã¼ã¶ããã®ãããªãç
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43 | * ç±ã«åºã¥ãè«æ±ãããï¼ä¸è¨èä½æ¨©è
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44 | ããã³TOPPERSããã¸ã§ã¯ãã
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45 | * å
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46 | 責ãããã¨ï¼
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47 | *
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48 | * æ¬ã½ããã¦ã§ã¢ã¯ï¼ç¡ä¿è¨¼ã§æä¾ããã¦ãããã®ã§ããï¼ä¸è¨èä½æ¨©è
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49 | ã
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50 | * ãã³TOPPERSããã¸ã§ã¯ãã¯ï¼æ¬ã½ããã¦ã§ã¢ã«é¢ãã¦ï¼ç¹å®ã®ä½¿ç¨ç®ç
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51 | * ã«å¯¾ããé©åæ§ãå«ãã¦ï¼ãããªãä¿è¨¼ãè¡ããªãï¼ã¾ãï¼æ¬ã½ããã¦ã§
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52 | * ã¢ã®å©ç¨ã«ããç´æ¥çã¾ãã¯éæ¥çã«çãããããªãæ害ã«é¢ãã¦ãï¼ã
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53 | * ã®è²¬ä»»ãè² ããªãï¼
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54 | *
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55 | * @(#) $Id: lm3sxxxx.h 301 2015-01-07 04:57:01Z ertl-ishikawa $
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56 | */
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57 |
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58 | /*
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59 | * TZ1000ã«é¢ããå®ç¾©
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60 | */
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61 |
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62 | #ifndef TOPPERS_TZ1000_H
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63 | #define TOPPERS_TZ1000_H
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64 |
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65 | /*
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66 | * å²è¾¼ã¿çªå·ã®æ大å¤
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67 | */
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68 | #define TMAX_INTNO (15 + 80)
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69 |
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70 | /*
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71 | * å²è¾¼ã¿åªå
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72 | 度ã®ãããå¹
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73 |
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74 | */
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75 | #define TBITW_IPRI 3
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76 |
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77 | /*
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78 | * å²è¾¼ã¿åªå
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79 | 度ãããå¹
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80 | ä¸ã®ãµãåªå
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81 | 度ã®ãããå¹
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82 |
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83 | */
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84 | #define TBITW_SUBIPRI 0
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85 |
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86 | #include <sil.h>
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87 |
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88 | #ifndef TOPPERS_MACRO_ONLY
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89 |
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90 | /*
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91 | * INTNO
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92 | */
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93 | #define INTNO_UART1 (16 + 41)
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94 | #define INTNO_TMR1 (16 + 61)
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95 |
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96 | /*
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97 | * TMR
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98 | */
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99 | #define TMR0_BASE 0x40042000
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100 | #define TMR1_BASE 0x40042020
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101 | #define TMRLOAD(tmr) ((void *)(tmr + 0x0000U))
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102 | #define TMRVALUE(tmr) ((void *)(tmr + 0x0004U))
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103 | #define TMRCONTROL(tmr) ((void *)(tmr + 0x0008U))
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104 | #define TMRINTCLR(tmr) ((void *)(tmr + 0x000CU))
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105 | #define TMRRIS(tmr) ((void *)(tmr + 0x0010U))
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106 | #define TMRMIS(tmr) ((void *)(tmr + 0x0014U))
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107 | #define TMRBGLOAD(tmr) ((void *)(tmr + 0x0018U))
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108 |
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109 | #define TMRCONTROL_ENABLE ((uint32_t)(1U << 7))
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110 | #define TMRCONTROL_PERIOD ((uint32_t)(1U << 6))
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111 | #define TMRCONTROL_INTENA ((uint32_t)(1U << 5))
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112 | #define TMRCONTROL_DIV_16 ((uint32_t)(1U << 2))
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113 | #define TMRCONTROL_DIV_256 ((uint32_t)(2U << 2))
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114 | #define TMRCONTROL_32BIT ((uint32_t)(1U << 1))
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115 | #define TMRCONTROL_ONESHOT ((uint32_t)(1U << 0))
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116 |
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117 | /*
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118 | * UART
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119 | */
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120 | #define UART1_BASE 0x40065000U
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121 | #define UARTDR(uart) ((void *)(uart + 0x0000U))
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122 | #define UARTRSR_ECR(uart) ((void *)(uart + 0x0004U))
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123 | #define UARTFR(uart) ((void *)(uart + 0x0018U))
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124 | #define UARTIBRD(uart) ((void *)(uart + 0x0024U))
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125 | #define UARTFBRD(uart) ((void *)(uart + 0x0028U))
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126 | #define UARTLCR_H(uart) ((void *)(uart + 0x002CU))
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127 | #define UARTCR(uart) ((void *)(uart + 0x0030U))
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128 | #define UARTIFLS(uart) ((void *)(uart + 0x0034U))
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129 | #define UARTIMSC(uart) ((void *)(uart + 0x0038U))
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130 | #define UARTRIS(uart) ((void *)(uart + 0x003CU))
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131 | #define UARTMIS(uart) ((void *)(uart + 0x0040U))
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132 | #define UARTICR(uart) ((void *)(uart + 0x0044U))
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133 | #define UARTDMACR(uart) ((void *)(uart + 0x0048U))
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134 |
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135 | #define UARTFR_TXFE ((uint32_t)(1U << 7))
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136 | #define UARTFR_RXFF ((uint32_t)(1U << 6))
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137 | #define UARTFR_TXFF ((uint32_t)(1U << 5))
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138 | #define UARTFR_RXFE ((uint32_t)(1U << 4))
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139 |
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140 | /*
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141 | * åä¿¡å²è¾¼ã¿ãçºçãããé¾å¤ã®åä¿¡FIFO Full byteæ°
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142 | */
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143 | #define UARTIFLS_RX_1 ((uint32_t)(0U << 3))
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144 | #define UARTIFLS_RX_2 ((uint32_t)(1U << 3))
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145 | #define UARTIFLS_RX_4 ((uint32_t)(2U << 3))
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146 | #define UARTIFLS_RX_6 ((uint32_t)(3U << 3))
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147 | #define UARTIFLS_RX_7 ((uint32_t)(4U << 3))
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148 |
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149 | /*
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150 | * éä¿¡å¯è½å²è¾¼ã¿ãçºçãããé¾å¤ã®éä¿¡FIFO Empty byteæ°
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151 | */
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152 | #define UARTIFLS_TX_14 ((uint32_t)(0U))
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153 | #define UARTIFLS_TX_12 ((uint32_t)(1U))
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154 | #define UARTIFLS_TX_8 ((uint32_t)(2U))
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155 | #define UARTIFLS_TX_4 ((uint32_t)(3U))
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156 | #define UARTIFLS_TX_2 ((uint32_t)(4U))
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157 |
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158 | #define UARTIMSC_TXIM ((uint32_t)(1U << 5))
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159 | #define UARTIMSC_RXIM ((uint32_t)(1U << 4))
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160 |
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161 | #define UARTICR_TXIC ((uint32_t)(1U << 5))
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162 | #define UARTICR_RXIC ((uint32_t)(1U << 4))
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163 |
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164 | /*
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165 | * æ±è製ãã©ã¤ãã使ç¨ããããã®I/F
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166 | */
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167 | #define _STDINT_H
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168 | #include "PMU_TZ10xx.h"
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169 | #include "GPIO_TZ10xx.h"
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170 | #include "TMR_TZ10xx.h"
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171 | #include "Driver_UART.h"
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172 | extern TZ10XX_DRIVER_PMU Driver_PMU;
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173 | extern TZ10XX_DRIVER_GPIO Driver_GPIO;
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174 | extern ARM_DRIVER_UART Driver_UART1;
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175 | extern TZ10XX_DRIVER_TMR Driver_TMR0;
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176 | extern TZ10XX_DRIVER_TMR Driver_TMR1;
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177 |
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178 | #endif /* TOPPERS_MACRO_ONLY */
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179 |
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180 | #endif /* TOPPERS_TZ1000_H */
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